ADSP-2171KST-104_技术文档

a

DSP Microcomputer

ADSP-2171/ADSP-2172/ADSP-2173

FUNCTIO NAL BLO CK D IAGRAM

FEATURES

30 ns Instruction Cycle Tim e (33 MIPS) from

16.67 MHz Crystal at 5.0 V

50 ns Instruction Cycle Tim e (20 MIPS) from 10 MHz

Crystal at 3.3 V

POWERDOWN

PROGRAM

MEMORY

CONTROL

ROM

LOGIC

8K x 24

DATA

ADDRESS

PROGRAM

SEQUENCER

PROGRAM

RAM

2K x 24

DATA

MEMORY

2K x 16

GENERATORS

FLAGS

DAG 1

DAG 2

ADSP-2100 Fam ily Code & Function Com patible w ith

New Instruction Set Enhancem ents for Bit Manipula-

tion Instructions, Multiplication Instructions, Biased

Rounding, and Global Interrupt Masking

Bus Grant Hang Logic

EXTERNAL

ADDRESS

BUS

PROGRAM MEMORY ADDRESS

DATA MEMORY ADDRESS

PROGRAM MEMORY DATA

2K Words of On-Chip Program Mem ory RAM

2K Words of On-Chip Data Mem ory RAM

8K Words of On-Chip Program Mem ory ROM

(ADSP-2172)

8- or 16-Bit Parallel Host Interface Port

300 m W Typical Pow er Dissipation at 5.0 V at 30 ns

70 m W Typical Pow er Dissipation at 3.3 V at 50 ns

Pow erdow n Mode Featuring Less than 0.55 m W (ADSP-

2171/ ADSP-2172) or 0.36 m W (ADSP-2173) CMOS

Standby Pow er Dissipation w ith 100 Cycle Recovery

from Pow erdow n

DATA MEMORY DATA

EXTERNAL

DATA

BUS

ARITHMETIC UNITS

MAC

TIMER

SERIAL PORTS

SPORT 0

HOST

INTERFACE

PORT

SHIFTER

ALU

SPORT 1

ADSP-2100 BASE

ARCHITECTURE

T he ADSP-217x combines the ADSP-2100 base architecture

(three computational units, data address generators, and a pro-

gram sequencer) with two serial ports, a host interface port, a

programmable timer, extensive interrupt capabilities, and on-

chip program and data memory.

Dual Purpose Program Mem ory for Both Instruction

and Data Storage

In addition, the ADSP-217x supports new instructions, which

include bit manipulations–bit set, bit clear, bit toggle, bit test–

new ALU constants, new multiplication instruction (x squared),

biased rounding, and global interrupt masking, for increased

flexibility. T he ADSP-217x also has a Bus Grant Hang Logic

(BGH) feature.

Independent ALU, Multiplier/ Accum ulator, and Barrel

Shifter Com putational Units

Tw o Independent Data Address Generators

Pow erful Program Sequencer Provides

Zero Overhead Looping

Conditional Instruction Execution

Tw o Double-Buffered Serial Ports w ith Com panding

Hardw are and Autom atic Data Buffering

Program m able 16-Bit Interval Tim er w ith Prescaler

Program m able Wait State Generation

Autom atic Booting of Internal Program Mem ory from

Byte-Wide External Mem ory, e.g., EPROM, or

Through Host Interface Port

Stand-Alone ROM Execution (Optional)

Single-Cycle Instruction Execution

Single-Cycle Context Sw itch

T he ADSP-217x provides 2K words (24-bit) of program RAM

and 2K words (16-bit) of data memory. T he ADSP-2172 pro-

vides an additional 8K words (24-bit) of program ROM. Power-

down circuitry is also provided to meet the low power needs of

battery operated portable equipment. T he ADSP-217x is avail-

able in 128-pin T QFP and 128-pin PQFP packages.

Fabricated in a high-speed, double metal, low power, CMOS

process, the ADSP-217X operates with a 30 ns instruction cycle

time. Every instruction can execute in a single processor cycle.

T he ADSP-217x’s flexible architecture and comprehensive in-

struction set allow the processor to perform multiple operations

in parallel. In one processor cycle the ADSP-217x can:

Multifunction Instructions

Three Edge- or Level-Sensitive External Interrupts

Low Pow er Dissipation in Standby Mode

128-Lead TQFP and 128-Lead PQFP

• generate the next program address

• fetch the next instruction

GENERAL D ESCRIP TIO N

• perform one or two data moves

• update one or two data address pointers

• perform a computational operation

T he ADSP-2171, ADSP-2172, and ADSP-2173 are single-chip

microcomputers optimized for digital signal processing (DSP)

and other high-speed numeric processing applications. T he

ADSP-2171 and ADSP-2172 are designed for 5.0 V applica-

tions. T he ADSP-2173 is designed for 3.3 V applications. T he

ADSP-2172 also has 8K words (24-bit) of program ROM.

T his takes place while the processor continues to:

• receive and transmit data through the two serial ports

• receive and/or transmit data through the host interface port

REV. A

• decrement timer

Inform ation furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assum ed by Analog Devices for its

use, nor for any infringem ents of patents or other rights of third parties

which m ay result from its use. No license is granted by im plication or

otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.

Tel: 617/ 329-4700

Fax: 617/ 326-8703

ADSP-2171/ADSP-2172/ADSP-2173

D evelopm ent System

Additional Infor m ation

T he ADSP-2100 Family Development Software, a complete set

of tools for software and hardware system development, supports

the ADSP-217x. T he System Builder provides a high-level

method for defining the architecture of systems under develop-

ment. T he Assembler has an algebraic syntax that is easy to

program and debug. T he Linker combines object files into

an executable file. T he Simulator provides an interactive

instruction-level simulation with a reconfigurable user interface

to display different portions of the hardware environment. A

PROM Splitter generates PROM programmer compatible files.

T he C Compiler, based on the Free Software Foundation’s

GNU C Compiler, generates ADSP-217x assembly source

code. T he Runtime Library includes over 100 ANSI-standard

mathematical and DSP-specific functions.

T his data sheet provides a general overview of ADSP-217x

functionality. For additional information on the architecture and

instruction set of the processor, refer to the ADSP-2100 Family

User’s Manual. For more information about the Development

System and ADSP-217x programmer’s reference information,

refer to the ADSP-2100 Family Assembler Tools & Simulator

Manual.

ARCH ITECTURE O VERVIEW

Figure 1 is an overall block diagram of the ADSP-217x. T he

processor contains three independent computational units: the

ALU, the multiplier/accumulator (MAC) and the shifter. T he

computational units process 16-bit data directly and have provi-

sions to support multiprecision computations. T he ALU per-

forms a standard set of arithmetic and logic operations; division

primitives are also supported. T he MAC performs single-cycle

multiply, multiply/add and multiply/subtract operations with

40 bits of accumulation. T he shifter performs logical and

arithmetic shifts, normalization, denormalization, and derive

exponent operations. T he shifter can be used to efficiently

implement numeric format control including multiword and

block floating-point representations.

EZ-T ools, low cost, easy-to-use hardware tools, also support the

ADSP-217x.

T he ADSP-217x EZ-ICE^®Emulator aids in the hardware de-

bugging of ADSP-217x systems. T he emulator consists of hard-

ware, host computer resident software, the emulator probe, and

the pin adaptor. T he emulator performs a full range of emula-

tion functions including stand-alone operation or operation in

the target, setting up to 20 breakpoints, single-step or full-speed

operation in the target, examining and altering registers and

memory values, and PC upload/download functions. If you plan

to use the emulator, you should consider the emulator’s restric-

tions (differences between emulator and processor operation).

T he EZ-LAB^®Evaluation Board is a PC plug-in card, but it can

operate in stand-alone mode. T he evaluation board/system de-

velopment board executes EPROM-based or downloaded pro-

grams. Modular Analog Front End daughter cards with different

codecs will be made available.

T he internal result (R) bus directly connects the computational

units so that the output of any unit may be the input of any unit

on the next cycle.

A powerful program sequencer and two dedicated data address

generators ensure efficient delivery of operands to these compu-

tational units. T he sequencer supports conditional jumps, sub-

routine calls and returns in a single cycle. With internal loop

counters and loop stacks, the ADSP-217x executes looped code

with zero overhead; no explicit jump instructions are required to

maintain the loop.

EZ-ICE and EZ-LAB are registered trademarks of Analog Devices, Inc.

2

POWER DOWN

CONTROL

INSTRUCTION

REGISTER

PROGRAM ROM

BOOT

ADDRESS

GENERATOR

DATA

SRAM

2K X 16

8K X 24

LOGIC

DATA

ADDRESS

GENERATOR

#2

DATA

ADDRESS

GENERATOR

#1

3

PROGRAM SRAM

2K X 24

FLAGS

PROGRAM

SEQUENCER

EXTERNAL

ADDRESS

BUS

14

PMA BUS

14

MUX

DMA BUS

PMD BUS

14

EXTERNAL

DATA

BUS

24

BUS

EXCHANGE

MUX

DMD BUS

16

11

COMPANDING

CIRCUITRY

HIP

CONTROL

LOGIC

TIMER

INPUT REGS

SHIFTER

INPUT REGS

ALU

INPUT REGS

MAC

TRANSMIT REG

HIP

DATA

BUS

16

RECEIVE REG

OUTPUT REGS

16

OUTPUT REGS

SERIAL

PORT 1

SERIAL

PORT 0

HIP

REGISTERS

R BUS

5

Figure 1. ADSP-217x Block Diagram

–2–

REV. A

ADSP-2171/ADSP-2172/ADSP-2173

T wo data address generators (DAGs) provide addresses for

simultaneous dual operand fetches (from data memory and pro-

gram memory). Each DAG maintains and updates four address

pointers. Whenever the pointer is used to access data (indirect

addressing), it is post-modified by the value of one of four pos-

sible modify registers. A length value may be associated with

each pointer to implement automatic modulo addressing for

circular buffers.

and loaded from the EPROM with no additional hardware. T he

on-chip program memory can also be initialized through the

HIP.

T he ADSP-217x features three general-purpose flag outputs

whose states can be simultaneously changed through software.

You can use these outputs to signal an event to an external

device. In addition, the data input and output pins on SPORT 1

can be alternatively configured as an input flag and an output

flag.

Efficient data transfer is achieved with the use of five internal

buses.

A programmable interval timer generates periodic interrupts. A

16-bit count register (T COUNT ) is decremented every n pro-

cessor cycles, where n-l is a scaling value stored in an 8-bit regis-

ter (T SCALE). When the value of the count register reaches

zero, an interrupt is generated and the count register is reloaded

from a 16-bit period register (T PERIOD).

• Program Memory Address (PMA) Bus

• Program Memory Data (PMD) Bus

• Data Memory Address (DMA) Bus

• Data Memory Data (DMD) Bus

• Result (R) Bus

T he ADSP-217x instruction set provides flexible data moves

and multifunction (one or two data moves with a computation)

instructions. Every instruction can be executed in a single pro-

cessor cycle. T he ADSP-217x assembly language uses an alge-

braic syntax for ease of coding and readability. A comprehensive

set of development tools supports program development.

T he two address buses (PMA and DMA) share a single external

address bus, allowing memory to be expanded off-chip, and the

two data buses (PMD and DMD) share a single external data

bus.

Program memory can store both instructions and data, permit-

ting the ADSP-217x to fetch two operands in a single cycle, one

from program memory and one from data memory. T he ADSP-

217x can fetch an operand from on-chip program memory and

the next instruction in the same cycle.

Ser ial P or ts

T he ADSP-217x incorporates two complete synchronous serial

ports (SPORT 0 and SPORT 1) for serial communications and

multiprocessor communication.

T he memory interface supports slow memories and memory-

mapped peripherals with programmable wait state generation.

External devices can gain control of external buses with bus

request/grant signals (BR and BG). One execution mode (Go

Mode) allows the ADSP-217x to continue running from inter-

nal memory. Normal execution mode requires the processor to

halt while buses are granted.

Here is a brief list of the capabilities of the ADSP-217x

SPORT s. Refer to the ADSP-2100 Family User’s Manual for

further details.

• SPORT s are bidirectional and have a separate, double-

buffered transmit and receive section.

• SPORT s can use an external serial clock or generate their own

serial clock internally.

In addition to the address and data bus for external memory

connection, the ADSP-217x has a configurable 8- or 16-bit

Host Interface Port (HIP) for easy connection to a host proces-

sor. T he HIP is made up of 16 data/address pins and 11 control

pins. T he HIP is extremely flexible and provides a simple inter-

face to a variety of host processors. For example, the Motorola

68000 series, the Intel 80C51 series and the Analog Devices’

ADSP-2101 can be easily connected to the HIP. T he host pro-

cessor can initialize the ASDP-217x’s on-chip memory through

the HIP.

• SPORT s have independent framing for the receive and trans-

mit sections. Sections run in a frameless mode or with frame

synchronization signals internally or externally generated.

Frame sync signals are active high or inverted, with either of

two pulse widths and timings.

• SPORT s support serial data word lengths from 3 to 16 bits

and provide optional A-law and µ-law companding according

to CCIT T recommendation G.711.

• SPORT receive and transmit sections can generate unique

interrupts on completing a data word transfer.

T he ADSP-217x can respond to eleven interrupts. T here can be

up to three external interrupts, configured as edge or level sensi-

tive, and eight internal interrupts generated by the T imer, the

Serial Ports (“SPORT s”), the HIP, the powerdown circuitry,

and software. T here is also a master RESET signal.

• SPORT s can receive and transmit an entire circular buffer of

data with only one overhead cycle per data word. An interrupt

is generated after a data buffer transfer.

• SPORT 0 has a multichannel interface to selectively receive

and transmit a 24 or 32 word, time-division multiplexed,

serial bitstream.

T he two serial ports provide a complete synchronous serial in-

terface with optional companding in hardware and a wide vari-

ety of framed or frameless data transmit and receive modes of

operation. Each port can generate an internal programmable

serial clock or accept an external serial clock.

• SPORT 1 can be configured to have two external interrupts

(IRQ0 and IRQ1) and the Flag In and Flag Out signals. T he

internally generated serial clock may still be used in this

configuration.

Boot circuitry provides for loading on-chip program memory

automatically from byte-wide external memory. After reset,

seven wait states are automatically generated. T his allows, for

example, a 30 ns ADSP-217x to use an external 200 ns

EPROM as boot memory. Multiple programs can be selected

REV. A

–3–

ADSP-2171/ADSP-2172/ADSP-2173

P in D escr iption

T he ADSP-217x is available in 128-lead T QFP and 128-lead

PQFP packages. T able I contains the pin descriptions.

SPORT 1

or

IRQ1 (T FS1) 1

5

I/O

Serial port 1 I/O pins

I

External interrupt request # 1

External interrupt request # 0

Programmable clock output

Flag Output pin

IRQ0 (RFS1) 1

I

Table I. AD SP -217x P in List

SCLK1

1

3

O

I

FO (DT 1)

FI (DR1)

FL2–0

P in

#

Flag Input pin

Group

Nam e

of

Input/

O

General purpose flag output

pins

P ins O utput Function

Address

Data

14

24

O

Address output for program,

data and boot memory spaces

V_DD

6

Power supply pins

Ground pins

GND

11

1

I/O

Data I/O pins for program

and data memories. Input

only for boot memory space,

with two MSBs used as boot

space addresses.

PWD

I

Powerdown pin

PWDACK

1

O

Powerdown acknowledge pin

H ost Inter face P or t

T he ADSP-217x host interface port is a parallel I/O port that al-

lows for an easy connection to a host processor. T hrough the

HIP, the ADSP-217x can be used as a memory-mapped periph-

eral to a host computer. T he HIP can be thought of as an area

of dual-ported memory, or mailbox registers, that allow commu-

nication between the computational core of the ADSP-217x and

the host computer.

RESET

IRQ2

BR

1

I

Processor reset input

I

External interrupt request # 2

External bus request input

External bus grant output

External bus grant hang output

External program memory select

External data memory select

Boot memory select

I

BG

O

I

BGH

PMS

DMS

BMS

RD

T he HIP is completely asynchronous. T he host processor can

write data into the HIP while the ADSP-217x is operating at full

speed.

External memory read enable

External memory write enable

Memory map select

T he HIP can be configured with the following pins:

WR

• HSIZE configures HIP for 8-bit or 16-bit communication with

the host processor.

MMAP

CLKIN,

XT AL

• BMODE (when MMAP = 0) determines whether the ADSP-

217x boots from the host processor (through the HIP) or ex-

ternal EPROM (through the data bus).

2

I

External clock or quartz crystal

input

CLKOUT

HSEL

1

O

I

Processor clock output

HIP select input

• HMD0 configures the bus strobes as separate read and write

strobes, or a single read/write select and a host data strobe.

HACK

HSIZE

O

HIP acknowledge output

• HMD1 selects separate address (3-bit) and data (16-bit)

buses, or a multiplexed, 16-bit address/data bus with address

latch enable.

8/16 bit host select input

0 = 16-bit; 1 = 8-bit

BMODE

HMD0

HMD1

1

I

Boot mode select input

0 = EPROM/data bus; 1 = HIP

T ying these pins to appropriate values configures the ADSP-

217x for straight-wire interface to a variety of industry-standard

microprocessors and microcomputers.

Bus strobe select input

0 = RD, WR; 1 = RW, DS

In 8-bit reads, the ADSP-217x three-states the upper eight bits

of the bus. When the host processor writes an 8-bit value to the

HIP, the upper eight bits are all zeros. For additional informa-

tion refer to the ADSP-2100 Family User’s Manual.

HIP address/data mode select

input 0 = separate; 1 =

multiplexed

HRD/HRW

HWR/HDS

1

I

HIP read strobe/read/write

select input

H IP O per ation

T he HIP contains six data registers (HDR5–0) and two status

registers (HSR7–6) with an associated HMASK register for

masking interrupts from individual HIP data registers. All HIP

data registers are memory-mapped into the internal data

memory of the ADSP-217x. HIP transfers can be managed us-

ing either interrupts or a polling scheme. T hese registers are

shown in the section “ADSP-217x Registers.”

HIP write strobe/host data

strobe select input

HD15–0/

HAD15-0

16

1

I/O

I

HIP data/data and address

HA2/ALE

Host address 2/Address latch

enable input

HA1–0/

Unused

T he HIP allows a software reset to be performed by the host

processor. T he internal software reset signal is asserted for five

ADSP-217x processor cycles.

2

5

I

Host addresses 1 and 0 inputs

SPORT 0

I/O

Serial port 0 I/O pins (T FS0,

RFS0, DT 0, DR0, SCLK0)

–4–

REV. A

ADSP-2171/ADSP-2172/ADSP-2173

Inter r upts

Table II. Interrupt P riority & Interrupt Vector Addresses

T he interrupt controller allows the processor to respond to the

eleven possible interrupts and reset with minimum overhead.

T he ADSP-217x provides up to three external interrupt input

pins, IRQ0, IRQ1 and IRQ2. IRQ2 is always available as a dedi-

cated pin; SPORT 1 may be reconfigured for IRQ0, IRQ1, and

the flags. T he ADSP-217x also supports internal interrupts from

the timer, the host interface port, the two serial ports, software,

and the powerdown control circuit. T he interrupt levels are in-

ternally prioritized and individually maskable (except power-

down and reset). T he input pins can be programmed to be

either level- or edge-sensitive. T he priorities and vector ad-

dresses of all interrupts are shown in T able II, and the interrupt

registers are shown in Figure 2.

Interrupt Vector

Address (H ex)

Source of Interrupt

Reset (or Power-Up with PUCR = 1) 0000 (Highest Priority)

Powerdown (Nonmaskable)

IRQ2

HIP Write

002C

0004

0008

000C

0010

0014

0018

001C

HIP Read

SPORT 0 T ransmit

SPORT 0 Receive

Software Interrupt 1

Software Interrupt 0

SPORT 1 T ransmit or IRQ1

SPORT 1 Receive or IRQ0

T imer

0020

0024

Interrupts can be masked or unmasked with the IMASK regis-

ter. Individual interrupt requests are logically ANDed with the

bits in IMASK; the highest priority unmasked interrupt is then

selected.T he powerdown interrupt is nonmaskable.

0028 (Lowest Priority)

On-chip stacks preserve the processor status and are automati-

cally maintained during interrupt handling.

T he ADSP-217x masks all interrupts for one instruction cycle

following the execution of an instruction that modifies the

IMASK register. T his does not affect autobuffering.

T he stacks are twelve levels deep to allow interrupt nesting.

T he following instructions allow global enable or disable servic-

ing of the interrupts (including powerdown), regardless of the

state of IMASK. Disabling the interrupts does not affect

autobuffering.

T he interrupt control register, ICNT L, allows the external in-

terrupts to be either edge- or level-sensitive. Interrupt routines

can either be nested with higher priority interrupts taking prece-

dence or processed sequentially.

ENA INT S;

DIS INT S;

T he IFC register is a write-only register used to force and clear

interrupts generated from software.

When you reset the processor, the interrupt servicing is enabled.

IMASK

ICNTL

15 14 13 12 11 10

9

0

8

7

6

5

0

4

0

3

0

2

0

1

0

4

3

0

2

1

0

1 = enable, 0 = disable

IRQ2

HIP Write

HIP Read

Timer

IRQ0 Sensitivity

IRQ1 Sensitivity

IRQ2 Sensitivity

1 = edge

0 = level

IRQ0 or SPORT1 Receive

IRQ1 or SPORT1 Transmit

Software 0

SPORT0 Transmit

SPORT0 Receive

Software 1

Interrupt Nesting

1 = enable, 0 = disable

IFC

15 14 13 12 11 10

9

0

8

0

7

6

0

5

0

4

0

3

0

2

0

1

0

INTERRUPT FORCE

INTERRUPT CLEAR

IRQ2

SPORT0 Transmit

SPORT0 Receive

Software 1

Timer

SPORT1 Receive or IRQ0

SPORT1 Transmit or IRQ1

Software 0

Software 1

SPORT1 Transmit or IRQ1

SPORT1 Receive or IRQ0

Timer

SPORT0 Receive

SPORT0 Transmit

IRQ2

Figure 2. Interrupt Registers

REV. A

–5–

ADSP-2171/ADSP-2172/ADSP-2173

LO W P O WER O P ERATIO N

programmable fraction of the normal clock rate, is specified by a

selectable divisor given in the IDLE instruction. T he format of

the instruction is

T he ADSP-217x has three low power modes that significantly

reduce the power dissipation when the device operates under

standby conditions. T hese modes are:

IDLE (n);

• Powerdown

• Idle

where n = 16, 32, 64, or 128. T his instruction keeps the proces-

sor fully functional, but operating at the slower clock rate. While

it is in this state, the processor’s other internal clock signals,

such as SCLK, CLKOUT , and timer clock, are reduced by the

same ratio. T he default form of the instruction, when no clock

divisor is given, is the standard IDLE instruction.

• Slow Idle

T he CLKOUT pin may also be disabled to reduce external

power dissipation. T he CLKOUT pin is controlled by Bit 14 of

SPORT 0 Autobuffer Control Register, DM[0x3FF3].

When the IDLE (n) instruction is used, it effectively slows down

the processor’s internal clock and thus its response time to in-

coming interrupts––the 1-cycle response time of the standard

idle state is increased by n, the clock divisor. When an enabled

interrupt is received, the ADSP-217x will remain in the idle

state for up to a maximum of n processor cycles (n = 16, 32, 64,

or 128) before resuming normal operation.

P ower down

T he ADSP-217x processor has a low power feature that lets the

processor enter a very low power dormant state through hard-

ware or software control. Here is a brief list of powerdown fea-

tures. Refer to the ADSP-2100 Family User’s Manual, Chapter 9

“System Interface” for detailed information about the

powerdown feature.

• Powerdown mode holds the processor in CMOS standby with

a maximum current of less than 100 µA in some modes.

When the IDLE (n) instruction is used in systems that have an

externally generated serial clock (SCLK), the serial clock rate

may be faster than the processor’s reduced internal clock rate.

Under these conditions, interrupts must not be generated at a

faster rate than can be serviced, due to the additional time the

processor takes to come out of the idle state (a maximum of n

processor cycles).

• Quick recovery from powerdown. T he processor begins ex-

ecuting instructions in as few as 100 CLKIN cycles.

• Support for an externally generated T T L or CMOS processor

clock. T he external clock can continue running during

powerdown without affecting the lowest power rating and 100

CLKIN cycle recovery.

SYSTEM INTERFACE

• Support for crystal operation includes disabling the oscillator

to save power (the processor automatically waits 4096 CLKIN

cycles for the crystal oscillator to start and stabilize), and let-

ting the oscillator run to allow 100 CLKIN cycle startup.

Figure 3 shows a basic system configuration with the ADSP-

217x, two serial devices, a host processor, a boot EPROM, and

optional external program and data memories. Up to 14K words

of data memory and 16K words of program memory can be sup-

ported. Programmable wait state generation allows the processor

to interface easily to slow memories. T he ADSP-217x also pro-

vides one external interrupt and two serial ports or three exter-

nal interrupts and one serial port.

• Powerdown is initiated by either the powerdown pin (PWD)

or the software powerdown force bit.

• Interrupt support allows an unlimited number of instructions

to be executed before optionally powering down. T he

powerdown interrupt also can be used as a non-maskable,

edge sensitive interrupt.

Clock Signals

T he ADSP-217x can be clocked by either a crystal or by a T T L-

compatible clock signal.

• Context clear/save control allows the processor to continue

where it left off or start with a clean context when leaving the

powerdown state.

T he CLKIN input cannot be halted, changed during operation,

or operated below the specified frequency during normal opera-

tion. T he only exception is while the processor is in the Power-

down State. For additional information, refer to Chapter 9,

ADSP-2100 Family User’s Manual for detailed information on

this powerdown feature.

• T he RESET pin also can be used to terminate powerdown,

and the host software reset feature can be used to terminate

powerdown under certain conditions.

• Powerdown acknowledge pin indicates when the processor has

entered powerdown.

If an external clock is used, it should be a T T L-compatible sig-

nal running at half the instruction rate. T he signal is connected

to the processor’s CLKIN input. When an external clock is

used, the XT AL input must be left unconnected.

Idle

When the ADSP-217x is in the Idle Mode, the processor waits

indefinitely in a low power state until an interrupt occurs. When

an unmasked interrupt occurs, it is serviced; execution then

continues with the instruction following the IDLE instruction.

T he ADSP-217x uses an input clock with a frequency equal to

half the instruction rate; a 16.67 MHz input clock yields a 30 ns

processor cycle (which is equivalent to 33 MHz). Normally, in-

structions are executed in a single processor cycle. All device

timing is relative to the internal instruction clock rate, which is

indicated by the CLKOUT signal when enabled.

Slow Idle

T he IDLE instruction is enhanced on the ADSP-217x to let the

processor’s internal clock signal be slowed during IDLE, further

reducing power consumption. T he reduced clock frequency, a

–6–

REV. A

ADSP-2171/ADSP-2172/ADSP-2173

HIP CONTROL

HOST

PROCESSOR

(OPTIONAL)

CLOCK OR

CRYSTAL

HIP DATA/ADDR

16

6

9

4

7

SCLK

RFS

TFS

DT

CLKIN

XTAL

PWD

PWDACK

V

GND

HOST

MODE

HIP

DD

CLKOUT

RESET

IRQ2

SERIAL DEVICE

(OPTIONAL)

SERIAL

PORT 0

DR

ADSP-217x

BR

SCLK

BG

RFS or IRQ0

TFS or IRQ1

DT or FO

DR or FI

SERIAL DEVICE

(OPTIONAL)

SERIAL

PORT 1

MMAP

3

FL2-0

DATA

PMS

RD

WR

ADDRESS

14

DMS

BMS

24

D

23-22

D

8

23-8

24

15-8

14

2

16

CS

A

D

A

CS

A

D

BOOT MEMORY

e.g., EPROM

DATA MEMORY

&

PERIPHERALS

OE

PROGRAM

MEMORY

OE

27C64

27C128

27C256

27C512

WE

(OPTIONAL)

NOTE:

THE TWO MSBs OF THE DATA BUS ARE USED AS THE MSBs OF THE BOOT EPROM ADDRESS.

THIS IS ONLY REQUIRED FOR THE 27C256 AND 27C512.

Figure 3. ADSP-217x Basic System Configuration

to stabilize. If RESET is activated any time after power-up, the

clock continues to run and does not require stabilization time.

Because the ADSP-217x includes an on-chip oscillator circuit,

an external crystal may be used. T he crystal should be con-

nected across the CLKIN and XT AL pins, with two capacitors

connected as shown in Figure 4. A parallel-resonant, fundamen-

tal frequency, microprocessor-grade crystal should be used.

T he power-up sequence is defined as the total time required for

the crystal oscillator circuit to stabilize after a valid V_DDis ap-

plied to the processor, and for the internal phase-locked loop

(PLL) to lock onto the specific crystal frequency. A minimum of

2000 CLKIN cycles ensures that the PLL has locked but does

not include the crystal oscillator start-up time. During this

power-up sequence the RESET signal should be held low. On

any subsequent resets, the RESET signal must meet the mini-

XTAL

ADSP-217x

CLKIN

CLKOUT

mum pulse width specification, t_RSP

.

T he RESET input contains some hysteresis; however, if you use

an RC circuit to generate your RESET signal, the use of an ex-

ternal Schmidt trigger is recommended.

Figure 4. External Crystal Connections

A clock output (CLKOUT ) signal is generated by the processor

at the processor’s cycle rate. T his can be enabled and disabled

by the CLKODIS bit in the SPORT 0 Autobuffer Control Reg-

ister, DM[0x3FF3].

T he master reset sets all internal stack pointers to the empty

stack condition, masks all interrupts and clears the MST AT reg-

ister. When RESET is released, if there is no pending bus re-

quest and the chip is configured for booting (MMAP = 0), the

boot-loading sequence is performed. T hen the first instruction is

fetched from internal program memory location 0x0000.

Reset

T he RESET signal initiates a master reset of the ADSP-217x.

T he RESET signal must be asserted during the power-up se-

quence to assure proper initialization. RESET during initial

power-up must be held long enough to allow the internal clock

REV. A

–7–

ADSP-2171/ADSP-2172/ADSP-2173

P r ogr am Mem or y Inter face

T he optional ROM always resides at locations PM[0x0800]

through PM[0x27FF] regardless of the state of the MMAP pin.

T he ROM is enabled by setting the ROMENABLE bit in the

Data Memory Wait State control register, DM[0x3FFE]. When

the ROMENABLE bit is set to 1, addressing program memory

in this range will access the on-chip ROM. When set to zero,

addressing program memory in this range will access external

program memory. T he ROMENABLE bit is set to 0 on chip re-

set unless MMAP and BMODE = 1.

T he on-chip program memory address bus (PMA) and the on-

chip program memory data bus (PMD) are multiplexed with

on-chip DMA and DMD buses, creating a single external data

bus and a single external address bus. T he 14-bit address bus

directly addresses up to 16K words. 10K words of memory for

ADSP-217x with optional 8K ROM and 2K words of memory

for the non-ROM version are on-chip. T he data bus is bidirec-

tional and 24 bits wide to external program memory. Program

memory may contain code and data.

T he program memory interface can generate 0 to 7 wait states

for external memory devices; default is to 7 wait states after

RESET.

T he program memory data lines are bidirectional. T he program

memory select (PMS) signal indicates access to the program

memory and can be used as a chip select signal. T he write (WR)

signal indicates a write operation and is used as a write strobe.

Boot Mem or y Inter face

T he ADSP-217x can load on-chip memory from external boot

memory space. T he boot memory space consists of 64K by 8-bit

space, divided into eight separate 8K by 8-bit pages. T hree bits

in the system control register select which page is loaded by the

boot memory interface. Another bit in the system control regis-

ter allows the user to force a boot loading sequence under soft-

ware control. Boot loading from page 0 after RESET is initiated

automatically if MMAP = 0.

T he read (RD) signal indicates a read operation and is used as a

read strobe or output enable signal.

T he ADSP-217x writes data from its 16-bit registers to the 24-

bit program memory using the PX register to provide the lower

eight bits. When it reads data (not instructions) from 24-bit pro-

gram memory to a 16-bit data register, the lower eight bits are

placed in the PX register.

T he boot memory interface can generate 0 to 7 wait states; it

defaults to 7 wait states after RESET. T his allows the ADSP-

217x to boot from a single low cost EPROM such as a 27C256.

Program memory is booted one byte at a time and converted to

24-bit program memory words.

P r ogr am Mem or y Maps

AD SP -217x

Program memory can be mapped in two ways, depending on the

state of the MMAP pin. Figure 5 shows the different configura-

tions. When MMAP = 0, internal RAM occupies 2K words be-

ginning at address 0x0000. In this configuration, the boot

loading sequence (described in “Boot Memory Interface”) is au-

tomatically initiated when RESET is released.

T he BMS and RD signals are used to select and to strobe the

boot memory interface. Only 8-bit data is read over the data

bus, on pins D8–D15. T o accommodate addressing up to eight

pages of boot memory, the two MSBs of the data bus are used

in the boot memory interface as the two MSBs of the boot space

address.

0000

2K

INTERNAL RAM

NOT BOOTED

INTERNAL RAM

BOOTED

EXTERNAL

07FF

0800

07FF

0800

07FF

0800

T he ADSP-2100 Family Assembler and Linker support the cre-

ation of programs and data structures requiring multiple boot

pages during execution.

8K

INTERNAL ROM

(ROMENABLE = 1)

INTERNAL ROM

(ROMENABLE = 1)

8K

RD and WR must always be qualified by PMS, DMS, or BMS

to ensure the correct program, data, or boot memory accessing.

INTERNAL ROM

(ROMENABLE

DEFAULTS

OR

TO 1

DURING RESET)

H IP Booting

8K

T he ADSP-217x can also boot programs through its Host Inter-

face Port. If BMODE = 1 and MMAP = 0, the ADSP-217x

boots from the HIP. If BMODE = 0, the ADSP-217x boots

through the data bus (in the same way as the ADSP-2101), as

described above in “Boot Memory Interface.” For additional in-

formation about HIP booting, refer to the ADSP-2100 Family

User’s Manual, Chapter 7, “Host Interface Port.”

EXTERNAL

(ROMENABLE = 0)

EXTERNAL

(ROMENABLE = 0)

27FF

2800

27FF

2800

27FF

2800

4K

EXTERNAL

6K

37FF

3800

EXTERNAL

2K

INTERNAL RAM

3FFF

T he ADSP-2100 Family Development Software includes a util-

ity program called the HIP Splitter. T his utility allows the cre-

ation of programs that can be booted via the ADSP-217x’s HIP,

in a similar fashion as EPROM-bootable programs generated by

the PROM Splitter utility.

MMAP = 1

BMODE = 1

MMAP = 0

BMODE = 0 or 1

MMAP = 1

BMODE = 0

Figure 5. ADSP-217x Mem ory Maps

When MMAP = 1, words of external program memory begin at

address 0x0000 and internal RAM is located in the upper 2K

words, beginning at address 0x3800. In this configuration, pro-

gram memory is not loaded although it can be written to and

read from under program control.

–8–

REV. A

ADSP-2171/ADSP-2172/ADSP-2173

Stand-Alone RO M Execution

Upon completion of the prototype manufacture, Analog Devices

will ship prototype units and a delivery schedule update for pro-

duction units. An invoice against your purchase order for the

NRE charges is issued at this time.

When the MMAP and BMODE pins both are set to 1, the

ROM is automatically enabled and execution commences from

program memory location 0x0800 at the start of ROM. T his

feature lets an embedded design operate without external

memory components. T o operate in this mode, the ROM coded

program must copy an interrupt vector table to the appropriate

locations in program memory RAM. In this mode, the ROM

enable bit defaults to 1 during reset.

T here is a charge for each ROM mask generated and a mini-

mum order quantity. Consult your sales representative for

details. A separate order must be placed for parts of a specific

package type, temperature range, and speed grade.

D ata Mem or y Inter face

T he data memory address (DMA) bus is 14 bits wide. T he bidi-

rectional external data bus is 24 bits wide, with the upper 16

bits (D8–D23) used for data memory data (DMD) transfers.

Table III. Boot Sum m ary Table

BMO D E = 0

BMO D E = 1

T he data memory select (DMS) signal indicates access to the

data memory and can be used as a chip select signal. T he write

(WR) signal indicates a write operation and can be used as a

write strobe. T he read (RD) signal indicates a read operation

and can be used as a read strobe or output enable signal.

MMAP = 0 Boot from EPROM,

then execution starts

at internal RAM

Boot from HIP, then

execution starts at

internal RAM location

0x0000

location 0x0000

MMAP = 1 No booting, execution

Stand-Alone Mode,

T he ADSP-217x supports memory-mapped I/O, with the pe-

ripherals memory mapped into the data or program memory ad-

dress spaces and accessed by the processor in the same manner.

starts at external memory execution starts at

location 0x0000

internal ROM location

0x0800

D ata Mem or y Map

T he on-chip data memory RAM resides in the 2K words of data

memory beginning at address 0x3000, as shown in Figure 6. In

addition, data memory locations from 0x3800 to the end of data

memory at 0x3FFF are reserved. Control registers for the sys-

tem, timer, wait state configuration, host interface port, and se-

rial port operations are located in this region of memory.

O r der ing P r ocedur e for AD SP -2172 P r ocessor s

T o place an order for a custom ROM-coded ADSP-2172 pro-

cessor, you must:

1. Complete the following forms contained in the ADSP ROM

Ordering Package, available from your Analog Devices sales

representative:

0000

ADSP-2172 ROM Specification Form

DWAIT 0

(1K EXTERNAL)

ROM Release Agreement

ROM NRE Agreement & Minimum Quantity Order (MQO)

Acceptance Agreement for Pre-production ROM Products.

03FF

0400

DWAIT 1

(1K EXTERNAL)

12K

EXTERNAL

07FF

0800

2. Return the forms to Analog Devices along with two copies of

the Memory Image File (.EXE file) of your ROM code. T he

files must be supplied on two 3.5" or 5.25" floppy disks for

IBM PC (DOS 2.01 or higher).

DWAIT 2

(10K EXTERNAL)

2FFF

3000

2FFF

3000

3. Place a purchase order with Analog Devices for nonrecurring

engineering charges (NRE) associated with ROM product

development.

2K

INTERNAL

DATA RAM

37FF

3800

After this information is received, it is entered into Analog

Devices’ ROM Manager System which assigns a custom ROM

model number to the product. T his model number will be

branded on all prototype and production units manufactured to

these specifications.

NO WAIT

STATES

1K

RESERVED

3BFF

3C00

MEMORY MAPPED

REGISTERS/

RESERVED

T o minimize the risk of code being altered during this process,

Analog Devices verifies that the .EXE files on both floppy disks are

identical, and recalculates the checksums for the .EXE file en-

tered into the ROM Manager System. The checksum data, in the

form of a ROM memory map, a hard copy of the .EXE file, and a

ROM Data Verification Form are returned to you for inspection.

3FFF

DATA MEMORY

WAIT STATES

Figure 6. ADSP-217x Data Mem ory Map

T he remaining 12K of data memory is external. External data

memory is divided into three zones, each associated with its own

wait state generator. By mapping peripherals into different

zones, you can accommodate peripherals with different wait

state requirements. All zones default to 7 wait states after

RESET. For compatibility with other ADSP-2100 Family pro-

cessors, bit definitions for DWAIT 3 and DWAIT 4 are shown

in the Data Memory Wait State Control Register, but they are

not used by the ADSP-217x.

A signed ROM Verification Form and a purchase order for pro-

duction units are required prior to any product being manufac-

tured. Prototype units may be applied toward the minimum

order quantity.

REV. A

–9–

ADSP-2171/ADSP-2172/ADSP-2173

Bus Request & Bus Gr ant

but cannot execute it because the bus is granted to some other

processor. With the BGH signal, the other processor(s) in the

system can be alerted that the ADSP-217x is hung and release

the bus by deasserting bus request. Once the bus is released the

ADSP-217x executes the external access and deasserts BGH.

T his is a signal to the other processors that external memory is

now available.

T he ADSP-217x can relinquish control of the data and address

buses to an external device. When the external device requires

access to memory, it asserts the bus request (BR) signal. If the

ADSP-217x is not performing an external memory access, then

it responds to the active BR input in the following processor

cycle by:

• three-stating the data and address buses and the PMS, DMS,

BMS, RD, WR output drivers,

AD SP -217X REGISTERS

Figure 7 summarizes all the registers in the ADSP-217x. Some

registers store values. For example, AX0 stores an ALU oper-

and; I4 stores a DAG2 pointer. Other registers consist of control

bits and fields, or status flags. For example, AST AT contains

status flags from arithmetic operations, and fields in DWAIT

control the numbers of wait states for different zones of data

memory.

• asserting the bus grant (BG) signal, and

• halting program execution.

If the Go Mode is enabled, the ADSP-217x will not halt pro-

gram execution until it encounters an instruction that requires

an external memory access.

If the ADSP-217x is performing an external memory access

when the external device asserts the BR signal, then it will not

three-state the memory interfaces or assert the BG signal until

the processor cycle after the access completes, which can be up

to eight cycles later depending on the number of wait states.

T he instruction does not need to be completed when the bus is

granted. If a single instruction requires two external memory ac-

cesses, the bus will be granted between the two accesses.

A secondary set of registers in all computational units allows a

single-cycle context switch.

T he bit and field definitions for control and status registers are

given in the rest of this section, except for IMASK, ICNT L and

IFC, which are defined earlier in this data sheet. T he system

control register, DWAIT register, timer registers, HIP control

registers, HIP data registers, and SPORT control registers are

all mapped into data memory; that is, registers are accessed by

reading and writing data memory locations rather than register

names. T he particular data memory address is shown with each

memory-mapped register.

When the BR signal is released, the processor releases the BG

signal, reenables the output drivers and continues program ex-

ecution from the point where it stopped.

T he bus request feature operates at all times, including when

the processor is booting and when RESET is active.

Register bit values shown on the following pages are the default

bit values after reset. If no values are shown, the bits are indeter-

minate at reset. Reserved bits are shown in gray; these bits

should always be written with zeros.

T he new Bus Grant Hang logic and associated BGH pin allow

the ADSP-217x to operate in a multiprocessor environment

with a minimal number of “wasted” processor cycles. T he bus

grant hang pin is asserted when the ADSP-217x desires a cycle,

PROGRAM SEQUENCER

ICNTL

IFC

PROGRAM

ROM

8K X 24

HOST

INTERFACE

PORT

SSTAT

LOOP

IMASK

STACK

MSTAT

ASTAT

DATA

SRAM

2K X 16

DAG 1

DAG 2

CNTR

OWRCNTR

4 X 18

I0 M0 L0

I1 M1 L1

I2 M2 L2

I3 M3 L3

I4 M4 L4

I5 M5 L5

I6 M6 L6

I7 M7 L7

0x3FE0-0x3FE5

DATA

PROGRAM

SRAM

2K X 24

COUNT

STACK

4 X 14

PC

STACK

16 X 14

STATUS

STACK

12 X 25

0x3FE6-0x3FE7

0x3FE8

STATUS

HMASK

0x3FFF

0x3FFE

SYSTEM CONTROL

DM WAIT CONTROL

PMA BUS

14

DMA BUS

PMD BUS

24

16

PX

DMD BUS

FLAGS

TIMER

TX0

RX1 TX1

RX0

AX1 AY0 AY1

AX0

MX0 MX1 MY0 MY1

SI SE SB

0x3FFD

0x3FFC

0x3FFB

TPERIOD

TCOUNT

TSCALE

0x3FFA-0x3FF3

0x3FF2-0x3FEF

CONTROL REGISTERS

SPORT 1

POWERDOWN

CONTROL

LOGIC

ALU

MAC

SHIFTER

SR0 SR1

CONTROL REGISTERS

SPORT 0

AR AF

MR0 MR1 MR2 MF

Figure 7. ADSP-217x Registers Control Register

–10–

REV. A

ADSP-2171/ADSP-2172/ADSP-2173

SSTAT (Read-Only)

ASTAT

7

0

6

0

5

0

4

0

3

0

2

0

1

0

7

0

6

1

5

0

4

1

3

0

2

1

0

1

PC Stack Empty

AZ ALU Result Zero

AN ALU Result Negative

AV ALU Overflow

AC ALU Carry

PC Stack Overflow

Count Stack Empty

Count Stack Overflow

Status Stack Empty

Status Stack Overflow

Loop Stack Empty

Loop Stack Overflow

AS ALU X Input Sign

AQ ALU Quotient

MV MAC Overflow

SS Shifter Input Sign

MSTAT

6

0

5

0

4

3

2

1

0

Data Register Bank Select

0 = primary, 1 = secondary

Bit Reverse Mode Enable (DAG1)

ALU Overflow Latch Mode Enable

AR Saturation Mode Enable

MAC Result Placement

0 = fractional, 1 = integer

Timer Enable

Go Mode Enable

System Control Register

0x3FFF

15 14 13 12 11 10

9

0

8

0

7

0

6

0

5

1

4

1

3

1

2

1

0

1

0

1

SPORT0 Enable

1 = enabled, 0 = disabled

PWAIT

Program Memory

Wait States

SPORT1 Enable

1 = enabled, 0 = disabled

BWAIT

Boot Wait States

BPAGE

Boot Page Select

SPORT1 Configure

1 = serial port

0 = FI, FO, IRQ0, IRQ1, SCLK

BFORCE

Boot Force Bit

Timer Registers

15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

0x3FFD

0x3FFC

0x3FFB

TPERIOD Period Register

TCOUNT Counter Register

TSCALE Scaling Register

0

Control Registers

–11–

REV. A

ADSP-2171/ADSP-2172/ADSP-2173

ROM Enable/Data Memory Wait State

Control Register

0x3FFE

15 14 13 12 11 10

9

1

8

1

7

1

6

1

5

1

4

1

3

1

2

1

0

1

0

1

DWAIT4

DWAIT3

DWAIT2

DWAIT1

DWAIT0

ROM enable

1 = enable

0 = disable

SPORT0 Multichannel Receive Word Enable Registers

SPORT0 Multichannel Transmit Word Enable Registers

1 = Channel Enabled

0 = Channel Ignored

1 = Channel Enabled

0 = Channel Ignored

0x3FFA

0x3FF8

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

0x3FF9

0x3FF7

15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

SPORT0 Control Register

0x3FF6

15 14 13 12 11 10

9

0

8

0

7

0

6

0

5

0

4

0

3

0

2

0

1

0

Multichannel Enable MCE

Internal Serial Clock Generation ISCLK

Receive Frame Sync Required RFSR

Receive Frame Sync Width RFSW

SLEN Serial Word Length

DTYPE Data Format

00 = right justify, zero-fill unused MSBs

01 = right justify, sign extend into unused MSBs

10 = compand using µ-law

11 = compand using A-law

Multichannel Frame Delay MFD

Only If Multichannel Mode Enabled

INVRFS Invert Receive Frame Sync

INVTFS Invert Transmit Frame Sync

(or INVTDV Invert Transmit Data Valid

Only If Multichannel Mode Enabled)

Transmit Frame Sync Required TFSR

Transmit Frame Sync Width TFSW

IRFS Internal Receive Frame Sync Enable

ITFS Internal Transmit Frame Sync Enable

(or MCL Multichannel Length; 1 = 32 words, 0 = 24 words

Only If Multichannel Mode Enabled)

Control Registers

–12–

REV. A

ADSP-2171/ADSP-2172/ADSP-2173

SPORT0 SCLKDIV

Serial Clock Divide Modulus

0x3FF5

15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

SPORT0 RFSDIV

Receive Frame Sync Divide Modulus

0x3FF4

15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

SPORT0 Autobuffer Control Register

0x3FF3

15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

RBUF

CLKODIS

Receive Autobuffering Enable

CLKOUT Disable Control Bit

TBUF

BIASRND

Transmit Autobuffering Enable

MAC Biased Rounding Control Bit

RMREG

TIREG

Receive Autobuffer M Register

Transmit Autobuffer I Register

RIREG

TMREG

Receive Autobuffer I Register

Transmit Autobuffer M Register

SPORT1 Control Register

0x3FF2

15 14 13 12 11 10

9

0

8

0

7

0

6

0

5

0

4

0

3

0

2

0

1

0

Flag Out (Read Only)

Internal Serial Clock Generation ISCLK

Receive Frame Sync Required RFSR

Receive Frame Sync Width RFSW

Transmit Frame Sync Required TFSR

Transmit Frame Sync Width TFSW

SLEN Serial Word Length

DTYPE Data Format

00 = right justify, zero-fill unused MSBs

01 = right justify, sign extend into unused MSBs

10 = compand using µ-law

11 = compand using A-law

INVRFS Invert Receive Frame Sync

INVTFS Invert Transmit Frame Sync

IRFS Internal Receive Frame Sync Enable

ITFS Internal Transmit Frame Sync Enable

Control Registers

REV. A

–13–

ADSP-2171/ADSP-2172/ADSP-2173

SPORT1 SCLKDIV

SPORT1 RFSDIV

Serial Clock Divide Modulus

Receive Frame Sync Divide Modulus

0x3FF1

0x3FF0

15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

SPORT1 Autobuffer Control Register

0x3FEF

15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

RBUF

XTALDIS

XTAL Pin Drive Disable

Receive Autobuffer Enable

during Powerdown

1 = disabled, 0 = enabled

(disable XTAL pin when no external

crystal connected)

TBUF

Transmit Autobuffer Enable

RMREG

XTALDELAY

4096 Cycle Delay Enable

1 = delay, 0 = no delay

Receive M Register

RIREG

Receive I Register

PDFORCE

TMREG

Powerdown Force

Transmit M Register

PUCR

Powerup Context Reset Enable

1 = soft reset (context clear),

0 = resume execution

TIREG

Transmit I Register

HMASK Register

0x3FE8

HIP Data Registers

0x3FE5

HDR5

15 14 13 12 11 10

9

8

7

6

5

4

3

0

2

0

1

0

15 14 13 12 11 10 9

8 7 6 5 4 3 2 1 0

0

0x3FE4

HDR4

HDR3

HDR2

HDR1

HDR0

Host HDR5

Read

Host HDR0

Write

Host HDR4

Read

Host HDR1

Write

0x3FE3

0x3FE2

0x3FE1

Host HDR3

Read

Host HDR2

Write

Host HDR2

Read

Host HDR3

Write

Host HDR1

Read

Host HDR4

Write

Host HDR0

Read

Host HDR5

Write

0x3FE0

Interrupt Enables

1 = Enable

0 = Disable

Control Registers

–14–

REV. A

ADSP-2171/ADSP-2172/ADSP-2173

HSR6

0x3FE6

15 14 13 12 11 10

9

0

8

7

6

0

5

0

4

0

3

0

2

0

1

0

2171 HDR5 Write

2171 HDR4 Write

2171 HDR3 Write

2171 HDR2 Write

2171 HDR1 Write

2171 HDR0 Write

Host HDR0 Write

Host HDR1 Write

Host HDR2 Write

Host HDR3 Write

Host HDR4 Write

Host HDR5 Write

HSR7

0x3FE7

15 14 13 12 11 10

9

0

8

7

6

0

5

0

4

0

3

0

2

0

1

0

1

0

2171 HDR0 Write

2171 HDR1 Write

2171 HDR2 Write

2171 HDR3 Write

2171 HDR4 Write

2171 HDR5 Write

Overwrite Mode

Software Reset

Control Registers

Biased Rounding

INSTRUCTIO N SET D ESCRIP TIO N

A new mode allows biased rounding in addition to the normal

unbiased rounding. When the BIASRND bit is set to 0, the nor-

mal unbiased rounding operations occur. When the BIASRND

bit is set to 1, biased rounding occurs instead of the normal un-

biased rounding. When operating in biased rounding mode all

rounding operations with MR0 set to 0x8000 will round up,

rather than only rounding odd MR1 values up. For example:

T he ADSP-217x assembly language instruction set has an alge-

braic syntax that was designed for ease of coding and read-

ability. T he assembly language, which takes full advantage of

the processor’s unique architecture, offers the following benefits:

• T he algebraic syntax eliminates the need to remember cryptic

assembler mnemonics. For example, a typical arithmetic add

instruction, such as AR = AX0 + AY0, resembles a simple

equation.

MR value before RND biased RND result unbiased RND result

00-0000-8000

00-0001-8000

00-0000-8001

00-0001-8001

00-0000-7FFF

00-0001-7FFF

00-0001-8000

00-0002-8000

00-0001-8001

00-0002-8001

00-0000-7FFF

00-0001-7FFF

00-0000-8000

00-0002-8000

00-0001-8001

00-0002-8001

00-0000-7FFF

00-0001-7FFF

• Every instruction assembles into a single, 24-bit word that can

execute in a single instruction cycle.

• T he syntax is a superset ADSP-2100 Family assembly lan-

guage and is completely source and object code compatible

with other family members. Programs may need to be relo-

cated to utilize internal memory and conform to the ADSP-

217x’s interrupt vector and reset vector map.

T his mode only has an effect when the MR0 register contains

0x8000, all other rounding operation work normally. T his mode

was added to allow more efficient implementation of bit speci-

fied algorithms which specify biased rounding such as the GSM

speech compression routines. Unbiased rounding is preferred

for most algorithms.

• Sixteen condition codes are available. For conditional jump,

call, return, or arithmetic instructions, the condition can be

checked and the operation executed in the same instruction

cycle.

• Multifunction instructions allow parallel execution of an arith-

metic instruction with up to two fetches or one write to pro-

cessor memory space during a single instruction cycle.

Note: BIASRND bit is Bit 12 of the SPORT 0 Autobuffer

Control register.

Consult the ADSP-2100 Family User’s Manual for a complete

description of the syntax and an instruction set reference.

REV. A

–15–

ADSP-2171/ADSP-2172/ADSP-2173

Exam ple Code

T he following example is a code fragment that performs the

filter tap update for an adaptive (least-mean-squared algorithm)

filter. Notice that the computations in the instructions are

written like algebraic equations.

MF=MX0*MY1 (RND), MX0=DM (I2,M1); /* MF=error*beta */

MR=MX0*MF (RND), AY0=PM (I6,MS);

DO adapt UNT IL CE;

AR=MR1 + AY0, MX0=DM (I2,M1), AY0=PM (I6,M7);

adapt: PM(I6,M6) =AR, MR=MX0*MF (RND);

MODIFY (I2, M3);

MODIFY (I6, M7);

/* Point to oldest data */

/* Point to start of data */

Inter r upt Enable

T he ADSP-217x supports an interrupt enable instruction. Inter-

rupts are enabled by default at reset. T he instruction source

code is specified as follows:

Syntax:

ENA INT S;

D escr iption: Executing the ENA INT S instruction allows all

unmasked interrupts to be serviced again.

Inter r upt D isable

T he ADSP-217x supports an interrupt disable instruction. T he

instruction source code is specified as follows:

Syntax:

DIS INT S;

D escr iption: Reset enables interrupt servicing. Executing the

DIS INT S instruction causes all interrupts to be

masked without changing the contents of the

IMASK register. Disabling interrupts does not

affect the autobuffer circuitry, which will operate

normally whether or not interrupts are enabled.

T he disable interrupt instruction masks all user

interrupts including the powerdown interrupt.

–16–

REV. A

ADSP-2171/ADSP-2172/ADSP-2173

ADSP-2171/ADSP-2172–SPECIFICATIONS

RECOMMENDED OPERATING CONDITIONS

K Grade

B Grade

P aram eter

Min

Max

Min

Max

Unit

V_DD

T _AMB

Supply Voltage

Ambient Operating T emperature

4.5

0

5.5

+70

4.5

–40

5.5

+85

V

°C

ELECTRICAL CHARACTERISTICS

K/B Grades

Min

P aram eter

Test Conditions

Max

Unit

V_IH

V_IL

V_OH

Hi-Level Input Voltage^{1, 2}

Hi-Level CLKIN Voltage

Hi-Level RESET Voltage

Lo-Level Input Voltage^{1, 3}

Hi-Level Output Voltage^{1, 4, 5}

@ V_DD= max

@ V_DD= min

I_OH= –0.5 mA

@ V_DD= min

I_OH= –100 µA⁶

@ V_DD= min

I_OL= 2 mA

@ V_DD= max

V_IN= V_DDmax

@ V_DD= max

V_IN= 0 V

@ V_DD= max,

V_IN= V_DDmax⁸

@ V_DD= max,

V_IN= 0 V⁸

@ V_DD= max

t_CK= 30 ns¹¹

Lowest Power Mode¹²

@ V_IN= 2.5 V,

f_IN= 1.0 MHz,

T _AMB= 25°C

@ V_IN= 2.5 V,

f_IN= 1.0 MHz,

T _AMB= 25°C

2.0

2.2

V

0.8

2.4

V

V_DD– 0.3

V

V_OL

I_IH

Lo-Level Output Voltage^{1, 4, 5}

Hi-Level Input Current³

Lo-Level Input Current³

T ristate Leakage Current⁷

0.4

10

V

µA

I_IL

I_OZH

I_OZL

10

18

µA

mA

I_DD

Supply Current (Idle)^{9, 10}

Supply Current (Dynamic)¹⁰

75

100

mA

µA

I_DD

C_I

Supply Current (Powerdown)¹⁰

Input Pin Capacitance^{3, 6, 13}

8

pF

C_O

Output Pin Capacitance^{6, 7, 13, 14}

NOT ES

¹Bidirectional pins: D0-D23, RFS0, RFS1, SCLK0, SCLK1, T FS0, T FS1, HD0-HD15/HAD0-HAD15.

²Input only pins: RESET, IRQ2, BR, MMAP, DR0, DR1, HSEL, HSIZE, BMODE, HMD0, HMD1, HRD/HWR, HWR/HDS, PWD, HA2/ALE, HA1-0.

³Input only pins: CLKIN, RESET, IRQ2, BR, MMAP, DR0, DR1, HSEL, HSIZE, BMODE, HMD0, HMD1, HRD/HWR, HWR/HDS, PWD, HA2/ALE, HA1-0.

⁴Output pins: BG, PMS, DMS, BMS, RD, WR, PWDACK, A0-A13, DT 0, DT 1, CLKOUT , HACK, FL2-0, BGH.

⁵Although specified for T T L outputs, all ADSP-2171/ADSP-2172 outputs are CMOS-compatible and will drive to V _DDand GND, assuming no dc loads.

⁶Guaranteed but not tested.

⁷T hree-statable pins: A0-A13, D0-D23, PMS, DMS, BMS, RD, WR, DT 0, DT 1, SCLK0, SCLK1, T FS0, T FS1, RFS0, RSF1, HD0-HD15/HAD0-HAD15.

⁸0 V on BR, CLKIN Active (to force three-state condition).

⁹Idle refers to ADSP-2171/ADSP-2172 state of operation during execution of IDLE instruction. Deasserted pins are driven to either V _DDor GND. Current reflects

device operation with CLKOUT disabled.

¹⁰Current reflects device operating with no output loads.

11

V

IN

= 0.4 V and 2.4 V. For typical figures for supply currents, refer to “Power Dissipation” section.

¹²See Chapter 9, of the ADSP-2100 Family User’s Manual for details.

¹³Applies to T QFP and PQFP package types.

¹⁴Output pin capacitance is the capacitive load for any three-state output pin.

Specifications subject to change without notice.

REV. A

–17–

ADSP-2171/ADSP-2172/ADSP-2173

ADSP-2171/ADSP-2172

ABSO LUTE MAXIMUM RATINGS^*

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

Input Voltage . . . . . . . . . . . . . . . . . . . . . –0.3 V to V_DD+ 0.3 V

Output Voltage Swing . . . . . . . . . . . . . . –0.3 V to V_DD+ 0.3 V

Operating T emperature Range (Ambient) . . . . –40°C to +85°C

Storage T emperature Range . . . . . . . . . . . . . –65°C to +150°C

Lead T emperature (5 sec) T QFP . . . . . . . . . . . . . . . . +280°C

Lead T emperature (5 sec) PQFP . . . . . . . . . . . . . . . . . +280°C

^*Stresses above those listed under “Absolute Maximum Ratings” may cause

permanent damage to the device. T hese are stress ratings only, and functional

operation of the device at these or any other conditions above those indicated in the

operational sections of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect device reliability.

ESD SENSITIVITY

T he ADSP-217x is an ESD (electrostatic discharge) sensitive device. Electrostatic charges readily

accumulate on the human body and equipment and can discharge without detection. Permanent

damage may occur to devices subjected to high energy electrostatic discharges.

T he ADSP-217x features proprietary ESD protection circuitry to dissipate high energy discharges

(Human Body Model). Per method 3015 of MIL-ST D-883, the ADSP-217x has been classified as

a Class 1 device.

WARNING!

ESD SENSITIVE DEVICE

Proper ESD precautions are recommended to avoid performance degradation or loss of function-

ality. Unused devices must be stored in conductive foam or shunts, and the foam should be

discharged to the destination before devices are removed.

ADSP-2171/ADSP-2172 TIMING PARAMETERS

ADSP-2171/ADSP-2172

GENERAL NO TES

Use the exact timing information given. Do not attempt to de-

rive parameters from the addition or subtraction of others.

MEMO RY REQ UIREMENTS

T his chart links common memory device specification names

and ADSP-2171/ADSP-2172 timing parameters for your

convenience.

While addition or subtraction would yield meaningful results for

an individual device, the values given in this data sheet reflect

statistical variations and worst cases. Consequently, you cannot

meaningfully add up parameters to derive longer times.

Com m on

P aram eter

Nam e

Mem ory D evice

Specification Nam e

TIMING NO TES

Function

Switching characteristics specify how the processor changes its

signals. You have no control over this timing; it is dependent on

the internal design. T iming requirements apply to signals that

are controlled outside the processor, such as the data input for a

read operation.

t_ASW

t_AW

A0-A13, DMS, PMS

Setup before WR Low

A0-A13, DMS, PMS

before WR Deasserted

A0-A13, DMS, PMS

Hold after WR Deasserted

Address Setup to

Write Start

Setup Address Setup

to Write End

t_WRA

Address Hold T ime

T iming requirements guarantee that the processor operates cor-

rectly with another device. Switching characteristics tell you

what the device will do under a given circumstance. Also, use

the switching characteristics to ensure any timing requirement

of a device connected to the processor (such as memory) is

satisfied.

t_DW

t_DH

t_RDD

t_AA

Data Setup before WR High Data Setup T ime

Data Hold after WR High

RD Low to Data Valid

A0-A13, DMS, PMS,

BMS to Data Valid

Data Hold T ime

OE to Data Valid

Address Access T ime

–18–

REV. A

ADSP-2171/ADSP-2172/ADSP-2173

ADSP-2171/ADSP-2172

P aram eter

Min

Max

Unit

Clock Signals

t_CKis defined as 0.5 t_CKI.T he ADSP-2171/ADSP-2172 uses an

input clock with a frequency equal to half the instruction rate; a

clock (which is equivalent to 60 ns) yields a 30 ns processor cycle

16.67 MHz input (equivalent to 33 MHz). t_CKvalues within the

range of 0.5 t_CKIperiod should be substituted for all relevant

timing parameters to obtain specification value.

Example: t_CKH= 0.5t_CK– 7 ns = 0.5 (30 ns) – 7 ns = 8 ns.

T iming Requirement:

t_CKI

t_CKIL

t_CKIH

CLKIN Period

CLKIN Width Low

CLKIN Width High

60

20

150

ns

Switching Characteristic:

t_CKL

t_CKH

t_CKOH

CLKOUT Width Low

CLKOUT Width High

CLKIN High to CLKOUT High

0.5t_CK– 7

0

ns

20

Contr ol Signals

T iming Requirement:

1

t_RSP

RESET Width Low

5t_CK

ns

NOT E

¹Applies after power-up sequence is complete. Internal phase lock loop requires no more than 2000 CLKIN cycles assuming stable CLKIN (not including crystal

oscillator start-up time).

t_CKI

t_CKIH

CLKIN

t_CKIL

t_CKOH

t_CKH

CLKOUT

t_CKL

Figure 8. Clock Signals

REV. A

–19–

ADSP-2171/ADSP-2172/ADSP-2173

ADSP-2171/ADSP-2172

P aram eter

Min

Max

Unit

Inter r upts and Flags

T iming Requirement:

t_IFS

t_IFH

IRQx or FI Setup before CLKOUT Low^{1, 2, 3}

IRQx or FI Hold after CLKOUT High^{1, 2, 3}

0.25t_CK+ 15

0.25t_CK

ns

Switching Characteristic:

t_FOH

Flag Output Hold after CLKOUT Low⁴

0.5t_CK– 7

ns

t_FOD

Flag Output Delay from CLKOUT Low⁴

0.5t_CK+ 5

NOT ES

¹If IRQx and FI inputs meet t_IFSand t_IFHsetup/hold requirements, they will be recognized during the current clock cycle; otherwise the signals will be recognized on

the following cycle. (Refer to “Interrupt Controller Operation” in the Program Control chapter of the User’s Manual for further information on interrupt servicing.)

²Edge-sensitive interrupts require pulse widths greater than 10 ns; level-sensitive interrupts must be held low until serviced.

³IRQx = IRQ0, IRQ1, and IRQ2.

⁴Flag Output = FL0, FL1, FL2, and FO.

t_FOD

CLKOUT

t_FOH

FLAG

OUTPUTS

t_IFH

IRQx

FI

t_IFS

Figure 9. Interrupts and Flags

–20–

REV. A

ADSP-2171/ADSP-2172/ADSP-2173

ADSP-2171/ADSP-2172

P aram eter

Min

Max

Unit

Bus Request/Gr ant

T iming Requirement:

t_BH

t_BS

BR Hold after CLKOUT High¹

BR Setup before CLKOUT Low¹

0.25t_CK+ 2

0.25t_CK+ 17

ns

Switching Characteristic:

t_SD

CLKOUT High to DMS, PMS, BMS,

0.25t_CK+ 16

ns

RD, WR Disable

t_SDB

t_SE

DMS, PMS, BMS, RD, WR

Disable to BG Low

BG High to DMS, PMS, BMS,

RD, WR Enable

DMS, PMS, BMS, RD, WR

Enable to CLKOUT High

DMS, PMS, BMS, RD, WR

Disable to BGH Low²

0

ns

0

t_SEC

t_SDBH

t_SEH

0.25t_CK– 7

0

BGH High to DMS, PMS, BMS,

RD, WR Enable²

NOT ES

¹BR is an asynchronous signal. If BR meets the setup/hold requirements, it will be recognized during the current clock cycle; otherwise the signal will be recognized

on the following cycle. Refer to the ADSP-2100 Family User’s Manual for BR/BG cycle relationships.

²BGH is asserted when the bus is granted and the processor requires control of the bus to continue.

t_BH

CLKOUT

BR

t_BS

CLKOUT

PMS, DMS

BMS, RD

t_SD

t_SEC

WR

BG

t_SDB

t_SE

BGH

t_SDBH

t_SEH

Figure 10. Bus Request–Bus Grant

REV. A

–21–

ADSP-2171/ADSP-2172/ADSP-2173

ADSP-2171/ADSP-2172

P aram eter

Min

Max

Unit

Mem or y Read

T iming Requirement:

t_RDD

t_AA

t_RDH

RD Low to Data Valid

A0–A13, PMS, DMS, BMS to Data Valid

Data Hold from RD High

0.5t_CK– 9 + w

0.75t_CK– 10.5 + w

ns

0

Switching Characteristic:

t_RP

RD Pulse Width

CLKOUT High to RD Low

A0–A13, PMS, DMS, BMS Setup before RD Low

A0–A13, PMS, DMS, BMS Hold after RD Deasserted

RD High to RD or WR Low

0.5t_CK– 5 + w

0.25t_CK– 5

0.25t_CK– 6

0.25t_CK– 3

0.5t_CK– 5

ns

t_CRD

t_ASR

t_RDA

t_RWR

0.25t_CK+ 7

w = wait states x t_CK

.

CLKOUT

A0–A13

DMS, PMS

BMS

t_RDA

RD

t_ASR

t_RP

t_RWR

t_CRD

D

t_RDD

t_RDH

t_AA

WR

Figure 11. Mem ory Read

–22–

REV. A

ADSP-2171/ADSP-2172/ADSP-2173

ADSP-2171/ADSP-2172

P aram eter

Min

Max

Unit

Mem or y Wr ite

Switching Characteristic:

t_DW

t_DH

t_WP

t_WDE

t_ASW

t_DDR

t_CWR

t_AW

Data Setup before WR High

Data Hold after WR High

WR Pulse Width

WR Low to Data Enabled

A0–A13, DMS, PMS Setup before WR Low

Data Disable before WR or RD Low

CLKOUT High to WR Low

A0–A13, DMS, PMS, Setup before WR Deasserted

A0–A13, DMS, PMS Hold after WR Deasserted

WR High to RD or WR Low

0.5 t_CK– 7 + w

0.25t_CK– 2

0.5t_CK– 5 + w

0

0.25t_CK– 6

0.25t_CK– 7

0.25t_CK– 5

0.75t_CK– 9 + w

0.25t_CK– 3

0.5t_CK– 5

ns

0.25 t_CK+ 7

t_WRA

t_WWR

w = wait states x t_CK

.

CLKOUT

A0–A13

DMS, PMS

t_WRA

WR

t_ASW

t_WP

t_WWR

t_AW

t_DH

t_DDR

t_CWR

D

t_DW

t_WDE

RD

Figure 12. Mem ory Write

REV. A

–23–

ADSP-2171/ADSP-2172/ADSP-2173

ADSP-2171/ADSP-2172

P aram eter

Min

Max

Unit

Ser ial P or ts

T iming Requirement:

t_SCK

t_SCS

t_SCH

t_SCP

SCLK Period

50

4

7

ns

DR/T FS/RFS Setup before SCLK Low

DR/T FS/RFS Hold after SCLK Low

SCLK_INWidth

20

Switching Characteristic:

t_CC

CLKOUT High to SCLK_OUT

SCLK High to DT Enable

SCLK High to DT Valid

T FS/RFS_OUTHold after SCLK High

T FS/RFS_OUTDelay from SCLK High

DT Hold after SCLK High

T FS(Alt) to DT Enable

T FS(Alt) to DT Valid

0.25t_CK

0

0.25t_CK+ 10

ns

t_SCDE

t_SCDV

t_RH

15

0

t_RD

t_SCDH

t_{T DE}

t_{T DV}

t_SCDD

t_RDV

0

15

SCLK High to DT Disable

RFS (Multichannel, Frame Delay Zero) to DT Valid

CLKOUT

t_CC

t_SCK

SCLK

t_SCP

t_SCS

t_SCH

t_SCP

DR

RFS

IN

TFS

IN

t_RD

t_RH

RFS

OUT

TFS

t_SCDD

t_SCDV

t_SCDE

t_SCDH

DT

t_TDE

t_TDV

TFS

ALTERNATE

FRAME MODE

t_RDV

RFS

MULTICHANNEL MODE,

FRAME DELAY 0

(MFD = 0)

Figure 13. Serial Ports

–24–

REV. A

ADSP-2171/ADSP-2172/ADSP-2173

ADSP-2171/ADSP-2172

P aram eter

Min

Max

Unit

H ost Inter face P or t

Separate Data and Address (HMD1 = 0)

Read Strobe and Write Strobe (HMD0 = 0)

T iming Requirement:

t_HSU

HA2–0 Setup before Start of Write or Read^{1, 2}

5

3

ns

t_HDSU

t_HWDH

t_HH

Data Setup before End of Write³

Data Hold after End of Write³

HA2–0 Hold after End of Write or Read^{3, 4}

Read or Write Pulse Width⁵

t_HRWP

20

Switching Characteristic:

t_HSHK

t_HKH

t_HDE

t_HDD

t_HRDH

t_HRDD

HACK Low after Start of Write or Read^{1, 2}

0

15

ns

HACK Hold after End of Write or Read^{3, 4}

Data Enabled after Start of Read²

Data Valid after Start of Read²

18

7

Data Hold after End of Read⁴

0

Data Disabled after End of Read⁴

NOT ES

¹Start of Write = HWR Low and HSEL Low.

²Start of Read = HRD Low and HSEL Low.

³End of Write = HWR High or HSEL High.

⁴End of Read = HRD High or HSEL High.

⁵Read Pulse Width = HRD Low and HSEL Low, Write Pulse Width = HWR Low and HSEL Low.

HA2–0

ADDRESS

t_HRWP

HSEL

t_HSU

Host Write Cycle

t_HH

HWR

HACK

t_HKH

t_HSHK

DATA

HD15–0

t_HWDH

t_HDSU

ADDRESS

t_HRWP

HA2–0

HSEL

t_HSU

Host Read Cycle

t_HH

HRD

HACK

t_HKH

t_HSHK

DATA

HD15–0

t_HDE

t_HDD

t_HRDH

t_HRDD

Figure 14. Host Interface Port (HMD1 = 0, HMD0 = 0)

REV. A

–25–

ADSP-2171/ADSP-2172/ADSP-2173

ADSP-2171/ADSP-2172

P aram eter

Min

Max

Unit

H ost Inter face P or t

Separate Data and Address (HMD1 = 0)

Read Strobe and Write Strobe (HMD0 = 1)

T iming Requirement:

t_HSU

HA2–0, HRW Setup before Start of Write or Read¹

Data Setup before End of Write²

5

3

ns

t_HDSU

t_HWDH

t_HH

Data Hold after End of Write²

HA2–0, HRW Hold after End of Write or Read²

Read or Write Pulse Width³

t_HRWP

20

Switching Characteristic:

t_HSHK

t_HKH

t_HDE

HACK Low after Start of Write or Read¹

0

15

ns

HACK Hold after End of Write or Read²

Data Enabled after Start of Read¹

Data Valid after Start of Read¹

t_HDD

t_HRDH

t_HRDD

18

7

Data Hold after End of Read²

0

Data Disabled after End of Read²

NOT ES

¹Start of Write or Read = HDS Low and HSEL Low.

²End of Write or Read = HDS High and HSEL High.

³Read or Write Pulse Width = HDS Low and HSEL Low.

ADDRESS

t_HRWP

HA2–0

HSEL

t_HSU

Host Write Cycle

HRW

t_HH

HDS

HACK

t_HSHK

t_HKH

DATA

t_HDSU

HD15–0

t_HWDH

ADDRESS

t_HRWP

HA2–0

HSEL

t_HSU

HRW

Host Read Cycle

t_HH

HDS

HACK

t_HKH

t_HSHK

DATA

t_HRDH

t_HRDD

HD15–0

t_HDE

t_HDD

Figure 15. Host Interface Port (HMD1 = 0, HMD0 = 1)

–26–

REV. A

ADSP-2171/ADSP-2172/ADSP-2173

ADSP-2171/ADSP-2172

P aram eter

Min

Max

Unit

H ost Inter face P or t

Multiplexed Data and Address (HMD1 = 1)

Read Strobe and Write Strobe (HMD0 = 0)

T iming Requirement:

t_HALP

t_HASU

t_HAH

t_HALS

t_HDSU

t_HWDH

t_HRWP

ALE Pulse Width

10

5

2

10

5

3

ns

HAD15–0 Address Setup, before ALE Low

HAD15–0 Address Hold after ALE Low

Start of Write or Read after ALE Low^{1, 2}

HAD15–0 Data Setup before End of Write³

HAD15–0 Data Hold after End of Write³

Read or Write Pulse Width⁴

20

Switching Characteristic:

t_HSHK

t_HKH

t_HDE

t_HDD

t_HRDH

t_HRDD

HACK Low after Start of Write or Read^{1, 2}

0

15

ns

HACK Hold after End of Write or Read^{3, 5}

HAD15–0 Data Enabled after Start of Read²

HAD15–0 Data Valid after Start of Read²

HAD15–0 Data Hold after End of Read

HAD15–0 Data Disabled after End of Read⁵

18

7

0

NOT ES

¹Start of Write = HWR Low and HSEL Low.

²Start of Read = HRD Low and HSEL Low.

³End of Write = HWR High or HSEL High.

⁴Read Pulse Width = HRD Low and HSEL Low, Write Pulse Width = HWR Low and HSEL Low.

⁵End of Read = HRD High or HSEL High.

ALE

t_HALP

t_HRWP

HSEL

t_HALS

Host Write Cycle

HWR

t_HSHK

t_HKH

t_HASU

t_HAH

HACK

ADDRESS

DATA

t_HDSU

HD15–0

t_HWDH

ALE

t_HALP

t_HRWP

Host Read Cycle

HSEL

HRD

t_HALS

t_HKH

t_HSHK

t_HASUt_HAH

ADDRESS

HACK

t_HDE

HAD15–0

DATA

t_HRDH

t_HRDD

t_HDD

Figure 16. Host Interface Port (HMD1 = 1, HMD0 = 0)

–27–

REV. A

ADSP-2171/ADSP-2172/ADSP-2173

ADSP-2171/ADSP-2172

P aram eter

Min

Max

Unit

Host Interface Port

Multiplexed Data and Address (HMD1 = 1)

Read Strobe and Write Strobe (HMD0 = 1)

T iming Requirement:

t_HALP

t_HASU

t_HAH

t_HALS

t_HSU

t_HDSU

t_HWDH

t_HH

ALE Pulse Width

10

5

2

10

5

3

20

ns

HAD15–0 Address Setup before ALE Low

HAD15–0 Address Hold after ALE Low

Start of Write or Read after ALE Low¹

HRW Setup before Start of Write or Read¹

HAD15–0 Data Setup before End of Write²

HAD15–0 Data Hold after End of Write²

HRW Hold after End of Write or Read²

Read or Write Pulse Width³

t_HRWP

Switching Characteristic:

t_HSHK

t_HKH

t_HDE

t_HDD

t_HRDH

t_HRDD

HACK Low after Start of Write or Read¹

0

15

ns

HACK Hold after End of Write or Read²

HAD15–0 Data Enabled after Start of Read¹

HAD15–0 Data Valid after Start of Read¹

HAD15–0 Data Hold after End of Read²

HAD15–0 Data Disabled after End of Read²

18

7

0

NOT ES

¹Start of Write or Read = HDS Low and HSEL Low.

²End of Write or Read = HDS High and HSEL High.

³Read or Write Pulse Width = HDS Low and HSEL Low.

ALE

t_HALP

t_HRWP

HSEL

t_HH

t_HALS

Host Write Cycle

HRW

t_HSU

HDS

t_HSHK

t_HKH

t_HASU

t_HAH

HACK

HD15–0

ALE

ADDRESS

DATA

t_HDSU

t_HWDH

t_HALP

t_HALS

t_HRWP

HSEL

t_HH

HRW

t_HSU

Host Read Cycle

HDS

HACK

t_HKH

t_HSHK

t_HASU

t_HAH

t_HDE

HD15–0

ADDRESS

DATA

t_HRDH

t_HDD

t_HRDD

Figure 17. Host Interface Port (HMD1 = 1, HMD0 = 1)

–28–

REV. A

ADSP-2171/ADSP-2172/ADSP-2173

1

POWER, INTERNAL

400

ADSP-2171/ADSP-2172

382mW

375

350

ENVIRO NMENTAL CO ND ITIO NS

Ambient T emperature Rating:

325

301mW

300

T _AMB= T _CASE– (PD × θ_{C A}

)

V

= 5.5V

DD

275

250

225

200

175

150

125

T _CASE= Case T emperature in °C

PD = Power Dissipation in W

θ_{C A}= T hermal Resistance (Case-to-Ambient)

θ_JA= T hermal Resistance (Junction-to-Ambient)

θ_JC= T hermal Resistance (Junction-to-Case)

V

= 5.0V

DD

229mW

186mW

V

= 4.5V

DD

148mW

110mW

P ackage

θ_JA

θ_JC

θ_CA

T QFP

PQFP

50°C/W

41°C/W

2°C/W

10°C/W

48°C/W

31°C/W

13 15 17 19 21 23 25 27 29 31 33

/ t_CK– MHz

1

1, 2

POWER, IDLE

85

80

75

70

65

60

55

50

45

40

35

30

P O WER D ISSIP ATIO N

T o determine total power dissipation in a specific application,

the following equation should be applied for each output:

82mW

2

C × V_DD× f

V

= 5.5V

DD

64mW

48mW

C = load capacitance, f = output switching frequency.

Exam ple:

V

= 5.0V

DD

48mW

In an application where external data memory is used and no

other outputs are active, power dissipation is calculated as

follows:

V

= 4.5V

DD

37mW

26mW

Assumptions:

•

External data memory is accessed every cycle with 50% of the

address pins switching.

13 15 17 19 21 23 25 27 29 31 33

/ t_CK– MHz

1

External data memory writes occur every other cycle with

50% of the data pins switching.

3

POWER, IDLE n MODES

72

68

64

60

56

52

48

44

40

36

32

28

24

20

16

•

Each address and data pin has a 10 pF total load at the pin.

82mW

T he application operates at V_DD= 5.0 V and t_CK= 30 ns.

64mW

IDLE;

2

Total Power Dissipation = P_INT+ (C × V_DD× f )

P_INT= internal power dissipation from Power vs. Frequency

graph (Figure 18).

2

(C × V_DD× f ) is calculated for each output:

# of

P ins × C

37mW

2

× V_{D D}

× f

31mW

28mW

Address, DMS

Data Output, WR

RD

8

9

1

× 10 pF × 5²

V

× 33.3 MHz

× 16.67 MHz = 37.5 mW

× 16.67 MHz =

× 33.3 MHz

=

66.6 mW

IDLE (16)

× 10 pF × 5²

V

IDLE (128)

× 10 pF × 5²

4.2 mW

8.3 mW

23mW

20mW

CLKOUT

=

116.6 mW

T otal power dissipation for this example is P_INT+ 116.6 mW.

13 15 17 19 21 23 25 27 29 31 33

/ t_CK– MHz

1

VALID FOR ALL TEMPERATURE GRADES.

1

POWER REFLECTS DEVICE OPERATING WITH NO OUTPUT LOADS.

IDLE REFERS TO ADSP-2171 STATE OF OPERATION DURING

EXECUTION OF IDLE INSTRUCTION. DEASSERTED PINS ARE

2

DRIVEN TO EITHER V

OR GND. POWER REFLECTS DEVICE

DD

OPERATING WITH CLKOUT DISABLED.

TYPICAL POWER DISSIPATION AT 5.0V V

3

DURING EXECUTION

DD

OF IDLE N INSTRUCTION (CLOCK FREQUENCY REDUCTION).

POWER REFLECTS DEVICE OPERATING WITH CLKOUT DISABLED.

Figure 18. Power vs. Frequency

REV. A

–29–

ADSP-2171/ADSP-2172/ADSP-2173

t_DECAY, is dependent on the capacitative load, C_L, and the cur-

rent load, i_L, on the output pin. It can be approximated by the

following equation:

ADSP-2171/ADSP-2172

CAP ACITIVE LO AD ING

Figures 19 and 20 show the capacitive loading characteristics of

the ADSP-2171/ADSP-2172.

C_L• 0.5V

t_DECAY

=

i_L

from which

28

24

20

t_DIS= t_MEASURED– t_DECAY

is calculated. If multiple pins (such as the data bus) are dis-

abled, the measurement value is that of the last pin to stop

driving.

V_DD= 4.5V

16

3.0V

INPUT

1.5V

0.0V

12

8

2.0V

1.5V

0.3V

OUTPUT

4

Figure 21. Voltage Reference Levels for AC Measure-

m ents (Except Output Enable/Disable)

25

50

75

100

125

150

C_L– pF

O utput Enable Tim e

Output pins are considered to be enabled when that have made

a transition from a high-impedance state to when they start driv-

ing. T he output enable time (t_ENA) is the interval from when a

reference signal reaches a high or low voltage level to when the

output has reached a specified high or low trip point, as shown

in the Output Enable/Disable diagram. If multiple pins (such as

the data bus) are enabled, the measurement value is that of the

first pin to start driving.

Figure 19. Typical Output Rise Tim e vs. Load Capacitance,

C_L(at Maxim um Am bient Operating Tem perature)

+14

+12

+10

+8

REFERENCE

SIGNAL

+4

+2

t_MEASURED

t_DIS

t_ENA

V

OH

NOMINAL

–2

(MEASURED)

V

(MEASURED) – 0.5V

(MEASURED) +0.5V

OH

2.0V

1.0V

OUTPUT

OL

V

OL

t_DECAY

(MEASURED)

25

50

75

100

– pF

125

150

C

L

OUTPUT STOPS

DRIVING

OUTPUT STARTS

DRIVING

Figure 20. Typical Output Valid Delay or Hold vs. Load

Capacitance, C_L(at Maxim um Am bient Operating

Tem perature)

HIGH-IMPEDANCE STATE. TEST CONDITIONS CAUSE

THIS VOLTAGE LEVEL TO BE APPROXIMATELY 1.5V.

Figure 22. Output Enable/Disable

TEST CO ND ITIO NS

O utput D isable Tim e

I

OL

Output pins are considered to be disabled when they have

stopped driving and started a transition from the measured out-

put high or low voltage to a high impedance state. T he output

disable time (t_DIS) is the difference of t_MEASUREDand t_DECAY, as

shown in the Output Enable/Disable diagram. T he time is the

interval from when a reference signal reaches a high or low volt-

age level to when the output voltages have changed by 0.5 V

from the measured output high or low voltage. T he decay time,

TO

OUTPUT

+1.5V

50pF

I

OH

Figure 23. Equivalent Device Loading for AC Measure-

m ents (Including All Fixtures)

–30–

REV. A

ADSP-2171/ADSP-2172/ADSP-2173

ADSP-2173–SPECIFICATIONS

RECOMMENDED OPERATING CONDITIONS

K Grade

B Grade

P aram eter

Min

Max

Min

Max

Unit

V_DD

T _AMB

Supply Voltage

Ambient Operating T emperature

3.0

0

3.6

+70

3.0

–40

3.6

+85

V

°C

ELECTRICAL CHARACTERISTICS

K/B Grades

Min

P aram eter

Test Conditions

Max

Unit

V_IH

V_IL

V_OH

Hi-Level Input Voltage^{1, 2}

Hi-Level CLKIN Voltage

Hi-Level RESET Voltage

Lo-Level Input Voltage^{1, 3}

Hi-Level Output Voltage^{1, 4, 5}

@ V_DD= max

@ V_DD= min

I_OH= –0.5 mA

@ V_DD= min

I_OH= –100 mA⁶

@ V_DD= min

I_OL= 2 mA

@ V_DD= max

V_IN= V_DDmax

@ V_DD= max

V_IN= 0 V

@ V_DD= max,

V_IN= V_DDmax⁸

@ V_DD= max,

V_IN= 0 V⁸

@ V_DD= max

t_CK= 50 ns¹¹

Lowest Power Mode¹²

@ V_IN= 2.5 V,

f_IN= 1.0 MHz,

T _AMB= 25°C

@ V_IN= 2.5 V,

f_IN= 1.0 MHz,

T _AMB= 25°C

2.0

2.2

V

0.4

2.4

V

V_DD– 0.3

V

V_OL

I_IH

Lo-Level Output Voltage^{1, 4, 5}

Hi-Level Input Current³

Lo-Level Input Current³

T ristate Leakage Current⁷

0.4

10

V

µA

I_IL

I_OZH

I_OZL

10

7

µA

mA

I_DD

Supply Current (Idle)^{9, 10}

Supply Current (Dynamic)¹⁰

27

100

mA

µA

I_DD

C_I

Supply Current (Powerdown)¹⁰

Input Pin Capacitance^{3, 6, 13}

8

pF

C_O

Output Pin Capacitance^{6, 7, 13, 14}

NOT ES

¹Bidirectional pins: D0-D23, RFS0, RFS1, SCLK0, SCLK1, T FS0, T FS1, HD0-HD15/HAD0-HAD15.

²Input only pins: RESET, IRQ2, BR, MMAP, DR0, DR1, HSEL, HSIZE, BMODE, HMD0, HMD1, HRD/HWR, HWR/HDS, PWD, HA2/ALE, HA1-0.

³Input only pins: CLKIN, RESET, IRQ2, BR, MMAP, DR0, DR1, HSEL, HSIZE, BMODE, HMD0, HMD1, HRD/HWR, HWR/HDS, PWD, HA2/ALE, HA1-0.

⁴Output pins: BG, PMS, DMS, BMS, RD, WR, PWDACK, A0-A13, DT 0, DT 1, CLKOUT , HACK, FL2-0, BGH.

⁵Although specified for T T L outputs, all ADSP-2173 outputs are CMOS-compatible and will drive to V _DDand GND, assuming no dc loads.

⁶Guaranteed but not tested.

⁷T hree-statable pins: A0-A13, D0-D23, PMS, DMS, BMS, RD, WR, DT 0, DT 1, SCLK0, SCLK1, T FS0, T FS1, RFS0, RSF1, HD0-HD15/HAD0-HAD15.

⁸0 V on BR, CLKIN Active (to force three-state condition).

⁹Idle refers to ADSP-2173 state of operation during execution of IDLE instruction. Deasserted pins are driven to either V _DDor GND. Current reflects

device operation with CLKOUT disabled.

¹⁰Current reflects device operating with no output loads.

11

V

IN

= 0.4 V and 2.4 V. For typical figures for supply currents, refer to “Power Dissipation” section.

¹²See Chapter 9, of the ADSP-2100 Family User’s Manual for details.

¹³Applies to T QFP and PQFP package types.

¹⁴Output pin capacitance is the capacitve load for any three-state output pin.

Specifications subject to change without notice.

REV. A

–31–

ADSP-2171/ADSP-2172/ADSP-2173

ADSP-2173 TIMING PARAMETERS

GENERAL NO TES

MEMO RY REQ UIREMENTS

Use the exact timing information given. Do not attempt to de-

rive parameters from the addition or subtraction of others.

While addition or subtraction would yield meaningful results for

an individual device, the values given in this data sheet reflect

statistical variations and worst cases. Consequently, you cannot

meaningfully add up parameters to derive longer times.

T his chart links common memory device specification names

and ADSP-2173 timing parameters for your convenience.

Com m on

P aram eter

Nam e

Mem ory D evice

Specification Nam e

Function

t_ASW

t_AW

A0-A13, DMS, PMS

Setup before WR Low

A0-A13, DMS, PMS

before WR Deasserted

A0-A13, DMS, PMS

Hold after WR Deasserted

Address Setup to

Write Start

Setup Address Setup

to Write End

TIMING NO TES

Switching characteristics specify how the processor changes its

signals. You have no control over this timing; it is dependent on

the internal design. T iming requirements apply to signals that

are controlled outside the processor, such as the data input for a

read operation.

t_WRA

Address Hold T ime

t_DW

t_DH

t_RDD

t_AA

Data Setup before WR High Data Setup T ime

T iming requirements guarantee that the processor operates cor-

rectly with another device. Switching characteristics tell you

what the device will do under a given circumstance. Also, use

the switching characteristics to ensure any timing requirement

of a device connected to the processor (such as memory) is

satisfied.

Data Hold after WR High

RD Low to Data Valid

A0-A13, DMS, PMS,

BMS to Data Valid

Data Hold T ime

OE to Data Valid

Address Access T ime

–32–

REV. A

ADSP-2171/ADSP-2172/ADSP-2173

ADSP-2173

P aram eter

Min

Max

Unit

Clock Signals

t_CKis defined as 0.5 t_CKI.T he ADSP-2173 uses an input clock with

a frequency equal to half the instruction rate; a 10.0 MHz input

clock (which is equivalent to 100 ns) yields a 50 ns processor cycle

(equivalent to 20 MHz). t_CKvalues within the range of 0.5 t_CKI

period should be substituted for all relevant timing parameters

to obtain specification value.

Example: t_CKH= 0.5t_CK– 10 ns = 0.5 (50 ns) – 10 ns = 15 ns.

T iming Requirement:

t_CKI

t_CKIL

t_CKIH

CLKIN Period

CLKIN Width Low

CLKIN Width High

100

20

160

ns

Switching Characteristic:

t_CKL

t_CKH

t_CKOH

CLKOUT Width Low

CLKOUT Width High

CLKIN High to CLKOUT High

0.5t_CK– 10

0

ns

25

Contr ol Signals

T iming Requirement:

1

t_RSP

RESET Width Low

5t_CK

ns

NOT E

¹Applies after power-up sequence is complete. Internal phase lock loop requires no more than 2000 CLKIN cycles assuming stable CLKIN (not including crystal

oscillator start-up time).

t_CKI

t_CKIH

CLKIN

t_CKIL

t_CKOH

t_CKH

CLKOUT

t_CKL

Figure 24. Clock Signals

REV. A

–33–

ADSP-2171/ADSP-2172/ADSP-2173

ADSP-2173

P aram eter

Min

Max

Unit

Inter r upts and Flags

T iming Requirement:

t_IFS

t_IFH

IRQx or FI Setup before CLKOUT Low^{1, 2, 3}

IRQx or FI Hold after CLKOUT High^{1, 2, 3}

0.25t_CK+ 23

0.25t_CK

ns

Switching Characteristic:

t_FOH

Flag Output Hold after CLKOUT Low⁴

0.5t_CK– 10

ns

t_FOD

Flag Output Delay from CLKOUT Low⁴

0.5t_CK+ 5

NOT ES

¹If IRQx and FI inputs meet t_IFSand t_IFHsetup/hold requirements, they will be recognized during the current clock cycle; otherwise the signals will be recognized on

the following cycle. (Refer to “Interrupt Controller Operation” in the Program Control chapter of the User’s Manual for further information on interrupt servicing.)

²Edge-sensitive interrupts require pulse widths greater than 10 ns; level-sensitive interrupts must be held low until serviced.

³IRQx = IRQ0, IRQ1, and IRQ2.

⁴Flag Output = FL0, FL1, FL2, and FO.

t_FOD

CLKOUT

t_FOH

FLAG

OUTPUTS

t_IFH

IRQx

FI

t_IFS

Figure 25. Interrupts and Flags

–34–

REV. A

ADSP-2171/ADSP-2172/ADSP-2173

ADSP-2173

P aram eter

Min

Max

Unit

Bus Request/Gr ant

T iming Requirement:

t_BH

t_BS

BR Hold after CLKOUT High¹

BR Setup before CLKOUT Low¹

0.25t_CK+ 2

0.25t_CK+ 22

ns

Switching Characteristic:

t_SD

CLKOUT High to DMS, PMS, BMS,

0.25t_CK+ 16

ns

RD, WR Disable

t_SDB

t_SE

DMS, PMS, BMS, RD, WR

Disable to BG Low

BG High to DMS, PMS, BMS,

RD, WR Enable

DMS, PMS, BMS, RD, WR

Enable to CLKOUT High

DMS, PMS, BMS, RD, WR

Disable to BGH Low²

0

ns

0

t_SEC

t_SDBH

t_SEH

0.25t_CK– 10

0

BGH High to DMS, PMS, BMS,

RD, WR Enable²

NOT ES

¹BR is an asynchronous signal. If BR meets the setup/hold requirements, it will be recognized during the current clock cycle; otherwise the signal will be recognized

on the following cycle. Refer to the ADSP-2100 Family User’s Manual for BR/BG cycle relationships.

²BGH is asserted when the bus is granted and the processor requires control of the bus to continue.

t_BH

CLKOUT

BR

t_BS

CLKOUT

PMS, DMS

BMS, RD

t_SD

t_SEC

WR

BG

t_SDB

t_SE

BGH

t_SDBH

t_SEH

Figure 26. Bus Request–Bus Grant

REV. A

–35–

ADSP-2171/ADSP-2172/ADSP-2173

ADSP-2173

P aram eter

Min

Max

Unit

Mem or y Read

T iming Requirement:

t_RDD

t_AA

t_RDH

RD Low to Data Valid

A0–A13, PMS, DMS, BMS to Data Valid

Data Hold from RD High

0.5t_CK– 15 + w

0.75t_CK– 20.5 + w

ns

0

Switching Characteristic:

t_RP

RD Pulse Width

CLKOUT High to RD Low

A0–A13, PMS, DMS, BMS Setup before RD Low

A0–A13, PMS, DMS, BMS Hold after RD Deasserted

RD High to RD or WR Low

0.5t_CK– 5 + w

0.25t_CK– 5

0.25t_CK– 7

0.25t_CK– 3

0.5t_CK– 5

ns

t_CRD

t_ASR

t_RDA

t_RWR

0.25t_CK+ 10

w = wait states x t_CK

.

CLKOUT

A0–A13

DMS, PMS

BMS

t_RDA

RD

t_ASR

t_RP

t_RWR

t_CRD

D

t_RDD

t_RDH

t_AA

WR

Figure 27. Mem ory Read

–36–

REV. A

ADSP-2171/ADSP-2172/ADSP-2173

ADSP-2173

P aram eter

Min

Max

Unit

Mem or y Wr ite

Switching Characteristic:

t_DW

t_DH

t_WP

t_WDE

t_ASW

t_DDR

t_CWR

t_AW

Data Setup before WR High

Data Hold after WR High

WR Pulse Width

WR Low to Data Enabled

A0–A13, DMS, PMS Setup before WR Low

Data Disable before WR or RD Low

CLKOUT High to WR Low

A0–A13, DMS, PMS, Setup before WR Deasserted

A0–A13, DMS, PMS Hold after WR Deasserted

WR High to RD or WR Low

0.5 t_CK– 7 + w

0.25t_CK– 2

0.5t_CK– 5 + w

0

0.25t_CK– 7

0.25t_CK– 5

0.75t_CK– 11.5 + w

0.25t_CK– 3

0.5t_CK– 5

ns

0.25 t_CK+ 10

t_WRA

t_WWR

w = wait states x t_CK

.

CLKOUT

A0–A13

DMS, PMS

t_WRA

WR

t_ASW

t_WP

t_WWR

t_AW

t_DH

t_DDR

t_CWR

D

t_DW

t_WDE

RD

Figure 28. Mem ory Write

REV. A

–37–

ADSP-2171/ADSP-2172/ADSP-2173

ADSP-2173

P aram eter

Min

Max

Unit

Ser ial P or ts

T iming Requirement:

t_SCK

t_SCS

t_SCH

t_SCP

SCLK Period

76.9

8

10

28

ns

DR/T FS/RFS Setup before SCLK Low

DR/T FS/RFS Hold after SCLK Low

SCLK_INWidth

Switching Characteristic:

t_CC

CLKOUT High to SCLK_OUT

SCLK High to DT Enable

SCLK High to DT Valid

T FS/RFS_OUTHold after SCLK High

T FS/RFS_OUTDelay from SCLK High

DT Hold after SCLK High

T FS(Alt) to DT Enable

T FS(Alt) to DT Valid

0.25t_CK

0

0.25t_CK+ 15

ns

t_SCDE

t_SCDV

t_RH

20

0

t_RD

t_SCDH

t_{T DE}

t_{T DV}

t_SCDD

t_RDV

0

19

25

20

SCLK High to DT Disable

RFS (Multichannel, Frame Delay Zero) to DT Valid

CLKOUT

t_CC

t_SCK

SCLK

t_SCP

t_SCS

t_SCH

t_SCP

DR

RFS

IN

TFS

IN

t_RD

t_RH

RFS

OUT

TFS

t_SCDD

t_SCDV

t_SCDE

t_SCDH

DT

t_TDE

t_TDV

TFS

ALTERNATE

FRAME MODE

t_RDV

RFS

MULTICHANNEL MODE,

FRAME DELAY 0

(MFD = 0)

Figure 29. Serial Ports

–38–

REV. A

ADSP-2171/ADSP-2172/ADSP-2173

ADSP-2173

P aram eter

Min

Max

Unit

H ost Inter face P or t

Separate Data and Address (HMD1 = 0)

Read Strobe and Write Strobe (HMD0 = 0)

T iming Requirement:

t_HSU

HA2–0 Setup before Start of Write or Read^{1, 2}

8

3

ns

t_HDSU

t_HWDH

t_HH

Data Setup before End of Write³

Data Hold after End of Write³

HA2–0 Hold after End of Write or Read^{3, 4}

Read or Write Pulse Width⁵

t_HRWP

30

Switching Characteristic:

t_HSHK

t_HKH

t_HDE

t_HDD

t_HRDH

t_HRDD

HACK Low after Start of Write or Read^{1, 2}

0

20

ns

HACK Hold after End of Write or Read^{3, 4}

Data Enabled after Start of Read²

Data Valid after Start of Read²

23

15

Data Hold after End of Read⁴

0

Data Disabled after End of Read⁴

NOT ES

¹Start of Write = HWR Low and HSEL Low.

²Start of Read = HRD Low and HSEL Low.

³End of Write = HWR High or HSEL High.

⁴End of Read = HRD High or HSEL High.

⁵Read Pulse Width = HRD Low and HSEL Low, Write Pulse Width = HWR Low and HSEL Low.

HA2–0

ADDRESS

t_HRWP

HSEL

t_HSU

Host Write Cycle

t_HH

HWR

HACK

t_HKH

t_HSHK

DATA

HD15–0

t_HWDH

t_HDSU

ADDRESS

t_HRWP

HA2–0

HSEL

t_HSU

Host Read Cycle

t_HH

HRD

HACK

t_HKH

t_HSHK

DATA

HD15–0

t_HDE

t_HDD

t_HRDH

t_HRDD

Figure 30. Host Interface Port (HMD1 = 0, HMD0 = 0)

REV. A

–39–

ADSP-2171/ADSP-2172/ADSP-2173

ADSP-2173

P aram eter

Min

Max

Unit

H ost Inter face P or t

Separate Data and Address (HMD1 = 0)

Read Strobe and Write Strobe (HMD0 = 1)

T iming Requirement:

t_HSU

HA2–0, HRW Setup before Start of Write or Read¹

Data Setup before End of Write²

8

3

ns

t_HDSU

t_HWDH

t_HH

Data Hold after End of Write²

HA2–0, HRW Hold after End of Write or Read²

Read or Write Pulse Width³

t_HRWP

30

Switching Characteristic:

t_HSHK

t_HKH

t_HDE

t_HDD

t_HRDH

t_HRDD

HACK Low after Start of Write or Read¹

0

20

ns

HACK Hold after End of Write or Read²

Data Enabled after Start of Read¹

Data Valid after Start of Read¹

23

15

Data Hold after End of Read²

0

Data Disabled after End of Read²

NOT ES

¹Start of Write or Read = HDS Low and HSEL Low.

²End of Write or Read = HDS High and HSEL High.

³Read or Write Pulse Width = HDS Low and HSEL Low.

ADDRESS

t_HRWP

HA2–0

HSEL

t_HSU

Host Write Cycle

HRW

t_HH

HDS

HACK

t_HSHK

t_HKH

DATA

t_HDSU

HD15–0

t_HWDH

ADDRESS

t_HRWP

HA2–0

HSEL

t_HSU

HRW

Host Read Cycle

t_HH

HDS

HACK

t_HKH

t_HSHK

DATA

t_HRDH

t_HRDD

HD15–0

t_HDE

t_HDD

Figure 31. Host Interface Port (HMD1 = 0, HMD0 = 1)

–40–

REV. A

ADSP-2171/ADSP-2172/ADSP-2173

ADSP-2173

P aram eter

Min

Max

Unit

H ost Inter face P or t

Multiplexed Data and Address (HMD1 = 1)

Read Strobe and Write Strobe (HMD0 = 0)

T iming Requirement:

t_HALP

t_HASU

t_HAH

t_HALS

t_HDSU

t_HWDH

t_HRWP

ALE Pulse Width

15

5

2

15

8

3

ns

HAD15–0 Address Setup, before ALE Low

HAD15–0 Address Hold after ALE Low

Start of Write or Read after ALE Low^{1, 2}

HAD15–0 Data Setup before End of Write³

HAD15–0 Data Hold after End of Write³

Read or Write Pulse Width⁵

30

Switching Characteristic:

t_HSHK

t_HKH

t_HDE

t_HDD

t_HRDH

t_HRDD

HACK Low after Start of Write or Read^{1, 2}

0

20

ns

HACK Hold after End of Write or Read^{3, 4}

HAD15–0 Data Enabled after Start of Read²

HAD15–0 Data Valid after Start of Read²

HAD15–0 Data Hold after End of Read

HAD15–0 Data Disabled after End of Read⁴

23

15

0

NOT ES

¹Start of Write = HWR Low and HSEL Low.

²Start of Read = HRD Low and HSEL Low.

³End of Write = HWR High or HSEL High.

⁴End of Read = HRD High or HSEL High.

⁵Read Pulse Width = HRD Low and HSEL Low, Write Pulse Width = HWR Low and HSEL Low.

ALE

t_HALP

t_HRWP

HSEL

t_HALS

Host Write Cycle

HWR

t_HSHK

t_HKH

t_HASU

t_HAH

HACK

ADDRESS

DATA

t_HDSU

HD15–0

t_HWDH

ALE

t_HALP

t_HRWP

HSEL

HRD

Host Read Cycle

t_HALS

t_HKH

t_HSHK

t_HASUt_HAH

ADDRESS

HACK

t_HDE

HAD15–0

DATA

t_HRDH

t_HRDD

t_HDD

Figure 32. Host Interface Port (HMD1 = 1, HMD0 = 0)

–41–

REV. A

ADSP-2171/ADSP-2172/ADSP-2173

ADSP-2173

P aram eter

Min

Max

Unit

Host Interface Port

Multiplexed Data and Address (HMD1 = 1)

Read Strobe and Write Strobe (HMD0 = 1)

T iming Requirement:

t_HALP

t_HASU

t_HAH

t_HALS

t_HSU

t_HDSU

t_HWDH

t_HH

ALE Pulse Width

15

5

2

15

8

3

30

ns

HAD15–0 Address Setup before ALE Low

HAD15–0 Address Hold after ALE Low

Start of Write or Read after ALE Low¹

HRW Setup before Start of Write or Read¹

HAD15–0 Data Setup before End of Write²

HAD15–0 Data Hold after End of Write²

HRW Hold after End of Write or Read²

Read or Write Pulse Width³

t_HRWP

Switching Characteristic:

t_HSHK

t_HKH

t_HDE

t_HDD

t_HRDH

t_HRDD

HACK Low after Start of Write or Read¹

0

20

ns

HACK Hold after End of Write or Read²

HAD15–0 Data Enabled after Start of Read¹

HAD15–0 Data Valid after Start of Read¹

HAD15–0 Data Hold after End of Read²

HAD15–0 Data Disabled after End of Read²

23

15

0

NOT ES

¹Start of Write or Read = HDS Low and HSEL Low.

²End of Write or Read = HDS High and HSEL High.

³Read or Write Pulse Width = HDS Low and HSEL Low.

ALE

t_HALP

t_HRWP

HSEL

t_HH

t_HALS

Host Write Cycle

HRW

t_HSU

HDS

t_HSHK

t_HKH

t_HASU

t_HAH

HACK

HD15–0

ALE

ADDRESS

DATA

t_HDSU

t_HWDH

t_HALP

t_HALS

t_HRWP

HSEL

t_HH

HRW

t_HSU

Host Read Cycle

HDS

HACK

t_HKH

t_HSHK

t_HASU

t_HAH

t_HDE

HD15–0

ADDRESS

DATA

t_HRDH

t_HDD

t_HRDD

Figure 33. Host Interface Port (HMD1 = 1, HMD0 = 1)

–42–

REV. A

ADSP-2171/ADSP-2172/ADSP-2173

1

POWER, INTERNAL

ADSP-2173

89 mW

90

ENVIRO NMENTAL CO ND ITIO NS

Ambient T emperature Rating:

85

80

75

71 mW

57 mW

T _AMB= T _CASE– (PD × θ_{C A}

T _CASE= Case T emperature in °C

PD = Power Dissipation in W

θ_{C A}= T hermal Resistance (Case-to-Ambient)

θ_JA= T hermal Resistance (Junction-to-Ambient)

θ_JC= T hermal Resistance (Junction-to-Case)

)

70

65

60

55

50

55 mW

44 mW

32 mW

45

40

35

P ackage

θ_JA

θ_JC

θ_CA

T QFP

PQFP

50°C/W

41°C/W

2°C/W

10°C/W

48°C/W

31°C/W

12 13 14

15 16 17 18 19 20

1/ t_CK– MHz

1, 2

POWER, IDLE

P O WER D ISSIP ATIO N

T o determine total power dissipation in a specific application,

the following equation should be applied for each output:

20

20.5 mW

16.2 mW

19

18

17

16

15

14

13

12

11

2

C × V_DD× f

C = load capacitance, f = output switching frequency.

Exam ple:

15.5 mW

11.8 mW

In an application where external data memory is used and no

other outputs are active, power dissipation is calculated as

follows:

12.7 mW

Assumptions:

10

9

8.5 mW

•

External data memory is accessed every cycle with 50% of the

address pins switching.

12 13 14 15 16 17 18 19 20

1/ t_CK– MHz

External data memory writes occur every other cycle with

50% of the data pins switching.

3

POWER, IDLE n MODES

•

Each address and data pin has a 10 pF total load at the pin.

T he application operates at V_DD= 3.3 V and t_CK= 50 ns.

16

15

16.2 mW

IDLE;

2

Total Power Dissipation = P_INT+ (C × V_DD× f )

14

13

12

11

10

9

P_INT= internal power dissipation from Power vs. Frequency

graph (Figure 18).

2

11.8 mW

(C × V_DD× f ) is calculated for each output:

# of

P ins × C

7.8 mW

7.2 mW

IDLE (16)

2

8

× V_{D D}

× f

6.8 mW

6.2 mW

7

Address, DMS

Data Output, WR

RD

8

9

1

× 10 pF × 3.3²

V

× 20 MHz

× 10 MHz

× 20 MHz

=

17.4 mW

9.8 mW

1.1 mW

2.2 mW

30.5 mW

IDLE (128)

6

5

CLKOUT

12 13 14 15 16 17 18 19 20

1/ t_CK– MHz

VALID FOR ALL TEMPERATURE GRADES.

1

T otal power dissipation for this example is P_INT+ 30.5 mW.

POWER REFLECTS DEVICE OPERATING WITH NO OUTPUT LOADS.

IDLE REFERS TO ADSP-2173 STATE OF OPERATION DURING

EXECUTION OF IDLE INSTRUCTION. DEASSERTED PINS ARE

2

DRIVEN TO EITHER V

OR GND. POWER REFLECTS DEVICE

DD

OPERATING WITH CLKOUT DISABLED.

TYPICAL POWER DISSIPATION AT 3.3V V

3

DURING EXECUTION

DD

OF IDLE n INSTRUCTION (CLOCK FREQUENCY REDUCTION).

POWER REFLECTS DEVICE OPERATING WITH CLKOUT DISABLED.

Figure 34. Power vs. Frequency

REV. A

–43–

ADSP-2171/ADSP-2172/ADSP-2173

t_DECAY, is dependent on the capacitative load, C_L, and the cur-

rent load, i_L, on the output pin. It can be approximated by the

following equation:

ADSP-2173

CAP ACITIVE LO AD ING

Figures 35 and 36 show the capacitive loading characteristics of

the ADSP-2173.

C_L• 0.5V

t_DECAY

=

i_L

from which

t_DIS= t_MEASURED– t_DECAY

28

is calculated. If multiple pins (such as the data bus) are dis-

abled, the measurement value is that of the last pin to stop

driving.

24

V_DD= 3.3 V

20

16

12

8

V

DD

INPUT

2

V

DD

OUTPUT

2

Figure 37. Voltage Reference Levels for AC Measure-

m ents (Except Output Enable/Disable)

25

50

75

100

C_L– pF

125

150

O utput Enable Tim e

Output pins are considered to be enabled when that have made

a transition from a high-impedance state to when they start driv-

ing. T he output enable time (t_ENA) is the interval from when a

reference signal reaches a high or low voltage level to when the

output has reached a specified high or low trip point, as shown

in the Output Enable/Disable diagram. If multiple pins (such as

the data bus) are enabled, the measurement value is that of the

first pin to start driving.

Figure 35. Typical Output Rise Tim e vs. Load Capacitance,

C_L(at Maxim um Am bient Operating Tem perature)

+14

+12

+10

+8

REFERENCE

SIGNAL

+4

t_MEASURED

t_DIS

t_ENA

+2

NOMINAL

-2

V

OH

(MEASURED)

V

(MEASURED) – 0.5V

(MEASURED) +0.5V

OH

2.0V

1.0V

OUTPUT

OL

V

OL

t_DECAY

(MEASURED)

25

50

75

100

– pF

125

150

C

L

OUTPUT STOPS

DRIVING

OUTPUT STARTS

DRIVING

Figure 36. Typical Output Valid Delay or Hold vs. Load

Capacitance, C_L(at Maxim um Am bient Operating

Tem perature)

HIGH-IMPEDANCE STATE. TEST CONDITIONS CAUSE

THIS VOLTAGE LEVEL TO BE APPROXIMATELY 1.5V.

Figure 38. Output Enable/Disable

TEST CO ND ITIO NS

O utput D isable Tim e

I_OL

Output pins are considered to be disabled when they have

stopped driving and started a transition from the measured out-

put high or low voltage to a high impedance state. T he output

disable time (t_DIS) is the difference of t_MEASUREDand t_DECAY, as

shown in the Output Enable/Disable diagram. T he time is the

interval from when a reference signal reaches a high or low volt-

age level to when the output voltages have changed by 0.5 V

from the measured output high or low voltage. T he decay time,

TO

OUTPUT

V_DD

2

50pF

I_OH

Figure 39. Equivalent Device Loading for AC Measure-

m ents (Including All Fixtures)

–44–

REV. A

ADSP-2171/ADSP-2172/ADSP-2173

128-Lead TQFP P ackage P inout

128

103

102

1

GND

HA2/ALE

HA1

HA0

HSEL

HD5

NC

D23

D22

D21

D20

D19

GND

D18

D17

D16

D15

D14

D13

D12

D11

HD4

HD3

HD2

HD1

HD0

V

DD

GND

V

DD

A0

A1

V

DD

TOP VIEW

(PINS DOWN)

A3

A2

A4

GND

D10

D9

D8

A5

D7

A6

D6

A7

D5

D4

D3

GND

D2

XTAL

CLKIN

CLKOUT

GND

A8

D1

A9

D0

A10

A11

A12

A13

NC

MMAP

NC

BG

NC

BR

NC

BGH

PWD

NC

38

65

39

64

NC = NO CONNECT

REV. A

–45–

ADSP-2171/ADSP-2172/ADSP-2173

TQFP P in Configurations

TQFP

P in

TQFP

P in

TQFP

P in

TQFP

P in

Num ber

Nam e

Num ber

Nam e

Num ber

Nam e

Num ber

Nam e

1

2

3

4

5

6

7

8

9

GND

HA2/ALE

HA1

HA0

HSEL

HD5

HD4

HD3

HD2

HD1

HD0

V_DD

GND

V_DD

A0

A1

A2

A3

A4

A5

A6

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

A13

NC

MMAP

NC

PWD

IRQ2

NC

BMODE

NC

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

NC

BGH

NC

BR

NC

BG

D0

D1

D2

GND

D3

D4

D5

D6

D7

D8

97

98

99

D20

D21

D22

D23

NC

RD

WR

GND

V_DD

PMS

DMS

BMS

PWDACK

HD15

HD14

HD13

HD12

HD11

V_DD

HD10

HD9

HD8

HD7

HD6

HSIZE

HRD/HRW

HWR/HDS

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

NC

V_DD

GND

RESET

NC

HACK

HMD0

HMD1

DT 0

T FS0

RFS0

DR0

SCLK0

DT 1/FO

T FS1/IRQ1

RFS1/IRQ0

GND

DR1/F1

SCLK1

FL0

D9

D10

GND

V_DD

D11

D12

D13

D14

D15

D16

D17

D18

GND

D19

A7

XT AL

CLKIN

CLKOUT

GND

A8

A9

A10

A11

A12

FL1

FL2

NC = T hese pins MUST remain unconnected.

–46–

REV. A

ADSP-2171/ADSP-2172/ADSP-2173

O UTLINE D IMENSIO NS

128-Lead Metr ic Thin P lastic Q uad Flatpack (TQ FP )

D

SEATING

PLANE

D

1

A

D

3

L

103

128

1

102

TOP VIEW

(PINS DOWN)

E

1

3

38

39

65

64

A

1

A

2

e

B

MILLIMETERS

TYP

INCHES

TYP

SYMBOL MIN

A

MAX

1.60

0.15

1.50

MIN

MAX

0.063

A₁

A₂

D

0.05

1.30

0.002

0.051

0.620

0.547

0.006

0.059

0.640

0.555

0.495

0.876

0.792

0.731

0.030

0.023

0.011

0.004

1.40

0.055

0.630

0.551

0.492

0.866

0.787

0.728

0.024

0.019

0.009

15.75

13.90

16.00 16.25

14.00 14.10

12.50 12.58

22.00 22.25

20.00 20.10

18.50 18.58

D₁

D₃

E

21.75

19.90

0.856

0.783

E₁

E₃

L

0.45

0.42

0.17

0.60

0.50

0.22

0.75

0.58

0.27

0.10

0.018

0.017

0.007

e

B

REV. A

–47–

ADSP-2171/ADSP-2172/ADSP-2173

128-Lead P QFP P ackage P inout

97

128

96

1

HA2/ALE

HA1

HA0

HSEL

HD5

D23

D22

D21

D20

D19

GND

D18

D17

D16

D15

D14

D13

D12

D11

HD4

HD3

HD2

HD1

HD0

V

DD

GND

128L PQFP

(28MM x 28MM)

V

DD

A0

A1

V

DD

TOP VIEW

(PINS DOWN)

GND

D10

D9

A2

A3

A4

A5

D8

A6

D7

A7

D6

XTAL

CLKIN

CLKOUT

GND

A8

D5

D4

D3

GND

D2

D1

A9

D0

A10

A11

A12

A13

NC

BG

NC

BR

NC

32

65

33

64

NC = NO CONNECT

–48–

REV. A

ADSP-2171/ADSP-2172/ADSP-2173

P QFP P in Configurations

P QFP

Num ber

P in

Nam e

P QFP

Num ber

P in

Nam e

P QFP

Num ber

P in

Nam e

P QFP

Num ber

P in

Nam e

1

2

3

4

5

6

7

8

9

HA2/ALE

HA1

HA0

HSEL

HD5

HD4

HD3

HD2

HD1

HD0

V_DD

GND

V_DD

A0

A1

A2

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

MMAP

NC

PWD

IRQ2

NC

BMODE

NC

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

NC

BR

NC

BG

D0

D1

D2

GND

D3

D4

D5

D6

D7

D8

D9

D10

GND

V_DD

D11

D12

D13

D14

D15

D16

D17

D18

GND

D19

D20

D21

D22

D23

97

98

99

NC

RD

WR

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

V_DD

GND

V_DD

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

GND

RESET

NC

HACK

HMD0

HMD1

DT 0

T FS0

RFS0

DR0

SCLK0

DT 1/FO

T FS1/IRQ1

RFS1/IRQ0

GND

DR1/F1

SCLK1

FL0

PMS

DMS

BMS

PWDACK

HD15

HD14

HD13

HD12

HD11

V_DD

HD10

HD9

HD8

HD7

HD6

A3

A4

A5

A6

A7

XT AL

CLKIN

CLKOUT

GND

A8

A9

A10

A11

A12

HSIZE

HRD/HRW

HWR/HDS

GND

NC

FL1

FL2

NC

BGH

A13

NC

NC = T hese pins MUST remain unconnected.

REV. A

–49–

ADSP-2171/ADSP-2172/ADSP-2173

O UTLINE D IMENSIO NS

128-Lead Metr ic Thin P lastic Q uad Flatpack (P Q FP )

D

SEATING

PLANE

D

1

A

D

3

L

97

128

1

96

TOP VIEW

(PINS DOWN)

E

3

1

32

33

65

64

A

1

A

e

B

2

MILLIMETERS

INCHES

TYP

SYMBOL MIN

A

TYP

MAX

4.07

MIN

MAX

0.160

A₁

0.25

3.17

0.010

0.125

1.219

1.098

0.974

0.031

0.029

0.012

A₂

3.49

3.67

0.137

1.228

1.102

0.976

0.035

0.031

0.014

0.144

1.238

1.106

0.979

0.041

0.034

0.018

0.004

D, E

D₁, E₁

D₃, E₃

L

30.95

27.90

24.73

0.65

31.20 31.45

28.00 28.10

24.80 24.87

0.88

0.80

0.35

1.03

0.87

0.45

0.10

e

0.73

B

0.30

–50–

REV. A

ADSP-2171/ADSP-2172/ADSP-2173

O RD ERING GUID E*

Am bient

Tem perature

Range

Instruction

Rate

(MH z)

P ackage

D escription

P art Num ber**

ADSP-2171KST -133

ADSP-2171BST -133

ADSP-2171KS-133

ADSP-2171BS-133

0°C to +70°C

–40°C to +85°C

0°C to +70°C

–40°C to +85°C

33.33

128-Lead T QFP

128-Lead PQFP

ADSP-2171KST -104

ADSP-2171BST -104

ADSP-2171KS-104

ADSP-2171BS-104

0°C to +70°C

–40°C to +85°C

0°C to +70°C

–40°C to +85°C

26

128-Lead T QFP

128-Lead PQFP

ADSP-2173BST -80

ADSP-2173BS-80

–40°C to +85°C

20

128-Lead T QFP

128 Lead PQFP

*Refer to section titled “Ordering Procedure for ADSP-2172 ROM Processors” for information about ordering ROM-coded parts.

**S = Plastic Quad Flatpack, ST = Plastic T hin Quad Flatpack.

REV. A

–51–

–52–


型号：	ADSP-2171KST-104
厂家：	ADI
描述：	DSP Microcomputer 微电脑DSP 外围集成电路电脑
文件：	总52页 (文件大小：665K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADSP-2171KST-104 [ADI]

相关型号：

ADSP-2171KST-133

ADSP-2171_15

ADSP-2172

ADSP-2172BS-104

ADSP-2172BS-133

ADSP-2172BST-104

ADSP-2172BST-133

ADSP-2172KS-104

ADSP-2172KS-133

ADSP-2172KST-104

ADSP-2172KST-133

ADSP-2173