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ADSP-2181 [ADI]

DSP Microcomputer; 微电脑DSP
ADSP-2181
型号： ADSP-2181
厂家： ADI    ADI
描述：

DSP Microcomputer
微电脑DSP

电脑
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中文：  中文翻译
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a
DSP Microcomputer  
ADSP-2181  
FUNCTIO NAL BLO CK D IAGRAM  
FEATURES  
PERFORMANCE  
25 ns Instruction Cycle Tim e from 20 MHz Crystal  
@ 5.0 Volts  
40 MIPS Sustained Perform ance  
Single-Cycle Instruction Execution  
Single-Cycle Context Sw itch  
PROGRAMMABLE  
I/O  
POWER-DOWN  
CONTROL  
FLAGS  
MEMORY  
DATA ADDRESS  
GENERATORS  
PROGRAM  
SEQUENCER  
DATA  
MEMORY  
PROGRAM  
MEMORY  
BYTE DMA  
CONTROLLER  
DAG 1 DAG 2  
EXTERNAL  
ADDRESS  
BUS  
3-Bus Architecture Allow s Dual Operand Fetches in  
Every Instruction Cycle  
Multifunction Instructions  
Pow er-Dow n Mode Featuring Low CMOS Standby  
Pow er Dissipation w ith 100 Cycle Recovery from  
Pow er-Dow n Condition  
PROGRAM MEMORY ADDRESS  
DATA MEMORY ADDRESS  
EXTERNAL  
DATA BUS  
PROGRAM MEMORY DATA  
DATA MEMORY DATA  
DMA BUS  
INTERNAL  
DMA  
PORT  
SERIAL PORTS  
SPORT 0 SPORT 1  
ARITHMETIC UNITS  
ALU MAC SHIFTER  
TIMER  
Low Pow er Dissipation in Idle Mode  
INTEGRATION  
ADSP-2100 Fam ily Code Com patible, w ith Instruction  
Set Extensions  
ADSP-2100 BASE  
ARCHITECTURE  
80K Bytes of On-Chip RAM, Configured as  
16K Words On-Chip Program Mem ory RAM  
16K Words On-Chip Data Mem ory RAM  
Dual Purpose Program Mem ory for Both Instruction  
and Data Storage  
GENERAL D ESCRIP TIO N  
T he ADSP-2181 is a single-chip microcomputer optimized for  
digital signal processing (DSP) and other high speed numeric  
processing applications.  
Independent ALU, Multiplier/ Accum ulator, and Barrel  
Shifter Com putational Units  
Tw o Independent Data Address Generators  
Pow erful Program Sequencer Provides  
Zero Overhead Looping  
Conditional Instruction Execution  
Program m able 16-Bit Interval Tim er w ith Prescaler  
128-Lead TQFP/ 128-Lead PQFP  
T he ADSP-2181 combines the ADSP-2100 family base archi-  
tecture (three computational units, data address generators and  
a program sequencer) with two serial ports, a 16-bit internal  
DMA port, a byte DMA port, a programmable timer, Flag I/O,  
extensive interrupt capabilities, and on-chip program and data  
memory.  
T he ADSP-2181 integrates 80K bytes of on-chip memory con-  
figured as 16K words (24-bit) of program RAM, and 16K words  
(16-bit) of data RAM. Power-down circuitry is also provided to  
meet the low power needs of battery operated portable equip-  
ment. T he ADSP-2181 is available in 128-lead T QFP and 128-  
lead PQFP packages.  
SYSTEM INTERFACE  
16-Bit Internal DMA Port for High Speed Access to  
On-Chip Mem ory  
4 MByte Mem ory Interface for Storage of Data Tables  
and Program Overlays  
8-Bit DMA to Byte Mem ory for Transparent  
Program and Data Mem ory Transfers  
I/ O Mem ory Interface w ith 2048 Locations Supports  
Parallel Peripherals  
Program m able Mem ory Strobe and Separate I/ O Mem ory  
Space Perm its “Glueless” System Design  
Program m able Wait State Generation  
Tw o Double-Buffered Serial Ports w ith Com panding  
Hardw are and Autom atic Data Buffering  
Autom atic Booting of On-Chip Program Mem ory from  
Byte-Wide External Mem ory, e.g., EPROM, or  
Through Internal DMA Port  
In addition, the ADSP-2181 supports new instructions, which  
include bit manipulations—bit set, bit clear, bit toggle, bit test—  
new ALU constants, new multiplication instruction (x squared),  
biased rounding, result free ALU operations, I/O memory trans-  
fers and global interrupt masking for increased flexibility.  
Fabricated in a high speed, double metal, low power, CMOS  
process, the ADSP-2181 operates with a 25 ns instruction cycle  
time. Every instruction can execute in a single processor cycle.  
T he ADSP-2181’s flexible architecture and comprehensive  
instruction set allow the processor to perform multiple opera-  
tions in parallel. In one processor cycle the ADSP-2181 can:  
Six External Interrupts  
13 Program m able Flag Pins Provide Flexible System  
Signaling  
• Generate the next program address  
• Fetch the next instruction  
ICE-Port™ Em ulator Interface Supports Debugging  
in Final System s  
ICE -P or t is a tr adem ar k of Analog D evices, Inc.  
• Perform one or two data moves  
• Update one or two data address pointers  
• Perform a computational operation  
REV. D  
Inform ation furnished by Analog Devices is believed to be accurate and  
reliable. However, no responsibility is assum ed by Analog Devices for its  
use, nor for any infringem ents of patents or other rights of third parties  
which m ay result from its use. No license is granted by im plication or  
otherwise under any patent or patent rights of Analog Devices.  
One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.  
Tel: 781/ 329-4700  
Fax: 781/ 326-8703  
World Wide Web Site: http:/ / w w w .analog.com  
© Analog Devices, Inc., 1998  
ADSP-2181  
T his takes place while the processor continues to:  
Additional Infor m ation  
T his data sheet provides a general overview of ADSP-2181  
functionality. For additional information on the architecture and  
instruction set of the processor, refer to the ADSP-2100 Family  
User’s Manual, Third Edition. For more information about the  
development tools, refer to the ADSP-2100 Family Development  
Tools Data Sheet.  
• Receive and transmit data through the two serial ports  
• Receive and/or transmit data through the internal DMA port  
• Receive and/or transmit data through the byte DMA port  
• Decrement timer  
D evelopm ent System  
T he ADSP-2100 Family Development Software, a complete  
set of tools for software and hardware system development,  
supports the ADSP-2181. T he System Builder provides a high  
level method for defining the architecture of systems under  
development. T he Assembler has an algebraic syntax that is easy  
to program and debug. T he Linker combines object files into  
an executable file. T he Simulator provides an interactive  
instruction-level simulation with a reconfigurable user interface  
to display different portions of the hardware environment. A  
PROM Splitter generates PROM programmer compatible files.  
T he C Compiler, based on the Free Software Foundation’s  
GNU C Compiler, generates ADSP-2181 assembly source  
code. T he source code debugger allows programs to be cor-  
rected in the C environment. The Runtime Library includes over  
100 ANSI-standard mathematical and DSP-specific functions.  
ARCH ITECTURE O VERVIEW  
T he ADSP-2181 instruction set provides flexible data moves  
and multifunction (one or two data moves with a computation)  
instructions. Every instruction can be executed in a single pro-  
cessor cycle. T he ADSP-2181 assembly language uses an alge-  
braic syntax for ease of coding and readability. A comprehensive  
set of development tools supports program development.  
Figure 1 is an overall block diagram of the ADSP-2181. T he  
processor contains three independent computational units: the  
ALU, the multiplier/accumulator (MAC) and the shifter. T he  
computational units process 16-bit data directly and have provi-  
sions to support multiprecision computations. T he ALU per-  
forms a standard set of arithmetic and logic operations; division  
primitives are also supported. T he MAC performs single-cycle  
multiply, multiply/add and multiply/subtract operations with  
40 bits of accumulation. T he shifter performs logical and arith-  
metic shifts, normalization, denormalization and derive expo-  
nent operations. The shifter can be used to efficiently implement  
numeric format control including multiword and block floating-  
point representations.  
T he EZ-KIT Lite is a hardware/software kit offering a complete  
development environment for the entire ADSP-21xx family: an  
ADSP-2181 evaluation board with PC monitor software plus  
Assembler, Linker, Simulator, and PROM Splitter software.  
T he ADSP-218x EZ-KIT Lite is a low-cost, easy to use hard-  
ware platform on which you can quickly get started with your  
DSP software design. T he EZ-KIT Lite includes the following  
features:  
T he internal result (R) bus connects the computational units so  
that the output of any unit may be the input of any unit on the  
next cycle.  
• 33 MHz ADSP-2181  
• Full 16-bit Stereo Audio I/O with AD1847 SoundPort® Codec  
• RS-232 Interface to PC with Windows 3.1 Control Software  
• Stand-Alone Operation with Socketed EPROM  
• EZ-ICE® Connector for Emulator Control  
• DSP Demo Programs  
A powerful program sequencer and two dedicated data address  
generators ensure efficient delivery of operands to these computa-  
tional units. The sequencer supports conditional jumps, subroutine  
calls and returns in a single cycle. With internal loop counters and  
loop stacks, the ADSP-2181 executes looped code with zero over-  
head; no explicit jump instructions are required to maintain loops.  
T he ADSP-218x EZ-ICE Emulator aids in the hardware debug-  
ging of ADSP-218x systems. T he emulator consists of hard-  
ware, host computer resident software and the target board  
connector. T he ADSP-218x integrates on-chip emulation sup-  
port with a 14-pin ICE-Port interface. T his interface provides a  
simpler target board connection requiring fewer mechanical  
clearance considerations than other ADSP-2100 Family EZ-ICEs.  
T he ADSP-218x device need not be removed from the target  
system when using the EZ-ICE, nor are any adapters needed. Due  
to the small footprint of the EZ-ICE connector, emulation can be  
supported in final board designs.  
T wo data address generators (DAGs) provide addresses for  
simultaneous dual operand fetches (from data memory and  
program memory). Each DAG maintains and updates four  
address pointers. Whenever the pointer is used to access data  
(indirect addressing), it is post-modified by the value of one of  
four possible modify registers. A length value may be associated  
with each pointer to implement automatic modulo addressing  
for circular buffers.  
Efficient data transfer is achieved with the use of five internal  
buses:  
T he EZ-ICE performs a full range of functions, including:  
• Program Memory Address (PMA) Bus  
• Program Memory Data (PMD) Bus  
• Data Memory Address (DMA) Bus  
• Data Memory Data (DMD) Bus  
• Result (R) Bus  
• In-target operation  
• Up to 20 breakpoints  
• Single-step or full-speed operation  
• Registers and memory values can be examined and altered  
• PC upload and download functions  
• Instruction-level emulation of program booting and execution  
• Complete assembly and disassembly of instructions  
• C source-level debugging  
T he two address buses (PMA and DMA) share a single external  
address bus, allowing memory to be expanded off-chip, and the  
two data buses (PMD and DMD) share a single external data  
bus. Byte memory space and I/O memory space also share the  
external buses.  
See the Designing An EZ-ICE-Compatible T arget System sec-  
tion of this data sheet for exact specifications of the EZ-ICE target  
board connector.  
Program memory can store both instructions and data, permit-  
ting the ADSP-2181 to fetch two operands in a single cycle,  
one from program memory and one from data memory. T he  
EZ-ICE and SoundPort are registered trademarks of Analog Devices, Inc.  
REV. D  
–2–  
ADSP-2181  
ADSP-2181 can fetch an operand from program memory and  
the next instruction in the same cycle.  
T he ADSP-2181 provides up to 13 general-purpose flag pins.  
T he data input and output pins on SPORT 1 can be alternatively  
configured as an input flag and an output flag. In addition, there  
are eight flags that are programmable as inputs or outputs and  
three flags that are always outputs.  
In addition to the address and data bus for external memory  
connection, the ADSP-2181 has a 16-bit Internal DMA port  
(IDMA port) for connection to external systems. T he IDMA  
port is made up of 16 data/address pins and five control pins.  
T he IDMA port provides transparent, direct access to the DSPs  
on-chip program and data RAM.  
A programmable interval timer generates periodic interrupts. A  
16-bit count register (T COUNT ) is decremented every n pro-  
cessor cycles, where n is a scaling value stored in an 8-bit regis-  
ter (T SCALE). When the value of the count register reaches  
zero, an interrupt is generated and the count register is reloaded  
from a 16-bit period register (T PERIOD).  
An interface to low cost byte-wide memory is provided by the  
Byte DMA port (BDMA port). T he BDMA port is bidirectional  
and can directly address up to four megabytes of external RAM  
or ROM for off-chip storage of program overlays or data tables.  
Ser ial P or ts  
T he ADSP-2181 incorporates two complete synchronous serial  
ports (SPORT 0 and SPORT 1) for serial communications and  
multiprocessor communication.  
The byte memory and I/O memory space interface supports slow  
memories and I/O memory-mapped peripherals with program-  
mable wait state generation. External devices can gain control of  
external buses with bus request/grant signals (BR, BGH and BG).  
One execution mode (Go Mode) allows the ADSP-2181 to con-  
tinue running from on-chip memory. Normal execution mode  
requires the processor to halt while buses are granted.  
Here is a brief list of the capabilities of the ADSP-2181 SPORTs.  
Refer to the ADSP-2100 Family User’s Manual, Third Edition for  
further details.  
• SPORT s are bidirectional and have a separate, double-  
buffered transmit and receive section.  
T he ADSP-2181 can respond to 13 possible interrupts, eleven  
of which are accessible at any given time. T here can be up to six  
external interrupts (one edge-sensitive, two level-sensitive and  
three configurable) and seven internal interrupts generated by  
the timer, the serial ports (SPORT s), the Byte DMA port and  
the power-down circuitry. T here is also a master RESET signal.  
• SPORT s can use an external serial clock or generate their  
own serial clock internally.  
• SPORT s have independent framing for the receive and trans-  
mit sections. Sections run in a frameless mode or with frame  
synchronization signals internally or externally generated.  
Frame sync signals are active high or inverted, with either of  
two pulsewidths and timings.  
The two serial ports provide a complete synchronous serial inter-  
face with optional companding in hardware and a wide variety of  
framed or frameless data transmit and receive modes of operation.  
Each port can generate an internal programmable serial clock or  
accept an external serial clock.  
21xx CORE  
ADSP-2181 INTEGRATION  
POWER-  
DOWN  
2
CONTROL  
LOGIC  
INSTRUCTION  
REGISTER  
PROGRAM  
SRAM  
16K 
؋
 24  
DATA  
SRAM  
16K 
؋
 16  
8
BYTE  
DMA  
CONTROLLER  
PROGRAMMABLE  
I/O  
DATA  
ADDRESS  
GENERATOR  
#2  
DATA  
ADDRESS  
GENERATOR  
#1  
3
PROGRAM  
SEQUENCER  
FLAGS  
PMA BUS  
DMA BUS  
14  
14  
PMA BUS  
14  
MUX  
DMA BUS  
EXTERNAL  
ADDRESS  
BUS  
PMD BUS  
DMD BUS  
24  
PMD BUS  
EXTERNAL  
DATA  
BUS  
BUS  
EXCHANGE  
MUX  
DMD  
BUS  
24  
16  
INPUT REGS  
INPUT REGS  
INPUT REGS  
SHIFTER  
COMPANDING  
CIRCUITRY  
16  
INTERNAL  
DMA  
PORT  
ALU  
MAC  
TIMER  
TRANSMIT REG  
TRANSMIT REG  
OUTPUT REGS  
OUTPUT REGS  
OUTPUT REGS  
RECEIVE REG  
RECEIVE REG  
4
SERIAL  
PORT 0  
SERIAL  
PORT 0  
16  
INTERRUPTS  
R BUS  
5
5
Figure 1. ADSP-2181 Block Diagram  
–3–  
REV. D  
ADSP-2181  
• SPORT s support serial data word lengths from 3 to 16 bits  
and provide optional A-law and µ-law companding according  
to CCIT T recommendation G.711.  
#
of  
P ins  
P in  
Nam e(s)  
Input/  
O utput Function  
• SPORT receive and transmit sections can generate unique  
interrupts on completing a data word transfer.  
CLKOUT  
SPORT 0  
SPORT 1  
1
5
5
O
Processor Clock Output  
I/O  
I/O  
Serial Port I/O Pins  
• SPORT s can receive and transmit an entire circular buffer of  
data with only one overhead cycle per data word. An interrupt  
is generated after a data buffer transfer.  
Serial Port 1 or T wo External  
IRQs, Flag In and Flag Out  
IRD, IWR  
IS  
2
1
1
I
I
I
IDMA Port Read/Write Inputs  
IDMA Port Select  
• SPORT 0 has a multichannel interface to selectively receive  
and transmit a 24- or 32-word, time-division multiplexed,  
serial bitstream.  
IAL  
IDMA Port Address Latch  
Enable  
• SPORT 1 can be configured to have two external interrupts  
(IRQ0 and IRQ1) and the Flag In and Flag Out signals. T he  
internally generated serial clock may still be used in this  
configuration.  
IAD  
16  
1
I/O  
O
IDMA Port Address/Data Bus  
IACK  
IDMA Port Access Ready  
Acknowledge  
PWD  
1
1
I
Power-Down Control  
Power-Down Control  
P in D escr iptions  
T he ADSP-2181 is available in 128-lead T QFP and 128-lead  
PQFP packages.  
PWDACK  
O
FL0, FL1,  
FL2  
3
8
1
1
1
1
1
1
1
1
1
11  
6
O
I/O  
*
Output Flags  
P IN FUNCTIO N D ESCRIP TIO NS  
#
PF7:0  
EE  
Programmable I/O Pins  
(Emulator Only*)  
(Emulator Only*)  
(Emulator Only*)  
(Emulator Only*)  
(Emulator Only*)  
(Emulator Only*)  
(Emulator Only*)  
(Emulator Only*)  
(Emulator Only*)  
Ground Pins  
P in  
of  
Input/  
O utput Function  
EBR  
*
Nam e(s)  
P ins  
EBG  
*
Address  
14  
O
Address Output Pins for Program,  
Data, Byte, and I/ O Spaces  
Data I/O Pins for Program and  
Data Memory Spaces (8 MSBs  
Are Also Used as Byte Space  
Addresses)  
ERESET  
EMS  
*
*
Data  
24  
I/O  
EINT  
ECLK  
ELIN  
ELOUT  
GND  
VDD  
*
*
*
RESET  
IRQ2  
1
1
I
I
Processor Reset Input  
*
Edge- or Level-Sensitive  
Interrupt Request  
–
–
Power Supply Pins  
IRQL0,  
IRQL1  
*T hese ADSP-2181 pins must be connected only to the EZ-ICE connector in  
the target system. T hese pins have no function except during emulation, and  
do not require pull-up or pull-down resistors.  
2
1
I
I
Level-Sensitive Interrupt  
Requests  
IRQE  
Edge-Sensitive Interrupt  
Request  
Inter r upts  
T he interrupt controller allows the processor to respond to the  
eleven possible interrupts and reset with minimum overhead.  
T he ADSP-2181 provides four dedicated external interrupt  
input pins, IRQ2, IRQL0, IRQL1 and IRQE. In addition,  
SPORT 1 may be reconfigured for IRQ0, IRQ1, FLAG_IN and  
FLAG_OUT , for a total of six external interrupts. T he ADSP-  
2181 also supports internal interrupts from the timer, the byte  
DMA port, the two serial ports, software and the power-down  
control circuit. T he interrupt levels are internally prioritized and  
individually maskable (except power down and reset). T he  
IRQ2, IRQ0 and IRQ1 input pins can be programmed to be  
either level- or edge-sensitive. IRQL0 and IRQL1 are level-  
sensitive and IRQE is edge sensitive. T he priorities and vector  
addresses of all interrupts are shown in T able I.  
BR  
1
1
1
1
1
1
1
1
1
1
1
1
I
Bus Request Input  
BG  
O
O
O
O
O
O
O
O
O
I
Bus Grant Output  
BGH  
PMS  
DMS  
BMS  
IOMS  
CMS  
RD  
Bus Grant Hung Output  
Program Memory Select Output  
Data Memory Select Output  
Byte Memory Select Output  
I/O Space Memory Select Output  
Combined Memory Select Output  
Memory Read Enable Output  
Memory Write Enable Output  
Memory Map Select Input  
Boot Option Control Input  
WR  
MMAP  
BMODE  
I
CLKIN,  
XT AL  
2
I
Clock or Quartz Crystal Input  
REV. D  
–4–  
ADSP-2181  
Table I. Interrupt P riority and Interrupt Vector Addresses  
Interrupt Vector  
P ower -D own  
T he ADSP-2181 processor has a low power feature that lets  
the processor enter a very low power dormant state through  
hardware or software control. Here is a brief list of power-  
down features. For detailed information about the power-  
down feature, refer to the ADSP-2100 Family User’s Manual,  
Third Edition, “System Interface” chapter.  
Source of Interrupt  
Address (H ex)  
Reset (or Power-Up with PUCR = 1) 0000 (Highest Priority)  
Power-Down (Nonmaskable)  
IRQ2  
002C  
0004  
IRQL1  
IRQL0  
0008  
000C  
• Quick recovery from power-down. T he processor begins  
executing instructions in as few as 100 CLKIN cycles.  
SPORT 0 T ransmit  
SPORT 0 Receive  
IRQE  
BDMA Interrupt  
SPORT 1 T ransmit or IRQ1  
SPORT 1 Receive or IRQ0  
T imer  
0010  
0014  
0018  
001C  
0020  
0024  
• Support for an externally generated T T L or CMOS  
processor clock. T he external clock can continue running  
during power-down without affecting the lowest power  
rating and 100 CLKIN cycle recovery.  
• Support for crystal operation includes disabling the oscil-  
lator to save power (the processor automatically waits 4096  
CLKIN cycles for the crystal oscillator to start and stabi-  
lize), and letting the oscillator run to allow 100 CLKIN  
cycle start up.  
0028 (Lowest Priority)  
Interrupt routines can either be nested with higher priority  
interrupts taking precedence or processed sequentially. Inter-  
rupts can be masked or unmasked with the IMASK register.  
Individual interrupt requests are logically ANDed with the bits  
in IMASK; the highest priority unmasked interrupt is then  
selected. T he power-down interrupt is nonmaskable.  
• Power-down is initiated by either the power-down pin  
(PWD) or the software power-down force bit.  
• Interrupt support allows an unlimited number of instruc-  
tions to be executed before optionally powering down.  
T he power-down interrupt also can be used as a non-  
maskable, edge-sensitive interrupt.  
T he ADSP-2181 masks all interrupts for one instruction cycle  
following the execution of an instruction that modifies the  
IMASK register. T his does not affect serial port autobuffering  
or DMA transfers.  
• Context clear/save control allows the processor to con-  
tinue where it left off or start with a clean context when  
leaving the power-down state.  
T he interrupt control register, ICNT L, controls interrupt nest-  
ing and defines the IRQ0, IRQ1 and IRQ2 external interrupts to  
be either edge- or level-sensitive. T he IRQE pin is an external  
edge-sensitive interrupt and can be forced and cleared. T he  
IRQL0 and IRQL1 pins are external level-sensitive interrupts.  
• T he RESET pin also can be used to terminate power-  
down.  
• Power-down acknowledge pin indicates when the proces-  
sor has entered power-down.  
T he IFC register is a write-only register used to force and clear  
interrupts.  
Idle  
When the ADSP-2181 is in the Idle Mode, the processor  
waits indefinitely in a low power state until an interrupt  
occurs. When an unmasked interrupt occurs, it is serviced;  
execution then continues with the instruction following the  
IDLE instruction.  
On-chip stacks preserve the processor status and are automati-  
cally maintained during interrupt handling. The stacks are twelve  
levels deep to allow interrupt, loop and subroutine nesting.  
T he following instructions allow global enable or disable servic-  
ing of the interrupts (including power down), regardless of the  
state of IMASK. Disabling the interrupts does not affect serial  
port autobuffering or DMA.  
Slow Idle  
T he IDLE instruction is enhanced on the ADSP-2181 to let  
the processor’s internal clock signal be slowed, further  
reducing power consumption. T he reduced clock fre-  
quency, a programmable fraction of the normal clock rate,  
is specified by a selectable divisor given in the IDLE in-  
struction. T he format of the instruction is  
ENA INTS;  
DIS INTS;  
When the processor is reset, interrupt servicing is enabled.  
LO W P O WER O P ERATIO N  
IDLE (n);  
T he ADSP-2181 has three low power modes that significantly  
reduce the power dissipation when the device operates under  
standby conditions. T hese modes are:  
where n = 16, 32, 64 or 128. T his instruction keeps the  
processor fully functional, but operating at the slower clock  
rate. While it is in this state, the processor’s other internal  
clock signals, such as SCLK, CLKOUT and timer clock,  
are reduced by the same ratio. T he default form of the  
instruction, when no clock divisor is given, is the standard  
IDLE instruction.  
• Power-Down  
• Idle  
• Slow Idle  
T he CLKOUT pin may also be disabled to reduce external  
power dissipation.  
REV. D  
–5–  
ADSP-2181  
When the IDLE (n) instruction is used, it effectively slows down  
the processor’s internal clock and thus its response time to in-  
coming interrupts. T he one-cycle response time of the standard  
idle state is increased by n, the clock divisor. When an enabled  
interrupt is received, the ADSP-2181 will remain in the idle  
state for up to a maximum of n processor cycles (n = 16, 32, 64  
or 128) before resuming normal operation.  
If an external clock is used, it should be a T T L-compatible  
signal running at half the instruction rate. T he signal is con-  
nected to the processor’s CLKIN input. When an external clock  
is used, the XT AL input must be left unconnected.  
T he ADSP-2181 uses an input clock with a frequency equal to  
half the instruction rate; a 20.00 MHz input clock yields a 25 ns  
processor cycle (which is equivalent to 40 MHz). Normally,  
instructions are executed in a single processor cycle. All device  
timing is relative to the internal instruction clock rate, which is  
indicated by the CLKOUT signal when enabled.  
When the IDLE (n) instruction is used in systems that have an  
externally generated serial clock (SCLK), the serial clock rate  
may be faster than the processor’s reduced internal clock rate.  
Under these conditions, interrupts must not be generated at a  
faster rate than can be serviced, due to the additional time the  
processor takes to come out of the idle state (a maximum of n  
processor cycles).  
Because the ADSP-2181 includes an on-chip oscillator circuit,  
an external crystal may be used. The crystal should be connected  
across the CLKIN and XTAL pins, with two capacitors connected  
as shown in Figure 3. Capacitor values are dependent on crystal  
type and should be specified by the crystal manufacturer. A  
parallel-resonant, fundamental frequency, microprocessor-grade  
crystal should be used.  
SYSTEM INTERFACE  
Figure 2 shows a typical basic system configuration with the  
ADSP-2181, two serial devices, a byte-wide EPROM, and op-  
tional external program and data overlay memories. Program-  
mable wait state generation allows the processor to connect  
easily to slow peripheral devices. T he ADSP-2181 also provides  
four external interrupts and two serial ports or six external inter-  
rupts and one serial port.  
A clock output (CLKOUT ) signal is generated by the processor  
at the processor’s cycle rate. T his can be enabled and disabled  
by the CLKODIS bit in the SPORT 0 Autobuffer Control  
Register.  
ADSP-2181  
CLKIN  
A
D
13-0  
1/2x CLOCK  
OR  
CLKIN  
XTAL  
CLKOUT  
14  
ADDR13-0  
XTAL  
CRYSTAL  
A0-A21  
23-16  
DSP  
FL0-2  
PF0-7  
BYTE  
MEMORY  
D
15-8  
24  
DATA23-0  
DATA  
IRQ2  
IRQE  
IRQL0  
IRQL1  
CS  
BMS  
A
Figure 3. External Crystal Connections  
10-0  
RD  
WR  
ADDR  
DATA  
D
23-8  
SPORT1  
SCLK1  
RFS1 OR IRQ0  
TFS1 OR IRQ1  
DT1 OR FO  
DR1 OR FI  
Reset  
I/O SPACE  
(PERIPHERALS)  
2048 LOCATIONS  
T he RESET signal initiates a master reset of the ADSP-2181.  
T he RESET signal must be asserted during the power-up se-  
quence to assure proper initialization. RESET during initial  
power-up must be held long enough to allow the internal clock  
to stabilize. If RESET is activated any time after power-up, the  
clock continues to run and does not require stabilization time.  
SERIAL  
DEVICE  
CS  
IOMS  
A
13-0  
ADDR  
DATA  
OVERLAY  
MEMORY  
D
SPORT0  
SCLK0  
RFS0  
TFS0  
DT0  
23-0  
SERIAL  
DEVICE  
TWO 8K  
PM SEGMENTS  
PMS  
DMS  
CMS  
DR0  
TWO 8K  
DM SEGMENTS  
IDMA PORT  
BR  
BG  
BGH  
T he power-up sequence is defined as the total time required for  
the crystal oscillator circuit to stabilize after a valid VDD is ap-  
plied to the processor, and for the internal phase-locked loop  
(PLL) to lock onto the specific crystal frequency. A minimum of  
2000 CLKIN cycles ensures that the PLL has locked, but does  
not include the crystal oscillator start-up time. During this  
power-up sequence the RESET signal should be held low. On  
any subsequent resets, the RESET signal must meet the mini-  
IRD  
SYSTEM  
INTERFACE  
OR  
IWR  
IS  
PWD  
IAL  
IACK  
IAD15-0  
␮CONTROLLER  
PWDACK  
16  
Figure 2. ADSP-2181 Basic System Configuration  
Clock Signals  
T he ADSP-2181 can be clocked by either a crystal or a T T L-  
compatible clock signal.  
mum pulse width specification, tRSP  
.
T he CLKIN input cannot be halted, changed during operation  
or operated below the specified frequency during normal opera-  
tion. T he only exception is while the processor is in the power-  
down state. For additional information, refer to Chapter 9,  
ADSP-2100 Family User’s Manual, Third Edition, for detailed  
information on this power-down feature.  
T he RESET input contains some hysteresis; however, if you use  
an RC circuit to generate your RESET signal, the use of an  
external Schmidt trigger is recommended.  
T he master reset sets all internal stack pointers to the empty  
stack condition, masks all interrupts and clears the MST AT  
register. When RESET is released, if there is no pending bus  
request and the chip is configured for booting (MMAP = 0), the  
boot-loading sequence is performed. T he first instruction is  
fetched from on-chip program memory location 0x0000 once  
boot loading completes.  
REV. D  
–6–  
ADSP-2181  
Table II.  
P MO VLAY Mem ory A13  
Mem or y Ar chitectur e  
T he ADSP-2181 provides a variety of memory and peripheral  
interface options. T he key functional groups are Program  
Memory, Data Memory, Byte Memory and I/O.  
A12:0  
0
1
Internal  
Not Applicable Not Applicable  
P r ogr am Mem or y is a 24-bit-wide space for storing both  
instruction opcodes and data. T he ADSP-2181 has 16K words  
of Program Memory RAM on chip and the capability of access-  
ing up to two 8K external memory overlay spaces using the  
external data bus. Both an instruction opcode and a data value  
can be read from on-chip program memory in a single cycle.  
External  
Overlay 1  
0
1
13 LSBs of Address  
Between 0x2000  
and 0x3FFF  
2
External  
13 LSBs of Address  
Between 0x2000  
and 0x3FFF  
Overlay 2  
D ata Mem or y is a 16-bit-wide space used for the storage of  
data variables and for memory-mapped control registers. T he  
ADSP-2181 has 16K words on Data Memory RAM on chip,  
consisting of 16,352 user-accessible locations and 32 memory-  
mapped registers. Support also exists for up to two 8K external  
memory overlay spaces through the external data bus.  
T his organization provides for two external 8K overlay segments  
using only the normal 14 address bits. T his allows for simple  
program overlays using one of the two external segments in  
place of the on-chip memory. Care must be taken in using this  
overlay space in that the processor core (i.e., the sequencer)  
does not take into account the PMOVLAY register value. For  
example, if a loop operation was occurring on one of the exter-  
nal overlays and the program changes to another external over-  
lay or internal memory, an incorrect loop operation could occur.  
In addition, care must be taken in interrupt service routines as  
the overlay registers are not automatically saved and restored on  
the processor mode stack.  
Byte Mem or y provides access to an 8-bit wide memory space  
through the Byte DMA (BDMA) port. T he Byte Memory inter-  
face provides access to 4 MBytes of memory by utilizing eight  
data lines as additional address lines. T his gives the BDMA Port  
an effective 22-bit address range. On power-up, the DSP can  
automatically load bootstrap code from byte memory.  
I/O Space allows access to 2048 locations of 16-bit-wide data.  
It is intended to be used to communicate with parallel periph-  
eral devices such as data converters and external registers or  
latches.  
For ADSP-2100 Family compatibility, MMAP = 1 is allowed.  
In this mode, booting is disabled and overlay memory is dis-  
abled (PMOVLAY must be 0). Figure 5 shows the memory map  
in this configuration.  
P r ogr am Mem or y  
T he ADSP-2181 contains a 16K × 24 on-chip program RAM.  
T he on-chip program memory is designed to allow up to two  
accesses each cycle so that all operations can complete in a  
single cycle. In addition, the ADSP-2181 allows the use of 8K  
external memory overlays.  
PROGRAM MEMORY  
ADDRESS  
0x3FFF  
INTERNAL 8K  
(PMOVLAY = 0,  
MMAP = 1)  
0x2000  
0x1FFF  
T he program memory space organization is controlled by the  
MMAP pin and the PMOVLAY register. Normally, the ADSP-  
2181 is configured with MMAP = 0 and program memory orga-  
nized as shown in Figure 4.  
8K EXTERNAL  
0x0000  
PROGRAM MEMORY  
ADDRESS  
0x3FFF  
Figure 5. Program Mem ory (MMAP = 1)  
D ata Mem or y  
T he ADSP-2181 has 16,352 16-bit words of internal data  
memory. In addition, the ADSP-2181 allows the use of 8K  
external memory overlays. Figure 6 shows the organization of  
the data memory.  
8K INTERNAL  
(PMOVLAY = 0,  
MMAP = 0)  
OR  
EXTERNAL 8K  
(PMOVLAY = 1 or 2,  
MMAP = 0)  
0x2000  
0x1FFF  
DATA MEMORY  
ADDRESS  
0x3FFF  
8K INTERNAL  
32 MEMORY–  
MAPPED REGISTERS  
0x0000  
0x3FEO  
0x3FDF  
Figure 4. Program Mem ory (MMAP = 0)  
INTERNAL  
8160 WORDS  
T here are 16K words of memory accessible internally when the  
PMOVLAY register is set to 0. When PMOVLAY is set to  
something other than 0, external accesses occur at addresses  
0x2000 through 0x3FFF. T he external address is generated as  
shown in T able II.  
0x2000  
0x1FFF  
8K INTERNAL  
(DMOVLAY = 0)  
OR  
EXTERNAL 8K  
(DMOVLAY = 1, 2)  
0x0000  
Figure 6. Data Mem ory  
REV. D  
–7–  
ADSP-2181  
T here are 16,352 words of memory accessible internally when  
the DMOVLAY register is set to 0. When DMOVLAY is set to  
something other than 0, external accesses occur at addresses  
0x0000 through 0x1FFF. T he external address is generated as  
shown in T able III.  
T he CMS pin functions like the other memory select signals,  
with the same timing and bus request logic. A 1 in the enable bit  
causes the assertion of the CMS signal at the same time as the  
selected memory select signal. All enable bits, except the BMS  
bit, default to 1 at reset.  
Byte Mem or y  
Table III.  
T he byte memory space is a bidirectional, 8-bit-wide, external  
memory space used to store programs and data. Byte memory is  
accessed using the BDMA feature. T he byte memory space  
consists of 256 pages, each of which is 16K × 8.  
D MO VLAY Mem ory A13  
A12:0  
0
1
Internal  
Not Applicable Not Applicable  
External  
Overlay 1  
0
1
13 LSBs of Address  
Between 0x0000  
and 0x1FFF  
T he byte memory space on the ADSP-2181 supports read and  
write operations as well as four different data formats. T he byte  
memory uses data bits 15:8 for data. T he byte memory uses  
data bits 23:16 and address bits 13:0 to create a 22-bit address.  
T his allows up to a 4 meg × 8 (32 megabit) ROM or RAM to be  
used without glue logic. All byte memory accesses are timed by  
the BMWAIT register.  
2
External  
13 LSBs of Address  
Between 0x0000  
and 0x1FFF  
Overlay 2  
T his organization allows for two external 8K overlays using only  
the normal 14 address bits.  
Byte Mem or y D MA (BD MA)  
T he Byte memory DMA controller allows loading and storing of  
program instructions and data using the byte memory space.  
T he BDMA circuit is able to access the byte memory space  
while the processor is operating normally, and steals only one  
DSP cycle per 8-, 16- or 24-bit word transferred.  
All internal accesses complete in one cycle. Accesses to external  
memory are timed using the wait states specified by the DWAIT  
register.  
I/O Space  
T he BDMA circuit supports four different data formats which  
are selected by the BT YPE register field. T he appropriate num-  
ber of 8-bit accesses are done from the byte memory space to  
build the word size selected. T able V shows the data formats  
supported by the BDMA circuit.  
T he ADSP-2181 supports an additional external memory space  
called I/O space. T his space is designed to support simple con-  
nections to peripherals or to bus interface ASIC data registers.  
I/O space supports 2048 locations. T he lower eleven bits of the  
external address bus are used; the upper three bits are unde-  
fined. T wo instructions were added to the core ADSP-2100  
Family instruction set to read from and write to I/O memory  
space. T he I/O space also has four dedicated 3-bit wait state  
registers, IOWAIT 0-3, which specify up to seven wait states to  
be automatically generated for each of four regions. T he wait  
states act on address ranges as shown in T able IV.  
Table V.  
Internal  
BTYP E  
Mem ory Space  
Word Size  
Alignm ent  
00  
01  
10  
11  
Program Memory  
Data Memory  
Data Memory  
Data Memory  
24  
16  
8
Full Word  
Full Word  
MSBs  
Table IV.  
8
LSBs  
Address Range  
Wait State Register  
Unused bits in the 8-bit data memory formats are filled with 0s.  
T he BIAD register field is used to specify the starting address  
for the on-chip memory involved with the transfer. T he 14-bit  
BEAD register specifies the starting address for the external byte  
memory space. T he 8-bit BMPAGE register specifies the start-  
ing page for the external byte memory space. T he BDIR register  
field selects the direction of the transfer. Finally the 14-bit  
BWCOUNT register specifies the number of DSP words to  
transfer and initiates the BDMA circuit transfers.  
0x000–0x1FF  
0x200–0x3FF  
0x400–0x5FF  
0x600–0x7FF  
IOWAIT 0  
IOWAIT 1  
IOWAIT 2  
IOWAIT 3  
Com posite Mem or y Select (CMS)  
T he ADSP-2181 has a programmable memory select signal that  
is useful for generating memory select signals for memories  
mapped to more than one space. T he CMS signal is generated  
to have the same timing as each of the individual memory select  
signals (PMS, DMS, BMS, IOMS) but can combine their  
functionality.  
BDMA accesses can cross page boundaries during sequential  
addressing. A BDMA interrupt is generated on the completion  
of the number of transfers specified by the BWCOUNT register.  
T he BWCOUNT register is updated after each transfer so it can  
be used to check the status of the transfers. When it reaches  
zero, the transfers have finished and a BDMA interrupt is gener-  
ated. T he BMPAGE and BEAD registers must not be accessed  
by the DSP during BDMA operations.  
When set, each bit in the CMSSEL register, causes the CMS  
signal to be asserted when the selected memory select is as-  
serted. For example, to use a 32K word memory to act as both  
program and data memory, set the PMS and DMS bits in the  
CMSSEL register and use the CMS pin to drive the chip select  
of the memory; use either DMS or PMS as the additional  
address bit.  
T he source or destination of a BDMA transfer will always be  
on-chip program or data memory, regardless of the values of  
MMAP, PMOVLAY or DMOVLAY.  
REV. D  
–8–  
ADSP-2181  
When the BWCOUNT register is written with a nonzero value,  
the BDMA circuit starts executing byte memory accesses with  
wait states set by BMWAIT . T hese accesses continue until the  
count reaches zero. When enough accesses have occurred to  
create a destination word, it is transferred to or from on-chip  
memory. T he transfer takes one DSP cycle. DSP accesses to  
external memory have priority over BDMA byte memory ac-  
cesses.  
Table VI. Boot Sum m ary Table  
MMAP BMO D E  
Booting Method  
0
0
BDMA feature is used in default mode  
to load the first 32 program memory  
words from the byte memory space.  
Program execution is held off until all  
32 words have been loaded.  
T he BDMA Context Reset bit (BCR) controls whether the  
processor is held off while the BDMA accesses are occurring.  
Setting the BCR bit to 0 allows the processor to continue opera-  
tions. Setting the BCR bit to 1 causes the processor to stop  
execution while the BDMA accesses are occurring, to clear the  
context of the processor and start execution at address 0 when  
the BDMA accesses have completed.  
0
1
1
IDMA feature is used to load any inter-  
nal memory as desired. Program execu-  
tion is held off until internal program  
memory location 0 is written to.  
X
Bootstrap features disabled. Program  
execution immediately starts from  
location 0.  
Inter nal Mem or y D MA P or t (ID MA P or t)  
T he IDMA Port provides an efficient means of communication  
between a host system and the ADSP-2181. T he port is used to  
access the on-chip program memory and data memory of the  
DSP with only one DSP cycle per word overhead. T he IDMA  
port cannot, however, be used to write to the DSP’s memory-  
mapped control registers.  
BDMA Booting  
When the BMODE and MMAP pins specify BDMA booting  
(MMAP = 0, BMODE = 0), the ADSP-2181 initiates a BDMA  
boot sequence when reset is released. T he BDMA interface is  
set up during reset to the following defaults when BDMA boot-  
ing is specified: the BDIR, BMPAGE, BIAD and BEAD regis-  
ters are set to 0, the BT YPE register is set to 0 to specify  
program memory 24 bit words, and the BWCOUNT register is  
set to 32. T his causes 32 words of on-chip program memory to  
be loaded from byte memory. T hese 32 words are used to set up  
the BDMA to load in the remaining program code. T he BCR  
bit is also set to 1, which causes program execution to be held  
off until all 32 words are loaded into on-chip program memory.  
Execution then begins at address 0.  
T he IDMA port has a 16-bit multiplexed address and data bus  
and supports 24-bit program memory. T he IDMA port is  
completely asynchronous and can be written to while the  
ADSP-2181 is operating at full speed.  
T he DSP memory address is latched and then automatically  
incremented after each IDMA transaction. An external device  
can therefore access a block of sequentially addressed memory  
by specifying only the starting address of the block. T his in-  
creases throughput as the address does not have to be sent for  
each memory access.  
T he ADSP-2100 Family Development Software (Revision 5.02  
and later) fully supports the BDMA booting feature and can  
generate byte memory space compatible boot code.  
IDMA Port access occurs in two phases. T he first is the IDMA  
Address Latch cycle. When the acknowledge is asserted, a 14-  
bit address and 1-bit destination type can be driven onto the bus  
by an external device. T he address specifies an on-chip memory  
location; the destination type specifies whether it is a DM or  
PM access. T he falling edge of the address latch signal latches  
this value into the IDMAA register.  
T he IDLE instruction can also be used to allow the processor to  
hold off execution while booting continues through the BDMA  
interface.  
IDMA Booting  
T he ADSP-2181 can also boot programs through its Internal  
DMA port. If BMODE = 1 and MMAP = 0, the ADSP-2181  
boots from the IDMA port. IDMA feature can load as much on-  
chip memory as desired. Program execution is held off until on-  
chip program memory location 0 is written to.  
Once the address is stored, data can either be read from or  
written to the ADSP-2181’s on-chip memory. Asserting the  
select line (IS) and the appropriate read or write line (IRD and  
IWR respectively) signals the ADSP-2181 that a particular  
transaction is required. In either case, there is a one-processor-  
cycle delay for synchronization. T he memory access consumes  
one additional processor cycle.  
T he ADSP-2100 Family Development Software (Revision 5.02  
and later) can generate IDMA compatible boot code.  
Bus Request and Bus Gr ant  
T he ADSP-2181 can relinquish control of the data and address  
buses to an external device. When the external device requires  
access to memory, it asserts the bus request (BR) signal. If the  
ADSP-2181 is not performing an external memory access, then  
it responds to the active BR input in the following processor  
cycle by:  
Once an access has occurred, the latched address is automati-  
cally incremented and another access can occur.  
T hrough the IDMAA register, the DSP can also specify the  
starting address and data format for DMA operation.  
Bootstr ap Loading (Booting)  
T he ADSP-2181 has two mechanisms to allow automatic load-  
ing of the on-chip program memory after reset. T he method for  
booting after reset is controlled by the MMAP and BMODE  
pins as shown in T able VI.  
• three-stating the data and address buses and the PMS, DMS,  
BMS, CMS, IOMS, RD, WR output drivers,  
• asserting the bus grant (BG) signal, and  
• halting program execution.  
REV. D  
–9–  
ADSP-2181  
• Multifunction instructions allow parallel execution of an  
arithmetic instruction with up to two fetches or one write to  
processor memory space during a single instruction cycle.  
If Go Mode is enabled, the ADSP-2181 will not halt program  
execution until it encounters an instruction that requires an  
external memory access.  
If the ADSP-2181 is performing an external memory access  
when the external device asserts the BR signal, then it will not  
three-state the memory interfaces or assert the BG signal until  
the processor cycle after the access completes. T he instruction  
does not need to be completed when the bus is granted. If a  
single instruction requires two external memory accesses, the  
bus will be granted between the two accesses.  
D ESIGNING AN EZ-ICE-CO MP ATIBLE SYSTEM  
T he ADSP-2181 has on-chip emulation support and an ICE-  
Port, a special set of pins that interface to the EZ-ICE. T hese  
features allow in-circuit emulation without replacing the target  
system processor by using only a 14-pin connection from the  
target system to the EZ-ICE. T arget systems must have a 14-pin  
connector to accept the EZ-ICE ’s in-circuit probe, a 14-pin plug.  
When the BR signal is released, the processor releases the BG  
signal, reenables the output drivers and continues program  
execution from the point where it stopped.  
The ICE-Port interface consists of the following ADSP-2181 pins:  
EBR  
EMS  
ELIN  
ELOUT  
EE  
EBG  
ERESET  
EINT  
ECLK  
T he bus request feature operates at all times, including when  
the processor is booting and when RESET is active.  
T hese ADSP-2181 pins must be connected only to the EZ-ICE  
connector in the target system. T hese pins have no function  
except during emulation, and do not require pull-up or pull-  
down resistors. T he traces for these signals between the ADSP-  
2181 and the connector must be kept as short as possible, no  
longer than three inches.  
T he BGH pin is asserted when the ADSP-2181 is ready to  
execute an instruction, but is stopped because the external bus  
is already granted to another device. T he other device can re-  
lease the bus by deasserting bus request. Once the bus is re-  
leased, the ADSP-2181 deasserts BG and BGH and executes  
the external memory access.  
T he following pins are also used by the EZ-ICE:  
Flag I/O P ins  
BR  
BG  
T he ADSP-2181 has eight general purpose programmable in-  
put/output flag pins. T hey are controlled by two memory  
mapped registers. T he PFT YPE register determines the direc-  
tion, 1 = output and 0 = input. T he PFDAT A register is used to  
read and write the values on the pins. Data being read from a  
pin configured as an input is synchronized to the ADSP-2181’s  
clock. Bits that are programmed as outputs will read the value  
being output. T he PF pins default to input during reset.  
GND  
RESET  
T he EZ-ICE uses the EE (emulator enable) signal to take con-  
trol of the ADSP-2181 in the target system. T his causes the  
processor to use its ERESET, EBR and EBG pins instead of the  
RESET, BR and BG pins. T he BG output is three-stated.  
T hese signals do not need to be jumper-isolated in your system.  
T he EZ-ICE connects to the target system via a ribbon cable  
and a 14-pin female plug. T he ribbon cable is 10 inches in  
length with one end fixed to the EZ-ICE. T he female plug is  
plugged onto the 14-pin connector (a pin strip header) on the  
target board.  
In addition to the programmable flags, the ADSP-2181 has  
five fixed-mode flags, FLAG_IN, FLAG_OUT , FL0, FL1 and  
FL2. FL0-FL2 are dedicated output flags. FLAG_IN and  
FLAG_OUT are available as an alternate configuration of  
SPORT 1.  
Tar get Boar d Connector for EZ-ICE P r obe  
T he EZ-ICE connector (a standard pin strip header) is shown in  
Figure 7. You must add this connector to your target board  
design if you intend to use the EZ-ICE. Be sure to allow enough  
room in your system to fit the EZ-ICE probe onto the 14-pin  
connector.  
INSTRUCTIO N SET D ESCRIP TIO N  
T he ADSP-2181 assembly language instruction set has an  
algebraic syntax that was designed for ease of coding and read-  
ability. T he assembly language, which takes full advantage of the  
processor’s unique architecture, offers the following benefits:  
• T he algebraic syntax eliminates the need to remember cryptic  
assembler mnemonics. For example, a typical arithmetic add  
instruction, such as AR = AX0 + AY0, resembles a simple  
equation.  
1
3
2
4
GND  
BG  
EBG  
BR  
• Every instruction assembles into a single, 24-bit word that can  
execute in a single instruction cycle.  
5
6
EBR  
EINT  
ELIN  
ECLK  
EMS  
ERESET  
7
8
• T he syntax is a superset ADSP-2100 Family assembly lan-  
guage and is completely source and object code compatible  
with other family members. Programs may need to be relo-  
cated to utilize on-chip memory and conform to the ADSP-  
2181’s interrupt vector and reset vector map.  
KEY (NO PIN)  
9
10  
12  
14  
ELOUT  
EE  
11  
13  
• Sixteen condition codes are available. For conditional jump,  
call, return or arithmetic instructions, the condition can be  
checked and the operation executed in the same instruction  
cycle.  
RESET  
TOP VIEW  
Figure 7. Target Board Connector for EZ-ICE  
REV. D  
–10–  
ADSP-2181  
T he 14-pin, 2-row pin strip header is keyed at the Pin 7 loca-  
tion—you must remove Pin 7 from the header. T he pins must  
be 0.025 inch square and at least 0.20 inch in length. Pin spac-  
ing should be 0.1 x 0.1 inches. T he pin strip header must have  
at least 0.15 inch clearance on all sides to accept the EZ-ICE  
probe plug. Pin strip headers are available from vendors such as  
3M, McKenzie and Samtec.  
Tar get System Inter face Signals  
When the EZ-ICE board is installed, the performance on some  
system signals changes. Design your system to be compatible  
with the following system interface signal changes introduced by  
the EZ-ICE board:  
• EZ-ICE emulation introduces an 8 ns propagation delay be-  
tween your target circuitry and the DSP on the RESET  
signal.  
Tar get Mem or y Inter face  
For your target system to be compatible with the EZ-ICE emu-  
lator, it must comply with the memory interface guidelines listed  
below.  
• EZ-ICE emulation introduces an 8 ns propagation delay be-  
tween your target circuitry and the DSP on the BR signal.  
• EZ-ICE emulation ignores RESET and BR when single-  
stepping.  
P M, D M, BM, IO M and CM  
Design your Program Memory (PM), Data Memory (DM),  
Byte Memory (BM), I/O Memory (IOM) and Composite  
Memory (CM) external interfaces to comply with worst case  
device timing requirements and switching characteristics as  
specified in the DSP’s data sheet. T he performance of the  
EZ-ICE may approach published worst case specification for  
some memory access timing requirements and switching  
characteristics.  
• EZ-ICE emulation ignores RESET and BR when in Emulator  
Space (DSP halted).  
• EZ-ICE emulation ignores the state of target BR in certain  
modes. As a result, the target system may take control of the  
DSP’s external memory bus only if bus grant (BG) is asserted  
by the EZ-ICE board’s DSP.  
Tar get Ar chitectur e File  
Note: If your target does not meet the worst case chip specifica-  
tion for memory access parameters, you may not be able to  
emulate your circuitry at the desired CLKIN frequency. De-  
pending on the severity of the specification violation, you may  
have trouble manufacturing your system as DSP components  
statistically vary in switching characteristic and timing require-  
ments within published limits.  
T he EZ-ICE software lets you load your program in its linked  
(executable) form. T he EZ-ICE PC program can not load sec-  
tions of your executable located in boot pages (by the linker).  
With the exception of boot page 0 (loaded into PM RAM), all  
sections of your executable mapped into boot pages are not  
loaded.  
Write your target architecture file to indicate that only PM  
RAM is available for program storage, when using the EZ-ICE  
software’s loading feature. Data can be loaded to PM RAM or  
DM RAM.  
Restr iction: All memory strobe signals on the ADSP-2181  
(RD, WR, PMS, DMS, BMS, CMS and IOMS) used in your  
target system must have 10 kΩ pull-up resistors connected when  
the EZ-ICE is being used. T he pull-up resistors are necessary  
because there are no internal pull-ups to guarantee their state  
during prolonged three-state conditions resulting from typical  
EZ-ICE debugging sessions. T hese resistors may be removed at  
your option when the EZ-ICE is not being used.  
REV. D  
–11–  
ADSP-2181–SPECIFICATIONS  
RECOMMENDED OPERATING CONDITIONS  
K Grade  
B Grade  
P aram eter  
Min  
Max  
Min  
Max  
Unit  
VDD  
T AMB  
Supply Voltage  
Ambient Operating T emperature  
4.5  
0
5.5  
+70  
4.5  
–40  
5.5  
+85  
V
°C  
ELECTRICAL CHARACTERISTICS  
K/B Grades  
Typ  
P aram eter  
Test Conditions  
Min  
Max  
Unit  
VIH  
VIH  
VIL  
VOH  
Hi-Level Input Voltage1, 2  
Hi-Level CLKIN Voltage  
Lo-Level Input Voltage1, 3  
Hi-Level Output Voltage1, 4, 5  
@ VDD = max  
@ VDD = max  
@ VDD = min  
@ VDD = min  
IOH = –0.5 mA  
@ VDD = min  
IOH = –100 µA6  
@ VDD = min  
IOL = 2 mA  
@ VDD = max  
VIN = VDDmax  
@ VDD = max  
VIN = 0 V  
@ VDD = max  
VIN = VDDmax8  
@ VDD = max  
VIN = 0 V8  
@ VDD = 5.0  
TAMB = +25°C  
tCK = 34.7 ns  
tCK = 30 ns  
2.0  
2.2  
V
V
V
0.8  
2.4  
V
VDD – 0.3  
V
VOL  
IIH  
Lo-Level Output Voltage1, 4, 5  
Hi-Level Input Current3  
0.4  
10  
10  
10  
10  
V
µA  
µA  
µA  
µA  
IIL  
Lo-Level Input Current3  
T hree-State Leakage Current7  
T hree-State Leakage Current7  
Supply Current (Idle)9  
IOZH  
IOZL  
IDD  
12  
13  
15  
mA  
mA  
mA  
tCK = 25 ns  
IDD  
Supply Current (Dynamic)10  
@ VDD = 5.0  
TAMB = +25°C  
tCK = 34.7 ns11  
tCK = 30 ns11  
tCK = 25 ns11  
@ VIN = 2.5 V,  
fIN = 1.0 MHz,  
TAMB = +25°C  
@ VIN = 2.5 V,  
fIN = 1.0 MHz,  
TAMB = +25°C  
65  
73  
85  
mA  
mA  
mA  
CI  
Input Pin Capacitance3, 6, 12  
8
8
pF  
pF  
CO  
Output Pin Capacitance6, 7, 12, 13  
NOT ES  
1Bidirectional pins: D0–D23, RFS0, RFS1, SCLK0, SCLK1, T FS0, T FS1, A1–A13, PF0–PF7.  
2Input only pins: RESET, BR, DR0, DR1, PWD.  
3Input only pins: CLKIN, RESET, BR, DR0, DR1, PWD.  
4Output pins: BG, PMS, DMS, BMS, IOMS, CMS, RD, WR, PWDACK, A0, DT 0, DT 1, CLKOUT , FL2-0, BGH.  
5Although specified for T T L outputs, all ADSP-2186 outputs are CMOS-compatible and will drive to VDD and GND, assuming no dc loads.  
6Guaranteed but not tested.  
7T hree-statable pins: A0–A13, D0–D23, PMS, DMS, BMS, IOMS, CMS, RD, WR, DT 0, DT 1, SCLK0, SCLK1, T FS0, T FS1, RFS0, RSF1, PF0–PF7.  
80 V on BR, CLKIN Inactive.  
9Idle refers to ADSP-2181 state of operation during execution of IDLE instruction. Deasserted pins are driven to either V DD or GND.  
10  
I
measurement taken with all instructions executing from internal memory. 50% of the instructions are multifunction (types 1, 4, 5, 12, 13, 14), 30% are type 2  
DD  
and type 6, and 20% are idle instructions.  
11  
V
= 0 V and 3 V. For typical figures for supply currents, refer to Power Dissipation section.  
IN  
12Applies to T QFP and PQFP package types.  
13Output pin capacitance is the capacitive load for any three-stated output pin.  
Specifications subject to change without notice.  
–12–  
REV. D  
ADSP-2181  
ABSO LUTE MAXIMUM RATINGS*  
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V  
Input Voltage . . . . . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V  
Output Voltage Swing . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V  
Operating T emperature Range (Ambient) . . . . –40°C to +85°C  
Storage T emperature Range . . . . . . . . . . . . . –65°C to +150°C  
Lead T emperature (5 sec) T QFP . . . . . . . . . . . . . . . . +280°C  
Lead T emperature (5 sec) PQFP . . . . . . . . . . . . . . . . . +280°C  
*Stresses above those listed under Absolute Maximum Ratings may cause perma-  
nent damage to the device. T hese are stress ratings only; functional operation of  
the device at these or any other conditions above those indicated in the operational  
sections of this specification is not implied. Exposure to absolute maximum rating  
conditions for extended periods may affect device reliability.  
ESD SENSITIVITY  
T he ADSP-2181 is an ESD (electrostatic discharge) sensitive device. Electrostatic charges readily  
accumulate on the human body and equipment and can discharge without detection. Permanent  
damage may occur to devices subjected to high energy electrostatic discharges.  
WARNING!  
T he ADSP-2181 features proprietary ESD protection circuitry to dissipate high energy discharges  
(Human Body Model). Per method 3015 of MIL-ST D-883, the ADSP-2181 has been classified as  
a Class 1 device.  
ESD SENSITIVE DEVICE  
Proper ESD precautions are recommended to avoid performance degradation or loss of function-  
ality. Unused devices must be stored in conductive foam or shunts, and the foam should be  
discharged to the destination before devices are removed.  
TIMING PARAMETERS  
GENERAL NO TES  
MEMO RY TIMING SP ECIFICATIO NS  
Use the exact timing information given. Do not attempt to  
derive parameters from the addition or subtraction of others.  
While addition or subtraction would yield meaningful results for  
an individual device, the values given in this data sheet reflect  
statistical variations and worst cases. Consequently, you cannot  
meaningfully add up parameters to derive longer times.  
T he table below shows common memory device specifications  
and the corresponding ADSP-2181 timing parameters, for your  
convenience.  
Mem ory  
AD SP -2181 Tim ing  
D evice  
Tim ing  
P aram eter  
Specification  
P aram eter D efinition  
TIMING NO TES  
Address Setup to  
Write Start  
Address Setup to  
Write End  
tASW  
A0–A13, xMS Setup before  
WR Low  
A0–A13, xMS Setup before  
WR Deasserted  
A0–A13, xMS Hold after  
WR Deasserted  
Switching Characteristics specify how the processor changes its  
signals. You have no control over this timing—circuitry external  
to the processor must be designed for compatibility with these  
signal characteristics. Switching characteristics tell you what the  
processor will do in a given circumstance. You can also use switch-  
ing characteristics to ensure that any timing requirement of a  
device connected to the processor (such as memory) is satisfied.  
tAW  
Address Hold T ime tWRA  
Data Setup T ime  
tDW  
Data Setup before WR  
High  
Timing Requirements apply to signals that are controlled by cir-  
cuitry external to the processor, such as the data input for a read  
operation. T iming requirements guarantee that the processor  
operates correctly with other devices.  
Data Hold T ime  
OE to Data Valid  
Address Access Time tAA  
tDH  
tRDD  
Data Hold after WR High  
RD Low to Data Valid  
A0–A13, xMS to Data Valid  
xMS = PMS, DMS, BMS, CMS, IOMS.  
FREQ UENCY D EP END ENCY FO R TIMING  
SP ECIFICATIO NS  
tCK is defined as 0.5tCKI. T he ADSP-2181 uses an input clock  
with a frequency equal to half the instruction rate: a 16.67 MHz  
input clock (which is equivalent to 60 ns) yields a 30 ns proces-  
sor cycle (equivalent to 33 MHz). tCK values within the range of  
0.5tCKI period should be substituted for all relevant timing pa-  
rameters to obtain the specification value.  
Example: tCKH = 0.5tCK – 7 ns = 0.5 (25 ns) – 7 ns = 8 ns  
REV. D  
–13–  
ADSP-2181  
P aram eter  
Min  
Max  
Unit  
Clock Signals and Reset  
Timing Requirements:  
tCKI  
tCKIL  
tCKIH  
CLKIN Period  
CLKIN Width Low  
CLKIN Width High  
50  
20  
20  
150  
ns  
ns  
ns  
Switching Characteristics:  
tCKL  
tCKH  
tCKOH  
CLKOUT Width Low  
CLKOUT Width High  
CLKIN High to CLKOUT High  
0.5tCK – 7  
0.5tCK – 7  
0
ns  
ns  
ns  
20  
Contr ol Signals  
Timing Requirement:  
1
tRSP  
RESET Width Low  
5tCK  
ns  
NOT E  
1Applies after power-up sequence is complete. Internal phase lock loop requires no more than 2000 CLKIN cycles assuming stable CLKIN (not including crystal  
oscillator start-up time).  
tCKI  
tCKIH  
CLKIN  
tCKIL  
tCKOH  
tCKH  
CLKOUT  
tCKL  
PF(2:0)*  
tMH  
tMS  
RESET  
*PF2 IS MODE C, PF1 IS MODE B, PF0 IS MODE A  
Figure 8. Clock Signals  
REV. D  
–14–  
ADSP-2181  
P aram eter  
Min  
Max  
Unit  
Inter r upts and Flag  
Timing Requirements:  
tIFS  
tIFH  
IRQx, FI, or PFx Setup before CLKOUT Low1, 2, 3, 4  
IRQx, FI, or PFx Hold after CLKOUT High1, 2, 3, 4  
0.25tCK + 15  
0.25tCK  
ns  
ns  
Switching Characteristics:  
tFOH  
Flag Output Hold after CLKOUT Low5  
tFOD  
Flag Output Delay from CLKOUT Low5  
0.5tCK – 7  
ns  
ns  
0.5tCK + 5  
NOT ES  
1If IRQx and FI inputs meet tIFS and tIFH setup/hold requirements, they will be recognized during the current clock cycle; otherwise the signals will be recognized on  
the following cycle. (Refer to “Interrupt Controller Operation” in the Program Control chapter of the User’s Manual for further information on interrupt servicing.)  
2Edge-sensitive interrupts require pulsewidths greater than 10 ns; level-sensitive interrupts must be held low until serviced.  
3IRQx = IRQ0, IRQ1, IRQ2, IRQL0, IRQL1, IRQE.  
4PFx = PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7.  
5Flag outputs = PFx, FL0, FL1, FL2, Flag_out4.  
tFOD  
CLKOUT  
tFOH  
FLAG  
OUTPUTS  
tIFH  
IRQx  
FI  
PFx  
tIFS  
Figure 9. Interrupts and Flags  
REV. D  
–15–  
ADSP-2181  
P aram eter  
Min  
Max  
Unit  
Bus Request/Gr ant  
Timing Requirements:  
tBH  
tBS  
BR Hold after CLKOUT High1  
BR Setup before CLKOUT Low1  
0.25tCK + 2  
0.25tCK + 17  
ns  
ns  
Switching Characteristics:  
tSD  
CLKOUT High to xMS,  
0.25tCK + 10  
ns  
RD, WR Disable  
xMS, RD, WR  
Disable to BG Low  
BG High to xMS,  
RD, WR Enable  
tSDB  
tSE  
0
ns  
ns  
ns  
ns  
ns  
0
tSEC  
tSDBH  
tSEH  
xMS, RD, WR  
Enable to CLKOUT High  
xMS, RD, WR  
0.25tCK – 4  
Disable to BGH Low2  
BGH High to xMS,  
RD, WR Enable2  
0
0
NOT ES  
xMS = PMS, DMS, CMS, IOMS, BMS.  
1BR is an asynchronous signal. If BR meets the setup/hold requirements, it will be recognized during the current clock cycle; otherwise the signal will be recognized on  
the following cycle. Refer to the ADSP-2100 Family User’s Manual, Third Edition for BR/BG cycle relationships.  
2BGH is asserted when the bus is granted and the processor requires control of the bus to continue.  
tBH  
CLKOUT  
BR  
tBS  
CLKOUT  
PMS, DMS  
BMS, RD  
tSD  
WR  
tSEC  
BG  
tSDB  
tSE  
BGH  
tSDBH  
tSEH  
Figure 10. Bus Request–Bus Grant  
REV. D  
–16–  
ADSP-2181  
P aram eter  
Min  
Max  
Unit  
Mem or y Read  
Timing Requirements:  
tRDD  
tAA  
tRDH  
RD Low to Data Valid  
A0–A13, xMS to Data Valid  
Data Hold from RD High  
0.5tCK – 9 + w  
0.75tCK – 10.5 + w  
ns  
ns  
ns  
0
Switching Characteristics:  
tRP  
RD Pulsewidth  
CLKOUT High to RD Low  
A0–A13, xMS Setup before RD Low  
A0–A13, xMS Hold after RD Deasserted  
RD High to RD or WR Low  
0.5tCK – 5 + w  
0.25tCK – 5  
0.25tCK – 4  
0.25tCK – 3  
0.5tCK – 5  
ns  
ns  
ns  
ns  
ns  
tCRD  
tASR  
tRDA  
tRWR  
0.25tCK + 7  
w = wait states × tCK  
.
xMS = PMS, DMS, CMS, IOMS, BMS.  
CLKOUT  
A0–A13  
DMS, PMS,  
BMS, IOMS,  
CMS  
tRDA  
RD  
D
tASR  
tCRD  
tRP  
tRWR  
tRDD  
tRDH  
tAA  
WR  
Figure 11. Mem ory Read  
REV. D  
–17–  
ADSP-2181  
P aram eter  
Min  
Max  
Unit  
Mem or y Wr ite  
Switching Characteristics:  
tDW  
tDH  
tWP  
tWDE  
tASW  
tDDR  
tCWR  
tAW  
Data Setup before WR High  
Data Hold after WR High  
WR Pulsewidth  
WR Low to Data Enabled  
A0–A13, xMS Setup before WR Low  
Data Disable before WR or RD Low  
CLKOUT High to WR Low  
A0–A13, xMS, Setup before WR Deasserted  
A0–A13, xMS Hold after WR Deasserted  
WR High to RD or WR Low  
0.5tCK – 7 + w  
0.25tCK – 2  
0.5tCK – 5 + w  
0
0.25tCK – 4  
0.25tCK – 4  
0.25tCK – 5  
0.75tCK – 9 + w  
0.25tCK – 3  
0.5tCK – 5  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
0.25 tCK + 7  
tWRA  
tWWR  
w = wait states × tCK  
.
xMS = PMS, DMS, CMS, IOMS, BMS.  
CLKOUT  
A0–A13  
DMS, PMS,  
BMS, CMS,  
IOMS  
tWRA  
WR  
tWWR  
tASW  
tWP  
tAW  
tDH  
tDDR  
tCWR  
D
tDW  
tWDE  
RD  
Figure 12. Mem ory Write  
REV. D  
–18–  
ADSP-2181  
P aram eter  
Min  
Max  
Unit  
Ser ial P or ts  
Timing Requirements:  
tSCK  
tSCS  
tSCH  
tSCP  
SCLK Period  
50  
4
7
ns  
ns  
ns  
ns  
DR/T FS/RFS Setup before SCLK Low  
DR/T FS/RFS Hold after SCLK Low  
SCLKIN Width  
20  
Switching Characteristics:  
tCC  
CLKOUT High to SCLKOUT  
SCLK High to DT Enable  
SCLK High to DT Valid  
T FS/RFSOUT Hold after SCLK High  
T FS/RFSOUT Delay from SCLK High  
DT Hold after SCLK High  
T FS (Alt) to DT Enable  
T FS (Alt) to DT Valid  
0.25tCK  
0
0.25tCK + 10  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tSCDE  
tSCDV  
tRH  
15  
15  
0
tRD  
tSCDH  
tT DE  
tT DV  
tSCDD  
tRDV  
0
0
14  
15  
15  
SCLK High to DT Disable  
RFS (Multichannel, Frame Delay Zero) to DT Valid  
CLKOUT  
tSCK  
tCC  
tCC  
SCLK  
tSCP  
tSCP  
tSCS  
tSCH  
DR  
TFS  
RFS  
IN  
IN  
tRD  
tRH  
RFS  
TFS  
OUT  
OUT  
tSCDD  
tSCDV  
tSCDH  
tSCDE  
DT  
tTDE  
tTDV  
TFS  
OUT  
ALTERNATE  
FRAME MODE  
tRDV  
RFS  
OUT  
MULTICHANNEL MODE,  
FRAME DELAY 0  
(MFD = 0)  
tTDE  
tTDV  
TFS  
IN  
ALTERNATE  
FRAME MODE  
tRDV  
RFS  
IN  
MULTICHANNEL MODE,  
FRAME DELAY 0  
(MFD = 0)  
Figure 13. Serial Ports  
REV. D  
–19–  
ADSP-2181  
P aram eter  
Min  
Max  
Unit  
ID MA Addr ess Latch  
Timing Requirements:  
tIALP  
tIASU  
tIAH  
tIKA  
tIALS  
Duration of Address Latch1, 2  
10  
5
2
0
3
ns  
ns  
ns  
ns  
ns  
IAD15–0 Address Setup before Address Latch End2  
IAD15–0 Address Hold after Address Latch End2  
IACK Low before Start of Address Latch1  
Start of Write or Read after Address Latch End2, 3  
NOT ES  
1Start of Address Latch = IS Low and IAL High.  
2End of Address Latch = IS High or IAL Low.  
3Start of Write or Read = IS Low and IWR Low or IRD Low.  
IACK  
tIKA  
IAL  
tIALP  
IS  
tIASU  
tIAH  
IAD15–0  
tIALS  
IRD OR  
IWR  
Figure 14. IDMA Address Latch  
REV. D  
–20–  
ADSP-2181  
P aram eter  
Min  
Max  
Unit  
ID MA Wr ite, Shor t Wr ite Cycle  
Timing Requirements:  
tIKW  
tIWP  
tIDSU  
tIDH  
IACK Low before Start of Write1  
0
15  
5
ns  
ns  
ns  
ns  
Duration of Write1, 2  
IAD15–0 Data Setup before End of Write2, 3, 4  
IAD15–0 Data Hold after End of Write2, 3, 4  
2
Switching Characteristic:  
tIKHW  
Start of Write to IACK High  
15  
ns  
NOT ES  
1Start of Write = IS Low and IWR Low.  
2End of Write = IS High or IWR High.  
3If Write Pulse ends before IACK Low, use specifications tIDSU, tIDH  
.
4If Write Pulse ends after IACK Low, use specifications t IKSU, tIKH  
.
tIKW  
IACK  
tIKHW  
IS  
tIWP  
IWR  
tIDH  
tIDSU  
DATA  
IAD15–0  
Figure 15. IDMA Write, Short Write Cycle  
REV. D  
–21–  
ADSP-2181  
P aram eter  
Min  
Max  
Unit  
ID MA Wr ite, Long Wr ite Cycle  
Timing Requirements:  
tIKW  
tIKSU  
tIKH  
IACK Low before Start of Write1  
0
ns  
ns  
ns  
IAD15–0 Data Setup before IACK Low2, 3  
IAD15–0 Data Hold after IACK Low2, 3  
0.5tCK + 10  
2
Switching Characteristics:  
tIKLW  
Start of Write to IACK Low4  
tIKHW Start of Write to IACK High  
1.5tCK  
ns  
ns  
15  
NOT ES  
1Start of Write = IS Low and IWR Low.  
2If Write Pulse ends before IACK Low, use specifications tIDSU, tIDH  
.
3If Write Pulse ends after IACK Low, use specifications t IKSU, tIKH  
.
4T his is the earliest time for IACK Low from Start of Write. For IDMA Write cycle relationships, please refer to the User’s Manual.  
tIKW  
IACK  
tIKHW  
tIKLW  
IS  
IWR  
tIKSU  
tIKH  
DATA  
IAD15–0  
Figure 16. IDMA Write, Long Write Cycle  
REV. D  
–22–  
ADSP-2181  
P aram eter  
Min  
Max  
Unit  
ID MA Read, Long Read Cycle  
Timing Requirements:  
tIKR  
tIRP  
IACK Low before Start of Read1  
Duration of Read  
0
15  
ns  
ns  
Switching Characteristics:  
tIKHR  
tIKDS  
tIKDH  
tIKDD  
tIRDE  
tIRDV  
tIRDH1  
tIRDH2  
IACK High after Start of Read1  
15  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
IAD15–0 Data Setup before IACK Low  
0.5tCK – 10  
0
IAD15–0 Data Hold after End of Read2  
IAD15–0 Data Disabled after End of Read2  
12  
15  
IAD15–0 Previous Data Enabled after Start of Read  
IAD15–0 Previous Data Valid after Start of Read  
IAD15–0 Previous Data Hold after Start of Read (DM/PM1)3  
IAD15–0 Previous Data Hold after Start of Read (PM2)4  
0
2tCK – 5  
tCK – 5  
NOT ES  
1Start of Read = IS Low and IRD Low.  
2End of Read = IS High or IRD High.  
3DM read or first half of PM read.  
4Second half of PM read.  
IACK  
IS  
tIKHR  
tIKR  
tIRP  
IRD  
tIKDH  
tIKDS  
tIRDE  
PREVIOUS  
DATA  
READ  
DATA  
IAD15–0  
tIRDV  
tIKDD  
tIRDH  
Figure 17. IDMA Read, Long Read Cycle  
REV. D  
–23–  
ADSP-2181  
P aram eter  
Min  
Max  
Unit  
ID MA Read, Shor t Read Cycle  
Timing Requirements:  
tIKR  
tIRP  
IACK Low before Start of Read1  
Duration of Read  
0
15  
ns  
ns  
Switching Characteristics:  
tIKHR  
tIKDH  
tIKDD  
tIRDE  
tIRDV  
IACK High after Start of Read1  
15  
12  
15  
ns  
ns  
ns  
ns  
ns  
IAD15–0 Data Hold after End of Read2  
0
0
IAD15–0 Data Disabled after End of Read2  
IAD15–0 Previous Data Enabled after Start of Read  
IAD15–0 Previous Data Valid after Start of Read  
NOT ES  
1Start of Read = IS Low and IRD Low.  
2End of Read = IS High or IRD High.  
IACK  
IS  
tIKR  
tIKHR  
tIRP  
IRD  
tIKDH  
tIRDE  
PREVIOUS  
DATA  
IAD15–0  
tIKDD  
tIRDV  
Figure 18. IDMA Read, Short Read Cycle  
REV. D  
–24–  
ADSP-2181  
(C × VDD 2 × f ) is calculated for each output:  
O UTP UT D RIVE CURRENTS  
Figure 19 shows typical I-V characteristics for the output drivers  
of the ADSP-2181. T he curves represent the current drive  
capability of the output drivers as a function of output voltage.  
# of  
P ins × C  
2
× VD D  
× f  
× 10 pF × 52  
V
× 33.3 MHz  
× 16.67 MHz  
× 16.67 MHz  
× 33.3 MHz  
=
=
=
=
66.6 mW  
37.5 mW  
4.2 mW  
8.3 mW  
116.6 mW  
120  
Address, DMS  
Data Output, WR  
RD  
8
9
1
1
× 10 pF × 52  
× 10 pF × 52  
× 10 pF × 52  
V
V
V
100  
80  
60  
5.5V, –40؇C  
5.0V, +25؇C  
CLKOUT  
40  
4.5V, +85؇C  
20  
T otal power dissipation for this example is PINT + 116.6 mW.  
0
4.5V, +85؇C  
1, 3, 4  
2181 POWER, INTERNAL  
–20  
–40  
–60  
–80  
570  
5.5V, –40؇C  
5.0V, +25؇C  
550mW  
520  
V
= 5.5V  
DD  
470  
420  
0
1
2
3
4
5
6
SOURCE VOLTAGE – Volts  
425mW  
330mW  
410mW  
V
= 5.0V  
Figure 19. Typical Drive Currents  
DD  
370  
320  
P O WER D ISSIP ATIO N  
T o determine total power dissipation in a specific application,  
the following equation should be applied for each output:  
325mW  
250mW  
V
= 4.5V  
DD  
270  
220  
2
C × VDD × f  
28  
30  
32  
34  
36  
38  
40  
42  
1/t – MHz  
CK  
C = load capacitance, f = output switching frequency.  
1, 2, 3  
POWER, IDLE  
Exam ple:  
100  
90  
In an application where external data memory is used and no  
other outputs are active, power dissipation is calculated as  
follows:  
V
= 5.5V  
= 5.0V  
= 4.5V  
DD  
95mW  
75mW  
80  
70  
60  
Assumptions:  
V
77mW  
DD  
•
•
External data memory is accessed every cycle with 50% of the  
address pins switching.  
60mW  
45mW  
30  
V
DD  
External data memory writes occur every other cycle with  
50% of the data pins switching.  
54mW  
50  
40  
30  
•
•
Each address and data pin has a 10 pF total load at the pin.  
T he application operates at VDD = 5.0 V and tCK = 30 ns.  
28  
32  
34  
36  
38  
40  
3
42  
1/t – MHz  
CK  
2
Total Power Dissipation = PINT + (C × VDD × f )  
POWER, IDLE n MODES  
PINT = internal power dissipation from Power vs. Frequency  
graph (Figure 20).  
80  
75  
70  
65  
60  
55  
50  
45  
40  
IDLE  
75mW  
1000  
60mW  
n
V
V
V
= 5.5V  
= 5.0V  
= 4.5V  
DD  
DD  
DD  
100  
10  
1
39mW  
IDLE (16)  
IDLE (128)  
35mW  
35  
30  
37mW  
40  
34mW  
30  
28  
32  
34  
36  
38  
42  
1/t – MHz  
CK  
VALID FOR ALL TEMPERATURE GRADES.  
1
POWER REFLECTS DEVICE OPERATING WITH NO OUTPUT LOADS.  
2
IDLE REFERS TO ADSP-2181 STATE OF OPERATION DURING EXECUTION OF IDLE  
INSTRUCTION. DEASSERTED PINS ARE DRIVEN TO EITHER V OR GND.  
5
15  
25  
35  
45  
55  
65  
75  
85  
–5  
DD  
TEMPERATURE – °C  
NOTES:  
1. REFLECTS ADSP-2181 OPERATION IN LOWEST POWER MODE.  
(SEE “SYSTEM INTERFACE" CHAPTER OF THE ADSP-2100 FAMILY  
USER'S MANUAL, THIRD EDITION, FOR DETAILS.)  
2. CURRENT REFLECTS DEVICE OPERATING WITH NO OUTPUT LOADS.  
3
TYPICAL POWER DISSIPATION AT 5.0V V AND 25؇C EXCEPT WHERE SPECIFIED.  
DD  
4
I
MEASUREMENT TAKEN WITH ALL INSTRUCTIONS EXECUTING FROM INTERNAL  
MEMORY. 50% OF THE INSTRUCTIONS ARE MULTIFUNCTION (TYPES 1, 4, 5, 12, 13, 14),  
30% ARE TYPE 2 AND TYPE 6 AND 20% ARE IDLE INSTRUCTIONS.  
DD  
Figure 21. Power vs. Frequency  
Figure 20. Power-Down Supply Current (Typical)  
REV. D  
–25–  
ADSP-2181  
CAP ACITIVE LO AD ING  
Figures 22 and 23 show the capacitive loading characteristics of  
the ADSP-2181.  
is calculated. If multiple pins (such as the data bus) are dis-  
abled, the measurement value is that of the last pin to stop  
driving.  
25  
INPUT  
1.5V  
1.5V  
OR  
OUTPUT  
20  
15  
10  
Figure 24. Voltage Reference Levels for AC Measure-  
m ents (Except Output Enable/Disable)  
O utput Enable Tim e  
Output pins are considered to be enabled when they have made  
a transition from a high-impedance state to when they start  
driving. T he output enable time (tENA) is the interval from when  
a reference signal reaches a high or low voltage level to when  
the output has reached a specified high or low trip point, as  
shown in the Output Enable/Disable diagram. If multiple pins  
(such as the data bus) are enabled, the measurement value is  
that of the first pin to start driving.  
5
0
50  
0
100  
150  
– pF  
200  
250  
C
L
Figure 22. Range of Output Rise Tim e vs. Load Capaci-  
tance, CL (at Maxim um Am bient Operating Tem perature)  
REFERENCE  
SIGNAL  
tMEASURED  
16  
tENA  
14  
12  
V
V
OH tDIS  
OH  
(MEASURED)  
(MEASURED)  
V
V
(MEASURED) – 0.5V  
(MEASURED) +0.5V  
2.0V  
1.0V  
OH  
OUTPUT  
10  
8
OL  
V
V
OL  
OL  
tDECAY  
(MEASURED)  
(MEASURED)  
6
4
OUTPUT STARTS  
DRIVING  
OUTPUT STOPS  
DRIVING  
2
0
HIGH-IMPEDANCE STATE. TEST CONDITIONS CAUSE  
THIS VOLTAGE LEVEL TO BE APPROXIMATELY 1.5V.  
Figure 25. Output Enable/Disable  
–2  
–4  
I
0
50  
100  
150  
200  
250  
OL  
C
– pF  
L
Figure 23. Range of Output Valid Delay or Hold vs. Load  
Capacitance, CL (at Maxim um Am bient Operating  
Tem perature)  
TO  
OUTPUT  
PIN  
+1.5V  
50pF  
TEST CO ND ITIO NS  
O utput D isable Tim e  
Output pins are considered to be disabled when they have  
stopped driving and started a transition from the measured  
output high or low voltage to a high impedance state. T he out-  
put disable time (tDIS) is the difference of tMEASURED and tDECAY  
as shown in the Output Enable/Disable diagram. T he time is the  
interval from when a reference signal reaches a high or low volt-  
age level to when the output voltages have changed by 0.5 V  
from the measured output high or low voltage. T he decay time,  
tDECAY, is dependent on the capacitive load, CL, and the current  
load, iL, on the output pin. It can be approximated by the fol-  
lowing equation:  
I
OH  
Figure 26. Equivalent Device Loading for AC Measure-  
m ents (Including All Fixtures)  
,
CL × 0.5V  
tDECAY  
=
iL  
from which  
tDIS = tMEASURED – tDECAY  
REV. D  
–26–  
ADSP-2181  
ENVIRO NMENTAL CO ND ITIO NS  
Ambient T emperature Rating:  
TAMB  
TCASE  
PD  
θC A  
θJA  
=
=
=
=
=
=
TCASE – (PD × θC A)  
Case T emperature in °C  
Power Dissipation in W  
T hermal Resistance (Case-to-Ambient)  
T hermal Resistance (Junction-to-Ambient)  
T hermal Resistance (Junction-to-Case)  
θJC  
P ackage  
θJA  
θJC  
θCA  
T QFP  
PQFP  
50°C/W  
41°C/W  
2°C/W  
10°C/W  
48°C/W  
31°C/W  
REV. D  
–27–  
ADSP-2181  
128-Lead TQFP P ackage P inout  
103  
102  
128  
1
IAL  
PF3  
PF2  
PF1  
PF0  
GND  
D23  
D22  
D21  
D20  
D19  
D18  
D17  
D16  
D15  
GND  
VDD  
GND  
WR  
RD  
IOMS  
BMS  
DMS  
CMS  
GND  
VDD  
D14  
D13  
D12  
D11  
D10  
D9  
PMS  
A0  
A1  
A2  
A3  
A4  
TOP VIEW  
(PINS DOWN)  
A5  
D8  
A6  
D7  
A7  
D6  
XTAL  
CLKIN  
GND  
CLKOUT  
GND  
VDD  
A8  
D5  
GND  
D4  
D3  
D2  
D1  
D0  
A9  
VDD  
A10  
BG  
A11  
A12  
EBG  
BR  
A13  
EBR  
EINT  
ELIN  
ELOUT  
IRQE  
MMAP  
PWD  
IRQ2  
ECLK  
38  
65  
39  
64  
REV. D  
–28–  
ADSP-2181  
TQFP P in Configurations  
TQFP  
P in  
TQFP  
P in  
TQFP  
P in  
TQFP  
P in  
Num ber  
Nam e  
Num ber  
Nam e  
Num ber  
Nam e  
Num ber  
Nam e  
1
2
3
4
5
6
7
8
IAL  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
A12  
A13  
IRQE  
MMAP  
PWD  
65  
66  
67  
68  
69  
70  
71  
72  
73  
74  
75  
76  
77  
78  
79  
80  
81  
82  
83  
84  
85  
86  
87  
88  
89  
90  
91  
92  
93  
94  
95  
96  
ECLK  
ELOUT  
ELIN  
EINT  
EBR  
BR  
EBG  
BG  
VDD  
D0  
D1  
D2  
D3  
D4  
GND  
D5  
D6  
D7  
D8  
97  
98  
99  
D19  
D20  
D21  
D22  
PF3  
PF2  
PF1  
PF0  
WR  
100  
101  
102  
103  
104  
105  
106  
107  
108  
109  
110  
111  
112  
113  
114  
115  
116  
117  
118  
119  
120  
121  
122  
123  
124  
125  
126  
127  
128  
D23  
IRQ2  
GND  
IWR  
IRD  
RD  
BMODE  
PWDACK  
IACK  
BGH  
VDD  
GND  
IRQL0  
IRQL1  
FL0  
FL1  
FL2  
IOMS  
BMS  
DMS  
CMS  
GND  
VDD  
PMS  
A0  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
XT AL  
CLKIN  
GND  
CLKOUT  
GND  
VDD  
A8  
9
IAD15  
IAD14  
IAD13  
IAD12  
IAD11  
IAD10  
IAD9  
IAD8  
IAD7  
IAD6  
VDD  
GND  
IAD5  
IAD4  
IAD3  
IAD2  
IAD1  
IAD0  
PF7  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
DT 0  
T FS0  
RFS0  
DR0  
D9  
D10  
D11  
D12  
D13  
D14  
GND  
VDD  
GND  
D15  
D16  
D17  
D18  
SCLK0  
DT 1/F0  
T FS1/IRQ1  
RFS1/IRQ0  
GND  
DR1/FI  
SCLK1  
ERESET  
RESET  
EMS  
PF6  
PF5  
PF4  
GND  
IS  
A9  
A10  
A11  
EE  
REV. D  
–29–  
ADSP-2181  
128-Lead P QFP P ackage P inout  
97  
128  
96  
1
PF0  
D22  
D21  
D20  
D19  
D18  
D17  
D16  
D15  
GND  
VDD  
GND  
D14  
D13  
D12  
D11  
D10  
D9  
WR  
RD  
IOMS  
BMS  
DMS  
CMS  
GND  
VDD  
PMS  
A0  
A1  
A2  
A3  
A4  
A5  
A6  
128L PQFP  
(28MM x 28MM)  
TOP VIEW  
(PINS DOWN)  
D8  
A7  
D7  
D6  
D5  
GND  
D4  
XTAL  
CLKIN  
GND  
CLKOUT  
GND  
VDD  
A8  
D3  
D2  
A9  
D1  
A10  
D0  
VDD  
A11  
A12  
A13  
BG  
EBG  
IRQE  
MMAP  
BR  
EBR  
32  
65  
64  
33  
REV. D  
–30–  
ADSP-2181  
P QFP P in Configurations  
P QFP  
P in  
P QFP  
P in  
P QFP  
P in  
P QFP  
P in  
Num ber  
Nam e  
Num ber  
Nam e  
Num ber  
Nam e  
Num ber  
Nam e  
1
2
3
4
5
6
7
8
PF0  
WR  
RD  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
PWD  
IRQ2  
BMODE  
PWDACK  
IACK  
BGH  
VDD  
GND  
IRQL0  
IRQL1  
FL0  
FL1  
FL2  
DT 0  
T FS0  
RFS0  
DR0  
SCLK0  
DT 1/FO  
T FS1/IRQ1  
RFS1/IRQ0  
GND  
DR1/FI  
SCLK1  
ERESET  
RESET  
EMS  
65  
66  
67  
68  
69  
70  
71  
72  
73  
74  
75  
76  
77  
78  
79  
80  
81  
82  
83  
84  
85  
86  
87  
88  
89  
90  
91  
92  
93  
94  
95  
96  
EBR  
BR  
EBG  
BG  
VDD  
D0  
D1  
D2  
D3  
D4  
GND  
D5  
97  
98  
99  
D23  
GND  
IWR  
IRD  
IOMS  
BMS  
DMS  
CMS  
GND  
VDD  
PMS  
A0  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
XT AL  
CLKIN  
GND  
CLKOUT  
GND  
VDD  
A8  
100  
101  
102  
103  
104  
105  
106  
107  
108  
109  
110  
111  
112  
113  
114  
115  
116  
117  
118  
119  
120  
121  
122  
123  
124  
125  
126  
127  
128  
IAD15  
IAD14  
IAD13  
IAD12  
IAD11  
IAD10  
IAD9  
IAD8  
IAD7  
IAD6  
VDD  
GND  
IAD5  
IAD4  
IAD3  
IAD2  
IAD1  
IAD0  
PF7  
PF6  
PF5  
PF4  
GND  
IS  
IAL  
PF3  
PF2  
PF1  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
D6  
D7  
D8  
D9  
D10  
D11  
D12  
D13  
D14  
GND  
VDD  
GND  
D15  
D16  
D17  
D18  
D19  
D20  
D21  
D22  
A9  
A10  
A11  
A12  
A13  
IRQE  
MMAP  
EE  
ECLK  
ELOUT  
ELIN  
EINT  
REV. D  
–31–  
ADSP-2181  
O UTLINE D IMENSIO NS  
D imensions shown in mm and (inches).  
128-Lead Metr ic P lastic Q uad Flatpack (P Q FP )  
128-Lead Metr ic Thin P lastic Q uad Flatpack (TQ FP )  
(ST-128)  
(S-128)  
31.45 (1.238)  
30.95 (1.219)  
28.10 (1.106)  
27.90 (1.098)  
24.87 (0.979)  
24.73 (0.974)  
16.25 (0.640)  
15.75 (0.620)  
14.10 (0.555)  
13.90 (0.547)  
1.60 (0.063)  
TYP  
4.07  
(0.160)  
MAX  
12.50 (0.492) TYP  
0.75 (0.030)  
0.45 (0.018)  
1.03 (0.041)  
0.65 (0.031)  
128  
1
103  
102  
128  
1
103  
102  
SEATING  
PLANE  
SEATING  
PLANE  
TOP VIEW  
(PINS DOWN)  
TOP VIEW  
(PINS DOWN)  
0.10 (0.004)  
MAX  
32  
33  
65  
64  
0.25 (0.010)  
MIN  
0.45 (0.018)  
0.30 (0.012)  
0.87 (0.034)  
0.73 (0.029)  
0.10  
(0.004)  
MAX  
38  
39  
65  
64  
3.67 (0.144)  
3.17 (0.125)  
0.15 (0.006)  
0.27 (0.011)  
0.17 (0.007)  
0.58 (0.023)  
0.42 (0.017)  
0.05 (0.002)  
NOTE: THE ACTUAL POSITION OF EACH LEAD IS  
WITHIN .20 (.008) FROM ITS IDEAL POSITION  
1.50 (0.059)  
1.30 (0.051)  
WHEN MEASURED IN THE LATERAL DIRECTION.  
UNLESS OTHERWISE NOTED.  
NOTE: THE ACTUAL POSITION OF EACH LEAD IS  
WITHIN .08 (.0032) FROM ITS IDEAL POSITION  
WHEN MEASURED IN THE LATERAL DIRECTION.  
UNLESS OTHERWISE NOTED.  
O RD ERING GUID E  
Am bient  
Tem perature  
Instruction  
Rate  
P ackage  
P ackage  
P art Num ber  
Range  
(MH z)  
D escription  
O ptions*  
ADSP-2181KST -115  
ADSP-2181BST -115  
ADSP-2181KS-115  
ADSP-2181BS-115  
ADSP-2181KST -133  
ADSP-2181BST -133  
ADSP-2181KS-133  
ADSP-2181BS-133  
ADSP-2181KST -160  
ADSP-2181KS-160  
0°C to +70°C  
–40°C to +85°C  
0°C to +70°C  
–40°C to +85°C  
0°C to +70°C  
–40°C to +85°C  
0°C to +70°C  
–40°C to +85°C  
0°C to +70°C  
0°C to +70°C  
28.8  
28.8  
28.8  
28.8  
33.3  
33.3  
33.3  
33.3  
40  
128-Lead T QFP  
128-Lead T QFP  
128-Lead PQFP  
128-Lead PQFP  
128-Lead T QFP  
128-Lead T QFP  
128-Lead PQFP  
128-Lead PQFP  
128-Lead T QFP  
128-Lead PQFP  
ST -128  
ST -128  
S-128  
S-128  
ST -128  
ST -128  
S-128  
S-128  
ST -128  
S-128  
40  
*S = Plastic Quad Flatpack (PQFP), ST = Plastic T hin Quad Flatpack (T QFP).  
REV. D  
–32–  

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