ADSP-2185MKCA-300_技术文档

DSP

Microcomputer

a

ADSP-2185M

FEATURES

System Interface

Performance

Flexible I/O Structure Allows 2.5 V or 3.3 V Operation;

All Inputs Tolerate up to 3.6 V Regardless of Mode

16-Bit Internal DMA Port for High-Speed Access to

On-Chip Memory (Mode Selectable)

4 MByte Memory Interface for Storage of Data Tables

and Program Overlays (Mode Selectable)

8-Bit DMA to Byte Memory for Transparent Program

and Data Memory Transfers (Mode Selectable)

I/O Memory Interface with 2048 Locations Supports

Parallel Peripherals (Mode Selectable)

Programmable Memory Strobe and Separate I/O

Memory Space Permits “Glueless” System Design

Programmable Wait State Generation

Two Double-Buffered Serial Ports with Companding

Hardware and Automatic Data Buffering

Automatic Booting of On-Chip Program Memory from

Byte-Wide External Memory, e.g., EPROM, or

through Internal DMA Port

13.3 ns Instruction Cycle Time @ 2.5 V (Internal),

75 MIPS Sustained Performance

Single-Cycle Instruction Execution

Single-Cycle Context Switch

3-Bus Architecture Allows Dual Operand Fetches in

Every Instruction Cycle

Multifunction Instructions

Power-Down Mode Featuring Low CMOS Standby Power

Dissipation with 200 CLKIN Cycle Recovery from

Power-Down Condition

Low Power Dissipation in Idle Mode

Integration

ADSP-2100 Family Code Compatible (Easy to Use

Algebraic Syntax), with Instruction Set Extensions

80K Bytes of On-Chip RAM, Configured as

16K Words Program Memory RAM

16K Words Data Memory RAM

Dual-Purpose Program Memory for Both Instruction and

Data Storage

Six External Interrupts

13 Programmable Flag Pins Provide Flexible System

Signaling

UART Emulation through Software SPORT Reconfiguration

ICE-Port™ Emulator Interface Supports Debugging in

Final Systems

Independent ALU, Multiplier/Accumulator, and Barrel

Shifter Computational Units

Two Independent Data Address Generators

Powerful Program Sequencer Provides Zero Overhead

Looping Conditional Instruction Execution

Programmable 16-Bit Interval Timer with Prescaler

100-Lead LQFP and 144-Ball Mini-BGA

FUNCTIONAL BLOCK DIAGRAM

POWER-DOWN

CONTROL

FULL MEMORY MODE

MEMORY

DATA ADDRESS

GENERATORS

PROGRAMMABLE

EXTERNAL

ADDRESS

BUS

PROGRAM

MEMORY

16K 24 BIT

DATA

PROGRAM

SEQUENCER

I/O

MEMORY

AND

FLAGS

DAG1 DAG2

؋

16K

؋

16 BIT

EXTERNAL

DATA

BUS

PROGRAM MEMORY ADDRESS

BYTE DMA

DATA MEMORY ADDRESS

PROGRAM MEMORY DATA

DATA MEMORY DATA

CONTROLLER

OR

EXTERNAL

DATA

BUS

SERIAL PORTS

ARITHMETIC UNITS

TIMER

SPORT0 SPORT1

ALU

MAC

SHIFTER

INTERNAL

DMA

PORT

ADSP-2100 BASE

ARCHITECTURE

HOST MODE

ICE-Port is a trademark of Analog Devices, Inc.

REV. 0

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties

which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700

Fax: 781/326-8703

World Wide Web Site: http://www.analog.com

ADSP-2185M

TABLE OF CONTENTS

RECOMMENDED OPERATING CONDITIONS . . . . . 18

ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . 18

ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . 19

TIMING SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . 19

GENERAL NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

TIMING NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

MEMORY TIMING SPECIFICATIONS . . . . . . . . . . . . 19

FREQUENCY DEPENDENCY FOR

TIMING SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . 20

ENVIRONMENTAL CONDITIONS . . . . . . . . . . . . . . . 20

POWER DISSIPATION . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Output Drive Currents . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Capacitive Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

TEST CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Output Disable Time . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Output Enable Time . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Clock Signals and Reset . . . . . . . . . . . . . . . . . . . . . . . . . 23

Interrupts and Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Bus Request–Bus Grant . . . . . . . . . . . . . . . . . . . . . . . . . 25

Memory Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Memory Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

IDMA Address Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

IDMA Write, Short Write Cycle . . . . . . . . . . . . . . . . . . 30

IDMA Write, Long Write Cycle . . . . . . . . . . . . . . . . . . . 31

IDMA Read, Long Read Cycle . . . . . . . . . . . . . . . . . . . 32

IDMA Read, Short Read Cycle . . . . . . . . . . . . . . . . . . . 33

IDMA Read, Short Read Cycle in Short Read

FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

FUNCTIONAL BLOCK DIAGRAM . . . . . . . . . . . . . . . . 1

GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . 3

DEVELOPMENT SYSTEM . . . . . . . . . . . . . . . . . . . . . . . 3

Additional Information . . . . . . . . . . . . . . . . . . . . . . . . . . 3

ARCHITECTURE OVERVIEW . . . . . . . . . . . . . . . . . . . . 4

Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

PIN DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Common-Mode Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Memory Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Full Memory Mode Pins (Mode C = 0) . . . . . . . . . . . . . . 7

Host Mode Pins (Mode C = 1) . . . . . . . . . . . . . . . . . . . . 7

Terminating Unused Pins . . . . . . . . . . . . . . . . . . . . . . . . 8

Pin Terminations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

LOW POWER OPERATION . . . . . . . . . . . . . . . . . . . . . . . 9

Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Idle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Slow Idle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

SYSTEM INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

MODES OF OPERATION . . . . . . . . . . . . . . . . . . . . . . . 11

Setting Memory Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Passive Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Active Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

IACK Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

MEMORY ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . 12

Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Memory Mapped Registers (New to the

Only Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

100-LEAD LQFP PIN CONFIGURATION . . . . . . . . . . 35

LQFP Package Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

144-Ball Mini-BGA Package Pinout . . . . . . . . . . . . . . . . . 37

Mini-BGA Package Pinout . . . . . . . . . . . . . . . . . . . . . . . . 38

OUTLINE DIMENSIONS

100-Lead Metric Thin Plastic Quad Flatpack

(LQFP) (ST-100) . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

OUTLINE DIMENSIONS

ADSP-2185M) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

I/O Space (Full Memory Mode) . . . . . . . . . . . . . . . . . . . 13

Composite Memory Select (CMS) . . . . . . . . . . . . . . . . . 14

Byte Memory Select (BMS) . . . . . . . . . . . . . . . . . . . . . . 14

Byte Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Byte Memory DMA (BDMA, Full Memory Mode) . . . . 14

Internal Memory DMA Port

144-Ball Mini-BGA (CA-144) . . . . . . . . . . . . . . . . . . . . 40

ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

(IDMA Port; Host Memory Mode) . . . . . . . . . . . . . . 15

Bootstrap Loading (Booting) . . . . . . . . . . . . . . . . . . . . . 15

IDMA Port Booting . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Bus Request and Bus Grant . . . . . . . . . . . . . . . . . . . . . . 16

Flag I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Instruction Set Description . . . . . . . . . . . . . . . . . . . . . . 16

DESIGNING AN EZ-ICE-COMPATIBLE SYSTEM . . . 16

Target Board Connector for EZ-ICE Probe . . . . . . . . . . 17

Target Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . 17

PM, DM, BM, IOM, AND CM . . . . . . . . . . . . . . . . . . . . 17

Target System Interface Signals . . . . . . . . . . . . . . . . . . . 17

Tables

Table I. Interrupt Priority and Interrupt

Vector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table II. Modes of Operation . . . . . . . . . . . . . . . . . . . . . . 11

Table III. PMOVLAY Bits . . . . . . . . . . . . . . . . . . . . . . . . 12

Table IV. DMOVLAY Bits . . . . . . . . . . . . . . . . . . . . . . . . 13

Table V. Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table VI. Data Formats . . . . . . . . . . . . . . . . . . . . . . . . . . 14

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ADSP-2185M

GENERAL DESCRIPTION

The EZ-KIT Lite is a hardware/software kit offering a complete

evaluation environment for the ADSP-218x family: an ADSP-

2189M-based evaluation board with PC monitor software plus

assembler, linker, simulator, and PROM splitter software. The

ADSP-2189M EZ-KIT Lite is a low cost, easy to use hardware

platform on which you can quickly get started with your DSP

software design. The EZ-KIT Lite includes the following features:

The ADSP-2185M is a single-chip microcomputer optimized

for digital signal processing (DSP) and other high-speed numeric

processing applications.

The ADSP-2185M combines the ADSP-2100 family base archi-

tecture (three computational units, data address generators, and

a program sequencer) with two serial ports, a 16-bit internal DMA

port, a byte DMA port, a programmable timer, Flag I/O, exten-

sive interrupt capabilities, and on-chip program and data memory.

• 75 MHz ADSP-2189M

• Full 16-Bit Stereo Audio I/O with AD73322 Codec

• RS-232 Interface

• EZ-ICE Connector for Emulator Control

• DSP Demo Programs

• Evaluation Suite of VisualDSP

The ADSP-218x EZ-ICE^®Emulator aids in the hardware

debugging of an ADSP-2185M system. The ADSP-2185M

integrates on-chip emulation support with a 14-pin ICE-Port

interface. This interface provides a simpler target board connec-

tion that requires fewer mechanical clearance considerations

than other ADSP-2100 Family EZ-ICEs. The ADSP-2185M

device need not be removed from the target system when using

the EZ-ICE, nor are any adapters needed. Due to the small

footprint of the EZ-ICE connector, emulation can be supported

in final board designs.

The ADSP-2185M integrates 80K bytes of on-chip memory

configured as 16K words (24-bit) of program RAM, and 16K

words (16-bit) of data RAM. Power-down circuitry is also pro-

vided to meet the low power needs of battery-operated portable

equipment. The ADSP-2185M is available in a 100-lead LQFP

package and 144 Ball Mini-BGA.

In addition, the ADSP-2185M supports new instructions, which

include bit manipulations—bit set, bit clear, bit toggle, bit test—

new ALU constants, new multiplication instruction (× squared),

biased rounding, result-free ALU operations, I/O memory trans-

fers, and global interrupt masking, for increased flexibility.

Fabricated in a high-speed, low-power, CMOS process, the

ADSP-2185M operates with a 13.3 ns instruction cycle time.

Every instruction can execute in a single processor cycle.

The EZ-ICE performs a full range of functions, including:

The ADSP-2185M’s flexible architecture and comprehensive

instruction set allow the processor to perform multiple opera-

tions in parallel. In one processor cycle, the ADSP-2185M can:

• In-target operation

• Up to 20 breakpoints

• Single-step or full-speed operation

• Registers and memory values can be examined and altered

• PC upload and download functions

• Instruction-level emulation of program booting and execution

• Complete assembly and disassembly of instructions

• C source-level debugging

• Generate the next program address

• Fetch the next instruction

• Perform one or two data moves

• Update one or two data address pointers

• Perform a computational operation

This takes place while the processor continues to:

See Designing An EZ-ICE-Compatible Target System in the

ADSP-2100 Family EZ-Tools Manual (ADSP-2181 sections) as

well as the Designing an EZ-ICE-Compatible System section of

this data sheet for the exact specifications of the EZ-ICE target

board connector.

• Receive and transmit data through the two serial ports

• Receive and/or transmit data through the internal DMA port

• Receive and/or transmit data through the byte DMA port

• Decrement timer

Additional Information

DEVELOPMENT SYSTEM

This data sheet provides a general overview of ADSP-2185M

functionality. For additional information on the architecture and

instruction set of the processor, refer to the ADSP-2100 Family

User’s Manual. For more information about the development

tools, refer to the ADSP-2100 Family Development Tools

data sheet.

The ADSP-2100 Family Development Software, a complete set

of tools for software and hardware system development, supports

the ADSP-2185M. The System Builder provides a high-level

method for defining the architecture of systems under develop-

ment. The Assembler has an algebraic syntax that is easy to

program and debug. The Linker combines object files into an

executable file. The Simulator provides an interactive instruction-

level simulation with a reconfigurable user interface to display

different portions of the hardware environment.

EZ-ICE is a registered trademark of Analog Devices, Inc.

REV. 0

–3–

ADSP-2185M

POWER-DOWN

CONTROL

FULL MEMORY MODE

MEMORY

DATA ADDRESS

GENERATORS

PROGRAMMABLE

EXTERNAL

ADDRESS

BUS

PROGRAM

MEMORY

16K 24 BIT

DATA

PROGRAM

SEQUENCER

I/O

MEMORY

AND

FLAGS

DAG1 DAG2

؋

16K

؋

16 BIT

EXTERNAL

DATA

BUS

PROGRAM MEMORY ADDRESS

BYTE DMA

DATA MEMORY ADDRESS

PROGRAM MEMORY DATA

DATA MEMORY DATA

CONTROLLER

OR

EXTERNAL

DATA

BUS

SERIAL PORTS

ARITHMETIC UNITS

TIMER

SPORT0 SPORT1

ALU

MAC

SHIFTER

INTERNAL

DMA

PORT

ADSP-2100 BASE

ARCHITECTURE

HOST MODE

Figure 1. Functional Block Diagram

ARCHITECTURE OVERVIEW

(indirect addressing), it is post-modified by the value of one of

four possible modify registers. A length value may be associated

with each pointer to implement automatic modulo addressing

for circular buffers.

The ADSP-2185M instruction set provides flexible data moves

and multifunction (one or two data moves with a computation)

instructions. Every instruction can be executed in a single

processor cycle. The ADSP-2185M assembly language uses an

algebraic syntax for ease of coding and readability. A compre-

hensive set of development tools supports program development.

Efficient data transfer is achieved with the use of five

internal buses:

• Program Memory Address (PMA) Bus

• Program Memory Data (PMD) Bus

• Data Memory Address (DMA) Bus

• Data Memory Data (DMD) Bus

• Result (R) Bus

Figure 1 is an overall block diagram of the ADSP-2185M. The

processor contains three independent computational units:

the ALU, the multiplier/accumulator (MAC), and the shifter.

The computational units process 16-bit data directly and have

provisions to support multiprecision computations. The ALU

performs a standard set of arithmetic and logic operations;

division primitives are also supported. The MAC performs

single-cycle multiply, multiply/add, and multiply/subtract opera-

tions with 40 bits of accumulation. The shifter performs logical

and arithmetic shifts, normalization, denormalization, and

derive exponent operations.

The two address buses (PMA and DMA) share a single external

address bus, allowing memory to be expanded off-chip, and the

two data buses (PMD and DMD) share a single external data

bus. Byte memory space and I/O memory space also share the

external buses.

Program memory can store both instructions and data, permit-

ting the ADSP-2185M to fetch two operands in a single cycle,

one from program memory and one from data memory. The

ADSP-2185M can fetch an operand from program memory and

the next instruction in the same cycle.

The shifter can be used to efficiently implement numeric

format control, including multiword and block floating-point

representations.

The internal result (R) bus connects the computational units so

that the output of any unit may be the input of any unit on the

next cycle.

In lieu of the address and data bus for external memory connec-

tion, the ADSP-2185M may be configured for 16-bit Internal

DMA port (IDMA port) connection to external systems. The

IDMA port is made up of 16 data/address pins and five control

pins. The IDMA port provides transparent, direct access to the

DSPs on-chip program and data RAM.

A powerful program sequencer and two dedicated data address

generators ensure efficient delivery of operands to these computa-

tional units. The sequencer supports conditional jumps, subroutine

calls, and returns in a single cycle. With internal loop counters

and loop stacks, the ADSP-2185M executes looped code with

zero overhead; no explicit jump instructions are required to

maintain loops.

An interface to low-cost byte-wide memory is provided by the

Byte DMA port (BDMA port). The BDMA port is bidirectional

and can directly address up to four megabytes of external RAM

or ROM for off-chip storage of program overlays or data tables.

Two data address generators (DAGs) provide addresses for

simultaneous dual operand fetches (from data memory and

program memory). Each DAG maintains and updates four

address pointers. Whenever the pointer is used to access data

The byte memory and I/O memory space interface supports slow

memories and I/O memory-mapped peripherals with program-

mable wait state generation. External devices can gain control of

–4–

REV. 0

ADSP-2185M

external buses with bus request/grant signals (BR, BGH, and BG).

One execution mode (Go Mode) allows the ADSP-2185M to

continue running from on-chip memory. Normal execution

mode requires the processor to halt while buses are granted.

• SPORTs can use an external serial clock or generate their

own serial clock internally.

• SPORTs have independent framing for the receive and trans-

mit sections. Sections run in a frameless mode or with frame

synchronization signals internally or externally generated.

Frame sync signals are active high or inverted, with either of

two pulsewidths and timings.

The ADSP-2185M can respond to eleven interrupts. There can

be up to six external interrupts (one edge-sensitive, two level-

sensitive, and three configurable) and seven internal interrupts

generated by the timer, the serial ports (SPORTs), the Byte DMA

port, and the power-down circuitry. There is also a master

RESET signal. The two serial ports provide a complete synchro-

nous serial interface with optional companding in hardware and

a wide variety of framed or frameless data transmit and receive

modes of operation.

• SPORTs support serial data word lengths from 3 to 16 bits

and provide optional A-law and µ-law companding according

to CCITT recommendation G.711.

• SPORT receive and transmit sections can generate unique

interrupts on completing a data word transfer.

• SPORTs can receive and transmit an entire circular buffer of

data with only one overhead cycle per data word. An interrupt

is generated after a data buffer transfer.

Each port can generate an internal programmable serial clock or

accept an external serial clock.

The ADSP-2185M provides up to 13 general-purpose flag pins.

The data input and output pins on SPORT1 can be alternatively

configured as an input flag and an output flag. In addition, eight

flags are programmable as inputs or outputs, and three flags are

always outputs.

• SPORT0 has a multichannel interface to selectively receive

and transmit a 24 or 32 word, time- division multiplexed,

serial bitstream.

• SPORT1 can be configured to have two external interrupts

(IRQ0 and IRQ1) and the FI and FO signals. The internally

generated serial clock may still be used in this configuration.

A programmable interval timer generates periodic interrupts.

A 16-bit count register (TCOUNT) decrements every n pro-

cessor cycle, where n is a scaling value stored in an 8-bit register

(TSCALE). When the value of the count register reaches zero,

an interrupt is generated and the count register is reloaded from

a 16-bit period register (TPERIOD).

PIN DESCRIPTIONS

The ADSP-2185M is available in a 100-lead LQFP package

and a 144-Ball Mini-BGA package. In order to maintain maxi-

mum functionality and reduce package size and pin count, some

serial port, programmable flag, interrupt and external bus pins

have dual, multiplexed functionality. The external bus pins are

configured during RESET only, while serial port pins are soft-

ware configurable during program execution. Flag and interrupt

functionality is retained concurrently on multiplexed pins. In

cases where pin functionality is reconfigurable, the default state is

shown in plain text; alternate functionality is shown in italics.

Serial Ports

The ADSP-2185M incorporates two complete synchronous

serial ports (SPORT0 and SPORT1) for serial communications

and multiprocessor communication.

Here is a brief list of the capabilities of the ADSP-2185M

SPORTs. For additional information on Serial Ports, refer to

the ADSP-2100 Family User’s Manual.

• SPORTs are bidirectional and have a separate, double-

buffered transmit and receive section.

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–5–

ADSP-2185M

Common-Mode Pins

Pin Name

# of Pins

I/O

Function

RESET

BR

1

I

Processor Reset Input

Bus Request Input

Bus Grant Output

BG

O

BGH

DMS

PMS

IOMS

BMS

CMS

RD

Bus Grant Hung Output

Data Memory Select Output

Program Memory Select Output

Memory Select Output

Byte Memory Select Output

Combined Memory Select Output

Memory Read Enable Output

Memory Write Enable Output

WR

IRQ2

PF7

1

I

I/O

Edge- or Level-Sensitive Interrupt Request¹

Programmable I/O Pin

Level-Sensitive Interrupt Requests¹

Programmable I/O Pin

Level-Sensitive Interrupt Requests¹

Programmable I/O Pin

Edge-Sensitive Interrupt Requests¹

Programmable I/O Pin

IRQL1

PF6

I

I/O

IRQL0

PF5

I

I/O

IRQE

PF4

I

I/O

Mode D

PF3

I

I/O

Mode Select Input—Checked Only During RESET

Programmable I/O Pin During Normal Operation

Mode C

PF2

I

I/O

Mode Select Input—Checked Only During RESET

Programmable I/O Pin During Normal Operation

Mode B

PF1

I

I/O

Mode Select Input—Checked Only During RESET

Programmable I/O Pin During Normal Operation

Mode A

I

Mode Select Input—Checked Only During RESET

PF0

I/O

Programmable I/O Pin During Normal Operation

CLKIN, XTAL

CLKOUT

SPORT0

SPORT1

IRQ1:0, FI, FO

2

1

5

I

O

I/O

Clock or Quartz Crystal Input

Processor Clock Output

Serial Port I/O Pins

Edge- or Level-Sensitive Interrupts, FI, FO²

PWD

1

3

2

4

10

4

7

20

9

I

Power-Down Control Input

Power-Down Control Output

Output Flags

Internal V_DD(2.5 V) Power (LQFP)

External V_DD(2.5 V or 3.3 V) Power (LQFP)

Ground (LQFP)

Internal V_DD(2.5 V) Power (Mini-BGA)

External V_DD(2.5 V or 3.3 V) Power (Mini-BGA)

Ground (Mini-BGA)

PWDACK

FL0, FL1, FL2

V_DDINT

V_DDEXT

GND

V_DDINT

V_DDEXT

GND

O

I

EZ-Port

I/O

For Emulation Use

NOTES

¹Interrupt/Flag pins retain both functions concurrently. If IMASK is set to enable the corresponding interrupts, then the DSP will vector to the appropriate interrupt

vector address when the pin is asserted, either by external devices, or set as a programmable flag.

²SPORT configuration determined by the DSP System Control Register. Software configurable.

–6–

REV. 0

ADSP-2185M

Memory Interface Pins

The ADSP-2185M processor can be used in one of two modes: Full Memory Mode, which allows BDMA operation with full exter-

nal overlay memory and I/O capability, or Host Mode, which allows IDMA operation with limited external addressing capabilities.

The operating mode is determined by the state of the Mode C pin during RESET and cannot be changed while the processor is running.

The following tables list the active signals at specific pins of the DSP during either of the two operating modes (Full Memory or

Host). A signal in one table shares a pin with a signal from the other table, with the active signal determined by the mode set. For the

shared pins and their alternate signals (e.g., A4/IAD3), refer to the package pinout tables.

Full Memory Mode Pins (Mode C = 0)

Pin Name

# of Pins

I/O

Function

A13:0

D23:0

14

24

O

I/O

Address Output Pins for Program, Data, Byte, and I/O Spaces

Data I/O Pins for Program, Data, Byte, and I/O Spaces (8 MSBs are also

used as Byte Memory Addresses.)

Host Mode Pins (Mode C = 1)

Pin Name

# of Pins

I/O

Function

IAD15:0

A0

D23:8

IWR

IRD

16

1

16

1

I/O

O

I/O

I

IDMA Port Address/Data Bus

Address Pin for External I/O, Program, Data, or Byte Access¹

Data I/O Pins for Program, Data, Byte, and I/O Spaces

IDMA Write Enable

1

I

IDMA Read Enable

IAL

1

I

IDMA Address Latch Pin

IS

1

I

IDMA Select

IACK

1

O

IDMA Port Acknowledge Configurable in Mode D; Open Drain

NOTE

¹In Host Mode, external peripheral addresses can be decoded using the A0, CMS, PMS, DMS, and IOMS signals.

REV. 0

–7–

ADSP-2185M

Terminating Unused Pins

The following table shows the recommendations for terminating unused pins.

Pin Terminations

I/O 3-State

(Z)

Reset

State

Hi-Z*

Caused By

Pin Name

Unused Configuration

XTAL

CLKOUT

A13:1 or

IAD 12:0

A0

D23:8

D7 or

I

O

I

O

Float

High (Inactive)

O (Z)

I/O (Z)

O (Z)

I/O (Z)

I

Hi-Z

I

BR, EBR

IS

BR, EBR

IWR

D6 or

IRD

I/O (Z)

I

Hi-Z

I

BR, EBR

Float

High (Inactive)

D5 or

IAL

I/O (Z)

I

Hi-Z

I

Float

Low (Inactive)

D4 or

IS

D3 or

I/O (Z)

I

I/O (Z)

Hi-Z

I

Hi-Z

BR, EBR

Float

High (Inactive)

Float

IACK

D2:0 or

IAD15:13

PMS

DMS

BMS

IOMS

CMS

RD

WR

BR

Float

I/O (Z)

O (Z)

Hi-Z

BR, EBR

IS

Hi-Z

O

I

BR, EBR

Float

High (Inactive)

O (Z)

I

BG

BGH

O (Z)

O

I/O (Z)

I/O

I

O

I

EE

Float

IRQ2/PF7

IRQL1/PF6

IRQL0/PF5

IRQE/PF4

SCLK0

RFS0

Input = High (Inactive) or Program as Output, Set to 1, Let Float

Input = High or Low, Output = Float

High or Low

DR0

TFS0

DT0

I/O

O

I/O

I

I/O

O

I

O

I

O

I

High or Low

Float

Input = High or Low, Output = Float

High or Low

Float

SCLK1

RFS1/IRQ0

DR1/FI

TFS1/IRQ1

DT1/FO

EE

Float

EBR

I

Float

EBG

O

Float

ERESET

EMS

EINT

ECLK

ELIN

I

O

I

O

I

Float

ELOUT

O

Float

NOTES

*Hi-Z = High Impedance.

1. If the CLKOUT pin is not used, turn it OFF, using CLKODIS in SPORT0 autobuffer control register.

2. If the Interrupt/Programmable Flag pins are not used, there are two options: Option 1: When these pins are configured as INPUTS at reset and function as inter-

rupts and input flag pins, pull the pins High (inactive). Option 2: Program the unused pins as OUTPUTS, set them to 1, prior to enabling interrupts, and let pins float.

3. All bidirectional pins have three-stated outputs. When the pin is configured as an output, the output is Hi-Z (high impedance) when inactive.

4. CLKIN, RESET, and PF3:0/MODE D:A are not included in the table because these pins must be used.

–8–

REV. 0

ADSP-2185M

Interrupts

of the state of IMASK. Disabling the interrupts does not affect

serial port autobuffering or DMA.

The interrupt controller allows the processor to respond to the

11 possible interrupts and reset with minimum overhead. The

ADSP-2185M provides four dedicated external interrupt input

pins: IRQ2, IRQL0, IRQL1, and IRQE (shared with the PF7:4

pins). In addition, SPORT1 may be reconfigured for IRQ0,

IRQ1, FI and FO, for a total of six external interrupts. The

ADSP-2185M also supports internal interrupts from the timer,

the byte DMA port, the two serial ports, software, and the power-

down control circuit. The interrupt levels are internally prioritized

and individually maskable (except power- down and reset). The

IRQ2, IRQ0, and IRQ1 input pins can be programmed to be

either level- or edge-sensitive. IRQL0 and IRQL1 are level-

sensitive and IRQE is edge-sensitive. The priorities and vector

addresses of all interrupts are shown in Table I.

ENA INTS;

DIS INTS;

When the processor is reset, interrupt servicing is enabled.

LOW POWER OPERATION

The ADSP-2185M has three low power modes that significantly

reduce the power dissipation when the device operates under

standby conditions. These modes are:

• Power-Down

• Idle

• Slow Idle

The CLKOUT pin may also be disabled to reduce external

power dissipation.

Table I. Interrupt Priority and Interrupt Vector Addresses

Interrupt Vector

Power-Down

The ADSP-2185M processor has a low power feature that lets

the processor enter a very low-power dormant state through

hardware or software control. Following is a brief list of power-

down features. Refer to the ADSP-2100 Family User’s Manual,

“System Interface” chapter, for detailed information about the

power-down feature.

Source Of Interrupt

Address (Hex)

Reset (or Power-Up with PUCR = 1)

Power-Down (Nonmaskable)

IRQ2

0000 (Highest Priority)

002C

0004

0008

IRQL1

IRQL0

000C

0010

0014

0018

001C

0020

0024

• Quick recovery from power-down. The processor begins

executing instructions in as few as 200 CLKIN cycles.

SPORT0 Transmit

SPORT0 Receive

IRQE

BDMA Interrupt

SPORT1 Transmit or IRQ1

SPORT1 Receive or IRQ0

Timer

• Support for an externally generated TTL or CMOS processor

clock. The external clock can continue running during power-

down without affecting the lowest power rating and 200 CLKIN

cycle recovery.

• Support for crystal operation includes disabling the oscillator

to save power (the processor automatically waits approximately

4096 CLKIN cycles for the crystal oscillator to start or stabi-

lize), and letting the oscillator run to allow 200 CLKIN cycle

start-up.

0028 (Lowest Priority)

Interrupt routines can either be nested with higher priority inter-

rupts taking precedence or processed sequentially. Interrupts

can be masked or unmasked with the IMASK register. Individual

interrupt requests are logically ANDed with the bits in IMASK;

the highest priority unmasked interrupt is then selected. The

power-down interrupt is nonmaskable.

• Power-down is initiated by either the power-down pin (PWD)

or the software power-down force bit. Interrupt support allows

an unlimited number of instructions to be executed before

optionally powering down. The power-down interrupt also

can be used as a nonmaskable, edge-sensitive interrupt.

The ADSP-2185M masks all interrupts for one instruction

cycle following the execution of an instruction that modifies the

IMASK register. This does not affect serial port autobuffering

or DMA transfers.

• Context clear/save control allows the processor to continue

where it left off or start with a clean context when leaving the

power-down state.

The interrupt control register, ICNTL, controls interrupt nest-

ing and defines the IRQ0, IRQ1, and IRQ2 external interrupts

to be either edge- or level-sensitive. The IRQE pin is an exter-

nal edge sensitive interrupt and can be forced and cleared. The

IRQL0 and IRQL1 pins are external level sensitive interrupts.

• The RESET pin also can be used to terminate power-down.

• Power-down acknowledge pin indicates when the processor

has entered power-down.

Idle

The IFC register is a write-only register used to force and clear

interrupts. On-chip stacks preserve the processor status and are

automatically maintained during interrupt handling. The stacks

are twelve levels deep to allow interrupt, loop, and subroutine

nesting. The following instructions allow global enable or disable

servicing of the interrupts (including power down), regardless

When the ADSP-2185M is in the Idle Mode, the processor

waits indefinitely in a low-power state until an interrupt occurs.

When an unmasked interrupt occurs, it is serviced; execution

then continues with the instruction following the IDLE instruc-

tion. In Idle mode IDMA, BDMA and autobuffer cycle steals

still occur.

REV. 0

–9–

ADSP-2185M

Slow Idle

ADSP-2185M also provides four external interrupts and two

serial ports or six external interrupts and one serial port. Host

Memory Mode allows access to the full external data bus, but

limits addressing to a single address bit (A0). Through the use

of external hardware, additional system peripherals can be added

in this mode to generate and latch address signals.

The IDLE instruction is enhanced on the ADSP-2185M to let

the processor’s internal clock signal be slowed, further reducing

power consumption. The reduced clock frequency, a program-

mable fraction of the normal clock rate, is specified by a selectable

divisor given in the IDLE instruction.

The format of the instruction is:

Clock Signals

The ADSP-2185M can be clocked by either a crystal or a

TTL-compatible clock signal.

IDLE (n);

where n = 16, 32, 64, or 128. This instruction keeps the proces-

sor fully functional, but operating at the slower clock rate. While

it is in this state, the processor’s other internal clock signals, such

as SCLK, CLKOUT, and timer clock, are reduced by the same

ratio. The default form of the instruction, when no clock divisor

is given, is the standard IDLE instruction.

The CLKIN input cannot be halted, changed during opera-

tion, nor operated below the specified frequency during normal

operation. The only exception is while the processor is in the

power-down state. For additional information, refer to Chap-

ter 9, ADSP-2100 Family User’s Manual, for detailed information

on this power-down feature.

When the IDLE (n) instruction is used, it effectively slows down

the processor’s internal clock and thus its response time to incom-

ing interrupts. The one-cycle response time of the standard idle

state is increased by n, the clock divisor. When an enabled inter-

rupt is received, the ADSP-2185M will remain in the idle state

for up to a maximum of n processor cycles (n = 16, 32, 64, or

128) before resuming normal operation.

If an external clock is used, it should be a TTL-compatible signal

running at half the instruction rate. The signal is connected to

the processor’s CLKIN input. When an external clock is used,

the XTAL input must be left unconnected.

The ADSP-2185M uses an input clock with a frequency equal to

half the instruction rate; a 37.50 MHz input clock yields a 13 ns

processor cycle (which is equivalent to 75 MHz). Normally,

instructions are executed in a single processor cycle. All device

timing is relative to the internal instruction clock rate, which is

indicated by the CLKOUT signal when enabled.

When the IDLE (n) instruction is used in systems that have an

externally generated serial clock (SCLK), the serial clock rate

may be faster than the processor’s reduced internal clock rate.

Under these conditions, interrupts must not be generated at a

faster than can be serviced, due to the additional time the

processor takes to come out of the idle state (a maximum of n

processor cycles).

Because the ADSP-2185M includes an on-chip oscillator circuit,

an external crystal may be used. The crystal should be connected

across the CLKIN and XTAL pins, with two capacitors con-

nected as shown in Figure 3. Capacitor values are dependent on

crystal type and should be specified by the crystal manufacturer.

A parallel-resonant, fundamental frequency, microprocessor-

grade crystal should be used.

SYSTEM INTERFACE

Figure 2 shows typical basic system configurations with the

ADSP-2185M, two serial devices, a byte-wide EPROM, and

optional external program and data overlay memories (mode-

selectable). Programmable wait state generation allows the

processor to connect easily to slow peripheral devices. The

A clock output (CLKOUT) signal is generated by the processor

at the processor’s cycle rate. This can be enabled and disabled by

the CLKODIS bit in the SPORT0 Autobuffer Control Register.

HOST MEMORY MODE

ADSP-2185M

FULL MEMORY MODE

1/2x CLOCK

OR

CLKIN

XTAL

FL0–2

CLKIN

1/2x CLOCK

OR

A

14

13–0

XTAL

CRYSTAL

1

ADDR13–0

DATA23–0

A0

D

A0–A21

23–16

FL0–2

BYTE

IRQ2/PF7

IRQE/PF4

IRQL0/PF5

IRQL1/PF6

16

24

D

IRQ2/PF7

IRQE/PF4

IRQL0/PF5

IRQL1/PF6

15–8

MEMORY

DATA23–8

DATA

ADSP-2185M

BMS

WR

CS

BMS

MODE D/PF3

MODE C/PF2

MODE A/PF0

MODE B/PF1

A

10–0

WR

RD

MODE D/PF3

MODE C/PF2

MODE A/PF0

MODE B/PF1

ADDR

RD

I/O SPACE

D

23–8

(PERIPHERALS)

2048 LOCATIONS

DATA

SPORT1

IOMS

CS

IOMS

SPORT1

SCLK1

RFS1 OR IRQ0

TFS1 OR IRQ1

DT1 OR FO

DR1 OR FI

A

D

13–0

ADDR

DATA

SERIAL

DEVICE

OVERLAY

MEMORY

RFS1 OR IRQ0

TFS1 OR IRQ1

DT1 OR FO

SERIAL

DEVICE

23–0

TWO 8K

PMS

DMS

CMS

PMS

DMS

CMS

DR1 OR F

I

PM SEGMENTS

SPORT0

SCLK0

RFS0

TFS0

DT0

TWO 8K

SPORT0

DM SEGMENTS

SERIAL

DEVICE

SCLK0

RFS0

TFS0

DT0

BR

BG

BGH

BR

BG

BGH

SERIAL

DEVICE

DR0

PWD

DR0

IDMA PORT

PWDACK

IRD/D6

IWR/D7

IS/D4

IAL/D5

IACK/D3

SYSTEM

INTERFACE

OR

␮CONTROLLER

IAD15–0

16

Figure 2. Basic System Interface

–10–

REV. 0

ADSP-2185M

performed. The first instruction is fetched from on-chip pro-

gram memory location 0x0000 once boot loading completes.

CLKIN

XTAL

CLKOUT

Power Supplies

The ADSP-2185M has separate power supply connections for

the internal (V_DDINT) and external (V_DDEXT) power supplies.

The internal supply must meet the 2.5 V requirement. The

external supply can be connected to either a 2.5 V or 3.3 V supply.

All external supply pins must be connected to the same supply.

All input and I/O pins can tolerate input voltages up to 3.6 V,

regardless of the external supply voltage. This feature provides

maximum flexibility in mixing 2.5 V and 3.3 V components.

DSP

Figure 3. External Crystal Connections

RESET

The RESET signal initiates a master reset of the ADSP-2185M.

The RESET signal must be asserted during the power-up

sequence to assure proper initialization. RESET during initial

power-up must be held long enough to allow the internal clock

to stabilize. If RESET is activated any time after power-up, the

clock continues to run and does not require stabilization time.

MODES OF OPERATION

Setting Memory Mode

Memory Mode selection for the ADSP-2185M is made during

chip reset through the use of the Mode C pin. This pin is multi-

plexed with the DSP’s PF2 pin, so care must be taken in how

the mode selection is made. The two methods for selecting the

value of Mode C are active and passive.

The power-up sequence is defined as the total time required for the

crystal oscillator circuit to stabilize after a valid V_DDis applied to

the processor, and for the internal phase-locked loop (PLL) to lock

onto the specific crystal frequency. A minimum of 2000 CLKIN

cycles ensures that the PLL has locked but does not include the

crystal oscillator start-up time. During this power-up sequence

the RESET signal should be held low. On any subsequent resets,

the RESET signal must meet the minimum pulsewidth specifi-

Passive Configuration

Passive Configuration involves the use a pull-up or pull-down

resistor connected to the Mode C pin. To minimize power con-

sumption, or if the PF2 pin is to be used as an output in the DSP

application, a weak pull-up or pull-down, on the order of 10 kΩ,

can be used. This value should be sufficient to pull the pin to the

desired level and still allow the pin to operate as a programmable

flag output without undue strain on the processor’s output driver.

For minimum power consumption during power-down, recon-

figure PF2 to be an input, as the pull-up or pull-down will

hold the pin in a known state, and will not switch.

cation, t_RSP

.

The RESET input contains some hysteresis; however, if an

RC circuit is used to generate the RESET signal, the use of an

external Schmidt trigger is recommended.

The master reset sets all internal stack pointers to the empty stack

condition, masks all interrupts, and clears the MSTAT register.

When RESET is released, if there is no pending bus request and

the chip is configured for booting, the boot-loading sequence is

Table II. Modes of Operation

MODE D

MODE C

MODE B

MODE A

Booting Method

X

0

BDMA feature is used to load the first 32 program memory words from

the byte memory space. Program execution is held off until all 32 words

have been loaded. Chip is configured in Full Memory Mode.¹

X

0

1

0

No automatic boot operations occur. Program execution starts at external

memory location 0. Chip is configured in Full Memory Mode. BDMA can

still be used, but the processor does not automatically use or wait for these

operations.

BDMA feature is used to load the first 32 program memory words from

the byte memory space. Program execution is held off until all 32 words

have been loaded. Chip is configured in Host Mode. IACK has active

pull-down. (REQUIRES ADDITIONAL HARDWARE).

0

1

0

1

0

IDMA feature is used to load any internal memory as desired. Program

execution is held off until internal program memory location 0 is written

to. Chip is configured in Host Mode. IACK has active pull-down.¹

BDMA feature is used to load the first 32 program memory words from

the byte memory space. Program execution is held off until all 32 words

have been loaded. Chip is configured in Host Mode; IACK requires exter-

nal pull down. (REQUIRES ADDITIONAL HARDWARE)

1

0

1

IDMA feature is used to load any internal memory as desired. Program

execution is held off until internal program memory location 0 is written

to. Chip is configured in Host Mode. IACK requires external pull-down.¹

NOTE

¹Considered as standard operating settings. Using these configurations allows for easier design and better memory management.

REV. 0

–11–

ADSP-2185M

Active Configuration

MEMORY ARCHITECTURE

Active Configuration involves the use of a three-statable external

driver connected to the Mode C pin. A driver’s output enable

should be connected to the DSP’s RESET signal such that it

only drives the PF2 pin when RESET is active (low). When

RESET is deasserted, the driver should three-state, thus allow-

ing full use of the PF2 pin as either an input or output. To

minimize power consumption during power-down, configure

the programmable flag as an output when connected to a three-

stated buffer. This ensures that the pin will be held at a constant

level, and will not oscillate should the three-state driver’s level

hover around the logic switching point.

The ADSP-2185M provides a variety of memory and peripheral

interface options. The key functional groups are Program Memory,

Data Memory, Byte Memory, and I/O. Refer to the following

figures and tables for PM and DM memory allocations in the

ADSP-2185M.

Program Memory

Program Memory (Full Memory Mode) is a 24-bit-wide

space for storing both instruction opcodes and data. The ADSP-

2185M has 16K words of Program Memory RAM on chip, and

the capability of accessing up to two 8K external memory over-

lay spaces using the external data bus.

IACK Configuration

Mode D = 0 and in host mode: IACK is an active, driven signal

and cannot be “wire OR’d.”

Program Memory (Host Mode) allows access to all internal

memory. External overlay access is limited by a single external

address line (A0). External program execution is not available in

host mode due to a restricted data bus that is 16 bits wide only.

Mode D = 1 and in host mode: IACK is an open drain and

requires an external pull-down, but multiple IACK pins can be

“wire OR’d” together.

PM (MODE B = 1)¹

PM (MODE B = 0)

ALWAYS

ACCESSIBLE

AT ADDRESS

0x0000 – 0x1FFF

RESERVED

0x2000 –

0x3FFF

ACCESSIBLE WHEN

PMOVLAY = 0

0x2000 –

0x3FFF

0

x

0000 –

0

1FFF²

ACCESSIBLE WHEN

PMOVLAY = 0

0

x

0000 –

ACCESSIBLE WHEN

PMOVLAY = 0

0

1FFF²

0

x

2000 –

0

3FFF²

ACCESSIBLE WHEN

PMOVLAY = 1

EXTERNAL

MEMORY

RESERVED

0x

2000 –

3FFF²

NOTES:

¹WHEN MODE B = 1, PMOVLAY MUST BE SET TO 0

ACCESSIBLE WHEN

PMOVLAY = 2

EXTERNAL

MEMORY

²SEE TABLE III FOR PMOVLAY BITS

PROGRAM MEMORY

MODE B = 0

MODE B = 1

ADDRESS

0

x

3FFF

0

x3FFF

8K INTERNAL

PMOVLAY = 0

OR

8K EXTERNAL

PMOVLAY = 1, 2

8K INTERNAL

PMOVLAY = 0

0x

2000

0x

2000

0

x1FFF

0

x1FFF

8K

EXTERNAL

INTERNAL

0x0000

Figure 4. Program Memory

Table III. PMOVLAY Bits

PMOVLAY

Memory

A13

A12:0

0

1

2

Internal

External Overlay 1

External Overlay 2

Not Applicable

0

1

Not Applicable

13 LSBs of Address Between 0x2000 and 0x3FFF

–12–

REV. 0

ADSP-2185M

Data Memory

complete in one cycle. Accesses to external memory are timed

using the wait states specified by the DWAIT register and the

wait state mode bit.

Data Memory (Full Memory Mode) is a 16-bit-wide space used

for the storage of data variables and for memory-mapped control

registers. The ADSP-2185M has 16K words on Data Memory

RAM on-chip. Part of this space is used by 32 memory-mapped

registers. Support also exists for up to two 8K external memory

overlay spaces through the external data bus. All internal accesses

Data Memory (Host Mode) allows access to all internal memory.

External overlay access is limited by a single external address

line (A0).

DATA MEMORY

ADDR

0

x

3FFF

32 MEMORY

MAPPED

ALWAYS

ACCESSIBLE

AT ADDRESS

0x2000 – 0x3FFF

REGISTERS

0

x3FE0

0

x

3FDF

INTERNAL

8160 WORDS

0

x

2000

1FFF

0x0000 – 0x1FFF

x

8K INTERNAL

DMOVLAY = 0

OR

ACCESSIBLE WHEN

DM OVLAY = 0

1

0

x0000 – 0

x1FFF

EXTERNAL 8K

DMOVLAY = 1, 2

1

0

x0000 – 0x1FFF

0

x0000

ACCESSIBLE WHEN

DMOVLAY = 1

EXTERNAL

MEMORY

NOTE:

ACCESSIBLE WHEN

DMOVLAY = 2

1

SEE TABLE IV FOR DMOVAY BITS

Figure 5. Data Memory Map

Table IV. DMOVLAY Bits

DMOVLAY

Memory

A13

A12:0

0

1

2

Internal

External Overlay 1

External Overlay 2

Not Applicable

0

1

Not Applicable

13 LSBs of Address Between 0x2000 and 0x3FFF

SYSTEM CONTROL

Memory Mapped Registers (New to the ADSP-2185M)

The ADSP-2185M has three memory mapped registers that differ

from other ADSP-21xx Family DSPs. The slight modifications

to these registers (Wait State Control, Programmable Flag and

Composite Select Control, and System Control) provide the

ADSP-2185M’s wait state and BMS control features. Default

bit values at reset are shown; if no value is shown, the bit is unde-

fined at reset. Reserved bits are shown on a grey field. These bits

should always be written with zeros.

15 14 13 12 11 10

9

0

8

0

7

0

6

0

5

0

4

0

3

0

2

1

0

1

DM(0x3FFF)

0

1

RESERVED

SET TO 0

RESERVED, ALWAYS

SET TO 0

PWAIT

PROGRAM MEMORY

WAIT STATES

SPORT0 ENABLE

0 = DISABLE

1 = ENABLE

DISABLE BMS

0 = ENABLE BMS

1 = DISABLE BMS, EXCEPT WHEN MEMORY

STROBES ARE THREE-STATED

SPORT1 ENABLE

0 = DISABLE

1 = ENABLE

WAITSTATE CONTROL

SPORT1 CONFIGURE

0 = FI, FO, IRQ0, IRQ1, SCLK

1 = SPORT1

15 14 13 12 11 10

9

1

8

1

7

1

6

1

5

1

4

1

3

1

2

1

0

1

DM(0

؋

3FFE)

1

NOTE: RESERVED BITS ARE SHOWN ON A GRAY FIELD. THESE BITS SHOULD

ALWAYS BE WRITTEN WITH ZEROS.

DWAIT

IOWAIT3

IOWAIT2 IOWAIT1 IOWAIT0

Figure 8. System Control Register

WAIT STATE MODE SELECT

0 = NORMAL MODE (PWAIT, DWAIT, IOWAIT0–3 = N WAIT STATES, RANGING

I/O Space (Full Memory Mode)

FROM 0 TO 7)

1 = 2N + 1 MODE (PWAIT, DWAIT, IOWAIT0–3 = 2N + 1 WAIT STATES, RANGING

The ADSP-2185M supports an additional external memory

space called I/O space. This space is designed to support simple

connections to peripherals (such as data converters and external

registers) or to bus interface ASIC data registers. I/O space sup-

ports 2048 locations of 16-bit wide data. The lower eleven bits

of the external address bus are used; the upper three bits are

undefined. Two instructions were added to the core ADSP-2100

Family instruction set to read from and write to I/O memory

space. The I/O space also has four dedicated three-bit wait state

registers, IOWAIT0–3, which in combination with the wait state

mode bit, specify up to 15 wait states to be automatically gener-

ated for each of four regions. The wait states act on address

ranges as shown in Table V.

FROM 0 TO 15)

Figure 6. Wait State Control Register

PROGRAMMABLE FLAG AND COMPOSITE SELECT CONTROL

15 14 13 12 11 10

9

1

8

1

7

0

6

0

5

0

4

0

3

0

2

0

1

0

1

0

DM(0x3FE6)

BMWAIT

CMSSEL

0 = DISABLE CMS

1 = ENABLE CMS

PFTYPE

0 = INPUT

1 = OUTPUT

(WHERE BIT: 11-IOM, 10-BM, 9-DM, 8-PM)

Figure 7. Programmable Flag and Composite Control

Register

REV. 0

–13–

ADSP-2185M

BDMA CONTROL

Table V. Wait States

15 14 13 12 11 10

9

8

7

6

5

4

0

3

1

2

0

1

0

DM (0

؋

3FE3)

0

Address Range

Wait State Register

BTYPE

BDIR

0x000–0x1FF

0x200–0x3FF

0x400–0x5FF

0x600–0x7FF

IOWAIT0 and Wait State Mode Select Bit

IOWAIT1 and Wait State Mode Select Bit

IOWAIT2 and Wait State Mode Select Bit

IOWAIT3 and Wait State Mode Select Bit

BMPAGE

BDMA

OVERLAY

BITS

0 = LOAD FROM BM

1 = STORE TO BM

BCR

0 = RUN DURING BDMA

1 = HALT DURING BDMA

Composite Memory Select (CMS)

Figure 9. BDMA Control Register

The ADSP-2185M has a programmable memory select signal that

is useful for generating memory select signals for memories

mapped to more than one space. The CMS signal is gener-

ated to have the same timing as each of the individual memory

select signals (PMS, DMS, BMS, IOMS) but can combine their

functionality.

The BDMA circuit supports four different data formats that are

selected by the BTYPE register field. The appropriate number

of 8-bit accesses are done from the byte memory space to build

the word size selected. Table VI shows the data formats sup-

ported by the BDMA circuit.

Each bit in the CMSSEL register, when set, causes the CMS

signal to be asserted when the selected memory select is

asserted. For example, to use a 32K word memory to act as both

program and data memory, set the PMS and DMS bits in the

CMSSEL register and use the CMS pin to drive the chip

select of the memory, and use either DMS or PMS as the

additional address bit.

Table VI. Data Formats

BTYPE Internal Memory Space Word Size Alignment

00

01

10

11

Program Memory

Data Memory

24

16

8

Full Word

MSBs

8

LSBs

The CMS pin functions like the other memory select signals

with the same timing and bus request logic. A 1 in the enable bit

causes the assertion of the CMS signal at the same time as the

selected memory select signal. All enable bits default to 1 at reset,

except the BMS bit.

Unused bits in the 8-bit data memory formats are filled with 0s.

The BIAD register field is used to specify the starting address

for the on-chip memory involved with the transfer. The 14-bit

BEAD register specifies the starting address for the external byte

memory space. The 8-bit BMPAGE register specifies the start-

ing page for the external byte memory space. The BDIR register

field selects the direction of the transfer. Finally, the 14-bit

BWCOUNT register specifies the number of DSP words to

transfer and initiates the BDMA circuit transfers.

Byte Memory Select (BMS)

The ADSP-2185M’s BMS disable feature combined with the

CMS pin allows use of multiple memories in the byte memory

space. For example, an EPROM could be attached to the BMS

select, and an SRAM could be connected to CMS. Because at

reset BMS is enabled, the EPROM would be used for booting.

After booting, software could disable BMS and set the CMS

signal to respond to BMS, enabling the SRAM.

BDMA accesses can cross page boundaries during sequential

addressing. A BDMA interrupt is generated on the completion

of the number of transfers specified by the BWCOUNT register.

Byte Memory

The BWCOUNT register is updated after each transfer so it can

be used to check the status of the transfers. When it reaches zero,

the transfers have finished and a BDMA interrupt is generated.

The BMPAGE and BEAD registers must not be accessed by the

DSP during BDMA operations.

The byte memory space is a bidirectional, 8-bit-wide, external

memory space used to store programs and data. Byte memory is

accessed using the BDMA feature. The byte memory space con-

sists of 256 pages, each of which is 16K × 8.

The byte memory space on the ADSP-2185M supports read and

write operations as well as four different data formats. The byte

memory uses data bits 15:8 for data. The byte memory uses data

bits 23:16 and address bits 13:0 to create a 22-bit address. This

allows up to a 4 meg × 8 (32 megabit) ROM or RAM to be used

without glue logic. All byte memory accesses are timed by the

BMWAIT register and the wait state mode bit.

The source or destination of a BDMA transfer will always be

on-chip program or data memory.

When the BWCOUNT register is written with a nonzero value

the BDMA circuit starts executing byte memory accesses with wait

states set by BMWAIT. These accesses continue until the count

reaches zero. When enough accesses have occurred to create a

destination word, it is transferred to or from on-chip memory.

The transfer takes one DSP cycle. DSP accesses to external

memory have priority over BDMA byte memory accesses.

Byte Memory DMA (BDMA, Full Memory Mode)

The byte memory DMA controller allows loading and storing of

program instructions and data using the byte memory space. The

BDMA circuit is able to access the byte memory space while the

processor is operating normally and steals only one DSP cycle

per 8-, 16- or 24-bit word transferred.

The BDMA Context Reset bit (BCR) controls whether the

processor is held off while the BDMA accesses are occurring.

Setting the BCR bit to 0 allows the processor to continue opera-

tions. Setting the BCR bit to 1 causes the processor to stop

execution while the BDMA accesses are occurring, to clear the

context of the processor, and start execution at address 0 when

the BDMA accesses have completed.

–14–

REV. 0

ADSP-2185M

The BDMA overlay bits specify the OVLAY memory blocks to

be accessed for internal memory. For ADSP-2185M, set to zero

BDMA overlay bits in BDMA control register.

Through the IDMAA register, the DSP can also specify the

starting address and data format for DMA operation. Asserting

the IDMA port select (IS) and address latch enable (IAL) directs

the ADSP-2185M to write the address onto the IAD0–14 bus

into the IDMA Control Register. If Bit 15 is set to 0, IDMA

latches the address. If Bit 15 is set to 1, IDMA latches into the

OVLAY register. This register, shown below, is memory mapped

at address DM (0x3FE0). Note that the latched address (IDMAA)

cannot be read back by the host. When Bit 14 in 0x3FE7 is set

to 1, timing in Figure 31 applies for short reads. When Bit 14

in 0x3FE7 is set to zero, short reads use the timing shown in Fig-

ure 32. For ADSP-2185M, IDDMOVLAY and IDPMOVLAY

bits in IDMA overlay register should be set to zero.

The BMWAIT field, which has 4 bits on ADSP-2185M, allows

selection up to 15 wait states for BDMA transfers.

Internal Memory DMA Port (IDMA Port; Host Memory

Mode)

The IDMA Port provides an efficient means of communication

between a host system and the ADSP-2185M. The port is used

to access the on-chip program memory and data memory of the

DSP with only one DSP cycle per word overhead. The IDMA

port cannot, however, be used to write to the DSP’s memory-

mapped control registers. A typical IDMA transfer process is

described as follows:

Refer to the following figures for more information on IDMA

and DMA memory maps.

1. Host starts IDMA transfer

IDMA OVERLAY

2. Host checks IACK control line to see if the DSP is busy

15 14 13 12 11 10

9

8

7

6

5

4

0

3

0

2

0

1

0

3. Host uses IS and IAL control lines to latch either the DMA

starting address (IDMAA) or the PM/DM OVLAY selection

into the DSP’s IDMA control registers. If Bit 15 = 1, the

value of bits 7:0 represent the IDMA overlay: bits 14:8 must

be set to 0. If Bit 15 = 0, the value of Bits 13:0 represent the

starting address of internal memory to be accessed and

Bit 14 reflects PM or DM for access. For ADSP-2185M,

IDDMOVLAY and IDPMOVLAY bits in IDMA overlay

register should be set to zero.

0

DM (0x3FE7)

RESERVED SET TO 0

IDDMOVLAY

IDPMOVLAY

SHORT READ ONLY

0 = ENABLE

1 = DISABLE

IDMA CONTROL (U = UNDEFINED AT RESET)

15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

U

DM (0x3FE0)

IDMAA ADDRESS

4. Host uses IS and IRD (or IWR) to read (or write) DSP inter-

IDMAD DESTINATION MEMORY TYPE

0 = PM

1 = DM

nal memory (PM or DM).

RESERVED SET TO 0

NOTES: RESERVED BITS ARE SHOWN ON A GRAY FIELD. THESE BITS

SHOULD ALWAYS BE WRITTEN WITH ZEROS.

5. Host checks IACK line to see if the DSP has completed the

previous IDMA operation.

6. Host ends IDMA transfer.

Figure 10. IDMA Control/OVLAY Registers

The IDMA port has a 16-bit multiplexed address and data bus

and supports 24-bit program memory. The IDMA port is com-

pletely asynchronous and can be written while the ADSP-2185M

is operating at full speed.

DMA

PROGRAM MEMORY

OVLAY

DMA

DATA MEMORY

OVLAY

ALWAYS

The DSP memory address is latched and then automatically incre-

mented after each IDMA transaction. An external device can

therefore access a block of sequentially addressed memory by

specifying only the starting address of the block. This increases

throughput as the address does not have to be sent for each

memory access.

ACCESSIBLE

AT ADDRESS

ACCESSIBLE

AT ADDRESS

0x

0000 – 0

x

1FFF

0x2000 – 0x3FFF

0

x2000 –

x3FFF

0

x0000 –

x1FFF

0

ACCESSIBLE WHEN

PMOVLAY = 0

ACCESSIBLE WHEN

DMOVLAY = 0

IDMA Port access occurs in two phases. The first is the IDMA

Address Latch cycle. When the acknowledge is asserted, a 14-bit

address and 1-bit destination type can be driven onto the bus by

an external device. The address specifies an on-chip memory

location, the destination type specifies whether it is a DM or

PM access. The falling edge of the IDMA address latch signal

(IAL) or the missing edge of the IDMA select signal (IS) latches

this value into the IDMAA register.

NOTE: IDMA AND BDMA HAVE SEPARATE DMA CONTROL REGISTERS.

Figure 11. Direct Memory Access—PM and DM

Memory Maps

Bootstrap Loading (Booting)

The ADSP-2185M has two mechanisms to allow automatic load-

ing of the internal program memory after reset. The method for

booting is controlled by the Mode A, B, and C configuration bits.

Once the address is stored, data can be read from, or written to,

the ADSP-2185M’s on-chip memory. Asserting the select line

(IS) and the appropriate read or write line (IRD and IWR

respectively) signals the ADSP-2185M that a particular transac-

tion is required. In either case, there is a one-processor-cycle

delay for synchronization. The memory access consumes one

additional processor cycle.

When the MODE pins specify BDMA booting, the ADSP-2185M

initiates a BDMA boot sequence when reset is released.

The BDMA interface is set up during reset to the following

defaults when BDMA booting is specified: the BDIR, BMPAGE,

BIAD, and BEAD registers are set to 0, the BTYPE register is

set to 0 to specify program memory 24-bit words, and the

BWCOUNT register is set to 32. This causes 32 words of

on-chip program memory to be loaded from byte memory.

Once an access has occurred, the latched address is automati-

cally incremented, and another access can occur.

REV. 0

–15–

ADSP-2185M

These 32 words are used to set up the BDMA to load in the

remaining program code. The BCR bit is also set to 1, which

causes program execution to be held off until all 32 words are

loaded into on-chip program memory. Execution then begins at

address 0.

read and write the values on the pins. Data being read from a

pin configured as an input is synchronized to the ADSP-2185M’s

clock. Bits that are programmed as outputs will read the value

being output. The PF pins default to input during reset.

In addition to the programmable flags, the ADSP-2185M has five

fixed-mode flags, FI, FO, FL0, FL1, and FL2. FL0–FL2 are

dedicated output flags. FI and FO are available as an alternate

configuration of SPORT1.

The ADSP-2100 Family development software (Revision 5.02

and later) fully supports the BDMA booting feature and can

generate byte memory space compatible boot code.

The IDLE instruction can also be used to allow the processor

to hold off execution while booting continues through the

BDMA interface. For BDMA accesses while in Host Mode, the

addresses to boot memory must be constructed externally to the

ADSP-2185M. The only memory address bit provided by the

processor is A0.

Note: Pins PF0, PF1, PF2, and PF3 are also used for device

configuration during reset.

Instruction Set Description

The ADSP-2185M assembly language instruction set has an

algebraic syntax that was designed for ease of coding and read-

ability. The assembly language, which takes full advantage of the

processor’s unique architecture, offers the following benefits:

IDMA Port Booting

The ADSP-2185M can also boot programs through its Internal

DMA port. If Mode C = 1, Mode B = 0, and Mode A = 1, the

ADSP-2185M boots from the IDMA port. IDMA feature can

load as much on-chip memory as desired. Program execution is

held off until on-chip program memory location 0 is written to.

• The algebraic syntax eliminates the need to remember cryptic

assembler mnemonics. For example, a typical arithmetic add

instruction, such as AR = AX0 + AY0, resembles a simple

equation.

• Every instruction assembles into a single, 24-bit word that

can execute in a single instruction cycle.

Bus Request and Bus Grant

The ADSP-2185M can relinquish control of the data and address

buses to an external device. When the external device requires

access to memory, it asserts the bus request (BR) signal. If the

ADSP-2185M is not performing an external memory access, it

responds to the active BR input in the following processor cycle by:

• The syntax is a superset ADSP-2100 Family assembly lan-

guage and is completely source and object code compatible

with other family members. Programs may need to be relocated

to utilize on-chip memory and conform to the ADSP-2185M’s

interrupt vector and reset vector map.

• Three-stating the data and address buses and the PMS, DMS,

BMS, CMS, IOMS, RD, WR output drivers,

• Sixteen condition codes are available. For conditional jump,

call, return, or arithmetic instructions, the condition can

be checked and the operation executed in the same instruc-

tion cycle.

• Asserting the bus grant (BG) signal, and

• Halting program execution.

If Go Mode is enabled, the ADSP-2185M will not halt program

execution until it encounters an instruction that requires an

external memory access.

• Multifunction instructions allow parallel execution of an

arithmetic instruction with up to two fetches or one write to

processor memory space during a single instruction cycle.

If the ADSP-2185M is performing an external memory access

when the external device asserts the BR signal, it will not three-

state the memory interfaces nor assert the BG signal until the

processor cycle after the access completes. The instruction does

not need to be completed when the bus is granted. If a single

instruction requires two external memory accesses, the bus will

be granted between the two accesses.

DESIGNING AN EZ-ICE-COMPATIBLE SYSTEM

The ADSP-2185M has on-chip emulation support and an

ICE-Port, a special set of pins that interface to the EZ-ICE.

These features allow in-circuit emulation without replacing the

target system processor by using only a 14-pin connection from

the target system to the EZ-ICE. Target systems must have a

14-pin connector to accept the EZ-ICE’s in-circuit probe, a

14-pin plug.

When the BR signal is released, the processor releases the BG

signal, re-enables the output drivers, and continues program

execution from the point at which it stopped.

Issuing the chip reset command during emulation causes the

DSP to perform a full chip reset, including a reset of its memory

mode. Therefore, it is vital that the mode pins are set correctly

PRIOR to issuing a chip reset command from the emulator user

interface. If a passive method of maintaining mode information is

being used (as discussed in Setting Memory Modes), it does not

matter that the mode information is latched by an emulator

reset. However, if the RESET pin is being used as a method of

setting the value of the mode pins, the effects of an emulator

reset must be taken into consideration.

The bus request feature operates at all times, including when

the processor is booting and when RESET is active.

The BGH pin is asserted when the ADSP-2185M requires the

external bus for a memory or BDMA access, but is stopped.

The other device can release the bus by deasserting bus request.

Once the bus is released, the ADSP-2185M deasserts BG and

BGH and executes the external memory access.

Flag I/O Pins

One method of ensuring that the values located on the mode

pins are those desired is to construct a circuit like the one shown

in Figure 12. This circuit forces the value located on the Mode

A pin to logic high; regardless of whether it is latched via the

RESET or ERESET pin.

The ADSP-2185M has eight general purpose programmable

input/output flag pins. They are controlled by two memory

mapped registers. The PFTYPE register determines the direc-

tion, 1 = output and 0 = input. The PFDATA register is used to

–16–

REV. 0

ADSP-2185M

The 14-pin, 2-row pin strip header is keyed at the Pin 7 loca-

tion—Pin 7 must be removed from the header. The pins must

be 0.025 inch square and at least 0.20 inch in length. Pin spac-

ing should be 0.1 × 0.1 inches. The pin strip header must have

at least 0.15 inch clearance on all sides to accept the EZ-ICE

probe plug.

ERESET

RESET

ADSP-2185M

1k⍀

MODE A/PFO

Pin strip headers are available from vendors such as 3M,

McKenzie, and Samtec.

PROGRAMMABLE I/O

Target Memory Interface

Figure 12. Mode A Pin/EZ-ICE Circuit

For your target system to be compatible with the EZ-ICE

emulator, it must comply with the memory interface guidelines

listed below.

See the ADSP-2100 Family EZ-Tools data sheet for complete

information on ICE products.

The ICE-Port interface consists of the following ADSP-2185M

pins: EBR, EINT, EE, EBG, ECLK, ERESET, ELIN, EMS,

and ELOUT

PM, DM, BM, IOM, AND CM

Design your Program Memory (PM), Data Memory (DM), Byte

Memory (BM), I/O Memory (IOM), and Composite Memory

(CM) external interfaces to comply with worst case device tim-

ing requirements and switching characteristics as specified in

this data sheet. The performance of the EZ- ICE may approach

published worst-case specification for some memory access

timing requirements and switching characteristics.

These ADSP-2185M pins must be connected only to the EZ-ICE

connector in the target system. These pins have no function except

during emulation, and do not require pull-up or pull-down

resistors. The traces for these signals between the ADSP-2185M

and the connector must be kept as short as possible, no longer

than 3 inches.

Note: If your target does not meet the worst-case chip specifica-

tion for memory access parameters, you may not be able to

emulate your circuitry at the desired CLKIN frequency. Depend-

ing on the severity of the specification violation, you may have

trouble manufacturing your system as DSP components statisti-

cally vary in switching characteristic and timing requirements

within published limits.

The following pins are also used by the EZ-ICE: BR, BG,

RESET, and GND.

The EZ-ICE uses the EE (emulator enable) signal to take con-

trol of the ADSP-2185M in the target system. This causes the

processor to use its ERESET, EBR, and EBG pins instead of

the RESET, BR, and BG pins. The BG output is three-stated.

These signals do not need to be jumper-isolated in your system.

Restriction: All memory strobe signals on the ADSP-2185M

(RD, WR, PMS, DMS, BMS, CMS, and IOMS) used in your

target system must have 10 kΩ pull-up resistors connected when

the EZ-ICE is being used. The pull-up resistors are necessary

because there are no internal pull-ups to guarantee their state

during prolonged three-state conditions resulting from typical

EZ-ICE debugging sessions. These resistors may be removed at

your option when the EZ-ICE is not being used.

The EZ-ICE connects to your target system via a ribbon cable

and a 14-pin female plug. The female plug is plugged onto the

14-pin connector (a pin strip header) on the target board.

Target Board Connector for EZ-ICE Probe

The EZ-ICE connector (a standard pin strip header) is shown in

Figure 13. You must add this connector to your target board

design if you intend to use the EZ-ICE. Be sure to allow enough

room in your system to fit the EZ-ICE probe onto the 14-pin

connector.

Target System Interface Signals

When the EZ-ICE board is installed, the performance on some

system signals change. Design your system to be compatible

with the following system interface signal changes introduced by

the EZ-ICE board:

1

3

5

2

4

BG

GND

EBG

• EZ-ICE emulation introduces an 8 ns propagation delay

between your target circuitry and the DSP on the RESET

signal.

BR

6

EBR

EINT

ELIN

ECLK

EMS

7

8

؋

KEY (NO PIN)

ELOUT

EE

• EZ-ICE emulation introduces an 8 ns propagation delay

between your target circuitry and the DSP on the BR signal.

10

12

14

9

11

13

-

• EZ-ICE emulation ignores RESET and BR when single-

stepping.

RESET

ERESET

• EZ-ICE emulation ignores RESET and BR when in Emulator

Space (DSP halted).

TOP VIEW

• EZ-ICE emulation ignores the state of target BR in certain

modes. As a result, the target system may take control of the

DSP’s external memory bus only if bus grant (BG) is asserted

by the EZ- ICE board’s DSP.

Figure 13. Target Board Connector for EZ-ICE

REV. 0

–17–

ADSP-2185M–SPECIFICATIONS

RECOMMENDED OPERATING CONDITIONS

K Grade

B Grade

Parameter

Min

Max

Min

Max

Unit

V_DDINT

V_DDEXT

V_INPUT

2.37

V_IL= –0.3

0

2.63

3.6

V_IH= +3.6

+70

2.25

V_IL= –0.3

–40

2.75

3.6

V_IH= +3.6

+85

V

°C

1

T_AMB

NOTES

¹The ADSP-2185M is 3.3 V tolerant (always accepts up to 3.6 V max V_IH), but voltage compliance (on outputs, V_OH) depends on the input V_DDEXT; because V_OH(max)

≈ V_DDEXT(max). This applies to bidirectional pins (D0–D23, RFS0, RFS1, SCLK0, SCLK1, TFS0, TFS1, A1–A13, PF0–PF7) and input only pins (CLKIN, RESET,

BR, DR0, DR1, PWD).

Specifications subject to change without notice.

ELECTRICAL CHARACTERISTICS

K/B Grades

Parameter

Test Conditions

Min

Typ

Max

Unit

V_IH

V_IL

Hi-Level Input Voltage^{1, 2}

Hi-Level CLKIN Voltage

Lo-Level Input Voltage^{1, 3}

Hi-Level Output Voltage^{1, 4, 5}

@ V_DDINT= max

@ V_DDINT= min

1.5

2.0

V

µA

mA

µA

0.7

V_OH

@ V_DDEXT= min, I_OH= –0.5 mA

@ V_DDEXT= 3.0 V, I_OH= –0.5 mA

@ V_DDEXT= min, I_OH= –100 µA⁶

@ V_DDEXT= min, I_OL= 2 mA

@ V_DDINT= max, V_IN= 3.6 V

@ V_DDINT= max, V_IN= 0 V

@ V_DDEXT= max, V_IN= 3.6 V⁸

@ V_DDEXT= max, V_IN= 0 V⁸

@ V_DDINT= 2.5, t_CK= 15 ns

@ V_DDINT= 2.5, t_CK= 13.3 ns

@ V_DDINT= 2.5, t_CK= 15 ns¹¹, T_AMB= 25°C

@ V_DDINT= 2.5, t_CK= 13.3 ns¹¹, T_AMB= 25°C

2.0

2.4

V_DDEXT– 0.3

V_OL

I_IH

I_IL

Lo-Level Output Voltage^{1, 4, 5}

Hi-Level Input Current³

Lo-Level Input Current³

0.4

10

I_OZHThree-State Leakage Current⁷

I_OZL

I_DD

Three-State Leakage Current⁷

Supply Current (Idle)⁹

9

Supply Current (Idle)⁹

10

35

38

100

Supply Current (Dynamic)¹⁰

Supply Current (Power-Down)¹²@ V_DDINT= 2.5, T_AMB= 25°C in Lowest

Power Mode

@ V_IN= 2.5 V, f_IN= 1.0 MHz, T_AMB= 25°C

C_I

C_O

Input Pin Capacitance^{3, 6}

8

pF

Output Pin Capacitance^{6, 7, 12, 13}

NOTES

¹Bidirectional pins: D0–D23, RFS0, RFS1, SCLK0, SCLK1, TFS0, TFS1, A1–A13, PF0–PF7.

²Input only pins: RESET, BR, DR0, DR1, PWD.

³Input only pins: CLKIN, RESET, BR, DR0, DR1, PWD.

⁴Output pins: BG, PMS, DMS, BMS, IOMS, CMS, RD, WR, PWDACK, A0, DT0, DT1, CLKOUT, FL2–0, BGH.

⁵Although specified for TTL outputs, all ADSP-2185M outputs are CMOS-compatible and will drive to V_DDEXTand GND, assuming no dc loads.

⁶Guaranteed but not tested.

⁷Three-statable pins: A0–A13, D0–D23, PMS, DMS, BMS, IOMS, CMS, RD, WR, DT0, DT1, SCLK0, SCLK1, TFS0, TFS1, RFS0, RFS1, PF0–PF7.

⁸0 V on BR.

⁹Idle refers to ADSP-2185M state of operation during execution of IDLE instruction. Deasserted pins are driven to either V_DDor GND.

10

I

measurement taken with all instructions executing from internal memory. 50% of the instructions are multifunction (Types 1, 4, 5, 12, 13, 14), 30% are Type 2

DD

and Type 6, and 20% are idle instructions.

11

V

= 0 V and 3 V. For typical figures for supply currents, refer to Power Dissipation section.

IN

¹²See Chapter 9 of the ADSP-2100 Family User’s Manual for details.

¹³Output pin capacitance is the capacitive load for any three-stated output pin.

Specifications subject to change without notice.

–18–

REV. 0

ADSP-2185M

ABSOLUTE MAXIMUM RATINGS¹

Parameter

NOTES

¹Stresses greater than those listed may cause permanent damage to the device.

These are stress ratings only; functional operation of the device at these or any other

conditions greater than those indicated in the operational sections of this specifi-

cation is not implied. Exposure to absolute maximum rating conditions for

extended periods may affect device reliability.

Value

Min

Max

Internal Supply Voltage (V_DDINT

)

–0.3 V

–0.5 V

–40°C

–65°C

+3.0 V

+4.0 V

V_DDEXT+ 0.5 V

+85°C

+150°C

280°C

External Supply Voltage (V_DDEXT

)

²Applies to Bidirectional pins (D0–D23, RFS0, RFS1, SCLK0, SCLK1, TFS0,

TFS1, A1–A13, PF0–PF7) and Input only pins (CLKIN, RESET, BR, DR0,

DR1, PWD).

Input Voltage²

Output Voltage Swing³

³AppliestoOutputpins(BG,PMS, DMS,BMS,IOMS, CMS, RD, WR,PWDACK,

A0, DT0, DT1, CLKOUT, FL2–0, BGH).

Operating Temperature Range

Storage Temperature Range

Lead Temperature (5 sec) LQFP

ESD SENSITIVITY

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection. Although

the ADSP-2185M features proprietary ESD protection circuitry, permanent damage may occur on

devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are

recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

Timing requirements apply to signals that are controlled by

circuitry external to the processor, such as the data input for a

read operation. Timing requirements guarantee that the proces-

sor operates correctly with other devices.

TIMING SPECIFICATIONS

GENERAL NOTES

Use the exact timing information given. Do not attempt to

derive parameters from the addition or subtraction of others.

While addition or subtraction would yield meaningful results for

an individual device, the values given in this data sheet reflect

statistical variations and worst cases. Consequently, you cannot

meaningfully add up parameters to derive longer times.

MEMORY TIMING SPECIFICATIONS

The table below shows common memory device specifications

and the corresponding ADSP-2185M timing parameters, for

your convenience.

TIMING NOTES

Memory

Device

Specification

Timing

Parameter

Switching characteristics specify how the processor changes its

signals. You have no control over this timing—circuitry external

to the processor must be designed for compatibility with these

signal characteristics. Switching characteristics tell you what the

processor will do in a given circumstance. You can also use

switching characteristics to ensure that any timing require-

ment of a device connected to the processor (such as memory)

is satisfied.

Parameter Definition¹

Address Setup to

Write Start

Address Setup to

Write End

t_ASW

A0–A13, xMS Setup before

WR Low

A0–A13, xMS Setup before

WR Deasserted

A0–A13, xMS Hold before

WR Low

t_AW

Address Hold Time t_WRA

Data Setup Time

t_DW

Data Setup before WR

High

Data Hold Time

OE to Data Valid

t_DH

t_RDD

Data Hold after WR High

RD Low to Data Valid

Address Access Time t_AA

A0–A13, xMS to Data Valid

NOTE

¹xMS = PMS, DMS, BMS, CMS or IOMS.

REV. 0

–19–

ADSP-2185M

FREQUENCY DEPENDENCY FOR TIMING

• Each address and data pin has a 10 pF total load at the pin.

• The application operates at V_DDEXT= 3.3 V and t_CK= 30 ns.

Total Power Dissipation = P_INT+ (C × V_DDEXT²× f)

SPECIFICATIONS

t_CKis defined as 0.5 t_CKI. The ADSP-2185M uses an input clock

with a frequency equal to half the instruction rate. For example,

a 37.50 MHz input clock (which is equivalent to 26.6 ns) yields

a 13.3 ns processor cycle (equivalent to 75 MHz). t_CKvalues

within the range of 0.5 t_CKIperiod should be substituted for all

relevant timing parameters to obtain the specification value.

P

_INT= internal power dissipation from Power vs. Frequency

graph (Figure 15).

(C × V_DDEXT²× f ) is calculated for each output:

Example: t_CKH= 0.5 t_CK– 2 ns = 0.5 (15 ns) – 2 ns = 5.5 ns

2

# of

؋

C

؋

V_DDEXT

؋

f

PD

Parameters

Pins

pF

V

MHz mW

ENVIRONMENTAL CONDITIONS¹

Address

Data Output, WR

RD

7

9

1

2

10

3.3²

16.67 12.7

16.67 16.3

Rating

Description

Symbol

LQFP

Mini-BGA

16.67

33.3

1.8

7.2

CLKOUT, DMS

Thermal Resistance

(Case-to-Ambient)

Thermal Resistance

(Junction-to-Ambient)

Thermal Resistance

(Junction-to-Case)

θ_CA

48°C/W

63.3°C/W

38.0

θ_JA

θ_JC

50°C/W

2°C/W

70.7°C/W

7.4°C/W

Total power dissipation for this example is P_INT+ 38.0 mW.

Output Drive Currents

Figure 14 shows typical I-V characteristics for the output drivers

on the ADSP-2185M. The curves represent the current drive

capability of the output drivers as a function of output voltage.

NOTE

¹Where the Ambient Temperature Rating (T_AMB) is:

T_AMB= T_CASE– (PD × θ_CA

)

T_CASE= Case Temperature in °C

80

PD = Power Dissipation in W

V

60

40

OH

V

= 3.6V @ –40؇C

= 3.3V @ +25؇C

DDEXT

POWER DISSIPATION

To determine total power dissipation in a specific application,

the following equation should be applied for each output:

V

DDEXT

20

V

= 2.5V @ +85؇C

DDEXT

C × V_DD2 × f

C = load capacitance, f = output switching frequency.

Example:

0

–20

–40

V

= 3.6V @ –40؇C

DDEXT

V

= 2.5V @ +85؇C

DDEXT

V

OL

In an application where external data memory is used and no other

outputs are active, power dissipation is calculated as follows:

V

= 3.3V @ +25؇C

DDEXT

–60

–80

Assumptions:

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

• External data memory is accessed every cycle with 50% of the

address pins switching.

SOURCE VOLTAGE – V

Figure 14. Typical Output Driver Characteristics

• External data memory writes occur every other cycle with

50% of the data pins switching.

–20–

REV. 0

ADSP-2185M

1, 2, 3

Capacitive Loading

POWER, INTERNAL

115

110

Figure 16 and Figure 17 show the capacitive loading character-

istics of the ADSP-2185M.

110mW

105

100

95

V

= 2.65V

DD

30

95mW

82mW

T = 85؇C

V

= 0V TO 2.0V

DD

90

85

V

= 2.5V

25

DD

82mW

80

75

70

V

= 2.35V

20

15

10

5

DD

70mW

61mW

65

60

55

50

55

60

65

70

75

80

1/t – MHz

CK

1, 2, 4

POWER, IDLE

30

28

26

24

22

20

28mW

24mW

20mW

0

V

= 2.65V

50

0

100

150

– pF

200

250

300

DD

C

L

24mW

20mW

Figure 16. Typical Output Rise Time vs. Load Capacitance

(at Maximum Ambient Operating Temperature)

V

= 2.5V

DD

18

V

= 2.35V

DD

16

14

18

16.5mW

16

14

12

10

50

55

60

65

70

75

1/t – MHz

CK

8

2

6

4

POWER, IDLE n MODES

26

24

24mW

2

IDLE

NOMINAL

22

20

18

16

–2

–4

–6

20mW

15mW

0

50

100

150

200

250

C

– pF

L

16.4mW

15.7mW

IDLE (16)

IDLE (128)

Figure 17. Typical Output Valid Delay or Hold vs. Load

Capacitance, C_L(at Maximum Ambient Operating

Temperature)

14

12

14.25mW

55

50

60

65

1/t – MHz

70

75

CK

NOTES:

VALID FOR ALL TEMPERATURE GRADES.

1

POWER REFLECTS DEVICE OPERATING WITH NO OUTPUT LOADS.

2

TYPICAL POWER DISSIPATION AT 2.5V V

WHERE SPECIFIED.

AND 25؇C, EXCEPT

DDINT

3

I

MEASUREMENT TAKEN WITH ALL INSTRUCTIONS EXECUTING FROM

DD

INTERNAL MEMORY. 50% OF THE INSTRUCTIONS ARE MULTIFUNCTION

(TYPES 1, 4, 5, 12, 13, 14), 30% ARE TYPE 2 AND TYPE 6, AND 20% ARE

IDLE INSTRUCTIONS.

4

IDLE REFERS TO STATE OF OPERATION DURING EXECUTION

OF IDLE INSTRUCTION. DEASSERTED PINS ARE DRIVEN TO EITHER V

OR GND.

DD

Figure 15. Power vs. Frequency

REV. 0

–21–

ADSP-2185M

TEST CONDITIONS

Output Enable Time

Output Disable Time

Output pins are considered to be enabled when they have made

a transition from a high-impedance state to when they start driving.

The output enable time (t_ENA) is the interval from when a refer-

ence signal reaches a high or low voltage level to when the output

has reached a specified high or low trip point, as shown Figure

19. If multiple pins (such as the data bus) are enabled, the mea-

surement value is that of the first pin to start driving.

Output pins are considered to be disabled when they have stopped

driving and started a transition from the measured output high

or low voltage to a high impedance state. The output disable

time (t_DIS) is the difference of t_MEASUREDand t_DECAY, as shown

in the Output Enable/Disable diagram. The time is the interval

from when a reference signal reaches a high or low voltage level

to when the output voltages have changed by 0.5 V from the

measured output high or low voltage.

REFERENCE

SIGNAL

The decay time, t_DECAY, is dependent on the capacitive load,

C_L, and the current load, i_L, on the output pin. It can be

approximated by the following equation:

t_MEASURED

t_DIS

t_ENA

V

OH

(MEASURED)

C_L× 0.5V

V

(MEASURED) – 0.5V

2.0V

1.0V

OH

t_DECAY

=

OUTPUT

i_L

(MEASURED) +0.5V

OL

V

from which

OL

t_DECAY

(MEASURED)

t

_DIS= t_MEASURED– t_DECAY

OUTPUT

STARTS

DRIVING

OUTPUT STOPS

DRIVING

is calculated. If multiple pins (such as the data bus) are disabled,

the measurement value is that of the last pin to stop driving.

HIGH-IMPEDANCE STATE. TEST CONDITIONS CAUSE

THIS VOLTAGE LEVEL TO BE APPROXIMATELY 1.5V.

Figure 19. Output Enable/Disable

INPUT

1.5V

I

OL

2.0V

OUTPUT

1.5V

0.8V

TO

OUTPUT

Figure 18. Voltage Reference Levels for AC Measure-

ments (Except Output Enable/Disable)

1.5V

50pF

I

OH

Figure 20. Equivalent Loading for AC Measurements

(Including All Fixtures)

–22–

REV. 0

ADSP-2185M

Parameter

Min

Max

Unit

Clock Signals and Reset

Timing Requirements:

t_CKI

CLKIN Period

26.6

8

80

ns

t_CKIL

t_CKIH

CLKIN Width Low

CLKIN Width High

Switching Characteristics:

t_CKL

CLKOUT Width Low

0.5t_CK– 2

0

ns

t_CKH

t_CKOH

CLKOUT Width High

CLKIN High to CLKOUT High

13

Control Signals Timing Requirements:

1

t_RSP

t_MS

t_MH

RESET Width Low

Mode Setup before RESET High

Mode Hold after RESET High

5t_CK

2

5

ns

NOTE

¹Applies after power-up sequence is complete. Internal phase lock loop requires no more than 2000 CLKIN cycles assuming stable CLKIN (not including crystal

oscillator start-up time).

t_CKI

t_CKIH

CLKIN

t_CKIL

t_CKOH

t_CKH

CLKOUT

t_CKL

PF(3:0)*

t_MH

t_MS

RESET

t_RSP

*PF3 IS MODE D, PF2 IS MODE C, PF1 IS MODE B, PF0 IS MODE A

Figure 21. Clock Signals

REV. 0

–23–

ADSP-2185M

Parameter

Min

Max

Unit

Interrupts and Flags

Timing Requirements:

t_IFS

t_IFH

IRQx, FI, or PFx Setup before CLKOUT Low^{1, 2, 3, 4}

IRQx, FI, or PFx Hold after CLKOUT High^{1, 2, 3, 4}

0.25t_CK+ 10

0.25t_CK

ns

Switching Characteristics:

t_FOH

Flag Output Hold after CLKOUT Low⁵

t_FOD

Flag Output Delay from CLKOUT Low⁵

0.5t_CK– 5

ns

0.5t_CK+ 4

NOTES

¹If IRQx and FI inputs meet t_IFSand t_IFHsetup/hold requirements, they will be recognized during the current clock cycle; otherwise the signals will be recognized on

the following cycle. (Refer to “Interrupt Controller Operation” in the Program Control chapter of the ADSP-2100 Family User’s Manual for further information on

interrupt servicing.)

²Edge-sensitive interrupts require pulsewidths greater than 10 ns; level-sensitive interrupts must be held low until serviced.

³IRQx = IRQ0, IRQ1, IRQ2, IRQL0, IRQL1, IRQLE.

⁴PFx = PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7.

⁵Flag Outputs = PFx, FL0, FL1, FL2, FO.

t_FOD

CLKOUT

t_FOH

FLAG

OUTPUTS

t_IFH

IRQx

FI

PFx

t_IFS

Figure 22. Interrupts and Flags

–24–

REV. 0

ADSP-2185M

Parameter

Min

Max

Unit

Bus Request–Bus Grant

Timing Requirements:

t_BH

t_BS

BR Hold after CLKOUT High¹

BR Setup before CLKOUT Low¹

0.25t_CK+ 2

0.25t_CK+ 10

ns

Switching Characteristics:

t_SD

CLKOUT High to xMS, RD, WR Disable

0.25t_CK+ 8

ns

t_SDB

t_SE

xMS, RD, WR Disable to BG Low

BG High to xMS, RD, WR Enable

xMS, RD, WR Enable to CLKOUT High

xMS, RD, WR Disable to BGH Low²

BGH High to xMS, RD, WR Enable²

0

t_SEC

t_SDBH

t_SEH

0.25t_CK– 3

0

NOTES

xMS = PMS, DMS, CMS, IOMS, BMS.

¹BR is an asynchronous signal. If BR meets the setup/hold requirements, it will be recognized during the current clock cycle; otherwise the signal will be recognized on

the following cycle. Refer to the ADSP-2100 Family User’s Manual for BR/BG cycle relationships.

²BGH is asserted when the bus is granted and the processor or BDMA requires control of the bus to continue.

t_BH

CLKOUT

BR

t_BS

CLKOUT

PMS, DMS

BMS, RD

WR

t_SD

t_SEC

BG

t_SDB

t_SE

BGH

t_SDBH

t_SEH

Figure 23. Bus Request–Bus Grant

REV. 0

–25–

ADSP-2185M

Parameter

Min

Max

Unit

Memory Read

Timing Requirements:

t_RDD

t_AA

RD Low to Data Valid

A0–A13, xMS to Data Valid

Data Hold from RD High

0.5t_CK– 5 + w

0.75t_CK– 6 + w

ns

t_RDH

0

Switching Characteristics:

t_RP

RD Pulsewidth

0.5t_CK– 3 + w

0.25t_CK– 2

0.25t_CK– 3

0.5t_CK– 3

ns

t_CRD

t_ASR

t_RDA

t_RWR

CLKOUT High to RD Low

0.25t_CK+ 4

A0–A13, xMS Setup before RD Low

A0–A13, xMS Hold after RD Deasserted

RD High to RD or WR Low

NOTES

w = wait states x t_CK

.

xMS = PMS, DMS, CMS, IOMS, BMS.

CLKOUT

A0–A13

DMS, PMS,

BMS, IOMS,

CMS

t_RDA

t_RWR

t_RDH

RD

D0–D23

WR

t_ASR

t_CRD

t_RP

t_RDD

t_AA

Figure 24. Memory Read

–26–

REV. 0

ADSP-2185M

Parameter

Min

Max

Unit

Memory Write

Switching Characteristics:

t_DW

t_DH

t_WP

t_WDE

t_ASW

t_DDR

t_CWR

t_AW

Data Setup before WR High

Data Hold after WR High

WR Pulsewidth

WR Low to Data Enabled

A0–A13, xMS Setup before WR Low

Data Disable before WR or RD Low

CLKOUT High to WR Low

A0–A13, xMS, Setup before WR Deasserted

A0–A13, xMS Hold after WR Deasserted

WR High to RD or WR Low

0.5t_CK– 4 + w

0.25t_CK– 1

0.5t_CK– 3 + w

0

0.25t_CK– 3

0.25t_CK– 2

0.75t_CK– 5 + w

0.25t_CK– 1

0.5t_CK– 3

ns

0.25 t_CK+ 4

t_WRA

t_WWR

NOTES

w = wait states x t_CK.

xMS = PMS, DMS, CMS, IOMS, BMS.

CLKOUT

A0–A13

DMS, PMS,

BMS, CMS,

IOMS

t_WRA

WR

t_WWR

t_ASW

t_WP

t_AW

t_DH

t_DDR

t_CWR

D0–D23

t_DW

t_WDE

RD

Figure 25. Memory Write

REV. 0

–27–

ADSP-2185M

Serial Ports

Parameter

Min

Max

Unit

Serial Ports

Timing Requirements:

t_SCK

t_SCS

t_SCH

t_SCP

SCLK Period

26.6

4

7

ns

DR/TFS/RFS Setup before SCLK Low

DR/TFS/RFS Hold after SCLK Low

SCLKIN Width

12

Switching Characteristics:

t_CC

CLKOUT High to SCLKOUT

SCLK High to DT Enable

SCLK High to DT Valid

TFS/RFS_OUTHold after SCLK High

TFS/RFS_OUTDelay from SCLK High

DT Hold after SCLK High

0.25t_CK

0

0.25t_CK+ 6

ns

t_SCDE

t_SCDV

t_RH

12

0

t_RD

t_SCDH

t_TDE

t_TDV

t_SCDD

t_RDV

0

TFS (Alt) to DT Enable

TFS (Alt) to DT Valid

12

SCLK High to DT Disable

RFS (Multichannel, Frame Delay Zero) to DT Valid

CLKOUT

t_CC

t_SCK

SCLK

t_SCP

t_SCS

t_SCH

DR

TFS

RFS

IN

t_RD

t_RH

RFS

TFS

OUT

t_SCDD

t_SCDV

t_SCDH

t_SCDE

DT

t_TDE

t_TDV

TFS

OUT

ALTERNATE

FRAME MODE

t_RDV

RFS

OUT

MULTICHANNEL

MODE,

FRAME DELAY 0

(MFD = 0)

t_TDE

t_TDV

TFS

IN

ALTERNATE

FRAME MODE

t_RDV

RFS

IN

MULTICHANNEL

MODE,

FRAME DELAY 0

(MFD = 0)

Figure 26. Serial Ports

–28–

REV. 0

ADSP-2185M

Parameter

Min

Max

Unit

IDMA Address Latch

Timing Requirements:

t_IALP

t_IASU

t_IAH

Duration of Address Latch^{1, 2}

10

5

3

0

3

ns

IAD15–0 Address Setup before Address Latch End²

IAD15–0 Address Hold after Address Latch End²

IACK Low before Start of Address Latch^{2, 3}

t_IKA

t_IALS

t_IALD

Start of Write or Read after Address Latch End^{2, 3}

Address Latch Start after Address Latch End^{1, 2}

2

NOTES

¹Start of Address Latch = IS Low and IAL High.

²End of Address Latch = IS High or IAL Low.

³Start of Write or Read = IS Low and IWR Low or IRD Low.

IACK

t_IKA

t_IALD

IAL

t_IALP

IS

IAD15–0

t_IASU

t_IAH

t_IALS

IRD OR IWR

Figure 27. IDMA Address Latch

REV. 0

–29–

ADSP-2185M

Parameter

Min

Max

Unit

IDMA Write, Short Write Cycle

Timing Requirements:

t_IKW

t_IWP

t_IDSU

t_IDH

IACK Low before Start of Write¹

0

10

3

ns

Duration of Write^{1, 2}

IAD15–0 Data Setup before End of Write^{2, 3, 4}

IAD15–0 Data Hold after End of Write^{2, 3, 4}

2

Switching Characteristic:

t_IKHW

Start of Write to IACK High

10

ns

NOTES

¹Start of Write = IS Low and IWR Low.

²End of Write = IS High or IWR High.

³If Write Pulse ends before IACK Low, use specifications t_IDSU, t_IDH

.

⁴If Write Pulse ends after IACK Low, use specifications t_IKSU, t_IKH

.

t_IKW

IACK

IS

t_IKHW

t_IWP

IWR

t_IDH

t_IDSU

DATA

IAD15–0

Figure 28. IDMA Write, Short Write Cycle

–30–

REV. 0

ADSP-2185M

Parameter

Min

Max

Unit

IDMA Write, Long Write Cycle

Timing Requirements:

t_IKW

t_IKSU

t_IKH

IACK Low before Start of Write¹

0

ns

IAD15–0 Data Setup before End of Write^{2, 3, 4}

IAD15–0 Data Hold after End of Write^{2, 3, 4}

0.5t_CK+ 5

0

Switching Characteristics:

t_IKLW

Start of Write to IACK Low⁴

t_IKHWStart of Write to IACK High

1.5t_CK

ns

10

NOTES

¹Start of Write = IS Low and IWR Low.

²If Write Pulse ends before IACK Low, use specifications t_IDSU, t_IDH

.

³If Write Pulse ends after IACK Low, use specifications t_IKSU, t_IKH

.

⁴This is the earliest time for IACK Low from Start of Write. For IDMA Write cycle relationships, please refer to the ADSP-2100 Family User’s Manual.

t_IKW

IACK

t_IKHW

t_IKLW

IS

IWR

t_IKSU

t_IKH

DATA

IAD15–0

Figure 29. IDMA Write, Long Write Cycle

REV. 0

–31–

ADSP-2185M

Parameter

Min

Max

Unit

IDMA Read, Long Read Cycle

Timing Requirements:

t_IKR

t_IRK

IACK Low before Start of Read¹

End of read after IACK Low²

0

2

ns

Switching Characteristics:

t_IKHR

t_IKDS

t_IKDH

t_IKDD

t_IRDE

t_IRDV

t_IRDH1

t_IRDH2

IACK High after Start of Read¹

10

ns

IAD15–0 Data Setup before IACK Low

0.5t_CK– 2

0

IAD15–0 Data Hold after End of Read²

IAD15–0 Data Disabled after End of Read²

10

11

IAD15–0 Previous Data Enabled after Start of Read

IAD15–0 Previous Data Valid after Start of Read

IAD15–0 Previous Data Hold after Start of Read (DM/PM1)³

IAD15–0 Previous Data Hold after Start of Read (PM2)⁴

0

2t_CK– 5

t_CK– 5

NOTES

¹Start of Read = IS Low and IRD Low.

²End of Read = IS High or IRD High.

³DM read or first half of PM read.

⁴Second half of PM read.

IACK

IS

t_IKHR

t_IKR

t_IRK

IRD

t_IKDH

t_IKDS

t_IRDE

READ

DATA

IAD15–0

t_IRDV

t_{IRDH1 or}t_IRDH2

t_IKDD

Figure 30. IDMA Read, Long Read Cycle

–32–

REV. 0

ADSP-2185M

Parameter

Min

Max

Unit

IDMA Read, Short Read Cycle^{1, 2}

Timing Requirements:

t_IKR

IACK Low before Start of Read³

0

10

ns

t_IRP1

t_IRP2

Duration of Read (DM/PM1)⁴

Duration of Read (PM2)⁵

2t_CK– 5

t_CK– 5

Switching Characteristics:

t_IKHR

t_IKDH

t_IKDD

t_IRDE

t_IRDV

IACK High after Start of Read³

10

ns

IAD15–0 Data Hold after End of Read⁶

0

IAD15–0 Data Disabled after End of Read⁶

IAD15–0 Previous Data Enabled after Start of Read

IAD15–0 Previous Data Valid after Start of Read

NOTES

¹Short Read Only must be disabled in the IDMA Overlay memory mapped register.

²Consider using the Short Read Only mode, instead, because Short Read mode is not applicable at high clock frequencies.

³Start of Read = IS Low and IRD Low.

⁴DM Read or first half of PM Read.

⁵Second half of PM Read.

⁶End of Read = IS High or IRD High.

IACK

t_IKR

t_IKHR

IS

t_IRP

IRD

t_IKDH

t_IRDE

IAD15–0

t_IKDD

t_IRDV

Figure 31. IDMA Read, Short Read Cycle

REV. 0

–33–

ADSP-2185M

Parameter

Min

Max

Unit

IDMA Read, Short Read Cycle in Short Read Only Mode¹

Timing Requirements:

t_IKR

t_IRP

IACK Low before Start of Read²

0

10

ns

Duration of Read³

Switching Characteristics:

t_IKHR

t_IKDH

t_IKDD

t_IRDE

t_IRDV

IACK High after Start of Read²

10

ns

IAD15–0 Previous Data Hold after End of Read³

IAD15–0 Previous Data Disabled after End of Read³

IAD15–0 Previous Data Enabled after Start of Read

IAD15–0 Previous Data Valid after Start of Read

0

NOTES

¹Short Read Only is enabled by setting Bit 14 of the IDMA Overlay Register to 1 (0x3FE7). Short Read Only can be enabled by the processor core writing to the

register or by an external host writing to the register. Disabled by default.

²Start of Read = IS Low and IRD Low. Previous data remains until end of read.

³End of Read = IS High or IRD High.

IACK

t_IKR

t_IKHR

IS

t_IRP

IRD

t_IKDH

t_IRDE

IAD15–0

t_IKDD

t_IRDV

Figure 32. IDMA Read, Short Read Only Cycle

–34–

REV. 0

ADSP-2185M

100-LEAD LQFP PIN CONFIGURATION

75

74

73

72

71

70

69

68

67

66

65

64

A4/IAD3

A5/IAD4

1

2

D15

D14

PIN 1

IDENTIFIER

3

GND

D13

4

A6/IAD5

A7/IAD6

D12

5

GND

6

A8/IAD7

A9/IAD8

D11

D10

7

8

A10/IAD9

D9

V

9

A11/IAD10

A12/IAD11

DDEXT

10

GND

11

12

A13/IAD12

GND

D8

D7/IWR

ADSP-2185M

TOP VIEW

(Not to Scale)

63 D6/IRD

13

14

15

16

17

18

19

CLKIN

XTAL

62

61

60

59

58

D5/IAL

D4/IS

GND

V

DDEXT

CLKOUT

GND

V

DDINT

D3/IACK

V

DDINT

57 D2/IAD15

WR

D1/IAD14

D0/IAD13

BG

RD 20

56

55

54

53

52

51

21

22

BMS

DMS

PMS 23

EBG

24

25

IOMS

CMS

BR

EBR

REV. 0

–35–

ADSP-2185M

The LQFP package pinout is shown in the table below. Pin names in bold text replace the plain text named functions when

Mode C = 1. A + sign separates two functions when either function can be active for either major I/O mode. Signals enclosed in

brackets [ ] are state bits latched from the value of the pin at the deassertion of RESET.

The multiplexed pins DT1/FO, TFS1/IRQ1, RFS1/IRQ0, and DR1/FI, are mode selectable by setting Bit 10 (SPORT1 configure)

of the System Control Register. If Bit 10 = 1, these pins have serial port functionality. If Bit 10 = 0, these pins are the external inter-

rupt and flag pins. This bit is set to 1 by default upon reset.

LQFP Package Pinout

No.

Pin Name

1

2

3

4

5

6

7

8

A4/IAD3

A5/IAD4

GND

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

IRQE + PF4

IRQL0 + PF5

GND

IRQL1 + PF6

IRQ2 + PF7

DT0

TFS0

RFS0

DR0

SCLK0

V_DDEXT

DT1/FO

TFS1/IRQ1

RFS1/IRQ0

DR1/FI

GND

SCLK1

ERESET

RESET

EMS

EE

ECLK

ELOUT

ELIN

EINT

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

EBR

BR

EBG

BG

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

D16

D17

D18

D19

GND

D20

D21

D22

D23

FL2

FL1

FL0

PF3 [MODE D]

PF2 [MODE C]

V_DDEXT

PWD

A6/IAD5

A7/IAD6

A8/IAD7

A9/IAD8

A10/IAD9

A11/IAD10

A12/IAD11

A13/IAD12

GND

CLKIN

XTAL

V_DDEXT

CLKOUT

GND

V_DDINT

WR

D0/IAD13

D1/IAD14

D2/IAD15

D3/IACK

V_DDINT

GND

D4/IS

D5/IAL

D6/IRD

D7/IWR

D8

GND

V_DDEXT

D9

D10

D11

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

GND

PF1 [MODE B]

PF0 [MODE A]

BGH

PWDACK

A0

A1/IAD0

A2/IAD1

A3/IAD2

RD

BMS

DMS

PMS

IOMS

CMS

GND

D12

D13

D14

D15

–36–

REV. 0

ADSP-2185M

144-Ball Mini-BGA Package Pinout (Bottom View)

1

12

11

10

9

8

7

6

5

4

3

2

GND

D22

NC

GND

NC

A0

GND

A1/IAD0

A2/IAD1

A

B

C

D

E

F

D16

D14

GND

D10

D9

D17

NC

D18

D15

D12

D20

D19

D23

D21

V

GND

NC

A5/IAD4

BGH

GND

A3/IAD2

A6/IAD5

WR

A4/IAD3

PWDACK

NC

DDEXT

V

A7/IAD6

A9/IAD8

PWD

RD

DDEXT

PF2

[MODE C]

PF1

[MODE B]

NC

D13

NC

PF3

[MODE D]

PF0

[MODE A]

GND

NC

V

GND

D11

GND

FL2

NC

FL0

A8/IAD7

A12/IAD11

GND

V

DDEXT

D8

NC

FL1

NC

A11/IAD10

A10/IAD9

GND

NC

A13/IAD12

XTAL

D7/IWR

D6/IRD

D2/IAD15

RFS1/IRQ0

SCLK1

GND

NC

D5/IAL

NC

G

H

J

D4/IS

GND

NC

GND

TFS0

DT0

V

GND

CLKIN

D3/IACK

BG

DDINT

V

D1/IAD14

D0/IAD13

SCLK0

RFS0

V

NC

V

CLKOUT

NC

DDINT

DDEXT

DDINT

NC

K

L

EBG

EINT

ECLK

BR

EBR

ERESET

RESET

NC

TFS1/IRQ1

DR0

DMS

GND

BMS

IOMS

CMS

ELOUT

EE

ELIN

PMS

IRQL1 + PF6

IRQE + PF4

GND

DR1/FI

DT1/FO

NC

M

EMS

IRQ2 + PF7 IRQL0 + PF5

REV. 0

–37–

ADSP-2185M

The Mini-BGA package pinout is shown in the table below. Pin names in bold text replace the plain text named functions when

Mode C = 1. A + sign separates two functions when either function can be active for either major I/O mode. Signals enclosed in

brackets [ ] are state bits latched from the value of the pin at the deassertion of RESET.

The multiplexed pins DT1/FO, TFS1/IRQ1, RFS1/IRQ0, and DR1/FI, are mode selectable by setting Bit 10 (SPORT1 configure) of

the System Control Register. If Bit 10 = 1, these pins have serial port functionality. If Bit 10 = 0, these pins are the external interrupt

and flag pins. This bit is set to 1 by default upon reset.

Mini-BGA Package Pinout

Ball #

Pin Name

Ball #

Pin Name

Ball #

Pin Name

Ball #

Pin Name

A01

A02

A03

A04

A05

A06

A07

A08

A09

A10

A11

A12

A2/IAD1

A1/IAD0

GND

A0

NC

GND

NC

D22

GND

D01

D02

D03

D04

D05

D06

D07

D08

D09

D10

D11

D12

NC

WR

NC

BGH

A9/IAD8

PF1 [MODE B]

PF2 [MODE C]

NC

D13

D12

G01

G02

G03

G04

G05

G06

G07

G08

G09

G10

G11

G12

XTAL

NC

GND

A10/IAD9

NC

D6/IRD

D5/IAL

NC

K01

K02

K03

K04

K05

K06

K07

K08

K09

K10

K11

K12

NC

BMS

DMS

RFS0

TFS1/IRQ1

SCLK1

ERESET

EBR

NC

GND

NC

D4/IS

BR

EBG

B01

B02

B03

B04

B05

B06

B07

B08

B09

B10

B11

B12

A4/IAD3

A3/IAD2

GND

NC

E01

E02

E03

E04

E05

E06

E07

E08

E09

E10

E11

E12

V_DDEXT

A8/IAD7

FL0

PF0 [MODE A]

FL2

PF3 [MODE D]

GND

H01

H02

H03

H04

H05

H06

H07

H08

H09

H10

H11

H12

CLKIN

GND

V_DDINT

DT0

L01

L02

L03

L04

L05

L06

L07

L08

L09

L10

L11

L12

IRQE + PF4

NC

IRQL1 + PF6

IOMS

GND

PMS

DR0

GND

RESET

ELIN

ELOUT

EINT

NC

GND

V_DDEXT

D23

D20

D18

TFS0

D2/IAD15

D3/IACK

GND

NC

GND

V_DDEXT

GND

D10

D17

D16

C01

C02

C03

C04

C05

C06

C07

C08

C09

C10

C11

C12

PWDACK

A6/IAD5

RD

A5/IAD4

A7/IAD6

PWD

V_DDEXT

D21

D19

F01

F02

F03

F04

F05

F06

F07

F08

F09

F10

F11

F12

A13/IAD12

NC

A12/IAD11

A11/IAD10

FL1

NC

D7/IWR

D11

D8

J01

J02

J03

J04

J05

J06

J07

J08

J09

J10

J11

J12

CLKOUT

V_DDINT

NC

V_DDEXT

SCLK0

D0/IAD13

RFS1/IRQ0

BG

M01

M02

M03

M04

M05

M06

M07

M08

M09

M10

M11

M12

IRQL0 + PF5

IRQL2 + PF7

NC

CMS

GND

DT1/FO

DR1/FI

GND

NC

EMS

D15

NC

D14

D1/IAD14

V_DDINT

NC

D9

EE

ECLK

–38–

REV. 0

ADSP-2185M

OUTLINE DIMENSIONS

Dimensions shown in millimeters.

100-Lead Metric Thin Plastic Quad Flatpack (LQFP)

(ST-100)

16.20

16.00 TYP SQ

15.80

14.05

14.00 TYP SQ

13.95

1.60 MAX

12.00 BSC

0.75

0.60 TYP

0.50

100

1

76

75

12؇

TYP

SEATING

PLANE

TOP VIEW

(PINS DOWN)

0.08

25

26

51

50

MAX LEAD

6؇ 4؇

COPLANARITY

0؇ – 7؇

0.50

BSC

0.27

0.22 TYP

0.17

0.15

0.05

LEAD PITCH

LEAD WIDTH

NOTE:

THE ACTUAL POSITION OF EACH LEAD IS WITHIN 0.08 FROM ITS IDEAL

POSITION WHEN MEASURED IN THE LATERAL DIRECTION.

REV. 0

–39–

ADSP-2185M

OUTLINE DIMENSIONS

Dimensions shown in millimeters.

144-Ball Mini-BGA

(CA-144)

10.10

10.00 SQ

9.90

12 11 10

9 8 7 6 5 4 3 2 1

A

B

C

D

E

F

G

H

J

8.80

10.10

BSC

TOP VIEW

10.00 SQ

9.90

0.80

BSC

K

L

M

0.80 BSC

8.80 BSC

DETAIL A

1.40 MAX

NOTES:

DETAIL A

1.00

0.85

1. THE ACTUAL POSITION OF THE BALL POPULATION

IS WITHIN 0.150 OF ITS IDEAL POSITION RELATIVE

TO THE PACKAGE EDGES.

2. THE ACTUAL POSITION OF EACH BALL IS WITHIN 0.08

OF ITS IDEAL POSITION RELATIVE TO THE BALL

POPULATION.

0.40

0.25

0.55

0.50

0.45

SEATING

PLANE

0.12

MAX

BALL DIAMETER

ORDERING GUIDE

Ambient Temperature

Range

Instruction

Rate

Package

Description*

Package

Option

Part Number

ADSP-2185MKST-300

ADSP-2185MBST-266

ADSP-2185MKCA-300

ADSP-2185MBCA-266

0°C to 70°C

75

66

75

66

100-Lead LQFP

144-Ball Mini-BGA

ST-100

CA-144

–40°C to +85°C

0°C to 70°C

–40°C to +85°C

*In 1998, JEDEC reevaluated the specifications for the TQFP package designation, assigning it to packages 1.0 mm thick. Previously labeled TQFP packages (1.6 mm

thick) are now designated as LQFP.

–40–

REV. 0


型号：	ADSP-2185MKCA-300
厂家：	ADI
描述：	DSP Microcomputer 微电脑DSP 电脑
文件：	总40页 (文件大小：286K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADSP-2185MKCA-300 [ADI]

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