ADSP-2188MKST-300X_技术文档

DSP

Microcomputer

Preliminary Technical Data ADSP-2188M

÷

FEATURES

Performance

12.5 ns Instruction Cycle Time @ 2.5 Volts (internal), 75 MIPS Sustained Performance

Single-Cycle Instruction Execution

Single-Cycle Context Switch

3-Bus Architecture Allows Dual Operand Fetches in Every Instruction Cycle

Multifunction Instructions

•

Powerdown Mode Featuring Low CMOS Standby Power Dissipation with 200 CLKIN Cycle Recovery from

Powerdown Condition

Low Power Dissipation in Idle Mode

•

Integration

ADSP-2100 Family Code Compatible (easy to use algebraic syntax), with Instruction Set Extensions

•

256K Bytes of On-Chip RAM, Configured as 48K Words On-Chip Program Memory RAM and 56K Words

On-Chip Data Memory RAM

•

Dual Purpose Program Memory for Both Instruction and Data Storage

Independent ALU, Multiplier/Accumulator, & Barrel Shifter Computational Units

Two Independent Data Address Generators

Powerful Program Sequencer Provides Zero Overhead Looping Conditional Instruction Execution

Programmable 16-Bit Interval Timer with Prescaler

•

100-Lead LQFP

System Interface

Flexible I/O structure allows 2.5V or 3.3V operation; all inputs tolerate up to 3.6V regardless of mode

16-Bit Internal DMA Port for High Speed Access to on-Chip Memory (Mode Selectable)

4 MByte Memory Interface for Storage of Data Tables & Program Overlays (Mode Selectable)

8-Bit DMA to Byte Memory for Transparent Program and Data Memory Transfers (Mode Selectable)

I/O Memory Interface with 2048 Locations Supports Parallel Peripherals (Mode Selectable)

Programmable Memory Strobe & Separate I/O Memory Space Permits “Glueless” System Design

Programmable Wait State Generation

•

Two Double-Buffered Serial Ports with Companding Hardware and Automatic Data Buffering

Automatic Booting of On-Chip Program Memory from Byte-Wide External Memory, e.g., EPROM, or

Through Internal DMA Port

Six External Interrupts

•

13 Programmable Flag Pins Provide Flexible System Signaling

UART Emulation through Software SPORT Reconfiguration

ICE-Port™ Emulator Interface Supports Debugging in Final Systems

This information applies to a product under development. Its characteristics and

specifications are subject to change without notice. Analog Devices assumes no

obligation regarding future manufacturing unless otherwise agreed to in writing.

One Technology Way

P.O. Box 9106

Norwood MA 02062-9106

U.S.A.

http://www.analog.com/dsp

Tel: 1-800-ANALOG-D

Fax: 1-781-461-3010

REV. PrA

Analog Devices Inc., 1999

April 1999

ADSP-2188M Preliminary Data Sheet

For current information contact Analog Devices at (781) 461-3881

General note

This data sheet represents preliminary (x- grade) specifications for the ADSP-2188M 2.5V processor.

GENERAL DESCRIPTION

The ADSP-2188M is a single-chip microcomputer optimized for digital signal processing (DSP) and

other high speed numeric processing applications.

The ADSP-2188M combines the ADSP-2100 family base architecture (three computational units, data

address generators and a program sequencer) with two serial ports, a 16-bit internal DMA port, a byte

DMA port, a programmable timer, Flag I/O, extensive interrupt capabilities, and on-chip program and

data memory.

The ADSP-2188M integrates 256K bytes of on-chip memory configured as 48K words (24-bit) of

program RAM, and 56K words (16-bit) of data RAM. Power down circuitry is also provided to meet

the low power needs of battery operated portable equipment. The ADSP-2188M is available in a 100-

pin LQFP package.

In addition, the ADSP-2188M supports new instructions, which include bit manipulations—bit set,

bit clear, bit toggle, bit test—new ALU constants, new multiplication instruction (x squared), biased

rounding, result free ALU operations, I/O memory transfers, and global interrupt masking, for

increased flexibility.

Fabricated in a high speed, low power, CMOS process, the ADSP-2188M operates with a 13.3 ns

instruction cycle time. Every instruction can execute in a single processor cycle.

The ADSP-2188M’s flexible architecture and comprehensive instruction set allow the processor to

perform multiple operations in parallel. In one processor cycle, the ADSP-2188M can:

Generate the next program address

Fetch the next instruction

•

Perform one or two data moves

Update one or two data address pointers

Perform a computational operation

This takes place while the processor continues to:

Receive and transmit data through the two serial ports

Receive and/or transmit data through the internal DMA port

Receive and/or transmit data through the byte DMA port

Decrement timer

•

DEVELOPMENT SYSTEM

The ADSP-2100 Family Development Software, a complete set of tools for software and hardware

system development, supports the ADSP-2188M. The System Builder provides a high level method for

defining the architecture of systems under development. The Assembler has an algebraic syntax that is

easy to program and debug. The Linker combines object files into an executable file. The Simulator

provides an interactive instruction-level simulation with a reconfigurable user interface to display

different portions of the hardware environment.

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

2

REV. PrA

ADSP-2188M Preliminary Data Sheet

For current information contact Analog Devices at (781) 461-3881

April 1999

A PROM Splitter generates PROM programmer compatible files. The C Compiler, based on the Free

Software Foundation’s GNU C Compiler, generates ADSP-2188M assembly source code. The source

code debugger allows programs to be corrected in the C environment. The Runtime Library includes

over 100 ANSI-standard mathematical and DSP-specific functions.

The EZ-KIT Lite is a hardware/software kit offering a complete development environment for the

entire ADSP-21xx family: an ADSP-218x based evaluation board with PC monitor software plus

Assembler, Linker, Simulator, and PROM Splitter software. The ADSP-218x EZ-KIT Lite is a low

cost, easy to use hardware platform on which you can quickly get started with your DSP software

design. The EZ-KIT Lite includes the following features:

33 MHz ADSP-218x

•

Full 16-bit Stereo Audio I/O with AD1847 SoundPort® Codec

RS-232 Interface to PC with Windows 3.1 Control Software

EZ-ICE Connector for Emulator Control

DSP Demo Programs

The ADSP-218x EZ-ICE® Emulator aids in the hardware debugging of an ADSP-2188M system. The

emulator consists of hardware, host computer resident software, and the target board connector. The

ADSP-2188M integrates on-chip emulation support with a 14-pin ICE-Port interface. This interface

provides a simpler target board connection that requires fewer mechanical clearance considerations than

other ADSP-2100 Family EZ-ICEs. The ADSP-2188M device need not be removed from the target

system when using the EZ-ICE, nor are any adapters needed. Due to the small footprint of the EZ-ICE

connector, emulation can be supported in final board designs.

The EZ-ICE performs a full range of functions, including:

In-target operation

•

Up to 20 breakpoints

Single-step or full-speed operation

Registers and memory values can be examined and altered

PC upload and download functions

Instruction-level emulation of program booting and execution

Complete assembly and disassembly of instructions

C source-level debugging

See “Designing An EZ-ICE-Compatible Target System” in the ADSP-2100 Family EZ-Tools Manual

(ADSP-2181 sections) as well as the “Designing an EZ-ICE compatible System” section of this data

sheet for the exact specifications of the EZ-ICE target board connector.

Additional Information

This data sheet provides a general overview of ADSP-2188M functionality. For additional information

on the architecture and instruction set of the processor, refer to the ADSP-2100 Family User’s Manual.

For more information about the development tools, refer to the ADSP-2100 Family Development

Tools Data Sheet.

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

REV. PrA

3

April 1999

ADSP-2188M Preliminary Data Sheet

For current information contact Analog Devices at (781) 461-3881

ARCHITECTURE OVERVIEW

The ADSP-2188M instruction set provides flexible data moves and multifunction (one or two data

moves with a computation) instructions. Every instruction can be executed in a single processor cycle.

The ADSP-2188M assembly language uses an algebraic syntax for ease of coding and readability. A

comprehensive set of development tools supports program development.

32:(5'2:1

&21752/

0(02 5<

)8// 0(02 5< 02'(

'$7$ $''5(66

*(1(5$7256

(;7(51$/

$''5(66

%86

'DWD 0HP RU\

èç. [ ìçðELW

3URJUDP 0 HP RU\

éå. [ ëéðELW

352*5$00$%/(

352*5$0

6(48(1&(5

, î 2

DQG

)/$*6

'$* ì '$* ë

(;7(51$/

'$7$

352*5$0 0(025< $''5(66

%86

%<7( '0 $

'$7$ 0(025< $''5(66

352*5$0 0(025< '$7$

'$7$ 0(025< '$7$

&21752//(5

25

(;7(51$/

'$ 7$

%86

6(5,$/ 32576

$5,7+0(7,& 81,76

7,0(5

632 57 í

63 2 57ì

,17(51$/

'0$

6+,)7(5

$/8

0$&

32 57

$'63ðëìíí %$6(

$5&+,7(&785(

+267 02 '(

Figure 1 FUNCTIONAL BLOCK DIAGRAM

Figure 1 is an overall block diagram of the ADSP-2188M. The processor contains three independent

computational units: the ALU, the multiplier/accumulator (MAC) and the shifter. The computational

units process 16-bit data directly and have provisions to support multiprecision computations. The

ALU performs a standard set of arithmetic and logic operations; division primitives are also supported.

The MAC performs single-cycle multiply, multiply/add and multiply/subtract operations with 40 bits

of accumulation. The shifter performs logical and arithmetic shifts, normalization, denormalization,

and derive exponent operations.

The shifter can be used to efficiently implement numeric format control including multi-word and

block floating-point representations.

The internal result (R) bus connects the computational units so that the output of any unit may be the

input of any unit on the next cycle.

A powerful program sequencer and two dedicated data address generators ensure efficient delivery of

operands to these computational units. The sequencer supports conditional jumps, subroutine calls and

returns in a single cycle. With internal loop counters and loop stacks, the ADSP-2188M executes

looped code with zero overhead; no explicit jump instructions are required to maintain loops.

Two data address generators (DAGs) provide addresses for simultaneous dual operand fetches (from

data memory and program memory). Each DAG maintains and updates four address pointers.

Whenever the pointer is used to access data (indirect addressing), it is post-modified by the value of one

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

4

REV. PrA

ADSP-2188M Preliminary Data Sheet

For current information contact Analog Devices at (781) 461-3881

April 1999

of four possible modify registers. A length value may be associated with each pointer to implement

automatic modulo addressing for circular buffers.

Efficient data transfer is achieved with the use of five internal buses:

Program Memory Address (PMA) Bus

Program Memory Data (PMD) Bus

Data Memory Address (DMA) Bus

Data Memory Data (DMD) Bus

Result (R) Bus

•

The two address buses (PMA and DMA) share a single external address bus, allowing memory to be

expanded off-chip, and the two data buses (PMD and DMD) share a single external data bus. Byte

memory space and I/O memory space also share the external buses.

Program memory can store both instructions and data, permitting the ADSP-2188M to fetch two

operands in a single cycle, one from program memory and one from data memory. The ADSP-2188M

can fetch an operand from program memory and the next instruction in the same cycle.

In lieu of the address and data bus for external memory connection, the ADSP-2188M may be

configured for 16-bit Internal DMA port (IDMA port) connection to external systems. The IDMA port

is made up of 16 data/address pins and five control pins. The IDMA port provides transparent, direct

access to the DSPs on-chip program and data RAM.

An interface to low cost byte-wide memory is provided by the Byte DMA port (BDMA port). The

BDMA port is bidirectional and can directly address up to four megabytes of external RAM or ROM

for off-chip storage of program overlays or data tables.

The byte memory and I/O memory space interface supports slow memories and I/O memory-mapped

peripherals with programmable wait state generation. External devices can gain control of external

buses with bus request/grant signals (BR, BGH, and BG). One execution mode (Go Mode) allows the

ADSP-2188M to continue running from on-chip memory. Normal execution mode requires the

processor to halt while buses are granted.

The ADSP-2188M can respond to eleven interrupts. There can be up to six external interrupts (one

edge-sensitive, two level-sensitive, and three configurable) and seven internal interrupts generated by

the timer, the serial ports (SPORTs), the Byte DMA port, and the power-down circuitry. There is also

a master RESET signal.The two serial ports provide a complete synchronous serial interface with

optional companding in hardware and a wide variety of framed or frameless data transmit and receive

modes of operation.

Each port can generate an internal programmable serial clock or accept an external serial clock.

The ADSP-2188M provides up to 13 general-purpose flag pins. The data input and output pins on

SPORT1 can be alternatively configured as an input flag and an output flag. In addition, there are eight

flags that are programmable as inputs or outputs, and three flags that are always outputs.

A programmable interval timer generates periodic interrupts. A 16-bit count register (TCOUNT)

decrements every n processor cycles, where n is a scaling value stored in an 8-bit register (TSCALE).

When the value of the count register reaches zero, an interrupt is generated and the count register is

reloaded from a 16-bit period register (TPERIOD).

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

REV. PrA

5

April 1999

ADSP-2188M Preliminary Data Sheet

For current information contact Analog Devices at (781) 461-3881

Serial Ports

The ADSP-2188M incorporates two complete synchronous serial ports (SPORT0 and SPORT1) for

serial communications and multiprocessor communication.

Here is a brief list of the capabilities of the ADSP-2188M SPORTs. For additional information on

Serial Ports, refer to the ADSP-2100 Family User’s Manual.

SPORTs are bidirectional and have a separate, double-buffered transmit and receive section.

SPORTs can use an external serial clock or generate their own serial clock internally.

•

SPORTs have independent framing for the receive and transmit sections. Sections run in a frameless

mode or with frame synchronization signals internally or externally generated. Frame sync signals

are active high or inverted, with either of two pulse widths and timings.

SPORTs support serial data word lengths from 3 to 16 bits and provide optional A-law and µ-law

companding according to CCITT recommendation G.711.

•

SPORT receive and transmit sections can generate unique interrupts on completing a data word

transfer.

SPORTs can receive and transmit an entire circular buffer of data with only one overhead cycle per

data word. An interrupt is generated after a data buffer transfer.

SPORT0 has a multichannel interface to selectively receive and transmit a 24 or 32 word, time-

division multiplexed, serial bitstream.

SPORT1 can be configured to have two external interrupts (IRQ0 and IRQ1) and the Flag In and

Flag Out signals. The internally generated serial clock may still be used in this configuration.

Pin Descriptions

The ADSP-2188M will be available in a 100-lead LQFP package. In order to maintain maximum

functionality and reduce package size and pin count, some serial port, programmable flag, interrupt and

external bus pins have dual, multiplexed functionality. The external bus pins are configured during

RESET only, while serial port pins are software configurable during program execution. Flag and

interrupt functionality is retained concurrently on multiplexed pins. In cases where pin functionality is

reconfigurable, the default state is shown in plain text; alternate functionality is shown in italics.

Common Mode Pins

Pin Name(s)

# of I/O

Pins

Function

RESET

BR

1

I

Processor Reset Input

I

Bus Request Input

BG

O

Bus Grant Output

BGH

DMS

PMS

IOMS

Bus Grant Hung Output

Data Memory Select Output

Program Memory Select Output

Memory Select Output

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

6

REV. PrA

ADSP-2188M Preliminary Data Sheet

For current information contact Analog Devices at (781) 461-3881

April 1999

Common Mode Pins (Continued)

Pin Name(s)

# of I/O

Pins

Function

BMS

CMS

RD

1

O

Byte Memory Select Output

Combined Memory Select Output

Memory Read Enable Output

Memory Write Enable Output

WR

1

IRQ2

PF7

I

Edge- or Level-Sensitive Interrupt Request

Programmable I/O Pin

I/O

1

IRQL0

PF6

1

2

I

Level-Sensitive Interrupt Requests

Programmable I/O Pin

I/O

1

IRQL1

PF5

I

Level-Sensitive Interrupt Requests

Programmable I/O Pin

I/O

1

IRQE

PF4

I

Edge-Sensitive Interrupt Requests

Programmable I/O Pin

I/O

Mode D

PF3

I

Mode Select Input - Checked only coming out of RESET

Programmable I/O Pin during normal operation

I/O

Mode C

PF2

I

Mode Select Input - Checked only coming out of RESET

Programmable I/O Pin during normal operation

I/O

Mode B

PF1

I

Mode Select Input - Checked only coming out of RESET

Programmable I/O Pin during normal operation

I/O

Mode A

PF0

I

Mode Select Input - Checked only coming out of RESET

Programmable I/O Pin during normal operation

I/O

CLKIN

XTAL

I

Clock or Quartz Crystal Input

CLKOUT

SPORT0

1

5

O

Processor Clock Output

Serial Port I/O Pins

I/O

SPORT1

2

IRQ1:0, FI, FO

Edge- or Level-Sensitive Interrupts, Flag In, Flag Out

PWD

1

3

2

I

Powerdown Control Input

Powerdown Control Output

Output Flags

PWDACK

FL0, FL1, FL2

O

I

V

Internal VDD (2.5V) Power

DDINT

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

REV. PrA

7

April 1999

ADSP-2188M Preliminary Data Sheet

For current information contact Analog Devices at (781) 461-3881

Common Mode Pins (Continued)

Pin Name(s)

# of I/O

Pins

Function

V

4

I

External VDD (2.5V or 3.3V) Power

Ground

DDEXT

GND

10

9

I

EZ-Port

I/O

For emulation use

1. Interrupt/Flag Pins retain both functions concurrently. If IMASK is set to enable the corresponding interrupts, then the DSP will vector

to the appropriate interrupt vector address when the pin is asserted, either by external devices, or set as a programmable flag.

2. SPORT configuration determined by the DSP System Control Register. Software configurable

Memory Interface Pins

The ADSP-2188M processor can be used in one of two modes, Full Memory Mode, which allows

BDMA operation with full external overlay memory and I/O capability, or Host Mode, which allows

IDMA operation with limited external addressing capabilities. The operating mode is determined by

the state of the Mode C pin during RESET and cannot be changed while the processor is running.

Full Memory Mode Pins (Mode C = 0)

Pin Name

# of I/O

Pins

Function

A13:0

D23:0

14

24

O

Address Output Pins for Program, Data, Byte and I/O Spaces

I/O

Data I/O Pins for Program, Data, Byte and I/O Spaces (8 MSBs

are also used as Byte Memory addresses)

Host Mode Pins (Mode C = 1)

Pin Name

# of I/O

Pins

Function

IAD15:0

A0

16

1

I/O

O

I/O

I

IDMA Port Address/Data Bus

1

Address Pin for External I/O, Program, Data, or Byte access

D23:8

IWR

IRD

16

1

Data I/O Pins for Program, Data Byte and I/O spaces

IDMA Write Enable

1

I

IDMA Read Enable

IAL

1

I

IDMA Address Latch Pin

IS

1

I

IDMA Select

IACK

1

O

IDMA Port Acknowledge Configurable in Mode D; Open Drain

^{1. In Host Mode, external peripheral addresses can be decoded using the A0,}CMS^,PMS^,DMS^{, and}IOMS ^signals

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

8

REV. PrA

ADSP-2188M Preliminary Data Sheet

For current information contact Analog Devices at (781) 461-3881

April 1999

Interrupts

The interrupt controller allows the processor to respond to the eleven possible interrupts and reset with

minimum overhead. The ADSP-2188M provides four dedicated external interrupt input pins, IRQ2,

IRQL0, IRQL1, and IRQE (shared with the PF7:4 pins). In addition, SPORT1 may be reconfigured

for IRQ0, IRQ1, FLAG_IN and FLAG_OUT, for a total of six external interrupts. The ADSP-2188M

also supports internal interrupts from the timer, the byte DMA port, the two serial ports, software, and

the power-down control circuit. The interrupt levels are internally prioritized and individually

maskable (except power down and reset). The IRQ2, IRQ0, and IRQ1 input pins can be programmed

to be either level- or edge-sensitive. IRQL0 and IRQL1 are level-sensitive and IRQE is edge sensitive.

The priorities and vector addresses of all interrupts are shown in Table 1.

Table 1 Interrupt Priority & Interrupt Vector Addresses

Source Of Interrupt

Reset (or Power-Up with PUCR = 1)

Power Down (Nonmaskable)

IRQ2

Interrupt Vector Address (Hex)

0000 (Highest Priority)

002C

0004

IRQL1

0008

IRQL0

000C

SPORT0 Transmit

SPORT0 Receive

IRQE

0010

0014

0018

BDMA Interrupt

SPORT1 Transmit or IRQ1

SPORT1 Receive or IRQ0

Timer

001C

0020

0024

0028 (Lowest Priority)

Interrupt routines can either be nested with higher priority interrupts taking precedence or processed

sequentially. Interrupts can be masked or unmasked with the IMASK register. Individual interrupt

requests are logically ANDed with the bits in IMASK; the highest priority unmasked interrupt is then

selected. The power-down interrupt is nonmaskable.

The ADSP-2188M masks all interrupts for one instruction cycle following the execution of an

instruction that modifies the IMASK register. This does not affect serial port autobuffering or DMA

transfers.

The interrupt control register, ICNTL, controls interrupt nesting and defines the IRQ0, IRQ1, and

IRQ2 external interrupts to be either edge- or level-sensitive. The IRQE pin is an external edge sensitive

interrupt and can be forced and cleared. The IRQL0 and IRQL1 pins are external level sensitive

interrupts.

The IFC register is a write-only register used to force and clear interrupts. On-chip stacks preserve the

processor status and are automatically maintained during interrupt handling. The stacks are twelve

levels deep to allow interrupt, loop, and subroutine nesting. The following instructions allow global

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

REV. PrA

9

April 1999

ADSP-2188M Preliminary Data Sheet

For current information contact Analog Devices at (781) 461-3881

enable or disable servicing of the interrupts (including power down), regardless of the state of IMASK.

Disabling the interrupts does not affect serial port autobuffering or DMA.

ENA INTS;

DIS INTS;

When the processor is reset, interrupt servicing is enabled.

LOW POWER OPERATION

The ADSP-2188M has three low power modes that significantly reduce the power dissipation when the

device operates under standby conditions. These modes are:

Power Down

Idle

•

Slow Idle

The CLKOUT pin may also be disabled to reduce external power dissipation.

Power Down

The ADSP-2188M processor has a low power feature that lets the processor enter a very low power

dormant state through hardware or software control. Here is a brief list of power-down features. Refer

to the ADSP-2100 Family User’s Manual, “System Interface” chapter, for detailed information about

the power-down feature.

Quick recovery from power down. The processor begins executing instructions in as few as 200

CLKIN cycles.

•

Support for an externally generated TTL or CMOS processor clock. The external clock can contin-

ue running during power down without affecting the lowest power rating and 200 CLKIN cycle

recovery.

•

Support for crystal operation includes disabling the oscillator to save power (the processor automat-

ically waits approximately 4096 CLKIN cycles for the crystal oscillator to start or stabilize), and let-

ting the oscillator run to allow 200 CLKIN cycle start up.

•

Power down is initiated by either the power down pin (PWD) or the software power-down force

bit.Interrupt support allows an unlimited number of instructions to be executed before optionally

powering down. The power down interrupt also can be used as a non-maskable, edge sensitive in-

terrupt.

Context clear/save control allows the processor to continue where it left off or start with a clean

context when leaving the power down state.

•

The RESET pin also can be used to terminate power down.

•

Power down acknowledge pin indicates when the processor has entered power down.

Idle

When the ADSP-2188M is in the Idle Mode, the processor waits indefinitely in a low power state until

an interrupt occurs. When an unmasked interrupt occurs, it is serviced; execution then continues with

the instruction following the IDLE instruction. In Idle mode IDMA, BDMA and autobuffer cycle

steals still occur.

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

10

REV. PrA

ADSP-2188M Preliminary Data Sheet

For current information contact Analog Devices at (781) 461-3881

April 1999

Slow Idle

The IDLE instruction is enhanced on the ADSP-2188M to let the processor’s internal clock signal be

slowed, further reducing power consumption. The reduced clock frequency, a programmable fraction

of the normal clock rate, is specified by a selectable divisor given in the IDLE instruction.

The format of the instruction is:

IDLE (n);

where n = 16, 32, 64, or 128. This instruction keeps the processor fully functional, but operating at the

slower clock rate. While it is in this state, the processor’s other internal clock signals, such as SCLK,

CLKOUT, and timer clock, are reduced by the same ratio. The default form of the instruction, when

no clock divisor is given, is the standard IDLE instruction.

When the IDLE (n) instruction is used, it effectively slows down the processor’s internal clock and thus

its response time to incoming interrupts. The one-cycle response time of the standard idle state is

increased by n, the clock divisor. When an enabled interrupt is received, the ADSP-2188M will remain

in the idle state for up to a maximum of n processor cycles (n = 16, 32, 64, or 128) before resuming

normal operation.

When the IDLE (n) instruction is used in systems that have an externally generated serial clock (SCLK),

the serial clock rate may be faster than the processor’s reduced internal clock rate. Under these

conditions, interrupts must not be generated at a faster rate than can be serviced, due to the additional

time the processor takes to come out of the idle state (a maximum of n processor cycles).

SYSTEM INTERFACE

Figure 2 shows typical basic system configurations with the ADSP-2188M, two serial devices, a byte-

wide EPROM, and optional external program and data overlay memories (mode selectable).

Programmable wait state generation allows the processor connects easily to slow peripheral devices. The

ADSP-2188M also provides four external interrupts and two serial ports or six external interrupts and

one serial port. Host Memory Mode allows access to the full external data bus, but limits addressing to

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

REV. PrA

11

April 1999

ADSP-2188M Preliminary Data Sheet

For current information contact Analog Devices at (781) 461-3881

a single address bit (A0). Additional system peripherals can be added in this mode through the use of

external hardware to generate and latch address signals.

+ 2 6 7 0 ( 0 2 5 < 0 2 ' (

) 8 / / 0 ( 0 2 5 < 0 2 ' (

$ ' 6 3 ðë ì å å 0

& / . ,1

$ ' 6 3 ðë ì å å 0

& / . ,1

ìîë [ & / 2 & .

2 5

ìîë [ & / 2 & .

2 5

& 5 < 6 7 $ /

$

ì ê ðí

ì é

; 7 $ /

) / í ðë

& 5 < 6 7 $ /

$ ' ' 5 ìê ð í

ì

$ í

'

$ í ð $ ë ì

) / í ðë

ë ê ðì ç

% < 7 (

0 ( 0 2 5 <

ì ç

'

ë é

ì è ðå

,5 4 ë

,5 4 (

,5 4 / í î3) è

,5 4 / ì

î3) æ

î3) é

,5 4 ë î3 ) æ

,5 4 ( î3) é

,5 4 / í î3) è

,5 4 / ì î3) ç

' $ 7 $ ë ê ð å

% 0 6

' $ 7 $ ë ê ð í

% 0 6

' $ 7 $

& 6

î3) ç

$

ì í ðí

ë ê ðå

: 5

5 '

: 5

5 '

0 2 ' ( ' î3 ) ê

0 2 ' ( & î3 ) ë

0 2 ' ( $ î3 ) í

0 2 ' ( % î3 ) ì

0 2 ' ( ' î3 ) ê

3 ) ë

$ ' ' 5

' $ 7 $

'

0 2 ' ( & î

,î2 6 3 $ & (

õ3 ( 5 ,3 + ( 5 $ / 6 ô

0 2 ' ( $ î3 ) í

0 2 ' ( % î3 ) ì

ëí é å /2 & $ 7 ,2 1 6

,2 0 6

& 6

6 3 2 5 7 ì

6 & / . ì

5 ) 6 ì 2 5 ,5 4 í

7 ) 6 ì 2 5 ,5 4 ì

' 7 ì 2 5 ) 2

' 5 ì 2 5 ) ,

6 3 2 5 7 ì

6 & / . ì

$

'

ì ê ðí

ë ê ðí

6 ( 5 ,$ /

' ( 9 ,& (

5 ) 6 ì 2 5 ,5 4 í

7 ) 6 ì 2 5 ,5 4 ì

' 7 ì 2 5 ) 2

6 ( 5 ,$ /

' ( 9 ,& (

$ ' ' 5

' $ 7 $

2 9 ( 5 / $ <

0 ( 0 2 5 <

' 5 ì 2 5 ) ,

7 : 2 å.

3 0 6 ( * 0 ( 1 7 6

3 0 6

' 0 6

& 0 6

3 0 6

' 0 6

& 0 6

6 3 2 5 7 í

6 & / . í

5 ) 6 í

7 ) 6 í

' 7 í

6 & / . í

5 ) 6 í

7 ) 6 í

' 7 í

7 : 2 å.

' 0 6 ( * 0 ( 1 7 6

6 ( 5 ,$ /

' ( 9 ,& (

6 ( 5 ,$ /

' ( 9 ,& (

% 5

% *

% * +

% 5

% *

% * +

' 5 í

,' 0 $ 3 2 5 7

,5 ' î' ç

,: 5 î ' æ

,6 î' é

3 : '

3 : ' $ & .

3 : '

3 : ' $ & .

6 < 6 7 ( 0

,1 7 ( 5 ) $ & (

2 5

“ & 2 1 7 5 2 // ( 5

,$ / î' è

,$ & . î' ê

,$ ' ì è ðí

ì ç

Figure 2 ADSP-2188M Basic System Interface

Clock Signals

The ADSP-2188M can be clocked by either a crystal or by a TTL-compatible clock signal.

The CLKIN input cannot be halted, changed during operation, or operated below the specified

frequency during normal operation. The only exception is while the processor is in the power down

state. For additional information, refer to Chapter 9, ADSP-2100 Family User’s Manual for detailed

information on this power down feature.

If an external clock is used, it should be a TTL-compatible signal running at half the instruction rate.

The signal is connected to the processor’s CLKIN input. When an external clock is used, the XTAL

input must be left unconnected.

The ADSP-2188M uses an input clock with a frequency equal to half the instruction rate; a 37.50 MHz

input clock yields a 13.3 ns processor cycle (which is equivalent to 75 MHz). Normally, instructions

are executed in a single processor cycle. All device timing is relative to the internal instruction clock

rate, which is indicated by the CLKOUT signal when enabled.

Because the ADSP-2188M includes an on-chip oscillator circuit, an external crystal may be used. The

crystal should be connected across the CLKIN and XTAL pins, with two capacitors connected as shown

in Figure 3. Capacitor values are dependent on crystal type and should be specified by the crystal

manufacturer. A parallel-resonant, fundamental frequency, microprocessor-grade crystal should be

used.

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

12

REV. PrA

ADSP-2188M Preliminary Data Sheet

For current information contact Analog Devices at (781) 461-3881

April 1999

A clock output (CLKOUT) signal is generated by the processor at the processor’s cycle rate. This can

be enabled and disabled by the CLKODIS bit in the SPORT0 Autobuffer Control Register.

XTAL

CLKOUT

CLK IN

'63

Figure 3 External Crystal Connections

Reset

The RESET signal initiates a master reset of the ADSP-2188M. The RESET signal must be asserted

during the power-up sequence to assure proper initialization. RESET during initial power-up must be

held long enough to allow the internal clock to stabilize. If RESET is activated any time after power

up, the clock continues to run and does not require stabilization time.

The power-up sequence is defined as the total time required for the crystal oscillator circuit to stabilize

after a valid V

is applied to the processor, and for the internal phase-locked loop (PLL) to lock onto

DD

the specific crystal frequency. A minimum of 2000 CLKIN cycles ensures that the PLL has locked but

does not include the crystal oscillator start-up time. During this power-up sequence the RESET signal

should be held low. On any subsequent resets, the RESET signal must meet the minimum pulse width

specification, t

.

RSP

The RESET input contains some hysteresis; however, if you use an RC circuit to generate your RESET

signal, the use of an external Schmidt trigger is recommended.

The master reset sets all internal stack pointers to the empty stack condition, masks all interrupts and

clears the MSTAT register. When RESET is released, if there is no pending bus request and the chip is

configured for booting, the boot-loading sequence is performed. The first instruction is fetched from

on-chip program memory location 0x0000 once boot loading completes.

Power Supplies

The ADSP-2188M has separate power supply connections for the internal (V

) and external

DDINT

(V

) power supplies. The internal supply must meet the 2.5V requirement. The external supply

DDEXT

can be connected to either a 2.5V or 3.3V supply. All external supply pins must be connected to the

same supply. All input and I/O pins can tolerate input voltages up to 3.6V regardless of the external

supply voltage. This feature provides maximum flexibility in mixing 2.5V and 3.3 volt components.

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

REV. PrA

13

April 1999

ADSP-2188M Preliminary Data Sheet

For current information contact Analog Devices at (781) 461-3881

MODES OF OPERATION

Setting Memory Mode

Memory Mode selection for the ADSP-2188M is made during chip reset through the use of the Mode

C pin. This pin is multiplexed with the DSP’s PF2 pin, so care must be taken in how the mode selection

is made. The two methods for selecting the value of Mode C are active and passive.

Passive configuration involves the use a pull-up or pull-down resistor connected to the Mode C pin. To

minimize power consumption, or if the PF2 pin is to be used as an output in the DSP application, a

weak pull-up or pull-down, on the order of 100 kΩ, can be used. This value should be sufficient to pull

the pin to the desired level and still allow the pin to operate as a programmable flag output without

undue strain on the processor’s output driver. For minimum power consumption during powerdown,

reconfigure PF2 to be an input, as the pull-up or pull-down will hold the pin in a known state, and will

not switch.

Active configuration involves the use of a three-statable external driver connected to the Mode C pin.

A driver’s output enable should be connected to the DSP’s RESET signal such that it only drives the

PF2 pin when RESET is active (low). When RESET is de-asserted, the driver should three-state, thus

allowing full use of the PF2 pin as either an input or output. To minimize power consumption during

powerdown, configure the programmable flag as an output when connected to a three-stated buffer.

This ensures that the pin will be held at a constant level, and will not oscillate should the three-state

driver’s level hover around the logic switching point.

Table 2 ADSP-2188M Modes of Operation

MODE D

MODE C

MODE B

MODE A

Booting Method

BDMA feature is used to load the first 32 program memory words from the

byte memory space. Program execution is held off until all 32 words have

been loaded. Chip is configured in Full Memory Mode.¹

X

0

No Automatic boot operations occur. Program execution starts at external

memory location 0. Chip is configured in Full Memory Mode. BDMA can

still be used but the processor does not automatically use or wait for these

operations.

X

0

1

0

BDMA feature is used to load the first 32 program memory words from the

byte memory space. Program execution is held off until all 32 words have

^{been loaded. Chip is configured in Host Mode.}IACK ^{has active pull-}

down. (REQUIRES ADDITIONAL HARDWARE).

IDMA feature is used to load any internal memory as desired. Program exe-

cution is held off until internal program memory location 0 is written to.

^{Chip is configured in Host Mode.}IACK ^{has active pulldown.}¹

0

1

0

1

0

BDMA feature is used to load the first 32 program memory words from the

byte memory space. Program execution is held off until all 32 words have

^{been loaded. Chip is configured in Host Mode;}IACK ^{requires external}

pulldown. (REQUIRES ADDITIONAL HARDWARE).

IDMA feature is used to load any internal memory as desired. Program exe-

cution is held off until internal program memory location 0 is written to.

^{Chip is configured in Host Mode.}IACK ^{requires external pulldown.}¹

1

0

1

1. Considered as standard operating settings. Using these configurations allows for easier design and better memory management.

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

14

REV. PrA

ADSP-2188M Preliminary Data Sheet

For current information contact Analog Devices at (781) 461-3881

April 1999

IACK Configuration

Mode D = 0 and in host mode: IACK is an active, driven signal and cannot be “wire OR’d”.

Mode D = 1 and in host mode: IACK is an open drain and requires an external pulldown, but multiple

IACK pins can be “wire OR’d” together.

MEMORY ARCHITECTURE

The ADSP-2188M provides a variety of memory and peripheral interface options. The key functional

groups are Program Memory, Data Memory, Byte Memory, and I/O. Refer to the following figures and

tables for PM and DM memory allocations in the ADSP-2188M.

Program Memory

Program Memory (Full Memory Mode) is a 24-bit-wide space for storing both instruction opcodes and

data. The ADSP-2188M has 48K words of Program Memory RAM on chip, and the capability of

accessing up to two 8K external memory overlay spaces using the external data bus.

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

REV. PrA

15

April 1999

ADSP-2188M Preliminary Data Sheet

For current information contact Analog Devices at (781) 461-3881

Program Memory (Host Mode) allows access to all internal memory. External overlay access is limited

by a single external address line (A0). External program execution is not available in host mode due to

a restricted data bus that is 16-bits wide only.

30 õ02'( % ìô^ì

30 02'( % í

$/:$<6

$&&(66,%/(

$7 $''5(66

í[íííí ð í[ì)))

í[ëííí ð

í[ê)))

5(6(59('

í[ëííí ð

í[ê)))

$&&(66,%/( :+(1

30 29/$< í

$&&(66,%/( :+(1

30 29/$< í

í[ëííí ð

í[ê)))

5(6(59('

í[ëííí ð

í[ê)))

,17(51$/

0(025<

5(6(59('

$&&(66,%/( :+(1

30 29/$< é

í[ëííí ð

í[ê)))

5(6(59('

$&&(66,%/( :+(1

30 29/$< è

,17(51$/

0(025<

í;íííí ð

í;ì)))^ë

í[ëííí ð

í[ê)))

5(6(59('

$&&(66,%/( :+(1

30 29/$< ç

í;íííí ð

í;ì)))^ë

í;ëííí ð

í;ê)))^ë

$&&(66,%/( :+(1

30 29/$< æ

$&&(66,%/( :+(1

3029/$< í

í;ëííí ð

í;ê)))^ë

(;7(51$/

0(025<

5(6(59('

$&&(66,%/( :+(1

3029/$< ì

(;7(51$/

0(025<

$&&(66,%/( :+(1

3029/$< ë

^ì:+(1 02'( % ìñ 3029/$< 0867 %( 6(7 72 í

^ë6(( 7$%/( ,,, )25 3029/$< %,76

352*5$0 0(025<

02'( % í

352*5$0 0(025<

$''5(66

í[ê)))

02'( % ì

í[ê)))

å. ,17(51$/

3029/$< íñ éñ èñ çñæ

25

å. (;7(51$/

3029/$< ìñ ë

å. ,17(51$/

3029/$< í

í[ëííí

í[ì)))

í[ëííí

í[ì)))

å.

,17(51$/

å.

(;7(51$/

í[íííí

Figure 4 Program Memory

Table 3 PMOVLAY bits

PMOVLAY

0, 4, 5, 6, 7

1

Memory

Internal

A13

A12:0

Not Applicable

External Overlay 1

0

13 LSBs of Address Between

0x2000 and 0x3FFF

2

External Overlay 2

1

13 LSBs of Address Between

0x2000and 0x3FFF

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

16

REV. PrA

ADSP-2188M Preliminary Data Sheet

For current information contact Analog Devices at (781) 461-3881

April 1999

Data Memory

Data Memory (Full Memory Mode) is a 16-bit-wide space used for the storage of data variables and for

memory-mapped control registers. The ADSP-2188M has 56K words on Data Memory RAM on chip.

Part of this space is used by 32 memory-mapped registers. Support also exists for up to two 8K external

memory overlay spaces through the external data bus. All internal accesses complete in one cycle.

Accesses to external memory are timed using the wait states specified by the DWAIT register and the

waitstate mode bit.

'$7$0(025<

'$7$ 0(025<

$''5

í[ê)))

êë 0(025<

0$33('

$/:$<6

$&&(66,%/(

$7$''5(66

í[ëíííðí[ê)))

5(*,67(56

í[ê)(í

í[ê)')

,17(51$/

åìçí :25'6

í[ëííí

í[ì)))

í[ííííðí[ì)))

å. ,17(51$/

'029/$<

íñ éñ èñ çñ æñ å

í[ííííðí[ì)))

$&&(66,%/(:+(1

'029/$< í

í[ííííðí[ì)))

25

(;7(51$/ å.

'029/$< ìñ ë

$&&(66,%/(:+(1

'029/$< é

í[ííííðí[ì)))

í[íííí

$&&(66,%/(:+(1

'029/$< è

$&&(66,%/(:+(1

'029/$< ç

í[ííííðí[ì)))

,17(51$/

0(025<

$&&(66,%/(:+(1

'029/$< æ

í;ííííð í;ì)))

$&&(66,%/(:+(1

'029/$< å

$&&(66,%/(:+(1

'029/$< ì

(;7(51$/

0(025<

$&&(66,%/(:+(1

'029/$< ë

Figure 5 Data Memory Map

Data Memory (Host Mode) allows access to all internal memory. External overlay access is limited by

a single external address line (A0).

Table 4 DMOVLAY bits

DMOVLAY

0, 4, 5, 6, 7, 8

1

Memory

A13

A12:0

Internal

Not Applicable

0

Not Applicable

External Overlay 1

13 LSBs of Address Between

0x2000 and0x3FFF

2

External Overlay 2

1

13 LSBs of Address Between

0x2000and 0x3FFF

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

REV. PrA

17

April 1999

ADSP-2188M Preliminary Data Sheet

For current information contact Analog Devices at (781) 461-3881

Memory Mapped Registers (New to the ADSP-2188M)

The ADSP-2188M has three memory mapped registers that differ from other ADSP-21xx Family

DSPs. The slight modifications to these registers (Waitstate Control, Programmable Flag & Composite

Select Control, and System Control) provide the ADSP-2188M’s waitstate and BMS control features.

:$,767$7( &217 52/

ìè ìé ìê ìë ìì ìí

ä

å

æ

ç

è

é

ê

ì

ë

ì

í

ì

'0 õí[ê))(ô

ì

':$,7

,2: $,7 ê

,2: $,7 ë

,2: $,7 ì

,2: $,7 í

:DLW 6WDWH 0RGH 6HOHFW õ$'63ðëìåå0ô

í 1RUPDO PRGH õ':$,7ñ ,2: $,7 íðê 1 ZDLW VWDWHVñ UDQJLQJ IURP í WR æô

ì ë1òì PRGH õ':$,7ñ ,2: $,7íðê ë1òì ZDLW VWDWHVñ UDQJLQJ IURP í WR ìèô

Figure 6 Waitstate Control Register (ADSP-2188M)

352* 5$00$%/( )/$* ÷ &20326,7 ( 6(/(&7 &21752/

ìè ìé ìê ìë ìì ìí

ä

ì

å

ì

æ

ç

ì

è

é

ê

ì

ë

ì

í

ì

'0õí[ê)(çô

ì

%0: $,7

õELWðìèñ $'63ðëìåå0ô

&066(/

í 'LVDEOH &06

ì (QDEOH &06

3)7<3(

í ,QSXW

ì 2XWSXW

õZKHUH ELWã ììð,2 0ñ ìíð%0ñ äð'0 ñ åð30ô

Figure 7 Programmable Flag & Composite Select Control Register (ADSP-2188M)

6<67(0 &21752/

ìè ìé ìê ìë ìì ìí

ä

å

æ

ç

è

é

ê

í

ë

ì

í

ì

'0õí[ê)))ô

í

ì

í

63257í (QDEOH

í 'LVDEOH

ì (QDEOH

5(6(59('ñ $/:$<6 í

õ$'63ðëìåå0ô

3:$,7

3URJUDP 0HPRU\

:DLW 6WDWHV

63257ì (QDEOH

í 'LVDEOH

ì (QDEOH

63257ì &RQILJXUH

í ),ñ )2ñ ,54íñ ,54ìñ 6&/.

ì 63257ì

'LVDEOH %06 õ$'63ðëìåå0ô

í (QDEOH %06 õDV RQ $'63ðëìåæô

ì 'LVDEOH %06ñ H[FHSW ZKHQ

PHPRU\ VWUREHV DUH WKUHHðVWDWHG

Figure 8 System Control Register (ADSP-2188M)

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

18

REV. PrA

ADSP-2188M Preliminary Data Sheet

For current information contact Analog Devices at (781) 461-3881

April 1999

I/O Space (Full Memory Mode)

The ADSP-2188M supports an additional external memory space called I/O space. This space is

designed to support simple connections to peripherals (such as data converters and external registers)

or to bus interface ASIC data registers. I/O space supports 2048 locations of 16-bit wide data. The

lower eleven bits of the external address bus are used; the upper three bits are undefined. Two

instructions were added to the core ADSP-2100 Family instruction set to read from and write to I/O

memory space. The I/O space also has four dedicated three-bit wait state registers, IOWAIT0-3, which

in combination with the waitstate mode bit, specify up to 15 wait states to be automatically generated

for each of four regions. The wait states act on address ranges as shown in Table 5.

Table 5 Wait States

Address Range

0x000–0x1FF

0x200–0x3FF

0x400–0x5FF

0x600–0x7FF

Wait State Register

IOWAIT0 and Wait State Mode Select bit

IOWAIT1 and Wait State Mode Select bit

IOWAIT2 and Wait State Mode Select bit

IOWAIT3 and Wait State Mode Select bit

Composite Memory Select (CMS)

The ADSP-2188M has a programmable memory select signal that is useful for generating memory

select signals for memories mapped to more than one space. The CMS signal is generated to have the

same timing as each of the individual memory select signals (PMS, DMS, BMS, IOMS) but can

combine their functionality.

Each bit in the CMSSEL register, when set, causes the CMS signal to be asserted when the selected

memory select is asserted. For example, to use a 32K word memory to act as both program and data

memory, set the PMS and DMS bits in the CMSSEL register and use the CMS pin to drive the chip

select of the memory, and use either DMS or PMS as the additional address bit.

The CMS pin functions like the other memory select signals with the same timing and bus request logic.

A 1 in the enable bit causes the assertion of the CMS signal at the same time as the selected memory

select signal. All enable bits default to 1 at reset, except the BMS bit.

Byte Memory Select (BMS)

The ADSP-2188M’s BMS disable feature combined with the CMS pin lets you use multiple memories

in the byte memory space. For example, an EPROM could be attached to the BMS select, and an SRAM

could be connected to CMS. Because at reset BMS is enabled, the EPROM would be used for booting.

After booting, software could disable BMS and set the CMS signal to respond to BMS, enabling the

SRAM.

Byte Memory

The byte memory space is a bidirectional, 8-bit-wide, external memory space used to store programs

and data. Byte memory is accessed using the BDMA feature. The byte memory space consists of 256

pages, each of which is 16K x 8.

The byte memory space on the ADSP-2188M supports read and write operations as well as four

different data formats. The byte memory uses data bits 15:8 for data. The byte memory uses data bits

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

REV. PrA

19

April 1999

ADSP-2188M Preliminary Data Sheet

For current information contact Analog Devices at (781) 461-3881

23:16 and address bits 13:0 to create a 22-bit address. This allows up to a 4 meg x 8 (32 megabit) ROM

or RAM to be used without glue logic. All byte memory accesses are timed by the BMWAIT register

and the waitstate mode bit.

Byte Memory DMA (BDMA, Full Memory Mode)

The Byte memory DMA controller allows loading and storing of program instructions and data using

the byte memory space. The BDMA circuit is able to access the byte memory space while the processor

is operating normally and steals only one DSP cycle per 8-, 16- or 24-bit word transferred.

%'0$ &21752/

ìè ìé ìê ìë ìì ìí

ä

å

æ

ç

è

é

ê

ì

ë

í

ì

í

'0õí[ê)(êô

%7<3(

í

%03$*(

%'0$

29(5/$<

%,76

%',5

í /2$' )520 %0

ì 6725( 72 %0

%&5

í 581 '85,1* %'0$

ì +$/7 '85,1* %'0$

Figure 9 BDMA Control Register

The BDMA circuit supports four different data formats which are selected by the BTYPE register field.

The appropriate number of 8-bit accesses are done from the byte memory space to build the word size

selected. Table 6 shows the data formats supported by the BDMA circuit.

Table 6 Data Formats

BTYPE

00

Internal Memory Space

Program Memory

Data Memory

Word Size

Alignment

Full Word

MSBs

24

16

8

01

10

Data Memory

11

Data Memory

8

LSBs

Unused bits in the 8-bit data memory formats are filled with 0s. The BIAD register field is used to

specify the starting address for the on-chip memory involved with the transfer. The 14-bit BEAD

register specifies the starting address for the external byte memory space. The 8-bit BMPAGE register

specifies the starting page for the external byte memory space. The BDIR register field selects the

direction of the transfer. Finally, the 14-bit BWCOUNT register specifies the number of DSP words

to transfer and initiates the BDMA circuit transfers.

BDMA accesses can cross page boundaries during sequential addressing. A BDMA interrupt is

generated on the completion of the number of transfers specified by the BWCOUNT register.

The BWCOUNT register is updated after each transfer so it can be used to check the status of the

transfers. When it reaches zero, the transfers have finished and a BDMA interrupt is generated. The

BMPAGE and BEAD registers must not be accessed by the DSP during BDMA operations.

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

20

REV. PrA

ADSP-2188M Preliminary Data Sheet

For current information contact Analog Devices at (781) 461-3881

April 1999

The source or destination of a BDMA transfer will always be on-chip program or data memory.

When the BWCOUNT register is written with a nonzero value the BDMA circuit starts executing byte

memory accesses with wait states set by BMWAIT. These accesses continue until the count reaches zero.

When enough accesses have occurred to create a destination word, it is transferred to or from on-chip

memory. The transfer takes one DSP cycle. DSP accesses to external memory have priority over BDMA

byte memory accesses.

The BDMA Context Reset bit (BCR) controls whether the processor is held off while the BDMA

accesses are occurring. Setting the BCR bit to 0 allows the processor to continue operations. Setting the

BCR bit to 1 causes the processor to stop execution while the BDMA accesses are occurring, to clear

the context of the processor, and start execution at address 0 when the BDMA accesses have completed.

The BDMA overlay bits specify the OVLAY memory blocks to be accessed for internal memory.

The BMWAIT field, which has 4-bits on ADSP-2188M, lets you select up to 15 waitstates for BDMA

transfers.

Internal Memory DMA Port (IDMA Port; Host Memory Mode)

The IDMA Port provides an efficient means of communication between a host system and the ADSP-

2188M. The port is used to access the on-chip program memory and data memory of the DSP with

only one DSP cycle per word overhead. The IDMA port cannot be used, however, to write to the DSP’s

memory-mapped control registers. A typical IDMA transfer process is described as follows:

1. Host starts IDMA transfer

2. Host checks IACK control line to see if the DSP is busy

3. Host uses IS and IAL control lines to latch either the DMA starting address (IDMAA) or the PM/

DM OVLAY selection into the DSP’s IDMA control registers. If bit 15 = 1, the value of bits 7:0

represent the IDMA overlay: bits 14:8 must be set to 0. If bit 15 = 0, the value of bits 13:0 represent

the starting address of internal memory to be accessed and bit 14 reflects PM or DM for access.

4. Host uses IS and IRD (or IWR) to read (or write) DSP internal memory (PM or DM).

5. Host checks IACK line to see if the DSP has completed the previous IDMA operation.

6. Host ends IDMA transfer.

The IDMA port has a 16-bit multiplexed address and data bus and supports 24-bit program memory.

The IDMA port is completely asynchronous and can be written while the ADSP-2188M is operating

at full speed.

The DSP memory address is latched and then is automatically incremented after each IDMA

transaction. An external device can therefore access a block of sequentially addressed memory by

specifying only the starting address of the block. This increases throughput as the address does not have

to be sent for each memory access.

IDMA Port access occurs in two phases. The first is the IDMA Address Latch cycle. When the

acknowledge is asserted, a 14-bit address and 1-bit destination type can be driven onto the bus by an

external device. The address specifies an on-chip memory location, the destination type specifies

whether it is a DM or PM access. The falling edge of the IDMA address latch signal (IAL) or the missing

edge of the IDMA select signal (IS) latches this value into the IDMAA register.

Once the address is stored, data can then be either read from, or written to, the ADSP-2188M’s on-

chip memory. Asserting the select line (IS) and the appropriate read or write line (IRD and IWR

respectively) signals the ADSP-2188M that a particular transaction is required. In either case, there is

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

REV. PrA

21

April 1999

ADSP-2188M Preliminary Data Sheet

For current information contact Analog Devices at (781) 461-3881

a one-processor-cycle delay for synchronization. The memory access consumes one additional processor

cycle.

Once an access has occurred, the latched address is automatically incremented, and another access can

occur.

Through the IDMAA register, the DSP can also specify the starting address and data format for DMA

operation. Asserting the IDMA port select (IS) and address latch enable (IAL) directs the ADSP-2188M

to write the address onto the IAD0-14 bus into the IDMA Control Register. If bit 15 is set to 0, IDMA

latches the address. If bit 15 is set to 1, IDMA latches into the OVLAY register.This register, shown

below, is memory mapped at address DM (0x3FE0). Note that the latched address (IDMAA) cannot

be read back by the host.

Refer to the following figures for more information on IDMA and DMA memory maps.

,'0$ 29(5/$<

ìè ìé ìê ìë ìì ìí

ä

å

æ

ç

è

í

é

í

ê

í

ë

í

ì

í

'0õí[ê)(æô

í

5(6(59('

6(7 72 í

,' 3029/$<

,' '029/$<

,'0$ &21752/ õ8 81'(),1(' $7 5(6(7ô

ìè ìé ìê ìë ìì ìí

ä

å

æ

ç

è

é

ê

ë

ì

í

'0õí[ê)(íô

8

,'0$$

,'0$'

$''5(66

'HVWLQDWLRQ PHP RU\ W\SHã

í 30

ì '0

Figure 10 IDMA Control/OVLAY Registers

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

22

REV. PrA

ADSP-2188M Preliminary Data Sheet

For current information contact Analog Devices at (781) 461-3881

April 1999

' 0 $

' $ 7 $ 0 ( 0 2 5 <

2 9 / $ <

' 0 $

3 5 2 * 5 $ 0 0 ( 0 2 5 <

2 9 / $ <

$ / : $ < 6

$ & & ( 6 6 ,% / (

$ 7 $ ' ' 5 ( 6 6

$ & & ( 6 6 ,% / (

$ 7 $ ' ' 5 ( 6 6

í [ ë í í í

ð í [ ê ) ) )

í [ í í í í

ð í [ ì ) ) )

í [ ë í í í

í [ ê ) ) )

ð

í [ í í í í

í [ ì ) ) )

í [ í í í í

í [ ì ) ) )

ð

í [ ë í í í

í [ ê ) ) )

ð

$ & & ( 6 6 , % / ( : + ( 1

' 0 2 9 / $ <

í [ í í í í

í [ ì ) ) )

ð

$ & & ( 6 6 , % / ( : + ( 1

3 0 2 9 / $ <

í [ ë í í í

í [ ê ) ) )

ð

í

í [ í í í í

í [ ì ) ) )

ð

$ & & ( 6 6 , % / ( : + ( 1

' 0 2 9 / $ <

$ & & ( 6 6 , % / ( : + ( 1

3 0 2 9 / $ <

í [ ë í í í

í [ ê ) ) )

ð

é

í [ í í í í

í [ ì ) ) )

ð

$ & & ( 6 6 , % / ( : + ( 1

' 0 2 9 / $ <

$ & & ( 6 6 , % / ( : + ( 1

3 0 2 9 / $ <

è

í [ ë í í í

ð

$ & & ( 6 6 , % / ( : + ( 1

' 0 2 9 / $ <

$ & & ( 6 6 , % / ( : + ( 1

3 0 2 9 / $ <

í [ ê ) ) )

ç

í [ í í í í

ð

ç

í [ ì ) ) )

$ & & ( 6 6 , % / ( : + ( 1

' 0 2 9 / $ <

$ & & ( 6 6 , % / ( : + ( 1

æ

3 0 2 9 / $ <

æ

$ & & ( 6 6 , % / ( : + ( 1

' 0 2 9 / $ <

å

1 2 7 ( ã ,' 0 $ $ 1 ' % ' 0 $ + $ 9 (

6 ( 3 $ 5 $ 7 ( ' 0 $ & 2 1 7 5 2 / 5 ( * ,6 7 ( 5 6

Figure 11 Direct Memory Access-PM and DM Memory Maps

Bootstrap Loading (Booting)

The ADSP-2188M has two mechanisms to allow automatic loading of the internal program memory

after reset. The method for booting is controlled by the Mode A, B, and C configuration bits.

When the MODE pins specify BDMA booting, the ADSP-2188M initiates a BDMA boot sequence

when reset is released.

The BDMA interface is set up during reset to the following defaults when BDMA booting is specified:

the BDIR, BMPAGE, BIAD, and BEAD registers are set to 0, the BTYPE register is set to 0 to specify

program memory 24 bit words, and the BWCOUNT register is set to 32. This causes 32 words of on-

chip program memory to be loaded from byte memory. These 32 words are used to set up the BDMA

to load in the remaining program code. The BCR bit is also set to 1, which causes program execution

to be held off until all 32 words are loaded into on-chip program memory. Execution then begins at

address 0.

The ADSP-2100 Family development software (Revision 5.02 and later) fully supports the BDMA

booting feature and can generate byte memory space compatible boot code.

The IDLE instruction can also be used to allow the processor to hold off execution while booting

continues through the BDMA interface. For BDMA accesses while in Host Mode, the addresses to boot

memory must be constructed externally to the ADSP-2188M. The only memory address bit provided

by the processor is A0.

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

REV. PrA

23

April 1999

ADSP-2188M Preliminary Data Sheet

For current information contact Analog Devices at (781) 461-3881

IDMA Port Booting

The ADSP-2188M can also boot programs through its Internal DMA port. If Mode C = 1, Mode B =

0, and Mode A = 1, the ADSP-2188M boots from the IDMA port. IDMA feature can load as much

on-chip memory as desired. Program execution is held off until on-chip program memory location 0 is

written to.

Bus Request & Bus Grant

The ADSP-2188M can relinquish control of the data and address buses to an external device. When

the external device requires access to memory, it asserts the bus request (BR) signal. If the ADSP-

2188M is not performing an external memory access, then it responds to the active BR input in the

following processor cycle by:

Three-stating the data and address buses and the PMS, DMS, BMS, CMS, IOMS, RD, WR output

drivers,

•

Asserting the bus grant (BG) signal, and

Halting program execution.

•

If Go Mode is enabled, the ADSP-2188M will not halt program execution until it encounters an

instruction that requires an external memory access.

If the ADSP-2188M is performing an external memory access when the external device asserts the BR

signal, then it will not three-state the memory interfaces or assert the BG signal until the processor cycle

after the access completes. The instruction does not need to be completed when the bus is granted. If

a single instruction requires two external memory accesses, the bus will be granted between the two

accesses.

When the BR signal is released, the processor releases the BG signal, re-enables the output drivers and

continues program execution from the point where it stopped.

The bus request feature operates at all times, including when the processor is booting and when RESET

is active.

The BGH pin is asserted when the ADSP-2188M requires the external bus for a memory or BDMA

access, but is stopped. The other device can release the bus by deasserting bus request. Once the bus is

released, the ADSP-2188M deasserts BG and BGH and executes the external memory access.

Flag I/O Pins

The ADSP-2188M has eight general purpose programmable input/output flag pins. They are

controlled by two memory mapped registers. The PFTYPE register determines the direction, 1 = output

and 0 = input. The PFDATA register is used to read and write the values on the pins. Data being read

from a pin configured as an input is synchronized to the ADSP-2188M’s clock. Bits that are

programmed as outputs will read the value being output. The PF pins default to input during reset.

In addition to the programmable flags, the ADSP-2188M has five fixed-mode flags, FLAG_IN,

FLAG_OUT, FL0, FL1, and FL2. FL0-FL2 are dedicated output flags. FLAG_IN and FLAG_OUT

are available as an alternate configuration of SPORT1.

Note: Pins PF0, PF1, PF2 and PF3 are also used for device configuration during reset.

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

24

REV. PrA

ADSP-2188M Preliminary Data Sheet

For current information contact Analog Devices at (781) 461-3881

April 1999

Instruction Set Description

The ADSP-2188M assembly language instruction set has an algebraic syntax that was designed for ease

of coding and readability. The assembly language, which takes full advantage of the processor’s unique

architecture, offers the following benefits:

The algebraic syntax eliminates the need to remember cryptic assembler mnemonics. For example,

a typical arithmetic add instruction, such as AR = AX0 + AY0, resembles a simple equation.

•

Every instruction assembles into a single, 24-bit word that can execute in a single instruction cycle.

•

The syntax is a superset ADSP-2100 Family assembly language and is completely source and object

code compatible with other family members. Programs may need to be relocated to utilize on-chip

memory and conform to the ADSP-2188M’s interrupt vector and reset vector map.

Sixteen condition codes are available. For conditional jump, call, return, or arithmetic instructions,

the condition can be checked and the operation executed in the same instruction cycle.

•

Multifunction instructions allow parallel execution of an arithmetic instruction with up to two

fetches or one write to processor memory space during a single instruction cycle.

DESIGNING AN EZ-ICE-COMPATIBLE SYSTEM

The ADSP-2188M has on-chip emulation support and an ICE-Port, a special set of pins that interface

to the EZ-ICE. These features allow in-circuit emulation without replacing the target system processor

by using only a 14-pin connection from the target system to the EZ-ICE. Target systems must have a

14-pin connector to accept the EZ-ICE’s in-circuit probe, a 14-pin plug.

Issuing the chip reset command during emulation causes the DSP to perform a full chip reset, including

a reset of its memory mode. Therefore, it is vital that the mode pins are set correctly PRIOR to issuing

a chip reset command from the emulator user interface. If you are using a passive method of

maintaining mode information (as discussed in Setting Memory Modes) then it does not matter that

the mode information is latched by an emulator reset. However, if you are using the RESET pin as a

method of setting the value of the mode pins, then you have to take into consideration the effects of an

emulator reset.

One method of ensuring that the values located on the mode pins are those desired is to construct a

circuit like the one shown in Figure 12. This circuit forces the value located on the Mode A pin to logic

high; regardless if it latched via the RESET or ERESET pin .

(5( 6( 7

5(6 (7

$' 6 3ðëìåå0

ì NΩ

0 2' ( $ î3) 2

352* 5$ 0 0 $% / ( ,î2

Figure 12 Mode A Pin/EZ-ICE Circuit

See the ADSP-2100 Family EZ-Tools data sheet for complete information on ICE products.

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

REV. PrA

25

April 1999

ADSP-2188M Preliminary Data Sheet

For current information contact Analog Devices at (781) 461-3881

The ICE-Port interface consists of the following ADSP-2188M pins: EBR, EINT, EE, EBG, ECLK,

ERESET, ELIN, EMS, and ELOUT

These ADSP-2188M pins must be connected only to the EZ-ICE connector in the target system. These

pins have no function except during emulation, and do not require pull-up or pull-down resistors. The

traces for these signals between the ADSP-2188M and the connector must be kept as short as possible,

no longer than 3 inches.

The following pins are also used by the EZ-ICE: BR, BG, RESET, and GND

The EZ-ICE uses the EE (emulator enable) signal to take control of the ADSP-2188M in the target

system. This causes the processor to use its ERESET, EBR, and EBG pins instead of the RESET, BR,

and BG pins. The BG output is three-stated. These signals do not need to be jumper-isolated in your

system.

The EZ-ICE connects to your target system via a ribbon cable and a 14-pin female plug. The female

plug is plugged onto the 14-pin connector (a pin strip header) on the target board.

Target Board Connector for EZ-ICE Probe

The EZ-ICE connector (a standard pin strip header) is shown in Figure 13. You must add this

connector to your target board design if you intend to use the EZ-ICE. Be sure to allow enough room

in your system to fit the EZ-ICE probe onto the 14-pin connector.

ì

ê

è

æ

ë

%*

*1'

é

(%*

%5

ç

å

(%5

(,17

.(< õ12 3,1ô

∞

(/,1

ä

ìí

ìë

ìé

(/287

(&/.

ìì

ìê

(06

((

5(6(7

(5(6(7

723 9,(:

Figure 13 Target Board Connector for EZ-ICE

The 14-pin, 2-row pin strip header is keyed at the Pin 7 location—you must remove Pin 7 from the

header. The pins must be 0.025 inch square and at least 0.20 inch in length. Pin spacing should be 0.1

x 0.1 inches. The pin strip header must have at least 0.15 inch clearance on all sides to accept the EZ-

ICE probe plug.

Pin strip headers are available from vendors such as 3M, McKenzie, and Samtec.

Target Memory Interface

For your target system to be compatible with the EZ-ICE emulator, it must comply with the memory

interface guidelines listed below.

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

26

REV. PrA

ADSP-2188M Preliminary Data Sheet

For current information contact Analog Devices at (781) 461-3881

April 1999

PM, DM, BM, IOM, & CM

Design your Program Memory (PM), Data Memory (DM), Byte Memory (BM), I/O Memory (IOM),

and Composite Memory (CM) external interfaces to comply with worst case device timing

requirements and switching characteristics as specified in this data sheet. The performance of the EZ-

ICE may approach published worst case specification for some memory access timing requirements and

switching characteristics.

Note: If your target does not meet the worst case chip specification for memory access parameters, you

may not be able to emulate your circuitry at the desired CLKIN frequency. Depending on the severity

of the specification violation, you may have trouble manufacturing your system as DSP components

statistically vary in switching characteristic and timing requirements within published limits.

Restriction: All memory strobe signals on the ADSP-2188M (RD, WR, PMS, DMS, BMS, CMS, and

IOMS) used in your target system must have 10 kΩ pull-up resistors connected when the EZ-ICE is

being used. The pull-up resistors are necessary because there are no internal pull-ups to guarantee their

state during prolonged three-state conditions resulting from typical EZ-ICE debugging sessions. These

resistors may be removed at your option when the EZ-ICE is not being used.

Target System Interface Signals

When the EZ-ICE board is installed, the performance on some system signals change. Design your

system to be compatible with the following system interface signal changes introduced by the EZ-ICE

board:

EZ-ICE emulation introduces an 8 ns propagation delay between your target circuitry and the DSP

on the RESET signal.

•

EZ-ICE emulation introduces an 8 ns propagation delay between your target circuitry and the DSP

on the BR signal.

•

EZ-ICE emulation ignores RESET and BR when single- stepping.

•

EZ-ICE emulation ignores RESET and BR when in Emulator Space (DSP halted).

EZ-ICE emulation ignores the state of target BR in certain modes. As a result, the target system

may take control of the DSP’s external memory bus only if bus grant (BG) is asserted by the EZ-

ICE board’s DSP.

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

REV. PrA

27

April 1999

ADSP-2188M Preliminary Data Sheet

For current information contact Analog Devices at (781) 461-3881

ADSP-2188M–ELECTRICAL SPECIFICATIONS

RECOMMENDED OPERATING CONDITIONS

Parameter

K Grade

B Grade

Unit

Min

2.37

Max

2.63

3.6

Min

Max

V

TBD

V

DDINT

DDEXT

1

V = -0.3

V

= 3.6

IL

IH

V

T

INPUT

0

+70

-40

+85

°C

AMB

1. The ADSP-2188M is 3.3V tolerant (always accepts up to 3.6 Volt max V_IH), but voltage compliance (on outputs, V_OH) depends on

the input V_DDEXT; because V_OH(max)≈V_DDEXT(max). This applies to Bidirectional pins (D0–D23, RFS0, RFS1, SCLK0, SCLK1,

TFS0, TFS1, A1–A13, PF0–PF7) and Input only pins (CLKIN, RESET, BR, DR0, DR1, PWD).

ELECTRICAL CHARACTERISTICS

K/B Grades

Parameter

Test Conditions

@ V_'',17= max

Unit

V

Min

1.5

Typ

Max

0.7

1, 2

V_,+, Hi-Level Input Voltage

V_,+, Hi-Level CLKIN Voltage

@ V_'',17= max

@ V_'',17= min

2.0

V

1, 3

V_,/, Lo-Level Input Voltage

1, 4, 5

@ V_''(;7= min,

I₂₊= –0.5 mA

2.0

V

V₂₊, Hi-Level Output Voltage

@ V_''(;7= 3.0V,

I₂₊= –0.5 mA

2.4

@ V_''(;7= min,

V_''(;7-0.3

6

I₂₊= –100 µA

1, 4, 5

@ V_''(;7= min,

I_2/= 2 mA

0.4

10

V

V_2/, Lo-Level Output Voltage

3

@ V_'',17= max,

V_,1= 3.6V

µA

I_,+, Hi-Level Input Current

3

@ V_'',17= max,

V_,1= 0 V

I_,/, Lo-Level Input Current

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

28

REV. PrA

ADSP-2188M Preliminary Data Sheet

For current information contact Analog Devices at (781) 461-3881

April 1999

ELECTRICAL CHARACTERISTICS (Continued)

K/B Grades

Parameter

Test Conditions

Unit

Min

Typ

Max

7

@ V_''(;7= max,

10

µA

I₂₌₊, Three-State Leakage Current

8

V_,1= 3.6V

7

@ V

V

= max,

10

DDEXT

I_2=/, Three-State Leakage Current

8

= 0 V

IN

9

@ V_'',17= 2.5,

t_&.= 15 ns

TBD

mA

I_'', Supply Current (Idle)

9

@ V_'',17= 2.5,

t_&.= 13.3 ns

I_'', Supply Current (Idle)

10

@ V_'',17= 2.5,

I_'', Supply Current (Dynamic)

11

t_&.= 15 ns ,

T_$0%=+25°C

10

@ V_'',17= 2.5,

TBD

mA

I_'', Supply Current (Dynamic)

11

t

_&.= 13.3 ns ,

T_$0%=+25°C

12

I_'', Supply Current (Powerdown)

Lowest power mode

µA

3, 6, 13

@ V_,1= 2.5 V,

f_,1= 1.0 MHz,

T_$0%= +25°C

8

pF

C_,, Input Pin Capacitance

6,7,12,14

@ V_,1= 2.5 V,

f_,1= 1.0 MHz,

T_$0%=+25°C

pF

C₂, Output Pin Capacitance

1. Bidirectional pins: D0–D23, RFS0, RFS1, SCLK0, SCLK1, TFS0, TFS1, A1–A13, PF0–PF7.

2. Input only pins: RESET, BR, DR0, DR1, PWD.

3. Input only pins: CLKIN, RESET, BR, DR0, DR1, PWD.

4. Output pins: BG, PMS, DMS, BMS, IOMS, CMS, RD, WR, PWDACK, A0, DT0, DT1, CLKOUT, FL2-0, BGH.

5. Although specified for TTL outputs, all ADSP-2188M outputs are CMOS-compatible and will drive to V_DDEXTand GND, assuming

no DC loads.

6. Guaranteed but not tested.

7. Three-statable pins: A0–A13, D0-D23, PMS, DMS, BMS, IOMS, CMS, RD, WR, DT0, DT1, SCLK0, SCLK1, TFS0, TFS1, RFS0,

RSF1, PF0–PF7.

8. 0 V on BR.

9. Idle refers to ADSP-2188M state of operation during execution of IDLE instruction. Deasserted pins are driven to either V_DDor GND.

10.I_DDmeasurement taken with all instructions executing from internal memory. 50% of the instructions are multifunction (types 1, 4,

5, 12, 13, 14), 30% are type 2 and type 6, and 20% are idle instructions.

11.V_IN= 0 V and 3 V. For typical figures for supply currents, refer to “Power Dissipation” section.

12.See Chapter 9 of the ADSP-2100 Family User’s Manual for details

13.Applies to LQFP package type.

14.Output pin capacitance is the capacitive load for any three-stated output pin.

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

REV. PrA

29

April 1999

ADSP-2188M Preliminary Data Sheet

For current information contact Analog Devices at (781) 461-3881

1

ABSOLUTE MAXIMUM RATINGS

Value

Min

Parameter

Max

+3.0 V

+4.6 V

Internal Supply Voltage (V

)

–0.3 V

DDINT

External Supply Voltage (V

)

DDEXT

2

Input Voltage

–0.5 V

+4.6 V

+ 0.5 V

3

Output Voltage Swing

V

DDEXT

Operating Temperature Range (Ambient)

Storage Temperature Range

–40 °C

–65 °C

+85 °C

+150 °C

+280 °C

Lead Temperature (5 sec) LQFP

1. Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this

specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

2. Applies to Bidirectional pins (D0–D23, RFS0, RFS1, SCLK0, SCLK1, TFS0, TFS1, A1–A13, PF0–PF7) and Input only pins (CLKIN,

RESET, BR, DR0, DR1, PWD).

3. Applies to Output pins (BG, PMS, DMS, BMS, IOMS, CMS, RD, WR, PWDACK, A0, DT0, DT1, CLKOUT, FL2-0, BGH).

ESD SENSITIVITY

CAUTION: ESD (electrostatic discharge) sensitive device. Elec-

trostatic charges as high as 4000V readily accumulate on the human

body and test equipment and can discharge without detection.

Although the ADSP-2188M features proprietary ESD protection

circuitry, permanent damage may occur on devices subjected to

high energy electrostatic discharges. Therefore, proper ESD precau-

tions are recommended to avoid performance degradation or loss of

functionality.

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

30

REV. PrA

ADSP-2188M Preliminary Data Sheet

For current information contact Analog Devices at (781) 461-3881

April 1999

ADSP-2188M TIMING PARAMETERS

GENERAL NOTES

Use the exact timing information given. Do not attempt to derive parameters from the addition or

subtraction of others. While addition or subtraction would yield meaningful results for an individual

device, the values given in this data sheet reflect statistical variations and worst cases. Consequently,

you cannot meaningfully add up parameters to derive longer times.

TIMING NOTES

Switching characteristics specify how the processor changes its signals. You have no control over this

timing—circuitry external to the processor must be designed for compatibility with these signal

characteristics. Switching characteristics tell you what the processor will do in a given circumstance.

You can also use switching characteristics to ensure that any timing requirement of a device connected

to the processor (such as memory) is satisfied.

Timing requirements apply to signals that are controlled by circuitry external to the processor, such as

the data input for a read operation. Timing requirements guarantee that the processor operates correctly

with other devices.

MEMORY TIMING SPECIFICATIONS

The table below shows common memory device specifications and the corresponding ADSP-2188M

timing parameters, for your convenience.

1

Memory Device Specification

Address setup to Write Start

Parameter

t_$6:

Timing Parameter Definition

A0-A13, xMS Setup before WR Low

Address Setup to Write End

Address Hold Time

Data Setup Time

t_$:

t_:5$

t_':

t_'+

A0-A13, xMS Setup before WR Deasserted

A0-A13, xMS Hold before WR Low

Data Setup before WR High

Data Hold after WR High

Data Hold Time

OE to Data Valid

t_5''

t_$$

RD Low to Data Valid

Address Access Time

A0-A13, xMS to Data Valid

1. NOTE: xMS = PMS, DMS, BMS, CMS, or IOMS

FREQUENCY DEPENDENCY FOR TIMING SPECIFICATIONS

t

is defined as 0.5t . The ADSP-2188M uses an input clock with a frequency equal to half the

CKI

CK

instruction rate: a 37.50 MHz input clock (which is equivalent to 26.7 ns) yields a 13.3 ns processor

cycle (equivalent to 75 MHz). t values within the range of 0.5t

all relevant timing parameters to obtain the specification value.

period should be substituted for

CK

CKI

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

REV. PrA

31

April 1999

ADSP-2188M Preliminary Data Sheet

For current information contact Analog Devices at (781) 461-3881

Example: t_&.+= 0.5t_&.– 7 ns = 0.5 (15 ns) – 7 ns = 0.5 ns

1

ENVIRONMENTAL CONDITIONS

Rating Description

Symbol

Value

Thermal Resistance (Case-to-Ambient)

Thermal Resistance (Junction-to-Ambient)

θ

48 °C/W

50 °C/W

2 °C/W

CA

JA

Thermal Resistance (Junction-to-Case)

JC

1. Where the Ambient Temperature Rating (T_AMB) is:

T_AMB= T_CASE– (PD x θ_CA

)

T

_CASE= Case Temperature in °C

PD = Power Dissipation in W

POWER DISSIPATION

To determine total power dissipation in a specific application, the following equation should be applied

for each output:

C x V 2 x f

DD

C = load capacitance, f = output switching frequency.

Example:

In an application where external data memory is used and no other outputs are active, power dissipation

is calculated as follows:

Assumptions:

External data memory is accessed every cycle with 50% of the address pins switching.

External data memory writes occur every other cycle with 50% of the data pins switching.

Each address and data pin has a 10 pF total load at the pin.

•

The application operates at V

= 3.3 V and t = 15 ns.

DDEXT

CK

2

Total Power Dissipation = PINT + (C x V

x f)

DDEXT

PINT = internal power dissipation from Power vs. Frequency graph (Figure 15).

2

(C x V

x f) is calculated for each output:

DDEXT

2

Parameters

Address, DMS

Data Output, WR

RD

# of Pins

xC

x V_DDEXT

3.3²V

x f

PD

8

9

1

10 pF

33.3 MHz

16.67 MHz

33.3 MHz

29.0 mW

16.3 mW

1.8 mW

3.6 mW

50.7 mW

3.3²V

CLKOUT

3.3²V

Total power dissipation for this example is PINT + 50.7 mW.

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

32

REV. PrA

ADSP-2188M Preliminary Data Sheet

For current information contact Analog Devices at (781) 461-3881

April 1999

Output Drive Currents

Figure 14 shows typical I-V characteristics for the output drivers on the ADSP-2188M. The curves

represent the current drive capability of the output drivers as a function of output voltage.

åí

çí

éí

ëí

7%'

í

ðëí

ðéí

ðçí

ðåí

í

ïè

ì

ìïè

ë

ëïè

ê

êïè

é

6285&( 92/7$*(

ð

9

Figure 14 Typical Output Driver Characteristics

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

REV. PrA

33

April 1999

ADSP-2188M Preliminary Data Sheet

For current information contact Analog Devices at (781) 461-3881

ìñ ëñ ê

32: (5ñ ,'/(

ìñ êñ é

ëìåå0 32: (5ñ ,17(51$/

êë

ììè

ììí

êí

ìíè

ìíí

äè

äí

åè

åí

æè

æí

çè

çí

èè

ëå

ëç

ëé

ëë

ëí

ìå

ìç

ìé

7%'

ìë

ìí

èí

èè

çí

ìîI

çè

æí

æè

ê

åí

èí

èè

çí

çè

æí

æè

åí

ð 0+]

&.

ìîW

ð 0+]

&.

32: (5ñ ,'/( Q 02'(6

9$/,' )25 $// 7(03(5$785( *5$'(6ï

ì

êë

32:(5 5()/(&76 '(9,&( 23(5$7,1* : ,7+ 12

287387 /2$'6ï

ëí

ëå

ë

,'/( 5()(56 72 $'63ðëìåå0 67$7( 2)

23(5$7,21 '85,1* (;(&87,21 2) ,'/(

,'/(

,16758&7,21ï '($66(57(' 3,16 $5( '5,9(1 72

ëé

ëë

ëí

(,7+(5 9

ê

25 *1'ï

''

7<3,&$/ 32: (5 ',66,3$7,21 $7 ëïè9 9

'',17

7%'

ο

$1' ëè & (;&(37 : +(5( 63(&,),('ï

é

,

0($685(0(17 7$.(1 : ,7+ $//

''

ìå

ìç

ìé

ìë

ìí

,16758&7,216 (;(&87,1* )520 ,17(51$/

0(025<ï èíø 2) 7+( ,16758&7,216 $5(

08/7,)81&7,21 õ7<3(6 ìñéñèñìëñìêñìéôñ êíø $5(

7<3( ë $1' 7<3( çñ $1' ëíø $5( ,'/(

,16758&7,216ï

èí

èè

çí

çè

ð 0+]

æí

æè

åí

ìîI

&.

Figure 15 Power vs. Frequency

Capacitive Loading

Figure 16 and Figure 17 show the capacitive loading characteristics of the ADSP-2188M.

êí

T = +85°C

V_DD= 0V to 2.0V

ëè

ëí

7%'

ìè

ìí

è

í

èí

í

ìíí

ìèí

ð S)

ëíí

ëèí

êíí

&

/

Figure 16 Typical Output Rise Time vs. Load Capacitance, CL

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

34

REV. PrA

ADSP-2188M Preliminary Data Sheet

For current information contact Analog Devices at (781) 461-3881

April 1999

(at Maximum Ambient Operating Temperature)

ìå

ìç

ìé

ìë

ìí

å

ç

7%'

é

ë

120,1$/

Íë

Íé

Íç

í

èí

ìíí

ìèí

Í S)

ëíí

ëèí

&

/

Figure 17 Typical Output Valid Delay or Hold vs. Load Capacitance, CL

(at Maximum Ambient Operating Temperature)

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

REV. PrA

35

April 1999

ADSP-2188M Preliminary Data Sheet

For current information contact Analog Devices at (781) 461-3881

TEST CONDITIONS

Output Disable Time

Output pins are considered to be disabled when they have stopped driving and started a transition from

the measured output high or low voltage to a high impedance state. The output disable time (t ) is

DIS

the difference of t

and t

, as shown in the Output Enable/Disable diagram. The time

MEASURED

DECAY

is the interval from when a reference signal reaches a high or low voltage level to when the output

voltages have changed by 0.5 V from the measured output high or low voltage.

The decay time, t

, is dependent on the capacitive load, CL, and the current load, iL, on the

DECAY

output pin. It can be approximated by the following equation:

C • 0.5V

L

t

ðððððððððððððððððððððððð

DECAY =

i

L

from which

= t

t

- t

DECAY

DIS

MEASURED

is calculated. If multiple pins (such as the data bus) are disabled, the measurement value is that of the

last pin to stop driving.

INPUT

1.5V

2.0V

1.5V

0.8V

OUT PUT

Figure 18 Voltage Reference Levels for AC Measurements

(Except Output Enable/Disable)

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

36

REV. PrA

ADSP-2188M Preliminary Data Sheet

For current information contact Analog Devices at (781) 461-3881

April 1999

Output Enable Time

Output pins are considered to be enabled when that have made a transition from a high-impedance

state to when they start driving. The output enable time (t ) is the interval from when a reference

ENA

signal reaches a high or low voltage level to when the output has reached a specified high or low trip

point, as shown in the Output Enable/Disable diagram. If multiple pins (such as the data bus) are

enabled, the measurement value is that of the first pin to start driving

REFERENC E

SIG NAL

t_0($685('

t_' ,6

t_(1$

V

2+

(M EASURED)

VOH (M EASURED) Ð 0.5V

2.0V

1.0V

OUTPUT

VOL (M EA SURED) +0.5V

t_'(& $<

V

2/

(M EASURED)

OUTPUT STARTS

DRIVING

OUTPUT S TOPS

DRIVING

HIGH-IM PEDANCE STAT E. T EST CONDITIONS CAUSE

THIS VOLTA GE LEVEL T O BE APPRO XIM ATELY 1.5V.

Figure 19 Output Enable/Disable

I

2/

TO

OUT PUT

+1.5V

50pF

I

2+

Figure 20 Equivalent Device Loading for AC Measurements

(Including All Fixtures)

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

REV. PrA

37

April 1999

ADSP-2188M Preliminary Data Sheet

For current information contact Analog Devices at (781) 461-3881

TIMING PARAMETERS ADSP-2188M

Clock Signals and Reset

Parameter

Min

Max Unit

Clock Signals and Reset

Timing Requirements:

t_CKI

CLKIN Period

26.6

13

100

ns

t_CKIL

CLKIN Width Low

CLKIN Width High

t_CKIH

Switching Characteristics:

t_CKL

CLKOUT Width Low

0.5t_CK- 2

0

ns

t_CKH

CLKOUT Width High

CLKIN High to CLKOUT High

t_CKOH

13

Control Signals

Timing Requirements:

1

t_RSP

RESET Width Low

5t_CK

2

5

ns

t_MS

Mode Setup Before RESET High

Mode Hold After RESET High

t_MH

1Applies after power-up sequence is complete. Internal phase lock loop requires no more than 2000 CLKIN cycles assuming stable

CLKIN (not including crystal oscillator start-up time)

t_CKI

t_CKIH

CLK IN

t_CKIL

t_{CK OH}

t_CKH

CLKOUT

t_CKL

3) õêãí ôó

W₀₊

W₀₆

5(6 (7

ó3)ê LV 0 2'( 'ñ 3) ë LV 0 RGH &ñ 3)ì LV 0 RGH %ñ 3)í LV 0 RGH

$

Figure 21 Clock Signals

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

38

REV. PrA

ADSP-2188M Preliminary Data Sheet

For current information contact Analog Devices at (781) 461-3881

April 1999

TIMING PARAMETERS ADSP-2188M

Interrupts and Flags

3DUDPHWHU

0LQ

0D[

8QLW

Interrupts and Flag

Timing Requirements:

t_IFS

IRQx, FI, or PFx Setup before CLKOUT Low^{1, 2, 3, 4}

0.25t_CK+ 10

0.25t_CK

ns

t_IFH

IRQx, FI, or PFx Hold after CLKOUT High^{1, 2, 3, 4}

Switching Characteristics:

t_FOH

Flag Output Hold after CLKOUT Low⁵

t_FOD

Flag Output Delay from CLKOUT Low⁵

0.5t_CK- 5

ns

0.5t_CK+ 4 ns

NOTES

¹If IRQx and FI inputs meet t_IFSand t_IFHsetup/hold requirements, they will be recognized during the current clock cycle; otherwise the

signals will be recognized on the following cycle. (Refer to Interrupt Controller Operation” in the Program Control chapter of the ADSP-

2100 Family User’s Manual for further information on interrupt servicing.)

²Edge-sensitive interrupts require pulse widths greater than 10ns; level-sensitive interrupts must be held low until serviced.

³IRQx = IRQ0, IRQ1, IRQ2, IRQL0, IRQL1, IRQLE.

⁴PFx = PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7.

5Flag Outputs = PFx, FL0, FL1, FL2, Flag_out.

W_)2'

&/.287

W₎₂₊

)/$*

2873876

W_,)+

,5 4 [

),

3)[

W_,)6

Figure 22 Interrupts and Flags

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

REV. PrA

39

April 1999

ADSP-2188M Preliminary Data Sheet

For current information contact Analog Devices at (781) 461-3881

TIMING PARAMETERS ADSP-2188M

Bus Request-Bus Grant

3DUDPHWHU

0LQ

0D[

8QLW

Bus Request/Grant

Timing Requirements:

t_BH

t_BS

BR Hold after CLKOUT High¹

BR Setup before CLKOUT Low¹

0.25t_CK+ 2

0.25t_CK+ 10

ns

Switching Characteristics:

t_SD

CLKOUT High to xMS, RD, WR Disable

0.25t_CK+ 8 ns

t_SDB

xMS, RD, WR Disable to BG Low

BG High to xMS, RD, WR Enable

xMS, RD, WR Enable to CLKOUT High

xMS, RD, WR Disable to BGH Low²

BGH High to xMS, RD, WR Enable²

0

ns

t_SE

0

t_SEC

t_SDBH

t_SEH

0.25t_CK– 3

0

NOTES

xMS = PMS, DMS, CMS, IOMS, BMS

¹BR is an asynchronous signal. If BR meets the setup/hold requirements, it will be recognized during the current clock cycle; otherwise

the signal will be recognized on the following cycle. Refer to the ADSP-2100 Family User’s Manual for BR/BG cycle relationships.

²BGH is asserted when the bus is granted and the processor or BDMA requires control of the bus to continue.

t_BH

CLKOUT

% 5

t_{B S}

CLKOUT

3 0 6 ñ ' 0 6

% 0 6 ñ 5 '

: 5

t_SD

t_{SE C}

%*

t_SDB

t_SE

%* +

t_{SD BH}

t_{S EH}

Figure 23 Bus Request–Bus Grant

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

40

REV. PrA

ADSP-2188M Preliminary Data Sheet

For current information contact Analog Devices at (781) 461-3881

April 1999

TIMING PARAMETERS ADSP-2188M

Memory Read

3DUDPHWHU

0LQ

0D[

8QLW

Memory Read

Timing Requirements:

t_RDD

RD Low to Data Valid

0.5t_CK– 5 + w ns

0.75t_CK- 6 + w ns

ns

t_AA

A0-A13, xMS to Data Valid

Data Hold from RD High

t_RDH

0

Switching Characteristics:

t_RP

RD Pulse Width

0.5t_CK- 3 + w

0.25t_CK- 2

0.25t_CK- 3

0.25t_CK– 3

0.5t_CK- 3

ns

t_CRD

t_ASR

t_RDA

t_RWR

CLKOUT High to RD Low

0.25t_CK+ 4

ns

A0-A13, xMS Setup before RD Low

A0-A13, xMS Hold after RD Deasserted

RD High to RD or WR Low

w = wait states x t_CK

xMS = PMS, DMS, CMS, IOMS, BMS

&/.287

$í ð $ìê

'06ñ 306ñ

%06ñ ,206ñ &06

t_RDA

5'

t_ASR

t_CRD

t_RP

t_{RW R}

'

t_RDD

t_RDH

t_AA

: 5

Figure 24 Memory Read

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

REV. PrA

41

April 1999

ADSP-2188M Preliminary Data Sheet

For current information contact Analog Devices at (781) 461-3881

TIMING PARAMETERS ADSP-2188M

Memory Write

3DUDPHWHU

0LQ

0D[

8QLW

Memory Write

Switching Characteristics:

t_DW

Data Setup before WR High

Data Hold after WR High

0.5t_CK– 4+ w

0.25t_CK– 1

0.5t_CK– 3 + w

0

0.25t_CK– 3

0.25t_CK– 2

0.75t_CK– 5 + w

0.25t_CK– 1

0.5t_CK– 3

ns

t_DH

t_WP

WR Pulse Width

WR Low to Data Enabled

t_WDE

t_ASW

t_DDR

t_CWR

t_AW

A0-A13, xMS Setup before WR Low

Data Disable before WR or RD Low

CLKOUT High to WR Low

A0-A13, xMS, Setup before WR Deasserted

A0-A13, xMS Hold after WR Deasserted

WR High to RD or WR Low

0.25 t_CK+ 4 ns

ns

t_WRA

t_WWR

w = wait states x t_CK

xMS = PMS, DMS, CMS, IOMS, BMS

CLKOUT

A0-A13

'0 6ñ 30 6ñ

%0 6ñ &0 6ñ

,2 0 6

t_{W RA}

: 5

t_{W W R}

t_{A SW}

t_{W P}

t_AW

t_DH

t_{D DR}

t_{CW R}

D

t_DW

t_{W DE}

5'

Figure 25 Memory Write

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

42

REV. PrA

ADSP-2188M Preliminary Data Sheet

For current information contact Analog Devices at (781) 461-3881

April 1999

TIMING PARAMETERS ADSP-2188MSerial Ports

3DUDPHWHU

0LQ

0D[

8QLW

Serial Ports

Timing Requirements:

t_SCK

t_SCS

t_SCH

t_SCP

SCLK Period

26.67

ns

DR/TFS/RFS Setup before SCLK Low

DR/TFS/RFS Hold after SCLK Low

SCLKIN Width

4

7

12

Switching Characteristics:

ns

t_CC

CLKOUT High to SCLKOUT

0.25t_CK

0

0.25t_CK+ 6

t_SCDE

t_SCDV

t_RH

SCLK High to DT Enable

SCLK High to DT Valid

12

TFS/RFSOUT Hold after SCLK High

TFS/RFSOUT Delay from SCLK High

DT Hold after SCLK High

TFS (Alt) to DT Enable

0

t_RD

t_SCDH

t_TDE

t_TDV

t_SCDD

t_RDV

0

TFS (Alt) to DT Valid

12

SCLK High to DT Disable

RFS (Multichannel, Frame Delay Zero) to DT

Valid

12

CLKOUT

t_CC

t_SCK

SCLK

t_{SC P}

t_{SC S}

t_{S CH}

'5

7)6

5)6

,1

t_RD

t_RH

5)6

7)6

287

t_{SC DD}

t_{SCD V}

t_{SC DH}

t_{SCD E}

DT

t_{T DE}

t_TDV

TFS

287

ALT ER NATE

FRA M E M OD E

t_{R DV}

RF S

OUT

M U LT ICH AN N EL

M O D E,

FR A M E DELA Y

(M FD

0

t_TDE

=

0)

t_TDV

TFS

IN

ALT ER NATE

FRA M E M OD E

t_{R DV}

RF S

IN

M U LT ICH AN N EL

M O D E ,

FR A M E DEL A Y

(M FD

0

=

0)

Figure 26 Serial Ports

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

REV. PrA

43

April 1999

ADSP-2188M Preliminary Data Sheet

For current information contact Analog Devices at (781) 461-3881

TIMING PARAMETERS ADSP-2188M

IDMA Address Latch

3DUDPHWHU

0LQ

0D[

8QLW

IDMA Address Latch

Timing Requirements:

t_IALP

t_IASU

t_IAH

Duration of Address Latch^{1, 3}

10

ns

IAD15–0 Address Setup before Address Latch End³

IAD15–0 Address Hold after Address Latch End³

IACK Low before Start of Address Latch^{2, 3}

Start of Write or Read after Address Latch End^{2, 3}

Address Latch Start after Address Latch End^{1, 3}

5

2

t_IKA

0

t_IALS

3

t_IALD

TBD

NOTES

¹Start of Address Latch = IS Low and IAL High.

²Start of Write or Read = IS Low and IWR Low or IRD Low.

³End of Address Latch = IS High or IAL Low.

,$&.

W_,.$

W_,$/'

,$/

W_,$/3

,6

,$' ìèðí

W_,$68

W_,$+

W_,$/6

,5'

2

,:5

5

Figure 27 IDMA Address Latch

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

44

REV. PrA

ADSP-2188M Preliminary Data Sheet

For current information contact Analog Devices at (781) 461-3881

April 1999

TIMING PARAMETERS ADSP-2188M

IDMA Write, Short Write Cycle

3DUDPHWHU

0LQ

0D[

8QLW

IDMA Write, Short Write Cycle

Timing Requirements:

t_IKW

t_IWP

t_IDSU

t_IDH

IACK Low before Start of Write¹

0

ns

Duration of Write^{1, 2}

10

3

IAD15–0 Data Setup before End of Write^{2, 3, 4}

IAD15–0 Data Hold after End of Write^{2, 3, 4}

2

Switching Characteristics:

t_IKHW

Start of Write to IACK High

10

ns

NOTES

¹Start of Write = IS Low and IWR Low.

²End of Write = IS High or IWR High.

³If Write Pulse ends before IACK Low, use specifications t_IDSU, t_IDH.

⁴If Write Pulse ends after IACK Low, use specifications t_IKSU, t_IKH.

t_,.:

,$&.

t_,.+ :

,6

t_,: 3

,: 5

t_,' +

t_,'68

IAD 15-0

DATA

Figure 28 IDMA Write, Short Write Cycle

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

REV. PrA

45

April 1999

ADSP-2188M Preliminary Data Sheet

For current information contact Analog Devices at (781) 461-3881

TIMING PARAMETERS ADSP-2188M

IDMA Write, Long Write Cycle

3DUDPHWHU

0LQ

0D[

8QLW

IDMA Write, Long Write Cycle

Timing Requirements:

t_IKW

t_IKSU

t_IKH

IACK Low before Start of Write¹

0

ns

IAD15–0 Data Setup before End of Write^{2, 3, 4}

IAD15–0 Data Hold after End of Write^{2, 3, 4}

.5t_&.+ 5

0

Switching Characteristics:

t_IKLW

Start of Write to IACK Low⁴

t_IKHWStart of Write to IACK High

1.5t_CK

ns

10

NOTES

¹Start of Write = IS Low and IWR Low.

²If Write Pulse ends before IACK Low, use specifications t_IDSU, t_IDH.

³If Write Pulse ends after IACK Low, use specifications t_IKSU, t_IKH.

⁴This is the earliest time for IACK Low from Start of Write. For IDMA Write cycle relationships, please refer to the ADSP-2100 Family

User’s Manual.

,$&.

W_,.$

W_,$/'

,$/

W_,$/3

,6

,$' ìèðí

W_,$68

W_,$+

W_,$/6

,5'

2

,:5

5

Figure 29 IDMA Write, Long Write Cycle

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

46

REV. PrA

ADSP-2188M Preliminary Data Sheet

For current information contact Analog Devices at (781) 461-3881

April 1999

TIMING PARAMETERS ADSP-2188M

IDMA Read, Long Read Cycle

3DUDPHWHU

0LQ

0D[

8QLW

IDMA Read, Long Read Cycle

Timing Requirements:

t_IKR

IACK Low before Start of Read¹

0

ns

Switching Characteristics:

t_IKHR

t_IKDS

IACK High after Start of Read¹

10

ns

IAD15–0 Data Setup before IACK Low

0.5t_CK- 2

0

t_IKDH

t_IKDD

t_IRDE

t_IRDV

t_IRDH1

t_IRDH2

IAD15–0 Data Hold after End of Read²

IAD15–0 Data Disabled after End of Read²

10

IAD15–0 Previous Data Enabled after Start of Read

IAD15–0 Previous Data Valid after Start of Read

IAD15–0 Previous Data Hold after Start of Read (DM/PM1)³

IAD15–0 Previous Data Hold after Start of Read (PM2)⁴

0

2t_CK- 5

t_CK- 5

NOTES

¹Start of Read = IS Low and IRD Low.

²End of Read = IS High or IRD High.

³DM read or first half of PM read.

⁴Second half of PM read.

,$&.

t_IKHR

t_IKR

,6

t_IRP

,5'

t_{IKD S}

t_IKDH

t_{IRD E}

READ

DATA

IAD 15-0

t_{IRD V}

t_IKDD

t_IRDH

Figure 30 IDMA Read, Long Read Cycle

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

REV. PrA

47

April 1999

ADSP-2188M Preliminary Data Sheet

For current information contact Analog Devices at (781) 461-3881

TIMING PARAMETERS ADSP-2188M

IDMA Read, Short Read Cycle

3DUDPHWHU

0LQ0D[

8QLW

IDMA Read, Short Read Cycle

Timing Requirements:

t_IKR

t_IRP

IACK Low before Start of Read¹

Duration of Read

0

10

ns

Switching Characteristics:

ns

t_IKHR

t_IKDH

t_IKDD

t_IRDE

t_IRDV

IACK High after Start of Read¹

10

IAD15–0 Data Hold after End of Read²

0

IAD15–0 Data Disabled after End of Read²

IAD15–0 Previous Data Enabled after Start of Read

IAD15–0 Previous Data Valid after Start of Read

NOTES

¹Start of Read = IS Low and IRD Low.

²End of Read = IS High or IRD High.

,$&.

t_IKR

t_IKHR

,6

t_IRP

,5'

t_IKDH

t_{IRD E}

PREVIO US

DATA

IAD 15-0

t_IKDD

t_{IRD V}

Figure 31 IDMA Read, Short Read Cycle

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

48

REV. PrA

ADSP-2188M Preliminary Data Sheet

For current information contact Analog Devices at (781) 461-3881

April 1999

100-Lead LQFP Package Pinout

ì

$é î ,$'ê

$è î ,$'é

*1'

$ç î ,$'è

$æî ,$'ç

æè

'ìè

'ìé

'ìê

'ìë

*1'

$å î ,$'æ

$ä î ,$'å

$ìí î ,$'ä

$ìì î ,$'ìí

$ìë î ,$'ìì

'ìì

'ìí

'ä

9''(;7

*1'

$ìê î ,$'ìë

'å

$'63ðëìåå0

*1'

&/.,1

;7$/

9''(;7

'æ î ,:5

'ç î ,5'

'è î ,$/

'é î ,6

ìííð/HDG /4 )3 3LQRXW

7RS 9LHZ õSLQV GRZQô

&/.287

*1'

9'',17

: 5

9'',17

'ê î ,$&.

'ë î ,$'ìè

'ì î ,$'ìé

'í î ,$'ìê

%*

5'

%0 6

'06

30 6

,206

&0 6

ëè

(%*

%5

(%5

èì

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

REV. PrA

49

ADSP-2188M Preliminary Data Sheet

For current information contact Analog Devices at (781) 461-3881

April 1999

The ADSP-2188M package pinout appears in Table 7. Pin names in bold text replace the plain text

named functions when Mode C = 1. A + sign separates two functions when either function can be active

for either major I/O mode. Signals enclosed in brackets [ ] are state bits latched from the value of the

pin at the deassertion of RESET.

Table 7 ADSP-2188M Package Pinout

LQFP

Pin Name

LQFP

Pin Name

LQFP

Pin Name

LQFP

Pin Name

Number

1

A4 / IAD3

A5 / IAD4

GND

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

IRQE + PF4

IRQL0 + PF5

GND

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

EBR

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

D16

2

BR

D17

3

EBG

D18

4

A6 / IAD5

A7 / IAD6

A8 / IAD7

A9 / IAD8

A10 / IAD9

A11 / IAD10

A12 / IAD11

A13 / IAD12

GND

IRQL1 + PF6

IRQ2 + PF7

DT0

BG

D19

5

D0 / IAD13

D1 / IAD14

D2 / IAD15

D3 / IACK

VDDINT

GND

6

D20

7

TFS0

D21

8

RFS0

D22

9

DR0

D23

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

SCLK0

VDDEXT

DT1

FL2

D4 / IS

D5 / IAL

D6 / IRD

D7 / IWR

D8

FL1

FL0

CLKIN

TFS1

PF3 [Mode D]

PF2 [Mode C]

VDDEXT

PWD

XTAL

RFS1

VDDEXT

CLKOUT

GND

DR1

GND

SCLK1

ERESET

RESET

EMS

VDDEXT

D9

GND

VDDINT

WR

PF1 [Mode B]

PF0 [Mode A]

BGH

D10

RD

D11

BMS

EE

GND

PWDACK

A0

DMS

ECLK

D12

PMS

ELOUT

ELIN

D13

A1/IAD0

A2 / IAD1

A3 / IAD2

IOMS

D14

CMS

EINT

D15

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

REV. PrA

50

ADSP-2188M Preliminary Data Sheet

For current information contact Analog Devices at (781) 461-3881

April 1999

OUTLINE DIMENSIONS

íïçéí õìçïëèô

íïçêí õìçïííô

íïçëí õìèïæèô

7<3 64

íïèèê õìéïíèô

íïèèì õìéïííô

íïèéä õìêïäèô

íïíçê õìïçíô 0$;

íïéæë õìëïííô %6& 64

íïíêí õíïæèô

íïíëé õíïçíô

íïíëí õíïèíô

7<3

ìíí

ì

æç

æè

ìëƒ

7<3

6($7,1*

3/$1(

723 9,(:

õ3,16 '2: 1ô

íïííé

õíïìíëô

,1&+(6 õ0,//,0(7(56ô

0$; /($'

&23/$1$5,7<

ëè

èì

èí

ëç

çƒ ‘ éƒ

íƒ ð æƒ

íïííæ õíïìææô

íïíëí õíïèíô

%6&

íïíìì õíïëæô

íïííä õíïëëô 7<3

íïííæ õíïìæô

íïííè õíïìëæô 7<3

íïííê õíïíææô

/($' 3,7&+

/($' : ,'7+

127(ã

7+( $&78$/ 326,7,21 2) ($&+ /($' ,6 : ,7+,1 íïííêë

õíïíåô )520 ,76 ,'($/ 326,7,21 : +(1 0($685(' ,1

7+( /$7(5$/ ',5(&7,21ï

&(17(5 ),*85(6 $5( 7<3,&$/ 81/(66 27+(5: ,6( 127('

Figure 32 100-Lead Metric Thin Plastic Quad Flatpack

(Dimensions shown in millimeters and inches)

ORDERING GUIDE

Ambient

Temperature

Range

Instruction

Rate

Package

Description

Part Number

Package Option

ST-100

1

ADSP-2188MKST-300x 0°C to +70°C

75

100-Lead LQFP

1. In 1998, JEDEC re-evaluated the specifications for the TQFP package designation, assigning it to packages 1.0 mm thick. Previously

labelled TQFP packages (1.6 mm thick) are now designated as LQFP.

PRINTED IN USA

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

REV. PrA

51

ADSP-2188M Preliminary Data Sheet

For current information contact Analog Devices at (781) 461-3881

April 1999

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

REV. PrA

52


型号：	ADSP-2188MKST-300X
厂家：	ADI
描述：	IC 24-BIT, 75 MHz, OTHER DSP, PQFP100, METRIC, PLASTIC, LQFP-100, Digital Signal Processor 时钟外围集成电路
文件：	总52页 (文件大小：677K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADSP-2188MKST-300X [ADI]

相关型号：

ADSP-2188MKSTZ-300

ADSP-2188N

ADSP-2188NBCA-320

ADSP-2188NBST-320

ADSP-2188NBSTZ-320

ADSP-2188NBSTZ-3202

ADSP-2188NKCA-300X

ADSP-2188NKCA-320

ADSP-2188NKCAZ-320

ADSP-2188NKCAZ-3202

ADSP-2188NKST-320

ADSP-2188NKSTZ-320