ADSP-21MSP58BST-104_技术文档

a

DSP Microcomputers

ADSP-21msp58/59

FUNCTIO NAL BLO CK D IAGRAM

FEATURES

38 ns Instruction Cycle Tim e (26 MIPS) from 13.00 MHz

Crystal

POWERDOWN

CONTROL

LOGIC

MEMORY

ADSP-21msp58/59

ADSP-21msp59

ADSP-2100 Fam ily Code and Function Com patible w ith

New Instruction Set Enhanced for Bit Manipulation

Instructions, Multiplication Instructions, Biased

Rounding, and Global Interrupt Masking

2K

؋

24 Words of On-Chip Program Mem ory RAM

2K

؋

16 Words of On-Chip Data Mem ory RAM

4K

؋

24 Words of On-Chip Program Mem ory ROM

(ADSP-21m sp59 Only)

FLAG

DATA

PROGRAM

MEMORY

4K x 24

PROGRAM

MEMORY

2K x 24

DATA

MEMORY

2K x 16

ADDRESS

PROGRAM

SEQUENCER

GENERATORS

ANALOG

INTERFACE

(ROM)

DAG 1 DAG 2

PROGRAM MEMORY ADDRESS

DATA MEMORY ADDRESS

PROGRAM MEMORY DATA

DATA MEMORY DATA

EXTERNAL

ADDRESS

BUS

EXTERNAL

DATA

BUS

8-Bit Parallel Host Interface Port

Analog Interface Provides:

16-Bit Sigm a-Delta ADC and DAC

ARITHMETIC UNITS

ALU SHIFTER

TIMER

MAC

HOST

INTERFACE

PORT

SERIAL PORTS

SPORT 1

Program m able Gain Stages

On-Chip Anti-Aliasing & Anti-Im aging Filters

8 kHz Sam pling Frequency

SPORT 0

ADSP-2100 BASE

ARCHITECTURE

65 dB ADC, SNR and THD

GENERAL D ESCRIP TIO N

72 dB DAC, SNR and THD

T he ADSP-21msp58 and ADSP-21msp59 Mixed-Signal Pro-

cessors (MSProcessor^®DSPs) are fully integrated, single-chip

DSPs complete with a high performance analog front end. T he

ADSP-21msp58/59 Family is optimized for voice band applica-

tions such as Speech Compression, Speech Processing, Speech

Recognition, T ext-to Speech, and Speech-to-T ext conversion.

425 m W Typical Pow er Dissipation @ 5.0 V @ 38 ns

<1 m W Pow erdow n Mode w ith 100 Cycle Recovery

Dual Purpose Program Mem ory for Both Instruction

and Data Storage

Independent ALU, Multiplier/ Accum ulator, and Barrel

Shifter Com putational Units

Tw o Independent Data Address Generators

Pow erful Program Sequencer Provides:

Zero Overhead Looping

T he ADSP-21msp58/59 combines the ADSP-2100 base archi-

tecture (three computation units, data address generators, and

program sequencer) with two serial ports, a host interface port,

an analog front end, a programmable timer, extensive interrupt

capability, and on-chip program and data memory.

Conditional Instruction Execution

Tw o Double-Buffered Serial Ports w ith Com panding

Hardw are, One Serial Port (SPORT0) has Autom atic

Data Buffering

Program m able 16-Bit Interval Tim er w ith Prescaler

Program m able Wait State Generation

Autom atic Booting of Internal Program Mem ory from

Byte-Wide External Mem ory, e.g., EPROM, or

Through Host Interface Port

T he ADSP-21msp58 provides 2K words (24-bit) of program

RAM and 2K words (16-bit) of data memory. T he ADSP-

21msp59 provides an additional 4K words (24-bit) of program

ROM. T he ADSP-21msp58/59 integrates a high performance

analog codec based on a single chip, voice band codec, the

AD28msp02. Powerdown circuitry is also provided to meet the

low power needs of battery operated portable equipment. T he

ADSP-21msp58/59 is available in a 100-pin T QFP package

(thin quad flat package).

Stand-Alone ROM Execution (ADSP-21m sp59 Only)

Single-Cycle Instruction Execution

Single-Cycle Context Sw itch

Multifunction Instructions

In addition, the ADSP-21msp58/59 supports new instructions,

which include bit manipulations–bit set, bit clear, bit toggle,

bit test–new ALU constants, new multiplication instruction

(x squared), biased rounding, and global interrupt masking.

Three Edge- or Level-Sensitive External Interrupts

Low Pow er Dissipation in Standby Mode

100-Lead TQFP

MSProcessor is a registered trademark of Analog Devices, Inc.

REV. 0

Inform ation furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assum ed by Analog Devices for its

use, nor for any infringem ents of patents or other rights of third parties

which m ay result from its use. No license is granted by im plication or

otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norw ood. MA 02062-9106, U.S.A.

Tel: 617/ 329-4700

Fax: 617/ 326-8703

ADSP-21msp58/59

D IGITAL ARCH ITECTURE O VERVIEW

T he two address buses (PMA, DMA) share a single external ad-

dress bus, allowing memory to be expanded off chip, and the

two data buses (PMD, DMD) share a single external data bus.

T he BMS, DMS, and PMS signals indicate which memory

space the external buses are being used for.

Figure 1 is an overall block diagram of the ADSP-21msp58/59.

T he processors contain three independent computational units:

the ALU, the multiplier/accumulator (MAC), and the shifter.

T he computational units process 16-bit data directly and have

provisions to support multiprecision computations. T he ALU

performs a standard set of arithmetic and logic operations; divi-

sion primitives are also supported. T he MAC performs single-

cycle multiply, multiply/add, and multiply/subtract operations.

T he shifter performs logical and arithmetic shifts, normalization,

denormalization, and derive exponent operations. T he shifter

can be used to efficiently implement numeric format control in-

cluding multiword floating-point representations.

Program memory can store both instructions and data, permit-

ting the ADSP-21msp58/59 to fetch two operands in a single

cycle, one from program memory and one from data memory.

T he ADSP-21msp58/59 can fetch an operand from on-chip

program memory and the next instruction in the same cycle.

T he memory interface supports slow memories and memory-

mapped peripherals with programmable wait state generation.

External devices can gain control of the processors’ buses with

the use of the bus request/grant signals (BR and BG). Bus grant

has two modes of operation. If GoMode is enabled in the MSTAT

register, instruction execution continues from internal memory.

If GoMode is disabled, the processor stops instruction execution

and waits for deassertion of BR.

T he internal result (R) bus directly connects the computational

units so that the output of any unit may be the input of any unit

on the next cycle.

A powerful program sequencer and two dedicated data address

generators ensure efficient use of these computational units.

T he sequencer supports conditional jumps, subroutine calls,

and returns in a single cycle. With internal loop counters and

loop stacks, the ADSP-21msp58/59 executes looped code with

zero overhead—no explicit jump instructions are required to

maintain the loop.

In addition to the address and data bus for external memory

connection, the ADSP-21msp58/59 has a host interface port

(HIP) for easy connection to a host processor. T he HIP is made

up of 8 data/address pins and 10 control pins. T he HIP is ex-

tremely flexible and provides a simple interface to a variety of

host processors. For example, the Motorola 68000 series, the

Intel 80C51 series, and the Analog Devices ADSP-2101 can be

easily connected to the HIP. T he host processor can boot the

ADSP-21msp58/59 on-chip memory through the HIP.

T wo data address generators (DAGs) provide addresses for si-

multaneous dual operand fetches (from data memory and pro-

gram memory). Each DAG maintains and updates four address

pointers. Whenever the pointer is used to access data (indirect

addressing), it is post-modified by the value of one of four

modify registers. A length value may be associated with each

pointer to implement automatic modulo addressing for circular

buffers. T he circular buffering feature is also used by the serial

ports for automatic data transfers to (and from) on-chip

memory.

T he ADSP-21msp58/59 can respond to eleven interrupts. T here

can be up to three external interrupts, configured as edge- or

level-sensitive, and seven internal interrupts generated by the

T imer, the Serial Ports (SPORT s), the HIP, the powerdown cir-

cuitry, and the analog interface. T here is also a master RESET

signal.

Efficient data transfer is achieved with the use of five internal

buses:

T he two serial ports provide a complete synchronous serial in-

terface with optional companding in hardware and a wide vari-

ety of framed or frameless data transmit and receive modes of

operation. Each port can generate an internal programmable se-

rial clock or accept an external serial clock.

• Program Memory Address (PMA) Bus

• Program Memory Data (PMD) Bus

• Data Memory Address (DMA) Bus

• Data Memory Data (DMD) Bus

• Result (R) Bus

Booting circuitry provides for loading on-chip program memory

automatically from byte-wide external memory. After reset,

1

PROGRAM

INSTRUCTION

SRAM

FLAG

REGISTER

2K x 24

DATA

SRAM

2K x 16

BOOT

ADDRESS

GENERATOR

PROGRAM

ROM

DATA

ADDRESS

GENERATOR

#1

DATA

ADDRESS

GENERATOR

#2

7

ADC, DAC

AND

FILTERS

4K x 24

PROGRAM

SEQUENCER

(ADSP-21msp59)

PMA BUS

DMA BUS

PMD BUS

DMD BUS

14

24

16

14

24

EXTERNAL

ADDRESS

BUS

MUX

HIP

EXTERNAL

DATA

BUS

COMPANDING

CIRCUITRY

10

8

INPUT REGS

ALU

INPUT REGS

MAC

INPUT REGS

SHIFTER

CONTROL

TRANSMIT REG

CONTROL

LOGIC

TIMER

RECEIVE REG

SERIAL

PORT 0

SERIAL

PORT 1

OUTPUT REGS

16

OUTPUT REGS

HIP

DATA

BUS

HIP

REGISTER

5

R BUS

POWER

DOWN

CONTROL

LOGIC

1

Figure 1. ADSP-21m sp58/59 Block Diagram

–2–

REV. 0

ADSP-21msp58/59

seven wait states are automatically generated. T his allows, for

example, a 38 ns ADSP-21msp58/59 to use a 250 ns EPROM

as external boot memory. Multiple programs can be selected

and loaded from the EPROM with no additional hardware. T he

on-chip program memory can also be initialized through the

HIP.

P in D escr iptions

T he ADSP-21msp58 and ADSP-21msp59 are available in a

100-lead T QFP package. T able I contains the pin descriptions.

Table I. AD SP -21m sp58/59 P in List

P in

#

T he ADSP-21msp58/59 features a general purpose flag output

whose state is controlled through software. You can use this

output to signal an event to an external device. In addition, the

data input and output pins on SPORT 1 can be alternatively

configured as an input and an output flag.

Group

Nam e

of

Input/

P ins O utput Function

Digital Pins

Address

14

24

O

Address output for program,

data and boot memory spaces

A programmable interval timer can generate periodic interrupts.

A 16-bit count register (T COUNT ) is decremented every n

cycles, where n–1 is a scaling value stored in an 8-bit register

(T SCALE). When the value of the count register reaches zero,

an interrupt is generated and the count register is reloaded from

a 16-bit period register (T PERIOD).

Data

I/O

Data I/O pins for program

and data memories. Input

only for boot memory space,

with two MSBs used as boot

space addresses.

T he ADSP-21msp58/59 instruction set provides flexible data

moves and multifunction (one or two data moves with a compu-

tation) instructions. Every instruction can be executed in a

single processor cycle. T he ADSP-21msp58/59 uses an alge-

braic syntax for ease of coding and readability. A comprehensive

set of development tools supports program development.

RESET

IRQ2

BR

1

I

Processor reset input

I

External interrupt request # 2

External bus request input

External bus grant output

External program memory select

External data memory select

Boot memory select

I

BG

O

I

PMS

DMS

BMS

RD

Ser ial P or ts

T he ADSP-21msp58/59 processors include two synchronous se-

rial ports (SPORT 0 and SPORT 1) for serial communications

and multiprocessor communication.

External memory read enable

External memory write enable

Memory map select

WR

MMAP

Here is a brief list of the capabilities of the ADSP-21msp58/59

SPORT s. Refer to the ADSP-2100 Family User’s Manual for fur-

ther details.

CLKIN,

XT AL

2

I

External clock or quartz crystal

input

• SPORT s are bidirectional with a separate, double-buffered

transmit and receive section.

CLKOUT

HACK

1

O

I

Processor clock output

HIP acknowledge output

HIP select input

• SPORT s can use an external serial clock or generate their own

clock internally.

HSEL

BMODE

I

Boot mode select (0 = Standard

EPROM Booting, 1 = HIP

Booting)

• SPORT s have independent framing for the transmit and

receive sections. Sections run in a frameless mode or with

frame synchronization signals internally or externally gener-

ated. Frame sync signals are programmed to be active high or

low, with either of two pulse widths and timings.

HMD0

1

I

Bus strobe select (0 = RD/WR,

1 = RW/DS)

HIP address/data mode select

HMD1

• SPORT s support serial data word lengths from 3 to 16 bits

and provide optional A-law and µ-law companding according

to CCIT T recommendation G.711.

(0 = Separate, 1 = Multiplexed)

HRD/HRW

HWR/HDS

HIP read strobe or read/write

select

• SPORT s receive and transmit sections generate separate

interrupts when the SPORT s are ready to read or write new

data.

HIP write strobe or host data

strobe select

HD7–0/

HAD7–0

• SPORT s can receive and transmit an entire circular buffer of

data with only one overhead cycle per data word (Autobuffering

Mode). An interrupt is generated after a complete data buffer

transfer.

8

1

I/O

I

HIP data or HIP data and

address

HA2/ALE

Host address 2 or address latch

enable

• SPORT 0 has a multichannel interface to selectively receive

and transmit a 24- or 32-word, time-division multiplexed

serial bit stream.

HA1–0/

(unused)

2

5

I

Host address 1 and 0 inputs

SPORT 0

SPORT 1

or

I/O

Serial port 0 pins (TFS0, RFS0,

DT0, DR0, SCLK0)

• SPORT 1 can be reconfigured as two external interrupt inputs

(IRQ0 and IRQ1) and the Flag In and Flag Out signals (FI,

FO). T he internally generated serial clock may still be used in

this configuration.

5

I/O

Serial port 1 pins (TFS1, RFS1,

DT1, DR1, SCLK1)

REV. 0

–3–

ADSP-21msp58/59

T ying these pins to appropriate values configures the ADSP-

21msp58/59 for straight-wire interface to a variety of industry-

standard microprocessors and microcomputers.

P in

Group

Nam e

#

of

Input/

P ins O utput Function

When the host processor writes an 8-bit value to the HIP, the

upper eight bits of the HIP registers are all zeros. For additional

information, refer to the ADSP-2100 Family User’s Manual,

Chapter 7, for information about 8-bit configuration.

IRQ0 (RFS1) 1

IRQ1 (TFS1) 1

I

External interrupt request # 0

External interrupt request # 1

Programmable clock output

Flag input pin

I

SCLK1

FI (DR1)

FO (DT1)

FL0

1

4

5

1

O

I

H IP O per ation

T he HIP contains six data registers (HDR5-0) and two status

registers (HSR7-6) with an associated HMASK register for

masking interrupts from individual HIP data registers. T he HIP

data registers are memory-mapped in the internal data memory

of the ADSP-21msp58/59. HIP transfers can be managed using

either interrupts or polling. T hese registers are shown in the sec-

tion “ADSP-21msp58/59 Registers.” T he two status registers

provide status information to both the ADSP-21msp58/59 and

the host processor. HSR7 contains a software reset bit that can

be set by the ADSP-21msp58/59 and the host.

O

Flag output pin

General purpose flag output pin

Digital power supply pins

Ground pins

V_DD

GND

PWD

I

Powerdown pin

Analog Pins

VIN_NORM

1

Input terminal of the NORM

amplifier for the encoder section

(ADC)

T he HIP allows a software reset to be performed by the host

processor. T he internal software reset signal is asserted for five

ADSP-21msp58/59 cycles.

VIN_AUX

Decouple

VOUT_P

VOUT _N

V_REF

I

Input terminal of the AUX

amplifier for the encoder section

(ADC)

I

Ground reference of the NORM

and AUX amplifiers for the

encoder section (ADC)

T he HIP generates an interrupt whenever an HDR register re-

ceives data from a host processor write. It also generates an in-

terrupt when the host processor has performed a successful read

of any HDR. T he read/write status of the HDRs is also stored in

the HSR registers.

O

Noninverting output terminal of

the differential amplifier from

the decoder section (DAC)

T he HMASK register bits can be used to mask the generation of

read or write interrupts from individual HDR registers. Bits in

the IMASK register enable and disable all HIP read interrupts

or all HIP write interrupts. So, for example, a write to HDR4

will cause an interrupt only if both the HDR4 Write bit in

HMASK and the HIP Write interrupt enable bit in IMASK are

set.

Inverting output terminal of the

differential amplifier from the

decoder section (DAC)

1

O

Output voltage reference

REF_

FILT ER

Voltage reference external by-

pass filter node

T he HIP provides a second method of booting the ADSP-

21msp58/59 in which the host processor loads instructions into

the HIP. T he ADSP-21msp58/59 automatically transfers the

data, in this case opcodes, to internal program memory. T he

BMODE pin determines whether the ADSP-21msp58/59 boots

from the host processor through the HIP or from external

EPROM over the data bus.

V_CC

GND_A

1

2

Analog power supply

Analog ground

H ost Inter face P or t

T he ADSP-21msp58/59 host interface port (HIP) is a parallel

I/O port that allows for an easy connection to a host processor.

T hrough the HIP, the ADSP-21msp58/59 can be used as a

memory-mapped peripheral to a host computer. T he HIP can

be thought of as an area of dual-ported memory, or mailbox reg-

isters, that allows communication between the computational

core of the ADSP-21msp58/59 and the host computer.

Inter r upts

T he interrupt controller lets the processor respond to interrupts

and reset with a minimum of overhead. T he ADSP-21msp58/59

provides up to three external interrupt input pins, IRQ0, IRQ1,

and IRQ2. IRQ2 is always available as a dedicated pin;

SPORT 1 may be reconfigured for IRQ1 and IRQ0 and the flag.

T he ADSP-21msp58/59 also supports internal interrupts from

the timer, the host interface port, the serial ports, the analog in-

terface, and the powerdown control circuit. T he interrupts are

internally prioritized and individually maskable (except for

powerdown and RESET). T he input pins can be programmed

for either level- or edge-sensitivity. T he priorities and vector ad-

dresses for the interrupts are shown in T able II; the interrupt

registers are shown in Figure 2.

T he host interface port is completely asynchronous. T he host

processor can write data into the HIP while the ADSP-

21msp58/59 is operating at full speed.

T he HIP can be configured with the following pins:

• BMODE (when MMAP = 0) determines whether the ADSP-

21msp58/59 boots from the host processor (through the HIP)

or external EPROM (through the data bus).

• HMD0 configures the bus strobes as separate read and write

strobes, or a single read/write select and a host data strobe.

• HMD1 selects separate address (3-bit) and data (8-bit) buses,

or a multiplexed 8-bit address/data bus with address latch

enable.

–4–

REV. 0

ADSP-21msp58/59

IMASK

ICNTL

9

0

8

0

7

0

6

0

5

4

3

0

2

0

1

0

4

3

0

2

1

0

Timer

IRQ2

HIP Write

IRQ0 Sensitivity

IRQ1 Sensitivity

IRQ2 Sensitivity

1 = edge

0 = level

IRQ0 or SPORT1 Receive

IRQ1 or SPORT1 Transmit

Analog Receive

HIP Read

SPORT0 Transmit

SPORT0 Receive

Analog Transmit

1 = enable, 0 = disable

Interrupt Nesting

1 = enable, 0 = disable

IFC

15 14 13 12 11 10

9

0

8

7

6

0

5

0

4

0

3

0

2

0

1

0

INTERRUPT FORCE

INTERRUPT CLEAR

IRQ2

SPORT0 Transmit

SPORT0 Receive

Analog Transmit

Analog Receive

Timer

SPORT1 Receive or IRQ0

SPORT1 Transmit or IRQ1

Analog Receive

Analog Transmit

SPORT0 Receive

SPORT0 Transmit

SPORT1 Transmit or IRQ1

SPORT1 Receive or IRQ0

Timer

IRQ2

1 = enable, 0 = disable

Figure 2. Interrupt Registers

T he following instructions allow global enable or disable servic-

ing of the interrupts (including powerdown), regardless of the

state of IMASK. Disabling the interrupts does not affect

autobuffering.

Table II. Interrupt P riority & Interrupt Vector Addresses

Interrupt Vector

Source of Interrupt

Address (Hex)

ENA INTS;

DIS INTS;

Interrupt servicing is enabled on processor reset.

Reset (or Power-Up with PUCR = 1)

Powerdown (Nonmaskable)

IRQ2

0000 (Highest Priority)

002C

0004

HIP Write

HIP Read

0008

000C

System Inter face

Figure 3 shows a basic system configuration with the ADSP-

21msp58/59, two serial devices, a host processor, a boot

EPROM, optional external program and data memories, and an

analog interface. Up to 15K words of data memory and 16K

words of program memory can be supported. Programmable

wait state generation allows the processor to interface easily to

slow memories. T he ADSP-21msp58/59 also provides one ex-

ternal interrupt and two serial ports or three external interrupts

and one serial port.

SPORT 0 T ransmit

SPORT 0 Receive

0010

0014

0018

001C

0020

0024

Analog Interface T ransmit

Analog Interface Receive

SPORT 1 T ransmit or (IRQ1)

SPORT 1 Receive or (IRQ0)

T imer

0028 (Lowest Priority)

Interrupts can be masked or unmasked with the IMASK regis-

ter. Individual interrupt requests are logically ANDed with the

bits in IMASK; the highest priority unmasked interrupt is then

selected. T he powerdown interrupt is non-maskable.

Clock Signals

T he ADSP-21msp58/59 CLKIN input may be driven by a crys-

tal or by a T T L-compatible external clock signal.

T he CLKIN input may not be halted, changed in frequency

during operation, or operated at any frequency other the one

specified. Operating the ADSP-21msp58/59 at any other fre-

quency changes the analog performance, which is not tested or

supported.

T he interrupt control register, ICNT L, allows the external in-

terrupts to be set as either edge- or level-sensitive. Interrupt ser-

vice routines can either be nested (with higher priority interrupts

taking precedence) or be processed sequentially (with only one

interrupt service active at a time).

If an external clock is used, it should be a T T L-compatible sig-

nal running at half the instruction rate. T he signal should be

connected to the processor’s CLKIN input; in this case, the

XT AL input must be left unconnected.

T he interrupt force and clear register, IFC, is a write-only regis-

ter used to force an interrupt or clear a pending edge-sensitive

interrupt.

On-chip stacks preserve the processor status and are automati-

cally maintained during interrupt handling. T he stack is twelve

levels deep to allow interrupt nesting.

T he ADSP-21msp58/59 uses an input clock with a frequency

equal to half the instruction rate; a 13 MHz input clock yields a

38.46 ns processor cycle (which is equivalent to 26 MHz). Nor-

mally, instructions are executed in a single processor cycle.

Register bit values shown in Figure 2 are the default bit values

after reset. If no values are shown, the bits are indeterminate at

reset. Reserved bits are shown in gray; these bits should always

be written with zeros.

All device timing is relative to the internal instruction clock rate,

which is indicated by the CLKOUT signal when enabled. T he

REV. 0

–5–

ADSP-21msp58/59

ANALOG

INPUT

ANALOG

OUTPUT

HIP CONTROL

HOST

PROCESSOR

CLOCK OR

CRYSTAL

HIP DATA/ADDR

(OPTIONAL)

3

4

5

1

2

3

4

7

8

CLKIN

HOST

MODE

XTAL

V

GND

V

GND

HIP

SCLK

RFS

TFS

DT

CC

A

DD

CLKOUT

RESET

IRQ2

BR

SERIAL DEVICE

(OPTIONAL)

SERIAL

PORT 0

DR

ADSP-21msp58/59

SCLK

RFS OR IRQ0

BG

SERIAL DEVICE

(OPTIONAL)

TFS OR IRQ1

DT OR FO

DR OR FI

MMAP

FL0

SERIAL

PORT 1

PMS

RD

WR

ADDRESS DATA DMS

14

BMS

24

D

23-22

2

D

23-8

16

14

D

15-8

24

8

CS

A

D

A

D

CS

A

D

CS

OE

BOOT

MEMORY

e.g., EPROM

27C64

27C128

27C256

27C512

DATA

MEMORY &

PERIPHERALS

WE

PROGRAM

MEMORY

(OPTIONAL)

NOTE: The two MSBs of the Boot EPROM Address are also the two MSBs of the Data Bus.

This is only for the 27C256 and 27C512.

Figure 3. ADSP-21m sp58/59 Basic System Configuration

2000 CLKIN cycles will ensure that the PLL has locked (this

does not, however, include the crystal oscillator start-up time).

During this power-up sequence, the RESET signal should be

held low. On any subsequent resets, the RESET signal must

CLKOUT signal is enabled and disabled by the CLKODIS bit

in the SPORT 0 Autobuffer Control Register, DM[0x3FF3].

Because the ADSP-21msp58/59 includes an on-chip oscillator

circuit, an external crystal may also be used. T he crystal should

be connected across the CLKIN and XT AL pins, with two ca-

pacitors connected as shown in Figure 4. A parallel-resonant,

fundamental frequency, microprocessor-grade crystal should be

used.

meet the minimum pulse width specification, t_RSP

.

T he RESET input contains some hysteresis; however, if you use

an RC circuit to generate your RESET signal, the use of an ex-

ternal Schmidt trigger is recommended.

T he master RESET sets all internal stack pointers to the empty

stack condition, masks all interrupts, and clears the MST AT

register. When RESET is released, if there is no pending bus re-

quest and the chip is configured for booting (MMAP = 0), the

boot loading sequence is performed. T hen the first instruction is

fetched from internal program memory location 0x0000 and ex-

ecution begins.

CLKIN

XTAL

CLKOUT

ADSP-21msp58/59

P r ogr am Mem or y Inter face

Figure 4. External Crystal Connections

T he on-chip program memory address bus (PMA) and on-chip

program memory data bus (PMD) are multiplexed with the on-

chip data memory buses (DMA, DMD), creating a single exter-

nal data bus and a single external address bus. T he data and

address busses are three-stated when the DSP runs from inter-

nal memory. Refer to the ADSP-2100 Family User’s Manual,

Chapter 10, “Memory Interface” for a detailed explanation. T he

14-bit address bus directly addresses up to 16K words. See

“Program Memory Maps” for details on program memory

addressing.

Reset

T he RESET signal initiates a master reset of the ADSP-

21msp58/59. T he RESET signal must be asserted during the

power-up sequence to assure proper initialization. RESET dur-

ing initial power-up must be held long enough to allow the

processor’s internal clock to stabilize. If RESET is asserted at

any time after power-up, the clock continues to run and does

not require stabilization time.

T he power-up sequence is defined as the total time required for

the crystal oscillator circuit to stabilize after a valid V_DDis ap-

plied to the processor and for the internal phase-locked loop

(PLL) to lock onto the specific crystal frequency. A minimum of

T he program memory data lines are bidirectional. T he program

memory select (PMS) signal indicates access to program

memory and can be used as a chip select signal. T he write (WR)

signal indicates a write operation and is used as a write strobe.

–6–

REV. 0

ADSP-21msp58/59

T he read (RD) signal indicates a read operation and is used as a

read strobe or output enable signal. An external program

memory access should always be qualified with the PMS signal.

When MMAP = 1, 14K words of external program memory be-

gin at address 0x0000 and internal RAM is located in the upper

2K words, beginning at address 0x3800. In this configuration,

the boot loading sequence does not take place; execution begins

immediately after RESET.

T he ADSP-21msp58/59 writes data from its 16-bit registers to

24-bit program memory using the PX register to provide the

lower eight bits. When the processor reads data (not instruc-

tions) from 24-bit program memory to a 16-bit data register, the

lower eight bits are placed in the PX register. T he program

memory interface can generate zero to seven wait states for ex-

ternal memory devices; the default is seven wait states after

RESET.

AD SP -21m sp59

T he ADSP-21msp59 is functionally identical to the ADSP-

21msp58. T he ADSP-21msp59 includes an additional 4K by

24-bit mask programmable ROM (see Figure 6). T he ROM

can be used to hold program instructions or data and can be

accessed twice in one instruction cycle if necessary. T he ROM

always resides at locations PM[0x0800] through PM[0x17FF]

regardless of the state of the MMAP pin. Sixteen addresses at

the end of ROM (0x17F0–0x17FF) are reserved for Analog

Devices’ use. The ROM is enabled by setting the ROMENABLE

bit in the Data Memory Wait State control register, DM[0x3FFE].

When the ROMENABLE bit is set to 1, addressing program

memory in this range will access the on-chip ROM. When set

to 0, addressing program memory in this range will access exter-

nal program memory. T he ROMENABLE bit is set to 0 on

chip reset.

P r ogr am Mem or y Maps

AD SP -21m sp58

ADSP-21msp58 Program memory can be mapped in two ways,

depending on the state of the MMAP pin. Figure 5 shows the

two configurations. When MMAP = 0, internal RAM occupies

2K words beginning at address 0x0000; external program

memory uses the remaining 14K words beginning at address

0x0800. In this configuration, the boot loading sequence (de-

scribed in “Boot Memory Interface”) is automatically initiated

when RESET is released.

D ata Mem or y Inter face

0000

T he data memory address bus (DMA) is 14 bits wide. T he bi-

directional external data bus is 24 bits wide, with the upper 16

bits used for data memory data (DMD) transfers.

INTERNAL

RAM

LOADED FROM

EXTERNAL

BOOT

EXTERNAL

MEMORY

T he data memory select (DMS) signal indicates access to data

memory and can be used as a chip select signal. T he write (WR)

signal indicates a write operation and can be used as a write

strobe. T he read (RD) signal indicates a read operation and can

be used as a read strobe or output enable signal.

07FF

0800

EXTERNAL

T he ADSP-21msp58/59 supports memory-mapped I/O, with

the peripherals memory mapped into the data or program

memory address spaces and accessed by the processor in the

same manner.

37FF

3800

INTERNAL

RAM

NOT LOADED

D ata Mem or y Map

T he on-chip data memory RAM resides in the 2K words begin-

ning at address 0x3000, as shown in Figure 7. In addition, data

memory locations from 0x3800 to the end of data memory at

0x3FFF are reserved. Control registers for the system, timer,

3FFF

MMAP=0

MMAP=1

Figure 5. ADSP-21m sp58 Program Mem ory Maps

0000

INTERNAL

RAM

INTERNAL

RAM

LOADED FROM

EXTERNAL

BOOT

LOADED FROM

EXTERNAL

BOOT

EXTERNAL

MEMORY

07FF

0800

07FF

0800

07FF

0800

INTERNAL

MASK

INTERNAL

MASK

PROGRAMMED

ROM

PROGRAMMED

ROM

17F0 – 17FF

RESERVED

17F0 – 17FF

RESERVED

17FF

1800

17FF

1800

EXTERNAL

37FF

3800

EXTERNAL

37FF

3800

INTERNAL

RAM

NOT LOADED

EXTERNAL

INTERNAL

RAM

NOT LOADED

3FFF

ROM ENABLE = 1

MMAP = 0

ROM ENABLE = 0

MMAP = 0

ROM ENABLE = 1

MMAP = 1

ROM ENABLE = 0

MMAP = 1

Figure 6. ADSP-21m sp59 Program Mem ory Maps

–7–

REV. 0

ADSP-21msp58/59

H IP Booting

wait-state configuration, host interface port, codec, and serial

port operations are located in this region of memory.

T he ADSP-21msp58/59 can also boot programs through the

Host Interface Port. If BMODE = 1 and MMAP = 0, the

ADSP-21msp58/59 boots from the HIP. If BMODE = 0, the

ADSP-21msp58/59 boots through the data bus (in the same

way as the ADSP-2101), as described above in “Boot Memory

Interface.” For additional information about HIP booting, refer

to the ADSP-2100 Family User’s Manual, Chapter 7, “Host In-

terface Port.”

T he remaining 12K of data memory is external. External data

memory is divided into three zones, each associated with its own

wait-state generator. By mapping peripherals into different

zones, you can accommodate peripherals with different wait-

state requirements. All zones default to seven wait states after

RESET.

For compatibility with other ADSP-2100 Family processors, bit

definitions for DWAIT 3 and DWAIT 4 are shown in the Data

Memory Wait State Control register, but they are not used by

the ADSP-21msp58/59.

T he ADSP-2100 Family Development Software includes a

utility program called the HIP Splitter. T his utility allows the

creation of programs that can be booted through the ADSP-

21msp58/59 HIP, in a similar fashion as EPROM-bootable

programs generated by the PROM Splitter utility.

0000

DWAIT0

(1K EXTERNAL)

Bus Request and Bus Gr ant

03FF

0400

T he ADSP-21msp58/59 can relinquish control of the data and

address buses to an external device. When the external device

requires access to memory, it asserts the bus request signal

(BR). If the ADSP-21msp58/59 is not performing an external

memory access, it responds to the active BR input in the follow-

ing processor cycle by

DWAIT1

(1K EXTERNAL)

07FF

0800

12K

EXTERNAL

DWAIT2

(10K EXTERNAL)

2FFF

3000

2FFF

3000

• three-stating the data and address buses and the PMS, DMS,

BMS, RD, and WR output drivers,

2K

INTERNAL

• asserting the bus grant (BG) signal, and

37FF

3800

NO WAIT STATES

1K

• halting program execution.

RESERVED

3BFF

3C00

If GoMode is enabled, the ADSP-21msp58/59 will not halt pro-

gram execution until it encounters an instruction that requires

an external memory access.

MEMORY MAPPED

REGISTERS

AND RESERVED

3FFF

DATA MEMORY

WAIT STATES

If the ADSP-21msp58/59 is performing an external memory ac-

cess when the external device asserts the BR signal, then it will

not three-state the memory interfaces or assert the BG signal

until the cycle after the access is completed, which can be up to

eight cycles later depending on the number of wait states. T he

instruction does not need to be completed when the bus is

granted. If a single instruction requires two external memory

accesses, the bus will be granted between the two accesses.

Figure 7. ADSP-21m sp58/59 Data Mem ory Maps

Boot Mem or y Inter face

T he ADSP-21msp58/59 can load on-chip memory from exter-

nal boot memory space. T he boot memory space consists of

64K by 8-bit space, divided into eight separate 8K by 8-bit

pages. T hree bits in the System Control Register select which

page is loaded by the boot memory interface. Another bit in the

System Control Register allows the user to force a boot loading

sequence under software control. Boot loading from Page 0 after

RESET is initiated automatically if MMAP = 0.

When the BR signal is released, the processor releases the BG

signal, which reenables the output drivers, and continues pro-

gram execution from the point where it stopped.

T he bus request feature operates at all times, including when

the processor is booting and when RESET is active.

T he boot memory interface can generate zero to seven wait

states; it defaults to seven wait states after RESET. T his allows

the ADSP-21msp58/59 to boot from a single low cost EPROM

such as a 27C256. Program memory is booted one byte at a

time and converted to 24-bit program memory words.

LO W P O WER O P ERATIO N

T he ADSP-21msp58/59 has three low power modes that signifi-

cantly reduce the power dissipation when the device operates

under standby conditions. T hese modes are:

T he BMS and RD signals are used to select and to strobe the

boot memory interface. Only 8-bit data is read over the data

bus, on pins D8–D15. T o accommodate addressing up to eight

pages of boot memory, the two MSBs of the data bus are used

in the boot memory interface as the two MSBs of the boot

memory address.

• Powerdown

• Idle

• Slow Idle

T he CLKOUT pin may also be disabled to reduce external

power dissipation. T he CLKOUT pin is controlled by Bit 14 of

SPORT 0 Autobuffer Control Register, DM[0x3FF3].

T he ADSP-2100 Family Assembler and Linker support the cre-

ation of programs and data structures requiring multiple boot

pages during execution.

P ower down

RD and WR must always be qualified by PMS, DMS, or BMS

T he ADSP-21msp58/59 has a low power feature that lets the

processors enter a very low power dormant state through hard-

ware or software control. Here is a brief list of powerdown fea-

tures. Refer to the ADSP-2100 Family User’s Manual, Chapter 9,

to ensure the correct program, data, or boot memory accessing.

–8–

REV. 0

ADSP-21msp58/59

“System Interface” for detailed information about the power-

down feature.

When the IDLE (n) instruction is used in systems that have an

externally generated serial clock (SCLK), the serial clock rate

may be faster than the processor’s reduced internal clock rate.

Under these conditions, interrupts must not be generated at a

faster rate than can be serviced, due to the additional time the

processor takes to come out of the idle state (a maximum of n

processor cycles).

• Powerdown mode holds the processor in CMOS standby with

a maximum current of less than 100 µA in some modes.

• Quick recovery from powerdown. In some modes, the proces-

sor can begin executing instructions in less than 100 CLKIN

cycles.

Standalone RO M Execution (AD SP -21m sp59 O nly)

When the MMAP and BMODE pins both are set to 1, the

ROM is automatically enabled and execution commences from

program memory location 0x0800 at the start of ROM. T his

feature lets an embedded design operate without external

memory components. T o operate in this mode, the ROM coded

program must copy an interrupt vector table to the appropriate

locations in program memory RAM. In this mode, the ROM

enable bit defaults to 1 during reset.

• Support for an externally generated T T L or CMOS processor

clock. T he external clock can continue running during

powerdown without affecting the lowest power rating and 100

CLKIN cycle recovery.

• Support for crystal operation includes disabling the oscillator

to save power (the processor automatically waits 4096 CLKIN

cycles for the crystal oscillator to start and stabilize), and

letting the oscillator run to allow 100 CLKIN cycle start-up.

• Powerdown is initiated by either the powerdown pin (PWD)

or the software powerdown force bit.

Table III. Boot Sum m ary Table

BMODE = 0

BMODE = 1

• Interrupt support allows an unlimited number of instructions

to be executed before optionally powering down. T he power-

down interrupt also can be used as a non-maskable, edge-

sensitive interrupt.

MMAP = 0 Boot from EPROM,

then execution starts

at internal RAM

Boot from HIP, then

execution starts at

internal RAM location

0x0000

• Context clear/save control lets the processor continue where it

left off or start with a clean context when leaving the power-

down state.

location 0x0000

MMAP = 1 No booting, execution

Stand Alone Mode,

starts at external memory execution starts at

location 0x0000

• T he RESET pin also can be used to terminate powerdown,

and the host software reset feature can be used to terminate

powerdown under certain conditions.

internal ROM location

0x0800

• Setting the CLKODIS bit (Bit 14 of the SPORT 0 Autobuffer

Control Register [0x3FF3]) disables the CLKOUT pin during

powerdown.

O r der ing P r ocedur e For AD SP -21m sp59 RO M P r ocessor s

T o place an order for a custom ROM-coded ADSP-21msp59

processor, you must:

Idle

1. Complete the following forms contained in the ADSP ROM

Ordering Package, available from your Analog Devices sales

representative:

When the ADSP-21msp58/59 is in the Idle Mode, the processor

waits indefinitely in a low power state until an interrupt occurs.

When an unmasked interrupt occurs, it is serviced; execution

then continues with the instruction following the IDLE instruction.

ADSP-21msp59 ROM Specification Form

ROM Release Agreement

ROM NRE Agreement & Minimum Quantity Order (MQO)

Acceptance Agreement for Preproduction ROM Products

Slow Idle

T he IDLE instruction is enhanced on the ADSP-21msp58/59 to

let the processor’s internal clock signal be slowed, further reduc-

ing power consumption. T he reduced clock frequency, a pro-

grammable fraction of the normal clock rate, is specified by a

selectable divisor given in the IDLE instruction. T he format of

the instruction is

2. Return the forms to Analog Devices along with two copies of

the Memory Image File (.EXE file) of your ROM code. T he

files must be supplied on two 3.5" or 5.25" floppy disks for

the IBM PC (DOS 2.01 or higher).

3. Place a purchase order with Analog Devices for nonrecurring

engineering changes (NRE) associated with ROM product

development.

IDLE (n);

where n = 16, 32, 64, or 128. T his instruction keeps the proces-

sor fully functional, but operating at the slower clock rate. While

it is in this state, the processor’s other internal clock signals,

such as SCLK, and timer clock, are reduced by the same ratio.

CLKOUT remains at the normal rate; it is not reduced. T he de-

fault form of the instruction, when no clock divisor is given, is

the standard IDLE instruction.

After this information is received, it is entered into Analog

Devices’ ROM Manager System that assigns a custom ROM

model number to the product. T his model number will be

branded on all prototype and production units manufactured to

these specifications.

T o minimize the risk of code being altered during this process,

Analog Devices verifies that the .EXE files on both floppy disks

are identical, and recalculates the checksums for the .EXE file

entered into the ROM Manager System. T he checksum data, in

the form of a ROM Memory Map, a hard copy of the .EXE file,

and a ROM Data Verification form are returned to you for

inspection.

When the IDLE (n) instruction is used, it effectively slows down

the processor’s internal clock and thus its response time to in-

coming interrupts––the 1-cycle response time of the standard

idle state is increased by n, the clock divisor. When an enabled

interrupt is received, the ADSP-21msp58/59 remains in the idle

state for up to a maximum of n processor cycles (n = 16, 32, 64,

or 128) before resuming normal operation.

REV. 0

–9–

ADSP-21msp58/59

A signed ROM Verification Form and a purchase order for pro-

duction units are required prior to any product being manufac-

tured. Prototype units may be applied toward the minimum

order quantity.

Bit 10 of the Analog Control Register (0x3FEE) may be set to

add an offset to the input of the ADC sigma-delta converter.

T his offset moves ADC sigma-delta idle tones out of the 4.0

kHz speech band range. T his added offset must be removed by

the ADC high-pass filter. T herefore, the high-pass filter must be

inserted when you use the offset feature.

Upon completion of prototype manufacture, Analog Devices

will ship prototype units and a delivery schedule update for pro-

duction units. An invoice against your purchase order for the

NRE charges is issued at this time.

D /A Conver sion

T he D/A conversion circuitry of the analog interface consists of

a sigma-delta digital-to-analog converter (DAC), an analog

smoothing filter, a programmable gain amplifier (DAC PGA),

and a differential output amplifier.

T here is a charge for each ROM mask generated and a mini-

mum order quantity. Consult your sales representative for de-

tails. A separate order must be placed for parts of a specific

package type, temperature range, and speed grade.

D igital-to-Analog Conver ter

T he digital-to-analog converter consists of an optional digital

high-pass filter, an anti-imaging interpolation filter, and a

sigma-delta modulator. T he digital filters and the sigma-delta

modulator have the same characteristics as the filters and

modulator of the ADC. For detailed description of the DAC

components, refer to the ADSP-2100 Family User’s Manual,

Chapter 8, “Analog Interface.”

ANALO G INTERFACE

T he analog interface contains encoding circuitry (ADC), decod-

ing circuitry (DAC), and processor interface logic. A block dia-

gram of the ADSP-21msp58/59 analog section is shown in

Figure 8.

T he analog interface is configured through the Analog Control

Register and the Analog Autobuffer/Powerdown Register (refer

to “ADSP-21msp58/59 Registers”). T he Analog Control Regis-

ter DM[0x3FEE] configures the programmable gain stages, the

analog input multiplexer, and the analog interface powerdown

state. Note that the unused bits must be cleared to zero.

Analog Sm oothing Filter and P r ogr am m able Gain Am plifier

T he analog smoothing filter consists of a 3rd-order switched ca-

pacitor filter with a 3 dB point at approximately 25 kHz.

T he DAC’s programmable gain amplifier (DAC PGA) can be

used to adjust the output signal level by –15 dB to +6 dB in

3 dB increments. T his gain is selected by bits 2–4 (OG0, OG1,

OG2) of the analog control register.

VIN

16-BIT

SIGMA-

DELTA

ADC

NORM

MUX

ADC

PGA

VIN

AUX

D iffer ential O utput Am plifier

DECOUPLE

REF_FILTER

T he analog output signal (VOUT_P, VOUT_N) is produced by a

differential amplifier. T he differential amplifier meets specifica-

tions for loads greater than 2 kΩ and has a maximum differen-

tial output swing of ±3.156 V peak-to-peak (3.17 dBm0). T he

DAC will drive loads smaller than 2 kΩ, but with degraded

performance.

VOLTAGE

REFERENCE

16

PROCESSOR

INTERFACE

V

REF

BUF

16-BIT

SIGMA-

DELTA

DAC

VOUT

P

ANALOG

SMOOTHING

FILTER

DAC

PGA

VOUT

N

OUTPUT

DIFFERENTIAL AMP

T he output signal is dc-biased to the on-chip voltage reference

(V_REF) and can be ac-coupled directly to a load or dc-coupled to

an external amplifier.

Figure 8. Analog Interface Block Diagram

A/D Conver sion

T he A/D conversion circuitry of the analog interface consists of

an analog multiplexer, a programmable gain amplifier (ADC

PGA), and a 16-bit sigma-delta analog-to-digital converter

(ADC).

T he VOUT_P, VOUT _Noutput must be used as a differential sig-

nal otherwise performance will be severely compromised. Do

not use either pin as a single-ended output.

O P ERATING TH E ANALO G INTERFACE

T he analog interface is operated with several memory-mapped

control and data registers. T he ADC and DAC I/O data is re-

ceived and transmitted through two memory-mapped data regis-

ters. T he data can also be autobuffered directly into (or from)

on-chip memory. In both cases, the I/O processing is interrupt

driven; two interrupts are dedicated to the analog interface, one

for the ADC receive data and one for the DAC transmit data.

Analog Input Multiplexer and Am plifier s

T he analog multiplexer selects either the NORM or AUX input

to the ADC’s sigma-delta modulator. T he inputs should be ac

coupled.

T he ADC PGA may be used to additionally increase the signal

level by +6 dB, +20 dB, or +26 dB. T his gain is selected by bit

9 and bit 0 (IG0, IG1) of the analog control register. Input sig-

nal level to the sigma-delta ADC should not exceed the V_INMAX

specification.

T he ADSP-21msp58/59 must have an input clock frequency of

13 MHz. At this frequency, analog-to-digital and digital-to-ana-

log converted data is transmitted at an 8 kHz rate with a single

16-bit word transmitted every 125 µs.

Analog-To-D igital Conver ter

T he analog interface’s analog-to-digital converter consists of a

4th-order analog sigma-delta modulator, an anti-aliasing deci-

mation filter, and an optional digital high-pass filter. For a detailed

description of the ADC components, refer to the ADSP-2100

Family User’s Manual, Chapter 8, “Analog Interface.”

For detailed information about the analog interface, refer to the

ADSP-2100 Family User’s Manual, Chapter 8, “Analog Interface.”

–10–

REV. 0

ADSP-21msp58/59

Autobuffer ing

APWD bits (Bits 5 and 6) to one in the analog control register.

Because both interrupts occur simultaneously, only one should

be enabled (in IMASK) to vector to a single service routine that

handles transmit and receive data. However, when using

autobuffer transfers, both interrupts should be enabled.

In some applications, it is advantageous to perform block data

transfers between the analog converters and processor memory.

Analog interface autobuffering enables the automatic transfer of

data blocks directly from the ADC to on-chip processor data

memory or from on-chip processor data memory directly to the

DAC.

AD SP -21m sp58/59 REGISTERS

Figure 9 summarizes the ADSP-21msp58/59 registers. Some

registers store values. For example, AX0 stores an ALU oper-

and; I4 stores a DAG2 pointer. Other registers consist of control

bits and fields, or status flags. For example AST AT contains

status flags from arithmetic operations, and fields in DWAIT

control the number of wait states for different zones of data

memory.

AD C and D AC Inter r upts

T he analog interface generates two interrupts that signal either:

(1) a 16-bit, 8 kHz analog-to-digital or digital-to-analog conver-

sion has been completed, or (2) an autobuffer block transfer

has been completed (i.e., the data buffer contents have been

received or transferred).

When an analog interrupt occurs, the processor vectors to the

addresses listed in T able II, Interrupt Priority & Interrupt Vector

Addresses.

A secondary set of registers in all computational units allows a

single-cycle context switch.

T he bit and field definitions for control and status registers are

given in the rest of this section, except IMASK, ICNT L, and

IFC, which are defined earlier in this data sheet. T he system

control register, DWAIT register, timer registers, HIP control

registers, HIP data registers, and SPORT control registers are

all mapped into data memory locations; that is, you access these

registers by reading and writing data memory locations rather

than register names. T he particular data memory address is

shown with each memory-mapped register.

T he ADC receive and DAC transmit interrupts occur at an

8 kHz rate, indicating when the data registers should be ac-

cessed. On the receive side, the ADC interrupt is generated each

time an A/D conversion cycle is completed and the 16-bit data

word is available in the ADC receive register. On the transmit

side, the DAC interrupt is generated each time an D/A conver-

sion cycle is completed and the DAC transmit register is ready

for the next 16-bit data word.

Both interrupts are generated simultaneously at an 8 kHz rate,

occurring every 3250 instruction cycles with a 13 MHz internal

processor clock. T he interrupts are generated continuously,

starting when the analog interface is powered up by setting the

Register bit values shown on the following pages are the default

bit values after reset. If no values are shown, the bits are indeter-

minate at reset. Reserved bits are shown in gray; these bits

should always be written with zeros.

PROGRAM SEQUENCER

ICNTL

IFC

HOST

INTERFACE

PORT

SSTAT

LOOP

PROGRAM

ROM

4K x 24

IMASK

STACK

DAG 2

DAG 1

PROGRAM

SRAM

2K x 24

DATA

SRAM

2K x 16

MSTAT

ASTAT

CNTR

4 x 18

I0 M0 L0

I1 M1 L1

I2 M2 L2

I3 M3 L3

I4 M4 L4

I5 M5 L5

I6 M6 L6

I7 M7 L7

OWRCNTR

0x3FE0-0x3FE5 DATA

ADSP-21msp59

ONLY

PC

STACK

16 x 14

STATUS

STACK

12 x 25

COUNT

STACK

4 x 14

0x3FE6-0x3FE7 STATUS

0x3FFF

0x3FFE

SYSTEM CONTROL

DM WAIT CONTROL

0x3FE8

HMASK

PMA BUS

14

DMA BUS

PMD BUS

DMD BUS

14

24

PX

16

0x3FEC

DAC

0x3FEE-0x3FEF

0x3FED

ADC

AX0 AX1 AY0 AY1

FLAG

MX0 MX1 MY0 MY1

SI SE SB

RX0 TX0

RX1 TX1

TIMER

0x3FFD TPERIOD

0x3FFC TCOUNT

0x3FFB TSCALE

0x3FFA-0x3FF3

0x3FF2-0x3FEF

ALU

MAC

SHIFTER

SR0 SR1

CONTROL REGISTERS

SPORT 1

POWERDOWN

CONTROL

LOGIC

CONTROL REGISTERS

ANALOG INTERFACE

MR0 MR1 MR2 MF

AR AF

SPORT 0

Figure 9. ADSP-21m sp58/59 Registers

REV. 0

–11–

ADSP-21msp58/59

SSTAT (Read -Only)

ASTAT

7

0

6

0

5

0

4

3

2

0

1

0

7

0

6

5

4

3

2

1

0

1

0

1

0

1

0

1

0

AZ ALU Result Zero

AN ALU Result Negative

AV ALU Overflow

AC ALU Carry

PC Stack Empty

PC Stack Overflow

Count Stack Empty

Count Stack Overflow

Status Stack Empty

Status Stack Overflow

Loop Stack Empty

Loop Stack Overflow

AS ALU X Input Sign

AQ ALU Quotient

MV MAC Overflow

SS Shifter Input Sign

MSTAT

6

0

5

0

4

3

2

1

0

Data Register Bank Select

0 = primary, 1 = secondary

Bit Reverse Mode Enable (DAG1)

ALU Overflow Latch Mode Enable

AR Saturation Mode Enable

MAC Result Placement

0 = fractional, 1 = integer

Timer Enable

Go Mode Enable

System Control Register

0x3FFF

15 14 13 12 11 10

9

8

7

6

5

4

1

3

1

2

1

0

1

0

1

SPORT0 Enable

1 = enabled, 0 = disabled

PWAIT

Program Memory

Wait States

SPORT1 Enable

1 = enabled, 0 = disabled

BWAIT

Boot Wait States

BPAGE

Boot Page Select

SPORT1 Configure

1 = serial port

0 = FI, FO, IRQ0, IRQ1, SCLK

BFORCE

Boot Force Bit

Timer Registers

15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

0x3FFD

0x3FFC

0x3FFB

TPERIOD Period Register

TCOUNT Counter Register

TCOUNT Scaling Register

0

Control Registers

–12–

REV. 0

ADSP-21msp58/59

ROM Enable/Data Memory Wait State

Control Register

0x3FFE

15 14 13 12 11 10

9

8

7

6

1

5

1

4

1

3

1

2

1

0

1

DWAIT3

DWAIT4

DWAIT2

DWAIT1

DWAIT0

ROM enable (ADSP-21msp59)

1 = enable

0 = disable

SPORT0 Multichannel Receive Word Enable Registers

SPORT0 Multichannel Transmit Word Enable Registers

1 = Channel Enabled

0 = Channel Ignored

1 = Channel Enabled

0 = Channel Ignored

0x3FF8

0x3FFA

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

0x3FF7

0x3FF9

15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

SPORT0 Control Register

0x3FF6

15 14 13 12 11 10

9

8

7

6

5

4

0

3

0

2

0

1

0

Multichannel Enable MCE

Internal Serial Clock Generation ISCLK

Receive Frame Sync Required RFSR

Receive Frame Sync Width RFSW

SLEN Serial Word Length

DTYPE Data Format

00 = right justify, zero-fill unused MSBs

01 = right justify, sign extend into unused MSBs

10 = compand using µ-law

11 = compand using A-law

INVRFS Invert Receive Frame Sync

Multichannel Frame Delay MFD

Only If Multichannel Mode Enabled

INVTFS Invert Transmit Frame Sync

(or INVTDV Invert Transmit Data Valid

Only If Multichannel Mode Enabled )

Transmit Frame Sync Required TFSR

Transmit Frame Sync Width TFSW

IRFS Internal Receive Frame Sync Enable

ITFS Internal Transmit Frame Sync Enable

(or MCL Multichannel Length; 1 = 32 words, 0 = 24 words

Only If Multichannel Mode Enabled )

Control Registers

REV. 0

–13–

ADSP-21msp58/59

SPORT0 SCLKDIV

Serial Clock Divide Modulus

0x3FF5

15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

SPORT0 RFSDIV

Receive Frame Sync Divide Modulus

0x3FF4

15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

SPORT0 Autobuffer Control Register

0x3FF3

15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

RBUF

Receive Autobuffering Enable

CLKODIS

CLKOUT Disable Control Bit

TBUF

Transmit Autobuffering Enable

BIASRND

MAC Biased Rounding Control Bit

RMREG

Receive Autobuffer M Register

TIREG

Transmit Autobuffer I Register

RIREG

Receive Autobuffer I Register

TMREG

Transmit Autobuffer M Register

SPORT1 Control Register

0x3FF2

15 14 13 12 11 10

9

8

7

6

5

4

0

3

0

2

0

1

0

Flag Out (Read Only)

Internal Serial Clock Generation ISCLK

Receive Frame Sync Required RFSR

Receive Frame Sync Width RFSW

SLEN Serial Word Length

DTYPE Data Format

00 = right justify, zero-fill unused MSBs

01 = right justify, sign extend into unused MSBs

10 = compand using µ-law

11 = compand using A-law

INVRFS Invert Receive Frame Sync

INVTFS Invert Transmit Frame Sync

IRFS Internal Receive Frame Sync Enable

Transmit Frame Sync Required TFSR

Transmit Frame Sync Width TFSW

ITFS Internal Transmit Frame Sync Enable

Control Registers

–14–

REV. 0

ADSP-21msp58/59

SPORT1 SCLKDIV

Serial Clock Divide Modulus

0x3FF1

15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

SPORT1 RFSDIV

Receive Frame Sync Divide Modulus

0x3FF0

15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

Analog Autobuffer/Powerdown Control Register

0x3FEF

15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

XTALDIS

XTAL Pin Disable During Powerdown

1 = disabled, 0 = enabled

ARBUF

ADC Receive Autobuffer Enable

(XTAL pin should be disabled when

no external crystal is connected)

ATBUF

DAC Transmit Autobuffer Enable

XTALDELAY

Delay Startup From Powerdown 4096 Cycles

1 = delay, 0 = no delay

ARMREG

Receive M Register

(use delay to let internal phase locked

loop or external oscillator stabilize)

ARIREG

Receive I Register

PDFORCE

Powerdown Force

ATMREG

Transmit M Register

1 = force processor to vector to

powerdown interrupt

ATIREG

Transmit I Register

PUCR

Powerup Context Reset

1 = soft reset, 0 = resume execution

HMASK Register

0x3FE8

15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

Host HDR0 Write

Host HDR1 Write

Host HDR2 Write

Host HDR3 Write

Host HDR4 Write

Host HDR5 Write

Host HDR5 Read

Host HDR4 Read

Host HDR3 Read

Host HDR2 Read

Host HDR1 Read

Host HDR0 Read

Interrupt Enables

1 = Enable

0 = Disable

Control Registers

REV. 0

–15–

ADSP-21msp58/59

Analog Control Register

0x3FEE

IG0, IG1

ADC Input Gain (for PGA)

15 14 13 12 11 10

9

8

7

6

5

4

0

3

0

2

0

1

0

Gain

0dB

+6dB

+20dB

+26dB

IG1 IG0

0

1

0

1

0

1

OG2 OG1 OG0

ADC Offset

IG0

ADC Input Gain

IG1

ADC Input Gain

DABY

DAC High Pass Filter Bypass

1 = bypass, 0 = insert

IMS

ADC Input Multiplexer Select

1 = AUX input, 0 = NORM input

ADBY

ADC High Pass Filter Bypass

1 = bypass, 0 = insert

OG2, OG1, OG0

DAC Output Gain (for PGA)

APWD

Analog Interface Powerdown

0 = powerdown, 1 = enable

(set both bits to 1

Gain

+6dB

+3dB

0dB

–3dB

–6dB

–9dB

–12dB

–15dB

IG2 IG1 IG1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

to enable analog interface)

All bits are set to 0 at processor reset.

(Reserved bits 11–15 must always be set to 0)

ADC Receive

15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

DM(0x3FED)

DM(0x3FEC)

DAC Transmit

9

15 14 13 12 11 10

8

7

6

1

0

HIP Data Registers

HDR5

15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

0x3FE5

HDR4

0x3FE4

0x3FE3

0x3FE2

0x3FE1

0x3FE0

HDR3

HDR2

HDR1

HDR0

Control Registers

–16–

REV. 0

ADSP-21msp58/59

HSR6

0x3FE6

15 14 13 12 11 10

9

0

8

7

6

0

5

0

4

0

3

2

1

0

Host HDR0 Write

Host HDR1 Write

Host HDR2 Write

Host HDR3 Write

Host HDR4 Write

Host HDR5 Write

ADSP-21msp58/59 HDR5 Write

ADSP-21msp58/59 HDR4 Write

ADSP-21msp58/59 HDR3 Write

ADSP-21msp58/59 HDR2 Write

ADSP-21msp58/59 HDR1 Write

ADSP-21msp58/59 HDR0 Write

HSR7

0x3FE7

15 14 13 12 11 10

9

0

8

7

6

0

5

0

4

0

3

2

1

0

1

0

ADSP-21msp58/59 HDR0 Write

ADSP-21msp58/59 HDR1 Write

ADSP-21msp58/59 HDR2 Write

ADSP-21msp58/59 HDR3 Write

ADSP-21msp58/59 HDR4 Write

ADSP-21msp58/59 HDR5 Write

Overwrite Mode

Software Reset

Control Registers

INSTRUCTIO N SET D ESCRIP TIO N

AD SP -21m sp58/59 EXTEND ED INSTRUCTIO N SET

T he ADSP-21msp58/59 has a number of additional instruc-

tions beyond the standard ADSP-2100 Family instruction set.

T hese additional instructions and mathematical operations are

described below.

T he ADSP-21msp58/59 assembly language instruction set has

an algebraic syntax that was designed for ease of coding and

readability. T he assembly language, which takes full advantage

of the processor’s unique architecture, offers the following

benefits:

Slow ID LE

Slow IDLE allows slowing the processor’s internal clock by a

factor of 16, 32, 64, or 128 during IDLE. T he instruction

source code is specified as follows:

• T he algebraic syntax eliminates the need to remember cryptic

assembler mnemonics. For example, a typical arithmetic add

instruction, such as AR = AX0 + AY0, resembles a simple

equation.

Syntax:

IDLE (n);

• Every instruction assembles into a single 24-bit word and

executes in a single cycle.

Permissible Values for n

16, 32, 64, 128

•T he syntax is a superset of the ADSP-2100 Family assembly

language and is completely source and object code compatible

with other family members. Programs may, however, need to

be relocated to utilize internal memory and conform to the

ADSP-21msp58/59 interrupt vector and reset vector map.

Exam ples:

IDLE;

IDLE (16);

D escr iption: T he IDLE instruction causes the processor to

wait indefinitely in a low power state until an in-

terrupt occurs. When an unmasked interrupt oc-

curs, it is serviced; execution then continues with

the instruction following the IDLE instruction.

T he optional value provides a “slow idle” fea-

ture; slowing the clock down by the factor set

with the value.

• Sixteen condition codes are available. For conditional jump,

call, return, or arithmetic instructions, the condition can be

checked and the operation executed in the same instruction

cycle.

• Multifunction instructions allow parallel execution of an

arithmetic instruction with up to two fetches and one write to

processor memory space during a single instruction cycle.

Inter r upt Enable and D isable Instr uctions

T he ADSP-21msp58/59 supports an interrupt enable instruc-

tion and interrupt disable instruction. Interrupts are enabled by

default at reset. T he interrupt enable instruction source code is

specified as follows:

Consult the ADSP-2100 Family User’s Manual for a complete

description of the syntax and an instruction set reference.

REV. 0

–17–

ADSP-21msp58/59

Syntax:

ENA INT S;

1024, 1025, 2047, 2048, 2049, 4095, 4096, 4097, 8191, 8192,

8193, 16383, 16384, 16385, 32766, 32767, –1, –2, –3, –4, –5,

–6, –8, –9, –10, –16, –17, –18, –32, –33, –34, –64, –65, –66, –128,

–129, –130, –256, –257, –258, –512, –513, –514, –1024, –1025,

–1026, –2048, –2049, –2050, –4096, –4097, –4098, –8192, –8193,

–8194, –16384, –16385, –16386, –32767, –32768

D escr iption: Executing the ENA INT S instruction allows all

unmasked interrupts to be serviced again.

T he interrupt disable instruction source code is specified as

follows:

Syntax:

DIS INT S;

Exam ples:

IF GE AR = PASS AY0;

IF EQ AF = PASS –1025;

D escr iption: Reset enables interrupt servicing. Executing the

DIS INT S instruction causes all interrupts to be

masked without changing the contents of the

IMASK register. Disabling interrupts does not

affect the autobuffer circuitry, which will operate

normally whether or not interrupts are enabled.

T he disable interrupt instruction masks all user

interrupts including the powerdown interrupt.

D escr iption: T est the optional condition and, if true, pass the

source operand unmodified through the ALU

block and store in the destination location. If the

condition is not true, perform a no-operation.

Omitting the condition performs the pass uncon-

ditionally. T he source operand is contained in

the data registers specified in the instruction or

optional constant.

Extended ALU and Multiplier O per ations

T he following extended computation operations are available

only on the ADSP-21msp58/59 processor. T he term “base in-

struction set” refers to the computations and instructions avail-

able on all ADSP-21xx processors.

The PASS instruction performs the transfer to the

AR register and affect the status flag; this instruc-

tion is different from a register move operation

which does not affect any status flags. PASS 0 is

one method of clearing AR. PASS 0 can also be

combined in a multifunction instruction in con-

junction with memory reads and writes to clear AR.

Additiona l Consta nts for ALU Oper a tions

A new set of numerical constants may be used in all nonmulti-

function ALU operations (except DIVS and DIVQ) using both

X and Y operands. T he instruction source code is specified as

follows:

Note:

T he ALU status flags (in the AST AT register)

are not defined for the execution of this instruc-

tion when using the constant values other than 0,

1, and –1.

Syntax: [IF condition]

AR

AF

= xop function

yop

constant

Permissible xops

AX0, AX1, AR, MR0, MR1, MR2, SR0, SR1

ALU Bit Oper a tions

T he additional constants for ALU operations allow you to code

bit test, set, clear, and toggle operations through careful choice

of the constant and ALU function. For streamlined programming,

the source code for these operations can also be specified as:

Permissible functions

ADD/ADD with CARRY, SUBT RACT X–Y/SUBT RACT X–

Y with BORROW, SUBT RACT Y–X/SUBT RACT Y–X with

BORROW, AND, OR, XOR

Syntax: [IF condition]

AR

AF

=

T ST BIT n of xop;

SET BIT n of xop;

CLBIT n of xop;

T GBIT n of xop;

Permissible yops (base instruction set)

AY0, AY1, AF

Permissible yops and constants (extended instruction set)

AY0, AY1, AF, 0, 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024,

2048, 4096, 8192, 16384, 32767, –2, –3, –5, –9, –17, –33, –65,

–129, –257, –513, –1025, –2049, –4097, –8193, –16385, –32768

Permissible xops

AX0, AX1, AR, MR0, MR1, MR2, SR0, SR1

Permissible n Values (0 = LSB)

0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15

Exam ples:

AR = AR+1;

AR = MR1 - 33;

IF GT AF = AX1 OR 16;

Exam ples:

AF=T ST BIT 5 of AR;

IF NE JUMP SET ;

/* JUMP T O SET IF BIT IS SET */

D escr iption: T est the optional condition and, if true, perform

the specified function. If false then perform a no-

operation. Omitting the condition performs the

function unconditionally. T he operands are con-

tained in the data registers specified in the in-

Definitions of Operations

T ST BIT is an AND operation with a 1 in the selected bit

SET BIT is an OR operation with a 1 in the selected bit

CLBIT is an AND operation with a 0 in the selected bit

T GBIT is an XOR operation with a 1 in the selected bit

struction or optionally a constant may be used.

Additiona l Consta nts for ALU PASS Oper a tion

A new set of numerical constants may be used in the PASS in-

struction. T he instruction source code is specified as follows:

Result-Fr ee ALU Oper a tions

T he result-free ALU operations allow the generation of condi-

tion flags based on an ALU operation but discard the result.

T he source code for the instruction is specified as follows:

Syntax: [IF condition]

AR

AF

= pass

yop

constant

Syntax:

NONE = <ALU>;

Permissible yops (base instruction set)

AY0, AY1, AF

where <ALU> is any unconditional ALU operation of the 21xx

base instruction set (except DIVS or DIVQ). (Note that the addi-

tional constant ALU operations of the ADSP-2171/2181 ex-

tended instruction set are not allowed.)

Permissible yops and constants (extended instruction set)

AY0, AY1, AF, 0, 1, 2, 3, 4, 5, 7, 8, 9, 15, 16, 17, 31, 32, 33,

63, 64, 65, 127, 128, 129, 255, 256, 257, 511, 512, 513, 1023,

–18–

REV. 0

ADSP-21msp58/59

Exam ples:

NONE = AX0 – AY0;

NONE = PASS SR0;

be masked without changing the contents of the

IMASK register. Disabling interrupts does not af-

fect the autobuffer circuitry, which will operate

normally whether or not interrupts are enabled.

The disable interrupt instruction masks all user

interrupts including the powerdown interrupt.

D escr iption: Perform the designated ALU operation, set the

condition flags, then discard the result value.

T his allows the testing of register values without

disturbing the AR or AF register values.

MAC Oper a tions

CIRCUIT D ESIGN CO NSID ERATIO NS

A modified MAC operation allows additional type 9 instruc-

tions. T he conditional ALU/MAC instruction has been modi-

fied to allow the X operand to be used as the Y operand as well.

T his allows a single cycle X², and also ∑X²operations.

T he following sections discuss interfacing analog signals to the

ADSP-21msp58/59.

Analog Signal Input

Figure 10 shows the recommended input circuit for the analog in-

put pin (either VIN_NORMor VIN_AUX). The circuit of Figure 10

implements a first-order low-pass filter (R1C1) with a 3 dB point

less than 40 kHz. This is the only filter required external to the

processor to prevent aliasing of the sampled signal. Since the

ADSP-21msp58/59’s sigma-delta ADC uses a highly oversampled

approach that transfers the bulk of the anti-aliasing filtering into the

digital domain, the off-chip anti-aliasing need only be of low order.

T he new MAC instructions allow the use of any xop as both the

X and Y operands. T he instructions source code is specified as

follows:

Syntax: [IF condition] MR

=

[MR +]

[MR –]

xop * yop (UU);

xop (SS) ;

MF

(RND);

Permissible xops

AR, MR0, MR1, MR2, MX0, MX1, SR0, SR1

C2

R1

VIN

NORM

Exam ple:

Note:

IF LT MR=MR+ SR0 * SR0 (SS);

MUX

AUX

C1

INPUT

SOURCE

PGA

Both X operators must be the same register.

C3

DECOUPLE

Bia sed Rounding

A new mode has been added to allow biased rounding in addi-

tion to the normal unbiased rounding. When the BIASRND bit

is set to 0 the normal unbiased rounding operations occur.

When the BIASRND bit is set to 1, biased rounding occurs in-

stead of the normal unbiased rounding. When operating in bi-

ased rounding mode all rounding operations with MR0 set to

0x8000 will round up, rather than only rounding odd MR1

values up. For example:

ADSP-21msp58/59

STAR

GROUND

Figure 10. Recom m end Analog Input Circuit

T he on-chip ADC PGA can be used when there is not enough

gain in the input circuit. T he PGA gain is set by bits 9 and 0

(IG1, IG0) of the processor’s analog control register. T he gain

must be chosen to ensure that a full-scale input signal (at R1 in

Figure 10) produces a signal level at the input to the sigma-delta

modulator of the ADC that does not exceed VIN_MAX(refer to

the “Analog Interface Electrical Characteristics” specifications).

MR value before RND

00-0000-8000

00-0001-8000

00-0000-8001

00-0001-8001

00-0000-7FFF

biased RND result

00-0001-8000

00-0002-8000

00-0001-8001

00-0002-8001

00-0000-7FFF

unbiased RND result

00-0000-8000

00-0002-8000

00-0001-8001

00-0002-8001

00-0000-7FFF

VIN_NORMand VIN_AUXare biased at the Internal Reference Volt-

age (nominal of 2.5 V) of the ADSP-21msp58/59, which lets the

analog section of the processor operate from a single supply.

T he input signal should be ac-coupled with an external capaci-

tor (C2). T he value of C2 is determined by the input resistance

of the analog input (VIN_NORM, VIN_AUX) (200 kΩ) and the de-

sired cutoff frequency. T he cutoff frequency should be ≤30 Hz.

T he following equation should be used to determine the values

of R1, C1, and C2; R1 should be ≤2.2 kΩ. C2 should be ≥0.027

µF; C3 should be equal to C2.

00-0001-7FFF

T his mode only has an effect when the MR0 register contains

0x8000, all other rounding operation work normally. T his mode

was added to allow more efficient implementation of bit speci-

fied algorithms which specify biased rounding such as the GSM

speech compression routines. Unbiased rounding is preferred

for most algorithms.

Note:

BIASRND bit is bit twelve of the SPORT 0

Autobuffer Control register.

1

C2 =

2 π f R_IN

Inter r upt Ena ble

T he ADSP-21msp58/59 supports an interrupt enable instruc-

tion. Interrupts are enabled by default at reset. T he instruction

source code is specified as follows:

R_IN= ADSP-21msp58/59 input resistance (200 kΩ)

f₁= cutoff frequency <30 Hz

1

R1 =

2 π f₂C1

Syntax:

ENA INT S;

D escr iption:

Executing the ENA INT S instruction allows

all unmasked interrupts to be serviced again.

R1 ≤ 2.2 kΩ

f₂> 20 kHz < 40 kHz*

Inter r upt D isable

T he ADSP-21msp58/59 supports an interrupt disable instruc-

tion. T he instruction source code is specified as follows:

1

C1 =

2 π f₂R1

For optimum ADC performance, C1 should be an NPO type

capacitor.

Syntax:

DIS INT S;

D escr iption: Reset enables interrupt servicing. Executing the

DIS INT S instruction causes all interrupts to

*If minimum (<0.1 dB) rolloff at 4 kHz is desired, f₂should be set to 40 kHz.

REV. 0

–19–

ADSP-21msp58/59

Analog Signal O utput

AP P LICATIO N EXAMP LES

T he differential analog output (VOUT_P, VOUT_N) is produced

by an on-chip differential amplifier which is part of the processor’s

analog interface. T he differential amplifier will meet dynamic

specifications for loads greater than 2 kΩ (R_L≥ 2 kΩ) and has a

maximum differential output voltage swing of ±3.156 V peak-to-

peak (3.17 dBm0). T he DAC will drive loads smaller than 2 kΩ,

but with degraded dynamic performance. T he differential out-

put can be ac-coupled directly to a load or dc-coupled to an ex-

ternal amplifier.

T he ADSP-21msp58/59 is ideal for speech processing applica-

tions where high performance for analog and digital circuitry is

required, but board space is severely limited. T he cellular radio

handset is one application. Here the ADSP-21msp58/59 can

digitize the speech, then perform compression algorithms that

sufficiently reduce the bit rate for transmission in a limited radio

bandwidth.

D EFINITIO N O F SP ECIFICATIO NS

Absolute Gain

Figure 11 shows a simple circuit providing a differential output

with ac coupling. T he capacitor of this circuit (C_OUT) is op-

tional; if used, its value can be chosen as follows:

Absolute gain is a measure of converter gain for a known signal.

Absolute gain is measured with a 1.0 kHz sine wave at 0 dBm0.

T he absolute gain specification is used as a reference for the

gain tracking error specification.

1

C_OUT

=

(60 π) R_L

Gain Tr acking Er r or

Gain tracking error measures changes in converter output for

different signal levels relative to an absolute signal level. T he

absolute signal level is 1.0 kHz at 0 dBm0. Gain tracking error

at 0 dBm0 is 0 dB by definition.

C

OUT

VOUT

P

R

ADSP-21msp58/59

L

OUT

VOUT

N

SNR + TH D

Signal-to-noise ratio plus total harmonic distortion is defined to

be the ratio of the rms value of the measured input signal to the

rms sum of all other spectral components in the frequency range

300 Hz–3400 Hz, including harmonics but excluding dc.

Figure 11. Exam ple Circuit for Differential Output with

AC Coupling

T he VOUT_Pand VOUT_Noutputs must be used as differential

outputs (do not use either as a single-ended output). Figure 12

shows an example circuit which can be used to convert the dif-

ferential output to a single-ended output. T he circuit uses a dif-

ferential-to-single-ended amplifier, the Analog Devices SSM2141.

Inter m odulation D istor tion

With inputs consisting of sine waves at two frequencies, fa and

fb, any active device with nonlinearities will create distortion

products at sum and difference frequencies of mfa ± nfb where

m, n = 0, 1, 2, 3, etc. Intermodulation terms are those which

neither m nor n are equal to zero. T he second order terms in-

clude (fa + fb) and (fa – fb), while the third order terms include

(2fa + fb), (2fa – fb), (fa + 2fb), and (fa – 2fb).

+12V

0.1µF

ADSP-21msp58/59

7

GND

A

5

1

VOUT

P

Idle Channel Noise

V

SSM2141

0.1µF

OUT

VOUT

N

Idle channel noise is defined as the total signal energy measured

at the output of the device when the input is grounded (mea-

sured in the frequency range 300 Hz–3400 Hz).

4

GND

A

GND

A

–12V

Cr osstalk

Crosstalk is defined as the ratio of the rms value of a full-scale

signal appearing on one channel to the rms value of the same

signal that couples onto the adjacent channel. Crosstalk is ex-

pressed in dB.

Figure 12. Exam ple Circuit for Single-Ended Output

Voltage Refer ence Filter Capacitance

Figure 13 shows the recommended reference filter capacitor

connections. T he capacitor grounds should be connected to the

same star ground point shown in Figure 10.

P ower Supply Rejection

Power supply rejection measures the susceptibility of a device to

a signal on the power supply. Power supply rejection is mea-

sured by modulating a signal on the power supply and measur-

ing the signal at the output (relative to 0 dB). Power supply

rejection is defined as the ratio of the rms value of the modula-

tion signal to the rms value of the same signal in the ADC/DAC

channel.

BUF

V

REF

REF_FILTER

VOLTAGE

REFERENCE

10µF

0.1µF

ADSP-21msp58/59

Gr oup D elay

Group delay is defined as the derivative of radian phase with re-

spect to radian frequency, ∂φ(ω)/∂ω. Group delay is a measure

of the average delay of a system as a function of frequency. A

linear system with a constant group delay has a linear phase re-

sponse. T he deviation of group delay away from a constant indi-

cates the degree of nonlinear phase response of the system.

STAR

GROUND

Figure 13. Voltage Reference Filter Capacitor

–20–

REV. 0

ADSP-21msp58/59

ADSP-21msp58/59–SPECIFICATIONS

RECOMMENDED OPERATING CONDITIONS

B Grade

P aram eter

Min

Max

Unit

V_DD

T _AMB

Supply Voltage

Ambient Operating T emperature

4.50

–40

5.50

+85

V

°C

See “Environmental Conditions” for information on thermal specifications.

ELECTRICAL CHARACTERISTICS

P aram eter

Test Conditions

Min

Max

Unit

V_IH

V_IL

V_OH

Hi-Level Input Voltage^{1, 2}

Hi-Level CLKIN Voltage

Lo-Level Input Voltage^{1, 3}

Hi-Level Output Voltage^{1, 4, 5}

@ V_DD= max

@ V_DD= min

@ V_DD= min,

I_OH= –0.5 mA

@ V_DD= min,

I_OH= –100 µA⁶

@ V_DD= min,

I_OL= 2 mA

@ V_DD= max,

V_IN= V_DDmax

@ V_DD= max,

V_IN= 0 V

@ V_DD= max,

V_IN= V_DDmax⁸

@ V_DD= max,

V_IN= 0 V⁸

@ V_DD= max,

Codec Inactive

@ V_DD= max,

V_CC= max

2.0

2.2

V

0.8

2.4

V

V_DD– 0.3

V

V_OL

I_IH

Lo-Level Output Voltage^{1, 4, 5}

Hi-Level Input Current³

0.4

10

18

92

V

µA

mA

I_IL

Lo-Level Input Current³

I_OZH

I_OZL

I_DD

T ristate Leakage Current⁷

Digital Supply Current (Idle)^{6, 9}

Digital Supply Current (Dynamic)^{9, 10}

Digital Supply Current (Powerdown)⁹

@ V_DD= max, See

ADSP-2100 Family User’s

Manual, Chapter 9

Codec Active

@ V_IN= 2.5 V,

f_IN= 1.0 MHz,

T_AMB= 25°C

@ V_IN= 2.5 V,

f_IN= 1.0 MHz,

T_AMB= 25°C

100

18

µA

mA

I_CC

C_I

Analog Supply Current (Dynamic)⁹

Input Pin Capacitance^{3, 11, 12}

8

pF

C_O

Output Pin Capacitance^{7, 11, 12}

NOT ES

¹Bidirectional pins: D0-D23, RFS0, RFS1, SCLK0, SCLK1, T FS0, T FS1, HD0-HD7/HAD0-HAD7.

²Input only pins: RESET, IRQ2, BR, MMAP, DR0, DR1, HSEL, HSIZE, BMODE, HMD0, HMD1, HRD/HWR, HWR/HDS, PWD, HA2/ALE, HA1-0.

³Input only pins: CLKIN, RESET, IRQ2, BR, MMAP, DR0, DR1, HSEL, HSIZE, BMODE, HMD0, HMD1, HRD/HWR, HWR/HDS, PWD, HA2/ALE, HA1-0.

⁴Output pins: BG, PMS, DMS, BMS, RD, WR, A0-A13, DT 0, DT 1, CLKOUT , HACK, FL0.

⁵Although specified for T T L outputs, all ADSP-21msp58/59 outputs are CMOS-compatible and will drive to V _DDand GND, assuming no dc loads.

⁶Idle refers to ADSP-21msp58/59 state of operation during IDLE instruction. Deasserted pins are driven to either V _DDor GND. Refer to chart in back for lower

IDLE currents.

⁷T hree-statable pins: A0-A13, D0-D23, PMS, DMS, BMS, RD, WR, DT 0, DT 1, SCLK0, SCLK1, T FS0, T FS1, RFS0, RSF1, HD0-HD7/HAD0-HAD7.

⁸0 V on BR, CLKIN Active (to force three-state condition).

⁹Current reflects the digital portion of device operating with no output loads and a 2 k Ω load on the analog output (VOUT _P, VOUT _N).

10

t

= 76.92 ns, CODEC active, 80% execution type 1 instructions, with random data. For typical figures for digital and analog supply currents, refer to “Power

CK

Dissipation” section.

¹¹Guaranteed but not tested.

¹²Output pin capacitance is the capacitive load for any three-stated output pin.

Specifications subject to change without notice.

REV. 0

–21–

ADSP-21msp58/59

ABSO LUTE MAXIMUM RATINGS^*

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

Input Voltage . . . . . . . . . . . . . . . . . . . . . –0.3 V to V_DD+ 0.3 V

Output Voltage Swing . . . . . . . . . . . . . . –0.3 V to V_DD+ 0.3 V

Operating T emperature Range (Ambient) . . . . –40°C to +85°C

Storage T emperature Range . . . . . . . . . . . . . –65°C to +150°C

Lead T emperature (5 sec) . . . . . . . . . . . . . . . . . . . . . . +280°C

^*Stresses above those listed under “Absolute Maximum Ratings” may cause

permanent damage to the device. T hese are stress ratings only, and functional

operation of the device at these or any other conditions above those indicated in the

operational sections of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect device reliability.

ESD SENSITIVITY

T he ADSP-21msp58/59 is an ESD (electrostatic discharge) sensitive device. Electrostatic charges

readily accumulate on the human body and equipment and can discharge without detection.

Permanent damage may occur to devices subjected to high energy electrostatic discharges.

WARNING!

T he ADSP-21msp58/59 features proprietary ESD protection circuitry to dissipate high energy

discharges (Human Body Model).

ESD SENSITIVE DEVICE

Proper ESD precautions are recommended to avoid performance degradation or loss of function-

ality. Unused devices must be stored in conductive foam or shunts, and the foam should be

discharged to the destination before devices are removed.

TIMING PARAMETERS

MEMO RY REQ UIREMENTS

GENERAL NO TES

T his chart links common memory device specification

names and ADSP-21msp58/59 timing parameters for your

convenience.

Use the exact timing information given. Do not attempt to de-

rive parameters from the addition or subtraction of others. While

addition or subtraction would yield meaningful results for an in-

dividual device, the values given in this data sheet reflect statisti-

cal variations and worst cases. Consequently, you cannot

meaningfully add up parameters to derive longer times.

Com m on

P aram eter

Nam e

Mem ory D evice

Specification Nam e

Function

TIMING NO TES

t_ASW

t_AW

A0-A13, DMS, PMS

Setup before WR Low

A0-A13, DMS, PMS Setup Address Setup

before WR Deasserted

A0-A13, DMS, PMS

Hold after WR Deasserted

Address Setup to

Write Start

Switching characteristics specify how the processor changes its

signals. You have no control over this timing; it is dependent on

the internal design. T iming requirements apply to signals that

are controlled outside the processor, such as the data input for a

read operation.

to Write End

Address Hold T ime

t_WRA

t_DW

t_DH

t_RDD

t_AA

Data Setup before WR High Data Setup T ime

T iming requirements guarantee that the processor operates cor-

rectly with another device. Switching characteristics tell you

what the device will do under a given circumstance. Also, use the

switching characteristics to ensure any timing requirement of a

device connected to the processor (such as memory) is satisfied.

Data Hold after WR High

RD Low to Data Valid

A0-A13, DMS, PMS,

BMS to Data Valid

Data Hold T ime

OE to Data Valid

Address Access T ime

–22–

REV. 0

ADSP-21msp58/59

FREQ UENCY RESP O NSE

AD C

Max

(dB)

AD C

Min

(dB)

D AC

Max

(dB)

D AC

Min

(dB)

Frequency

(H z)

0+

75

150

300

1000

2000

3000

3400

3700

3850

4000

–60.00

–25.00

+0.266

+0.272

+0.000

+0.050

–0.200

–0.300

–0.375

–25.00

–60.00

N/A

–60.00

–25.00

+0.015

+0.030

+0.000

+0.050

–0.050

–0.090

–0.120

–25.00

–60.00

N/A

–0.134

–0.128

+0.000

–0.350

–0.600

–0.700

–0.775

N/A

–0.185

–0.170

+0.000

–0.200

–0.300

–0.340

–0.370

N/A

NOT ES

All specifications relative to absolute gain @ 1.0 kHz.

ADC and DAC high-pass filters inserted.

ADC specifications do not include RC filter attenuation and assumes an ac coupled input (see “Analog T est Conditions”

for RC filter details).

NO ISE & D ISTO RTIO N

P aram eter

Min

Max

Unit

Test Condition

ADC Intermodulation Distortion

DAC Intermodulation Distortion

ADC Idle Channel Noise

DAC Idle Channel Noise

ADC Crosstalk¹

–60

–70

dB

dBm0

dB

m, n = 1 and 2; f_a= 984; f_b= 1047

65

72

–65

–55

ADC input signal level: 1.0 kHz, 0 dBm0

DAC input at idle.

DAC Crosstalk¹

dB

ADC input signal level: analog ground

DAC output signal level: 1.0 kHz, 0 dBm0

Input signal level at V_CCand V_DDpins:

1.0 kHz, 100 mV p-p sine wave

Input signal level at V_CCand V_DDpins:

1.0 kHz, 100 mV p-p sine wave

300 Hz–3000 Hz

1.0 kHz, 0 dBm0

ADC Power Supply Rejection¹

DAC Power Supply Rejection¹

ADC Group Delay¹

DAC Group Delay¹

ADC SNR and T HD

DAC SNR and T HD

1

ms

dB

65

72

NOT E

¹Guaranteed but not tested.

100

80

60

40

20

ADC SNR + THD

80

DAC SNR + THD

PEAK @

72dB

PEAK @

65dB

60

40

20

0

20dB

SLOPE =

20dBm0

0

–60

–50

–40

–30

–20

–10

0

10

–60

–50

–40

–30

–20

–10

0

10

3.17

V

– dBm0

V

– dBm0

IN

Figure 14. SNR + THD vs. V_IN

–23–

REV. 0

ADSP-21msp58/59

ANALO G INTERFACE ELECTRICAL CH ARACTERISTICS

Sym bol

P aram eter

Min

Typ

Max

Unit

ADC

R_I

VIN_MAX

DAC:

R_O

V_OOFF

Input Resistance^{1, 2}at VIN_NORM, VIN_AUX

Maximum Input Range^{1, 3}

200

kΩ

V p-p

3.156

400

Output Resistance^{1, 4}

Output DC Offset⁵

2.5

Ω

mV

–400

V_O

Maximum Voltage Output Swing (p-p) Across R_L

Single-Ended¹

3.156

6.312

V

Differential¹

R_L

Load Resistance^{1, 4}

2

kΩ

Reference Buffer:

Voltage Reference (V_REF

Output Impedence¹

Capacitive Load¹

PSRR¹

)

2.25

2.75

10

V

Ω

nf

dB

250

55

NOT ES

T est conditions for all analog interface tests: ADC PGA bypassed, DAC PGA set to 0 dB gain, with 2 k Ω load on analog output (VOUT _P, VOUT _N), V_CC= 5.0 V.

¹Guaranteed but not tested.

²Varies with PGA setting.

³At input to sigma-delta modulator of ADC.

⁴At VOUT _P, VOUT _N

.

⁵Between VOUT _Pand VOUT _N

.

GAIN

P aram eter

Min

Typ

Max

Unit

Test Conditions

ADC Absolute Gain

–0.7

–0.1

–0.6

–0.75

–0.1

–0.6

0

0.7

0.1

0.6

0.75

0.1

0.6

dBm0

1.0 kHz, 0 dBm0

1.0 kHz, +3 to –50 dBm0

1.0 kHz

1.0 kHz, 0 dBm0

1.0 kHz, +3 to –50 dBm0

1.0 kHz

ADC Gain T racking Error

ADC PGA Relative Gain

DAC Absolute Gain

DAC Gain T racking Error

DAC PGA Relative Gain

–24–

REV. 0

ADSP-21msp58/59

P aram eter

Min

Max

Unit

Clock Signals

t_CKis defined as 0.5 t_CKI.T he ADSP-21msp58/59 uses

an input clock with a quency equal to half the instruction

rate; a 13 MHz input clock (which is equivalent to 76.92 ns)

yields a 38.46 ns processor cycle (equivalent to 26 MHz).

t_CKvalues within the range of 0.5 t_CKIperiod should be

substituted for all relevant timing parameters to obtain

specification value. Example: t_CKH= 0.5t_CK– 7 ns

= 0.5 (38.46 ns) – 7 ns = 12.23 ns.

T iming Requirement:

t_CKI

t_CKIL

t_CKIH

CLKIN Period

CLKIN Width Low

CLKIN Width High

76.92

20

125

ns

Switching Characteristic:

t_CKL

t_CKH

t_CKOH

CLKOUT Width Low

CLKOUT Width High

CLKIN High to CLKOUT High

0.5t_CK– 7

0

ns

20

Contr ol Signals

T iming Requirement:

t_RSP

1

RESET Width Low

5t_CK

ns

NOT ES

¹Applies after power-up sequence is complete. Internal phase lock loop requires no more than 2000 CLKIN cycles assuming stable CLKIN (not including

crystal oscillator start-up time).

t_CKI

t_CKIH

CLKIN

t_CKIL

t_CKOH

t_CKH

CLKOUT

t_CKL

Figure 15. Clock Signals

REV. 0

–25–

ADSP-21msp58/59

P aram eter

Min

Max

Unit

Inter r upts and Flags

T iming Requirement:

t_IFS

t_IFH

IRQx or FI Setup before CLKOUT Low^{1, 2, 3}

0.25t_CK+ 15

0.25t_CK

ns

IRQx or FI Hold after CLKOUT High^{1, 2, 3}

Switching Characteristics:

t_FOH

Flag Output Hold after CLKOUT Low⁴

t_FOD

Flag Output Delay from CLKOUT Low⁴

0.5t_CK– 7

ns

0.5t_CK+ 5

NOT ES

¹If IRQx and FI inputs meet t_IFSand t_IFHsetup/hold requirements, they will be recognized during the current clock cycle; otherwise the signals will be recognized on

the following cycle. (Refer to “Interrupt Controller Operation” in the Program Control chapter of the User’s Manual for further information on interrupt servicing.)

²Edge-sensitive interrupts require pulse widths greater than 10 ns; level-sensitive interrupts must be held low until serviced.

³IRQx = IRQ0, IRQ1, and IRQ2.

⁴Flag Output = FL0 and FO.

CLKOUT

t_FOD

t_FOH

FLAG

OUTPUTS

t_IFH

IRQ

FI

x

t_IFS

Figure 16. Interrupts and Flags

–26–

REV. 0

ADSP-21msp58/59

P aram eter

Min

Max

Unit

Bus Request/Gr ant

T iming Requirement:

t_BH

t_BS

BR Hold after CLKOUT High¹

0.25t_CK+ 2

0.25t_CK+ 17

ns

BR Setup before CLKOUT Low¹

Switching Characteristic:

t_SD

CLKOUT High to DMS, PMS, BMS,

0.25t_CK+ 10

ns

RD, WR Disable

t_SDB

t_SE

DMS, PMS, BMS, RD, WR

Disable to BG Low

BG High to DMS, PMS, BMS,

RD, WR Enable

DMS, PMS, BMS, RD, WR

Enable to CLKOUT High

0

ns

0

t_SEC

0.25t_CK– 7

NOT ES

¹BR is an asynchronous signal. If BR meets the setup/hold requirements, it will be recognized during the current clock cycle; otherwise the signal will be recognized

on the following cycle. Refer to the ADSP-2100 Family User’s Manual for BR/BG cycle relationships.

t_BH

CLKOUT

BR

t_BS

CLKOUT

PMS, DMS,

BMS,RD,

t_SEC

WR

t_SD

BG

t_SDB

t_SE

Figure 17. Bus Request–Bus Grant

REV. 0

–27–

ADSP-21msp58/59

P aram eter

Min

Max

Unit

Mem or y Read

T iming Requirement:

t_RDD

t_AA

t_RDH

RD Low to Data Valid

A0-A13, PMS, DMS, BMS to Data Valid

Data Hold from RD High

0.5t_CK– 11 + w

0.75t_CK– 12 + w

ns

0

Switching Characteristic:

t_RP

RD Pulse Width

CLKOUT High to RD Low

A0-A13, PMS, DMS, BMS Setup before RD Low

A0-A13, PMS, DMS, BMS Hold after RD Deasserted

RD High to RD or WR Low

0.5t_CK– 5 + w

0.25t_CK– 5

0.25t_CK– 6

0.25t_CK– 3

0.5t_CK– 5

ns

t_CRD

t_ASR

t_RDA

t_RWR

0.25t_CK+ 7

NOT E

w = wait states × t_CK

.

CLKOUT

A0 – A13

DMS, PMS,

BMS

t_RDA

RD

t_RP

t_ASR

t_CRD

t_RWR

D

t_ROD

t_RDH

t_AA

WR

Figure 18. Mem ory Read

–28–

REV. 0

ADSP-21msp58/59

P aram eter

Min

Max

Unit

Mem or y Wr ite

Switching Characteristic:

t_DW

t_DH

t_WP

t_WDE

t_ASW

t_DDR

t_CWR

t_AW

Data Setup before WR High

Data Hold after WR High

WR Pulse Width

WR Low to Data Enabled

A0-A13, DMS, PMS Setup before WR Low

Data Disable before WR or RD Low

CLKOUT High to WR Low

A0-A13, DMS, PMS, Setup before WR Deasserted

A0-A13, DMS, PMS Hold after WR Deasserted

WR High to RD or WR Low

0.5t_CK– 7 + w

0.25t_CK– 2

0.5t_CK– 5 + w

0

0.25t_CK– 6

0.25t_CK– 5

0.75t_CK– 9 + w

0.25t_CK– 3

0.5t_CK– 5

ns

0.25t_CK+ 7

t_WRA

t_WWR

NOT E

w = wait states × t_CK.

CLKOUT

A0 – A13

DMS, PMS

t_WRA

WR

t_WWR

t_WP

t_ASW

t_AW

t_DH

t_DDR

t_CWR

D

t_WDE

t_DW

RD

Figure 19. Mem ory Write

REV. 0

–29–

ADSP-21msp58/59

P aram eter

Min

Max

Unit

Ser ial P or ts

T iming Requirement:

t_SCK

t_SCS

t_SCH

t_SCP

SCLK Period

50

4

7

ns

DR/T FS/RFS Setup before SCLK Low

DR/T FS/RFS Hold after SCLK Low

SCLK_inWidth

20

Switching Characteristic:

t_CC

CLKOUT High to SCLK_out

SCLK High to DT Enable

SCLK High to DT Valid

T FS/RFS_outHold after SCLK High

T FS/RFS_outDelay from SCLK High

DT Hold after SCLK High

T FS(Alt) to DT Enable

T FS(Alt) to DT Valid

0.25t_CK

0

0.25t_CK+ 10

ns

t_SCDE

t_SCDV

t_RH

15

0

t_RD

t_SCDH

t_{T DE}

t_{T DV}

t_SCDD

t_RDV

0

14

15

SCLK High to DT Disable

RFS (Multichannel, Frame Delay Zero) to DT Valid

CLKOUT

t_CC

t_SCK

SCLK

DR

t_SCP

t_SCS

t_SCH

t_SCP

RFS

IN

TFS

IN

t_RD

t_RH

RFS

OUT

TFS

t_SCDV

t_SCDE

t_SCDD

t_SCDH

DT

t_TDE

t_TDV

TFS

alternate

frame mode

t_RDV

RFS

multichannel

mode, frame

delay 0 (MFD = 0)

Figure 20. Serial Ports

–30–

REV. 0

ADSP-21msp58/59

P aram eter

Min

Max

Unit

H ost Inter face P or t

Separate Data and Address (HMD1 = 0)

Read Strobe and Write Strobe (HMD0 = 0)

T iming Requirement:

t_HSU

HA2-0 Setup before Start of Write or Read^{1, 2}

5

3

ns

t_HDSU

t_HWDH

t_HH

Data Setup before End of Write³

Data Hold after End of Write³

HA2-0 Hold after End of Write or Read^{3, 4}

Read or Write Pulse Width⁵

t_HRWP

20

Switching Characteristic:

t_HSHK

t_HKH

HACK Low after Start of Write or Read^{1, 2}

0

15

ns

HACK Hold after End of Write or Read^{3, 4}

Data Enabled after Start of Read²

Data Valid after Start of Read²

t_HDE

t_HDD

t_HRDH

t_HRDD

18

7

Data Hold after End of Read⁴

0

Data Disabled after End of Read⁴

NOT ES

¹Start of Write = HWR Low and HSEL Low.

²Start of Read = HRD Low and HSEL Low.

³End of Write = HWR High or HSEL High.

⁴End of Read = HRD High or HSEL High.

⁵Read Pulse Width = HRD Low and HSEL Low, Write Pulse Width = HWR Low and HSEL Low.

HA2–0

ADDRESS

t_HRWP

HSEL

t_HSU

HOST WRITE CYCLE

t_HH

HWR

HACK

t_HKH

t_HSHK

DATA

t_HDSU

HD7–0

t_HWDH

HA2–0

ADDRESS

t_HRWP

HSEL

t_HSU

HOST READ CYCLE

t_HH

HRD

HACK

t_HSHK

t_HKH

DATA

HD7–0

t_HDE

t_HDD

t_HRDH

t_HRDD

Figure 21. Host Interface Port (HMD1 = 0, HMD0 = 0)

REV. 0

–31–

ADSP-21msp58/59

P aram eter

Min

Max

Unit

H ost Inter face P or t

Separate Data and Address (HMD1 = 0)

Read Strobe and Write Strobe (HMD0 = 1)

T iming Requirement:

t_HSU

HA2-0, HRW Setup before Start of Write or Read¹

5

3

ns

t_HDSU

t_HWDH

t_HH

Data Setup before End of Write²

Data Hold after End of Write²

HA2-0, HRW Hold after End of Write or Read²

Read or Write Pulse Width³

t_HRWP

20

Switching Characteristic:

t_HSHK

t_HKH

HACK Low after Start of Write or Read¹

0

15

ns

HACK Hold after End of Write or Read²

Data Enabled after Start of Read¹

Data Valid after Start of Read¹

t_HDE

t_HDD

t_HRDH

t_HRDD

18

7

Data Hold after End of Read²

0

Data Disabled after End of Read²

NOT ES

¹Start of Write or Read = HDS Low and HSEL Low.

²End of Write or Read = HDS High and HSEL High.

³Read or Write Pulse Width = HDS Low and HSEL Low.

HA2–0

ADDRESS

t_HRWP

HSEL

t_HSU

HOST WRITE CYCLE

HRW

t_HH

HDS

HACK

t_HSHK

t_HKH

DATA

t_HDSU

HD7–0

t_HWDH

HA2–0

HSEL

HRW

ADDRESS

t_HRWP

t_HSU

HOST READ CYCLE

t_HH

HDS

HACK

t_HSHK

t_HKH

HD7–0

DATA

t_HDE

t_HDD

t_HRDH

t_HRDD

Figure 22. Host Interface Port (HMD1 = 0, HMD0 =1)

–32–

REV. 0

ADSP-21msp58/59

P aram eter

Min

Max

Unit

H ost Inter face P or t

Multiplexed Data and Address (HMD1 = 1)

Read Strobe and Write Strobe (HMD0 = 0)

T iming Requirement:

t_HALP

t_HASU

t_HAH

t_HALS

t_HDSU

t_HWDH

t_HRWP

ALE Pulse Width

10

5

2

10

5

3

ns

HAD15-0 Address Setup, before ALE Low

HAD15-0 Address Hold after ALE Low

Start of Write or Read after ALE Low^{1, 2}

HAD15-0 Data Setup before End of Write³

HAD15-0 Data Hold after End of Write³

Read or Write Pulse Width⁵

20

Switching Characteristic:

t_HSHK

t_HKH

t_HDE

t_HDD

t_HRDH

t_HRDD

HACK Low after Start of Write or Read^{1, 2}

0

15

ns

HACK Hold after End of Write or Read^{3, 4}

HAD15-0 Data Enabled after Start of Read²

HAD15-0 Data Valid after Start of Read²

HAD15-0 Data Hold after End of Read

HAD15-0 Data Disabled after End of Read⁴

18

7

0

NOT ES

¹Start of Write = HWR Low and HSEL Low.

²Start of Read = HRD Low and HSEL Low.

³End of Write = HWR High or HSEL High.

⁴End of Read = HRD High or HSEL High.

⁵Read Pulse Width = HRD Low and HSEL Low, Write Pulse Width = HWR Low and HSEL Low.

ALE

t_HALP

t_HRWP

HSEL

HWR

t_HALS

HOST WRITE CYCLE

t_HKH

t_HSHK

t_HASUt_HAH

HACK

HAD7–0

ADDRESS

DATA

t_HDSU

t_HWDH

ALE

t_HALP

t_HRWP

HSEL

HRD

t_HALS

HOST READ CYCLE

t_HSHK

t_HKH

HACK

t_HASUt_HAH

ADDRESS

t_HDE

t_HRDH

HAD7–0

DATA

t_HDD

t_HRDD

Figure 23. Host Interface Port (HMD1 = 1, HMD0 = 0)

REV. 0

–33–

ADSP-21msp58/59

P aram eter

Min

Max

Unit

H ost Inter face P or t

Multiplexed Data and Address (HMD1 = 1)

Read Strobe and Write Strobe (HMD0 = 1)

T iming Requirement:

t_HALP

t_HASU

t_HAH

t_HALS

t_HSU

t_HDSU

t_HWDH

t_HH

ALE Pulse Width

10

5

2

10

5

3

20

ns

HAD15-0 Address Setup before ALE Low

HAD15-0 Address Hold after ALE Low

Start of Write or Read after ALE Low¹

HRW Setup before Start of Write or Read¹

HAD15-0 Data Setup before End of Write²

HAD15-0 Data Hold after End of Write²

HRW Hold after End of Write or Read²

Read or Write Pulse Width³

t_HRWP

Switching Characteristic:

t_HSHK

t_HKH

t_HDE

t_HDD

HACK Low after Start of Write or Read¹

0

15

ns

HACK Hold after End of Write or Read²

HAD15-0 Data Enabled after Start of Read¹

HAD15-0 Data Valid after Start of Read¹

HAD15-0 Data Hold after End of Read²

HAD15-0 Data Disabled after End of Read²

18

7

t_HRDH

t_HRDD

0

NOT ES

¹Start of Write or Read = HDS Low and HSEL Low.

²End of Write or Read = HDS High and HSEL High.

³Read or Write Pulse Width = HDS Low and HSEL Low.

ALE

t_HALP

t_HRWP

HSEL

t_HALS

t_HH

HOST WRITE CYCLE

HRW

t_HSU

HDS

t_HKH

t_HSHK

t_HASU

t_HAH

HACK

HAD7–0

ADDRESS

DATA

t_HDSU

t_HWDH

ALE

t_HALP

t_HALS

t_HRWP

HSEL

HRW

t_HH

t_HSU

HOST READ CYCLE

HDS

t_HKH

t_HSHK

HACK

t_HASUt_HAH

ADDRESS

t_HDE

t_HRDH

HAD7–0

DATA

t_HDD

t_HRDD

Figure 24. Host Interface Port (HMD1 = 1, HMD0 = 1)

–34–

REV. 0

ADSP-21msp58/59

ENVIRO NMENTAL CO ND ITIO NS

Ambient T emperature Rating:

frequency, the codec performance changes and the performance

specifications cannot be guaranteed. T he codec filter character-

istics, however, scale approximately linearly with frequency.

T_AMB= T _CASE– (PD × θ_{C A}

)

T_CASE= Case T emperature in °C

PD = Power Dissipation in W

θ_{C A}= T hermal Resistance (Case-to-Ambient)

θ_JA= T hermal Resistance (Junction-to-Ambient)

θ_JC= T hermal Resistance (Junction-to-Case)

If the codec is disabled, then the processor can be used at any

allowed input frequency. T he power consumption of the ADSP-

21msp58/59 at these frequencies is shown in Figure 25.

1

POWER, INTERNAL

550

500

450

400

350

300

250

200

150

550

480mW 500

450

INTERNAL

P ackage

θ_JA

θ_JC

θ_CA

(80% NOMINAL LOADING)

CODEC INACTIVE

MAX VALUES

T QFP

50°C/W

2°C/W

48°C/W

391mW

400

V

= 5.5V

DD

350

P O WER D ISSIP ATIO N

310mW

T o determine total power dissipation in a specific application,

the following equation should be applied for each output:

300

250

200

150

= 5.0V

DD

V

2

C × V_DD× f

191mW

154mW

V

= 4.5V

C = load capacitance, f = output switching frequency.

DD

Exam ple:

118mW

100

50

100

50

In an application where external data memory is used and no

other outputs are active, power dissipation is calculated as

follows:

2

6

10

14

18

22

26

30

1/t – MHz

CK

2

POWER, IDLE

Assumptions:

110

100

90

100mW

•

External data memory is accessed every cycle with 50% of the

address pins switching.

IDLE 0

CODEC INACTIVE

MAX VALUES

•

External data memory writes occur every other cycle with

50% of the data pins switching.

83mW

V

= 5.5V

DD

80

•

Each address and data pin has a 10 pF total load at the pin.

70

T he application operates at V_DD= 5.0 V and t_CK= 76.92 ns.

= 5.0V

DD

V

2

Total Power Dissipation = P_INT+ (C × V_DD× f )

60

69mW

57mW

49mW

42mW

P_INT= internal power dissipation from Power vs. Frequency

50

graph (Figure 25).

V

= 4.5V

18

DD

2

40

(C × V_DD× f ) is calculated for each output:

30

6

10

14

22

26

30

# of

P ins × C

1/t – MHz

2

CK

× V_{D D}

× f

3

POWER, IDLE n MODES

Address, DMS

Data Output, WR

RD

8

9

1

× 10 pF × 5²

V

× 26 MHz

× 13 MHz

× 26 MHz

=

52 mW

30 mW

4 mW

6 mW

92 mW

70

60

50

40

30

20

× 10 pF × 5²

V

IDLEs @ 5.0V

CODEC INACTIVE

TYPICAL VALUES

65mW

CLKOUT

T otal power dissipation for this example is P_INT+ 92 mW.

IDLE (16)

Typical P ower Consum ption

IDLE (32)

IDLE (64)

IDLE (128)

37mW

35mW

T he typical power consumption can be calculated from the fol-

lowing data, taken at 5.0 V and +25°C. Dynamic V_DDdata was

taken while executing 80% type 1 multifunction instructions, on

random data.

29mW

21mW

20mW

Parameter

T yp

19 mA

13 mA

10

I_DDDigital Supply Current (Idle, Codec Powered Up)

I_DDDigital Supply Current (Idle)

6

10

14

18

22

26

30

1/t – MHz

CK

VALID FOR ALL TEMPERATURE GRADES.

1

I_DDDigital Supply Current (Dynamic, Codec Powered Up) 83 mA

POWER REFLECTS DEVICE OPERATING WITH NO OUTPUT LOADS.

I_DDDigital Supply Current (Dynamic)

I_DDDigital Supply Current (Powerdown)

I_CCAnalog Supply Current (Dynamic)

78 mA

10 µA

15 mA

2

IDLE REFERS TO ADSP-21msp58/59 STATE OF OPERATION DURING EXECUTION OF

IDLE INSTRUCTION. DEASSERTED PINS ARE DRIVEN TO EITHER V OR GND.

DD

POWER REFLECTS DEVICE OPERATING WITH CLKOUT DISABLED.

TYPICAL POWER DISSIPATION AT 5.0V V DURING EXECUTION OF IDLE n

3

DD

INSTRUCTION (CLOCK FREQUENCY REDUCTION). POWER REFLECTS DEVICE

OPERATING WITH CLKOUT DISABLED.

Analog Devices recommends that the ADSP-21msp58/59

is used with a 13 MH z input clock. Below this input clock

Figure 25. Power vs. Internal Processor Frequency

REV. 0

–35–

ADSP-21msp58/59

CAP ACITIVE LO AD ING

TEST CO ND ITIO NS

Figures 26 and 27 show the capacitive loading characteristics of

the ADSP-21msp58/59.

D igital

Figure 28 shows the voltage reference levels and Figure 29

shows the equivalent device loading for the ac measurements.

28

24

3.0V

1.5V

0.0V

INPUT

V

= 4.5V

DD

20

16

12

8

2.0V

1.5V

0.8V

OUTPUT

Figure 28. Voltage Reference Levels for AC Measure-

m ents (Except Output Enable/Disable)

4

I

OL

0

25

50

75

C

100

– pF

125

150

175

L

TO

OUTPUT

+1.5V

Figure 26. Typical Output Rise Tim e vs. Load Capacitance,

C_L(at Maxim um Am bient Operating Tem perature)

50pF

+14

I

OH

+12

+10

Figure 29. Equivalent Device Loading for AC Measure-

m ents (Including All Fixtures)

+8

+6

Analog

+4

Figure 30 shows the analog test conditions.

+2

NOMINAL

–2

1.0µF

2.2kΩ

DECOUPLE

REF_CAP

VIN

NORM

1.0µF

2200pF

NPO

–4

25

50

75

C

100

– pF

125

150

175

1.0µF

2.2kΩ

L

VIN

AUX

10µF

0.1µF

2200pF

NPO

Figure 27. Typical Output Valid Delay or Hold vs. Load

Capacitance, C_L(at Maxim um Am bient Operating

Tem perature)

Figure 30. Analog Test Conditions

–36–

REV. 0

ADSP-21msp58/59

O utput D isable Tim e

O utput Enable Tim e

Output pins are considered to be disabled when they have

stopped driving and started a transition from the measured out-

put high or low voltage to a high impedance state. T he output

disable time (t_DIS) is the difference of t_MEASUREDand t_DECAY, as

shown in the Output Enable/Disable diagram. T he time is the

interval from when a reference signal reaches a high or low volt-

age level to when the output voltages have changed by 0.5 V

from the measured output high or low voltage. T he decay time,

Output pins are considered to be enabled when that have made

a transition from a high-impedance state to when they start driv-

ing. T he output enable time (t_ENA) is the interval from when a

reference signal reaches a high or low voltage level to when the

output has reached a specified high or low trip point, as shown

in the Output Enable/Disable diagram. If multiple pins (such as

the data bus) are enabled, the measurement value is that of the

first pin to start driving.

t

_DECAY, is dependent on the capacitative load, C_L, and the cur-

rent load, i_L, on the output pin. It can be approximated by the

following equation:

REFERENCE

SIGNAL

t_MEASURED

t_ENA

C_L• 0.5V

t_DECAY

=

t_DIS

V

OH

i_L

(MEASURED)

V

(MEASURED)

OUTPUT

OH

V

(MEASURED) –0.5V

(MEASURED) +0.5V

OH

2.0V

1.0V

from which

V

OL

(MEASURED)

t_DIS= t_MEASURED– t_DECAY

OL

V

OL

(MEASURED)

t_DECAY

is calculated. If multiple pins (such as the data bus) are dis-

abled, the measurement value is that of the last pin to stop

driving.

OUTPUT STOPS

DRIVING

OUTPUT STARTS

HERE

HIGH-IMPEDANCE STATE. TEST CONDITIONS CAUSE

THIS VOLTAGE LEVEL TO BE APPROXIMATELY 1.5V.

Figure 31. Output Enable/Disable

REV. 0

–37–

ADSP-21msp58/59

P IN CO NFIGURATIO N

100-Lead Thin P lastic Quad Flatpack (TQFP )

100

76

1

75

D15

D16

VINNORM

DECOUPLE

VINAUX

REF_FILTER

GNDA

D17

D18

D19

D20

MMAP

RESET

IRQ2

D21

D22

D23

HMD0

VDD

GND

PMS

DMS

BMS

RD

HMD1

HACK

FL0

TOP VIEW

(PINS DOWN)

SCLK1

DR1/FI

RFS1/IRW0

TFS1/IRQ1

DT1/FO

GND

WR

HD7

HD6

HD5

HD4

HD3

HD2

HD1

HD0

HA2/ALE

SCLK0

DR0

FRS0

TFS0

DT0

VDD

A13

25

51

26

50

–38–

REV. 0

ADSP-21msp58/59

100-Lead Thin P lastic Quad Flatpack (TQFP ) P inout

TQFP

P in

TQFP

P in

TQFP

P in

TQFP

P in

Num ber

Nam e

Num ber

Nam e

Num ber

Nam e

Num ber

Nam e

1

2

3

4

5

6

7

8

D15

D16

D17

D18

D19

D20

D21

D22

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

HA1

HA0

HSEL

HWR/HDS

HRD/HRW

CLKOUT

VDD

GND

XT AL

CLKIN

GND

VDD

A0

A1

A2

A3

A4

A5

A6

A7

A8

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

A13

VDD

DT 0

T FS0

RFS0

DR0

SCLK0

GND

DT 1/FO

T FS1/IRQ1

RFS1/IRQ0

DR1/FI

SCLK1

FL0

HACK

HMD1

HMD0

IRQ2

RESET

MMAP

GNDA

REF_FILT ER

VINAUX

DECOUPLE

VINNORM

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

VCC

VREF

VOUT P

VOUT N

GND

BMODE

PWD

BR

BG

D0

D1

D2

D3

D4

D5

D6

D7

GND

D8

9

D23

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

VDD

GND

PMS

DMS

BMS

RD

WR

HD7

HD6

HD5

HD4

HD3

HD2

HD1

HD0

HA2/ALE

D9

D10

D11

D12

D13

D14

A9

A10

A11

A12

REV. 0

–39–

ADSP-21msp58/59

O UTLINE D IMENSIO NS

D imensions shown in millimeters and (inches)

100-Lead Metr ic Thin P lastic Q uad Flat P ack (TQ FP )

16.25 (0.640)

SQ

15.75 (0.620)

14.05 (0.553)

13.95 (0.549)

1.60 (0.063)

MAX

SQ

0.75 (0.030)

0.50 (0.019)

100

1

76

75

SEATING

PLANE

TOP VIEW

(PINS DOWN)

25

51

50

0.1 (0.004)

26

0.15 (0.006)

0.05 (0.002)

0.27 (0.011)

0.17 (0.007)

0.56 (0.022)

0.44 (0.018)

0.057 (1.45)

0.053 (1.35)

12.06 (0.475) SQ

O RD ERING GUID E*

Am bient

Tem perate

Range

Instruction

Rate

(MIP S)

P ackage

D escription

P ackage

O ption

P art Num ber

ADSP-21msp58BST -104

–40°C to +85°C

26

100-Lead T QFP

ST -100

*Refer to the section titled “Ordering Procedure for ADSP-21msp59 ROM Processors” for information about ordering ROM coded parts.

–40–

REV. 0


型号：	ADSP-21MSP58BST-104
厂家：	ADI
描述：	DSP Microcomputers DSP微型计算机计算机
文件：	总40页 (文件大小：373K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADSP-21MSP58BST-104 [ADI]

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