ADSP-BF533SBBZ500 [ADI]
Blackfin Embedded Processor; Blackfin嵌入式处理器型号: | ADSP-BF533SBBZ500 |
厂家: | ADI |
描述: | Blackfin Embedded Processor |
文件: | 总56页 (文件大小:672K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Blackfin
Embedded Processor
®
a
ADSP-BF531/ADSP-BF532/ADSP-BF533
External Memory Controller with glueless support for
SDRAM, SRAM, FLASH, and ROM
Flexible memory booting options from SPI and external
FEATURES
Up to 600 MHz high performance Blackfin processor
Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs,
40-bit Shifter
memory
RISC-like register and instruction model for ease of pro-
gramming and compiler-friendly support
Advanced debug, trace, and performance monitoring
0.8 V to 1.2 V core VDD with on-chip voltage regulation
3.3 V and 2.5 V tolerant I/O
PERIPHERALS
Parallel Peripheral Interface (PPI)/GPIO, supporting
ITU-R 656 video data formats
Two dual-channel, full duplex synchronous serial ports, sup-
porting eight stereo I2S channels
12-channel DMA controller
160-ball mini-BGA, 169-ball lead free PBGA, and 176-lead
LQFP packages
SPI compatible port
Three Timer/Counters with PWM support
UART with support for IrDA®
Event Handler
Real-Time Clock
Watchdog Timer
Debug/JTAG interface
On-chip PLL capable of 1x to 63x frequency multiplication
Core Timer
MEMORY
Up to 148K bytes of on-chip memory:
16K bytes of instruction SRAM/Cache
64K bytes of instruction SRAM
32K bytes of data SRAM/Cache
32K bytes of data SRAM
4K bytes of scratchpad SRAM
Two dual-channel memory DMA controllers
Memory Management Unit providing memory protection
EVENT
JTAG TEST AND
WATCHDOG TIMER
REAL-TIME CLOCK
CONTROLLER/
EMULATION
CORE TIMER
VOLTAGE
REGULATOR
B
UART PORT
IRDA®
L1
L1
DATA
MMU
INSTRUCTION
MEMORY
MEMORY
TIMER0, TIMER1,
TIMER2
CORE / SYSTEM BUS INTERFACE
PPI / GPIO
DMA
CONTROLLER
SERIAL PORTS (2)
SPI PORT
BOOT ROM
EXTERNAL PORT
FLASH, SDRAM
CONTROL
Figure 1. Functional Block Diagram
Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703
www.analog.com
© 2004 Analog Devices, Inc. All rights reserved.
ADSP-BF531/ADSP-BF532/ADSP-BF533
TABLE OF CONTENTS
General Description ................................................. 3
Portable Low Power Architecture ............................. 3
System Integration ................................................ 3
ADSP-BF531/2/3 Processor Peripherals ..................... 3
Blackfin Processor Core .......................................... 3
Memory Architecture ............................................ 4
DMA Controllers .................................................. 8
Real-Time Clock ................................................... 8
Watchdog Timer .................................................. 9
Timers ............................................................... 9
Serial Ports (SPORTs) ............................................ 9
Serial Peripheral Interface (SPI) Port ......................... 9
UART Port ........................................................ 10
Programmable Flags (PFx) .................................... 10
Parallel Peripheral Interface ................................... 10
Dynamic Power Management ................................ 11
Voltage Regulation .............................................. 12
Clock Signals ..................................................... 12
Booting Modes ................................................... 13
Instruction Set Description ................................... 14
Development Tools ............................................. 14
Designing an Emulator Compatible Processor Board ... 15
Pin Descriptions .................................................... 16
Specifications ........................................................ 19
Recommended Operating Conditions ...................... 19
Electrical Characteristics ....................................... 19
Absolute Maximum Ratings .................................. 20
ESD Sensitivity ................................................... 20
Timing Specifications ........................................... 21
Clock and Reset Timing ..................................... 22
Asynchronous Memory Read Cycle Timing ............ 23
Asynchronous Memory Write Cycle Timing ........... 24
SDRAM Interface Timing .................................. 25
External Port Bus Request and Grant Cycle Timing .. 26
Parallel Peripheral Interface Timing ...................... 27
Serial Ports ..................................................... 28
Serial Peripheral Interface (SPI) Port
—Master Timing ........................................... 33
Serial Peripheral Interface (SPI) Port
—Slave Timing ............................................. 34
Universal Asynchronous Receiver-Transmitter
(UART) Port—Receive and Transmit Timing ...... 35
Programmable Flags Cycle Timing ....................... 36
Timer Cycle Timing .......................................... 37
JTAG Test And Emulation Port Timing ................. 38
Output Drive Currents ......................................... 39
Power Dissipation ............................................... 41
Test Conditions .................................................. 42
Environmental Conditions .................................... 45
160-Lead BGA Pinout ............................................. 46
169-Ball PBGA Pinout ............................................. 49
176-Lead LQFP Pinout ............................................ 51
Outline Dimensions ................................................ 53
Ordering Guide ..................................................... 56
REVISION HISTORY
Revision 0: Initial Version
Rev. 0
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ADSP-BF531/ADSP-BF532/ADSP-BF533
GENERAL DESCRIPTION
The ADSP-BF531/2/3 processors are members of the Blackfin
family of products, incorporating the Analog Devices/Intel
Micro Signal Architecture (MSA). Blackfin processors combine
a dual-MAC state-of-the-art signal processing engine, the
advantages of a clean, orthogonal RISC-like microprocessor
instruction set, and single-instruction, multiple-data (SIMD)
multimedia capabilities into a single instruction-set
architecture.
ADSP-BF531/2/3 PROCESSOR PERIPHERALS
The ADSP-BF531/2/3 processor contains a rich set of peripher-
als connected to the core via several high bandwidth buses,
providing flexibility in system configuration as well as excellent
overall system performance (see the functional block diagram in
Figure 1 on Page 1). The general-purpose peripherals include
functions such as UART, Timers with PWM (Pulse-Width
Modulation) and pulse measurement capability, general-pur-
pose flag I/O pins, a Real-Time Clock, and a Watchdog Timer.
This set of functions satisfies a wide variety of typical system
support needs and is augmented by the system expansion capa-
bilities of the part. In addition to these general-purpose
The ADSP-BF531/2/3 processors are completely code and pin
compatible, differing only with respect to their performance and
on-chip memory. Specific performance and memory configura-
tions are shown in Table 1.
peripherals, the ADSP-BF531/2/3 processor contains high speed
serial and parallel ports for interfacing to a variety of audio,
video, and modem codec functions; an interrupt controller for
flexible management of interrupts from the on-chip peripherals
or external sources; and power management control functions
to tailor the performance and power characteristics of the pro-
cessor and system to many application scenarios.
Table 1. Processor Comparison
ADSP-BF531 ADSP-BF532 ADSP-BF533
Maximum
400 MHz
400 MHz
600 MHz
1200 MMACs
Performance
800 MMACs
800 MMACs
Instruction
SRAM/Cache
16K bytes
16K bytes
16K bytes
16K bytes
32K bytes
32K bytes
16K bytes
64K bytes
32K bytes
All of the peripherals, except for general-purpose I/O, Real-
Time Clock, and timers, are supported by a flexible DMA struc-
ture. There is also a separate memory DMA channel dedicated
to data transfers between the processor's various memory
spaces, including external SDRAM and asynchronous memory.
Multiple on-chip buses running at up to 133 MHz provide
enough bandwidth to keep the processor core running along
with activity on all of the on-chip and external peripherals.
Instruction
SRAM
Data
SRAM/Cache
Data SRAM
Scratchpad
32K bytes
4K bytes
4K bytes
4K bytes
The ADSP-BF531/2/3 processor includes an on-chip voltage
regulator in support of the ADSP-BF531/2/3 processor
Dynamic Power Management capability. The voltage regulator
provides a range of core voltage levels from a single 2.25 V to
3.6 V input. The voltage regulator can be bypassed at the user's
discretion.
By integrating a rich set of industry-leading system peripherals
and memory, Blackfin processors are the platform of choice for
next-generation applications that require RISC-like program-
mability, multimedia support, and leading-edge signal
processing in one integrated package.
PORTABLE LOW POWER ARCHITECTURE
BLACKFIN PROCESSOR CORE
Blackfin processors provide world-class power management
and performance. Blackfin processors are designed in a low
power and low voltage design methodology and feature
Dynamic Power Management, the ability to vary both the volt-
age and frequency of operation to significantly lower overall
power consumption. Varying the voltage and frequency can
result in a substantial reduction in power consumption, com-
pared with just varying the frequency of operation. This
translates into longer battery life for portable appliances.
As shown in Figure 2 on Page 5, the Blackfin processor core
contains two 16-bit multipliers, two 40-bit accumulators, two
40-bit ALUs, four video ALUs, and a 40-bit shifter. The compu-
tation units process 8-bit, 16-bit, or 32-bit data from the
register file.
The compute register file contains eight 32-bit registers. When
performing compute operations on 16-bit operand data, the
register file operates as 16 independent 16-bit registers. All
operands for compute operations come from the multiported
register file and instruction constant fields.
SYSTEM INTEGRATION
The ADSP-BF531/2/3 processors are highly integrated system-
on-a-chip solutions for the next generation of digital communi-
cation and consumer multimedia applications. By combining
industry-standard interfaces with a high performance signal
processing core, users can develop cost-effective solutions
quickly without the need for costly external components. The
system peripherals include a UART port, an SPI port, two serial
ports (SPORTs), four general-purpose timers (three with PWM
capability), a real-time clock, a watchdog timer, and a Parallel
Peripheral Interface.
Each MAC can perform a 16-bit by 16-bit multiply in each
cycle, accumulating the results into the 40-bit accumulators.
Signed and unsigned formats, rounding, and saturation are
supported.
The ALUs perform a traditional set of arithmetic and logical
operations on 16-bit or 32-bit data. In addition, many special
instructions are included to accelerate various signal processing
tasks. These include bit operations such as field extract and pop-
ulation count, modulo 232 multiply, divide primitives,
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ADSP-BF531/ADSP-BF532/ADSP-BF533
saturation and rounding, and sign/exponent detection. The set
of video instructions includes byte alignment and packing oper-
ations, 16-bit and 8-bit adds with clipping, 8-bit average
operations, and 8-bit subtract/absolute value/accumulate (SAA)
operations. Also provided are the compare/select and vector
search instructions.
The Blackfin processor assembly language uses an algebraic syn-
tax for ease of coding and readability. The architecture has been
optimized for use in conjunction with the C/C++ compiler,
resulting in fast and efficient software implementations.
MEMORY ARCHITECTURE
The ADSP-BF531/2/3 processor views memory as a single uni-
fied 4G byte address space, using 32-bit addresses. All resources,
including internal memory, external memory, and I/O control
registers, occupy separate sections of this common address
space. The memory portions of this address space are arranged
in a hierarchical structure to provide a good cost/performance
balance of some very fast, low latency on-chip memory as cache
or SRAM, and larger, lower cost and performance off-chip
memory systems. See Figure 3 on Page 5, Figure 4 on Page 5,
and Figure 5 on Page 6.
For certain instructions, two 16-bit ALU operations can be per-
formed simultaneously on register pairs (a 16-bit high half and
16-bit low half of a compute register). By also using the second
ALU, quad 16-bit operations are possible.
The 40-bit shifter can perform shifts and rotates and is used to
support normalization, field extract, and field deposit
instructions.
The program sequencer controls the flow of instruction execu-
tion, including instruction alignment and decoding. For
program flow control, the sequencer supports PC relative and
indirect conditional jumps (with static branch prediction), and
subroutine calls. Hardware is provided to support zero-over-
head looping. The architecture is fully interlocked, meaning that
the programmer need not manage the pipeline when executing
instructions with data dependencies.
The L1 memory system is the primary highest performance
memory available to the Blackfin processor. The off-chip mem-
ory system, accessed through the External Bus Interface Unit
(EBIU), provides expansion with SDRAM, flash memory, and
SRAM, optionally accessing up to 132M bytes of physical
memory.
The address arithmetic unit provides two addresses for simulta-
neous dual fetches from memory. It contains a multiported
register file consisting of four sets of 32-bit Index, Modify,
Length, and Base registers (for circular buffering), and eight
additional 32-bit pointer registers (for C-style indexed stack
manipulation).
The memory DMA controller provides high bandwidth data-
movement capability. It can perform block transfers of code or
data between the internal memory and the external memory
spaces.
Internal (On-Chip) Memory
Blackfin processors support a modified Harvard architecture in
combination with a hierarchical memory structure. Level 1 (L1)
memories are those that typically operate at the full processor
speed with little or no latency. At the L1 level, the instruction
memory holds instructions only. The two data memories hold
data, and a dedicated scratchpad data memory stores stack and
local variable information.
The ADSP-BF531/2/3 processor has three blocks of on-chip
memory providing high bandwidth access to the core.
The first is the L1 instruction memory, consisting of up to
80K bytes SRAM, of which 16K bytes can be configured as a
four-way set-associative cache. This memory is accessed at full
processor speed.
The second on-chip memory block is the L1 data memory, con-
sisting of up to two banks of up to 32K bytes each. Each memory
bank is configurable, offering both cache and SRAM functional-
ity. This memory block is accessed at full processor speed.
In addition, multiple L1 memory blocks are provided, offering a
configurable mix of SRAM and cache. The Memory Manage-
ment Unit (MMU) provides memory protection for individual
tasks that may be operating on the core and can protect system
registers from unintended access.
The third memory block is a 4K byte scratchpad SRAM which
runs at the same speed as the L1 memories, but is only accessible
as data SRAM and cannot be configured as cache memory.
The architecture provides three modes of operation: User mode,
Supervisor mode, and Emulation mode. User mode has
restricted access to certain system resources, thus providing a
protected software environment, while Supervisor mode has
unrestricted access to the system and core resources.
External (Off-Chip) Memory
The External Bus interface can be used with both asynchronous
devices such as SRAM, FLASH, EEPROM, ROM, and I/O
devices, and synchronous devices such as SDRAMs. The bus
width is always 16 bits. A1 is the least significant address of a
16-bit word. 8-bit peripherals should be addressed as if they
were 16-bit devices, where only the lower 8 bits of data should
be used.
The Blackfin processor instruction set has been optimized so
that 16-bit opcodes represent the most frequently used instruc-
tions, resulting in excellent compiled code density. Complex
DSP instructions are encoded into 32-bit opcodes, representing
fully featured multifunction instructions. Blackfin processors
support a limited multi-issue capability, where a 32-bit instruc-
tion can be issued in parallel with two 16-bit instructions,
allowing the programmer to use many of the core resources in a
single instruction cycle.
The PC133-compliant SDRAM controller can be programmed
to interface to up to 128M bytes of SDRAM. The SDRAM con-
troller allows one row to be open for each internal SDRAM
bank, for up to four internal SDRAM banks, improving overall
system performance.
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ADSP-BF531/ADSP-BF532/ADSP-BF533
ADDRESS ARITHMETIC UNIT
SP
FP
P5
P4
P3
P2
P1
P0
I3
I2
I1
I0
L3
L2
L1
L0
B3
B2
B1
B0
M3
M2
M1
M0
DAG0
DAG 1
SEQUENCER
ALIGN
DECODE
R7 R7.H
R6 R6.H
R5 R5.H
R4 R4.H
R3 R3.H
R7.L
R6.L
R5.L
R4.L
R3.L
LD0 32 BITS
LD1 32 BITS
SD 32 BITS
LOOP BUFFER
16
16
8
8
8
8
CONTROL
UNIT
R2 R2.H
R1 R1.H
R2.L
R1.L
BARREL
SHIFTER
R0 R0.H
R0.L
40
40
A 0
A1
DATA ARITHMETIC UNIT
Figure 2. Blackfin Processor Core
0xFFFF FFFF
0xFFE0 0000
0xFFC0 0000
0xFFB0 1000
0xFFB0 0000
0xFFA1 4000
0xFFA1 0000
0xFFA0 0000
0xFF90 8000
0xFF90 4000
0xFF90 0000
0xFF80 8000
0xFF80 4000
0xFF80 0000
0xEF00 0000
0x2040 0000
0x2030 0000
0x2020 0000
0x2010 0000
0x2000 0000
0x0800 0000
0x0000 0000
0xFFFF FFFF
0xFFE0 0000
0xFFC0 0000
0xFFB0 1000
0xFFB0 0000
0xFFA1 4000
CORE MMR REGISTERS (2M BYTE)
SYSTEM MMR REGISTERS (2M BYTE)
RESERVED
CORE MMR REGISTERS (2M BYTE)
SYSTEM MMR REGISTERS (2M BYTE)
RESERVED
SCRATCHPAD SRAM (4K BYTE)
RESERVED
SCRATCHPAD SRAM (4K BYTE)
RESERVED
INSTRUCTION SRAM / CACHE (16K BYTE)
INSTRUCTION SRAM (64K BYTE)
RESERVED
INSTRUCTION SRAM / CACHE (16K BYTE)
INSTRUCTION SRAM (32K BYTE)
0xFFA1 0000
0xFFA0 8000
0xFFA0 0000
0xFF90 8000
0xFF90 4000
0xFF80 8000
0xFF80 4000
RESERVED
DATA BANK B SRAM / CACHE (16K BYTE)
DATA BANK B SRAM (16K BYTE)
RESERVED
RESERVED
DATA BANK B SRAM / CACHE (16K BYTE)
RESERVED
DATA BANK A SRAM / CACHE (16K BYTE)
DATA BANK A SRAM (16K BYTE)
DATA BANK A SRAM / CACHE (16K BYTE)
RESERVED
RESERVED
0xEF00 0000
0x2040 0000
0x2030 0000
0x2020 0000
0x2010 0000
0x2000 0000
0x0800 0000
0x0000 0000
RESERVED
RESERVED
ASYNC MEMORY BANK 3 (1M BYTE)
ASYNC MEMORY BANK 2 (1M BYTE)
ASYNC MEMORY BANK 1 (1M BYTE)
ASYNC MEMORY BANK 0 (1M BYTE)
RESERVED
ASYNC MEMORY BANK 3 (1M BYTE)
ASYNC MEMORY BANK 2 (1M BYTE)
ASYNC MEMORY BANK 1 (1M BYTE)
ASYNC MEMORY BANK 0 (1M BYTE)
RESERVED
SDRAM MEMORY (16M BYTE TO 128M BYTE)
SDRAM MEMORY (16M BYTE TO 128M BYTE)
Figure 3. ADSP-BF533 Internal/External Memory Map
Figure 4. ADSP-BF532 Internal/External Memory Map
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ADSP-BF531/ADSP-BF532/ADSP-BF533
Event Handling
0xFFFF FFFF
CORE MMR REGISTERS (2M BYTE)
0xFFE0 0000
SYSTEM MMR REGISTERS (2M BYTE)
0xFFC0 0000
The event controller on the ADSP-BF531/2/3 processor handles
all asynchronous and synchronous events to the processor. The
ADSP-BF531/2/3 processor provides event handling that sup-
ports both nesting and prioritization. Nesting allows multiple
event service routines to be active simultaneously. Prioritization
ensures that servicing of a higher priority event takes prece-
dence over servicing of a lower priority event. The controller
provides support for five different types of events:
RESERVED
0xFFB0 1000
SCRATCHPAD SRAM (4K BYTE)
0xFFB0 0000
RESERVED
0xFFA1 4000
INSTRUCTION SRAM / CACHE (16K BYTE)
0xFFA1 0000
RESERVED
0xFFA0 C000
• Emulation – An emulation event causes the processor to
enter emulation mode, allowing command and control of
the processor via the JTAG interface.
INSTRUCTION SRAM (16K BYTE)
0xFFA0 8000
RESERVED
0xFFA0 0000
RESERVED
0xFF90 8000
RESERVED
0xFF90 4000
RESERVED
0xFF80 8000
DATA BANK A SRAM / CACHE (16K BYTE)
0xFF80 4000
RESERVED
0xEF00 0000
RESERVED
0x2040 0000
• Reset – This event resets the processor.
• Non-Maskable Interrupt (NMI) – The NMI event can be
generated by the software watchdog timer or by the NMI
input signal to the processor. The NMI event is frequently
used as a power-down indicator to initiate an orderly shut-
down of the system.
ASYNC MEMORY BANK 3 (1M BYTE)
0x2030 0000
ASYNC MEMORY BANK 2 (1M BYTE)
0x2020 0000
ASYNC MEMORY BANK 1 (1M BYTE)
0x2010 0000
ASYNC MEMORY BANK 0 (1M BYTE)
0x2000 0000
RESERVED
0x0800 0000
SDRAM MEMORY (16M BYTE TO 128M BYTE)
0x0000 0000
• Exceptions – Events that occur synchronously to program
flow (i.e., the exception will be taken before the instruction
is allowed to complete). Conditions such as data alignment
violations and undefined instructions cause exceptions.
• Interrupts – Events that occur asynchronously to program
flow. They are caused by input pins, timers, and other
peripherals, as well as by an explicit software instruction.
Each event type has an associated register to hold the return
address and an associated return-from-event instruction. When
an event is triggered, the state of the processor is saved on the
supervisor stack.
Figure 5. ADSP-BF531 Internal/External Memory Map
The asynchronous memory controller can be programmed to
control up to four banks of devices with very flexible timing
parameters for a wide variety of devices. Each bank occupies a
1M byte segment regardless of the size of the devices used, so
that these banks will only be contiguous if each is fully popu-
lated with 1M byte of memory.
The ADSP-BF531/2/3 processor Event Controller consists of
two stages, the Core Event Controller (CEC) and the System
Interrupt Controller (SIC). The Core Event Controller works
with the System Interrupt Controller to prioritize and control all
system events. Conceptually, interrupts from the peripherals
enter into the SIC, and are then routed directly into the general-
purpose interrupts of the CEC.
I/O Memory Space
Blackfin processors do not define a separate I/O space. All
resources are mapped through the flat 32-bit address space.
On-chip I/O devices have their control registers mapped into
memory-mapped registers (MMRs) at addresses near the top of
the 4G byte address space. These are separated into two smaller
blocks, one of which contains the control MMRs for all core
functions, and the other of which contains the registers needed
for setup and control of the on-chip peripherals outside of the
core. The MMRs are accessible only in supervisor mode and
appear as reserved space to on-chip peripherals.
Core Event Controller (CEC)
The CEC supports nine general-purpose interrupts (IVG15–7),
in addition to the dedicated interrupt and exception events. Of
these general-purpose interrupts, the two lowest-priority inter-
rupts (IVG15–14) are recommended to be reserved for software
interrupt handlers, leaving seven prioritized interrupt inputs to
support the peripherals of the ADSP-BF531/2/3 processor.
Table 2 describes the inputs to the CEC, identifies their names
in the Event Vector Table (EVT), and lists their priorities.
Booting
System Interrupt Controller (SIC)
The ADSP-BF531/2/3 processor contains a small boot kernel,
which configures the appropriate peripheral for booting. If the
ADSP-BF531/2/3 processor is configured to boot from boot
ROM memory space, the processor starts executing from the
on-chip boot ROM. For more information, see Booting Modes
on Page 13.
The System Interrupt Controller provides the mapping and
routing of events from the many peripheral interrupt sources to
the prioritized general-purpose interrupt inputs of the CEC.
Although the ADSP-BF531/2/3 processor provides a default
mapping, the user can alter the mappings and priorities of
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ADSP-BF531/ADSP-BF532/ADSP-BF533
Table 2. Core Event Controller (CEC)
Table 3. System Interrupt Controller (SIC)
Priority
(0 is Highest)
Event Class
EVT Entry
Peripheral Interrupt Event
PLL Wakeup
Default Mapping
IVG7
0
Emulation/Test Control EMU
Reset RST
Non-Maskable Interrupt NMI
DMA Error
IVG7
1
PPI Error
IVG7
2
SPORT 0 Error
IVG7
3
Exception
EVX
SPORT 1 Error
IVG7
4
Reserved
SPI Error
IVG7
5
Hardware Error
IVHW
IVTMR
IVG7
UART Error
IVG7
6
Core Timer
Real-Time Clock
DMA Channel 0 (PPI)
DMA Channel 1 (SPORT 0 RX)
DMA Channel 2 (SPORT 0 TX)
DMA Channel 3 (SPORT 1 RX)
DMA Channel 4 (SPORT 1 TX)
DMA Channel 5 (SPI)
DMA Channel 6 (UART RX)
DMA Channel 7 (UART TX)
Timer 0
IVG8
7
General Interrupt 7
General Interrupt 8
General Interrupt 9
General Interrupt 10
General Interrupt 11
General Interrupt 12
General Interrupt 13
General Interrupt 14
General Interrupt 15
IVG8
8
IVG8
IVG9
9
IVG9
IVG9
10
11
12
13
14
15
IVG10
IVG11
IVG12
IVG13
IVG14
IVG15
IVG9
IVG9
IVG10
IVG10
IVG10
IVG11
IVG11
IVG11
IVG12
IVG12
IVG13
Timer 1
interrupt events by writing the appropriate values into the Inter-
rupt Assignment Registers (IAR). Table 3 describes the inputs
into the SIC and the default mappings into the CEC.
Timer 2
PF Interrupt A
PF Interrupt B
Event Control
DMA Channels 8 and 9
(Memory DMA Stream 1)
The ADSP-BF531/2/3 processor provides the user with a very
flexible mechanism to control the processing of events. In the
CEC, three registers are used to coordinate and control events.
Each register is 16 bits wide:
DMA Channels 10 and 11
(Memory DMA Stream 0)
IVG13
IVG13
Software Watchdog Timer
• CEC Interrupt Latch Register (ILAT) – The ILAT register
indicates when events have been latched. The appropriate
bit is set when the processor has latched the event and
cleared when the event has been accepted into the system.
This register is updated automatically by the controller, but
it may be written only when its corresponding IMASK bit
is cleared.
The SIC allows further control of event processing by providing
three 32-bit interrupt control and status registers. Each register
contains a bit corresponding to each of the peripheral interrupt
events shown in Table 3 on Page 7.
• SIC Interrupt Mask Register (SIC_IMASK)– This register
controls the masking and unmasking of each peripheral
interrupt event. When a bit is set in the register, that
peripheral event is unmasked and will be processed by the
system when asserted. A cleared bit in the register masks
the peripheral event, preventing the processor from servic-
ing the event.
• CEC Interrupt Mask Register (IMASK) – The IMASK reg-
ister controls the masking and unmasking of individual
events. When a bit is set in the IMASK register, that event is
unmasked and will be processed by the CEC when asserted.
A cleared bit in the IMASK register masks the event, pre-
venting the processor from servicing the event even though
the event may be latched in the ILAT register. This register
may be read or written while in supervisor mode. (Note
that general-purpose interrupts can be globally enabled and
disabled with the STI and CLI instructions, respectively.)
• SIC Interrupt Status Register (SIC_ISR) – As multiple
peripherals can be mapped to a single event, this register
allows the software to determine which peripheral event
source triggered the interrupt. A set bit indicates the
peripheral is asserting the interrupt, and a cleared bit indi-
cates the peripheral is not asserting the event.
• CEC Interrupt Pending Register (IPEND) – The IPEND
register keeps track of all nested events. A set bit in the
IPEND register indicates the event is currently active or
nested at some level. This register is updated automatically
by the controller but may be read while in supervisor mode.
• SIC Interrupt Wakeup Enable Register (SIC_IWR) – By
enabling the corresponding bit in this register, a peripheral
can be configured to wake up the processor, should the
core be idled when the event is generated. (For more infor-
mation, see Dynamic Power Management on Page 11.)
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ADSP-BF531/ADSP-BF532/ADSP-BF533
Because multiple interrupt sources can map to a single general-
purpose interrupt, multiple pulse assertions can occur simulta-
neously, before or during interrupt processing for an interrupt
event already detected on this interrupt input. The IPEND reg-
ister contents are monitored by the SIC as the interrupt
acknowledgement.
DMA transfers can be controlled by a very flexible descriptor
based methodology or by a standard register based autobuffer
mechanism.
REAL-TIME CLOCK
The ADSP-BF531/2/3 processor Real-Time Clock (RTC) pro-
vides a robust set of digital watch features, including current
time, stopwatch, and alarm. The RTC is clocked by a
32.768 KHz crystal external to the ADSP-BF531/2/3 processor.
The RTC peripheral has dedicated power supply pins so that it
can remain powered up and clocked even when the rest of the
processor is in a low-power state. The RTC provides several
programmable interrupt options, including interrupt per sec-
ond, minute, hour, or day clock ticks, interrupt on
The appropriate ILAT register bit is set when an interrupt rising
edge is detected (detection requires two core clock cycles). The
bit is cleared when the respective IPEND register bit is set. The
IPEND bit indicates that the event has entered into the proces-
sor pipeline. At this point the CEC will recognize and queue the
next rising edge event on the corresponding event input. The
minimum latency from the rising edge transition of the general-
purpose interrupt to the IPEND output asserted is three core
clock cycles; however, the latency can be much higher, depend-
ing on the activity within and the state of the processor.
programmable stopwatch countdown, or interrupt at a pro-
grammed alarm time.
The 32.768 KHz input clock frequency is divided down to a
1 Hz signal by a prescaler. The counter function of the timer
consists of four counters: a 60-second counter, a 60-minute
counter, a 24-hour counter, and a 32,768-day counter.
DMA CONTROLLERS
The ADSP-BF531/2/3 processor has multiple, independent
DMA controllers that support automated data transfers with
minimal overhead for the processor core. DMA transfers can
occur between the ADSP-BF531/2/3 processor's internal memo-
ries and any of its DMA-capable peripherals. Additionally,
DMA transfers can be accomplished between any of the DMA-
capable peripherals and external devices connected to the exter-
nal memory interfaces, including the SDRAM controller and
the asynchronous memory controller. DMA-capable peripher-
als include the SPORTs, SPI port, UART, and PPI. Each
individual DMA-capable peripheral has at least one dedicated
DMA channel.
When enabled, the alarm function generates an interrupt when
the output of the timer matches the programmed value in the
alarm control register. There are two alarms: The first alarm is
for a time of day. The second alarm is for a day and time of that
day.
The stopwatch function counts down from a programmed
value, with one-second resolution. When the stopwatch is
enabled and the counter underflows, an interrupt is generated.
Like other peripherals, the RTC can wake up the processor from
Sleep mode upon generation of any RTC wakeup event.
Additionally, an RTC wakeup event can wake up the processor
from Deep Sleep mode, and wake up the on-chip internal volt-
age regulator from a powered-down state.
The ADSP-BF531/2/3 processor DMA controller supports both
1-dimensional (1D) and 2-dimensional (2D) DMA transfers.
DMA transfer initialization can be implemented from registers
or from sets of parameters called descriptor blocks.
Connect RTC pins RTXI and RTXO with external components
as shown in Figure 6.
The 2D DMA capability supports arbitrary row and column
sizes up to 64K elements by 64K elements, and arbitrary row
and column step sizes up to 32K elements. Furthermore, the
column step size can be less than the row step size, allowing
implementation of interleaved data streams. This feature is
especially useful in video applications where data can be
de-interleaved on the fly.
RTXI
RTXO
R1
X1
Examples of DMA types supported by the ADSP-BF531/2/3
processor DMA controller include:
C1
C2
• A single, linear buffer that stops upon completion
• A circular, auto-refreshing buffer that interrupts on each
full or fractionally full buffer
SUGGESTED COMPONENTS:
ECLIPTEK EC38J (THROUGH-HOLE PACKAGE)
• 1-D or 2-D DMA using a linked list of descriptors
EPSON MC405 12 PF LOAD (SURFACE-MOUNT PACKAGE)
C1 = 22 PF
C2 = 22 PF
R1 = 10 M OHM
• 2-D DMA using an array of descriptors, specifying only the
base DMA address within a common page
NOTE: C1 AND C2 ARE SPECIFIC TO CRYSTAL SPECIFIED FOR X1.
CONTACT CRYSTAL MANUFACTURER FOR DETAILS. C1 AND C2
SPECIFICATIONS ASSUME BOARD TRACE CAPACITANCE OF 3 PF.
In addition to the dedicated peripheral DMA channels, there are
two memory DMA channels provided for transfers between the
various memories of the ADSP-BF531/2/3 processor system.
This enables transfers of blocks of data between any of the
memories—including external SDRAM, ROM, SRAM, and
flash memory—with minimal processor intervention. Memory
Figure 6. External Components for RTC
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ADSP-BF531/ADSP-BF532/ADSP-BF533
• Clocking – Each transmit and receive port can either use an
external serial clock or generate its own, in frequencies
ranging from (fSCLK/131,070) Hz to (fSCLK/2) Hz.
WATCHDOG TIMER
The ADSP-BF531/2/3 processor includes a 32-bit timer that can
be used to implement a software watchdog function. A software
watchdog can improve system availability by forcing the proces-
sor to a known state through generation of a hardware reset,
non-maskable interrupt (NMI), or general-purpose interrupt, if
the timer expires before being reset by software. The program-
mer initializes the count value of the timer, enables the
appropriate interrupt, then enables the timer. Thereafter, the
software must reload the counter before it counts to zero from
the programmed value. This protects the system from remain-
ing in an unknown state where software, which would normally
reset the timer, has stopped running due to an external noise
condition or software error.
• Word length – Each SPORT supports serial data words
from 3 to 32 bits in length, transferred most-significant-bit
first or least-significant-bit first.
• Framing – Each transmit and receive port can run with or
without frame sync signals for each data word. Frame sync
signals can be generated internally or externally, active high
or low, and with either of two pulse widths and early or late
frame sync.
• Companding in hardware – Each SPORT can perform
A-law or µ-law companding according to ITU recommen-
dation G.711. Companding can be selected on the transmit
and/or receive channel of the SPORT without additional
latencies.
If configured to generate a hardware reset, the watchdog timer
resets both the core and the ADSP-BF531/2/3 processor periph-
erals. After a reset, software can determine if the watchdog was
the source of the hardware reset by interrogating a status bit in
the watchdog timer control register.
• DMA operations with single-cycle overhead – Each SPORT
can automatically receive and transmit multiple buffers of
memory data. The processor can link or chain sequences of
DMA transfers between a SPORT and memory.
The timer is clocked by the system clock (SCLK), at a maximum
frequency of fSCLK
.
• Interrupts – Each transmit and receive port generates an
interrupt upon completing the transfer of a data-word or
after transferring an entire data buffer or buffers through
DMA.
TIMERS
There are four general-purpose programmable timer units in
the ADSP-BF531/2/3 processor. Three timers have an external
pin that can be configured either as a Pulse-Width Modulator
(PWM) or timer output, as an input to clock the timer, or as a
mechanism for measuring pulse-widths and periods of external
events. These timers can be synchronized to an external clock
input to the PF1 pin, an external clock input to the PPI_CLK
pin, or to the internal SCLK.
• Multichannel capability – Each SPORT supports 128 chan-
nels out of a 1024-channel window and is compatible with
the H.100, H.110, MVIP-90, and HMVIP standards.
SERIAL PERIPHERAL INTERFACE (SPI) PORT
The ADSP-BF531/2/3 processor has an SPI-compatible port
that enables the processor to communicate with multiple SPI-
compatible devices.
The timer units can be used in conjunction with the UART to
measure the width of the pulses in the data stream to provide an
auto-baud detect function for a serial channel.
The SPI interface uses three pins for transferring data: two data
pins (Master Output-Slave Input, MOSI, and Master Input-
Slave Output, MISO) and a clock pin (Serial Clock, SCK). An
SPI chip select input pin (SPISS) lets other SPI devices select the
processor, and seven SPI chip select output pins (SPISEL7–1) let
the processor select other SPI devices. The SPI select pins are
reconfigured Programmable Flag pins. Using these pins, the SPI
port provides a full-duplex, synchronous serial interface, which
supports both master/slave modes and multimaster
environments.
The timers can generate interrupts to the processor core provid-
ing periodic events for synchronization, either to the system
clock or to a count of external signals.
In addition to the three general-purpose programmable timers,
a fourth timer is also provided. This extra timer is clocked by the
internal processor clock and is typically used as a system tick
clock for generation of operating system periodic interrupts.
SERIAL PORTS (SPORTS)
The SPI port’s baud rate and clock phase/polarities are pro-
grammable, and it has an integrated DMA controller,
configurable to support transmit or receive data streams. The
SPI’s DMA controller can only service unidirectional accesses at
any given time.
The ADSP-BF531/2/3 processor incorporates two dual-channel
synchronous serial ports (SPORT0 and SPORT1) for serial and
multiprocessor communications. The SPORTs support the fol-
lowing features:
• I2S capable operation.
The SPI port’s clock rate is calculated as:
• Bidirectional operation – Each SPORT has two sets of inde-
pendent transmit and receive pins, enabling eight channels
of I2S stereo audio.
fSCLK
2 × SPI_Baud
--------------------------------
SPI Clock Rate =
• Buffered (8-deep) transmit and receive ports – Each port
has a data register for transferring data words to and from
other processor components and shift registers for shifting
data in and out of the data registers.
Where the 16-bit SPI_Baud register contains a value of 2 to
65,535.
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ADSP-BF531/ADSP-BF532/ADSP-BF533
During transfers, the SPI port simultaneously transmits and
receives by serially shifting data in and out on its two serial data
lines. The serial clock line synchronizes the shifting and sam-
pling of data on the two serial data lines.
PROGRAMMABLE FLAGS (PFX)
The ADSP-BF531/2/3 processor has 16 bidirectional, general-
purpose Programmable Flag (PF15–0) pins. Each programma-
ble flag can be individually controlled by manipulation of the
flag control, status and interrupt registers:
UART PORT
• Flag Direction Control Register – Specifies the direction of
each individual PFx pin as input or output.
The ADSP-BF531/2/3 processor provides a full-duplex Univer-
sal Asynchronous Receiver/Transmitter (UART) port, which is
fully compatible with PC-standard UARTs. The UART port
provides a simplified UART interface to other peripherals or
hosts, supporting full-duplex, DMA-supported, asynchronous
transfers of serial data. The UART port includes support for 5 to
8 data bits, 1 or 2 stop bits, and none, even, or odd parity. The
UART port supports two modes of operation:
• Flag Control and Status Registers – The ADSP-BF531/2/3
processor employs a “write one to modify” mechanism that
allows any combination of individual flags to be modified
in a single instruction, without affecting the level of any
other flags. Four control registers are provided. One regis-
ter is written in order to set flag values, one register is
written in order to clear flag values, one register is written
in order to toggle flag values, and one register is written in
order to specify a flag value. Reading the flag status register
allows software to interrogate the sense of the flags.
• PIO (Programmed I/O) – The processor sends or receives
data by writing or reading I/O-mapped UART registers.
The data is double-buffered on both transmit and receive.
• DMA (Direct Memory Access) – The DMA controller
transfers both transmit and receive data. This reduces the
number and frequency of interrupts required to transfer
data to and from memory. The UART has two dedicated
DMA channels, one for transmit and one for receive. These
DMA channels have lower default priority than most DMA
channels because of their relatively low service rates.
• Flag Interrupt Mask Registers – The two Flag Interrupt
Mask Registers allow each individual PFx pin to function as
an interrupt to the processor. Similar to the two Flag Con-
trol Registers that are used to set and clear individual flag
values, one Flag Interrupt Mask Register sets bits to enable
interrupt function, and the other Flag Interrupt Mask reg-
ister clears bits to disable interrupt function. PFx pins
defined as inputs can be configured to generate hardware
interrupts, while output PFx pins can be triggered by soft-
ware interrupts.
The UART port's baud rate, serial data format, error code gen-
eration and status, and interrupts are programmable:
• Supporting bit rates ranging from (fSCLK/ 1,048,576) to
(fSCLK/16) bits per second.
• Flag Interrupt Sensitivity Registers – The two Flag Inter-
rupt Sensitivity Registers specify whether individual PFx
pins are level- or edge-sensitive and specify—if edge-sensi-
tive—whether just the rising edge or both the rising and
falling edges of the signal are significant. One register
selects the type of sensitivity, and one register selects which
edges are significant for edge-sensitivity.
• Supporting data formats from 7 to12 bits per frame.
• Both transmit and receive operations can be configured to
generate maskable interrupts to the processor.
The UART port’s clock rate is calculated as:
fSCLK
-----------------------------------------------
UART Clock Rate =
16 × UART_Divisor
PARALLEL PERIPHERAL INTERFACE
The processor provides a Parallel Peripheral Interface (PPI) that
can connect directly to parallel A/D and D/A converters, ITU-R
601/656 video encoders and decoders, and other general-pur-
pose peripherals. The PPI consists of a dedicated input clock
pin, up to 3 frame synchronization pins, and up to 16 data pins.
The input clock supports parallel data rates up to half the system
clock rate.
Where the 16-bit UART_Divisor comes from the DLH register
(most significant 8 bits) and DLL register (least significant
8 bits).
In conjunction with the general-purpose timer functions, auto-
baud detection is supported.
The capabilities of the UART are further extended with support
for the Infrared Data Association (IrDA®) Serial Infrared Physi-
cal Layer Link Specification (SIR) protocol.
In ITU-R 656 modes, the PPI receives and parses a data stream
of 8-bit or 10-bit data elements. On-chip decode of embedded
preamble control and synchronization information is
supported.
Three distinct ITU-R 656 modes are supported:
• Active Video Only - The PPI does not read in any data
between the End of Active Video (EAV) and Start of Active
Video (SAV) preamble symbols, or any data present during
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ADSP-BF531/ADSP-BF532/ADSP-BF533
the vertical blanking intervals. In this mode, the control
byte sequences are not stored to memory; they are filtered
by the PPI.
although the changes are not realized until the Full-On mode is
entered. DMA access is available to appropriately configured L1
memories.
• Vertical Blanking Only - The PPI only transfers Vertical
Blanking Interval (VBI) data, as well as horizontal blanking
information and control byte sequences on VBI lines.
In the Active mode, it is possible to disable the PLL through the
PLL Control register (PLL_CTL). If disabled, the PLL must be
re-enabled before transitioning to the Full-On or Sleep modes.
• Entire Field - The entire incoming bitstream is read in
through the PPI. This includes active video, control pream-
ble sequences, and ancillary data that may be embedded in
horizontal and vertical blanking intervals.
Table 4. Power Settings
Mode
PLL
PLL
Core
System Core
Clock Power
Bypassed Clock
Though not explicitly supported, ITU-R 656 output functional-
ity can be achieved by setting up the entire frame structure
(including active video, blanking, and control information) in
memory and streaming the data out the PPI in a frame sync-less
mode. The processor’s 2D DMA features facilitate this transfer
by allowing the static frame buffer (blanking and control codes)
to be placed in memory once, and simply updating the active
video information on a per-frame basis.
(CCLK) (SCLK)
Full On
Active
Enabled No
Enabled Enabled On
Enabled Enabled On
Enabled/ Yes
Disabled
Sleep
Enabled
Disabled Enabled On
Disabled Disabled On
Disabled Disabled Off
Deep Sleep Disabled
Hibernate Disabled
The general-purpose modes of the PPI are intended to suit a
wide variety of data capture and transmission applications. The
modes are divided into four main categories, each allowing up
to 16 bits of data transfer per PPI_CLK cycle:
Hibernate Operating Mode—Maximum Static Power
Savings
The Hibernate mode maximizes static power savings by dis-
abling the voltage and clocks to the processor core (CCLK) and
to all the synchronous peripherals (SCLK). The internal voltage
regulator for the processor can be shut off by writing b#00 to the
FREQ bits of the VR_CTL register. This disables both CCLK
and SCLK. Furthermore, it sets the internal power supply volt-
age (VDDINT) to 0 V to provide the lowest static power
dissipation. Any critical information stored internally (memory
contents, register contents, etc.) must be written to a non-vola-
tile storage device prior to removing power if the processor state
is to be preserved. Since VDDEXT is still supplied in this mode, all
of the external pins tri-state, unless otherwise specified. This
allows other devices that may be connected to the processor to
have power still applied without drawing unwanted current.
The internal supply regulator can be woken up either by a Real-
Time Clock wakeup or by asserting the RESET pin.
• Data Receive with Internally Generated Frame Syncs
• Data Receive with Externally Generated Frame Syncs
• Data Transmit with Internally Generated Frame Syncs
• Data Transmit with Externally Generated Frame Syncs
These modes support ADC/DAC connections, as well as video
communication with hardware signaling. Many of the modes
support more than one level of frame synchronization. If
desired, a programmable delay can be inserted between asser-
tion of a frame sync and reception/transmission of data.
DYNAMIC POWER MANAGEMENT
The ADSP-BF531/2/3 processor provides five operating modes,
each with a different performance/power profile. In addition,
Dynamic Power Management provides the control functions to
dynamically alter the processor core supply voltage, further
reducing power dissipation. Control of clocking to each of the
ADSP-BF531/2/3 processor peripherals also reduces power con-
sumption. See Table 4 for a summary of the power settings for
each mode.
Sleep Operating Mode—High Dynamic Power Savings
The Sleep mode reduces dynamic power dissipation by dis-
abling the clock to the processor core (CCLK). The PLL and
system clock (SCLK), however, continue to operate in this
mode. Typically an external event or RTC activity will wake up
the processor. When in the Sleep mode, assertion of wakeup will
cause the processor to sense the value of the BYPASS bit in the
PLL Control register (PLL_CTL). If BYPASS is disabled, the
processor will transition to the Full On mode. If BYPASS is
enabled, the processor will transition to the Active mode.
Full-On Operating Mode—Maximum Performance
In the Full-On mode, the PLL is enabled and is not bypassed,
providing capability for maximum operational frequency. This
is the power-up default execution state in which maximum per-
formance can be achieved. The processor core and all enabled
peripherals run at full speed.
When in the Sleep mode, system DMA access to L1 memory is
not supported.
Active Operating Mode—Moderate Power Savings
Deep Sleep Operating Mode—Maximum Dynamic Power
Savings
In the Active mode, the PLL is enabled but bypassed. Because
the PLL is bypassed, the processor’s core clock (CCLK) and sys-
tem clock (SCLK) run at the input clock (CLKIN) frequency. In
this mode, the CLKIN to CCLK multiplier ratio can be changed,
The Deep Sleep mode maximizes dynamic power savings by
disabling the clocks to the processor core (CCLK) and to all syn-
chronous peripherals (SCLK). Asynchronous peripherals, such
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ADSP-BF531/ADSP-BF532/ADSP-BF533
as the RTC, may still be running but will not be able to access
internal resources or external memory. This powered-down
mode can only be exited by assertion of the reset interrupt
(RESET) or by an asynchronous interrupt generated by the
RTC. When in Deep Sleep mode, an RTC asynchronous inter-
rupt causes the processor to transition to the Active mode.
Assertion of RESET while in Deep Sleep mode causes the pro-
cessor to transition to the Full-On mode.
• TNOM is the duration running at fCCLKNOM
• TRED is the duration running at fCCLKRED
The percent power savings is calculated as:
% Power Savings = (1 – Power Savings Factor) × 100%
VOLTAGE REGULATION
The Blackfin processor provides an on-chip voltage regulator
that can generate processor core voltage levels 0.85V(-5% /
+10%) to 1.2V(-5% / +10%) from an external 2.25 V to 3.6 V
supply. Figure 7 shows the typical external components
required to complete the power management system.* The regu-
lator controls the internal logic voltage levels and is
programmable with the Voltage Regulator Control Register
(VR_CTL) in increments of 50 mV. To reduce standby power
consumption, the internal voltage regulator can be programmed
to remove power to the processor core while keeping I/O power
(VDDEXT) supplied. While in hibernation, VDDEXT can still be
applied, eliminating the need for external buffers. The voltage
regulator can be activated from this power-down state either
through an RTC wakeup or by asserting RESET, which will then
initiate a boot sequence. The regulator can also be disabled and
bypassed at the user’s discretion.
Power Savings
As shown in Table 5, the ADSP-BF531/2/3 processor supports
three different power domains. The use of multiple power
domains maximizes flexibility, while maintaining compliance
with industry standards and conventions. By isolating the inter-
nal logic of the ADSP-BF531/2/3 processor into its own power
domain, separate from the RTC and other I/O, the processor
can take advantage of Dynamic Power Management, without
affecting the RTC or other I/O devices. There are no sequencing
requirements for the various power domains.
Table 5. Power Domains
Power Domain
VDD Range
VDDINT
All internal logic, except RTC
RTC internal logic and crystal I/O
All other I/O
VDDRTC
VDDEXT
VDDEXT
The power dissipated by a processor is largely a function of the
clock frequency of the processor and the square of the operating
voltage. For example, reducing the clock frequency by 25%
results in a 25% reduction in dynamic power dissipation, while
reducing the voltage by 25% reduces dynamic power dissipation
by more than 40%. Further, these power savings are additive, in
that if the clock frequency and supply voltage are both reduced,
the power savings can be dramatic.
100 µF
2.25V TO 3.6V
INPUT VOLTAGE
RANGE
10 µH
0.1 µF
ZHCS1000
VDDINT
NDS8434
100 µF
1 µF
VROUT1-0
The Dynamic Power Management feature of the ADSP-
BF531/2/3 processor allows both the processor’s input voltage
(VDDINT) and clock frequency (fCCLK) to be dynamically
controlled.
EXTERNAL COMPONENTS
NOTE: VROUT1-0 SHOULD BE TIED TOGETHER EXTERNALLY
AND DESIGNER SHOULD MINIMIZE TRACE LENGTH TO NDS8434.
The savings in power dissipation can be modeled using the
Power Savings Factor and % Power Savings calculations.
Figure 7. Voltage Regulator Circuit
The Power Savings Factor is calculated as:
CLOCK SIGNALS
Power Savings Factor
The ADSP-BF531/2/3 processor can be clocked by an external
crystal, a sine wave input, or a buffered, shaped clock derived
from an external clock oscillator.
2
fCCLKRED
---------------------
fCCLKNOM
V
T
RED
TNOM
DDINTRED
--------------------------
------------
×
=
×
VDDINTNOM
If an external clock is used, it should be a TTL compatible signal
and must not be halted, changed, or operated below the speci-
fied frequency during normal operation. This signal is
connected to the processor’s CLKIN pin. When an external
clock is used, the XTAL pin must be left unconnected.
where the variables in the equations are:
• fCCLKNOM is the nominal core clock frequency
• fCCLKRED is the reduced core clock frequency
• VDDINTNOM is the nominal internal supply voltage
• VDDINTRED is the reduced internal supply voltage
* See EE-228: Switching Regulator Design Considerations for ADSP-BF533
Blackfin Processors.
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ADSP-BF531/ADSP-BF532/ADSP-BF533
Alternatively, because the ADSP-BF531/2/3 processor includes
an on-chip oscillator circuit, an external crystal may be used.
The crystal should be connected across the CLKIN and XTAL
pins, with two capacitors connected as shown in Figure 8.
Capacitor values are dependent on crystal type and should be
specified by the crystal manufacturer. A parallel-resonant,
fundamental frequency, microprocessor-grade crystal should be
used.
into the SSEL fields define a divide ratio between the PLL output
(VCO) and the system clock. SCLK divider values are 1 through
15. Table 6 illustrates typical system clock ratios.
Table 6. Example System Clock Ratios
Signal Name Divider Ratio Example Frequency Ratios
SSEL3–0
VCO/SCLK
(MHz)
VCO
100
SCLK
100
133
50
0001
0011
1010
1:1
3:1
400
XTAL
CLKOUT
10:1
500
CLKIN
The maximum frequency of the system clock is fSCLK. Note that
the divisor ratio must be chosen to limit the system clock fre-
quency to its maximum of fSCLK. The SSEL value can be changed
dynamically without any PLL lock latencies by writing the
appropriate values to the PLL divisor register (PLL_DIV).
Figure 8. External Crystal Connections
As shown in Figure 9 on Page 13, the core clock (CCLK) and
system peripheral clock (SCLK) are derived from the input
clock (CLKIN) signal. An on-chip PLL is capable of multiplying
the CLKIN signal by a user programmable 1x to 63x multiplica-
tion factor (bounded by specified minimum and maximum
VCO frequencies). The default multiplier is 10x, but it can be
modified by a software instruction sequence. On-the-fly fre-
quency changes can be effected by simply writing to the
PLL_DIV register.
The core clock (CCLK) frequency can also be dynamically
changed by means of the CSEL1–0 bits of the PLL_DIV register.
Supported CCLK divider ratios are 1, 2, 4, and 8, as shown in
Table 7. This programmable core clock capability is useful for
fast core frequency modifications.
Table 7. Core Clock Ratios
Signal Name Divider Ratio Example Frequency Ratios
CSEL1–0
VCO/CCLK
VCO
300
300
500
200
CCLK
300
150
125
25
00
01
10
11
1:1
2:1
4:1
8:1
“FINE” ADJUSTMENT
REQUIRES PLL SEQUENCING
“COARSE” ADJUSTMENT
ON-THE-FLY
÷ 1, 2, 4, 8
÷ 1:15
CCLK
SCLK
PLL
0. 5× - 64×
CLKIN
BOOTING MODES
VCO
The ADSP-BF531/2/3 processor has two mechanisms (listed in
Table 8) for automatically loading internal L1 instruction mem-
ory after a reset. A third mode is provided to execute from
external memory, bypassing the boot sequence.
SCLK ≤ CCLK
SCLK ≤ 133 MHZ
Table 8. Booting Modes
Figure 9. Frequency Modification Methods
BMODE1–0
Description
All on-chip peripherals are clocked by the system clock (SCLK).
The system clock frequency is programmable by means of the
SSEL3–0 bits of the PLL_DIV register. The values programmed
00
Executefrom16-Bit ExternalMemory (Bypass
Boot ROM)
01
10
11
Boot from 8-Bit or 16-Bit FLASH
Reserved
Boot from SPI Serial EEPROM (8-, 16-, or 24-Bit
address range)
Rev. 0
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ADSP-BF531/ADSP-BF532/ADSP-BF533
The BMODE pins of the Reset Configuration Register, sampled
during power-on resets and software-initiated resets, imple-
ment the following modes:
• All registers, I/O, and memory are mapped into a unified
4G byte memory space, providing a simplified program-
ming model.
• Execute from 16-bit external memory – Execution starts
from address 0x2000 0000 with 16-bit packing. The boot
ROM is bypassed in this mode. All configuration settings
are set for the slowest device possible (3-cycle hold time;
15-cycle R/W access times; 4-cycle setup).
• Microcontroller features, such as arbitrary bit and bit-field
manipulation, insertion, and extraction; integer operations
on 8-, 16-, and 32-bit data-types; and separate user and
supervisor stack pointers.
• Code density enhancements, which include intermixing of
16- and 32-bit instructions (no mode switching, no code
segregation). Frequently used instructions are encoded in
16 bits.
• Boot from 8-bit or 16-bit external FLASH memory – The
FLASH boot routine located in boot ROM memory space is
set up using Asynchronous Memory Bank 0. All configura-
tion settings are set for the slowest device possible (3-cycle
hold time; 15-cycle R/W access times; 4-cycle setup).
DEVELOPMENT TOOLS
The ADSP-BF531/2/3 processor is supported with a complete
set of CROSSCORE®† software and hardware development
tools, including Analog Devices emulators and VisualDSP++®‡
development environment. The same emulator hardware that
supports other Blackfin processors also fully emulates the
ADSP-BF531/2/3 processor.
• Boot from SPI serial EEPROM (8, 16, or 24-bit
addressable) – The SPI uses the PF2 output pin to select a
single SPI EEPROM device, submits successive read com-
mands at addresses 0x00, 0x0000, and 0x000000 until a
valid 8, 16, or 24-bit addressable EEPROM is detected, and
begins clocking data into the beginning of L1 instruction
memory.
The VisualDSP++ project management environment lets pro-
grammers develop and debug an application. This environment
includes an easy to use assembler (which is based on an alge-
braic syntax), an archiver (librarian/library builder), a linker, a
loader, a cycle-accurate instruction-level simulator, a C/C++
compiler, and a C/C++ runtime library that includes DSP and
mathematical functions. A key point for these tools is C/C++
code efficiency. The compiler has been developed for efficient
translation of C/C++ code to processor assembly. The processor
has architectural features that improve the efficiency of com-
piled C/C++ code.
For each of the boot modes, an 10-byte header is first read from
an external memory device. The header specifies the number of
bytes to be transferred and the memory destination address.
Multiple memory blocks may be loaded by any boot sequence.
Once all blocks are loaded, program execution commences from
the start of L1 instruction SRAM.
In addition, bit 4 of the Reset Configuration Register can be set
by application code to bypass the normal boot sequence during
a software reset. For this case, the processor jumps directly to
the beginning of L1 instruction memory.
The VisualDSP++ debugger has a number of important fea-
tures. Data visualization is enhanced by a plotting package that
offers a significant level of flexibility. This graphical representa-
tion of user data enables the programmer to quickly determine
the performance of an algorithm. As algorithms grow in com-
plexity, this capability can have increasing significance on the
designer’s development schedule, increasing productivity. Sta-
tistical profiling enables the programmer to nonintrusively poll
the processor as it is running the program. This feature, unique
to VisualDSP++, enables the software developer to passively
gather important code execution metrics without interrupting
the real-time characteristics of the program. Essentially, the
developer can identify bottlenecks in software quickly and effi-
ciently. By using the profiler, the programmer can focus on
those areas in the program that impact performance and take
corrective action.
INSTRUCTION SET DESCRIPTION
The Blackfin processor family assembly language instruction set
employs an algebraic syntax designed for ease of coding and
readability. The instructions have been specifically tuned to pro-
vide a flexible, densely encoded instruction set that compiles to
a very small final memory size. The instruction set also provides
fully featured multifunction instructions that allow the pro-
grammer to use many of the processor core resources in a single
instruction. Coupled with many features more often seen on
microcontrollers, this instruction set is very efficient when com-
piling C and C++ source code. In addition, the architecture
supports both user (algorithm/application code) and supervisor
(O/S kernel, device drivers, debuggers, ISRs) modes of opera-
tion, allowing multiple levels of access to core processor
resources.
Debugging both C/C++ and assembly programs with the
VisualDSP++ debugger, programmers can:
The assembly language, which takes advantage of the proces-
sor’s unique architecture, offers the following advantages:
• View mixed C/C++ and assembly code (interleaved source
and object information).
• Seamlessly integrated DSP/CPU features are optimized for
both 8-bit and 16-bit operations.
• Insert breakpoints.
• A multi-issue load/store modified-Harvard architecture,
which supports two 16-bit MAC or four 8-bit ALU + two
load/store + two pointer updates per cycle.
† CROSSCORE is a registered trademark of Analog Devices, Inc.
‡ VisualDSP++ is a registered trademark of Analog Devices, Inc.
Rev. 0
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Page 14 of 56
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ADSP-BF531/ADSP-BF532/ADSP-BF533
• Set conditional breakpoints on registers, memory,
and stacks.
lator provides full speed emulation, allowing inspection and
modification of memory, registers, and processor stacks. Non-
intrusive in-circuit emulation is assured by the use of the
processor’s JTAG interface—the emulator does not affect target
system loading or timing.
• Trace instruction execution.
• Perform linear or statistical profiling of program execution.
• Fill, dump, and graphically plot the contents of memory.
• Perform source level debugging.
In addition to the software and hardware development tools
available from Analog Devices, third parties provide a wide
range of tools supporting the Blackfin processor family. Hard-
ware tools include Blackfin processor PC plug-in cards. Third
party software tools include DSP libraries, real-time operating
systems, and block diagram design tools.
• Create custom debugger windows.
The VisualDSP++ IDDE lets programmers define and manage
software development. Its dialog boxes and property pages let
programmers configure and manage all of the Blackfin develop-
ment tools, including the color syntax highlighting in the
VisualDSP++ editor. This capability permits programmers to:
DESIGNING AN EMULATOR COMPATIBLE
PROCESSOR BOARD
• Control how the development tools process inputs and
generate outputs.
The Analog Devices family of emulators are tools that every sys-
tem developer needs to test and debug hardware and software
systems. Analog Devices has supplied an IEEE 1149.1 JTAG
Test Access Port (TAP) on each JTAG processor. The emulator
uses the TAP to access the internal features of the processor,
allowing the developer to load code, set breakpoints, observe
variables, observe memory, and examine registers. The proces-
sor must be halted to send data and commands, but once an
operation has been completed by the emulator, the processor
system is set running at full speed with no impact on system
timing.
• Maintain a one-to-one correspondence with the tool’s
command line switches.
The VisualDSP++ Kernel (VDK) incorporates scheduling and
resource management tailored specifically to address the mem-
ory and timing constraints of DSP programming. These
capabilities enable engineers to develop code more effectively,
eliminating the need to start from the very beginning, when
developing new application code. The VDK features include
Threads, Critical and Unscheduled regions, Semaphores,
Events, and Device flags. The VDK also supports Priority-based,
Preemptive, Cooperative, and Time-Sliced scheduling
To use these emulators, the target board must include a header
that connects the processor’s JTAG port to the emulator.
approaches. In addition, the VDK was designed to be scalable. If
the application does not use a specific feature, the support code
for that feature is excluded from the target system.
For details on target board design issues including mechanical
layout, single processor connections, multiprocessor scan
chains, signal buffering, signal termination, and emulator pod
logic, see the EE-68: Analog Devices JTAG Emulation Technical
Reference on the Analog Devices web site (www.analog.com)—
use site search on “EE-68.” This document is updated regularly
to keep pace with improvements to emulator support.
Because the VDK is a library, a developer can decide whether to
use it or not. The VDK is integrated into the VisualDSP++
development environment, but can also be used via standard
command line tools. When the VDK is used, the development
environment assists the developer with many error-prone tasks
and assists in managing system resources, automating the gen-
eration of various VDK based objects, and visualizing the
system state, when debugging an application that uses the VDK.
VCSE is Analog Devices technology for creating, using, and
reusing software components (independent modules of sub-
stantial functionality) to quickly and reliably assemble software
applications. Download components from the Web and drop
them into the application. Publish component archives from
within VisualDSP++. VCSE supports component implementa-
tion in C/C++ or assembly language.
Use the Expert Linker to visually manipulate the placement of
code and data on the embedded system. View memory utiliza-
tion in a color-coded graphical form, easily move code and data
to different areas of the processor or external memory with the
drag of the mouse, examine run time stack and heap usage. The
Expert Linker is fully compatible with existing Linker Definition
File (LDF), allowing the developer to move between the graphi-
cal and textual environments.
Analog Devices emulators use the IEEE 1149.1 JTAG Test
Access Port of the ADSP-BF531/2/3 processor to monitor and
control the target board processor during emulation. The emu-
Rev. 0
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ADSP-BF531/ADSP-BF532/ADSP-BF533
PIN DESCRIPTIONS
ADSP-BF531/2/3 processor pin definitions are listed in Table 9.
In order to maintain maximum functionality and reduce pack-
age size and pin count, some pins have dual, multiplexed
functionality. In cases where pin functionality is reconfigurable,
the default state is shown in plain text, while alternate function-
ality is shown in italics.
All pins are three-stated during and immediately after reset,
except the Memory Interface, Asynchronous Memory Control,
and Synchronous Memory Control pins, which are driven high.
If BR is active, then the memory pins are also three-stated. All
unused I/O pins have their input buffers disabled with the
exception of the pins that need pullups or pulldowns as noted in
the table footnotes.
Table 9. Pin Descriptions
Pin Name
I/O Function
Driver Type1
Memory Interface
ADDR19–1
O
Address Bus for Async/Sync Access
A2
A2
A2
DATA15–0
I/O Data Bus for Async/Sync Access
ABE1–0/SDQM1–0
BR3
O
I
Byte Enables/Data Masks for Async/Sync Access
Bus Request
Bus Grant
BG
O
O
A2
A2
BGH
Bus Grant Hang
Asynchronous Memory Control
AMS3–0
O
I
Bank Select
A2
ARDY
Hardware Ready Control
Output Enable
Read Enable
AOE
O
O
O
A2
A2
A2
ARE
AWE
Write Enable
Synchronous Memory Control
SRAS
O
O
O
O
O
O
O
Row Address Strobe
Column Address Strobe
Write Enable
A2
A2
A2
A2
B4
A2
A2
SCAS
SWE
SCKE
Clock Enable
CLKOUT
SA10
Clock Output
A10 Pin
SMS
Bank Select
Timers
TMR0
I/O Timer 0
C5
C5
C5
TMR1/PPI_FS1
TMR2/PPI_FS2
I/O Timer 1/PPI Frame Sync1
I/O Timer 2/PPI Frame Sync2
Rev. 0
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Page 16 of 56
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ADSP-BF531/ADSP-BF532/ADSP-BF533
Table 9. Pin Descriptions (Continued)
I/O Function
Pin Name
Parallel Peripheral Interface Port/GPIO
PF0/SPISS
PF1/SPISEL1/TMRCLK
PF2/SPISEL2
PF3/SPISEL3/PPI_FS3
PF4/SPISEL4/PPI15
PF5/SPISEL5/PPI14
PF6/SPISEL6/PPI13
PF7/SPISEL7/PPI12
PF8/PPI11
PF9/PPI10
PF10/PPI9
PF11/PPI8
PF12/PPI7
PF13/PPI6
PF14/PPI5
PF15/PPI4
PPI3–0
Driver Type1
I/O Programmable Flag 0/SPI Slave Select Input
I/O Programmable Flag 1/SPI Slave Select Enable 1/External Timer Reference C5
C5
I/O Programmable Flag 2/SPI Slave Select Enable 2
I/O Programmable Flag 3/SPI Slave Select Enable 3/PPI Frame Sync 3
I/O Programmable Flag 4/SPI Slave Select Enable 4 / PPI 15
I/O Programmable Flag 5/SPI Slave Select Enable 5 / PPI 14
I/O Programmable Flag 6/SPI Slave Select Enable 6 / PPI 13
I/O Programmable Flag 7/SPI Slave Select Enable 7 / PPI 12
I/O Programmable Flag 8/PPI 11
C5
C5
C5
C5
C5
C5
C5
C5
C5
C5
C5
C5
C5
C5
C5
C5
I/O Programmable Flag 9/PPI 10
I/O Programmable Flag 10/PPI 9
I/O Programmable Flag 11/PPI 8
I/O Programmable Flag 12/PPI 7
I/O Programmable Flag 13/PPI 6
I/O Programmable Flag 14/PPI 5
I/O Programmable Flag 15/PPI 4
I/O PPI3–0
PPI_CLK
I
PPI Clock
Serial Ports
RSCLK0
I/O SPORT0 Receive Serial Clock
I/O SPORT0 Receive Frame Sync
D6
C5
RFS0
DR0PRI
I
I
SPORT0 Receive Data Primary
SPORT0 Receive Data Secondary
DR0SEC
TSCLK0
I/O SPORT0 Transmit Serial Clock
I/O SPORT0 Transmit Frame Sync
D6
C5
C5
C5
D6
C5
TFS0
DT0PRI
O
O
SPORT0 Transmit Data Primary
SPORT0 Transmit Data Secondary
DT0SEC
RSCLK1
I/O SPORT1 Receive Serial Clock
I/O SPORT1 Receive Frame Sync
RFS1
DR1PRI
I
I
SPORT1 Receive Data Primary
SPORT1 Receive Data Secondary
DR1SEC
TSCLK1
I/O SPORT1 Transmit Serial Clock
I/O SPORT1 Transmit Frame Sync
D6
C5
C5
C5
TFS1
DT1PRI
O
O
SPORT1 Transmit Data Primary
SPORT1 Transmit Data Secondary
DT1SEC
SPI Port
MOSI
MISO7
I/O Master Out Slave In
I/O Master In Slave Out
I/O SPI Clock
C5
C5
D6
SCK
Rev. 0
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Page 17 of 56
| March 2004
ADSP-BF531/ADSP-BF532/ADSP-BF533
Table 9. Pin Descriptions (Continued)
Pin Name
UART Port
RX
I/O Function
Driver Type1
I
UART Receive
TX
O
UART Transmit
C5
Real Time Clock
RTXI8
I
RTC Crystal Input
RTXO
O
RTC Crystal Output
JTAG Port
TCK
I
JTAG Clock
TDO
O
I
JTAG Serial Data Out
JTAG Serial Data In
JTAG Mode Select
JTAG Reset
C5
TDI
TMS
TRST9
I
I
EMU
O
Emulation Output
C5
Clock
CLKIN
I
Clock/Crystal Input
Crystal Output
XTAL
O
Mode Controls
RESET
NMI8
I
I
I
Reset
Non-maskable Interrupt
Boot Mode Strap
BMODE1–0
Voltage Regulator
VROUT1–0
Supplies
VDDEXT
VDDINT
O
External FET Drive
P
P
P
G
I/O Power Supply
Core Power Supply
Real Time Clock Power Supply
External Ground
VDDRTC
GND
1 Refer to Figure 26 on Page 39 to Figure 30 on Page 40.
2 See Figure 25 and Figure 26 on Page 39
3 This pin should be pulled HIGH when not used.
4 See Figure 27 and Figure 28 on Page 39
5 See Figure 29 and Figure 30 on Page 40
6 See Figure 31 and Figure 32 on Page 40
7 This pin should always be pulled HIGH through a 4.7K Ohm resistor if booting via the SPI port.
8 This pin should always be pulled LOW when not used.
9 This pin should be pulled LOW if the JTAG port will not be used.
Rev. 0
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Page 18 of 56
| March 2004
ADSP-BF531/ADSP-BF532/ADSP-BF533
SPECIFICATIONS
Component specifications are subject to change
without notice.
RECOMMENDED OPERATING CONDITIONS
Parameter
Minimum
0.8
Nominal
1.2
Maximum
1.32
3.6
Unit
V
VDDINT
VDDEXT
VDDRTC
VIH
Internal Supply Voltage
External Supply Voltage
2.25
2.25
2.0
2.5 or 3.3
V
Real-time Clock Power Supply Voltage
High Level Input Voltage1, 2 @ VDDEXT =maximum
High Level Input Voltage3 @ VDDEXT=maximum
Low Level Input Voltage2, 4 @ VDDEXT=minimum
3.6
V
3.6
V
VIHCLKIN
VIL
2.2
3.6
V
–0.3
0.6
V
1 The ADSP-BF531/2/3 processor is 3.3 V tolerant (always accepts up to 3.6 V maximum VIH), but voltage compliance (on outputs, VOH) depends on the input VDDEXT, because
VOH (maximum) approximately equals VDDEXT (maximum). This 3.3 V tolerance applies to bidirectional pins (DATA15–0, TMR2–0, PF15–0, PPI3–0, RSCLK1–0,
TSCLK1–0, RFS1–0, TFS1–0, MOSI, MISO, SCK) and input only pins (BR, ARDY, PPI_CLK, DR0PRI, DR0SEC, DR1PRI, DR1SEC, RX, RTXI, TCK, TDI, TMS, TRST,
CLKIN, RESET, NMI, and BMODE1–0).
2 Parameter value applies to all input and bidirectional pins except CLKIN.
3 Parameter value applies to CLKIN pin only.
4 Parameter value applies to all input and bidirectional pins.
ELECTRICAL CHARACTERISTICS
Parameter
Test Conditions
Minimum
Maximum
Unit
V
VOH
VOL
IIH
High Level Output Voltage1
Low Level Output Voltage2
High Level Input Current2
@ VDDEXT =3.0V, IOH = –0.5 mA
@ VDDEXT =3.0V, IOL = 2.0 mA
@ VDDEXT =maximum, VIN = VDD maximum
2.4
0.4
V
10.0
20.0
10.0
10.0
10.0
8.0
µA
µA
µA
µA
µA
pF
IIHP
IIL
High Level Input Current JTAG3 @ VDDEXT =maximum, VIN = VDD maximum
Low Level Input Current4
@ VDDEXT =maximum, VIN = 0 V
Three-State Leakage Current4 @ VDDEXT = maximum, VIN = VDD maximum
Three-State Leakage Current5 @ VDDEXT = maximum, VIN = 0 V
IOZH
IOZL
CIN
Input Capacitance5, 6
fIN = 1 MHz, TAMBIENT = 25°C, VIN = 2.5 V
1 Applies to output and bidirectional pins.
2 Applies to input pins except JTAG inputs.
3 Applies to JTAG input pins (TCK, TDI, TMS, TRST).
4 Applies to three-statable pins.
5 Applies to all signal pins.
6 Guaranteed, but not tested.
Rev. 0
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Page 19 of 56
| March 2004
ADSP-BF531/ADSP-BF532/ADSP-BF533
ABSOLUTE MAXIMUM RATINGS
Stresses greater than those listed in the table may cause perma-
nent damage to the device. These are stress ratings only.
Functional operation of the device at these or any other condi-
tions greater than those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
For proper SDRAM controller operation, the maximum load
capacitance is 50 pF (at 3.3 V) or 30 pF (at 2.5 V) for
ADDR19–1, DATA15–0, ABE1–0/SDQM1–0, CLKOUT,
SCKE, SA10, SRAS, SCAS, SWE, and SMS.
Parameter
Rating
Internal (Core) Supply Voltage (VDDINT
)
–0.3 V to +1.4 V
–0.3 V to +3.8 V
–0.5 V to 3.6 V
–0.5 V to VDDEXT+0.5 V
200 pF
External (I/O) Supply Voltage (VDDEXT
Input Voltage
)
Output Voltage Swing
Load Capacitance
ADSP-BF533 Core Clock (CCLK)
600 MHz
ADSP-BF532/BF531 Core Clock (CCLK)
Peripheral Clock (SCLK)
400 MHz
133 MHz
Storage Temperature Range
Junction Temperature Under Bias
–65ºC to +150ºC
125ºC
ESD SENSITIVITY
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADSP-BF531/2/3 processor features proprietary ESD protection circuitry, permanent damage
may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
Rev. 0
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Page 20 of 56
| March 2004
ADSP-BF531/ADSP-BF532/ADSP-BF533
TIMING SPECIFICATIONS
Table 10 through Table 14 describe the timing requirements for
the ADSP-BF531/2/3 processor clocks. Take care in selecting
MSEL, SSEL, and CSEL ratios so as not to exceed the maximum
core clock and system clock as described in Absolute Maximum
Ratings on Page 20, and the Voltage Controlled Oscillator
(VCO) operating frequencies described in Table 13. Table 13
describes Phase-Locked Loop operating conditions.
Table 10. Core and System Clock Requirements—ADSP-BF533SKBC600
Parameter
Min
Max
Max
Max
Unit
ns
tCCLK
tCCLK
tCCLK
tCCLK
tCCLK
tSCLK
Core Cycle Period (VDDINT=1.2 V–5%)
1.67
Core Cycle Period (VDDINT=1.1 V–5%)
Core Cycle Period (VDDINT=1.0 V–5%)
Core Cycle Period (VDDINT=0.9 V–5%)
Core Cycle Period (VDDINT=0.8 V)
System Clock Period
2.10
ns
2.35
ns
2.66
ns
4.00
ns
Maximum of 7.5 or tCCLK
ns
Table 11. Core and System Clock Requirements—ADSP-BF533SBBC500 and ADSP-BF533SBBZ500
Parameter
Min
Unit
ns
tCCLK
tCCLK
tCCLK
tCCLK
tCCLK
tSCLK
Core Cycle Period (VDDINT=1.2 V–5%)
2.0
Core Cycle Period (VDDINT=1.1 V–5%)
Core Cycle Period (VDDINT=1.0 V–5%)
Core Cycle Period (VDDINT=0.9 V–5%)
Core Cycle Period (VDDINT=0.8 V)
System Clock Period
2.25
ns
2.50
ns
3.00
ns
4.00
ns
Maximum of 7.5 or tCCLK
ns
Table 12. Core and System Clock Requirements—ADSP-BF532/531 All Package Types
Parameter
Min
Unit
ns
tCCLK Core Cycle Period (VDDINT =1.2 V–5%)
tCCLK Core Cycle Period (VDDINT =1.1 V–5%)
tCCLK Core Cycle Period (VDDINT =1.0 V–5%)
tCCLK Core Cycle Period (VDDINT =0.9 V–5%)
tCCLK Core Cycle Period (VDDINT =0.8 V)
tSCLK System Clock Period
2.5
2.75
ns
3.00
ns
3.25
ns
4.0
ns
Maximum of 7.5 or tCCLK
ns
Table 13. Phase-Locked Loop Operating Conditions
Parameter
Min
Max
Unit
fVCO
Voltage Controlled Oscillator (VCO) Frequency
50
Max CCLK
MHz
Table 14. Maximum SCLK Conditions
Parameter Condition
VDDEXT = 3.3 V
VDDEXT = 2.5 V
Unit
MBGA
fSCLK
fSCLK
LQFP
fSCLK
fSCLK
V
V
DDINT >= 1.14 V
DDINT < 1.14 V
133
100
133
100
MHz
MHz
V
V
DDINT >= 1.14 V
DDINT < 1.14 V
133
83
1331
831
MHz
MHz
1 Set bit 7 (output delay) of PLL_CTL register.
Rev. 0
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Page 21 of 56
| March 2004
ADSP-BF531/ADSP-BF532/ADSP-BF533
Clock and Reset Timing
Table 15 and Figure 10 describe clock and reset operations. Per
Absolute Maximum Ratings on Page 20, combinations of
CLKIN and clock multipliers must not select core/peripheral
clocks in excess of 600/133 MHz.
Table 15. Clock and Reset Timing
Parameter
Min
Max
Unit
Timing Requirements
tCKIN
CLKIN Period
CLKIN Low Pulse1
CLKIN High Pulse1
RESET Asserted Pulse Width Low2
25.0
100.0
ns
ns
ns
ns
tCKINL
tCKINH
tWRST
10.0
10.0
11 tCKIN
1 Applies to bypass mode and non-bypass mode.
2 Applies after power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 2000 CLKIN cycles, while RESET is asserted,
assuming stable power supplies and CLKIN (not including start-up time of external clock oscillator).
tCKIN
CLKIN
tCKINL
tCKINH
tWRST
RESET
Figure 10. Clock and Reset Timing
Rev. 0
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Page 22 of 56
| March 2004
ADSP-BF531/ADSP-BF532/ADSP-BF533
Asynchronous Memory Read Cycle Timing
Table 16. Asynchronous Memory Read Cycle Timing
Parameter
Min
Max
Unit
Timing Requirements
tSDAT
DATA15–0 Setup Before CLKOUT
DATA15–0 Hold After CLKOUT
ARDY Setup Before CLKOUT
ARDY Hold After CLKOUT
2.1
0.8
4.0
0.0
ns
ns
ns
ns
tHDAT
tSARDY
tHARDY
Switching Characteristics
tDO
tHO
Output Delay After CLKOUT1
Output Hold After CLKOUT 1
6.0
ns
ns
0.8
1 Output pins include AMS3–0, ABE1–0, ADDR19–1, AOE, ARE.
HOLD
1 CYCLE
SETUP
2 CYCLES
PROGRAMMED READ ACCESS
4 CYCLES
ACCESS EXTENDED
3 CYCLES
CLKOUT
tDO
tHO
AMSx
ABE1–0
BE, ADDRESS
ADDR19–1
AOE
tDO
tHO
ARE
tHARDY
tSARDY
tHARDY
ARDY
tSARDY
tSDAT
tHDAT
DATA15–0
READ
Figure 11. Asynchronous Memory Read Cycle Timing
Rev. 0
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Page 23 of 56
| March 2004
ADSP-BF531/ADSP-BF532/ADSP-BF533
Asynchronous Memory Write Cycle Timing
Table 17. Asynchronous Memory Write Cycle Timing
Parameter
Min
Max
Unit
Timing Requirements
tSARDY
tHARDY
ARDY Setup Before CLKOUT
ARDY Hold After CLKOUT
4.0
0.0
ns
ns
Switching Characteristics
tDDAT
tENDAT
tDO
DATA15–0 Disable After CLKOUT
6.0
6.0
ns
ns
ns
ns
DATA15–0 Enable After CLKOUT
Output Delay After CLKOUT1
Output Hold After CLKOUT 1
1.0
0.8
tHO
1 Output pins include AMS3–0, ABE1–0, ADDR19–1, DATA15–0, AOE, AWE.
ACCESS
EXTENDED
1 CYCLE
SETUP
2 CYCLES
HOLD
1 CYCLE
PROGRAMMED WRITE
ACCESS 2 CYCLES
CLKOUT
AMSx
tDO
tHO
ABE1–0
BE, ADDRESS
ADDR19–1
tDO
tHO
AWE
tHARDY
tSARDY
ARDY
tSARDY
tENDAT
tDDAT
DATA15–0
WRITE DATA
Figure 12. Asynchronous Memory Write Cycle Timing
Rev. 0
|
Page 24 of 56
| March 2004
ADSP-BF531/ADSP-BF532/ADSP-BF533
SDRAM Interface Timing
Table 18. SDRAM Interface Timing1
Parameter
Min
Max
Unit
Timing Requirements
tSSDAT
tHSDAT
Switching Characteristics
DATA Setup Before CLKOUT
2.1
0.8
ns
ns
DATA Hold After CLKOUT
tSCLK
CLKOUT Period
7.5
2.5
2.5
ns
ns
ns
ns
ns
ns
ns
tSCLKH
CLKOUT Width High
tSCLKL
CLKOUT Width Low
tDCAD
Command, ADDR, Data Delay After CLKOUT2
Command, ADDR, Data Hold After CLKOUT1
Data Disable After CLKOUT
6.0
6.0
tHCAD
0.8
1.0
tDSDAT
tENSDAT
1 For VDDINT = 1.2 V.
Data Enable After CLKOUT
2 Command pins include: SRAS, SCAS, SWE, SDQM, SMS, SA10, SCKE.
tSCLK
tSCLKH
CLKOUT
tSSDAT
tSCLKL
tHSDAT
DATA (IN)
tDCAD
tDSDAT
tENSDAT
tHCAD
DATA(OUT)
tDCAD
CMND ADDR
(OUT)
tHCAD
NOTE: COMMAND = SRAS, SCAS, SWE, SDQM, SMS, SA10, SCKE.
Figure 13. SDRAM Interface Timing
Rev. 0
|
Page 25 of 56
| March 2004
ADSP-BF531/ADSP-BF532/ADSP-BF533
External Port Bus Request and Grant Cycle Timing
Table 19 and Figure 14 describe external port bus request and
bus grant operations.
Table 19. External Port Bus Request and Grant Cycle Timing
Parameter, 1, 2
Min
Max
Unit
Timing Requirements
tBS
BR Asserted to CLKOUT High Setup
4.6
0.0
ns
ns
tBH
CLKOUT High to BR Deasserted Hold Time
Switching Characteristics
tSD
CLKOUT Low to xMS, Address, and RD/WR disable
4.5
4.5
3.6
3.6
3.6
3.6
ns
ns
ns
ns
ns
ns
tSE
CLKOUT Low to xMS, Address, and RD/WR enable
CLKOUT High to BG High Setup
tDBG
tEBG
tDBH
tEBH
CLKOUT High to BG Deasserted Hold Time
CLKOUT High to BGH High Setup
CLKOUT High to BGH Deasserted Hold Time
1 These are preliminary timing parameters that are based on worst-case operating conditions.
2 The pad loads for these timing parameters are 20 pF.
CLKOUT
tBH
tBS
BR
tSD
tSE
AMSx
tSD
tSE
ADDR19-1
ABE1-0
tSD
tSE
AWE
ARE
tDBG
tEBG
BG
tDBH
TEBH
BGH
Figure 14. External Port Bus Request and Grant Cycle Timing
Rev. 0
|
Page 26 of 56
| March 2004
ADSP-BF531/ADSP-BF532/ADSP-BF533
Parallel Peripheral Interface Timing
Table 20 and Figure 15 on Page 27 describe Parallel Peripheral
Interface operations.
Table 20. Parallel Peripheral Interface Timing
Parameter
Min
Max
Unit
Timing Requirements
tPCLKW
tPCLK
PPI_CLK Width
PPI_CLK Period1
6.0
15.0
3.0
3.0
2.0
4.0
ns
ns
ns
ns
ns
ns
tSFSPE
tHFSPE
tSDRPE
tHDRPE
External Frame Sync Setup Before PPI_CLK
External Frame Sync Hold After PPI_CLK
Receive Data Setup Before PPI_CLK
Receive Data Hold After PPI_CLK
Switching Characteristics - GP Output and Frame Capture Modes
tDFSPE
tHOFSPE
tDDTPE
tHDTPE
Internal Frame Sync Delay After PPI_CLK
Internal Frame Sync Hold After PPI_CLK
Transmit Data Delay After PPI_CLK
Transmit Data Hold After PPI_CLK
10.0
10.0
ns
ns
ns
ns
0.0
0.0
1 PPI_CLK frequency cannot exceed fSCLK/2
DRIVE
EDGE
SAMPLE
EDGE
tPCLKW
PPI_CLK
tDFSPE
tHOFSPE
tSFSPE
tHFSPE
PPI_FS1
PPI_FS2
tDDTPE
tSDRPE
tHDRPE
tHDTPE
PPIx
Figure 15. GP Output Mode and Frame Capture Timing
Rev. 0
|
Page 27 of 56
| March 2004
ADSP-BF531/ADSP-BF532/ADSP-BF533
Serial Ports
Table 21 through Table 26 on Page 29 and Figure 16 on Page 30
through Figure 18 on Page 32 describe Serial Port operations.
Table 21. Serial Ports—External Clock
Parameter
Min
Max
Unit
Timing Requirements
tSFSE
TFS/RFS Setup Before TSCLK/RSCLK1
TFS/RFS Hold After TSCLK/RSCLK1
Receive Data Setup Before RSCLK1
Receive Data Hold After RSCLK1
TSCLK/RSCLK Width
3.0
3.0
3.0
3.0
4.5
15.0
ns
ns
ns
ns
ns
ns
tHFSE
tSDRE
tHDRE
tSCLKEW
tSCLKE
TSCLK/RSCLK Period
1 Referenced to sample edge.
Table 22. Serial Ports—Internal Clock
Parameter
Min
Max
Unit
Timing Requirements
tSFSI
TFS/RFS Setup Before TSCLK/RSCLK1
8.0
ns
ns
ns
ns
ns
ns
tHFSI
TFS/RFS Hold After TSCLK/RSCLK1
Receive Data Setup Before RSCLK1
Receive Data Hold After RSCLK1
TSCLK/RSCLK Width
–2.0
6.0
tSDRI
tHDRI
tSCLKEW
tSCLKE
0.0
4.5
TSCLK/RSCLK Period
15.0
1 Referenced to sample edge.
Table 23. Serial Ports—External Clock
Parameter
Min
Max
10.0
10.0
Unit
Switching Characteristics
tDFSE
tHOFSE
tDDTE
tHDTE
TFS/RFS Delay After TSCLK/RSCLK (Internally Generated TFS/RFS)1
TFS/RFS Hold After TSCLK/RSCLK (Internally Generated TFS/RFS)1
Transmit Data Delay After TSCLK1
ns
ns
ns
ns
0.0
0.0
Transmit Data Hold After TSCLK1
1 Referenced to drive edge.
Table 24. Serial Ports—Internal Clock
Parameter
Min
Max
3.0
Unit
Switching Characteristics
tDFS
TFS/RFS Delay After TSCLK/RSCLK (Internally Generated TFS/RFS)1
TFS/RFS Hold After TSCLK/RSCLK (Internally Generated TFS/RFS)1
Transmit Data Delay After TSCLK1
ns
ns
ns
ns
ns
I
tHOFS
−1.0
I
tDDT
3.0
I
tHDT
Transmit Data Hold After TSCLK1
−2.0
I
tSCLKIW
TSCLK/RSCLK Width
4.5
1 Referenced to drive edge.
Rev. 0
|
Page 28 of 56
| March 2004
ADSP-BF531/ADSP-BF532/ADSP-BF533
Table 25. Serial Ports—Enable and Three-State
Parameter
Min
0
Max
Unit
Switching Characteristics
tDTENE
tDDTTE
tDTENI
tDDTTI
Data Enable Delay from External TSCLK1
Data Disable Delay from External TSCLK1
Data Enable Delay from Internal TSCLK1
Data Disable Delay from Internal TSCLK1
ns
ns
ns
ns
10.0
3.0
–2.0
1 Referenced to drive edge.
Table 26. External Late Frame Sync
Parameter
Min
Max
Unit
Switching Characteristics
tDDTLFSE
Data Delay from Late External TFS or External RFS with MCE = 1, MFD = 01, 2
Data Enable from late FS or MCE = 1, MFD = 01,2
10.0
ns
ns
tDTENLFSE
0
1 MCE = 1, TFS enable and TFS valid follow tDDTENFS and tDDTLFSE
.
2 If external RFS/TFS setup to RSCLK/TSCLK > tSCLKE/2, then tDDTLSCK and tDTENLSCK apply; otherwise tDDTLFSE and tDTENLFS apply.
Rev. 0
|
Page 29 of 56
| March 2004
ADSP-BF531/ADSP-BF532/ADSP-BF533
DATA RECEIVE- INTERNAL CLOCK
DATA RECEIVE- EXTERNAL CLOCK
DRIVE
EDGE
SAMPLE
EDGE
DRIVE
EDGE
SAMPLE
EDGE
tSCLKIW
tSCLKEW
RSCLK
RSCLK
tDFSE
tDFSE
tHOFSE
RFS
tSFSI
tHFSI
tHOFSE
tSFSE
tHFSE
RFS
tSDRI
tHDRI
tSDRE
tHDRE
DR
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK OR TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.
DR
DATA TRANSMIT- INTERNAL CLOCK
DATA TRANSMIT- EXTERNAL CLOCK
DRIVE
EDGE
SAMPLE
EDGE
DRIVE
EDGE
SAMPLE
EDGE
tSCLKIW
tSCLKEW
TSCLK
TSCLK
tDFSI
tDFSE
tHOFSI
tSFSI
tHFSI
tHOFSE
tSFSE
tHFSE
TFS
DT
TFS
tDDTI
tDDTE
tHDTI
tHDTE
DT
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK OR TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.
DRIVE
EDGE
DRIVE
EDGE
TSCLK (EXT)
TFS ("LATE", EXT.)
TSCLK / RSCLK
tDDTTE
tDTENE
DT
DRIVE
EDGE
DRIVE
EDGE
TSCLK (INT)
TFS ("LATE", INT.)
TSCLK / RSCLK
tDTENI
tDDTTI
DT
Figure 16. Serial Ports
Rev. 0
|
Page 30 of 56
| March 2004
ADSP-BF531/ADSP-BF532/ADSP-BF533
EXTERNAL RFS WITH MCE = 1, MFD = 0
DRIVE
SAMPLE
DRIVE
RSCLK
RFS
tHOFSE/I
tSFSE/I
tDDTE/I
tDDTENFS
tHDTE/I
1ST BIT
2ND BIT
DT
tDDTLFSE
LATE EXTERNAL TFS
DRIVE
SAMPLE
DRIVE
TSCLK
TFS
tSFSE/I
tHOFSE/I
tDDTE/I
tDDTENFS
tHDTE/I
DT
1ST BIT
2ND BIT
tDDTLFSE
Figure 17. External Late Frame Sync (Frame Sync Setup < tSCLKE/2)
Rev. 0
|
Page 31 of 56
| March 2004
ADSP-BF531/ADSP-BF532/ADSP-BF533
EXTERNAL RFS WITH MCE = 1, MFD = 0
DRIVE
SAMPLE
DRIVE
RSCLK
RFS
tSFSE/I
tHOFSE/I
tDDTE/I
tHDTE/I
tDTENLSCK
1ST BIT
DT
2ND BIT
tDDTLSCK
LATE EXTERNAL TFS
DRIVE
SAMPLE
DRIVE
TSCLK
TFS
tSFSE/I
tHOFSE/I
tDDTE/I
tHDTE/I
tDTENLSCK
DT
1ST BIT
2ND BIT
tDDTLSCK
Figure 18. External Late Frame Sync (Frame Sync Setup > tSCLKE/2)
Rev. 0
|
Page 32 of 56
| March 2004
ADSP-BF531/ADSP-BF532/ADSP-BF533
Serial Peripheral Interface (SPI) Port
—Master Timing
Table 27 and Figure 19 describe SPI port master operations.
Table 27. Serial Peripheral Interface (SPI) Port—Master Timing
Parameter
Min
Max
Unit
Timing Requirements
tSSPIDM
tHSPIDM
Data Input Valid to SCK Edge (Data Input Setup)
SCK Sampling Edge to Data Input Invalid
7.5
ns
ns
–1.5
Switching Characteristics
tSDSCIM
tSPICHM
tSPICLM
tSPICLK
SPISELx Low to First SCK edge (x=0 or 1)
2tSCLK –1.5
2tSCLK –1.5
2tSCLK –1.5
4tSCLK –1.5
2tSCLK –1.5
2tSCLK –1.5
0
ns
ns
ns
ns
ns
ns
ns
ns
Serial Clock High period
Serial Clock Low period
Serial Clock Period
tHDSM
Last SCK Edge to SPISELx High (x=0 or 1)
Sequential Transfer Delay
tSPITDM
tDDSPIDM
tHDSPIDM
SCK Edge to Data Out Valid (Data Out Delay)
SCK Edge to Data Out Invalid (Data Out Hold)
6
–1.0
4.0
SPISELx
(OUTPUT)
tSPICLK
tHDSM
tSPITDM
tSDSCIM
tSPICHM
tSPICLM
SCK
(CPOL = 0)
(OUTPUT)
tSPICLM
tSPICHM
SCK
(CPOL = 1)
(OUTPUT)
tDDSPIDM
tHDSPIDM
MOSI
(OUTPUT)
MSB
LSB
CPHA=1
tSSPIDM
tHSPIDM
tSSPIDM
tHSPIDM
MISO
(INPUT)
MSB VALID
LSB VALID
tDDSPIDM
tHDSPIDM
MOSI
(OUTPUT)
MSB
LSB
CPHA=0
tSSPIDM
tHSPIDM
MISO
(INPUT)
MSB VALID
LSB VALID
Figure 19. Serial Peripheral Interface (SPI) Port—Master Timing
Rev. 0
|
Page 33 of 56
| March 2004
ADSP-BF531/ADSP-BF532/ADSP-BF533
Serial Peripheral Interface (SPI) Port
—Slave Timing
Table 28 and Figure 20 describe SPI port slave operations.
Table 28. Serial Peripheral Interface (SPI) Port—Slave Timing
Parameter
Min
Max
Unit
Timing Requirements
tSPICHS
tSPICLS
tSPICLK
tHDS
Serial Clock High Period
2tSCLK –1.5
2tSCLK –1.5
4tSCLK –1.5
2tSCLK –1.5
2tSCLK –1.5
2tSCLK –1.5
1.6
ns
ns
ns
ns
ns
ns
ns
ns
Serial Clock low Period
Serial Clock Period
Last SCK Edge to SPISS Not Asserted
Sequential Transfer Delay
tSPITDS
tSDSCI
tSSPID
tHSPID
SPISS Assertion to First SCK Edge
Data Input Valid to SCK Edge (Data Input Setup)
SCK Sampling Edge to Data Input Invalid
1.6
Switching Characteristics
tDSOE
SPISS Assertion to Data Out Active
0
0
0
0
8
ns
ns
ns
ns
tDSDHI
tDDSPID
tHDSPID
SPISS Deassertion to Data High impedance
SCK Edge to Data Out Valid (Data Out Delay)
SCK Edge to Data Out Invalid (Data Out Hold)
8
10
10
SPISS
(INPUT)
tSPICHS
tSPICLS
tSPICLK
tHDS
tSPITDS
SCK
(CPOL = 0)
(INPUT)
tSDSCI
tSPICLS
tSPICHS
SCK
(CPOL = 1)
(INPUT)
tDSOE
tDDSPID
tHDSPID
MSB
tDDSPID
tDSDHI
LSB
MISO
(OUTPUT)
tHSPID
tSSPID
CPHA=1
tSSPID
tHSPID
MOSI
(INPUT)
MSB VALID
LSB VALID
tDSOE
tDDSPID
tDSDHI
MISO
(OUTPUT)
MSB
LSB
tHSPID
CPHA=0
tSSPID
MOSI
(INPUT)
MSB VALID
LSB VALID
Figure 20. Serial Peripheral Interface (SPI) Port—Slave Timing
Rev. 0
|
Page 34 of 56
| March 2004
ADSP-BF531/ADSP-BF532/ADSP-BF533
Universal Asynchronous Receiver-Transmitter
(UART) Port—Receive and Transmit Timing
Figure 21 describes UART port receive and transmit operations.
The maximum baud rate is SCLK/16. As shown in Figure 21
there is some latency between the generation internal UART
interrupts and the external data operations. These latencies are
negligible at the data transmission rates for the UART.
CLKOUT
(SAMPLE CLOCK)
RXD
DATA(5–8)
STOP
RECEIVE
INTERNAL
UART RECEIVE
INTERRUPT
UART RECEIVE BIT SET BY DATA STOP;
CLEARED BY FIFO READ
START
TXD
DATA(5–8)
STOP (1–2)
TRANSMIT
INTERNAL
UART TRANSMIT
INTERRUPT
UART TRANSMIT BIT SET BY PROGRAM;
CLEARED BY WRITE TO TRANSMIT
Figure 21. UART Port—Receive and Transmit Timing
Rev. 0
|
Page 35 of 56
| March 2004
ADSP-BF531/ADSP-BF532/ADSP-BF533
Programmable Flags Cycle Timing
Table 29 and Figure 22 describe programmable flag operations.
Table 29. Programmable Flags Cycle Timing
Parameter
Min
Max
Unit
ns
Timing Requirements
tWFI
Switching Characteristics
tDFO Flag Output Delay from CLKOUT Low
Flag Input Pulse Width
tSCLK + 1
6
ns
CLKOUT
tDFO
PF (OUTPUT)
FLAG OUTPUT
FLAG INPUT
tWFI
PF (INPUT)
Figure 22. Programmable Flags Cycle Timing
Rev. 0
|
Page 36 of 56
| March 2004
ADSP-BF531/ADSP-BF532/ADSP-BF533
Timer Cycle Timing
Table 30 and Figure 23 describe timer expired operations. The
input signal is asynchronous in “width capture mode” and
“external clock mode” and has an absolute maximum input fre-
quency of fSCLK/2 MHz.
Table 30. Timer Cycle Timing
Parameter
Min
Max
Unit
Timing Characteristics
tWL
Timer Pulse Width Input Low1 (Measured in SCLK Cycles)
Timer Pulse Width Input High1 (Measured in SCLK Cycles)
1
1
SCLK
SCLK
tWH
Switching Characteristics
tHTO
Timer Pulse Width Output2 (Measured in SCLK Cycles)
1
(232–1)
SCLK
1 The minimum pulse widths apply for TMRx input pins in width capture and external clock modes. They also apply to the PF1 or PPI_CLK input pins in PWM output mode.
2 The minimum time for tHTO is one cycle, and the maximum time for tHTO equals (232–1) cycles.
CLKOUT
tHTO
TMRx
(PWM OUTPUT MODE)
TMRx
tWL
tWH
(WIDTH CAPTURE AND
EXTERNAL CLOCK MODES)
Figure 23. Timer PWM_OUT Cycle Timing
Rev. 0
|
Page 37 of 56
| March 2004
ADSP-BF531/ADSP-BF532/ADSP-BF533
JTAG Test And Emulation Port Timing
Table 31 and Figure 24 describe JTAG port operations.
Table 31. JTAG Port Timing
Parameter
Min
Max
Unit
Timing Requirements
tTCK
TCK Period
20
4
ns
tSTAP
tHTAP
tSSYS
tHSYS
tTRSTW
TDI, TMS Setup Before TCK High
TDI, TMS Hold After TCK High
System Inputs Setup Before TCK High1
System Inputs Hold After TCK High1
TRST Pulse Width2 (Measured in TCK cycles)
ns
4
ns
4
ns
5
ns
4
TCK
Switching Characteristics
tDTDO TDO Delay from TCK Low
tDSYS
System Outputs Delay After TCK Low3
10
12
ns
ns
0
1 System Inputs=DATA15–0, ARDY, TMR2–0, PF15–0, PPI_CLK, RSCLK0–1, RFS0–1, DR0PRI, DR0SEC, TSCLK0–1, TFS0–1, DR1PRI, DR1SEC, MOSI, MISO, SCK, RX,
RESET, NMI, BMODE1–0, BR, PP3–0.
2 50 MHz maximum
3 System Outputs=DATA15–0, ADDR19–1, ABE1–0, AOE, ARE, AWE, AMS3–0, SRAS, SCAS, SWE, SCKE, CLKOUT, SA10, SMS, TMR2–0, PF15–0, RSCLK0–1, RFS0–1,
TSCLK0–1, TFS0–1, DT0PRI, DT0SEC, DT1PRI, DT1SEC, MOSI, MISO, SCK, TX, BG, BGH, PPI3–0.
tTCK
TCK
tSTAP
tHTAP
TMS
TDI
tDTDO
TDO
tSSYS
tHSYS
SYSTEM
INPUTS
tDSYS
SYSTEM
OUTPUTS
Figure 24. JTAG Port Timing
Rev. 0
|
Page 38 of 56
| March 2004
ADSP-BF531/ADSP-BF532/ADSP-BF533
OUTPUT DRIVE CURRENTS
Figure 25 through Figure 32 show typical current-voltage char-
acteristics for the output drivers of the ADSP-BF531/2/3
processor. The curves represent the current drive capability of
the output drivers as a function of output voltage.
150
°
V
V
V
= 2.25V @ 95 C
DDEXT
DDEXT
°
= 2.50V @ 25 C
100
50
°
= 2.75V @ –40 C
DDEXT
150
0
–50
V
°
OH
V
V
V
= 2.25V @ 95 C
DDEXT
DDEXT
°
= 2.50V @ 25 C
100
50
°
= 2.75V @ –40 C
DDEXT
V
–100
–150
OL
0
–50
V
0
OH
0.5
1.0
1.5
2.0
2.5
3.0
SOURCE VOLTAGE (V)
Figure 27. Drive Current B (Low VDDEXT
)
V
–100
–150
OL
0
0.5
1.0
1.5
2.0
2.5
3.0
150
100
50
°
V
= 2.95V @ 95 C
SOURCE VOLTAGE (V)
DDEXT
DDEXT
DDEXT
°
V
V
= 3.30V @ 25 C
°
= 3.65V @ –40 C
Figure 25. Drive Current A (Low VDDEXT
)
150
100
50
0
°
V
V
= 2.95V @ 95 C
OH
DDEXT
DDEXT
°
V
V
= 3.30V @ 25 C
–50
–100
°
= 3.65V @ –40 C
DDEXT
V
OL
0
–150
0
V
OH
0.5
1.0
1.5
2.0
2.5
3.0
3.5
SOURCE VOLTAGE (V)
–50
–100
–150
Figure 28. Drive Current B (High VDDEXT
)
V
OL
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
SOURCE VOLTAGE (V)
Figure 26. Drive Current A (High VDDEXT
)
Rev. 0
|
Page 39 of 56
| March 2004
ADSP-BF531/ADSP-BF532/ADSP-BF533
100
80
60
°
V
V
V
= 2.25V @ 95 C
DDEXT
DDEXT
°
= 2.50V @ 25 C
°
V
V
V
= 2.25V @ 95 C
DDEXT
DDEXT
°
60
40
40
20
= 2.75V @ –40 C
°
DDEXT
= 2.50V @ 25 C
°
= 2.75V @ –40 C
DDEXT
20
0
0
–20
–40
–60
V
OH
–20
V
OH
–40
–60
V
OL
–80
V
OL
–100
0
0
0.5
1.0
1.5
2.0
2.5
3.0
0.5
1.0
1.5
2.0
2.5
3.0
SOURCE VOLTAGE (V)
SOURCE VOLTAGE (V)
Figure 29. Drive Current C (Low VDDEXT
)
Figure 31. Drive Current D (Low VDDEXT)
150
100
50
°
°
V
= 2.95V @ 95 C
V
= 2.95V @ 95 C
80
DDEXT
DDEXT
DDEXT
DDEXT
DDEXT
°
°
V
V
= 3.30V @ 25 C
V
V
= 3.30V @ 25 C
°
°
60
40
20
= 3.65V @ –40 C
= 3.65V @ –40 C
DDEXT
0
0
–20
–40
–60
V
OH
V
OH
–50
V
OL
V
–100
OL
–80
–150
–100
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
SOURCE VOLTAGE (V)
SOURCE VOLTAGE (V)
Figure 30. Drive Current C (High VDDEXT
)
Figure 32. Drive Current D (High VDDEXT)
Rev. 0
|
Page 40 of 56
| March 2004
ADSP-BF531/ADSP-BF532/ADSP-BF533
POWER DISSIPATION
Total power dissipation has two components: one due to inter-
nal circuitry (PINT) and one due to the switching of external
output drivers (PEXT). Table 32 shows the power dissipation for
internal circuitry (VDDINT). Internal power dissipation is depen-
dent on the instruction execution sequence and the data
operands involved.
Table 32. Internal Power Dissipation1
Test Conditions2
Parameter fCCLK
=
fCCLK
=
fCCLK
=
fCCLK
=
Unit
50 MHz 400 MHz 500 MHz 600 MHz
VDDINT
0.8 V
=
VDDINT
1.2 V
=
VDDINT
1.2 V
=
VDDINT
1.2 V
=
3
IDDTYP
26
16
160
37
190
37
220
37
mA
mA
mA
A
A
4
IDDSLEEP
4
IDDDEEPSLEEP 14
31
31
31
5
IDDHIBERNATE 50
6
IDDRTC
30
1 See EE-229: Estimating Power for ADSP-BF533 Blackfin Processors.
2 IDD data is specified for typical process parameters. All data at 25ºC.
3 Processor executing 75% dual Mac, 25% ADD with moderate data bus activity.
4 See the ADSP-BF53x Blackfin Processor Hardware Reference Manual for defini-
tions of Sleep and Deep Sleep operating modes.
5 Measured at VDDEXT = 3.65V with voltage regulator off (VDDINT = 0V).
6 Measured at VDDRTC = 3.3V at 25ºC.
The external component of total power dissipation is caused by
the switching of output pins. Its magnitude depends on:
• Number of output pins (O) that switch during each cycle
• Maximum frequency (f) at which they can switch
• Their load capacitance (C)
• Their voltage swing (VDDEXT
)
The external component is calculated using:
PEXT = O × C × V2DD × f
The frequency f includes driving the load high and then back
low. For example: DATA15–0 pins can drive high and low at a
maximum rate of 1/(2
؋
tSCLK) while in SDRAM burst mode. A typical power consumption can now be calculated for these
conditions by adding a typical internal power dissipation:
PTOTAL = PEXT + (IDD × VDDINT
)
Note that the conditions causing a worst-case PEXT differ from
those causing a worst-case PINT . Maximum PINT cannot occur
while 100% of the output pins are switching from all ones (1s) to
all zeros (0s). Note, as well, that it is not common for an applica-
tion to have 100% or even 50% of the outputs switching
simultaneously.
Rev. 0
|
Page 41 of 56
| March 2004
ADSP-BF531/ADSP-BF532/ADSP-BF533
TEST CONDITIONS
REFERENCE
SIGNAL
All timing parameters appearing in this data sheet were mea-
sured under the conditions described in this section.
tDIS_MEASURED
tENA-MEASURED
Output Enable Time
tDIS
V
tENA
Output pins are considered to be enabled when they have made
a transition from a high impedance state to the point when they
start driving. The output enable time tENA is the interval from
the point when a reference signal reaches a high or low voltage
level to the point when the output starts driving as shown in the
Output Enable/Disable diagram (Figure 33). The time
tENA_MEASURED is the interval from when the reference signal
switches to when the output voltage reaches 2.0 V (output high)
or 1.0 V (output low). Time tTRIP is the interval from when the
output starts driving to when the output reaches the 1.0 V or
2.0 V trip voltage. Time tENA is calculated as shown in the
equation:
OH
V
OH
(MEASURED)
V
(MEASURED) ؊ ⌬V
(MEASURED) + ⌬V
2.0V
1.0V
OH
(MEASURED)
V
OL
V
V
OL
OL
(MEASURED)
(MEASURED)
tDECAY
tTRIP
OUTPUT STOPS DRIVING
OUTPUT STARTS DRIVING
HIGH IMPEDANCE STATE.
TEST CONDITIONS CAUSE THIS
VOLTAGE TO BE APPROXIMATELY 1.5V.
Figure 33. Output Enable/Disable
50 OHMS
TO
OUTPUT
PIN
tENA = tENA_MEASURED – tTRIP
1.5V
30pF
If multiple pins (such as the data bus) are enabled, the measure-
ment value is that of the first pin to start driving.
Output Disable Time
Figure 34. Equivalent Device Loading for AC Measurements
(Includes All Fixtures)
Output pins are considered to be disabled when they stop driv-
ing, go into a high impedance state, and start to decay from their
output high or low voltage. The time for the voltage on the bus
to decay by ∆V is dependent on the capacitive load, CL and the
load current, IL. This decay time can be approximated by the
equation:
INPUT
OR
1.5V
1.5V
OUTPUT
Figure 35. Voltage Reference Levels for AC
tDECAY = (CL∆V) ⁄ IL
Measurements (Except Output Enable/Disable)
delay and hold specifications given should be derated by a factor
derived from these figures. The graphs in these figures may not
be linear outside the ranges shown.
The output disable time tDIS is the difference between
t
DIS_MEASURED and tDECAY as shown in Figure 33. The time
tDIS_MEASURED is the interval from when the reference signal
switches to when the output voltage decays ∆V from the mea-
sured output high or output low voltage. The time tDECAY is
calculated with test loads CL and IL, and with ∆V equal to 0.5 V.
Example System Hold Time Calculation
To determine the data output hold time in a particular system,
first calculate tDECAY using the equation given above. Choose
∆V to be the difference between the ADSP-BF531/2/3 proces-
sor’s output voltage and the input threshold for the device
requiring the hold time. A typical ∆V will be 0.4 V. CL is the
total bus capacitance (per data line), and IL is the total leakage or
three-state current (per data line). The hold time will be tDECAY
plus the minimum disable time (for example, tDSDAT for an
SDRAM write cycle).
Capacitive Loading
Output delays and holds are based on standard capacitive loads:
30 pF on all pins (see Figure 34). Figure 36 through Figure 43 on
Page 44 show how output rise time varies with capacitance. The
Rev. 0
|
Page 42 of 56
| March 2004
ADSP-BF531/ADSP-BF532/ADSP-BF533
CLKOUT (CLKOUT DRIVER), EVDD
MIN
= 2.25V,TEMPERATURE = 85°C
12
10
ABE_B[0] (133 MHZ DRIVER), EVDD
MIN
= 2.25V,TEMPERATURE = 85°C
14
12
RISE TIME
RISE TIME
8
6
4
2
0
10
8
FALL TIME
FALL TIME
6
4
2
0
0
50
100
150
200
250
LOAD CAPACITANCE (PF)
0
50
100
150
200
250
LOAD CAPACITANCE (PF)
Figure 38. Typical Output Delay or Hold for Driver B at EVDDMIN
Figure 36. Typical Output Delay or Hold for Driver A at EVDDMIN
CLKOUT (CLKOUT DRIVER), EVDD
MAX
= 3.65V,TEMPERATURE = 85°C
10
ABE0 (133 MHZ DRIVER), EVDD
MAX
= 3.65V,TEMPERATURE = 85°C
9
8
7
12
RISE TIME
10
8
RISE TIME
6
5
FALL TIME
FALL TIME
6
4
3
2
1
0
4
2
0
50
100
150
200
250
LOAD CAPACITANCE (PF)
0
0
50
100
150
200
250
LOAD CAPACITANCE (PF)
Figure 39. Typical Output Delay or Hold for Driver B at EVDDMAX
Figure 37. Typical Output Delay or Hold for Driver A at EVDDMAX
Rev. 0
|
Page 43 of 56
|
March 2004
ADSP-BF531/ADSP-BF532/ADSP-BF533
TMR0 (33 MHZ DRIVER), EVDD
MIN
= 2.25V,TEMPERATURE = 85°C
SCK (66 MHZ DRIVER), EVDD = 2.25V,TEMPERATURE = 85°C
MIN
30
25
20
15
10
5
18
16
14
12
10
8
RISE TIME
RISE TIME
FALL TIME
FALL TIME
6
4
2
0
0
0
50
100
150
200
250
0
50
100
150
200
250
LOAD CAPACITANCE (PF)
LOAD CAPACITANCE (PF)
Figure 40. Typical Output Delay or Hold for Driver C at EVDDMIN
Figure 42. Typical Output Delay or Hold for Driver D at EVDDMIN
TMR0 (33 MHZ DRIVER), EVDD
MAX
= 3.65V,TEMPERATURE = 85°C
SCK (66 MHZ DRIVER), EVDD = 3.65V,TEMPERATURE = 85°C
MAX
14
20
18
16
14
12
10
8
RISE TIME
RISE TIME
12
10
FALL TIME
FALL TIME
6
4
2
0
8
6
4
2
0
0
50
100
150
200
250
0
50
100
150
200
250
LOAD CAPACITANCE (PF)
LOAD CAPACITANCE (PF)
Figure 41. Typical Output Delay or Hold for Driver C at EVDDMAX
Figure 43. Typical Output Delay or Hold for Driver D at EVDDMAX
Rev. 0
|
Page 44 of 56
|
March 2004
ADSP-BF531/ADSP-BF532/ADSP-BF533
Table 35. Thermal Characteristics for B-169 Package
ENVIRONMENTAL CONDITIONS
To determine the junction temperature on the application
printed circuit board use:
Parameter Condition
Typical Unit
θJA
0 Linear m/s Airflow
28.6
24.6
23.8
21.75
12.7
0.78
؇C/W
؇C/W
؇C/W
؇C/W
؇C/W
؇C/W
θJMA
θJMA
θJB
1 Linear m/s Airflow
2 Linear m/s Airflow
Not applicable
TJ = TCASE + (ΨJT × PD)
where:
TJ = Junction temperature (؇C)
θJC
Not applicable
TCASE = Case temperature (؇C) measured by customer at top
center of package.
ΨJT
0 Linear m/s Airflow
ΨJT = From Table 33
PD = Power dissipation (see Power Dissipation on Page 41 for
the method to calculate PD)
Values of θJA are provided for package comparison and printed
circuit board design considerations. θJA can be used for a first
order approximation of TJ by the equation:
TJ = TA + (θJA × PD)
where:
TA = Ambient temperature (؇C)
In Table 33, airflow measurements comply with JEDEC stan-
dards JESD51-2 and JESD51-6, and the junction-to-board
measurement complies with JESD51-8. The junction-to-case
measurement complies with MIL-STD-883 (Method 1012.1).
All measurements use a 2S2P JEDEC test board.
Thermal resistance θJA in Table 33 is the figure of merit relating
to performance of the package and board in a convective envi-
ronment. θJMA represents the thermal resistance under two
conditions of airflow. θJB represents the heat extracted from the
periphery of the board. ΨJT represents the correlation between
TJ and TCASE. Values of θJB are provided for package compari-
son and printed circuit board design considerations.
Table 33. Thermal Characteristics for BC-160 Package
Parameter Condition
Typical Unit
θJA
0 Linear m/s Airflow
34.1
30.1
28.8
25.55
8.75
0.13
؇C/W
؇C/W
؇C/W
؇C/W
؇C/W
؇C/W
θJMA
θJMA
θJB
1 Linear m/s Airflow
2 Linear m/s Airflow
Not applicable
θJC
Not applicable
ΨJT
0 Linear m/s Airflow
Table 34. Thermal Characteristics for ST-176-1 Package
Parameter Condition Typical Unit
θJA
0 Linear m/s Airflow
34.9
33.0
32.0
0.50
0.75
1.00
؇C/W
؇C/W
؇C/W
؇C/W
؇C/W
؇C/W
θJMA
θJMA
ΨJT
ΨJT
ΨJT
1 Linear m/s Airflow
2 Linear m/s Airflow
0 Linear m/s Airflow
1 Linear m/s Airflow
2 Linear m/s Airflow
Rev. 0
|
Page 45 of 56
| March 2004
ADSP-BF531/ADSP-BF532/ADSP-BF533
160-LEAD BGA PINOUT
Table 36 lists the BGA pinout by signal. Table 37 on Page 47
lists the BGA pinout by ball number.
Table 36. 160-Ball BGA Pin Assignment (Alphabetically by Signal)
Signal
ABE0
Ball No.
H13
H12
J14
Signal
DATA12
DATA13
DATA14
DATA15
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
DATA8
DATA9
DR0PRI
DR0SEC
DR1PRI
DR1SEC
DT0PRI
DT0SEC
DT1PRI
DT1SEC
EMU
Ball No.
M5
N5
Signal
GND
GND
GND
GND
GND
GND
MISO
MOSI
NMI
Ball No.
L6
Signal
SCK
Ball No.
D1
ABE1
L8
SCKE
B13
C13
D13
D12
P2
ADDR1
ADDR10
ADDR11
ADDR12
ADDR13
ADDR14
ADDR15
ADDR16
ADDR17
ADDR18
ADDR19
ADDR2
ADDR3
ADDR4
ADDR5
ADDR6
ADDR7
ADDR8
ADDR9
AMS0
P5
L10
M4
M10
P14
E2
SMS
M13
M14
N14
N13
N12
M11
N11
P13
P12
P11
K14
L14
J13
P4
SRAS
P9
SWE
M8
N8
TCK
TDI
M3
N3
P8
D3
B10
D2
C1
TDO
M7
N7
TFS0
H3
PF0
TFS1
E1
P7
PF1
TMR0
L2
M6
K1
PF10
PF11
PF12
PF13
PF14
PF15
PF2
A4
A5
B5
TMR1
M1
K2
TMR2
J2
TMS
N2
G3
B6
TRST
N1
F3
A6
C6
TSCLK0
TSCLK1
TX
J1
K13
L13
K12
L12
M12
E14
F14
F13
G12
G13
E13
G14
H14
P10
N10
N4
H1
F1
H2
C2
K3
F2
PF3
C3
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDRTC
VROUT0
VROUT1
XTAL
A1
E3
PF4
B1
C7
M2
A10
A14
B11
C4
PF5
B2
C12
D5
GND
PF6
B3
AMS1
GND
PF7
B4
D9
AMS2
GND
PF8
A2
A3
C8
F12
G4
AMS3
GND
PF9
AOE
GND
C5
PPI0
PPI1
PPI2
PPI3
PPI_CLK
RESET
RFS0
RFS1
RSCLK0
RSCLK1
RTXI
RTXO
RX
J4
ARDY
GND
C11
D4
B8
J12
L7
ARE
GND
A7
B7
AWE
GND
D7
L11
P1
BG
GND
D8
C9
BGH
GND
D10
D11
F4
C10
J3
D6
BMODE0
BMODE1
BR
GND
E4
P3
GND
G2
L1
E11
J11
L4
D14
A12
B14
M9
GND
F11
G11
H4
CLKIN
GND
G1
A9
A8
L3
CLKOUT
DATA0
DATA1
DATA10
DATA11
GND
L9
GND
H11
K4
B9
N9
GND
A13
B12
A11
N6
GND
K11
L5
SA10
SCAS
E12
C14
P6
GND
Rev. 0
|
Page 46 of 56
| March 2004
ADSP-BF531/ADSP-BF532/ADSP-BF533
Table 37 lists the BGA pinout by ball number. Table 36 on
Page 46 lists the BGA pinout by signal.
Table 37. 160-Ball BGA Pin Assignment (Numerically by Ball Number)
Ball No.
A1
Signal
VDDEXT
PF8
Ball No.
C13
C14
D1
Signal
SMS
Ball No.
H1
Signal
DT0PRI
DT0SEC
TFS0
Ball No.
M3
M4
M5
M6
M7
M8
M9
M10
M11
M12
M13
M14
N1
Signal
TDI
A2
SCAS
H2
GND
A3
PF9
SCK
H3
DATA12
DATA9
DATA6
DATA3
DATA0
GND
A4
PF10
PF11
PF14
PPI2
D2
PF0
H4
GND
A5
D3
MOSI
GND
H11
H12
H13
H14
J1
GND
A6
D4
ABE1
A7
D5
VDDEXT
VDDINT
GND
ABE0
A8
RTXO
RTXI
D6
AWE
A9
D7
TSCLK0
DR0SEC
RFS0
ADDR15
ADDR9
ADDR10
ADDR11
TRST
A10
A11
A12
A13
A14
B1
GND
D8
GND
J2
XTAL
CLKIN
VROUT0
GND
D9
VDDEXT
GND
J3
D10
D11
D12
D13
D14
E1
J4
VDDEXT
VDDINT
VDDEXT
ADDR4
ADDR1
DR0PRI
TMR2
GND
J11
J12
J13
J14
K1
SWE
N2
TMS
PF4
SRAS
N3
TDO
B2
PF5
BR
N4
BMODE0
DATA13
DATA10
DATA7
DATA4
DATA1
BGH
B3
PF6
TFS1
N5
B4
PF7
E2
MISO
DT1SEC
VDDINT
VDDINT
SA10
K2
N6
B5
PF12
PF13
PPI3
E3
K3
TX
N7
B6
E4
K4
GND
N8
B7
E11
E12
E13
E14
F1
K11
K12
K13
K14
L1
GND
N9
B8
PPI1
ADDR7
ADDR5
ADDR2
RSCLK0
TMR0
N10
N11
N12
N13
N14
P1
B9
VDDRTC
NMI
ARDY
AMS0
TSCLK1
DT1PRI
DR1SEC
GND
ADDR16
ADDR14
ADDR13
ADDR12
VDDEXT
TCK
B10
B11
B12
B13
B14
C1
GND
VROUT1
SCKE
CLKOUT
PF1
F2
L2
F3
L3
RX
F4
L4
VDDINT
GND
P2
F11
F12
F13
F14
G1
GND
L5
P3
BMODE1
DATA15
DATA14
DATA11
DATA8
DATA5
DATA2
BG
C2
PF2
VDDEXT
AMS2
AMS1
RSCLK1
RFS1
L6
GND
P4
C3
PF3
L7
VDDEXT
GND
P5
C4
GND
L8
P6
C5
GND
L9
VDDINT
GND
P7
C6
PF15
VDDEXT
PPI0
G2
L10
L11
L12
L13
L14
M1
M2
P8
C7
G3
DR1PRI
VDDEXT
GND
VDDEXT
ADDR8
ADDR6
ADDR3
TMR1
P9
C8
G4
P10
P11
P12
P13
P14
C9
PPI_CLK
RESET
GND
G11
G12
G13
G14
ADDR19
ADDR18
ADDR17
GND
C10
C11
C12
AMS3
AOE
VDDEXT
ARE
EMU
Figure 44 lists the top view of the BGA ball configuration.
Figure 45 lists the bottom view of the BGA ball configuration.
Rev. 0
|
Page 47 of 56
| March 2004
ADSP-BF531/ADSP-BF532/ADSP-BF533
1
2
3
4
5
6
7
8
9
10 11 12 13 14
A
B
C
D
E
F
G
H
J
K
L
M
N
P
KEY:
V
V
GND
I/O
DDINT
DDRTC
V
V
DDEXT
ROUT
Figure 44. 160-Ball BGA Ball Configuration (Top View)
14 13 12 11 10
9
8
7
6
5
4
3
2
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
KEY:
V
V
V
GND
DDINT
DDRTC
ROUT
V
I/O
DDEXT
Figure 45. 160-Ball BGA Ball Configuration (Bottom View)
Rev. 0
|
Page 48 of 56
| March 2004
ADSP-BF531/ADSP-BF532/ADSP-BF533
169-BALL PBGA PINOUT
Table 38 lists the PBGA pinout by signal. Table 39 on Page 52
lists the PBGA pinout by ball number.
Table 38. 169-Ball PBGA Pin Assignment (Alphabetically by Signal)
Signal
Ball No. Signal
Ball No. Signal
Ball No. Signal
Ball No. Signal
Ball No.
K12
ABE [0]
H16
H17
J16
DATA [13]
T7
GND
GND
G11
H7
H8
H9
H10
H11
J7
PF [8]
PF [9]
PPI [0]
PPI [1]
PPI [2]
PPI [3]
PPI_CLK
RESET
RFS0
RFS1
RSCLK0
RSCLK1
RTCVDD
RTXI
B4
VDD
ABE [1]
DATA [14]
DATA [15]
DATA [2]
DATA [3]
DATA [4]
DATA [5]
DATA [6]
DATA [7]
DATA [8]
DATA [9]
DR0PRI
DR0SEC
DR1PRI
DR1SEC
DT0PRI
DT0SEC
DT1PRI
DT1SEC
EMU
U6
T6
A4
VDD
L12
ADDR [1]
ADDR [10]
ADDR [11]
ADDR [12]
ADDR [13]
ADDR [14]
ADDR [15]
ADDR [16]
ADDR [17]
ADDR [18]
ADDR [19]
ADDR [2]
ADDR [3]
ADDR [4]
ADDR [5]
ADDR [6]
ADDR [7]
ADDR [8]
ADDR [9]
AMS [0]
AMS [1]
AMS [2]
AMS [3]
AOE
GND
B9
VDD
M10
M11
M12
B12
N16
P17
P16
R17
R16
T17
U15
T15
U16
T14
J17
U13
T11
U12
U11
T10
U10
T9
GND
A9
VDD
GND
B8
VDD
GND
A8
VROUT
VROUT
XTAL
GND
B10
A12
N1
J1
B13
GND
J8
A13
GND
J9
GND
J10
J11
K7
U9
M2
M1
H1
H2
K2
GND
N2
J2
GND
GND
K8
F10
A10
A11
T1
GND
K9
K16
K17
L16
L17
M16
M17
N17
D17
E16
E17
F16
F17
C16
G16
G17
T13
U17
U5
GND
K10
K11
L7
RTXO
RX
GND
K1
GND
SA10
SCAS
SCK
B15
A16
D1
B14
A17
A15
B17
U4
U3
T4
F1
GND
L8
F2
GND
L9
U1
B2
GND
L10
L11
M9
T16
E2
SCKE
SMS
EVDD
GND
EVDD
F6
GND
SRAS
SWE
EVDD
F7
GND
EVDD
F8
MISO
MOSI
NMI
TCK
EVDD
F9
E1
TDI
EVDD
G6
H6
J6
B11
D2
C1
B5
TDO
ARDY
EVDD
PF [0]
PF [1]
PF [10]
PF [11]
PF [12]
PF [13]
PF [14]
PF [15]
PF [2]
PF [3]
PF [4]
PF [5]
PF [6]
PF [7]
TFS0
L1
ARE
EVDD
TFS1
G2
R1
AWE
EVDD
K6
TMR0
TMR1
TMR2
TMS
BG
EVDD
L6
A5
A6
B6
P2
BGH
EVDD
M6
M7
M8
T2
P1
BMODE [0]
BMODE [1]
BR
EVDD
T3
T5
EVDD
A7
B7
TRST
TSCLK0
TSCLK1
TX
U2
L2
C17
A14
D16
U14
T12
T8
EVDD
CLKIN
GND
B16
F11
G7
G8
G9
G10
B1
G1
R2
CLKOUT
DATA [0]
DATA [1]
DATA [10]
DATA [11]
GND
C2
A1
A2
B3
GND
VDD
F12
G12
H12
J12
GND
VDD
GND
VDD
U8
GND
A3
VDD
Rev. 0
|
Page 49 of 56
|
March 2004
ADSP-BF531/ADSP-BF532/ADSP-BF533
Table 39 lists the PBGA pinout by ball number. Table 38 on
Page 51 lists the PBGA pinout by signal.
Table 39. 169-Ball PBGA Pin Assignment (Numerically by Ball Number)
Ball No. Signal
Ball No. Signal
Ball No. Signal
Ball No. Signal
Ball No. Signal
A1
PF [4]
PF [5]
PF [7]
PF [9]
PF [11]
PF [12]
PF [14]
PPI [3]
PPI [1]
RTXI
D16
D17
E1
CLKOUT
AMS [0]
MOSI
MISO
AMS [1]
AMS [2]
DT1PRI
DT1SEC
EVDD
EVDD
EVDD
EVDD
RTCVDD
GND
J2
RSCLK1
EVDD
GND
M12
M16
M17
N1
VDD
U8
DATA [11]
A2
J6
ADDR [7]
ADDR [8]
RFS0
U9
DATA [9]
DATA [7]
DATA [5]
DATA [4]
DATA [2]
DATA [0]
ADDR [16]
ADDR [18]
BGH
A3
J7
U10
U11
U12
U13
U14
U15
U16
U17
A4
E2
J8
GND
A5
E16
E17
F1
J9
GND
N2
RSCLK0
ADDR [10]
ADDR [9]
TMR2
A6
J10
J11
J12
J16
J17
K1
GND
N16
N17
P1
A7
GND
A8
F2
VDD
A9
F6
ADDR [1]
ADDR [2]
DT0SEC
DT0PRI
EVDD
GND
P2
TMR1
A10
A11
A12
A13
A14
A15
A16
A17
B1
F7
P16
P17
R1
ADDR [12]
ADDR [11]
TMR0
RTXO
RESET
XTAL
CLKIN
SRAS
F8
F9
K2
F10
F11
F12
F16
F17
G1
K6
R2
TX
K7
R16
R17
T1
ADDR [14]
ADDR [13]
RX
VDD
K8
GND
SCAS
SMS
AMS [3]
AOE
K9
GND
K10
K11
K12
K16
K17
L1
GND
T2
EVDD
PF [2]
EVDD
PF [6]
PF [8]
PF [10]
PF [13]
PF [15]
PPI [2]
PPI [0]
PPI_CLK
NMI
TSCLK1
TFS1
GND
T3
TMS
B2
G2
VDD
T4
TDO
B3
G6
EVDD
GND
ADDR [3]
ADDR [4]
TFS0
T5
BMODE [1]
DATA [15]
DATA [13]
DATA [10]
DATA [8]
DATA [6]
DATA [3]
DATA [1]
BG
B4
G7
T6
B5
G8
GND
T7
B6
G9
GND
L2
TSCLK0
EVDD
GND
T8
B7
G10
G11
G12
G16
G17
H1
GND
L6
T9
B8
GND
L7
T10
T11
T12
T13
T14
T15
T16
T17
U1
B9
VDD
L8
GND
B10
B11
B12
B13
B14
B15
B16
B17
C1
ARE
L9
GND
AWE
L10
L11
L12
L16
L17
M1
M2
M6
M7
M8
M9
M10
M11
GND
VROUT
VROUT
SCKE
DR1PRI
DR1SEC
EVDD
GND
GND
ADDR [19]
ADDR [17]
GND
H2
VDD
H6
ADDR [5]
ADDR [6]
DR0SEC
DR0PRI
EVDD
EVDD
EVDD
GND
SA10
H7
ADDR [15]
EMU
GND
H8
GND
SWE
H9
GND
U2
TRST
PF [1]
PF [3]
ARDY
BR
H10
H11
H12
H16
H17
J1
GND
U3
TDI
C2
GND
U4
TCK
C16
C17
D1
VDD
U5
BMODE [0]
DATA [14]
DATA [12]
DATA [11]
ABE [0]
ABE [1]
RFS1
U6
SCK
VDD
U7
D2
PF [0]
VDD
U8
Rev. 0
|
Page 50 of 56
|
March 2004
ADSP-BF531/ADSP-BF532/ADSP-BF533
176-LEAD LQFP PINOUT
Table 40 lists the LQFP pinout by signal. Table 41 on Page 52
lists the LQFP pinout by lead number.
Table 40. 176-Lead LQFP Pin Assignment (Alphabetically by Signal)
Signal
ABE0
Lead No.
151
150
149
137
136
135
127
126
125
124
123
122
121
148
147
146
142
141
140
139
138
161
160
159
158
154
162
153
152
119
120
96
Signal
DATA11
DATA12
DATA13
DATA14
DATA15
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
DATA8
DATA9
DR0PRI
DR0SEC
DR1PRI
DR1SEC
DT0PRI
DT0SEC
DT1PRI
DT1SEC
EMU
Lead No.
102
101
100
99
Signal
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
MISO
MOSI
NMI
Lead No.
88
Signal
PPI_CLK
PPI0
Lead No.
21
Signal
Lead No.
71
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDRTC
VROUT1
VROUT2
XTAL
ABE1
89
22
93
ADDR1
ADDR10
ADDR11
ADDR12
ADDR13
ADDR14
ADDR15
ADDR16
ADDR17
ADDR18
ADDR19
ADDR2
ADDR3
ADDR4
ADDR5
ADDR6
ADDR7
ADDR8
ADDR9
AMS0
90
PPI1
23
107
118
134
145
156
171
25
91
PPI2
24
98
92
PPI3
26
114
113
112
110
109
108
105
104
74
97
RESET
RFS0
13
106
117
128
129
130
131
132
133
144
155
170
174
175
176
54
75
RFS1
64
RSCLK0
RSCLK1
RTXI
76
65
52
17
66
RTXO
RX
16
80
82
111
143
157
168
18
SA10
SCAS
SCK
164
166
53
73
63
62
SCKE
173
172
167
165
94
68
SMS
5
67
SRAS
SWE
4
59
11
58
TCK
83
55
TDI
86
AMS1
GND
1
14
TDO
87
AMS2
GND
2
PF0
51
TFS0
69
AMS3
GND
3
PF1
50
TFS1
60
AOE
GND
7
PF10
PF11
PF12
PF13
PF14
PF15
PF2
34
TMR0
TMR1
TMR2
TMS
79
ARDY
GND
8
33
78
ARE
GND
9
32
77
AWE
GND
15
29
85
BG
GND
19
28
TRST
84
BGH
GND
30
27
TSCLK0
TSCLK1
TX
72
BMODE0
BMODE1
BR
GND
39
49
61
95
GND
40
PF3
48
81
163
10
GND
41
PF4
47
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
6
CLKIN
GND
42
PF5
46
12
CLKOUT
DATA0
DATA1
DATA10
169
116
115
103
GND
43
PF6
38
20
GND
44
PF7
37
31
GND
56
PF8
36
45
GND
70
PF9
35
57
Rev. 0
|
Page 51 of 56
| March 2004
ADSP-BF531/ADSP-BF532/ADSP-BF533
Table 41 lists the LQFP pinout by lead number. Table 40 on
Page 51 lists the LQFP pinout by signal.
Table 41. 176-Lead LQFP Pin Assignment (Numerically by Lead Number)
Lead No.
1
Signal
GND
Lead No.
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
Signal
GND
Lead No.
81
Signal
TX
Lead No.
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
Signal
ADDR19
ADDR18
ADDR17
ADDR16
ADDR15
ADDR14
ADDR13
GND
Lead No.
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
Signal
AMS0
ARDY
BR
2
GND
GND
82
RX
3
GND
GND
83
EMU
4
VROUT2
VROUT1
VDDEXT
GND
GND
84
TRST
SA10
SWE
5
VDDEXT
PF5
85
TMS
6
86
TDI
SCAS
SRAS
VDDINT
CLKOUT
GND
7
PF4
87
TDO
8
GND
PF3
88
GND
9
GND
PF2
89
GND
GND
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
CLKIN
XTAL
VDDEXT
RESET
NMI
PF1
90
GND
GND
PF0
91
GND
GND
VDDEXT
SMS
VDDINT
SCK
92
GND
GND
93
VDDEXT
TCK
GND
SCKE
GND
MISO
94
VDDEXT
ADDR12
ADDR11
ADDR10
ADDR9
ADDR8
ADDR7
ADDR6
ADDR5
VDDINT
GND
GND
MOSI
95
BMODE1
BMODE0
GND
GND
RTXO
RTXI
GND
96
GND
VDDEXT
DT1SEC
DT1PRI
TFS1
97
VDDRTC
GND
98
DATA15
DATA14
DATA13
DATA12
DATA11
DATA10
DATA9
DATA8
GND
99
VDDEXT
PPI_CLK
PPI0
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
TSCLK1
DR1SEC
DR1PRI
RFS1
PPI1
PPI2
VDDINT
PPI3
RSCLK1
VDDINT
DT0SEC
DT0PRI
TFS0
VDDEXT
ADDR4
ADDR3
ADDR2
ADDR1
ABE1
PF15
VDDEXT
DATA7
DATA6
DATA5
VDDINT
DATA4
DATA3
DATA2
DATA1
DATA0
GND
PF14
PF13
GND
GND
VDDEXT
PF12
VDDEXT
TSCLK0
DR0SEC
DR0PRI
RFS0
ABE0
AWE
PF11
ARE
PF10
AOE
PF9
GND
PF8
RSCLK0
TMR2
TMR1
TMR0
VDDINT
VDDEXT
VDDINT
AMS3
PF7
PF6
VDDEXT
BG
GND
AMS2
GND
BGH
AMS1
Rev. 0
|
Page 52 of 56
| March 2004
ADSP-BF531/ADSP-BF532/ADSP-BF533
OUTLINE DIMENSIONS
Dimensions in Figure 46—160-Ball Plastic Ball Grid Array,
mini-BGA (BC-160), Figure 47—176-LEAD LQFP (ST-176-1)
and Figure 48—169-Ball Plastic Ball Grid Array, mini-BGA
(B-169) are shown in millimeters.
12.00 BSC SQ
A1 CORNER
INDEX AREA
1
14 12 10
13 11
8
6
4
2
9
7
5
3
A
B
C
D
E
F
BALL A1
INDICATOR
10.40
BSC
SQ
G
H
J
K
L
M
N
P
TOP VIEW
0.80 BSC
BALL PITCH
BOTTOM VIEW
1.31
1.21
1.11
1.70
DETAIL A
MAX
SEATING
PLANE
0.12
MAX
COPLANARITY
0.55
0.50
0.45
0.40 NOM
(NOTE 3)
NOTES
1. DIMENSIONS ARE IN MILLIMETERS.
BALL DIAMETER
2. COMPLIES WITH JEDEC REGISTERED OUTLINE
MO-205, VARIATION AE.
DETAIL A
3. MINIMUM BALL HEIGHT 0.25.
Figure 46. 160-Ball Plastic Ball Grid Array, mini-BGA (BC-160)
Rev. 0
|
Page 53 of 56
| March 2004
ADSP-BF531/ADSP-BF532/ADSP-BF533
26.00 BSC SQ
24.00 BSC SQ
0.75
0.60
0.45
133
132
176
1
PIN 1
0.27
0.22
0.17
SEATING
PLANE
0.08 MAX LEAD
COPLANARITY
0.15
0.05
1.45
89
88
44
45
1.40
1.35
1.60 MAX
0.50 BSC
LEAD PITCH
DETAIL A
DETAIL A
TOP VIEW (PINS DOWN)
NOTES
1. DIMENSIONS IN MILLIMETERS
2. ACTUAL POSITION OF EACH LEAD IS WITHIN 0.08 OF ITS
IDEAL POSITION, WHEN MEASURED IN THE LATERAL DIRECTION.
3. CENTER DIMENSIONS ARE NOMINAL
Figure 47. 176-LEAD LQFP (ST-176-1)
Rev. 0
|
Page 54 of 56
| March 2004
ADSP-BF531/ADSP-BF532/ADSP-BF533
BOTTOM VIEW
16.00 BSC SQ
A1 BALL PAD CORNER
19.00 BSC SQ
1.00 BSC
BALL PITCH
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
16 14 12 10
17 15 13 11
8
6
4
2
9
7
5
3
1
TOP VIEW
0.40 MIN
2.50
2.23
1.97
SIDE VIEW
0.20 MAX
COPLANARITY
DETAIL A
SEATING PLANE
0.70
0.60
0.50
DETAIL A
BALL DIAMETER
NOTES
1. DIMENSIONS ARE IN MILLIMETERS.
2. COMPLIES WITH JEDEC REGISTERED OUTLINE
MS-034, VARIATION AAG-2
.
3. MINIMUM BALL HEIGHT 0.40
Figure 48. 169-Ball Plastic Ball Grid Array, mini-BGA (B-169)
Rev. 0
|
Page 55 of 56
| March 2004
ADSP-BF531/ADSP-BF532/ADSP-BF533
ORDERING GUIDE
Part Number
Temperature Package Description
Range
Instruction Operating Voltage
Rate (Max)
(Ambient )
ADSP-BF533SKBC600 0ºC to 70ºC
ADSP-BF533SBBC500 –40ºC to 85ºC Chip Scale Package Ball Grid Array (mini-BGA) BC-160 500 MHz
ADSP-BF533SBBZ5001 –40ºC to 85ºC Plastic Ball Grid Array (PBGA) B-169
500 MHz
ADSP-BF532SBBC400 –40ºC to 85ºC Chip Scale Package Ball Grid Array (mini-BGA) BC-160 400 MHz
Chip Scale Package Ball Grid Array (mini-BGA) BC-160 600 MHz
1.2 V internal, 2.5 V or 3.3 V I/O
1.2 V internal, 2.5 V or 3.3 V I/O
1.2 V internal, 2.5 V or 3.3 V I/O
1.2 V internal, 2.5 V or 3.3 V I/O
1.2 V internal, 2.5 V or 3.3 V I/O
1.2 V internal, 2.5 V or 3.3 V I/O
1.2 V internal, 2.5 V or 3.3 V I/O
1.2 V internal, 2.5 V or 3.3 V I/O
1.2 V internal, 2.5 V or 3.3 V I/O
ADSP-BF532SBST400 –40ºC to 85ºC Quad Flatpack (LQFP) ST-176-1
ADSP-BF532SBBZ4001 –40ºC to 85ºC Plastic Ball Grid Array (PBGA) B-169
400 MHz
400 MHz
ADSP-BF531SBBC400 –40ºC to 85ºC Chip Scale Package Ball Grid Array (mini-BGA) BC-160 400 MHz
ADSP-BF531SBST400 –40ºC to 85ºC Quad Flatpack (LQFP) ST-176-1
ADSP-BF531SBBZ4001 –40ºC to 85ºC Plastic Ball Grid Array (PBGA) B-169
1 Z = Pb-free part.
400 MHz
400 MHz
©
2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D03728-0-3/04(0)
Rev. 0
|
Page 56 of 56
| March 2004
相关型号:
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IC 16-BIT, 33.33 MHz, OTHER DSP, PBGA160, PLASTIC, MO-025AE, BGA-160, Digital Signal Processor
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ADSP-BF533SKBC600X
IC 16-BIT, 33.33 MHz, OTHER DSP, PBGA160, PLASTIC, MO-025AE, BGA-160, Digital Signal Processor
ADI
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IC 16-BIT, 40 MHz, OTHER DSP, PBGA160, 12 X 12 MM, 1.70 MM HEIGHT, MO-205AE, CSPBGA-160, Digital Signal Processor
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