ADSP-BF534BBCZ-4A1 [ADI]
IC 16-BIT, 50 MHz, OTHER DSP, PBGA182, LEAD FREE, MO-205AE, MBGA-182, Digital Signal Processor;
| 型号： | ADSP-BF534BBCZ-4A1 |
| 厂家： | 
ADI |
| 描述： | IC 16-BIT, 50 MHz, OTHER DSP, PBGA182, LEAD FREE, MO-205AE, MBGA-182, Digital Signal Processor |
| 文件： | 总60页 (文件大小：3350K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Blackfin®
Embedded Processor
a
Preliminary Technical Data
FEATURES
ADSP-BF534
Two Dual-Channel Memory DMA Controllers
Memory Management Unit Providing Memory Protection
Up to 500 MHz High-Performance Blackfin Processor
Two 16-Bit MACs, Two 40-Bit ALUs, Four 8-Bit Video
ALUs, 40-Bit Shifter
RISC-Like Register and Instruction Model for Ease of
Programming and Compiler-Friendly Support
Advanced Debug, Trace, and Performance-Monitoring
0.8 V to 1.2 V Core VDD with On-chip Voltage Regulation
2.5 V and 3.3 V-Tolerant I/O with Specific 5 V-Tolerant Pins
182-Ball MBGA and 208-Ball Sparse MBGA Packages
Lead Bearing and Lead Free Package Choices
PERIPHERALS
Controller Area Network (CAN) 2.0B Interface
Parallel Peripheral Interface (PPI), Supporting ITU-R 656
Video Data Formats
Two Dual-Channel, Full-Duplex Synchronous Serial Ports
(SPORTs), Supporting Eight Stereo I2S Channels
12 Peripheral DMAs
Two Memory-to-Memory DMAs With External Request Lines
Event Handler With 32 Interrupt Inputs
Serial Peripheral Interface (SPI)-Compatible
Two UARTs with IrDA® Support
MEMORY
132K Bytes of On-Chip Memory:
16K Bytes of Instruction SRAM/Cache
48K Bytes of Instruction SRAM
32K Bytes of Data SRAM/Cache
32K Bytes of Data SRAM
Two-Wire Interface (TWI) Controller
Eight 32-Bit Timer/Counters with PWM Support
Real-Time Clock (RTC) and Watchdog Timer
32-Bit Core Timer
48 General-Purpose I/Os (GPIOs), 8 with High Current Drivers
On-Chip PLL Capable of 1x to 63x Frequency Multiplication
Debug/JTAG Interface
4K Bytes of Scratchpad SRAM
External Memory Controller with Glueless Support for
SDRAM and Asynchronous 8/16-Bit Memories
Flexible Booting Options from External Flash, SPI and TWI
Memory or from SPI, TWI, and UART Host Devices
EVENT
JTAG TEST AND
CONTROLLER/
EMULATION
WATCHDOG TIMER
CORE TIMER
RTC
CAN
VOLTAGE
REGULATOR
B
PORT
TWI
J
SPORT0
L1
L1
MMU
INSTRUCTION
DATA
MEMORY
MEMORY
SPORT1
GPIO
PORT
G
PPI
CORE / SYSTEM BUS INTERFACE
UART 0-1
GPIO
PORT
F
DMA
CONTROLLER
SPI
TIMERS 0-7
GPIO
PORT
H
BOOT ROM
EXTERNAL PORT
FLASH, SDRAM
CONTROL
Figure 1. Functional Block Diagram
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Rev. PrE
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
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Specifications subject to change without notice. No license is granted by implication
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Tel:781/329-4700
Fax:781/461-3113
www.analog.com
© 2005 Analog Devices, Inc. All rights reserved.
ADSP-BF534
Preliminary Technical Data
TABLE OF CONTENTS
General Description ................................................. 3
Portable Low-Power Architecture ............................. 3
System Integration ................................................ 3
ADSP-BF534 Processor Peripherals ........................... 3
Blackfin Processor Core .......................................... 4
Memory Architecture ............................................ 4
Internal (On-chip) Memory ................................. 4
External (Off-Chip) Memory ................................ 5
I/O Memory Space ............................................. 5
Booting ........................................................... 5
Event Handling ................................................. 6
Core Event Controller (CEC) ................................ 6
System Interrupt Controller (SIC) .......................... 6
Event Control ................................................... 7
DMA Controllers .................................................. 8
Real-Time Clock (RTC) .......................................... 8
Watchdog Timer .................................................. 9
Timers ............................................................... 9
Serial Ports (SPORTs) ............................................ 9
Serial Peripheral Interface (SPI) Port ....................... 10
UART Ports (UARTs) .......................................... 10
Controller Area Network (CAN) ............................ 10
TWI Controller Interface ...................................... 11
Ports ................................................................ 11
General-Purpose I/O (GPIO) .............................. 11
Parallel Peripheral Interface (PPI) ........................... 11
Dynamic Power Management ................................ 12
Full-On Operating Mode – Maximum Performance . 12
Active Operating Mode – Moderate Power Savings .. 12
Designing an Emulator-Compatible Processor
Board (Target) ................................................. 16
Related Documents .............................................. 16
Pin Descriptions .................................................... 17
Specifications ........................................................ 20
Recommended Operating Conditions ...................... 20
Absolute Maximum Ratings ................................... 22
ESD Sensitivity ................................................... 22
Timing Specifications ........................................... 23
Asynchronous Memory Read Cycle Timing ............ 25
Asynchronous Memory Write Cycle Timing ........... 26
SDRAM Interface Timing .................................. 27
External Port Bus Request and Grant Cycle Timing .. 28
External DMA Request Timing ............................ 29
Parallel Peripheral Interface Timing ...................... 30
Serial Ports ..................................................... 31
Serial Peripheral Interface (SPI) Port—Master
Timing ........................................................36
Serial Peripheral Interface (SPI) Port—Slave Timing . 37
Universal Asynchronous Receiver-Transmitter
(UART) Ports—Receive and Transmit Timing ..... 38
General-Purpose Port Timing ............................. 39
Timer Cycle Timing .......................................... 40
JTAG Test And Emulation Port Timing ................. 41
TWI Controller Timing ..................................... 42
Output Drive Currents ......................................... 46
Power Dissipation ............................................... 49
Test Conditions .................................................. 49
Output Enable Time ......................................... 49
Output Disable Time ......................................... 50
Example System Hold Time Calculation ................ 50
Environmental Conditions .................................... 51
182-Ball Mini-BGA Pinout ....................................... 52
208-Ball Sparse Mini-BGA Pinout .............................. 55
Outline Dimensions ................................................ 58
Ordering Guide ..................................................... 59
Sleep Operating Mode – High Dynamic
Power Savings .............................................. 12
Deep Sleep Operating Mode – Maximum Dynamic
Power Savings .............................................. 12
Hibernate Operating Mode – Maximum Static Power
Savings ....................................................... 12
Power Savings ................................................. 12
Voltage Regulation .............................................. 13
Clock Signals ..................................................... 13
Booting Modes ................................................... 15
Instruction Set Description ................................... 15
Development Tools ............................................. 16
EZ-KIT Lite Evaluation Board ............................ 16
Rev. PrE
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Preliminary Technical Data
ADSP-BF534
REVISION HISTORY
Revision PrE: Corrections to PrD because of changes to Order-
ing Guide, changes to recommended operating conditions,
other minor corrections.
Related Documents ................................................. 16
Recommended Operating Conditions ......................... 20
Figure 8 ............................................................... 22
Tables 10 and 11 .................................................... 23
Figures 42 and 43 ....................................................54
Table 44 ................................................................55
Table 45 ................................................................56
Figures 44 and 45 ....................................................57
Figures 46 and 47 ....................................................58
Ordering Guide ..................................................... 59
Changes to:
Figure 2 ................................................................. 5
Dynamic Power Management .................................... 12
Clock Signals ......................................................... 13
Figure 6 ................................................................ 14
Booting Modes ....................................................... 15
Development Tools ................................................. 16
GENERAL DESCRIPTION
The ADSP-BF534 processor is a member of the Blackfin family
of products, incorporating the Analog Devices/Intel Micro Sig-
nal Architecture (MSA). Blackfin processors combine a dual-
MAC state-of-the-art signal processing engine, the advantages
of a clean, orthogonal RISC-like microprocessor instruction set,
and single-instruction, multiple-data (SIMD) multimedia capa-
bilities into a single instruction-set architecture.
SYSTEM INTEGRATION
The ADSP-BF534 processor is a highly integrated system-on-a-
chip solutions for the next generation of embedded network
connected applications. By combining industry-standard inter-
faces with a high performance signal processing core, users can
develop cost-effective solutions quickly without the need for
costly external components. The system peripherals include a
CAN 2.0B controller, a TWI controller, two UART ports, an SPI
port, two serial ports (SPORTs), nine general purpose 32-bit
timers (eight with PWM capability), a real-time clock, a watch-
dog timer, and a Parallel Peripheral Interface.
Specific performance and memory configuration is shown in
Table 1.
Table 1. Processor Comparison
ADSP-BF534
ADSP-BF534 PROCESSOR PERIPHERALS
Maximum performance
Instruction SRAM/Cache
Instruction SRAM
Data SRAM/Cache
Data SRAM
500 MHz
16K bytes
48K bytes
32K bytes
32K bytes
4K bytes
The ADSP-BF534 processor contains a rich set of peripherals
connected to the core via several high bandwidth buses, provid-
ing flexibility in system configuration as well as excellent overall
system performance (see the block diagram on Page 1). The
general-purpose peripherals include functions such as UARTs,
SPI, TWI, Timers with PWM (Pulse Width Modulation) and
pulse measurement capability, general purpose I/O pins, a Real-
Time Clock, and a Watchdog Timer. This set of functions satis-
fies a wide variety of typical system support needs and is
augmented by the system expansion capabilities of the part. The
ADSP-BF534 processor contains dedicated network communi-
cation modules and high-speed serial and parallel ports, an
interrupt controller for flexible management of interrupts from
the on-chip peripherals or external sources, and power manage-
ment control functions to tailor the performance and power
characteristics of the processor and system to many application
scenarios.
Scratchpad
By integrating a rich set of industry-leading system peripherals
and memory, Blackfin processors are the platform of choice for
next-generation applications that require RISC-like program-
mability, multimedia support and leading-edge signal
processing in one integrated package.
PORTABLE LOW-POWER ARCHITECTURE
Blackfin processors provide world-class power management
and performance. Blackfin processors are designed in a low
power and low voltage design methodology and feature on-chip
Dynamic Power Management, the ability to vary both the volt-
age and frequency of operation to significantly lower overall
power consumption. Varying the voltage and frequency can
result in a substantial reduction in power consumption, com-
pared with just varying the frequency of operation. This
translates into longer battery life for portable appliances.
All of the peripherals, except for general-purpose I/O, CAN,
TWI, Real-Time Clock, and timers, are supported by a flexible
DMA structure. There are also separate memory DMA channels
dedicated to data transfers between the processor's various
memory spaces, including external SDRAM and asynchronous
memory. Multiple on-chip buses running at up to 133 MHz
provide enough bandwidth to keep the processor core running
along with activity on all of the on-chip and external
peripherals.
Rev. PrE
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July 2005
ADSP-BF534
Preliminary Technical Data
The ADSP-BF534 processor includes an on-chip voltage regula-
tor in support of the ADSP-BF534 processor Dynamic Power
Management capability. The voltage regulator provides a range
of core voltage levels when supplied from a single 2.25 V to
3.6 V input. The voltage regulator can be bypassed at the user's
discretion.
Blackfin processors support a modified Harvard architecture in
combination with a hierarchical memory structure. Level 1 (L1)
memories are those that typically operate at the full processor
speed with little or no latency. At the L1 level, the instruction
memory holds instructions only. The two data memories hold
data, and a dedicated scratchpad data memory stores stack and
local variable information.
BLACKFIN PROCESSOR CORE
In addition, multiple L1 memory blocks are provided, offering a
configurable mix of SRAM and cache. The Memory Manage-
ment Unit (MMU) provides memory protection for individual
tasks that may be operating on the core and can protect system
registers from unintended access.
As shown in Figure 2 on Page 5, the Blackfin processor core
contains two 16-bit multipliers, two 40-bit accumulators, two
40-bit ALUs, four video ALUs, and a 40-bit shifter. The compu-
tation units process 8-bit, 16-bit, or 32-bit data from the register
file.
The architecture provides three modes of operation: User mode,
Supervisor mode, and Emulation mode. User mode has
restricted access to certain system resources, thus providing a
protected software environment, while Supervisor mode has
unrestricted access to the system and core resources.
The compute register file contains eight 32-bit registers. When
performing compute operations on 16-bit operand data, the
register file operates as 16 independent 16-bit registers. All
operands for compute operations come from the multiported
register file and instruction constant fields.
The Blackfin processor instruction set has been optimized so
that 16-bit opcodes represent the most frequently used instruc-
tions, resulting in excellent compiled code density. Complex
DSP instructions are encoded into 32-bit opcodes, representing
fully featured multifunction instructions. Blackfin processors
support a limited multi-issue capability, where a 32-bit instruc-
tion can be issued in parallel with two 16-bit instructions,
allowing the programmer to use many of the core resources in a
single instruction cycle.
Each MAC can perform a 16-bit by 16-bit multiply in each
cycle, accumulating the results into the 40-bit accumulators.
Signed and unsigned formats, rounding, and saturation are
supported.
The ALUs perform a traditional set of arithmetic and logical
operations on 16-bit or 32-bit data. In addition, many special
instructions are included to accelerate various signal processing
tasks. These include bit operations such as field extract and pop-
ulation count, modulo 232 multiply, divide primitives, saturation
and rounding, and sign/exponent detection. The set of video
instructions include byte alignment and packing operations, 16-
bit and 8-bit adds with clipping, 8-bit average operations, and 8-
bit subtract/absolute value/accumulate (SAA) operations. Also
provided are the compare/select and vector search instructions.
The Blackfin processor assembly language uses an algebraic syn-
tax for ease of coding and readability. The architecture has been
optimized for use in conjunction with the C/C++ compiler,
resulting in fast and efficient software implementations.
MEMORY ARCHITECTURE
For certain instructions, two 16-bit ALU operations can be per-
formed simultaneously on register pairs (a 16-bit high half and
16-bit low half of a compute register). By also using the second
ALU, quad 16-bit operations are possible.
The ADSP-BF534 processor views memory as a single unified
4G byte address space, using 32-bit addresses. All resources,
including internal memory, external memory, and I/O control
registers, occupy separate sections of this common address
space. The memory portions of this address space are arranged
in a hierarchical structure to provide a good cost/performance
balance of some very fast, low-latency on-chip memory as cache
or SRAM, and larger, lower-cost and performance off-chip
memory systems. See Figure 3 on Page 6.
The 40-bit shifter can perform shifts and rotates and is used to
support normalization, field extract, and field deposit
instructions.
The program sequencer controls the flow of instruction execu-
tion, including instruction alignment and decoding. For
program flow control, the sequencer supports PC relative and
indirect conditional jumps (with static branch prediction), and
subroutine calls. Hardware is provided to support zero-over-
head looping. The architecture is fully interlocked, meaning that
the programmer need not manage the pipeline when executing
instructions with data dependencies.
The on-chip L1 memory system is the highest-performance
memory available to the Blackfin processor. The off-chip mem-
ory system, accessed through the External Bus Interface Unit
(EBIU), provides expansion with SDRAM, flash memory, and
SRAM, optionally accessing up to 516M bytes of physical
memory.
The memory DMA controller provides high-bandwidth data-
movement capability. It can perform block transfers of code or
data between the internal memory and the external memory
spaces.
The address arithmetic unit provides two addresses for simulta-
neous dual fetches from memory. It contains a multiported
register file consisting of four sets of 32-bit Index, Modify,
Length, and Base registers (for circular buffering), and eight
additional 32-bit pointer registers (for C-style indexed stack
manipulation).
Internal (On-chip) Memory
The ADSP-BF534 processor has three blocks of on-chip mem-
ory providing high-bandwidth access to the core.
Rev. PrE
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July 2005
Preliminary Technical Data
ADSP-BF534
ADDRESS ARITHMETIC UNIT
SP
FP
P5
P4
P3
P2
P1
P0
I3
I2
I1
I0
L3
L2
L1
L0
B3
B2
B1
B0
M3
M2
M1
M0
DAG1
DAG0
DA1 32
DA0 32
32
PREG
32
RAB
SD 32
LD1 32
LD0 32
ASTAT
32
32
SEQUENCER
R7.H
R6.H
R5.H
R4.H
R3.H
R2.H
R1.H
R0.H
R7.L
R6.L
R5.L
R4.L
R3.L
R2.L
R1.H
R0.L
ALIGN
16
16
8
8
8
8
DECODE
BARREL
SHIFTER
LOOP BUFFER
40
40
40 40
A0
A1
CONTROL
UNIT
32
32
DATA ARITHMETIC UNIT
Figure 2. Blackfin Processor Core
The first block is the L1 instruction memory, consisting of
64K bytes SRAM, of which 16K bytes can be configured as a
four-way set-associative cache. This memory is accessed at full
processor speed.
The asynchronous memory controller can be programmed to
control up to four banks of devices with very flexible timing
parameters for a wide variety of devices. Each bank occupies a
1M byte segment regardless of the size of the devices used, so
that these banks will only be contiguous if each is fully popu-
lated with 1M byte of memory.
The second on-chip memory block is the L1 data memory, con-
sisting of two banks of 32K bytes each. Each memory bank is
configurable, offering both Cache and SRAM functionality. This
memory block is accessed at full processor speed.
I/O Memory Space
The ADSP-BF534 processor does not define a separate I/O
space. All resources are mapped through the flat 32-bit address
space. On-chip I/O devices have their control registers mapped
into memory-mapped registers (MMRs) at addresses near the
top of the 4G byte address space. These are separated into two
smaller blocks, one which contains the control MMRs for all
core functions, and the other which contains the registers
needed for setup and control of the on-chip peripherals outside
of the core. The MMRs are accessible only in supervisor mode
and appear as reserved space to on-chip peripherals.
The third memory block is a 4K byte scratchpad SRAM which
runs at the same speed as the L1 memories, but is only accessible
as data SRAM and cannot be configured as cache memory.
External (Off-Chip) Memory
External memory is accessed via the EBIU. This 16-bit interface
provides a glueless connection to a bank of synchronous DRAM
(SDRAM) as well as up to four banks of asynchronous memory
devices including flash, EPROM, ROM, SRAM, and memory
mapped I/O devices.
Booting
The PC133-compliant SDRAM controller can be programmed
to interface to up to 512M bytes of SDRAM. A separate row can
be open for each SDRAM internal bank and the SDRAM con-
troller supports up to 4 internal SDRAM banks, improving
overall performance.
The ADSP-BF534 processor contains a small on-chip Boot Ker-
nel, which configures the appropriate peripheral for booting. If
the ADSP-BF534 processor is configured to boot from Boot
Rev. PrE
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Page 5 of 60
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July 2005
ADSP-BF534
Preliminary Technical Data
• Exceptions – Events that occur synchronously to program
flow (i.e., the exception will be taken before the instruction
is allowed to complete). Conditions such as data alignment
violations and undefined instructions cause exceptions.
0xFFFF FFFF
0xFFE0 0000
0xFFC0 0000
0xFFB0 1000
0xFFB0 0000
0xFFA1 4000
0xFFA1 0000
0xFFA0 C000
0xFFA0 8000
CORE MMR REGISTERS (2M BYTE)
SYSTEM MMR REGISTERS (2M BYTE)
RESERVED
• Interrupts – Events that occur asynchronously to program
flow. They are caused by input pins, timers, and other
peripherals, as well as by an explicit software instruction.
SCRATCHPAD SRAM (4K BYTE)
RESERVED
INSTRUCTION SRAM / CACHE (16K BYTE)
RESERVED
Each event type has an associated register to hold the return
address and an associated return-from-event instruction. When
an event is triggered, the state of the processor is saved on the
supervisor stack.
INSTRUCTION BANK B SRAM (16K BYTE)
INSTRUCTION BANK A SRAM (32K BYTE)
RESERVED
0xFFA0 0000
0xFF90 8000
0xFF90 4000
0xFF90 0000
0xFF80 8000
0xFF80 4000
0xFF80 0000
0xEF00 0800
0xEF00 0000
The ADSP-BF534 processor Event Controller consists of two
stages, the Core Event Controller (CEC) and the System Inter-
rupt Controller (SIC). The Core Event Controller works with
the System Interrupt Controller to prioritize and control all sys-
tem events. Conceptually, interrupts from the peripherals enter
into the SIC, and are then routed directly into the general-pur-
pose interrupts of the CEC.
DATA BANK B SRAM / CACHE (16K BYTE)
DATA BANK B SRAM (16K BYTE)
RESERVED
DATA BANK A SRAM / CACHE (16K BYTE)
DATA BANK A SRAM (16K BYTE)
RESERVED
Core Event Controller (CEC)
BOOT ROM (2K BYTE)
The CEC supports nine general-purpose interrupts (IVG15–7),
in addition to the dedicated interrupt and exception events. Of
these general-purpose interrupts, the two lowest-priority inter-
rupts (IVG15–14) are recommended to be reserved for software
interrupt handlers, leaving seven prioritized interrupt inputs to
support the peripherals of the ADSP-BF534 processor. Table 2
describes the inputs to the CEC, identifies their names in the
Event Vector Table (EVT), and lists their priorities.
RESERVED
0x2040 0000
0x2030 0000
0x2020 0000
0x2010 0000
0x2000 0000
0x0000 0000
ASYNC MEMORY BANK 3 (1M BYTE)
ASYNC MEMORY BANK 2 (1M BYTE)
ASYNC MEMORY BANK 1 (1M BYTE)
ASYNC MEMORY BANK 0 (1M BYTE)
SDRAM MEMORY (16M BYTE - 512M BYTE)
Table 2. Core Event Controller (CEC)
Figure 3. ADSP-BF534 Internal/External Memory Map
Priority
(0 is Highest)
Event Class
EVT Entry
ROM memory space, the processor starts executing from the
on-chip Boot ROM. For more information, see Booting Modes
on Page 15.
0
Emulation/Test Control EMU
Reset RST
Non-Maskable Interrupt NMI
1
Event Handling
2
The event controller on the ADSP-BF534 processor handles all
asynchronous and synchronous events to the processor. The
ADSP-BF534 processor provides event handling that supports
both nesting and prioritization. Nesting allows multiple event
service routines to be active simultaneously. Prioritization
ensures that servicing of a higher-priority event takes prece-
dence over servicing of a lower-priority event. The controller
provides support for five different types of events:
3
Exception
EVX
4
Reserved
—
5
Hardware Error
IVHW
IVTMR
IVG7
6
Core Timer
7
General Interrupt 7
General Interrupt 8
General Interrupt 9
General Interrupt 10
General Interrupt 11
General Interrupt 12
General Interrupt 13
General Interrupt 14
General Interrupt 15
8
IVG8
9
IVG9
• Emulation – An emulation event causes the processor to
enter emulation mode, allowing command and control of
the processor via the JTAG interface.
10
11
12
13
14
15
IVG10
IVG11
IVG12
IVG13
IVG14
IVG15
• Reset – This event resets the processor.
• Non-Maskable Interrupt (NMI) – The NMI event can be
generated by the software watchdog timer or by the NMI
input signal to the processor. The NMI event is frequently
used as a power-down indicator to initiate an orderly shut-
down of the system.
System Interrupt Controller (SIC)
The System Interrupt Controller provides the mapping and
routing of events from the many peripheral interrupt sources to
the prioritized general-purpose interrupt inputs of the CEC.
Rev. PrE
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July 2005
Preliminary Technical Data
ADSP-BF534
Although the ADSP-BF534 processor provides a default map-
ping, the user can alter the mappings and priorities of interrupt
events by writing the appropriate values into the Interrupt
Assignment Registers (IAR). Table 3 describes the inputs into
the SIC and the default mappings into the CEC.
Table 3. System Interrupt Controller (SIC) (Continued)
Peripheral Interrupt Event
Default
Peripheral
Mapping
Interrupt ID
Port H Interrupt B
Timer 0
IVG11
IVG12
IVG12
IVG12
IVG12
IVG12
IVG12
IVG12
IVG12
IVG12
IVG12
IVG13
18
19
20
21
22
23
24
25
26
27
28
29
Table 3. System Interrupt Controller (SIC)
Timer 1
Timer 2
Peripheral Interrupt Event
Default
Peripheral
Mapping
Interrupt ID
Timer 3
PLL Wakeup
IVG7
IVG7
IVG7
IVG7
IVG7
IVG7
IVG7
IVG7
IVG7
IVG7
IVG7
IVG7
IVG7
IVG8
IVG8
IVG9
IVG9
IVG9
IVG9
IVG10
IVG10
IVG10
IVG10
IVG10
IVG10
IVG11
IVG11
IVG11
IVG11
IVG11
0
Timer 4
DMA Error (generic)
DMAR0 Block Interrupt
DMAR1 Block Interrupt
DMAR0 Overflow Error
DMAR1 Overflow Error
CAN Error
1
Timer 5
1
Timer 6
1
Timer 7
1
Port F, G Interrupt A
Port G Interrupt B
1
2
DMA Channels 12 and 13
(Memory DMA Stream 0)
SPORT 0 Error
2
DMA Channels 14 and 15
(Memory DMA Stream 1)
IVG13
30
SPORT 1 Error
2
PPI Error
2
Software Watchdog Timer
Port F Interrupt B
IVG13
IVG13
31
31
SPI Error
2
UART0 Error
2
UART1 Error
2
Event Control
Real-Time Clock
3
The ADSP-BF534 processor provides the user with a very flexi-
ble mechanism to control the processing of events. In the CEC,
three registers are used to coordinate and control events. Each
register is 16 bits wide:
DMA Channel 0 (PPI)
DMA Channel 3 (SPORT 0 RX)
DMA Channel 4 (SPORT 0 TX)
DMA Channel 5 (SPORT 1 RX)
DMA Channel 6 (SPORT 1 TX)
TWI
4
5
6
7
• CEC Interrupt Latch Register (ILAT) – The ILAT register
indicates when events have been latched. The appropriate
bit is set when the processor has latched the event and
cleared when the event has been accepted into the system.
This register is updated automatically by the controller, but
it may be written only when its corresponding IMASK bit
is cleared.
8
9
DMA Channel 7 (SPI)
DMA Channel 8 (UART0 RX)
DMA Channel 9 (UART0 TX)
DMA Channel 10 (UART1 RX)
DMA Channel 11 (UART1 TX)
CAN RX
10
11
12
13
14
15
16
17
17
18
• CEC Interrupt Mask Register (IMASK) – The IMASK reg-
ister controls the masking and unmasking of individual
events. When a bit is set in the IMASK register, that event is
unmasked and will be processed by the CEC when asserted.
A cleared bit in the IMASK register masks the event, pre-
venting the processor from servicing the event even though
the event may be latched in the ILAT register. This register
may be read or written while in supervisor mode. (Note
that general-purpose interrupts can be globally enabled and
disabled with the STI and CLI instructions, respectively.)
CAN TX
DMA Channel 1
Port H Interrupt A
DMA Channel 2
• CEC Interrupt Pending Register (IPEND) – The IPEND
register keeps track of all nested events. A set bit in the
IPEND register indicates the event is currently active or
nested at some level. This register is updated automatically
by the controller but may be read while in supervisor mode.
Rev. PrE
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ADSP-BF534
Preliminary Technical Data
The SIC allows further control of event processing by providing
three 32-bit interrupt control and status registers. Each register
contains a bit corresponding to each of the peripheral interrupt
events shown in Table 3 on Page 7.
The 2D DMA capability supports arbitrary row and column
sizes up to 64K elements by 64K elements, and arbitrary row
and column step sizes up to 32K elements. Furthermore, the
column step size can be less than the row step size, allowing
implementation of interleaved data streams. This feature is
especially useful in video applications where data can be de-
interleaved on the fly.
• SIC Interrupt Mask Register (SIC_IMASK)– This register
controls the masking and unmasking of each peripheral
interrupt event. When a bit is set in the register, that
peripheral event is unmasked and will be processed by the
system when asserted. A cleared bit in the register masks
the peripheral event, preventing the processor from servic-
ing the event.
Examples of DMA types supported by the ADSP-BF534 proces-
sor DMA controller include:
• A single, linear buffer that stops upon completion
• A circular, auto-refreshing buffer that interrupts on each
full or fractionally full buffer
• SIC Interrupt Status Register (SIC_ISR) – As multiple
peripherals can be mapped to a single event, this register
allows the software to determine which peripheral event
source triggered the interrupt. A set bit indicates the
peripheral is asserting the interrupt, and a cleared bit indi-
cates the peripheral is not asserting the event.
• 1-D or 2-D DMA using a linked list of descriptors
• 2-D DMA using an array of descriptors, specifying only the
base DMA address within a common page
In addition to the dedicated peripheral DMA channels, there are
two memory DMA channels provided for transfers between the
various memories of the ADSP-BF534 processor system. This
enables transfers of blocks of data between any of the memo-
ries—including external SDRAM, ROM, SRAM, and flash
memory—with minimal processor intervention. Memory DMA
transfers can be controlled by a very flexible descriptor-based
methodology or by a standard register-based autobuffer
mechanism.
• SIC Interrupt Wakeup Enable Register (SIC_IWR) – By
enabling the corresponding bit in this register, a peripheral
can be configured to wake up the processor, should the
core be idled when the event is generated. (For more infor-
mation, see Dynamic Power Management on Page 12.)
Because multiple interrupt sources can map to a single general-
purpose interrupt, multiple pulse assertions can occur simulta-
neously, before or during interrupt processing for an interrupt
event already detected on this interrupt input. The IPEND reg-
ister contents are monitored by the SIC as the interrupt
acknowledgement.
The ADSP-BF534 processor also includes an external DMA
controller capability via dual external DMA request pins when
used in conjunction with the External Bus Interface Unit
(EBIU). This functionality can be used when a high speed inter-
face is required for external FIFOs and high bandwidth
communications peripherals such as USB 2.0. It allows control
of the number of data transfers for memDMA. The number of
transfers per edge is programmable. This feature can be pro-
grammed to allow memDMA to have an increased priority on
the external bus relative to the core.
The appropriate ILAT register bit is set when an interrupt rising
edge is detected (detection requires two core clock cycles). The
bit is cleared when the respective IPEND register bit is set. The
IPEND bit indicates that the event has entered into the proces-
sor pipeline. At this point the CEC will recognize and queue the
next rising edge event on the corresponding event input. The
minimum latency from the rising edge transition of the general-
purpose interrupt to the IPEND output asserted is three core
clock cycles; however, the latency can be much higher, depend-
ing on the activity within and the state of the processor.
REAL-TIME CLOCK (RTC)
The ADSP-BF534 processor Real-Time Clock (RTC) provides a
robust set of digital watch features, including current time, stop-
watch, and alarm. The RTC is clocked by a 32.768 KHz crystal
external to the ADSP-BF534 processor. The RTC peripheral has
dedicated power supply pins so that it can remain powered up
and clocked even when the rest of the processor is in a low-
power state. The RTC provides several programmable interrupt
options, including interrupt per second, minute, hour, or day
clock ticks, interrupt on programmable stopwatch countdown,
or interrupt at a programmed alarm time.
DMA CONTROLLERS
The ADSP-BF534 processor has multiple, independent DMA
controllers that support automated data transfers with minimal
overhead for the processor core. DMA transfers can occur
between the ADSP-BF534 processor's internal memories and
any of its DMA-capable peripherals. Additionally, DMA trans-
fers can be accomplished between any of the DMA-capable
peripherals and external devices connected to the external
memory interfaces, including the SDRAM controller and the
asynchronous memory controller. DMA-capable peripherals
include the SPORTs, SPI port, UARTs, and PPI. Each individual
DMA-capable peripheral has at least one dedicated DMA
channel.
The 32.768 KHz input clock frequency is divided down to a
1 Hz signal by a prescaler. The counter function of the timer
consists of four counters: a 60-second counter, a 60-minute
counter, a 24-hour counter, and an 32,768-day counter.
When enabled, the alarm function generates an interrupt when
the output of the timer matches the programmed value in the
alarm control register. There are two alarms: The first alarm is
for a time of day. The second alarm is for a day and time of that
day.
The ADSP-BF534 processor DMA controller supports both 1-
dimensional (1D) and 2-dimensional (2D) DMA transfers.
DMA transfer initialization can be implemented from registers
or from sets of parameters called descriptor blocks.
Rev. PrE
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Preliminary Technical Data
ADSP-BF534
The stopwatch function counts down from a programmed
value, with one-second resolution. When the stopwatch is
enabled and the counter underflows, an interrupt is generated.
(PWM) or timer output, as an input to clock the timer, or as a
mechanism for measuring pulse widths and periods of external
events. These timers can be synchronized to an external clock
input to the several other associated PF pins, an external clock
input to the PPI_CLK input pin, or to the internal SCLK.
Like the other peripherals, the RTC can wake up the ADSP-
BF534 processor from Sleep mode upon generation of any RTC
wakeup event. Additionally, an RTC wakeup event can wake up
the ADSP-BF534 processor from Deep Sleep mode, and wake
up the on-chip internal voltage regulator from the Hibernate
operating mode.
The timer units can be used in conjunction with the two UARTs
and the CAN controller to measure the width of the pulses in
the data stream to provide a software auto-baud detect function
for the respective serial channels.
Connect RTC pins RTXI and RTXO with external components
as shown in Figure 4.
The timers can generate interrupts to the processor core provid-
ing periodic events for synchronization, either to the system
clock or to a count of external signals.
In addition to the eight general-purpose programmable timers,
a ninth timer is also provided. This extra timer is clocked by the
internal processor clock and is typically used as a system tick
clock for generation of operating system periodic interrupts.
RTXI
RTXO
R1
X1
SERIAL PORTS (SPORTS)
C1
C2
The ADSP-BF534 processor incorporates two dual-channel
synchronous serial ports (SPORT0 and SPORT1) for serial and
multiprocessor communications. The SPORTs support the fol-
lowing features:
SUGGESTED COMPONENTS:
ECLIPTEK EC38J (THROUGH-HOLE PACKAGE)
EPSON MC405 12 PF LOAD (SURFACE MOUNT PACKAGE)
C1 = 22 PF
C2 = 22 PF
• I2S capable operation.
• Bidirectional operation – Each SPORT has two sets of inde-
pendent transmit and receive pins, enabling eight channels
of I2S stereo audio.
⍀
R1 = 10 M
NOTE: C1 AND C2 ARE SPECIFIC TO CRYSTAL SPECIFIED FOR X1.
CONTACT CRYSTAL MANUFACTURER FOR DETAILS. C1 AND C2
SPECIFICATIONS ASSUME BOARD TRACE CAPACITANCE OF 3 PF.
• Buffered (8-deep) transmit and receive ports – Each port
has a data register for transferring data words to and from
other processor components and shift registers for shifting
data in and out of the data registers.
Figure 4. External Components for RTC
WATCHDOG TIMER
• Clocking – Each transmit and receive port can either use an
external serial clock or generate its own, in frequencies
ranging from (fSCLK/131,070) Hz to (fSCLK/2) Hz.
The ADSP-BF534 processor includes a 32-bit timer that can be
used to implement a software watchdog function. A software
watchdog can improve system availability by forcing the proces-
sor to a known state through generation of a hardware reset,
non-maskable interrupt (NMI), or general-purpose interrupt, if
the timer expires before being reset by software. The program-
mer initializes the count value of the timer, enables the
appropriate interrupt, then enables the timer. Thereafter, the
software must reload the counter before it counts to zero from
the programmed value. This protects the system from remain-
ing in an unknown state where software, which would normally
reset the timer, has stopped running due to an external noise
condition or software error.
• Word length – Each SPORT supports serial data words
from 3 to 32 bits in length, transferred most-significant-bit
first or least-significant-bit first.
• Framing – Each transmit and receive port can run with or
without frame sync signals for each data word. Frame sync
signals can be generated internally or externally, active high
or low, and with either of two pulsewidths and early or late
frame sync.
• Companding in hardware – Each SPORT can perform
A-law or µ-law companding according to ITU recommen-
dation G.711. Companding can be selected on the transmit
and/or receive channel of the SPORT without additional
latencies.
If configured to generate a hardware reset, the watchdog timer
resets both the core and the ADSP-BF534 processor peripherals.
After a reset, software can determine if the watchdog was the
source of the hardware reset by interrogating a status bit in the
watchdog timer control register.
• DMA operations with single-cycle overhead – Each SPORT
can automatically receive and transmit multiple buffers of
memory data. The processor can link or chain sequences of
DMA transfers between a SPORT and memory.
The timer is clocked by the system clock (SCLK), at a maximum
frequency of fSCLK
.
TIMERS
There are nine general-purpose programmable timer units in
the ADSP-BF534 processor. Eight timers have an external pin
that can be configured either as a Pulse Width Modulator
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ADSP-BF534
Preliminary Technical Data
• Interrupts – Each transmit and receive port generates an
interrupt upon completing the transfer of a data word or
after transferring an entire data buffer or buffers through
DMA.
DMA channels, one for transmit and one for receive. These
DMA channels have lower default priority than most DMA
channels because of their relatively low service rates.
Each UART port's baud rate, serial data format, error code gen-
eration and status, and interrupts are programmable:
• Multichannel capability – Each SPORT supports 128 chan-
nels out of a 1024-channel window and is compatible with
the H.100, H.110, MVIP-90, and HMVIP standards.
• Supporting bit rates ranging from (fSCLK/ 1,048,576) to
(fSCLK/16) bits per second.
SERIAL PERIPHERAL INTERFACE (SPI) PORT
• Supporting data formats from 7 to12 bits per frame.
• Both transmit and receive operations can be configured to
generate maskable interrupts to the processor.
The ADSP-BF534 processor has an SPI-compatible port that
enables the processor to communicate with multiple SPI-com-
patible devices.
The UART port’s clock rate is calculated as:
The SPI interface uses three pins for transferring data: two data
pins (Master Output-Slave Input, MOSI, and Master Input-
Slave Output, MISO) and a clock pin (Serial Clock, SCK). An
SPI chip select input pin (SPISS) lets other SPI devices select the
processor, and seven SPI chip select output pins (SPISEL7–1) let
the processor select other SPI devices. The SPI select pins are
reconfigured Programmable Flag pins. Using these pins, the SPI
port provides a full-duplex, synchronous serial interface, which
supports both master/slave modes and multimaster
environments.
f
SCLK
UART Clock Rate = ------------------------------------------------
16 × UART_Divisor
Where the 16-bit UART_Divisor comes from the DLH register
(most significant 8 bits) and DLL register (least significant
8 bits).
In conjunction with the general-purpose timer functions, auto-
baud detection is supported.
The capabilities of the UARTs are further extended with sup-
port for the Infrared Data Association (IrDA®) Serial Infrared
Physical Layer Link Specification (SIR) protocol.
The SPI port’s baud rate and clock phase/polarities are pro-
grammable, and it has an integrated DMA controller,
configurable to support transmit or receive data streams. The
SPI’s DMA controller can only service unidirectional accesses at
any given time.
CONTROLLER AREA NETWORK (CAN)
The ADSP-BF534 processor offers a CAN controller that is a
communication controller implementing the Controller Area
Network (CAN) 2.0B (active) protocol. This protocol is an asyn-
chronous communications protocol used in both industrial and
automotive control systems. The CAN protocol is well suited for
control applications due to its capability to communicate reli-
ably over a network since the protocol incorporates CRC
checking message error tracking, and fault node confinement.
The SPI port’s clock rate is calculated as:
f
SCLK
SPI Clock Rate = ---------------------------------
2 × SPI_Baud
Where the 16-bit SPI_Baud register contains a value of 2 to
65,535.
During transfers, the SPI port simultaneously transmits and
receives by serially shifting data in and out on its two serial data
lines. The serial clock line synchronizes the shifting and sam-
pling of data on the two serial data lines.
The ADSP-BF534 CAN controller offers the following features:
• 32 mailboxes (8 receive only, 8 transmit only, 16 config-
urable for receive or transmit).
• Dedicated acceptance masks for each mailbox.
• Additional data filtering on first two bytes.
UART PORTS (UARTS)
The ADSP-BF534 processor provides two full-duplex Universal
Asynchronous Receiver/Transmitter (UART) ports, which are
fully compatible with PC-standard UARTs. Each UART port
provides a simplified UART interface to other peripherals or
hosts, supporting full-duplex, DMA-supported, asynchronous
transfers of serial data. A UART port includes support for 5 to
8 data bits, 1 or 2 stop bits, and none, even, or odd parity. Each
UART port supports two modes of operation:
• Support for both the standard (11-bit) and extended (29-
bit) identifier (ID) message formats.
• Support for remote frames.
• Active or passive network support.
• CAN wakeup from Hibernation Mode (lowest static power
consumption mode).
• Interrupts, including: TX Complete, RX Complete, Error,
Global.
• PIO (Programmed I/O) – The processor sends or receives
data by writing or reading I/O-mapped UART registers.
The data is double-buffered on both transmit and receive.
The electrical characteristics of each network connection are
very demanding so the CAN interface is typically divided into
two parts: a controller and a transceiver. This allows a single
controller to support different drivers and CAN networks. The
• DMA (Direct Memory Access) – The DMA controller
transfers both transmit and receive data. This reduces the
number and frequency of interrupts required to transfer
data to and from memory. The UART has two dedicated
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Preliminary Technical Data
ADSP-BF534
ADSP-BF534 CAN module represents only the controller part
of the interface. The controller interface supports connection to
3.3V high-speed, fault-tolerant, single-wire transceivers.
enable interrupt function, and the other GPIO Interrupt
Mask register clears bits to disable interrupt function.
GPIO pins defined as inputs can be configured to generate
hardware interrupts, while output pins can be triggered by
software interrupts.
TWI CONTROLLER INTERFACE
The ADSP-BF534 processor includes a Two Wire Interface
(TWI) module for providing a simple exchange method of con-
trol data between multiple devices. The TWI is compatible with
the widely used I2C bus standard. The TWI module offers the
capabilities of simultaneous Master and Slave operation, sup-
port for both 7-bit addressing and multimedia data arbitration.
The TWI interface utilizes two pins for transferring clock (SCL)
and data (SDA) and supports the protocol at speeds up to 400k
bits/sec. The TWI interface pins are compatible with 5 V logic
levels.
• GPIO Interrupt Sensitivity Registers – The two GPIO
Interrupt Sensitivity Registers specify whether individual
pins are level- or edge-sensitive and specify—if edge-sensi-
tive—whether just the rising edge or both the rising and
falling edges of the signal are significant. One register
selects the type of sensitivity, and one register selects which
edges are significant for edge-sensitivity.
PARALLEL PERIPHERAL INTERFACE (PPI)
The ADSP-BF534 processor provides a Parallel Peripheral
Interface (PPI) that can connect directly to parallel A/D and
D/A converters, ITU-R-601/656 video encoders and decoders,
and other general-purpose peripherals. The PPI consists of a
dedicated input clock pin, up to 3 frame synchronization pins,
and up to 16 data pins.
Additionally, the ADSP-BF534 processor’s TWI module is fully
compatible with Serial Camera Control Bus (SCCB) functional-
ity for easier control of various CMOS camera sensor devices.
PORTS
Because of the rich set of peripherals, the ADSP-BF534 proces-
sor groups the many peripheral signals to four ports—Port F,
Port G, Port H, and Port J. Most of the associated pins are
shared by multiple signals. The ports function as multiplexer
controls. Eight of the pins (Port F7–0) offer high source/high
sink current capabilities.
In ITU-R-656 modes, the PPI receives and parses a data stream
of 8-bit or 10-bit data elements. On-chip decode of embedded
preamble control and synchronization information is
supported.
Three distinct ITU-R-656 modes are supported:
• Active Video Only Mode—The PPI does not read in any
data between the End of Active Video (EAV) and Start of
Active Video (SAV) preamble symbols, or any data present
during the vertical blanking intervals. In this mode, the
control byte sequences are not stored to memory; they are
filtered by the PPI.
General-Purpose I/O (GPIO)
The ADSP-BF534 processor has 48 bi-directional, general-pur-
pose I/O (GPIO) pins allocated across three separate GPIO
modules—PORTFIO, PORTGIO, and PORTHIO, associated
with Port F, Port G, and Port H, respectively. Port J does not
provide GPIO functionality. Each GPIO-capable pin shares
functionality with other ADSP-BF534 processor peripherals via
a multiplexing scheme; however, the GPIO functionality is the
default state of the device upon power-up. Neither GPIO output
or input drivers are active by default. Each general-purpose port
pin can be individually controlled by manipulation of the port
control, status, and interrupt registers:
• Vertical Blanking Only Mode—The PPI only transfers Ver-
tical Blanking Interval (VBI) data, as well as horizontal
blanking information and control byte sequences on VBI
lines.
• Entire Field Mode—The entire incoming bitstream is read
in through the PPI. This includes active video, control pre-
amble sequences, and ancillary data that may be embedded
in horizontal and vertical blanking intervals.
• GPIO Direction Control Register – Specifies the direction
of each individual GPIO pin as input or output.
Though not explicitly supported, ITU-R-656 output functional-
ity can be achieved by setting up the entire frame structure
(including active video, blanking, and control information) in
memory and streaming the data out the PPI in a frame sync-less
mode. The processor’s 2D DMA features facilitate this transfer
by allowing the static frame buffer (blanking and control codes)
to be placed in memory once, and simply updating the active
video information on a per-frame basis.
• GPIO Control and Status Registers – The ADSP-BF534
processor employs a “write one to modify” mechanism that
allows any combination of individual GPIO pins to be
modified in a single instruction, without affecting the level
of any other GPIO pins. Four control registers are pro-
vided. One register is written in order to set pin values, one
register is written in order to clear pin values, one register is
written in order to toggle pin values, and one register is
written in order to specify a pin value. Reading the GPIO
status register allows software to interrogate the sense of
the pins.
The general-purpose modes of the PPI are intended to suit a
wide variety of data capture and transmission applications. The
modes are divided into four main categories, each allowing up
to 16 bits of data transfer per PPI_CLK cycle:
• GPIO Interrupt Mask Registers – The two GPIO Interrupt
Mask registers allow each individual GPIO pin to function
as an interrupt to the processor. Similar to the two GPIO
Control Registers that are used to set and clear individual
pin values, one GPIO Interrupt Mask Register sets bits to
• Data Receive with Internally Generated Frame Syncs.
• Data Receive with Externally Generated Frame Syncs.
Rev. PrE
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ADSP-BF534
Preliminary Technical Data
• Data Transmit with Internally Generated Frame Syncs
• Data Transmit with Externally Generated Frame Syncs
cause the processor to sense the value of the BYPASS bit in the
PLL Control register (PLL_CTL). If BYPASS is disabled, the
processor will transition to the Full On mode. If BYPASS is
enabled, the processor will transition to the Active mode.
These modes support ADC/DAC connections, as well as video
communication with hardware signalling. Many of the modes
support more than one level of frame synchronization. If
desired, a programmable delay can be inserted between asser-
tion of a frame sync and reception/transmission of data.
When in the Sleep mode, system DMA access to L1 memory is
not supported.
Deep Sleep Operating Mode – Maximum Dynamic Power
Savings
DYNAMIC POWER MANAGEMENT
The Deep Sleep mode maximizes dynamic power savings by
disabling the clocks to the processor core (CCLK) and to all syn-
chronous peripherals (SCLK). Asynchronous peripherals, such
as the RTC, may still be running but will not be able to access
internal resources or external memory. This powered-down
mode can only be exited by assertion of the reset interrupt
(RESET) or by an asynchronous interrupt generated by the
RTC. When in Deep Sleep mode, an RTC asynchronous inter-
rupt causes the processor to transition to the Active mode.
Assertion of RESET while in Deep Sleep mode causes the pro-
cessor to transition to the Full On mode.
The ADSP-BF534 processor provides five operating modes,
each with a different performance/power profile. In addition,
Dynamic Power Management provides the control functions to
dynamically alter the processor core supply voltage, further
reducing power dissipation. Control of clocking to each of the
ADSP-BF534 processor peripherals also reduces power con-
sumption. See Table 4 for a summary of the power settings for
each mode.
Full-On Operating Mode – Maximum Performance
In the Full-On mode, the PLL is enabled and is not bypassed,
providing capability for maximum operational frequency. This
is the power-up default execution state in which maximum per-
formance can be achieved. The processor core and all enabled
peripherals run at full speed.
Hibernate Operating Mode – Maximum Static Power
Savings
The hibernate mode maximizes static power savings by dis-
abling the voltage and clocks to the processor core (CCLK) and
to all the synchronous peripherals (SCLK). The internal voltage
regulator for the processor can be shut off by writing b#00 to the
FREQ bits of the VR_CTL register. This disables both CCLK
and SCLK. Furthermore, it sets the internal power supply volt-
age (VDDINT) to 0V to provide the greatest power savings mode.
Any critical information stored internally (memory contents,
register contents, etc.) must be written to a non-volatile storage
device prior to removing power if the processor state is to be
preserved.
Active Operating Mode – Moderate Power Savings
In the Active mode, the PLL is enabled but bypassed. Because
the PLL is bypassed, the processor’s core clock (CCLK) and sys-
tem clock (SCLK) run at the input clock (CLKIN) frequency. In
this mode, the CLKIN to CCLK multiplier ratio can be changed,
although the changes are not realized until the Full-On mode is
entered. DMA access is available to appropriately configured L1
memories.
In the Active mode, it is possible to disable the PLL through the
PLL Control register (PLL_CTL). If disabled, the PLL must be
re-enabled before transitioning to the Full-On or Sleep modes.
Since VDDEXT is still supplied in this mode, all of the external
pins tri-state, unless otherwise specified. This allows other
devices that may be connected to the processor to have power
still applied without drawing unwanted current.
Table 4. Power Settings
The internal supply regulator can be woken up by CAN. It can
also be woken up by a Real-Time Clock wakeup event or by
asserting the RESET pin, both of which initiate the hardware
reset sequence.
With the exception of the VR_CTL and the RTC registers, all
internal registers and memories lose their content in hibernate
state. State variables may be held in external SRAM or SDRAM.
The CKELOW bit in the VR_CTL register controls whether
SDRAM operates in self-refresh mode to retain its content while
the processor is in reset.
Full On
Active
Enabled
No
Enabled Enabled On
Enabled Enabled On
Enabled/ Yes
Disabled
Sleep
Enabled
-
-
-
Disabled Enabled On
Disabled Disabled On
Disabled Disabled Off
Deep Sleep Disabled
Hibernate Disabled
Power Savings
As shown in Table 5, the ADSP-BF534 processor supports three
different power domains. The use of multiple power domains
maximizes flexibility, while maintaining compliance with
industry standards and conventions. By isolating the internal
logic of the ADSP-BF534 processor into its own power domain,
separate from the RTC and other I/O, the processor can take
Sleep Operating Mode – High Dynamic Power Savings
The Sleep mode reduces dynamic power dissipation by dis-
abling the clock to the processor core (CCLK). The PLL and
system clock (SCLK), however, continue to operate in this
mode. Typically an external event or RTC activity will wake up
the processor. When in the Sleep mode, assertion of wakeup will
Rev. PrE
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Preliminary Technical Data
ADSP-BF534
advantage of Dynamic Power Management, without affecting
the RTC or other I/O devices. There are no sequencing require-
ments for the various power domains.
can be activated from this power down state by assertion of the
RESET pin, which will then initiate a boot sequence. The regula-
tor can also be disabled and bypassed at the user’s discretion.
Table 5. Power Domains
V
DDEXT
Power Domain
VDD Range
VDDINT
100 µF
2.25V - 3.6V
INPUT VOLTAGE
RANGE
All internal logic, except RTC
RTC internal logic and crystal I/O
All other I/O
10 µH
0.1 µF
ZHCS1000
VDDRTC
V
DDINT
VDDEXT
FDS9431A
100 µF
1 µF
The power dissipated by a processor is largely a function of the
clock frequency of the processor and the square of the operating
voltage. For example, reducing the clock frequency by 25%
results in a 25% reduction in power dissipation, while reducing
the voltage by 25% reduces power dissipation by more than
40%. Further, these power savings are additive, in that if the
clock frequency and supply voltage are both reduced, the power
savings can be dramatic.
VR
1-0
OUT
EXTERNAL COMPONENTS
1-0 SHOULD BE TIED TOGETHER EXTERNALLY
NOTE: VR
OUT
AND DESIGNER SHOULD MINIMIZE TRACE LENGTH TO FDS9431A.
Figure 5. Voltage Regulator Circuit
The Dynamic Power Management feature of the ADSP-BF534
processor allows both the processor’s input voltage (VDDINT) and
clock frequency (fCCLK) to be dynamically controlled.
CLOCK SIGNALS
As explained above, the savings in power dissipation can be
modeled by the following equations:
The ADSP-BF534 processor can be clocked by an external crys-
tal, a sine wave input, or a buffered, shaped clock derived from
an external clock oscillator.
Power Savings Factor
If an external clock is used, it should be a TTL compatible signal
and must not be halted, changed, or operated below the speci-
fied frequency during normal operation. This signal is
connected to the processor’s CLKIN pin. When an external
clock is used, the XTAL pin must be left unconnected.
2
f
V
T
CCLKRED
DDINTRED
RED
-------------------------------
--------------------------------------
-----------------
=
×
×
f
V
T
CCLKNOM
DDINTNOM
NOM
Alternatively, because the ADSP-BF534 processor includes an
on-chip oscillator circuit, an external crystal may be used. For
fundamental frequency operation, use the circuit shown in
Figure 6. A parallel-resonant, fundamental frequency, micro-
processor-grade crystal is connected across the CLKIN and
XTAL pins. The on-chip resistance between CLKIN and the
XTAL pin is in the 500 kOhm range. Further parallel resistors
are typically not recommended. The two capacitors and the
series resistor shown in Figure 6 fine tune phase and amplitude
of the sine frequency.
% Power Savings = (1 – Power Savings Factor) × 100%
where the variables in the equations are:
• fCCLKNOM is the nominal core clock frequency
• fCCLKRED is the reduced core clock frequency
• VDDINTNOM is the nominal internal supply voltage
• VDDINTRED is the reduced internal supply voltage
• TNOM is the duration running at fCCLKNOM
• TRED is the duration running at fCCLKRED
The capacitor and resistor values shown in Figure 6 are typical
values only. The capacitor values are dependent upon the crystal
manufacturers’ load capacitance recommendations and the PCB
physical layout. The resistor value depends on the drive level
VOLTAGE REGULATION
The ADSP-BF534 processor provides an on-chip voltage regula-
tor that can generate processor core voltage levels (0.85V to
1.2V guaranteed from -5% to 10%) from an external 2.25 V to
3.6 V supply. Figure 5 shows the typical external components
required to complete the power management system. The regu-
lator controls the internal logic voltage levels and is
programmable with the Voltage Regulator Control Register
(VR_CTL) in increments of 50 mV. To reduce standby power
consumption, the internal voltage regulator can be programmed
to remove power to the processor core while keeping I/O power
supplied. While in Hibernate mode, VDDEXT can still be applied,
eliminating the need for external buffers. The voltage regulator
Rev. PrE
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ADSP-BF534
Preliminary Technical Data
specified by the crystal manufacturer. The user should verify the
customized values based on careful investigations on multiple
devices over temperature range.
DYNAMIC MODIFICATION
REQUIRES PLL SEQUENCING
DYNAMIC MODIFICATION
ON-THE-FLY
+ 1, 2, 4, 8
+ 1:15
CCLK
SCLK
BLACKFIN
PLL
.5x - 64x
CLKIN
VCO
CLKOUT
TO PLL CIRCUITRY
EN
CLKBUF
SCLK CCLK
SCLK 133 MHZ
EN
Figure 7. Frequency Modification Methods
CLKIN
18 pF*
XTAL
330⍀*
FOR OVERTONE
OPERATION ONLY:
into the SSEL fields define a divide ratio between the PLL output
(VCO) and the system clock. SCLK divider values are 1 through
15. Table 6 illustrates typical system clock ratios:
18 pF*
Table 6. Example System Clock Ratios
NOTE: VALUES MARKED WITH * MUST BE CUSTOMIZED
DEPENDING ON THE CRYSTAL AND LAYOUT. PLEASE
ANALYZE CAREFULLY.
Signal Name Divider Ratio Example Frequency Ratios
SSEL3–0
VCO/SCLK
(MHz)
VCO
100
Figure 6. External Crystal Connections
SCLK
100
50
0001
0110
1010
1:1
If the user prefers, a third-overtone crystal can be used at fre-
quencies above 25 MHz. The circuit is then modified to ensure
crystal operation only at the third overtone, by adding a tuned
inductor circuit as shown in Figure 6. A design procedure for
third-overtone operation is discussed in detail in application
note EE-168.
6:1
300
10:1
500
50
Note that the divisor ratio must be chosen to limit the system
clock frequency to its maximum of fSCLK. The SSEL value can be
changed dynamically without any PLL lock latencies by writing
the appropriate values to the PLL divisor register (PLL_DIV).
The CLKBUF pin is an output pin, and is a buffer version of the
input clock. The Blackfin core is running at a different clock rate
than the on-chip peripherals. As shown in Figure 7 on Page 14,
the core clock (CCLK) and system peripheral clock (SCLK) are
derived from the input clock (CLKIN) signal. An on-chip PLL is
capable of multiplying the CLKIN signal by a user programma-
ble 1x to 63x multiplication factor (bounded by specified
minimum and maximum VCO frequencies). The default multi-
plier is 10x, but it can be modified by a software instruction
sequence. On-the-fly frequency changes can be effected by sim-
ply writing to the PLL_DIV register. The CLKBUF output is
active by default and can be disabled by the VR_CTL register for
power savings.
The core clock (CCLK) frequency can also be dynamically
changed by means of the CSEL1–0 bits of the PLL_DIV register.
Supported CCLK divider ratios are 1, 2, 4, and 8, as shown in
Table 7. This programmable core clock capability is useful for
fast core frequency modifications.
The maximum CCLK frequency not only depends on the part's
speed grade (see page 59), it also depends on the applied VDDINT
voltage. See Table 10 - Table 11 for details. The maximal system
clock rate (SCLK) depends on the chip package and the applied
VDDEXT voltage (see Table 13).
On-the-fly CCLK and SCLK frequency changes can be effected
by simply writing to the PLL_DIV register. Whereas the maxi-
mum allowed CCLK and SCLK rates depend on the applied
voltages VDDINT and VDDEXT, the VCO is always permitted to run
up to the frequency specified by the part’s speed grade. The
CLKOUT pin reflects the SCLK frequency to the off-chip world.
It belongs to the SDRAM interface, but it functions as reference
signal in other timing specifications as well. While active by
default, it can be disabled by the EBIU_SDGCTL and
EBIU_AMGCTL registers.
Table 7. Core Clock Ratios
Signal Name Divider Ratio Example Frequency Ratios
CSEL1–0
VCO/CCLK
VCO
300
300
500
200
CCLK
300
150
125
25
00
01
10
11
1:1
2:1
4:1
8:1
All on-chip peripherals are clocked by the system clock (SCLK).
The system clock frequency is programmable by means of the
SSEL3–0 bits of the PLL_DIV register. The values programmed
Rev. PrE
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Preliminary Technical Data
ADSP-BF534
any more bytes until the flag is de-asserted. The flag is cho-
sen by the user and this information will be transferred to
the Blackfin processor via bits 10:5 of the FLAG header.
BOOTING MODES
The ADSP-BF534 processor has six mechanisms (listed in
Table 8) for automatically loading internal and external mem-
ory after a reset. A seventh mode is provided to execute from
external memory, bypassing the boot sequence.
• Boot from UART – Using an autobaud handshake
sequence, a boot-stream-formatted program is downloaded
by the Host. The Host agent selects a baud rate within the
UART’s clocking capabilities. When performing the auto-
baud, the UART expects a “@” (boot stream) character
(eight bits data, one start bit, one stop bit, no parity bit) on
the RXD pin to determine the bit rate. It then replies with
an acknowledgement which is composed of 4 bytes: 0xBF,
the value of UART_DLL, the value of UART_DLH, 0x00.
The Host can then download the boot stream. When the
processor needs to hold off the Host, it de-asserts CTS.
Therefore, the Host must monitor this signal.
Table 8. Booting Modes
BMODE2–0
Description
000
Execute from 16-bit external memory
(Bypass Boot ROM)
001
Boot from 8-bit or 16-bit memory
(EPROM/flash)
010
011
100
101
Reserved
Boot from serial SPI memory (EEPROM/flash)
Boot from SPI host (slave mode)
• Boot from serial TWI memory (EEPROM/flash) – The
Blackfin processor operates in master mode and selects the
TWI slave with the unique id 0xA0. It submits successive
read commands to the memory device starting at two byte
internal address 0x0000 and begins clocking data into the
processor. The TWI memory device should comply with
Philips I2C Bus Specification version 2.1 and have the capa-
bility to auto-increment its internal address counter such
that the contents of the memory device can be read
sequentially.
Boot from serial TWI memory
(EEPROM/flash)
110
111
Boot from TWI host (slave mode)
Boot from UART host (slave mode)
The BMODE pins of the Reset Configuration Register, sampled
during power-on resets and software-initiated resets, imple-
ment the following modes:
• Boot from TWI Host – The TWI Host agent selects the
slave with the unique id 0x5F. The processor replies with an
acknowledgement and the Host can then download the
boot stream. The TWI Host agent should comply with
Philips I2C Bus Specification version 2.1. An I2C multi-
plexer can be used to select one processor at a time when
booting multiple processors from a single TWI.
• Execute from 16-bit external memory – Execution starts
from address 0x2000 0000 with 16-bit packing. The Boot
ROM is bypassed in this mode. All configuration settings
are set for the slowest device possible (3-cycle hold time;
15-cycle R/W access times; 4-cycle setup).
• Boot from 8-bit and 16-bit external flash memory – The
8-bit or 16-bit flash boot routine located in Boot ROM
memory space is set up using Asynchronous Memory Bank
0. All configuration settings are set for the slowest device
possible (3-cycle hold time; 15-cycle R/W access times;
4-cycle setup). The Boot ROM evaluates the first byte of the
boot stream at address 0x2000 0000. If it is 0x40, 8-bit boot
is performed. A 0x60 byte assumes a 16-bit memory device
and performs 8-bit DMA. A 0x20 byte also assumes 16-bit
memory but performs 16-bit DMA.
For each of the boot modes, a 10-byte header is first brought in
from an external device. The header specifies the number of
bytes to be transferred and the memory destination address.
Multiple memory blocks may be loaded by any boot sequence.
Once all blocks are loaded, program execution commences from
the start of L1 instruction SRAM.
In addition, bit 4 of the Reset Configuration Register can be set
by application code to bypass the normal boot sequence during
a software reset. For this case, the processor jumps directly to
the beginning of L1 instruction memory.
• Boot from serial SPI memory (EEPROM or flash). 8-, 16-,
or 24-bit addressable devices are supported as well as are
AT45DB041, AT45DB081, AT45DB161, AT45DB321,
AT45DB642, and AT45DB1282 DataFlash® devices from
Atmel. The SPI uses the PF10/SPI SSEL1 output pin to
select a single SPI EEPROM/flash device, submits a read
command and successive address bytes (0x00) until a valid
8-, 16-, or 24-bit, or Atmel addressable device is detected,
and begins clocking data into the processor.
To augment the boot modes, a secondary software loader can be
added to provide additional booting mechanisms. This second-
ary loader could provide the capability to boot from flash,
variable baud rate, and other sources. In all boot modes except
Bypass, program execution starts from on-chip L1 memory
address 0xFFA0 0000.
INSTRUCTION SET DESCRIPTION
• Boot from SPI host device – The Blackfin processor oper-
ates in SPI slave mode and is configured to receive the bytes
of the .LDR file from an SPI host (master) agent. To hold
off the host device from transmitting while the Boot ROM
is busy, the Blackfin processor will assert a GPIO pin, called
host wait (HWAIT), to signal the host device not to send
The Blackfin processor family assembly language instruction set
employs an algebraic syntax designed for ease of coding and
readability. The instructions have been specifically tuned to pro-
vide a flexible, densely encoded instruction set that compiles to
a very small final memory size. The instruction set also provides
fully featured multifunction instructions that allow the pro-
Rev. PrE
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ADSP-BF534
Preliminary Technical Data
grammer to use many of the processor core resources in a single
instruction. Coupled with many features more often seen on
microcontrollers, this instruction set is very efficient when com-
piling C and C++ source code. In addition, the architecture
supports both user (algorithm/application code) and supervisor
(O/S kernel, device drivers, debuggers, ISRs) modes of opera-
tion, allowing multiple levels of access to core processor
resources.
To use these emulators, the target board must include a header
that connects the processor’s JTAG port to the emulator.
For details on target board design issues including mechanical
layout, single processor connections, multiprocessor scan
chains, signal buffering, signal termination, and emulator pod
logic, see Analog Devices JTAG Emulation Technical Reference
(EE-68) on the Analog Devices web site under
www.analog.com/ee-notes. This document is updated regularly
to keep pace with improvements to emulator support.
The assembly language, which takes advantage of the proces-
sor’s unique architecture, offers the following advantages:
RELATED DOCUMENTS
• Seamlessly integrated DSP/MCU features are optimized for
both 8-bit and 16-bit operations.
The following publications that describe the ADSP-BF534 pro-
cessors (and related processors) can be ordered from any
Analog Devices sales office or accessed electronically on our
web site:
• A multi-issue load/store modified-Harvard architecture,
which supports two 16-bit MAC or four 8-bit ALU + two
load/store + two pointer updates per cycle.
• Getting Started With Blackfin Processors
• All registers, I/O, and memory are mapped into a unified
4G byte memory space, providing a simplified program-
ming model.
• ADSP-BF537 Blackfin Processor Hardware Reference
• ADSP-BF53x/BF56x Blackfin Processor Programming
Reference
• Microcontroller features, such as arbitrary bit and bit-field
manipulation, insertion, and extraction; integer operations
on 8-, 16-, and 32-bit data-types; and separate user and
supervisor stack pointers.
• ADSP-BF534 Blackfin Processor Anomaly List
• Code density enhancements, which include intermixing of
16- and 32-bit instructions (no mode switching, no code
segregation). Frequently used instructions are encoded in
16 bits.
DEVELOPMENT TOOLS
The ADSP-BF534 processor is supported with a complete set of
CROSSCORE® software and hardware development tools,
including Analog Devices emulators and VisualDSP++® devel-
opment environment. The same emulator hardware that
supports other Blackfin processors also fully emulates the
ADSP-BF534 processor.
EZ-KIT Lite Evaluation Board
For evaluation of ADSP-BF534 processors, use the ADSP-
BF537 EZ-KIT Lite board available from Analog Devices. Order
part number ADDS-BF537-EZLITE. The board comes with on-
chip emulation capabilities and is equipped to enable software
development. Multiple daughter cards are available.
DESIGNING AN EMULATOR-COMPATIBLE
PROCESSOR BOARD (TARGET)
The Analog Devices family of emulators are tools that every sys-
tem developer needs to test and debug hardware and software
systems. Analog Devices has supplied an IEEE 1149.1 JTAG
Test Access Port (TAP) on each JTAG processor. The emulator
uses the TAP to access the internal features of the processor,
allowing the developer to load code, set breakpoints, observe
variables, observe memory, and examine registers. The proces-
sor must be halted to send data and commands, but once an
operation has been completed by the emulator, the processor
system is set running at full speed with no impact on system
timing.
Rev. PrE
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July 2005
Preliminary Technical Data
PIN DESCRIPTIONS
ADSP-BF534 processor pin definitions are listed in Table 9. In
order to maintain maximum functionality and reduce package
size and pin count, some pins have dual, multiplexed function-
ality. In cases where pin functionality is reconfigurable, the
default state is shown in plain text, while alternate functionality
is shown in italics. Pins shown with an asterisk after their name
(*) offer high source/high sink current capabilities.
ADSP-BF534
All pins are tristated during and immediately after reset with the
exception of the external memory interface. On the external
memory interface, the control and address lines are driven high
during reset unless the BR pin is asserted.
All I/O pins have their input buffers disabled with the exception
of the pins noted in the data sheet that need pullups or pull-
downs if unused.
Table 9. Pin Descriptions
Pin Name
I/O
Function
Driver Type1
Memory Interface
ADDR19–1
O
I/O
O
I
Address Bus for Async Access
Data Bus for Async/Sync Access
Byte Enables/Data Masks for Async/Sync Access
Bus Request
A
A
A
DATA15–0
ABE1–0/SDQM1–0
BR2
BG
O
O
Bus Grant
A
A
BGH
Bus Grant Hang
Asynchronous Memory Control
AMS3–0
O
I
Bank Select
A
ARDY
Hardware Ready Control
Output Enable
Read Enable
AOE
O
O
O
A
A
A
ARE
AWE
Write Enable
Synchronous Memory Control
SRAS
SCAS
SWE
O
O
O
O
O
O
O
Row Address Strobe
Column Address Strobe
Write Enable
A
A
A
A
B
SCKE
CLKOUT
SA10
SMS
Clock Enable
Clock Output
A10 Pin
A
A
Bank Select
Port F: GPIO/UART1–0/Timer7–0/External DMA Request (* = High Source/High Sink Pin)
PF0* - GPIO/UART0 TX/DMAR0
PF1*- GPIO/UART0 RX/DMAR1/TACI1
PF2* - GPIO/UART1 TX/TMR7
PF3* - GPIO/UART1 RX/TMR6/TACI6
PF4* - GPIO/TMR5/SPI SSEL6
PF5* - GPIO/TMR4/SPI SSEL5
PF6* - GPIO/TMR3/SPI SSEL4
PF7* - GPIO/TMR2/PPI FS3
PF8 - GPIO/TMR1/PPI FS2
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GPIO/UART0 Transmit/DMA Request 0
GPIO/UART0 Receive/DMA Request 1/Timer1 Alternate Input Capture
GPIO/UART1 Transmit/Timer7
C
C
C
C
C
C
C
C
D
D
D
D
GPIO/UART1 Receive/Timer6/Timer6 Alternate Input Capture
GPIO/Timer5/SPI Slave Select Enable 6
GPIO/Timer4/SPI Slave Select Enable 5
GPIO/Timer3/SPI Slave Select Enable 4
GPIO/Timer2/PPI Frame Sync 3
GPIO/Timer1/PPI Frame Sync 2
PF9 - GPIO/TMR0/PPI FS1
GPIO/Timer0/PPI Frame Sync 1
PF10 - GPIO/SPI SSEL1
GPIO/SPI Slave Select Enable 1
PF11 - GPIO/SPI MOSI
GPIO/SPI Master Out Slave In
Rev. PrE
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ADSP-BF534
Preliminary Technical Data
Table 9. Pin Descriptions (Continued)
Pin Name
I/O
Function
Driver Type1
Port F: GPIO/UART1–0/Timer7–0/External DMA Request (* = High Source/High Sink Pin), continued
PF12 - GPIO/SPI MISO3
PF13 - GPIO/SPI SCK
PF14 - GPIO/SPI SS/TACLK0
PF15 - GPIO/PPI CLK/TMRCLK
Port G: GPIO/PPI/SPORT1
PG0 - GPIO/PPI D0
PG1 - GPIO/PPI D1
PG2 - GPIO/PPI D2
PG3 - GPIO/PPI D3
PG4 - GPIO/PPI D4
PG5 - GPIO/PPI D5
PG6 - GPIO/PPI D6
PG7 - GPIO/PPI D7
PG8 - GPIO/PPI D8/DR1SEC
PG9 - GPIO/PPI D9/DT1SEC
PG10 - GPIO/PPI D10/RSCLK1
PG11 - GPIO/PPI D11/RFS1
PG12 - GPIO/PPI D12/DR1PRI
PG13 - GPIO/PPI D13/TSCLK1
PG14 - GPIO/PPI D14/TFS1
PG15 - GPIO/PPI D15/DT1PRI
Port H: GPIO
I/O
I/O
I/O
I/O
GPIO/SPI Master In Slave Out
GPIO/SPI Clock
D
D
GPIO/SPI Slave Select/Alternate Timer0 Clock Input
GPIO/PPI Clock/External Timer Reference
D
D
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GPIO/PPI Data 0
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
GPIO/PPI Data 1
GPIO/PPI Data 2
GPIO/PPI Data 3
GPIO/PPI Data 4
GPIO/PPI Data 5
GPIO/PPI Data 6
GPIO/PPI Data 7
GPIO/PPI Data 8/SPORT1 Receive Data Secondary
GPIO/PPI Data 9/SPORT1 Transmit Data Secondary
GPIO/PPI Data 10/SPORT1 Receive Serial Clock
GPIO/PPI Data 11/SPORT1 Receive Frame Sync
GPIO/PPI Data 12/SPORT1 Receive Data Primary
GPIO/PPI Data 13/SPORT1 Transmit Serial Clock
GPIO/PPI Data 14/SPORT1 Transmit Frame Sync
GPIO/PPI Data 15/SPORT1 Transmit Data Primary
PH0 - GPIO
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
PH1 - GPIO
PH2 - GPIO
PH3 - GPIO
PH4 - GPIO
PH5 - GPIO
PH6 - GPIO
PH7 - GPIO
PH8 - GPIO
PH9 - GPIO
PH10 - GPIO
PH11 - GPIO
PH12 - GPIO
PH13 - GPIO
PH14 - GPIO
PH15 - GPIO
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July 2005
Preliminary Technical Data
ADSP-BF534
Table 9. Pin Descriptions (Continued)
Pin Name
I/O
Function
Driver Type1
Port J:SPORT0/TWI/SPI Select/CAN
PJ0 - No connect
PJ1 - Connect to GND
PJ2 - SCL
No Connect
G
Connect to GND
TWI Serial Clock
TWI Serial Data
I/O
I/O
I
D
D
PJ3 - SDA
PJ4 - DR0SEC/CANRX/TACI0
SPORT0 Receive Data Secondary/CAN Receive/Timer0 Alternate Input
Capture
PJ5 - DT0SEC/CANTX/SPI SSEL7
O
SPORT0 Transmit Data Secondary/CAN Transmit/SPI Slave Select
D
Enable 7
PJ6 - RSCLK0/TACLK2
PJ7 - RFS0/TACLK3
PJ8 - DR0PRI/TACLK4
PJ9 - TSCLK0/TACLK1
PJ10 - TFS0/SPI SSEL3
PJ11 - DT0PRI/SPI SSEL2
Real Time Clock
RTXI4
I/O
I/O
I
SPORT0 Receive Serial Clock/Alternate Timer2 Clock Input
SPORT0 Receive Frame Sync/Alternate Timer3 Clock Input
SPORT0 Receive Data Primary/Alternate Timer4 Clock Input
SPORT0 Transmit Serial Clock/Alternate Timer1 Clock Input
SPORT0 Transmit Frame Sync/SPI Slave Select Enable 3
SPORT0 Transmit Data Primary/SPI Slave Select Enable 2
E
D
I/O
I/O
O
E
D
D
I
RTC Crystal Input
RTXO
O
RTC Crystal Output
JTAG Port
TCK
I
JTAG Clock
TDO
O
I
JTAG Serial Data Out
JTAG Serial Data In
JTAG Mode Select
JTAG Reset
D
D
TDI
TMS
TRST5
I
I
EMU
O
Emulation Output
Clock
CLKIN
I
Clock/Crystal Input
Crystal Output
XTAL
O
O
CLKBUF
Buffered CLKIN Output
Mode Controls
RESET
NMI6
I
I
I
Reset
Non-maskable Interrupt
Boot Mode Strap 2-0
BMODE2–0
Voltage Regulator
VROUT0
O
O
External FET Drive
External FET Drive
VROUT1
Supplies
VDDEXT
P
P
P
G
I/O Power Supply
VDDINT
Internal Power Supply (regulated from 2.25V to 3.6V)
Real Time Clock Power Supply
External Ground
VDDRTC
GND
1 See “Output Drive Currents” on page 46 for more information about each driver types.
2 This pin should be pulled HIGH when not used.
3 This pin should always be pulled HIGH through a 4.7 K Ohms resistor if booting via the SPI port.
4 This pin should always be pulled LOW when not used.
5 This pin should be pulled LOW if the JTAG port will not be used.
6 This pin should always be pulled HIGH when not used.
Rev. PrE
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ADSP-BF534
Preliminary Technical Data
SPECIFICATIONS
Note that component specifications are subject to change
without notice.
RECOMMENDED OPERATING CONDITIONS
Parameter1
Minimum
0.8
Nominal
1.2
Maximum
1.32
1.32
3.6
Unit
V
VDDINT
VDDINT
VDDEXT
VDDRTC
VIH
Internal Supply Voltage2 (400 MHz)
Internal Supply Voltage2 (500 MHz)
External Supply Voltage
0.8
1.26
V
2.25
2.25
2.0
2.5 or 3.3
V
Real Time Clock Power Supply Voltage
High Level Input Voltage3, 4, @ VDDEXT =maximum
High Level Input Voltage5, @ VDDEXT =maximum
High Level Input Voltage6, @ VDDEXT =maximum
Low Level Input Voltage3, 7, @ VDDEXT =minimum
Low Level Input Voltage6, @ VDDEXT =minimum
Ambient Operating Temperature
Automotive
3.6
V
3.6
V
VIHCLKIN
VIH5V
VIL
2.2
3.6
V
2.0
5.0
V
–0.3
–0.3
0.6
V
VIL5V
TA
0.8
V
–40
–40
105
85
ºC
ºC
Industrial
1 Specifications subject to change without notice.
2 Voltage regulator output is guaranteed from -5% to 10% of specified values.
3 The ADSP-BF534 processor is 3.3 V tolerant (always accepts up to 3.6 V maximum VIH), but voltage compliance (on outputs, VOH) depends on the input VDDEXT, because VOH
(maximum) approximately equals VDDEXT (maximum). This 3.3 V tolerance applies to bi-directional pins (DATA15–0, PF15–0, PG15–0, PH15–0, TFS0, TCLK0, RSCLK0,
RFS0) and input only pins (BR, ARDY, DR0PRI, DR0SEC, RTXI, TCK, TDI, TMS, TRST, CLKIN, RESET, NMI, and BMODE2–0).
4 Parameter value applies to all input and bi-directional pins except CLKIN, SDA, and SCL.
5 Parameter value applies to CLKIN pin only.
6 Certain ADSP-BF534 processor pins are 5.0 V tolerant (always accept up to 5.5 V maximum VIH), but voltage compliance (on outputs, VOH) depends on the input VDDEXT
because VOH (maximum) approximately equals VDDEXT (maximum). This 5.0 V tolerance applies to SDA and SCL pins only. The SDA and SCL pins are open drain and
therefore require a pullup resistor. Consult the I2C specification version 2.1 for the proper resistor value.
,
7 Parameter value applies to all input and bi-directional pins except SDA and SCL.
Rev. PrE
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Preliminary Technical Data
ADSP-BF534
ELECTRICAL CHARACTERISTICS
Parameter1
Test Conditions
Min
Max Unit
VOH
Port F7–0
High Level Output Voltage2
@ VDDEXT = 3.3V +/- 10%, IOH = –10 mA
@ VDDEXT = 2.5V +/- 10%, IOH = –6 mA
VDDEXT – 0.5V
DDEXT – 0.5V
V
V
V
V
V
V
Port F15–8, Port G, Port H
I
OH = –1 mA
VDDEXT – 0.5V
Max Combined for Port F7–0
TBD
TBD
Max Total for all Port F, Port G,
and Port H Pins
VOL
Low Level Output Voltage2
Port F7–0
@ VDDEXT = 3.3V +/- 10%, IOL = 10 mA
@ VDDEXT = 2.5V +/- 10%, IOL = 6 mA
0.5V
0.5V
0.5V
V
V
V
V
V
Port F15–8, Port G, Port H
IOL = 2 mA
Max Combined for Port F7–0
TBD
TBD
Max Total for all Port F, Port G,
and Port H Pins
IIH
High Level Input Current3 @ VDDEXT =maximum, VIN = VDD maximum
TBD µA
TBD µA
TBD µA
IIL
Low Level Input Current4
@ VDDEXT =maximum, VIN = 0 V
IOZH
Three-State Leakage
Current4
@ VDDEXT = maximum, VIN = VDD maximum
IOZL
Three-State Leakage
Current5
@ VDDEXT = maximum, VIN = 0 V
TBD µA
TBD mA
TBD pF
Max Total Current for all Port F,
Port G, and Port H Pins
CIN
Input Capacitance5, 6
fIN = 1 MHz, TAMBIENT = 25°C, VIN = 2.5 V
1 Specifications subject to change without notice.
2 Applies to output and bidirectional pins.
3 Applies to input pins.
4 Applies to three-statable pins.
5 Applies to all signal pins.
6 Guaranteed, but not tested.
Rev. PrE
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Page 21 of 60 | July 2005
ADSP-BF534
Preliminary Technical Data
ABSOLUTE MAXIMUM RATINGS
Internal (Core) Supply Voltage1 (VDDINT
)
–0.3 V to +1.4 V
–0.3 V to +3.8 V
–0.5 V to +3.6 V
–0.5 V to VDDEXT +0.5 V
200 pF
External (I/O) Supply Voltage1 (VDDEXT
Input Voltage1
)
a
ADSP-BF534
PRODUCT
Output Voltage Swing1
Load Capacitance1,2
BBCZ-5B1
B = TEMP RANGE
BC = MINI BGA
Z = LEAD FREE
367334.1 0.2
LOT NUMBER
DATE CODE
5 = SPEED GRADE
B1= PACKAGE TYPE
0440 SINGAPORE
Storage Temperature Range1
Junction Temperature Underbias1
–65ºC to +150ºC
SILICON REVISION
ASSEMBLY
B
+125ºC
1 Stresses greater than those listed above may cause permanent damage to the device. These
are stress ratings only. Functional operation of the device at these or any other conditions
greaterthanthoseindicatedintheoperationalsectionsofthisspecificationisnotimplied.
Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
Figure 8. Product Information on Package
2 ForproperSDRAMcontrolleroperation, themaximumloadcapacitanceis50pF(at3.3V)
or 30 pF (at 2.5V) for ADDR19–1, DATA15–0, ABE1–0/SDQM1–0, CLKOUT, SCKE,
SA10, SRAS, SCAS, SWE, and SMS.
ESD SENSITIVITY
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADSP-BF534 processor features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precau-
tions are recommended to avoid performance degradation or loss of functionality.
Rev. PrE
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Page 22 of 60
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July 2005
Preliminary Technical Data
ADSP-BF534
TIMING SPECIFICATIONS
Table 10 and Table 11 describe the timing requirements for the
ADSP-BF534 processor clocks. Take care in selecting MSEL,
SSEL, and CSEL ratios so as not to exceed the maximum core
clock and system clock. Table 12 describes Phase-Locked Loop
operating conditions.
Table 10. Core Clock Requirements—500 MHz Speed Grade1
Parameter
Minimum
Maximum
500
Unit
MHz
MHz
MHz
MHz
MHz
fCCLK
fCCLK
fCCLK
fCCLK
fCCLK
Core Clock Frequency (VDDINT =1.2 V minimum)
Core Clock Frequency (VDDINT =1.045 V minimum)
Core Clock Frequency (VDDINT =0.95 V minimum)
Core Clock Frequency (VDDINT =0.85 V minimum)
Core Clock Frequency (VDDINT =0.8 V )
TBD
TBD
TBD
TBD
1 The speed grade of a given part is printed on the chip’s package as shown in Figure 8 on Page 22 and can also be seen on the “Ordering Guide” on page 59. It stands for the
Maximum allowed CCLK frequency at VDDINT = 1.2V and the maximum allowed VCO frequency at any supply voltage.
Table 11. Core Clock Requirements—400 MHz Speed Grade1
Parameter
fCCLK
Minimum
Maximum
400
Unit
MHz
MHz
MHz
MHz
MHz
Core Clock Frequency (VDDINT =1.14 V minimum)
Core Clock Frequency (VDDINT =1.045 V minimum)
Core Clock Frequency (VDDINT =0.95 V minimum)
Core Clock Frequency (VDDINT =0.85 V minimum)
Core Clock Frequency (VDDINT =0.8 V )
fCCLK
TBD
fCCLK
TBD
fCCLK
TBD
fCCLK
TBD
1 The speed grade of a given part is printed on the chip’s package as shown in Figure 8 on Page 22 and can also be seen on the “Ordering Guide” on page 59. It stands for the
Maximum allowed CCLK frequency at VDDINT = 1.2V and the maximum allowed VCO frequency at any supply voltage.
Table 12. Phase-Locked Loop Operating Conditions
Parameter
Minimum
Maximum
Speed Grade1 MHz
Unit
fVCO
Voltage Controlled Oscillator (VCO) Frequency
50
1 The speed grade of a given part is printed on the chip’s package as shown in Figure 8 on Page 22 and can also be seen on the “Ordering Guide” on page 59. It stands for the
Maximum allowed CCLK frequency at VDDINT = 1.2V and the maximum allowed VCO frequency at any supply voltage.
Table 13. System Clock Requirements
Parameter
Condition
Minimum
Maximum
Unit
182 MBGA
fSCLK
VDDEXT = 3.3 V, VDDINT >= TBD V
VDDEXT = 3.3 V, VDDINT < TBD V
VDDEXT = 2.5 V, VDDINT >= TBD V
VDDEXT = 2.5 V, VDDINT < TBD V
TBD
TBD
TBD
TBD
MHz
MHz
MHz
MHz
fSCLK
fSCLK
fSCLK
208 MBGA
fSCLK
VDDEXT = 3.3 V, VDDINT >= TBD V
VDDEXT = 3.3 V, VDDINT < TBD V
VDDEXT = 2.5 V, VDDINT >= TBD V
VDDEXT = 2.5 V, VDDINT < TBD V
TBD
TBD
TBD
TBD
MHz
MHz
MHz
MHz
fSCLK
fSCLK
fSCLK
Rev. PrE
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Page 23 of 60 | July 2005
ADSP-BF534
Preliminary Technical Data
Table 14. Clock Input and Reset Timing
Parameter
Minimum
Maximum
Unit
Timing Requirements
tCKIN
CLKIN Period1
CLKIN Low Pulse2
CLKIN High Pulse2
20.0
10.0
10.0
100.0
ns
ns
ns
ns
ns
tCKINL
tCKINH
tBUFDLAY
tWRST
CLKIN to CLKBUF delay
RESET Asserted Pulsewidth Low3
TBD
11 tCKIN
1 Combinations of the CLKIN frequency and the PLL clock multiplier must not exceed the allowed fVCO, fCCLK, and fSCLK settings discussed in Table 10 and Table 11. Since by
default the PLL is multiplying the CLKIN frequency by 10, 400MHz speed grade parts can not use the full CLKIN period range.
2 Applies to bypass mode and non-bypass mode.
3 Applies after power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 2000 CLKIN cycles, while RESET is asserted,
assuming stable power supplies and CLKIN (not including start-up time of external clock oscillator).
tCKIN
CLKIN
tCKINL
tCKINH
tBUFDLAY
tBUFDLAY
CLKBUF
tWRST
RESET
Figure 9. Clock and Reset Timing
Rev. PrE
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Page 24 of 60
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July 2005
Preliminary Technical Data
ADSP-BF534
Asynchronous Memory Read Cycle Timing
Table 15. Asynchronous Memory Read Cycle Timing
Parameter
Minimum
Maximum
Unit
Timing Requirements
tSDAT
DATA15–0 Setup Before CLKOUT
DATA15–0 Hold After CLKOUT
ARDY Setup Before CLKOUT
ARDY Hold After CLKOUT
2.1
0.8
4.0
0.0
ns
ns
ns
ns
tHDAT
tSARDY
tHARDY
Switching Characteristic
tDO
tHO
Output Delay After CLKOUT1
Output Hold After CLKOUT 1
6.0
ns
ns
0.8
1 Output pins include AMS3–0, ABE1–0, ADDR19–1, AOE, ARE.
HOLD
1 CYCLE
SETUP
2 CYCLES
PROGRAMMED READ ACCESS
4 CYCLES
ACCESS EXTENDED
3 CYCLES
CLKOUT
tDO
tHO
AMSx
ABE1–0
BE, ADDRESS
ADDR19–1
AOE
tDO
tHO
ARE
tHARDY
tSARDY
tHARDY
ARDY
tSARDY
tSDAT
tHDAT
DATA15–0
READ
Figure 10. Asynchronous Memory Read Cycle Timing
Rev. PrE
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Page 25 of 60 | July 2005
ADSP-BF534
Preliminary Technical Data
Asynchronous Memory Write Cycle Timing
Table 16. Asynchronous Memory Write Cycle Timing
Parameter
Minimum
Maximum
Unit
Timing Requirements
tSARDY
tHARDY
ARDY Setup Before CLKOUT
ARDY Hold After CLKOUT
4.0
0.0
ns
ns
Switching Characteristic
tDDAT
tENDAT
tDO
DATA15–0 Disable After CLKOUT
6.0
6.0
ns
ns
ns
ns
DATA15–0 Enable After CLKOUT
Output Delay After CLKOUT1
Output Hold After CLKOUT 1
1.0
0.8
tHO
1 Output pins include AMS3–0, ABE1–0, ADDR19–1, DATA15–0, AOE, AWE.
ACCESS
EXTENDED
1 CYCLE
SETUP
2 CYCLES
HOLD
1 CYCLE
PROGRAMMED WRITE
ACCESS 2 CYCLES
CLKOUT
AMSx
tDO
tHO
ABE1–0
BE, ADDRESS
ADDR19–1
tDO
tHO
AWE
tHARDY
tSARDY
ARDY
tSARDY
tENDAT
tDDAT
DATA15–0
WRITE DATA
Figure 11. Asynchronous Memory Write Cycle Timing
Rev. PrE
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Page 26 of 60
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July 2005
Preliminary Technical Data
ADSP-BF534
SDRAM Interface Timing
Table 17. SDRAM Interface Timing (VDDINT = 1.2 V)
Parameter
Minimum
Maximum
Unit
Timing Requirement
tSSDAT
tHSDAT
DATA Setup Before CLKOUT
DATA Hold After CLKOUT
2.1
0.8
ns
ns
Switching Characteristic
tSCLK
CLKOUT Period1
7.5
2.5
2.5
ns
ns
ns
ns
ns
ns
ns
tSCLKH
tSCLKL
tDCAD
tHCAD
tDSDAT
tENSDAT
CLKOUT Width High
CLKOUT Width Low
Command, ADDR, Data Delay After CLKOUT2
Command, ADDR, Data Hold After CLKOUT2
Data Disable After CLKOUT
6.0
6.0
0.8
Data Enable After CLKOUT
1.0
1 The tSCLK value is the inverse of the fSCLK specification discussed in Table 13. Package type and reduced supply voltages affect the best-case value of 7.5ns listed here.
2 Command pins include: SRAS, SCAS, SWE, SDQM, SMS, SA10, SCKE.
tSCLK
tSCLKH
CLKOUT
tSSDAT
tSCLKL
tHSDAT
DATA (IN)
tDCAD
tDSDAT
tENSDAT
tHCAD
DATA(OUT)
tDCAD
CMND ADDR
(OUT)
tHCAD
NOTE: COMMAND = SRAS, SCAS, SWE, SDQM, SMS, SA10, SCKE.
Figure 12. SDRAM Interface Timing
Rev. PrE
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Page 27 of 60 | July 2005
ADSP-BF534
Preliminary Technical Data
External Port Bus Request and Grant Cycle Timing
Table 18 and Figure 13 describe external port bus request and
bus grant operations.
Table 18. External Port Bus Request and Grant Cycle Timing
Parameter 1, 2
Minimum
Maximum
Unit
Timing Requirements
tBS
BR asserted to CLKOUT high setup
4.6
0.0
ns
ns
tBH
CLKOUT high to BR de-asserted hold time
Switching Characteristics
tSD
CLKOUT low to xMS, address, and RD/WR disable
4.5
4.5
3.6
3.6
3.6
3.6
ns
ns
ns
ns
ns
ns
tSE
CLKOUT low to xMS, address, and RD/WR enable
CLKOUT high to BG asserted setup
tDBG
tEBG
tDBH
tEBH
CLKOUT high to BG de-asserted hold time
CLKOUT high to BGH asserted setup
CLKOUT high to BGH de-asserted hold time
1 These are preliminary timing parameters that are based on worst-case operating conditions.
2 The pad loads for these timing parameters are 20 pF.
CLKOUT
tBS
tBH
BR
tSD
tSE
AMSx
tSD
tSE
ADDR19-1
ABE1-0
tSD
tSE
AWE
ARE
tDBG
tEBG
BG
tDBH
tEBH
BGH
Figure 13. External Port Bus Request and Grant Cycle Timing
Rev. PrE
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Page 28 of 60
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July 2005
Preliminary Technical Data
ADSP-BF534
External DMA Request Timing
Table 19 and Figure 14 describe the External DMA Request
operations.
Table 19. External DMA Request Timing
Parameter
Minimum
Maximum
Unit
Timing Parameters
tDR
tDH
DMARx asserted to CLKOUT high setup
TBD
TBD
TBD
TBD
ns
ns
CLKOUT high to DMARx de-asserted hold time
Switching Characteristics
tDO
tHO
Output delay after CLKOUT1
Output hold after CLKOUT1
TBD
TBD
TBD
TBD
ns
ns
1 System Outputs=DATA15–0, ADDR19–1, ABE1–0, AOE, ARE, AWE, AMS3–0, SRAS, SCAS, SWE, SCKE, CLKOUT, SA10, SMS, SCL, SDA, TSCLK0, TFS0, RFS0, RSCLK0,
DT0PRI, DT0SEC, PF15–0, PG15–0, PH15–0, RTX0, TD0, EMU, XTAL, VROUT.
CLKOUT
tDR
tDH
DMAR0/1
AMSx
tDO
tHO
Figure 14. External DMA Request Timing
Rev. PrE
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Page 29 of 60 | July 2005
ADSP-BF534
Preliminary Technical Data
Parallel Peripheral Interface Timing
Table 20 and Figure 15 on Page 30, Figure 16 on Page 33, and
Figure 17 on Page 34 describe Parallel Peripheral Interface
operations.
Table 20. Parallel Peripheral Interface Timing
Parameter
Minimum
Maximum
Unit
Timing Requirements
tPCLKW
tPCLK
PPI_CLK Width1
PPI_CLK Period1
6.0
ns
ns
15.0
Timing Requirements - GP Input and Frame Capture Modes
tSFSPE
tHFSPE
tSDRPE
tHDRPE
External Frame Sync Setup Before PPI_CLK
External Frame Sync Hold After PPI_CLK
Receive Data Setup Before PPI_CLK
Receive Data Hold After PPI_CLK
3.0
3.0
2.0
4.0
ns
ns
ns
ns
Switching Characteristics - GP Output and Frame Capture Modes
tDFSPE
tHOFSPE
tDDTPE
tHDTPE
Internal Frame Sync Delay After PPI_CLK
Internal Frame Sync Hold After PPI_CLK
Transmit Data Delay After PPI_CLK
Transmit Data Hold After PPI_CLK
10.0
10.0
ns
ns
ns
ns
0.0
0.0
1 PPI_CLK frequency cannot exceed fSCLK/2
DRIVE
EDGE
SAMPLE
EDGE
tPCLKW
PPI_CLK
tDFSPE
tHOFSPE
tSFSPE
tHFSPE
PPI_FS1
PPI_FS2
tDDTPE
tSDRPE
tHDRPE
tHDTPE
PPIx
Figure 15. Parallel Peripheral Interface Timing
Rev. PrE
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Page 30 of 60
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July 2005
Preliminary Technical Data
ADSP-BF534
Serial Ports
Table 21 through Table 26 on Page 32 and Figure 16 on Page 33
through Figure 18 on Page 35 describe Serial Port operations.
Table 21. Serial Ports—External Clock
Parameter
Minimum
Maximum
Unit
Timing Requirements
tSFSE
TFS/RFS Setup Before TSCLK/RSCLK1
TFS/RFS Hold After TSCLK/RSCLK1
Receive Data Setup Before RSCLK1
Receive Data Hold After RSCLK1
TSCLK/RSCLK Width
3.0
3.0
3.0
3.0
4.5
15.0
ns
ns
ns
ns
ns
ns
tHFSE
tSDRE
tHDRE
tSCLKEW
tSCLKE
TSCLK/RSCLK Period
1 Referenced to sample edge.
Table 22. Serial Ports—Internal Clock
Parameter
Minimum
Maximum
Unit
Timing Requirements
tSFSI
TFS/RFS Setup Before TSCLK/RSCLK1
8.0
ns
ns
ns
ns
ns
ns
tHFSI
TFS/RFS Hold After TSCLK/RSCLK1
Receive Data Setup Before RSCLK1
Receive Data Hold After RSCLK1
TSCLK/RSCLK Width
–2.0
6.0
tSDRI
tHDRI
tSCLKEW
tSCLKE
0.0
4.5
TSCLK/RSCLK Period
15.0
1 Referenced to sample edge.
Table 23. Serial Ports—External Clock
Parameter
Minimum
Maximum
10.0
Unit
Switching Characteristics
tDFSE
tHOFSE
tDDTE
tHDTE
TFS/RFS Delay After TSCLK/RSCLK (Internally Generated TFS/RFS)1
TFS/RFS Hold After TSCLK/RSCLK (Internally Generated TFS/RFS)1
Transmit Data Delay After TSCLK1
ns
ns
ns
ns
0.0
0.0
10.0
Transmit Data Hold After TSCLK1
1 Referenced to drive edge.
Table 24. Serial Ports—Internal Clock
Parameter
Minimum
Maximum
Unit
Switching Characteristics
tDFS
TFS/RFS Delay After TSCLK/RSCLK (Internally Generated TFS/RFS)1
TFS/RFS Hold After TSCLK/RSCLK (Internally Generated TFS/RFS)1
Transmit Data Delay After TSCLK1
3.0
3.0
ns
ns
ns
ns
ns
I
tHOFS
−1.0
I
tDDT
I
tHDT
Transmit Data Hold After TSCLK1
−2.0
I
tSCLKIW
TSCLK/RSCLK Width
4.5
1 Referenced to drive edge.
Rev. PrE
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Page 31 of 60 | July 2005
ADSP-BF534
Preliminary Technical Data
Table 25. Serial Ports—Enable and Three-State
Parameter
Minimum
0.0
Maximum
Unit
Switching Characteristics
tDTENE
tDDTTE
tDTENI
tDDTTI
Data Enable Delay from External TSCLK1
Data Disable Delay from External TSCLK1
Data Enable Delay from Internal TSCLK1
Data Disable Delay from Internal TSCLK1
ns
ns
ns
ns
10.0
3.0
–2.0
1 Referenced to drive edge.
Table 26. External Late Frame Sync
Parameter
Minimum
Maximum
Unit
Switching Characteristics
tDDTLFSE
Data Delay from Late External TFS or External RFS with MCE = 1, MFD = 01,2
Data Enable from late FS or MCE = 1, MFD = 01,2
10.0
ns
ns
tDTENLFSE
0.0
1 MCE = 1, TFS enable and TFS valid follow tDDTENFS and tDDTLFSE
2 If external RFS/TFS setup to RSCLK/TSCLK > tSCLKE/2 then tDDTLSCK and tDTENLSCK apply, otherwise tDDTLFSE and tDTENLFS apply.
.
Rev. PrE
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Page 32 of 60
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July 2005
Preliminary Technical Data
ADSP-BF534
DATA RECEIVE- INTERNAL CLOCK
DATA RECEIVE- EXTERNAL CLOCK
DRIVE
EDGE
SAMPLE
EDGE
DRIVE
EDGE
SAMPLE
EDGE
tSCLKIW
tSCLKEW
RSCLK
RSCLK
tDFSE
tDFSE
tHOFSE
RFS
tSFSI
tHFSI
tHOFSE
tSFSE
tHFSE
RFS
tSDRI
tHDRI
tSDRE
tHDRE
DR
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK, TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.
DR
DATA TRANSMIT- INTERNAL CLOCK
DATA TRANSMIT- EXTERNAL CLOCK
DRIVE
EDGE
SAMPLE
EDGE
DRIVE
EDGE
SAMPLE
EDGE
tSCLKIW
tSCLKEW
TSCLK
TSCLK
tDFSI
tDFSE
tHOFSI
tSFSI
tHFSI
tHOFSE
tSFSE
tHFSE
TFS
DT
TFS
tDDTI
tDDTE
tHDTI
tHDTE
DT
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK OR TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.
DRIVE
EDGE
DRIVE
EDGE
TSCLK (EXT)
TFS ("LATE", EXT.)
TSCLK / RSCLK
tDDTTE
tDDTENE
DT
DRIVE
EDGE
DRIVE
EDGE
TSCLK (INT)
TFS ("LATE", INT.)
TSCLK / RSCLK
tDDTENI
tDDTTI
DT
Figure 16. Serial Ports
Rev. PrE
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Page 33 of 60 | July 2005
ADSP-BF534
Preliminary Technical Data
EXTERNAL RFS WITH MCE = 1, MFD = 0
DRIVE
SAMPLE
DRIVE
RSCLK
RFS
tHOFSE/I
tSFSE/I
tDDTE/I
tDTENLFSE
tHDTE/I
1ST BIT
2ND BIT
DT
tDDTLFSE
LATE EXTERNAL TFS
DRIVE
SAMPLE
DRIVE
TSCLK
TFS
tSFSE/I
tHOFSE/I
tDDTE/I
tDTENLFSE
tHDTE/I
DT
1ST BIT
2ND BIT
tDDTLFSE
Figure 17. External Late Frame Sync (Frame Sync Setup < tSCLKE/2)
Rev. PrE
|
Page 34 of 60
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July 2005
Preliminary Technical Data
ADSP-BF534
EXTERNAL RFS WITH MCE=1, MFD=0
DRIVE
SAMPLE
DRIVE
RSCLK
RFS
tSFSE/I
tHOFSE/I
tDDTE/I
tHDTE/I
tDTENLSCK
1ST BIT
DT
2ND BIT
tDDTLSCK
LATE EXTERNAL TFS
DRIVE
SAMPLE
DRIVE
TSCLK
TFS
tSFSE/I
tHOFSE/I
tDDTE/I
tHDTE/I
tDTENLSCK
DT
1ST BIT
2ND BIT
tDDTLSCK
Figure 18. External Late Frame Sync (Frame Sync Setup > tSCLKE/2)
Rev. PrE
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Page 35 of 60 | July 2005
ADSP-BF534
Preliminary Technical Data
Serial Peripheral Interface (SPI) Port—Master Timing
Table 27 and Figure 19 describe SPI port master operations.
Table 27. Serial Peripheral Interface (SPI) Port—Master Timing
Parameter
Minimum
Maximum
Unit
Timing Requirements
tSSPIDM
tHSPIDM
Data input valid to SCK edge (data input setup)
SCK sampling edge to data input invalid
7.5
ns
ns
–1.5
Switching Characteristics
tSDSCIM
tSPICHM
tSPICLM
tSPICLK
SPISELx low to first SCK edge (x=0 or 1)
2tSCLK –1.5
2tSCLK –1.5
2tSCLK –1.5
4tSCLK –1.5
2tSCLK –1.5
2tSCLK –1.5
0
ns
ns
ns
ns
ns
ns
ns
ns
Serial clock high period
Serial clock low period
Serial clock period
tHDSM
Last SCK edge to SPISELx high (x=0 or 1)
Sequential transfer delay
tSPITDM
tDDSPIDM
tHDSPIDM
SCK edge to data out valid (data out delay)
SCK edge to data out invalid (data out hold)
6
–1.0
4.0
SPISELx
(OUTPUT)
tSPICLK
tHDSM
tSPITDM
tSDSCIM
tSPICHM
tSPICLM
SCK
(CPOL = 0)
(OUTPUT)
tSPICLM
tSPICHM
SCK
(CPOL = 1)
(OUTPUT)
tDDSPIDM
tHDSPIDM
MOSI
(OUTPUT)
MSB
LSB
CPHA=1
tSSPIDM
tHSPIDM
tSSPIDM
tHSPIDM
MISO
(INPUT)
MSB VALID
LSB VALID
tDDSPIDM
tHDSPIDM
MOSI
(OUTPUT)
MSB
LSB
CPHA=0
tSSPIDM
tHSPIDM
MISO
(INPUT)
MSB VALID
LSB VALID
Figure 19. Serial Peripheral Interface (SPI) Port—Master Timing
Rev. PrE
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Page 36 of 60
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July 2005
Preliminary Technical Data
ADSP-BF534
Serial Peripheral Interface (SPI) Port—Slave Timing
Table 28 and Figure 20 describe SPI port slave operations.
Table 28. Serial Peripheral Interface (SPI) Port—Slave Timing
Parameter
Minimum
Maximum
Unit
Timing Requirements
tSPICHS
tSPICLS
tSPICLK
tHDS
Serial clock high period
2tSCLK –1.5
2tSCLK –1.5
4tSCLK –1.5
2tSCLK –1.5
2tSCLK –1.5
2tSCLK –1.5
1.6
ns
ns
ns
ns
ns
ns
ns
ns
Serial clock low period
Serial clock period
Last SCK edge to SPISS not asserted
Sequential Transfer Delay
tSPITDS
tSDSCI
tSSPID
tHSPID
SPISS assertion to first SCK edge
Data input valid to SCK edge (data input setup)
SCK sampling edge to data input invalid
1.6
Switching Characteristics
tDSOE
SPISS assertion to data out active
0
0
0
0
8
ns
ns
ns
ns
tDSDHI
tDDSPID
tHDSPID
SPISS deassertion to data high impedance
SCK edge to data out valid (data out delay)
SCK edge to data out invalid (data out hold)
8
10
10
SPISS
(INPUT)
tSPICHS
tSPICLS
tSPICLK
tHDS
tSPITDS
SCK
(CPOL = 0)
(INPUT)
tSDSCI
tSPICLS
tSPICHS
SCK
(CPOL = 1)
(INPUT)
tDSOE
tDDSPID
tHDSPID
MSB
tDDSPID
tDSDHI
LSB
MISO
(OUTPUT)
tHSPID
tSSPID
CPHA=1
tSSPID
tHSPID
MOSI
(INPUT)
MSB VALID
LSB VALID
tDSOE
tDDSPID
tDSDHI
MISO
(OUTPUT)
MSB
LSB
tHSPID
CPHA=0
tSSPID
MOSI
(INPUT)
MSB VALID
LSB VALID
Figure 20. Serial Peripheral Interface (SPI) Port—Slave Timing
Rev. PrE
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ADSP-BF534
Preliminary Technical Data
Universal Asynchronous Receiver-Transmitter
(UART) Ports—Receive and Transmit Timing
Figure 21 describes the UART ports receive and transmit opera-
tions. The maximum baud rate is SCLK/16. As shown in
Figure 21 there is some latency between the generation of
internal UART interrupts and the external data operations.
These latencies are negligible at the data transmission rates for
the UART.
CLKOUT
(SAMPLE CLOCK)
UARTX RX
DATA(5–8)
STOP
RECEIVE
INTERNAL
UART RECEIVE
INTERRUPT
UART RECEIVE BIT SET BY DATA STOP;
CLEARED BY FIFO READ
START
UARTX TX
DATA(5–8)
STOP (1–2)
TRANSMIT
INTERNAL
UART TRANSMIT
INTERRUPT
UART TRANSMIT BIT SET BY PROGRAM;
CLEARED BY WRITE TO TRANSMIT
Figure 21. UART Ports—Receive and Transmit Timing
Rev. PrE
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July 2005
Preliminary Technical Data
ADSP-BF534
General-Purpose Port Timing
Table 29 and Figure 22 describe general-purpose port
operations.
Table 29. General-Purpose Port Timing
Parameter
Minimum
Maximum
Unit
Timing Requirement
tWFI
General-purpose port pin input pulsewidth
General-purpose port pin input setup
General-purpose port pin input hold
tSCLK + 1
TBD
ns
ns
ns
tGPPIS
tGPPIH
Switching Characteristic
tGPOD General-purpose port pin output delay from CLKOUT low
TBD
0
6
ns
CLKOUT
tGPOD
GPP OUTPUT
tGPPIS
tGPPIH
GPP INPUT
tWFI
Figure 22. General-Purpose Port Timing
Rev. PrE
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ADSP-BF534
Preliminary Technical Data
Timer Cycle Timing
Table 30 and Figure 23 describe timer expired operations. The
input signal is asynchronous in “width capture mode” and
“external clock mode” and has an absolute maximum input fre-
quency of fSCLK/2 MHz.
Table 30. Timer Cycle Timing
Parameter
Minimum
Maximum
Unit
Timing Characteristics
tWL
tWH
tTIS
tTIH
Timer pulsewidth input low1 (measured in SCLK cycles)
Timer pulsewidth input high1 (measured in SCLK cycles)
Timer input setup time before CLKOUT low
1
SCLK
SCLK
ns
1
TBD
TBD
Timer input hold time after CLKOUT low
ns
Switching Characteristic
tHTO
Timer pulsewidth output2 (measured in SCLK cycles)
tTOD Timer output update delay after CLKOUT low
1
0
(232–1)
TBD
SCLK
ns
1 The minimum pulsewidths apply for TMRx signals in width capture and external clock modes. They also apply to the PF15 or PPI_CLK signals in PWM output mode.
2 The minimum time for tHTO is one cycle, and the maximum time for tHTO equals (232–1) cycles.
CLKOUT
tTOD
TIMER OUTPUT
tTIS
tTIH
TIMER INPUT
Figure 23. Timer Cycle Timing
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July 2005
Preliminary Technical Data
ADSP-BF534
JTAG Test And Emulation Port Timing
Table 31 and Figure 24 describe JTAG port operations.
Table 31. JTAG Port Timing
Parameter
Minimum
Maximum
Unit
Timing Parameters
tTCK
TCK Period
20
4
ns
tSTAP
tHTAP
tSSYS
tHSYS
tTRSTW
TDI, TMS Setup Before TCK High
TDI, TMS Hold After TCK High
System Inputs Setup Before TCK High1
System Inputs Hold After TCK High1
TRST Pulsewidth2 (measured in TCK cycles)
ns
4
ns
4
ns
5
ns
4
TCK
Switching Characteristics
tDTDO TDO Delay from TCK Low
tDSYS
System Outputs Delay After TCK Low3
10
12
ns
ns
0
1 System Inputs=DATA15–0, BR, ARDY, SCL, SDA, TFS0, TSCLK0, RSCLK0, RFS0, DR0PRI, DR0SEC, PF15–0, PG15–0, PH15–0, RTXI, TCK, TD1, TMS, TRST, CLKIN,
RESET, NMI, BMODE2–0.
2 50 MHz Maximum
3 System Outputs=DATA15–0, ADDR19–1, ABE1–0, AOE, ARE, AWE, AMS3–0, SRAS, SCAS, SWE, SCKE, CLKOUT, SA10, SMS, SCL, SDA, TSCLK0, TFS0, RFS0, RSCLK0,
DT0PRI, DT0SEC, PF15–0, PG15–0, PH15–0, RTX0, TD0, EMU, XTAL, VROUT.
tTCK
TCK
tSTAP
tHTAP
TMS
TDI
tDTDO
TDO
tSSYS
tHSYS
SYSTEM
INPUTS
tDSYS
SYSTEM
OUTPUTS
Figure 24. JTAG Port Timing
Rev. PrE
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ADSP-BF534
Preliminary Technical Data
TWI Controller Timing
Table 32 through Table 39 and Figure 25 through Figure 28
describe the TWI Controller operations.
Table 32. TWI Controller Timing: Bus Start/Stop Bits, Slave Mode, 100 kHz
Parameter
Minimum
TBD
Maximum
Unit
ns
tSU:STA
tHD:STA
tSU:STO
tHD:STO
Start condition setup time
Start condition hold time
Stop condition setup time
Stop condition hold time
-
-
-
-
TBD
ns
TBD
ns
TBD
ns
Table 33. TWI Controller Timing: Bus Start/Stop Bits, Slave Mode, 400 kHz
Parameter
Minimum
TBD
Maximum
Unit
ns
tSU:STA
tHD:STA
tSU:STO
tHD:STO
Start condition setup time
Start condition hold time
Stop condition setup time
Stop condition hold time
-
-
-
-
TBD
ns
TBD
ns
TBD
ns
Table 34. TWI Controller Timing: Bus Data Requirements, Slave Mode, 100 kHz
Parameter
Minimum
Maximum
Unit
µs
µs
ns
ns
µs
µs
ns
ns
µs
ns
µs
pF
tHIGH
tLOW
tR
Clock high time
TBD
TBD
-
-
Clock low time
-
SDA and SCL rise time
SDA and SCL fall time
Start condition setup time
Start condition hold time
Data input hold time
Data input setup time1
Stop condition setup time
Output valid from clock2
Bus free time
TBD
tF
-
TBD
tSU:STA
tHD:STA
tHD:DAT
tSU:DAT
tSU:STO
tTAA
TBD
TBD
TBD
TBD
TBD
-
-
-
-
-
-
TBD
-
tBUF
TBD
-
CB
Bus capacitive loading
TBD
1 As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. TBD ns) of the falling edge of SCL to avoid unintended
generation of START or STOP conditions.
2 A Fast mode TWI bus device can be used in a Standard mode TWI bus system, but the requirement TSU:DAT >= 250 ns must then be met. This will automatically be the case if
the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA
line. Before the SCL line is released, TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification).
Rev. PrE
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July 2005
Preliminary Technical Data
ADSP-BF534
Table 35. TWI Controller Timing: Bus Data Requirements, Slave Mode, 400 kHz
Parameter
Minimum
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
-
Maximum
Unit
µs
µs
ns
ns
µs
µs
µs
ns
µs
ns
µs
pF
tHIGH
tLOW
tR
Clock high time
-
Clock low time
-
SDA and SCL rise time
SDA and SCL fall time
Start condition setup time
Start condition hold time
Data input hold time
Data input setup time1
Stop condition setup time
Output valid from clock
Bus free time
TBD
tF
TBD
tSU:STA
tHD:STA
tHD:DAT
tSU:DAT
tSU:STO
tTAA
-
-
TBD
-
-
-
tBUF
TBD
-
CB
Bus capacitive loading
-
TBD
1 As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. TBD ns) of the falling edge of SCL to avoid unintended
generation of START or STOP conditions.
Table 36. TWI Controller Timing: Bus Start/Stop Bits, Master Mode, 100 kHz
Parameter
tSU:STA
Minimum
TBD
Maximum
Unit
ns
Start condition setup time
Start condition hold time
Stop condition setup time
Stop condition hold time
-
-
-
-
tHD:STA
TBD
ns
tSU:STO
TBD
ns
tHD:STO
TBD
ns
Table 37. TWI Controller Timing: Bus Start/Stop Bits, Master Mode, 400 kHz
Parameter
Minimum
TBD
Maximum
Unit
ns
tSU:STA
tHD:STA
tSU:STO
tHD:STO
Start condition setup time
Start condition hold time
Stop condition setup time
Stop condition hold time
-
-
-
-
TBD
ns
TBD
ns
TBD
ns
Table 38. TWI Controller Timing: Bus Data Requirements, Master Mode, 100 kHz
Parameter
Minimum
Maximum
Unit
ms
ms
ns
tHIGH
tLOW
tR
Clock high time
TBD
TBD
-
-
Clock low time
-
SDA and SCL rise time
SDA and SCL fall time
Start condition setup time
Start condition hold time
Data input hold time
Data input setup time1
Stop condition setup time
Output valid from clock
Bus free time
TBD
tF
-
TBD
ns
tSU:STA
tHD:STA
tHD:DAT
tSU:DAT
tSU:STO
tTAA
TBD
TBD
TBD
TBD
TBD
-
-
ms
ms
ns
-
-
-
ns
-
ms
ns
TBD
-
tBUF
TBD
ms
CB
Bus capacitive loading
-
TBD
pF
1 A Fast mode TWI bus device can be used in a Standard mode TWI bus system, but the requirement TSU:DAT >= 250 ns must then be met. This will automatically be the case if
the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA
line. Before the SCL line is released, TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification).
Rev. PrE
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ADSP-BF534
Preliminary Technical Data
Table 39. TWI Controller Timing: Bus Data Requirements, Master Mode, 400 kHz
Parameter
Minimum
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
-
Maximum
Unit
ms
ms
ns
tHIGH
tLOW
tR
Clock high time
-
Clock low time
-
SDA and SCL rise time
SDA and SCL fall time
Start condition setup time
Start condition hold time
Data input hold time
Data input setup time1
Stop condition setup time
Output valid from clock
Bus free time
TBD
tF
TBD
ns
tSU:STA
tHD:STA
tHD:DAT
tSU:DAT
tSU:STO
tTAA
-
ms
ms
ns
-
TBD
-
ns
-
ms
ns
-
tBUF
TBD
-
ms
CB
Bus capacitive loading
-
TBD
pF
1 A Fast mode TWI bus device can be used in a Standard mode TWI bus system, but the requirement TSU:DAT >= 250 ns must then be met. This will automatically be the case if
the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA
line. Before the SCL line is released, TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification).
SCL
tHD:STA
tHD:STO
tSU:STA
tSU:STO
SDA
STOP
START
Figure 25. TWI Controller Timing: Bus Start/Stop Bits, Slave Mode
tF
tR
tHIGH
tLO W
SCL
tSU:S TA
tHD:STA
tHD:DAT
tS U:DAT
tS U:STO
SDA
(I N)
tAA
tBUF
tAA
SDA
(OUT)
Figure 26. TWI Controller Timing: Bus Data, Slave Mode
Rev. PrE
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July 2005
Preliminary Technical Data
ADSP-BF534
SCL
tHD:STA
tHD:STO
tSU:STA
tSU:STO
SDA
STOP
START
Figure 27. TWI Controller Timing: Bus Start/Stop Bits, Master Mode
tF
tR
tHIGH
tLO W
SCL
tSU:S TA
tHD:STA
tHD:DAT
tS U:DAT
tS U:STO
SDA
(I N)
tAA
tBUF
tAA
SDA
(OUT)
Figure 28. TWI Controller Timing: Bus Data, Master Mode
Rev. PrE
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ADSP-BF534
Preliminary Technical Data
OUTPUT DRIVE CURRENTS
Figure 29 through Figure 38 show typical current-voltage char-
acteristics for the output drivers of the ADSP-BF534 processor.
The curves represent the current drive capability of the output
drivers as a function of output voltage. See Table 9 on page 17
for information about which driver type corresponds to a par-
ticular pin.
150
100
50
0
–50
TBD
150
100
50
–100
–150
0
0.5
1.0
1.5
2.0
2.5
3.0
SOURCE VOLTAGE (V)
0
TBD
Figure 31. Drive Current B (Low VDDEXT
)
–50
–100
–150
150
100
50
0
0.5
1.0
1.5
2.0
2.5
3.0
SOURCE VOLTAGE (V)
Figure 29. Drive Current A (Low VDDEXT
)
0
–50
TBD
150
100
50
–100
–150
0
0.5
1.0
1.5
2.0
2.5
3.0
SOURCE VOLTAGE (V)
0
–50
TBD
Figure 32. Drive Current B (High VDDEXT
)
–100
–150
0
0.5
1.0
1.5
2.0
2.5
3.0
SOURCE VOLTAGE (V)
Figure 30. Drive Current A (High VDDEXT
)
Rev. PrE
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|
July 2005
Preliminary Technical Data
ADSP-BF534
150
100
50
150
100
50
0
0
–50
TBD
TBD
–50
–100
–150
–100
–150
0
0
0.5
1.0
1.5
2.0
2.5
3.0
0.5
1.0
1.5
2.0
2.5
3.0
SOURCE VOLTAGE (V)
SOURCE VOLTAGE (V)
Figure 33. Drive Current C (Low VDDEXT
)
Figure 35. Drive Current D (Low VDDEXT)
150
100
50
150
100
50
0
–50
0
–50
TBD
TBD
–100
–150
–100
–150
0
0
0.5
1.0
1.5
2.0
2.5
3.0
0.5
1.0
1.5
2.0
2.5
3.0
SOURCE VOLTAGE (V)
SOURCE VOLTAGE (V)
Figure 34. Drive Current C (High VDDEXT
)
Figure 36. Drive Current D (High VDDEXT)
Rev. PrE
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ADSP-BF534
Preliminary Technical Data
150
100
50
0
–50
TBD
–100
–150
0
0.5
1.0
1.5
2.0
2.5
3.0
SOURCE VOLTAGE (V)
Figure 37. Drive Current E (Low VDDEXT
)
150
100
50
0
–50
TBD
–100
–150
0
0.5
1.0
1.5
2.0
2.5
3.0
SOURCE VOLTAGE (V)
Figure 38. Drive Current E (High VDDEXT
)
Rev. PrE
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July 2005
Preliminary Technical Data
ADSP-BF534
The frequency f includes driving the load high and then back
low. For example: DATA15–0 pins can drive high and low at a
maximum rate of 1/(2
؋
tSCLK) while in SDRAM burst mode. POWER DISSIPATION
Total power dissipation has two components: one due to inter-
nal circuitry (PINT) and one due to the switching of external
output drivers (PEXT). Table 40 shows the power dissipation for
internal circuitry (VDDINT). Internal power dissipation is depen-
dent on the instruction execution sequence and the data
operands involved.
A typical power consumption can now be calculated for these
conditions by adding a typical internal power dissipation:
P
= P
+ (I
× V
)
TOTAL
EXT
DD
DDINT
The external component of total power dissipation is caused by
the switching of output pins. Its magnitude depends on:
Note that the conditions causing a worst-case PEXT differ from
those causing a worst-case PINT . Maximum PINT cannot occur
while 100% of the output pins are switching from all ones (1s) to
all zeros (0s). Note, as well, that it is not common for an applica-
tion to have 100% or even 50% of the outputs switching
simultaneously.
• Maximum frequency (f0) at which all output pins can
switch during each cycle
• Load capacitance (C0) of all switching output pins
• Their voltage swing (VDDEXT
)
The external component is calculated using:
TEST CONDITIONS
2
All timing parameters appearing in this data sheet were mea-
sured under the conditions described in this section.
P
= V
×
C
f
∑
EXT
DDEXT
0
0
Output Enable Time
Table 40. Internal Power Dissipation
Output pins are considered to be enabled when they have made
a transition from a high impedance state to the point when they
start driving. The output enable time tENA is the interval from
the point when a reference signal reaches a high or low voltage
level to the point when the output starts driving as shown in the
Output Enable/Disable diagram (Figure 39). The time
Test Conditions1
Parameter fCCLK
=
fCCLK
=
fCCLK
=
fCCLK
=
Unit
50 MHz 150 MHz 250 MHz 400 MHz
VDDINT
0.8 V
=
VDDINT
0.9 V
=
VDDINT
1.0 V
=
VDDINT
1.2 V
=
t
ENA_MEASURED is the interval from when the reference signal
2
IDDTYP
TBD
TBD
TBD
TBD
50
TBD
TBD
TBD
TBD
50
TBD
TBD
TBD
TBD
50
TBD
TBD
TBD
TBD
50
mA
mA
mA
mA
µA
switches to when the output voltage reaches 2.0 V (output high)
or 1.0 V (output low). Time tTRIP is the interval from when the
output starts driving to when the output reaches the 1.0 V or
2.0 V trip voltage. Time tENA is calculated as shown in the
equation:
3
IDDEFR
45
IDDSLEEP
IDDDEEPSLEEP
IDDHIBERNATE
4
5
Parameter
fCCLK
=
fCCLK
=
fCCLK
=
Unit
200 MHz 400 MHz 500 MHz
t
= t
– t
ENA_MEASURED TRIP
ENA
VDDINT
0.9 V
=
VDDINT
1.0 V
=
VDDINT
1.2 V
=
If multiple pins (such as the data bus) are enabled, the measure-
ment value is that of the first pin to start driving.
2
IDDTYP
-
-
-
-
-
TBD
TBD
TBD
TBD
50
TBD
TBD
TBD
TBD
50
TBD
TBD
TBD
TBD
50
mA
mA
mA
mA
µA
3
IDDEFR
45
IDDSLEEP
4
IDDDEEPSLEEP
5
IDDHIBERNATE
1 IDD data is specified for typical process parameters. All data at 25ºC.
2 Processor executing 75% dual Mac, 25% ADD with moderate data bus activity.
3 Implementation of Enhanced Full Rate (EFR) GSM algorithm.
4 See the ADSP-BF537 Blackfin Processor Hardware Reference Manual for defini-
tions of Sleep and Deep Sleep operating modes.
5 IDDHIBERNATE is measured @ VDDEXT = 3.65 V with VR off (VDDCORE = 0 V).
Rev. PrE
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Page 49 of 60 | July 2005
ADSP-BF534
Preliminary Technical Data
Output Disable Time
Example System Hold Time Calculation
Output pins are considered to be disabled when they stop driv-
ing, go into a high impedance state, and start to decay from their
output high or low voltage. The time for the voltage on the bus
to decay by ∆V is dependent on the capacitive load, CL and the
load current, IL. This decay time can be approximated by the
equation:
To determine the data output hold time in a particular system,
first calculate tDECAY using the equation given above. Choose ∆V
to be the difference between the ADSP-BF534 processor’s out-
put voltage and the input threshold for the device requiring the
hold time. A typical ∆V will be 0.4 V. CL is the total bus capaci-
tance (per data line), and IL is the total leakage or three-state
current (per data line). The hold time will be tDECAY plus the
minimum disable time (for example, tDSDAT for an SDRAM write
cycle).
t
= (C ∆V) ⁄ I
DECAY
L
L
The output disable time tDIS is the difference between
tDIS_MEASURED and tDECAY as shown in Figure 39. The time
50V
TO
OUTPUT
PIN
t
DIS_MEASURED is the interval from when the reference signal
1.5V
switches to when the output voltage decays ∆V from the mea-
sured output high or output low voltage. The time tDECAY is
calculated with test loads CL and IL, and with ∆V equal to 0.5 V.
30pF
Figure 40. Equivalent Device Loading for AC Measurements
(Includes All Fixtures)
REFERENCE
SIGNAL
tDIS_MEASURED
tENA-MEASURED
tDIS
VOH
tENA
INPUT
OR
OUTPUT
1.5V
1.5V
VOH
(MEASURED)
VOH (MEASURED) ؊ ⌬V
VOL (MEASURED) + ⌬V
2.0V
1.0V
(MEASURED)
VOL
VOL
Figure 41. Voltage Reference Levels for AC
(MEASURED)
(MEASURED)
tDECAY
tTRIP
Measurements (Except Output Enable/Disable)
OUTPUT STOPS DRIVING
OUTPUT STARTS DRIVING
HIGH IMPEDANCE STATE.
TEST CONDITIONS CAUSE THIS
VOLTAGE TO BE APPROXIMATELY 1.5V.
Figure 39. Output Enable/Disable
Rev. PrE
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July 2005
Preliminary Technical Data
ADSP-BF534
ENVIRONMENTAL CONDITIONS
To determine the junction temperature on the application
printed circuit board use:
T
= T
+ (Ψ × P )
JT
J
CASE
D
where:
TJ = Junction temperature (؇C)
TCASE = Case temperature (؇C) measured by customer at top
center of package.
Ψ = From Table 41
JT
PD = Power dissipation (see Power Dissipation on Page 49 for
the method to calculate PD)
Values of θJA are provided for package comparison and printed
circuit board design considerations. θJA can be used for a first
order approximation of TJ by the equation:
T
= T + (θ × P )
JA
J
A
D
where:
TA = Ambient temperature (؇C)
Values of θJC are provided for package comparison and printed
circuit board design considerations when an external heatsink is
required.
Values of θJB are provided for package comparison and printed
circuit board design considerations.
In Table 41, airflow measurements comply with JEDEC stan-
dards JESD51-2 and JESD51-6, and the junction-to-board
measurement complies with JESD51-8. The junction-to-case
measurement complies with MIL-STD-883 (Method 1012.1).
All measurements use a 2S2P JEDEC test board.
Table 41. Thermal Characteristics
Parameter Condition
Typical Unit
؇C/W
θJA
0 linear m/s air flow
θJMA
θJMA
θJB
1 linear m/s air flow
2 linear m/s air flow
؇C/W
؇C/W
؇C/W
θJC
؇C/W
Ψ
JT
0 linear m/s air flow
؇C/W
Rev. PrE
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Page 51 of 60 | July 2005
ADSP-BF534
Preliminary Technical Data
182-BALL MINI-BGA PINOUT
Table 42 lists the mini-BGA pinout by signal mnemonic.
Table 43 on Page 53 lists the mini-BGA pinout by ball number.
Table 42. 182-Ball Mini-BGA Ball Assignment (Alphabetically by Signal Mnemonic)
Mnemonic Ball no.
Mnemonic Ball no.
Mnemonic Ball no.
Mnemonic Ball no.
Mnemonic Ball no.
ABE0
H13
H12
J14
CLKOUT
DATA0
DATA1
DATA10
DATA11
DATA12
DATA13
DATA14
DATA15
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
DATA8
DATA9
EMU
B14
M9
N9
N6
P6
GND
GND
GND
GND
GND
GND
NMI
PF0
L6
PG8
PG9
PH0
PH1
PH10
PH11
PH12
PH13
PH14
PH15
PH2
PH3
PH4
PH5
PH6
PH7
PH8
PH9
PJ0
E3
SRAS
D13
D12
P2
ABE1
L8
E4
SWE
ADDR1
ADDR10
ADDR11
ADDR12
ADDR13
ADDR14
ADDR15
ADDR16
ADDR17
ADDR18
ADDR19
ADDR2
ADDR3
ADDR4
ADDR5
ADDR6
ADDR7
ADDR8
ADDR9
AMS0
L10
M4
M10
P14
B10
M1
L1
C2
TCK
M13
M14
N14
N13
N12
M11
N11
P13
P12
P11
K14
L14
J13
C3
TDI
M3
N3
B6
TDO
M5
N5
P5
A2
A3
A4
A5
A6
C4
TMS
N2
TRST
N1
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDRTC
VROUT0
VROUT1
XTAL
A1
P4
PF1
C12
E6
P9
PF10
PF11
PF12
PF13
PF14
PF15
PF2
J2
M8
N8
P8
J3
E11
F4
H1
H2
H3
H4
L2
C5
C6
F12
H5
M7
N7
P7
B1
B2
H10
J11
J12
K7
B3
K13
L13
K12
L12
M12
E14
F14
F13
G12
G13
E13
G14
H14
P10
N10
N4
M6
M2
A10
A14
D4
E7
PF3
L3
B4
PF4
L4
B5
GND
PF5
K1
K2
K3
K4
J1
C7
K9
GND
PF6
PJ1
B7
L7
GND
PF7
PJ10
PJ11
PJ2
D10
D11
B11
C11
D7
D8
C8
L9
GND
PF8
L11
P1
AMS1
GND
E9
PF9
AMS2
GND
F5
PG0
PG1
PG10
PG11
PG12
PG13
PG14
PG15
PG2
PG3
PG4
PG5
PG6
PG7
G1
G2
D1
D2
D3
D5
D6
C1
G3
F1
PJ3
E5
AMS3
GND
F6
PJ4
E8
AOE
GND
F10
F11
G4
G5
G11
H11
J4
PJ5
E10
G10
K5
ARDY
GND
PJ6
ARE
GND
PJ7
B8
AWE
GND
PJ8
D9
C9
K8
BG
GND
PJ9
K10
B9
BGH
GND
RESET
RTXO
RTXI
SA10
SCAS
SCKE
SMS
C10
A8
A9
E12
C14
B13
C13
BMODE0
BMODE1
BMODE2
BR
GND
A13
B12
A11
P3
GND
J5
L5
GND
J9
F2
D14
A7
GND
J10
K6
F3
CLKBUF
CLKIN
GND
E1
A12
GND
K11
E2
Rev. PrE
|
Page 52 of 60
|
July 2005
Preliminary Technical Data
ADSP-BF534
Table 43 lists the mini-BGA pinout by ball number. Table 42 on
Page 52 lists the mini-BGA pinout by signal mnemonic.
Table 43. 182-Ball Mini-BGA Ball Assignment (Numerically by Ball Number)
Ball no.
A1
Mnemonic Ball no.
Mnemonic Ball no.
Mnemonic Ball no.
Mnemonic Ball no.
Mnemonic
DATA0
GND
VDDEXT
PH11
PH12
PH13
PH14
PH15
CLKBUF
RTXO
RTXI
C10
C11
C12
C13
C14
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
E1
RESET
PJ3
F5
GND
J14
K1
ADDR1
PF5
M9
M10
M11
M12
M13
M14
N1
A2
F6
GND
A3
VDDEXT
SMS
F10
F11
F12
F13
F14
G1
GND
K2
PF6
ADDR15
ADDR9
ADDR10
ADDR11
TRST
A4
GND
K3
PF7
A5
SCAS
PG10
PG11
PG12
GND
PG13
PG14
PJ4
VDDEXT
AMS2
AMS1
PG0
K4
PF8
A6
K5
VDDINT
GND
A7
K6
A8
K7
VDDEXT
VDDINT
VDDEXT
VDDINT
GND
N2
TMS
A9
G2
PG1
K8
N3
TDO
A10
A11
A12
A13
A14
B1
GND
XTAL
CLKIN
VROUT0
GND
PH5
G3
PG2
K9
N4
BMODE0
DATA13
DATA10
DATA7
DATA4
DATA1
BGH
G4
GND
K10
K11
K12
K13
K14
L1
N5
G5
GND
N6
PJ5
G10
G11
G12
G13
G14
H1
VDDINT
GND
ADDR7
ADDR5
ADDR2
PF1
N7
PJ8
N8
PJ10
AMS3
AOE
N9
B2
PH6
PJ11
N10
N11
N12
N13
N14
P1
B3
PH7
SWE
ARE
L2
PF2
ADDR16
ADDR14
ADDR13
ADDR12
VDDEXT
TCK
B4
PH8
SRAS
BR
PF12
PF13
PF14
PF15
VDDEXT
VDDEXT
GND
L3
PF3
B5
PH9
H2
L4
PF4
B6
PH10
PJ1
PG6
H3
L5
BMODE2
GND
B7
E2
PG7
H4
L6
B8
PJ7
E3
PG8
H5
L7
VDDEXT
GND
P2
B9
VDDRTC
NMI
E4
PG9
H10
H11
H12
H13
H14
J1
L8
P3
BMODE1
DATA15
DATA14
DATA11
DATA8
DATA5
DATA2
BG
B10
B11
B12
B13
B14
C1
E5
VDDINT
VDDEXT
GND
VDDINT
GND
VDDINT
VDDEXT
SA10
ARDY
AMS0
PG3
L9
VDDEXT
GND
P4
PJ2
E6
ABE1
ABE0
AWE
L10
L11
L12
L13
L14
M1
M2
M3
M4
M5
M6
M7
M8
P5
VROUT1
SCKE
CLKOUT
PG15
PH0
E7
VDDEXT
ADDR8
ADDR6
ADDR3
PF0
P6
E8
P7
E9
PF9
P8
E10
E11
E12
E13
E14
F1
J2
PF10
PF11
GND
P9
C2
J3
P10
P11
P12
P13
P14
C3
PH1
J4
EMU
ADDR19
ADDR18
ADDR17
GND
C4
PH2
J5
GND
TDI
C5
PH3
J9
GND
GND
C6
PH4
J10
J11
J12
J13
GND
DATA12
DATA9
DATA6
DATA3
C7
PJ0
F2
PG4
VDDEXT
VDDEXT
ADDR4
C8
PJ6
F3
PG5
C9
PJ9
F4
VDDEXT
Rev. PrE
|
Page 53 of 60 | July 2005
ADSP-BF534
Preliminary Technical Data
Figure 42 shows the top view of the mini-BGA ball configura-
tion. Figure 43 shows the bottom view of the mini-BGA ball
configuration.
1
2
3
4
5
6
7
8
9
10 11 12 13 14
A
B
C
D
E
F
G
H
J
K
L
M
N
P
KEY:
VDDINT
VDDEXT
VDDRTC
VROUT
GND
I/O
NC
Figure 42. 182-Ball Mini-BGA Ball Configuration (Top View)
14 13 12 11 10
9
8
7
6
5
4
3
2
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
KEY:
VDDINT
VDDRTC
VROUT
GND
NC
VDDEXT
I/O
Figure 43. 182-Ball Mini-BGA Ball Configuration (Bottom View)
Rev. PrE
|
Page 54 of 60
|
July 2005
Preliminary Technical Data
ADSP-BF534
208-BALL SPARSE MINI-BGA PINOUT
Table 44 lists the sparse mini-BGA pinout by signal mnemonic.
Table 45 on Page 56 lists the sparse mini-BGA pinout by ball
number.
Table 44. 208-Ball Sparse Mini-BGA Ball Assignment (Alphabetically by Signal Mnemonic)
Mnemonic Ball no.
Mnemonic Ball no.
Mnemonic Ball no.
Mnemonic Ball no.
Mnemonic Ball no.
ABE0
P19
P20
R19
W18
Y18
W17
Y17
W16
Y16
W15
Y15
W14
Y14
T20
T19
U20
U19
V20
V19
W20
Y19
M20
M19
G20
G19
N20
J19
DATA12
DATA13
DATA14
DATA15
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
DATA8
DATA9
EMU
Y4
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
NMI
PF0
M13
N9
N10
N11
N12
N13
P11
V2
PG6
PG7
PG8
PG9
PH0
PH1
PH10
PH11
PH12
PH13
PH14
PH15
PH2
PH3
PH4
PH5
PH6
PH7
PH8
PH9
PJ0
E2
TDI
V1
ABE1
W4
Y3
D1
TDO
Y2
ADDR1
ADDR10
ADDR11
ADDR12
ADDR13
ADDR14
ADDR15
ADDR16
ADDR17
ADDR18
ADDR19
ADDR2
ADDR3
ADDR4
ADDR5
ADDR6
ADDR7
ADDR8
ADDR9
AMS0
D2
TMS
U2
W3
Y9
C1
TRST
U1
B4
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDRTC
VROUT0
VROUT1
XTAL
G7
W9
Y8
A5
G8
B9
G9
W8
Y7
A10
B10
A11
B11
A12
B5
G10
H7
W2
W19
Y1
W7
Y6
H8
J7
W6
T1
Y13
Y20
C20
T2
J8
K7
GND
A1
A6
K8
GND
A13
A20
B2
B6
L7
GND
PF1
R1
A7
L8
GND
PF10
PF11
PF12
PF13
PF14
PF15
PF2
L2
B7
M7
M8
N7
GND
G11
H9
K1
A8
GND
K2
B8
GND
H10
H11
H12
H13
J9
J1
A9
N8
GND
J2
B12
B13
B19
C19
D19
E19
B18
A19
B15
B16
B17
B20
D20
A15
A14
L20
K20
H20
J20
K19
L19
W1
P7
GND
H1
R2
PJ1
P8
AMS1
GND
PJ10
PJ11
PJ2
P9
AMS2
GND
PF3
P1
P10
G12
G13
G14
H14
J14
K14
L14
M14
N14
P12
P13
P14
A16
E20
F20
A17
AMS3
GND
J10
J11
J12
J13
K9
PF4
P2
AOE
GND
PF5
N1
N2
M1
M2
L1
PJ3
ARDY
GND
PF6
PJ4
ARE
N19
R20
Y11
Y12
W13
W12
W11
F19
B14
A18
H19
Y10
W10
Y5
GND
PF7
PJ5
AWE
GND
PF8
PJ6
BG
GND
K10
K11
K12
K13
L9
PF9
PJ7
BGH
GND
PG0
H2
G1
C2
PJ8
BMODE0
BMODE1
BMODE2
BR
GND
PG1
PJ9
GND
PG10
PG11
PG12
PG13
PG14
PG15
PG2
RESET
RTXO
RTXI
SA10
SCAS
SCKE
SMS
SRAS
SWE
TCK
GND
B1
GND
L10
L11
L12
L13
M9
M10
M11
M12
A2
A3
B3
CLKBUF
CLKIN
GND
GND
CLKOUT
DATA0
DATA1
DATA10
DATA11
GND
A4
G2
F1
GND
GND
PG3
GND
PG4
F2
W5
GND
PG5
E1
Rev. PrE
|
Page 55 of 60 | July 2005
ADSP-BF534
Preliminary Technical Data
Table 45 lists the sparse mini-BGA pinout by ball number.
Table 44 on Page 55 lists the sparse mini-BGA pinout by signal
mnemonic.
Table 45. 208-Ball Sparse Mini-BGA Ball Assignment (Numerically by Ball Number)
Ball no.
A1
Mnemonic Ball no.
Mnemonic Ball no.
Mnemonic Ball no.
Mnemonic Ball no.
Mnemonic
TCK
GND
PG12
PG13
PG15
PH1
C19
C20
D1
PJ11
J9
GND
M19
M20
N1
AMS1
AMS0
PF5
W1
W2
W3
W4
W5
W6
W7
W8
W9
W10
W11
W12
W13
W14
W15
W16
W17
W18
W19
W20
Y1
A2
NMI
J10
J11
J12
J13
J14
J19
J20
K1
GND
GND
A3
PG7
GND
DATA15
DATA13
DATA11
DATA9
DATA7
DATA5
DATA3
DATA1
BMODE2
BMODE1
BMODE0
ADDR18
ADDR16
ADDR14
ADDR12
ADDR10
GND
A4
D2
PG8
GND
N2
PF6
A5
D19
D20
E1
PJ2
GND
N7
VDDEXT
VDDEXT
GND
A6
PH3
RESET
PG5
VDDINT
ARDY
SMS
N8
A7
PH5
N9
A8
PH7
E2
PG6
N10
N11
N12
N13
N14
N19
N20
P1
GND
A9
PH9
E19
E20
F1
PJ3
PF11
GND
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
B1
PH11
PH13
PH15
GND
RTXI
RTXO
VDDRTC
XTAL
CLKIN
PJ5
VROUT0
PG3
K2
PF12
GND
K7
VDDEXT
VDDEXT
GND
GND
F2
PG4
K8
VDDINT
ARE
F19
F20
G1
BR
K9
VROUT1
PG1
K10
K11
K12
K13
K14
K19
K20
L1
GND
AOE
GND
PF3
G2
PG2
GND
P2
PF4
G7
VDDEXT
VDDEXT
VDDEXT
VDDEXT
GND
GND
P7
VDDEXT
VDDEXT
VDDEXT
VDDEXT
GND
G8
VDDINT
SRAS
SCAS
PF9
P8
G9
P9
GND
PG11
GND
PG14
PH0
G10
G11
G12
G13
G14
G19
G20
H1
P10
P11
P12
P13
P14
P19
P20
R1
ADDR8
GND
B2
VDDINT
VDDINT
VDDINT
AMS3
AMS2
PF15
L2
PF10
VDDINT
VDDINT
VDDINT
ABE0
Y2
TDO
B3
L7
VDDEXT
VDDEXT
GND
Y3
DATA14
DATA12
DATA10
DATA8
DATA6
DATA4
DATA2
DATA0
BG
B4
L8
Y4
B5
PH2
L9
Y5
B6
PH4
L10
L11
L12
L13
L14
L19
L20
M1
M2
M7
M8
M9
M10
M11
M12
M13
M14
GND
ABE1
Y6
B7
PH6
GND
PF1
Y7
B8
PH8
H2
PG0
GND
R2
PF2
Y8
B9
PH10
PH12
PH14
PJ0
H7
VDDEXT
VDDEXT
GND
GND
R19
R20
T1
ADDR1
AWE
Y9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
C1
H8
VDDINT
SWE
Y10
Y11
Y12
Y13
Y14
Y15
Y16
Y17
Y18
Y19
Y20
H9
EMU
H10
H11
H12
H13
H14
H19
H20
J1
GND
SA10
PF7
T2
PF0
BGH
PJ1
GND
T19
T20
U1
ADDR3
ADDR2
TRST
GND
CLKBUF
PJ6
GND
PF8
ADDR19
ADDR17
ADDR15
ADDR13
ADDR11
ADDR9
GND
GND
VDDEXT
VDDEXT
GND
PJ7
VDDINT
CLKOUT
SCKE
U2
TMS
PJ8
U19
U20
V1
ADDR5
ADDR4
TDI
PJ4
GND
PJ10
PJ9
PF13
GND
J2
PF14
GND
V2
GND
PG9
J7
VDDEXT
VDDEXT
GND
V19
V20
ADDR7
ADDR6
C2
PG10
J8
VDDINT
Rev. PrE
|
Page 56 of 60
|
July 2005
Preliminary Technical Data
ADSP-BF534
Figure 44 shows the top view of the sparse mini-BGA ball con-
figuration. Figure 45 shows the bottom view of the sparse mini-
BGA ball configuration.
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
KEY:
V
V
GND
I/O
NC
DDINT
DDRTC
V
ROUT
V
DDEXT
Figure 44. 208-Ball Mini-BGA Ball Configuration (Top View)
20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
KEY:
VDDINT
VDDEXT
VDDRTC
VROUT
GND
I/O
NC
Figure 45. 208-Ball Mini-BGA Ball Configuration (Bottom View)
Rev. PrE
|
Page 57 of 60 | July 2005
ADSP-BF534
Preliminary Technical Data
OUTLINE DIMENSIONS
Dimensions in Figure 46—182-Ball Mini-BGA and Figure 47—
208-Ball Sparse Mini-BGA are shown in millimeters.
A1 CORNER
INDEX AREA
12.00 BSC SQ
13
14 12 10
9
7
5
3
1
11
8
6
4
2
A
B
C
D
E
F
PIN A1
INDICATOR
10.40
BSC
SQ
LOCATION
G
H
J
K
L
0.80
BSC
TYP
M
N
P
TOP VIEW
BOTTOM VIEW
1.70
1.56
1.35
DETAIL A
1.31
1.21
1.10
0.35 NOM
0.25 MIN
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
0.50
2. COMPLIANT TO JEDEC STANDARD MO-205-AE,
EXCEPT FOR BALL DIAMETER.
3. CENTER DIMENSIONS ARE NOMINAL.
4. THE ACTUAL POSITION OF THE BALL GRID IS
WITHIN 0.15 OF ITS IDEAL POSITION RELATIVE
TO THE PACKAGE EDGES.
0.12
COPLANARITY
SEATING
PLANE
0.45
0.40
(BALL
DIAMETER)
DETAIL A
5. RECOMMENDED SOLDER MASK OPENING IS 0.40mm,
RECOMMENDED BALL PAD SIZE IS 0.55mm.
Figure 46. 182-Ball Mini-BGA
A1 CORNER
INDEX AREA
17.00 BSC SQ
20 18 16 14 12 10
19 17 15 13 11
8
6
4
2
3 1
9
7
5
A
B
C
D
E
F
PIN A1
INDICATOR
15.20
BSC
SQ
G
LOCATION
H
J
K
L
M
N
P
R
T
0.80
BSC
TYP
U
V
W
Y
BOTTOM VIEW
TOP VIEW
1.70
1.61
1.46
1.36
1.26
1.16
DETAILA
0.35 NOM
0.30 MIN
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
0.50
0.45
2. COMPLIANT TO JEDEC STANDARD MO-205-AM,
EXCEPT FOR BALL DIAMETER.
0.12
COPLANARITY
SEATING
PLANE
0.40
3. CENTER DIMENSIONS ARE NOMINAL.
4. THE ACTUAL POSITION OF THE BALL GRID IS
WITHIN 0.15 OF ITS IDEAL POSITION RELATIVE
TO THE PACKAGE EDGES.
(BALL
DIAMETER)
DETAIL A
5. RECOMMENDED SOLDER MASK OPENING IS 0.40mm,
RECOMMENDED BALL PAD SIZE IS 0.55mm.
Figure 47. 208-Ball Sparse Mini-BGA
Rev. PrE
|
Page 58 of 60
|
July 2005
Preliminary Technical Data
ADSP-BF534
ORDERING GUIDE
Part numbers that include “A1” are 182-Ball mini-BGA. Part
numbers that include “B1” are 208-Ball Sparse mini-BGA. Part
numbers that include “Z” are lead free. See Figure 8 on Page 22
for more information about product information on the
package.
Part Number
Temperature Range (Ambient)
–40ºC to 85ºC
Speed Grade (Max)
400 MHz
Operating Voltage (Nominal)
ADSP-BF534BBC-4A1
ADSP-BF534BBCZ-4A1
ADSP-BF534BBCZ-4B1
ADSP-BF534BBC-5A1
ADSP-BF534BBCZ-5A1
ADSP-BF534BBCZ-5B1
1.2 V internal, 2.5 V or 3.3 V I/O
1.2 V internal, 2.5 V or 3.3 V I/O
1.2 V internal, 2.5 V or 3.3 V I/O
1.26 V internal, 2.5 V or 3.3 V I/O
1.26 V internal, 2.5 V or 3.3 V I/O
1.26 V internal, 2.5 V or 3.3 V I/O
–40ºC to 85ºC
400 MHz
–40ºC to 85ºC
400 MHz
–40ºC to 85ºC
500 MHz
–40ºC to 85ºC
500 MHz
–40ºC to 85ºC
500 MHz
The ADSP-BF534 processor is also available with a –40ºC to
105ºC ambient extended industrial temperature range in the
208-Ball Sparse MBGA package only. Please contact your local
authorized ADI sales representative for ordering information.
Rev. PrE
|
Page 59 of 60 | July 2005
ADSP-BF534
Preliminary Technical Data
©
2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
PR05317-0-7/05(PrE)
Rev. PrE
|
Page 60 of 60
|
July 2005
相关型号：
ADSP-BF534BBCZ-4B1
IC 16-BIT, 50 MHz, OTHER DSP, PBGA208, LEAD FREE, MO-205AM, MBGA-208, Digital Signal Processor
ADI
ADSP-BF534BBCZ-5A1
IC 16-BIT, 50 MHz, OTHER DSP, PBGA182, LEAD FREE, MO-205AE, MBGA-182, Digital Signal Processor
ADI
ADSP-BF534BBCZ-5B1
IC 16-BIT, 50 MHz, OTHER DSP, PBGA208, LEAD FREE, MO-205AM, MBGA-208, Digital Signal Processor
ADI
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