ADSP-BF536BBCZ3BRL [ADI]
Blackfin Processor with Embedded Network Connectivity;型号: | ADSP-BF536BBCZ3BRL |
厂家: | ADI |
描述: | Blackfin Processor with Embedded Network Connectivity 时钟 外围集成电路 |
文件: | 总68页 (文件大小:2212K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Blackfin
Embedded Processor
ADSP-BF534/ADSP-BF536/ADSP-BF537
FEATURES
PERIPHERALS
Up to 600 MHz high performance Blackfin processor
Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs,
40-bit shifter
RISC-like register and instruction model for ease of
programming and compiler-friendly support
Advanced debug, trace, and performance monitoring
Wide range of operating voltages (see Operating Conditions
on Page 23)
Qualified for Automotive Applications (see Automotive Prod-
ucts on Page 66)
Programmable on-chip voltage regulator
182-ball and 208-ball CSP_BGA packages
IEEE 802.3-compliant 10/100 Ethernet MAC (ADSP-BF536 and
ADSP-BF537 only)
Controller area network (CAN) 2.0B interface
Parallel peripheral interface (PPI), supporting ITU-R 656
video data formats
2 dual-channel, full-duplex synchronous serial ports
(SPORTs), supporting 8 stereo I2S channels
12 peripheral DMAs, 2 mastered by the Ethernet MAC
2 memory-to-memory DMAs with external request lines
Event handler with 32 interrupt inputs
Serial peripheral interface (SPI) compatible
2 UARTs with IrDA support
2-wire interface (TWI) controller
MEMORY
Eight 32-bit timer/counters with PWM support
Real-time clock (RTC) and watchdog timer
32-bit core timer
48 general-purpose I/Os (GPIOs), 8 with high current drivers
On-chip PLL capable of frequency multiplication
Debug/JTAG interface
Up to 132K bytes of on-chip memory
Instruction SRAM/cache and instruction SRAM
Data SRAM/cache plus additional dedicated data SRAM
Scratchpad SRAM (see Table 1 on Page 3 for available
memory configurations)
External memory controller with glueless support for SDRAM
and asynchronous 8-bit and 16-bit memories
Flexible booting options from external flash, SPI and TWI
memory or from SPI, TWI, and UART host devices
Memory management unit providing memory protection
VOLTAGE REGULATOR
JTAG TEST AND EMULATION
PERIPHERAL ACCESS BUS
WATCHDOG TIMER
RTC
INTERRUPT
CONTROLLER
CAN
B
TWI
PORT J
SPORT0
SPORT1
PPI
L1
L1
DATA
DMA
CONTROLLER
INSTRUCTION
MEMORY
GPIO
PORT G
MEMORY
UART0-1
SPI
DMA CORE BUS
EXTERNAL ACCESS BUS
GPIO
PORT F
EXTERNAL PORT
FLASH, SDRAM CONTROL
TIMER7-0
ETHERNET MAC
(See Table 1)
GPIO
PORT H
16
BOOT ROM
Figure 1. Functional Block Diagram
Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc.
Rev. J Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.
Tel: 781.329.4700
Technical Support
©2014 Analog Devices, Inc. All rights reserved.
www.analog.com
ADSP-BF534/ADSP-BF536/ADSP-BF537
TABLE OF CONTENTS
Features ................................................................. 1
Memory ................................................................ 1
Peripherals ............................................................. 1
General Description ................................................. 3
Portable Low Power Architecture ............................. 3
Booting Modes ................................................... 16
Instruction Set Description .................................... 17
Development Tools .............................................. 17
Additional Information ........................................ 18
Related Signal Chains ........................................... 18
System Integration ................................................ 3
Blackfin Processor Peripherals ................................. 3
Blackfin Processor Core .......................................... 4
Memory Architecture ............................................ 5
DMA Controllers .................................................. 8
Real-Time Clock ................................................... 9
Watchdog Timer .................................................. 9
Timers ............................................................... 9
Serial Ports (SPORTs) .......................................... 10
Serial Peripheral Interface (SPI) Port ....................... 10
UART Ports ...................................................... 10
Controller Area Network (CAN) ............................ 11
TWI Controller Interface ...................................... 11
10/100 Ethernet MAC .......................................... 11
Ports ................................................................ 12
Parallel Peripheral Interface (PPI) ........................... 12
Dynamic Power Management ................................ 13
Voltage Regulation .............................................. 14
Clock Signals ..................................................... 15
Pin Descriptions .................................................... 19
Specifications ........................................................ 23
Operating Conditions ........................................... 23
Electrical Characteristics ....................................... 25
Absolute Maximum Ratings ................................... 29
ESD Sensitivity ................................................... 29
Package Information ............................................ 29
Timing Specifications ........................................... 30
Output Drive Currents ......................................... 50
Test Conditions .................................................. 52
Thermal Characteristics ........................................ 56
182-Ball CSP_BGA Ball Assignment ........................... 57
208-Ball CSP_BGA Ball Assignment ........................... 60
Outline Dimensions ................................................ 63
Surface-Mount Design .......................................... 65
Automotive Products .............................................. 66
Ordering Guide ..................................................... 67
REVISION HISTORY
2/14—Rev. I to Rev. J
Corrected typographical error from Three 16-bit MACs to Two
16-bit MACs in Features ............................................ 1
Updated Development Tools .................................... 17
Added tHDRE parameter to Serial Port Timing ................ 38
Added footnotes in Serial Port Timing ........................ 38
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ADSP-BF534/ADSP-BF536/ADSP-BF537
GENERAL DESCRIPTION
The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors are
members of the Blackfin® family of products, incorporating the
Analog Devices, Inc./Intel Micro Signal Architecture (MSA).
Blackfin processors combine a dual-MAC, state-of-the-art sig-
nal processing engine, the advantages of a clean, orthogonal
RISC-like microprocessor instruction set, and single-instruc-
tion, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.
PORTABLE LOW POWER ARCHITECTURE
Blackfin processors provide world-class power management
and performance. They are produced with a low power and low
voltage design methodology and feature on-chip dynamic
power management, which is the ability to vary both the voltage
and frequency of operation to significantly lower overall power
consumption. This capability can result in a substantial reduc-
tion in power consumption, compared with just varying the
frequency of operation. This allows longer battery life for
portable appliances.
The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors are
completely code and pin compatible. They differ only with
respect to their performance, on-chip memory, and presence of
the Ethernet MAC module. Specific performance, memory, and
feature configurations are shown in Table 1.
SYSTEM INTEGRATION
The Blackfin processor is a highly integrated system-on-a-chip
solution for the next generation of embedded network-con-
nected applications. By combining industry-standard interfaces
with a high performance signal processing core, cost-effective
applications can be developed quickly, without the need for
costly external components. The system peripherals include an
IEEE-compliant 802.3 10/100 Ethernet MAC (ADSP-BF536 and
ADSP-BF537 only), a CAN 2.0B controller, a TWI controller,
two UART ports, an SPI port, two serial ports (SPORTs), nine
general-purpose 32-bit timers (eight with PWM capability), a
real-time clock, a watchdog timer, and a parallel peripheral
interface (PPI).
Table 1. Processor Comparison
Features
Ethernet MAC
—
1
1
1
1
2
2
1
8
1
1
1
48
1
1
1
2
2
1
8
1
1
1
48
CAN
TWI
1
SPORTs
2
BLACKFIN PROCESSOR PERIPHERALS
UARTs
2
The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors con-
tain a rich set of peripherals connected to the core via several
high bandwidth buses, providing flexibility in system configura-
tion as well as excellent overall system performance (see
Figure 1). The processors contain dedicated network communi-
cation modules and high speed serial and parallel ports, an
interrupt controller for flexible management of interrupts from
the on-chip peripherals or external sources, and power manage-
ment control functions to tailor the performance and power
characteristics of the processor and system to many application
scenarios.
SPI
1
GP Timers
8
Watchdog Timers
1
RTC
1
Parallel Peripheral Interface
GPIOs
1
48
L1 Instruction 16K bytes 16K bytes 16K bytes
SRAM/Cache
L1 Instruction 48K bytes 48K bytes 48K bytes
SRAM
Memory
Configuration
All of the peripherals, except for the general-purpose I/O, CAN,
TWI, real-time clock, and timers, are supported by a flexible
DMA structure. There are also separate memory DMA channels
dedicated to data transfers between the processor’s various
memory spaces, including external SDRAM and asynchronous
memory. Multiple on-chip buses running at up to 133 MHz
provide enough bandwidth to keep the processor core running
along with activity on all of the on-chip and external
peripherals.
L1 Data
32K bytes 32K bytes 32K bytes
SRAM/Cache
L1 Data SRAM 32K bytes
L1 Scratchpad 4K bytes
L3 Boot ROM 2K bytes
—
32K bytes
4K bytes 4K bytes
2K bytes 2K bytes
400 MHz 600 MHz
Maximum Speed Grade
500 MHz
Package Options:
CSP_BGA
CSP_BGA
208-Ball
182-Ball
208-Ball 208-Ball
182-Ball 182-Ball
The Blackfin processors include an on-chip voltage regulator in
support of the processors’ dynamic power management capabil-
ity. The voltage regulator provides a range of core voltage levels
when supplied from VDDEXT. The voltage regulator can be
bypassed at the user’s discretion.
By integrating a rich set of industry-leading system peripherals
and memory, the Blackfin processors are the platform of choice
for next-generation applications that require RISC-like pro-
grammability, multimedia support, and leading-edge signal
processing in one integrated package.
Rev. J
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ADSP-BF534/ADSP-BF536/ADSP-BF537
instructions include byte alignment and packing operations,
BLACKFIN PROCESSOR CORE
16-bit and 8-bit adds with clipping, 8-bit average operations,
and 8-bit subtract/absolute value/accumulate (SAA) operations.
Also provided are the compare/select and vector search
instructions.
As shown in Figure 2, the Blackfin processor core contains two
16-bit multipliers, two 40-bit accumulators, two 40-bit ALUs,
four video ALUs, and a 40-bit shifter. The computation units
process 8-, 16-, or 32-bit data from the register file.
For certain instructions, two 16-bit ALU operations can be per-
formed simultaneously on register pairs (a 16-bit high half and
16-bit low half of a compute register). If the second ALU is used,
quad 16-bit operations are possible.
The compute register file contains eight 32-bit registers. When
performing compute operations on 16-bit operand data, the
register file operates as 16 independent 16-bit registers. All
operands for compute operations come from the multiported
register file and instruction constant fields.
The 40-bit shifter can perform shifts and rotates, and is used to
support normalization, field extract, and field deposit
instructions.
Each MAC can perform a 16-bit by 16-bit multiply in each
cycle, accumulating the results into the 40-bit accumulators.
Signed and unsigned formats, rounding, and saturation
are supported.
The program sequencer controls the flow of instruction execu-
tion, including instruction alignment and decoding. For
program flow control, the sequencer supports PC relative and
indirect conditional jumps (with static branch prediction), and
subroutine calls. Hardware is provided to support zero-over-
head looping. The architecture is fully interlocked, meaning that
the programmer need not manage the pipeline when executing
instructions with data dependencies.
The ALUs perform a traditional set of arithmetic and logical
operations on 16-bit or 32-bit data. In addition, many special
instructions are included to accelerate various signal processing
tasks. These include bit operations such as field extract and pop-
ulation count, modulo 232 multiply, divide primitives, saturation
and rounding, and sign/exponent detection. The set of video
ADDRESS ARITHMETIC UNIT
SP
FP
P5
P4
I3
I2
I1
I0
L3
L2
L1
L0
B3
B2
B1
B0
M3
M2
M1
M0
DAG1
P3
DAG0
P2
P1
P0
DA1 32
DA0 32
32
PREG
32
RAB
SD 32
LD1 32
LD0 32
ASTAT
32
32
SEQUENCER
R7.H
R6.H
R5.H
R4.H
R3.H
R2.H
R1.H
R0.H
R7.L
R6.L
R5.L
R4.L
R3.L
R2.L
R1.L
R0.L
ALIGN
16
16
8
8
8
8
DECODE
BARREL
SHIFTER
LOOP BUFFER
40
40
40 40
A0
A1
CONTROL
UNIT
32
32
DATAARITHMETIC UNIT
Figure 2. Blackfin Processor Core
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ADSP-BF534/ADSP-BF536/ADSP-BF537
The address arithmetic unit provides two addresses for simulta-
The memory DMA controller provides high bandwidth data-
movement capability. It can perform block transfers of code or
data between the internal memory and the external
memory spaces.
neous dual fetches from memory. It contains a multiported
register file consisting of four sets of 32-bit index, modify,
length, and base registers (for circular buffering), and eight
additional 32-bit pointer registers (for C-style indexed stack
manipulation).
Internal (On-Chip) Memory
The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors have
three blocks of on-chip memory providing high-bandwidth
access to the core.
Blackfin processors support a modified Harvard architecture in
combination with a hierarchical memory structure. Level 1 (L1)
memories are those that typically operate at the full processor
speed with little or no latency. At the L1 level, the instruction
memory holds instructions only. The two data memories hold
data, and a dedicated scratchpad data memory stores stack and
local variable information.
The first block is the L1 instruction memory, consisting of
64K bytes SRAM, of which 16K bytes can be configured as a
four-way set-associative cache. This memory is accessed at full
processor speed.
In addition, multiple L1 memory blocks are provided, offering a
configurable mix of SRAM and cache. The memory manage-
ment unit (MMU) provides memory protection for individual
tasks that may be operating on the core and can protect system
registers from unintended access.
The second on-chip memory block is the L1 data memory, con-
sisting of up to two banks of up to 32K bytes each. Each memory
bank is configurable, offering both cache and SRAM functional-
ity. This memory block is accessed at full processor speed.
The third memory block is a 4K byte scratchpad SRAM, which
runs at the same speed as the L1 memories, but is only accessible
as data SRAM, and cannot be configured as cache memory.
The architecture provides three modes of operation: user mode,
supervisor mode, and emulation mode. User mode has
restricted access to certain system resources, thus providing a
protected software environment, while supervisor mode has
unrestricted access to the system and core resources.
External (Off-Chip) Memory
External memory is accessed via the EBIU. This 16-bit interface
provides a glueless connection to a bank of synchronous DRAM
(SDRAM) as well as up to four banks of asynchronous memory
devices including flash, EPROM, ROM, SRAM, and memory
mapped I/O devices.
The Blackfin processor instruction set has been optimized so
that 16-bit opcodes represent the most frequently used instruc-
tions, resulting in excellent compiled code density. Complex
DSP instructions are encoded into 32-bit opcodes, representing
fully featured multifunction instructions. Blackfin processors
support a limited multi-issue capability, where a 32-bit instruc-
tion can be issued in parallel with two 16-bit instructions,
allowing the programmer to use many of the core resources in a
single instruction cycle.
The PC133-compliant SDRAM controller can be programmed
to interface to up to 128M bytes of SDRAM. A separate row can
be open for each SDRAM internal bank, and the SDRAM con-
troller supports up to 4 internal SDRAM banks, improving
overall performance.
The Blackfin processor assembly language uses an algebraic syn-
tax for ease of coding and readability. The architecture has been
optimized for use in conjunction with the C/C++ compiler,
resulting in fast and efficient software implementations.
The asynchronous memory controller can be programmed to
control up to four banks of devices with very flexible timing
parameters for a wide variety of devices. Each bank occupies a
1M byte segment regardless of the size of the devices used, so
that these banks are only contiguous if each is fully populated
with 1M byte of memory.
MEMORY ARCHITECTURE
The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors view
memory as a single unified 4G byte address space, using 32-bit
addresses. All resources, including internal memory, external
memory, and I/O control registers, occupy separate sections of
this common address space. The memory portions of this
address space are arranged in a hierarchical structure to provide
a good cost/performance balance of some very fast, low latency
on-chip memory as cache or SRAM, and larger, lower cost, and
performance off-chip memory systems. (See Figure 3).
I/O Memory Space
The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors do
not define a separate I/O space. All resources are mapped
through the flat 32-bit address space. On-chip I/O devices have
their control registers mapped into memory-mapped registers
(MMRs) at addresses near the top of the 4G byte address space.
These are separated into two smaller blocks, one which contains
the control MMRs for all core functions, and the other which
contains the registers needed for setup and control of the on-
chip peripherals outside of the core. The MMRs are accessible
only in supervisor mode and appear as reserved space to on-
chip peripherals.
The on-chip L1 memory system is the highest performance
memory available to the Blackfin processor. The off-chip mem-
ory system, accessed through the external bus interface unit
(EBIU), provides expansion with SDRAM, flash memory, and
SRAM, optionally accessing up to 516M bytes of
physical memory.
Booting
The Blackfin processor contains a small on-chip boot kernel,
which configures the appropriate peripheral for booting. If the
Blackfin processor is configured to boot from boot ROM
Rev. J
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ADSP-BF534/ADSP-BF536/ADSP-BF537
ADSP-BF534/ADSP-BF537 MEMORY MAP
ADSP-BF536 MEMORY MAP
0xFFFF FFFF
0xFFFF FFFF
0xFFE0 0000
CORE MMR REGISTERS (2M BYTES)
SYSTEM MMR REGISTERS (2M BYTES)
RESERVED
CORE MMR REGISTERS (2M BYTES)
SYSTEM MMR REGISTERS (2M BYTES)
RESERVED
0xFFE0 0000
0xFFC0 0000
0xFFB0 1000
0xFFB0 0000
0xFFA1 4000
0xFFA1 0000
0xFFA0 C000
0xFFA0 8000
0xFFC0 0000
0xFFB0 1000
SCRATCHPAD SRAM (4K BYTES)
RESERVED
SCRATCHPAD SRAM (4K BYTES)
RESERVED
0xFFB0 0000
0xFFA1 4000
INSTRUCTION SRAM/CACHE (16K BYTES)
RESERVED
INSTRUCTION SRAM/CACHE (16K BYTES)
RESERVED
0xFFA1 0000
0xFFA0 C000
INSTRUCTION BANK B SRAM (16K BYTES)
INSTRUCTION BANK A SRAM (32K BYTES)
RESERVED
INSTRUCTION BANK B SRAM (16K BYTES)
INSTRUCTION BANK A SRAM (32K BYTES)
RESERVED
0xFFA0 8000
0xFFA0 0000
0xFF90 8000
0xFF90 4000
0xFF90 0000
0xFF80 8000
0xFF80 4000
0xFF80 0000
0xEF00 0800
0xEF00 0000
0x2040 0000
0x2030 0000
0x2020 0000
0x2010 0000
0x2000 0000
0x0000 0000
0xFFA0 0000
0xFF90 8000
DATA BANK B SRAM/CACHE (16K BYTES)
RESERVED
DATA BANK B SRAM/CACHE (16K BYTES)
DATA BANK B SRAM (16K BYTES)
RESERVED
0xFF90 4000
0xFF90 0000
0xFF80 8000
0xFF80 4000
RESERVED
DATA BANK A SRAM/CACHE (16K BYTES)
DATA BANK A SRAM/CACHE (16K BYTES)
DATA BANK A SRAM (16K BYTES)
RESERVED
RESERVED
0xFF80 0000
0xEF00 0800
0xEF00 0000
RESERVED
BOOT ROM (2K BYTES)
BOOT ROM (2K BYTES)
RESERVED
RESERVED
0x2040 0000
0x2030 0000
ASYNC MEMORY BANK 3 (1M BYTES)
ASYNC MEMORY BANK 2 (1M BYTES)
ASYNC MEMORY BANK 1 (1M BYTES)
ASYNC MEMORY BANK 0 (1M BYTES)
ASYNC MEMORY BANK 3 (1M BYTES)
ASYNC MEMORY BANK 2 (1M BYTES)
ASYNC MEMORY BANK 1 (1M BYTES)
ASYNC MEMORY BANK 0 (1M BYTES)
SDRAM MEMORY (16M BYTES TO 512M BYTES)
0x2020 0000
0x2010 0000
0x2000 0000
0x0000 0000
SDRAM MEMORY (16M BYTES TO 512M BYTES)
Figure 3. ADSP-BF534/ADSP-BF536/ADSP-BF537 Memory Maps
memory space, the processor starts executing from the on-chip
boot ROM. For more information, see Booting Modes on
Page 16.
• Exceptions – Events that occur synchronously to program
flow (in other words, the exception is taken before the
instruction is allowed to complete). Conditions such as
data alignment violations and undefined instructions cause
exceptions.
Event Handling
The event controller on the Blackfin processor handles all asyn-
chronous and synchronous events to the processor. The
Blackfin processor provides event handling that supports both
nesting and prioritization. Nesting allows multiple event service
routines to be active simultaneously. Prioritization ensures that
servicing of a higher priority event takes precedence over servic-
ing of a lower priority event. The controller provides support for
five different types of events:
• Interrupts – Events that occur asynchronously to program
flow. They are caused by input pins, timers, and other
peripherals, as well as by an explicit software instruction.
Each event type has an associated register to hold the return
address and an associated return-from-event instruction. When
an event is triggered, the state of the processor is saved on the
supervisor stack.
The Blackfin processor event controller consists of two stages:
the core event controller (CEC) and the system interrupt con-
troller (SIC). The core event controller works with the system
interrupt controller to prioritize and control all system events.
Conceptually, interrupts from the peripherals enter into the
SIC, and are then routed directly into the general-purpose inter-
rupts of the CEC.
• Emulation – An emulation event causes the processor to
enter emulation mode, allowing command and control of
the processor via the JTAG interface.
• Reset – This event resets the processor.
• Nonmaskable Interrupt (NMI) – The NMI event can be
generated by the software watchdog timer or by the NMI
input signal to the processor. The NMI event is frequently
used as a power-down indicator to initiate an orderly shut-
down of the system.
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ADSP-BF534/ADSP-BF536/ADSP-BF537
Table 3. System Interrupt Controller (SIC)
Core Event Controller (CEC)
The CEC supports nine general-purpose interrupts (IVG15–7),
in addition to the dedicated interrupt and exception events. Of
these general-purpose interrupts, the two lowest priority
interrupts (IVG15–14) are recommended to be reserved for
software interrupt handlers, leaving seven prioritized interrupt
inputs to support the peripherals of the Blackfin processor.
Table 2 describes the inputs to the CEC, identifies their names
in the event vector table (EVT), and lists their priorities.
Default
Mapping
Peripheral
Interrupt ID
Peripheral Interrupt Event
PLL Wakeup
IVG7
IVG7
IVG7
IVG7
IVG7
IVG7
IVG7
IVG7
0
1
1
1
1
1
2
2
DMA Error (Generic)
DMAR0 Block Interrupt
DMAR1 Block Interrupt
DMAR0 Overflow Error
DMAR1 Overflow Error
CAN Error
Table 2. Core Event Controller (CEC)
Priority
Ethernet Error (ADSP-BF536 and
ADSP-BF537 only)
(0 Is Highest) Event Class
EVT Entry
EMU
0
Emulation/Test Control
SPORT 0 Error
IVG7
2
1
Reset
RST
SPORT 1 Error
IVG7
2
2
Nonmaskable Interrupt
Exception
NMI
PPI Error
IVG7
2
3
EVX
SPI Error
IVG7
2
4
Reserved
—
UART0 Error
IVG7
2
5
Hardware Error
IVHW
IVTMR
IVG7
UART1 Error
IVG7
2
6
Core Timer
Real-Time Clock
IVG8
3
7
General-Purpose Interrupt 7
General-Purpose Interrupt 8
General-Purpose Interrupt 9
General-Purpose Interrupt 10
General-Purpose Interrupt 11
General-Purpose Interrupt 12
General-Purpose Interrupt 13
General-Purpose Interrupt 14
General-Purpose Interrupt 15
DMA Channel 0 (PPI)
DMA Channel 3 (SPORT 0 Rx)
DMA Channel 4 (SPORT 0 Tx)
DMA Channel 5 (SPORT 1 Rx)
DMA Channel 6 (SPORT 1 Tx)
TWI
IVG8
4
8
IVG8
IVG9
5
9
IVG9
IVG9
6
10
11
12
13
14
15
IVG10
IVG11
IVG12
IVG13
IVG14
IVG15
IVG9
7
IVG9
8
IVG10
IVG10
IVG10
IVG10
IVG10
IVG10
IVG11
IVG11
IVG11
9
DMA Channel 7 (SPI)
DMA Channel 8 (UART0 Rx)
DMA Channel 9 (UART0 Tx)
DMA Channel 10 (UART1 Rx)
DMA Channel 11 (UART1 Tx)
CAN Rx
10
11
12
13
14
15
16
17
System Interrupt Controller (SIC)
The system interrupt controller provides the mapping and rout-
ing of events from the many peripheral interrupt sources to the
prioritized general-purpose interrupt inputs of the CEC.
Although the processor provides a default mapping, the user
can alter the mappings and priorities of interrupt events by writ-
ing the appropriate values into the interrupt assignment
registers (IAR). Table 3 describes the inputs into the SIC and the
default mappings into the CEC.
CAN Tx
DMA Channel 1 (Ethernet Rx,
ADSP-BF536 and ADSP-BF537 only)
Port H Interrupt A
IVG11
IVG11
17
18
DMA Channel 2 (Ethernet Tx,
ADSP-BF536 and ADSP-BF537 only)
Port H Interrupt B
Timer 0
IVG11
IVG12
IVG12
IVG12
IVG12
IVG12
IVG12
IVG12
IVG12
IVG12
IVG12
18
19
20
21
22
23
24
25
26
27
28
Timer 1
Timer 2
Timer 3
Timer 4
Timer 5
Timer 6
Timer 7
Port F, G Interrupt A
Port G Interrupt B
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ADSP-BF534/ADSP-BF536/ADSP-BF537
Table 3. System Interrupt Controller (SIC) (Continued)
• SIC interrupt wake-up enable register (SIC_IWR) – By
enabling the corresponding bit in this register, a peripheral
can be configured to wake up the processor, should the
core be idled when the event is generated. (For more infor-
mation, see Dynamic Power Management on Page 13.)
Default
Mapping
Peripheral
Interrupt ID
Peripheral Interrupt Event
DMA Channels 12 and 13
(Memory DMA Stream 0)
IVG13
IVG13
29
30
Because multiple interrupt sources can map to a single general-
purpose interrupt, multiple pulse assertions can occur simulta-
neously, before or during interrupt processing for an interrupt
event already detected on this interrupt input. The IPEND reg-
ister contents are monitored by the SIC as the interrupt
acknowledgement.
DMA Channels 14 and 15
(Memory DMA Stream 1)
Software Watchdog Timer
Port F Interrupt B
IVG13
IVG13
31
31
Event Control
The appropriate ILAT register bit is set when an interrupt rising
edge is detected (detection requires two core clock cycles). The
bit is cleared when the respective IPEND register bit is set. The
IPEND bit indicates that the event has entered into the proces-
sor pipeline. At this point the CEC recognizes and queues the
next rising edge event on the corresponding event input. The
minimum latency from the rising edge transition of the general-
purpose interrupt to the IPEND output asserted is three core
clock cycles; however, the latency can be much higher, depend-
ing on the activity within and the state of the processor.
The Blackfin processor provides a very flexible mechanism to
control the processing of events. In the CEC, three registers are
used to coordinate and control events. Each register is
32 bits wide:
• CEC interrupt latch register (ILAT) – Indicates when
events have been latched. The appropriate bit is set when
the processor has latched the event and cleared when the
event has been accepted into the system. This register is
updated automatically by the controller, but it can be writ-
ten only when its corresponding IMASK bit is cleared.
DMA CONTROLLERS
• CEC interrupt mask register (IMASK) – Controls the
masking and unmasking of individual events. When a bit is
set in the IMASK register, that event is unmasked and is
processed by the CEC when asserted. A cleared bit in the
IMASK register masks the event, preventing the processor
from servicing the event even though the event may be
latched in the ILAT register. This register can be read or
written while in supervisor mode. (Note that general-pur-
pose interrupts can be globally enabled and disabled with
the STI and CLI instructions, respectively.)
The Blackfin processors have multiple, independent DMA
channels that support automated data transfers with minimal
overhead for the processor core. DMA transfers can occur
between the processor’s internal memories and any of its DMA-
capable peripherals. Additionally, DMA transfers can be accom-
plished between any of the DMA-capable peripherals and
external devices connected to the external memory interfaces,
including the SDRAM controller and the asynchronous mem-
ory controller. DMA-capable peripherals include the Ethernet
MAC (ADSP-BF536 and ADSP-BF537 only), SPORTs, SPI port,
UARTs, and PPI. Each individual DMA-capable peripheral has
at least one dedicated DMA channel.
• CEC interrupt pending register (IPEND) – The IPEND
register keeps track of all nested events. A set bit in the
IPEND register indicates the event is currently active or
nested at some level. This register is updated automatically
by the controller but can be read while in supervisor mode.
The DMA controller supports both one-dimensional (1-D) and
two-dimensional (2-D) DMA transfers. DMA transfer initial-
ization can be implemented from registers or from sets of
parameters called descriptor blocks.
The SIC allows further control of event processing by providing
three 32-bit interrupt control and status registers. Each register
contains a bit corresponding to each of the peripheral interrupt
events shown in Table 3 on Page 7.
The 2-D DMA capability supports arbitrary row and column
sizes up to 64K elements by 64K elements, and arbitrary row
and column step sizes up to 32K elements. Furthermore, the
column step size can be less than the row step size, allowing
implementation of interleaved data streams. This feature is
especially useful in video applications where data can be de-
interleaved on the fly.
• SIC interrupt mask register (SIC_IMASK) – Controls the
masking and unmasking of each peripheral interrupt event.
When a bit is set in the register, that peripheral event is
unmasked and is processed by the system when asserted. A
cleared bit in the register masks the peripheral event, pre-
venting the processor from servicing the event.
Examples of DMA types supported by the DMA controller
include
• SIC interrupt status register (SIC_ISR) – As multiple
peripherals can be mapped to a single event, this register
allows the software to determine which peripheral event
source triggered the interrupt. A set bit indicates the
peripheral is asserting the interrupt, and a cleared bit indi-
cates the peripheral is not asserting the event.
• A single, linear buffer that stops upon completion
• A circular, auto-refreshing buffer that interrupts on each
full or fractionally full buffer
• 1-D or 2-D DMA using a linked list of descriptors
• 2-D DMA using an array of descriptors, specifying only the
base DMA address within a common page.
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In addition to the dedicated peripheral DMA channels, there are
two memory DMA channels provided for transfers between the
various memories of the processor system. This enables trans-
fers of blocks of data between any of the memories—including
external SDRAM, ROM, SRAM, and flash memory—with mini-
mal processor intervention. Memory DMA transfers can be
controlled by a very flexible descriptor-based methodology or
by a standard register-based autobuffer mechanism.
RTXI
RTXO
R1
X1
C1
C2
The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors also
have an external DMA controller capability via dual external
DMA request pins when used in conjunction with the external
bus interface unit (EBIU). This functionality can be used when a
high speed interface is required for external FIFOs and high
bandwidth communications peripherals such as USB 2.0. It
allows control of the number of data transfers for memDMA.
The number of transfers per edge is programmable. This feature
can be programmed to allow memDMA to have an increased
priority on the external bus relative to the core.
SUGGESTED COMPONENTS:
X1 = ECLIPTEK EC38J (THROUGH-HOLE PACKAGE) OR
EPSON MC405 12 pF LOAD (SURFACE-MOUNT PACKAGE)
C1 = 22 pF
C2 = 22 pF
R1 = 10 M:
NOTE: C1 AND C2 ARE SPECIFIC TO CRYSTAL SPECIFIED FOR X1.
CONTACT CRYSTAL MANUFACTURER FOR DETAILS. C1 AND C2
SPECIFICATIONS ASSUME BOARD TRACE CAPACITANCE OF 3 pF.
Figure 4. External Components for RTC
REAL-TIME CLOCK
general-purpose interrupt, if the timer expires before being reset
by software. The programmer initializes the count value of the
timer, enables the appropriate interrupt, then enables the timer.
Thereafter, the software must reload the counter before it
counts to zero from the programmed value. This protects the
system from remaining in an unknown state where software,
which would normally reset the timer, has stopped running due
to an external noise condition or software error.
The real-time clock (RTC) provides a robust set of digital watch
features, including current time, stopwatch, and alarm. The
RTC is clocked by a 32.768 kHz crystal external to the
processor. The RTC peripheral has dedicated power supply pins
so that it can remain powered up and clocked even when the
rest of the processor is in a low power state. The RTC provides
several programmable interrupt options, including interrupt
per second, minute, hour, or day clock ticks, interrupt on pro-
grammable stopwatch countdown, or interrupt at a
programmed alarm time.
If configured to generate a hardware reset, the watchdog timer
resets both the core and the processor peripherals. After a reset,
software can determine if the watchdog was the source of the
hardware reset by interrogating a status bit in the watchdog
timer control register.
The 32.768 kHz input clock frequency is divided down to a 1 Hz
signal by a prescaler. The counter function of the timer consists
of four counters: a 60-second counter, a 60-minute counter, a
24-hour counter, and an 32,768-day counter.
The timer is clocked by the system clock (SCLK), at a maximum
frequency of fSCLK
.
When enabled, the alarm function generates an interrupt when
the output of the timer matches the programmed value in the
alarm control register. There are two alarms: The first alarm is
for a time of day, while the second alarm is for a day and time of
that day.
TIMERS
There are nine general-purpose programmable timer units in
the processor. Eight timers have an external pin that can be con-
figured either as a pulse-width modulator (PWM) or timer
output, as an input to clock the timer, or as a mechanism for
measuring pulse widths and periods of external events. These
timers can be synchronized to an external clock input to the sev-
eral other associated PF pins, to an external clock input to the
PPI_CLK input pin, or to the internal SCLK.
The stopwatch function counts down from a programmed
value, with one-second resolution. When the stopwatch is
enabled and the counter underflows, an interrupt is generated.
Like the other peripherals, the RTC can wake up the processor
from sleep mode upon generation of any RTC wake-up event.
Additionally, an RTC wake-up event can wake up the processor
from deep sleep mode, and wake up the on-chip internal voltage
regulator from the hibernate operating mode.
The timer units can be used in conjunction with the two UARTs
and the CAN controller to measure the width of the pulses in
the data stream to provide a software auto-baud detect function
for the respective serial channels.
Connect RTC pins RTXI and RTXO with external components
as shown in Figure 4.
The timers can generate interrupts to the processor core provid-
ing periodic events for synchronization, either to the system
clock or to a count of external signals.
WATCHDOG TIMER
In addition to the eight general-purpose programmable timers,
a ninth timer is also provided. This extra timer is clocked by the
internal processor clock and is typically used as a system tick
clock for generating periodic interrupts in an operating system.
The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors
include a 32-bit timer that can be used to implement a software
watchdog function. A software watchdog can improve system
availability by forcing the processor to a known state through
generation of a system reset, nonmaskable interrupt (NMI), or
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ADSP-BF534/ADSP-BF536/ADSP-BF537
port provides a full-duplex, synchronous serial interface, which
supports both master/slave modes and multimaster
environments.
SERIAL PORTS (SPORTs)
The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors
incorporate two dual-channel synchronous serial ports
(SPORT0 and SPORT1) for serial and multiprocessor commu-
nications. The SPORTs support the following features:
The SPI port’s baud rate and clock phase/polarities are pro-
grammable, and it has an integrated DMA controller,
configurable to support transmit or receive data streams. The
SPI’s DMA controller can only service unidirectional accesses at
any given time.
• I2S capable operation.
• Bidirectional operation – Each SPORT has two sets of inde-
pendent transmit and receive pins, enabling eight channels
of I2S stereo audio.
The SPI port’s clock rate is calculated as:
fSCLK
SPI Clock Rate = -----------------------------------
2 SPI_BAUD
• Buffered (8-deep) transmit and receive ports – Each port
has a data register for transferring data words to and from
other processor components and shift registers for shifting
data in and out of the data registers.
where the 16-bit SPI_BAUD register contains a value of 2
to 65,535.
• Clocking – Each transmit and receive port can either use an
external serial clock or generate its own, in frequencies
ranging from (fSCLK/131,070) Hz to (fSCLK/2) Hz.
During transfers, the SPI port simultaneously transmits and
receives by serially shifting data in and out on its two serial data
lines. The serial clock line synchronizes the shifting and sam-
pling of data on the two serial data lines.
• Word length – Each SPORT supports serial data words
from 3 bits to 32 bits in length, transferred most significant
bit first or least significant bit first.
UART PORTS
• Framing – Each transmit and receive port can run with or
without frame sync signals for each data word. Frame sync
signals can be generated internally or externally, active high
or low, and with either of two pulse widths and early or late
frame sync.
The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors pro-
vide two full-duplex universal asynchronous receiver and
transmitter (UART) ports, which are fully compatible with PC-
standard UARTs. Each UART port provides a simplified UART
interface to other peripherals or hosts, supporting full-duplex,
DMA-supported, asynchronous transfers of serial data. A
UART port includes support for five to eight data bits, one or
two stop bits, and none, even, or odd parity. Each UART port
supports two modes of operation:
• Companding in hardware – Each SPORT can perform
A-law or μ-law companding according to ITU recommen-
dation G.711. Companding can be selected on the transmit
and/or receive channel of the SPORT without additional
latencies.
• PIO (programmed I/O) – The processor sends or receives
data by writing or reading I/O mapped UART registers.
The data is double-buffered on both transmit and receive.
• DMA operations with single-cycle overhead – Each SPORT
can automatically receive and transmit multiple buffers of
memory data. The processor can link or chain sequences of
DMA transfers between a SPORT and memory.
• DMA (direct memory access) – The DMA controller trans-
fers both transmit and receive data. This reduces the
number and frequency of interrupts required to transfer
data to and from memory. The UART has two dedicated
DMA channels, one for transmit and one for receive. These
DMA channels have lower default priority than most DMA
channels because of their relatively low service rates.
• Interrupts – Each transmit and receive port generates an
interrupt upon completing the transfer of a data word or
after transferring an entire data buffer, or buffers,
through DMA.
• Multichannel capability – Each SPORT supports 128 chan-
nels out of a 1024-channel window and is compatible with
the H.100, H.110, MVIP-90, and HMVIP standards.
Each UART port’s baud rate, serial data format, error code gen-
eration and status, and interrupts are programmable:
• Supporting bit rates ranging from (fSCLK/1,048,576) to
(fSCLK/16) bits per second.
SERIAL PERIPHERAL INTERFACE (SPI) PORT
The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors have
an SPI-compatible port that enables the processor to communi-
cate with multiple SPI-compatible devices.
• Supporting data formats from 7 bits to 12 bits per frame.
• Both transmit and receive operations can be configured to
generate maskable interrupts to the processor.
The SPI interface uses three pins for transferring data: two data
pins (Master Output-Slave Input, MOSI, and Master Input-
Slave Output, MISO) and a clock pin (serial clock, SCK). An SPI
chip select input pin (SPISS) lets other SPI devices select the
processor, and seven SPI chip select output pins (SPISEL7–1) let
the processor select other SPI devices. The SPI select pins are
reconfigured programmable flag pins. Using these pins, the SPI
The UART port’s clock rate is calculated as:
fSCLK
UART Clock Rate = --------------------------------------------------
16 UARTx_Divisor
where the 16-bit UARTx_Divisor comes from the UARTx_DLH
register (most significant 8 bits) and UARTx_DLL register (least
significant 8 bits).
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In conjunction with the general-purpose timer functions, auto-
baud detection is supported.
10/100 ETHERNET MAC
The ADSP-BF536 and ADSP-BF537 processors offer the capa-
bility to directly connect to a network by way of an embedded
fast Ethernet Media Access Controller (MAC) that supports
both 10-BaseT (10 Mbps) and 100-BaseT (100 Mbps) operation.
The 10/100 Ethernet MAC peripheral is fully compliant to the
IEEE 802.3-2002 standard, and it provides programmable fea-
tures designed to minimize supervision, bus use, or message
processing by the rest of the processor system.
The capabilities of the UARTs are further extended with sup-
port for the infrared data association (IrDA®) serial infrared
physical layer link specification (SIR) protocol.
CONTROLLER AREA NETWORK (CAN)
The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors offer
a CAN controller that is a communication controller imple-
menting the CAN 2.0B (active) protocol. This protocol is an
asynchronous communications protocol used in both industrial
and automotive control systems. The CAN protocol is well-
suited for control applications due to its capability to communi-
cate reliably over a network, since the protocol incorporates
CRC checking message error tracking, and fault node
confinement.
Some standard features are
• Support of MII and RMII protocols for external PHYs.
• Full duplex and half duplex modes.
• Data framing and encapsulation: generation and detection
of preamble, length padding, and FCS.
• Media access management (in half-duplex operation): col-
lision and contention handling, including control of
retransmission of collision frames and of back-off timing.
The CAN controller offers the following features:
• 32 mailboxes (eight receive only, eight transmit only, 16
configurable for receive or transmit).
• Flow control (in full-duplex operation): generation and
detection of PAUSE frames.
• Dedicated acceptance masks for each mailbox.
• Additional data filtering on first two bytes.
• Station management: generation of MDC/MDIO frames
for read-write access to PHY registers.
• Support for both the standard (11-bit) and extended
(29-bit) identifier (ID) message formats.
• SCLK operating range down to 25 MHz (active and sleep
operating modes).
• Support for remote frames.
• Internal loopback from Tx to Rx.
Some advanced features are
• Active or passive network support.
• CAN wake-up from hibernation mode (lowest static power
consumption mode).
• Buffered crystal output to external PHY for support of a
single crystal system.
• Interrupts, including: Tx complete, Rx complete, error,
global.
• Automatic checksum computation of IP header and IP
payload fields of Rx frames.
The electrical characteristics of each network connection are
very demanding so the CAN interface is typically divided into
two parts: a controller and a transceiver. This allows a single
controller to support different drivers and CAN networks. The
CAN module represents only the controller part of the interface.
The controller interface supports connection to 3.3 V high-
speed, fault-tolerant, single-wire transceivers.
• Independent 32-bit descriptor-driven Rx and Tx DMA
channels.
• Frame status delivery to memory via DMA, including
frame completion semaphores, for efficient buffer queue
management in software.
• Tx DMA support for separate descriptors for MAC header
and payload to eliminate buffer copy operations.
TWI CONTROLLER INTERFACE
The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors
include a 2-wire interface (TWI) module for providing a simple
exchange method of control data between multiple devices. The
TWI is compatible with the widely used I2C® bus standard. The
TWI module offers the capabilities of simultaneous master and
slave operation, support for both 7-bit addressing and multime-
dia data arbitration. The TWI interface utilizes two pins for
transferring clock (SCL) and data (SDA) and supports the
protocol at speeds up to 400 kbps. The TWI interface pins are
compatible with 5 V logic levels.
• Convenient frame alignment modes support even 32-bit
alignment of encapsulated Rx or Tx IP packet data in mem-
ory after the 14-byte MAC header.
• Programmable Ethernet event interrupt supports any com-
bination of
• Any selected Rx or Tx frame status conditions.
• PHY interrupt condition.
• Wake-up frame detected.
• Any selected MAC management counter(s) at
half-full.
Additionally, the processor’s TWI module is fully compatible
with serial camera control bus (SCCB) functionality for easier
control of various CMOS camera sensor devices.
• DMA descriptor error.
• 47 MAC management statistics counters with selectable
clear-on-read behavior and programmable interrupts on
half maximum value.
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• Programmable Rx address filters, including a 64-bit
address hash table for multicast and/or unicast frames, and
programmable filter modes for broadcast, multicast, uni-
cast, control, and damaged frames.
GPIO pins defined as inputs can be configured to generate
hardware interrupts, while output pins can be triggered by
software interrupts.
• GPIO interrupt sensitivity registers – The two GPIO inter-
rupt sensitivity registers specify whether individual pins are
level- or edge-sensitive and specify—if edge-sensitive—
whether just the rising edge or both the rising and falling
edges of the signal are significant. One register selects the
type of sensitivity, and one register selects which edges are
significant for edge-sensitivity.
• Advanced power management supporting unattended
transfer of Rx and Tx frames and status to/from external
memory via DMA during low power sleep mode.
• System wake-up from sleep operating mode upon magic
packet or any of four user-definable wake-up frame filters.
• Support for 802.3Q tagged VLAN frames.
PARALLEL PERIPHERAL INTERFACE (PPI)
• Programmable MDC clock rate and preamble suppression.
The processor provides a parallel peripheral interface (PPI) that
can connect directly to parallel ADC and DAC converters, video
encoders and decoders, and other general-purpose peripherals.
The PPI consists of a dedicated input clock pin, up to three
frame synchronization pins, and up to 16 data pins. The input
clock supports parallel data rates up to half the system clock rate
and the synchronization signals can be configured as either
inputs or outputs.
• In RMII operation, 7 unused pins can be configured as
GPIO pins for other purposes.
PORTS
The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors
group the many peripheral signals to four ports—Port F, Port G,
Port H, and Port J. Most of the associated pins are shared by
multiple signals. The ports function as multiplexer controls.
Eight of the pins (Port F7–0) offer high source/high sink current
capabilities.
The PPI supports a variety of general-purpose and ITU-R 656
modes of operation. In general-purpose mode, the PPI provides
half-duplex, bidirectional data transfer with up to 16 bits of
data. Up to three frame synchronization signals are also pro-
vided. In ITU-R 656 mode, the PPI provides half-duplex
bidirectional transfer of 8- or 10-bit video data. Additionally,
on-chip decode of embedded start-of-line (SOL) and start-of-
field (SOF) preamble packets is supported.
General-Purpose I/O (GPIO)
The processors have 48 bidirectional, general-purpose I/O
(GPIO) pins allocated across three separate GPIO modules—
PORTFIO, PORTGIO, and PORTHIO, associated with Port F,
Port G, and Port H, respectively. Port J does not provide GPIO
functionality. Each GPIO-capable pin shares functionality with
other processor peripherals via a multiplexing scheme; however,
the GPIO functionality is the default state of the device upon
power-up. Neither GPIO output or input drivers are active by
default. Each general-purpose port pin can be individually con-
trolled by manipulation of the port control, status, and interrupt
registers:
General-Purpose Mode Descriptions
The general-purpose modes of the PPI are intended to suit a
wide variety of data capture and transmission applications.
Three distinct submodes are supported:
1. Input mode – Frame syncs and data are inputs into the PPI.
2. Frame capture mode – Frame syncs are outputs from the
PPI, but data are inputs.
• GPIO direction control register – Specifies the direction of
each individual GPIO pin as input or output.
3. Output mode – Frame syncs and data are outputs from the
PPI.
• GPIO control and status registers – The processors employ
a “write one to modify” mechanism that allows any combi-
nation of individual GPIO pins to be modified in a single
instruction, without affecting the level of any other GPIO
pins. Four control registers are provided. One register is
written in order to set pin values, one register is written in
order to clear pin values, one register is written in order to
toggle pin values, and one register is written in order to
specify a pin value. Reading the GPIO status register allows
software to interrogate the sense of the pins.
Input Mode
Input mode is intended for ADC applications, as well as video
communication with hardware signaling. In its simplest form,
PPI_FS1 is an external frame sync input that controls when to
read data. The PPI_DELAY MMR allows for a delay (in PPI_
CLK cycles) between reception of this frame sync and the initia-
tion of data reads. The number of input data samples is user
programmable and defined by the contents of the PPI_COUNT
register. The PPI supports 8-bit and 10-bit through 16-bit data,
programmable in the PPI_CONTROL register.
• GPIO interrupt mask registers – The two GPIO interrupt
mask registers allow each individual GPIO pin to function
as an interrupt to the processor. Similar to the two GPIO
control registers that are used to set and clear individual
pin values, one GPIO interrupt mask register sets bits to
enable interrupt function, and the other GPIO interrupt
mask register clears bits to disable interrupt function.
Frame Capture Mode
Frame capture mode allows the video source(s) to act as a slave
(for frame capture for example). The ADSP-BF534/
ADSP-BF536/ADSP-BF537 processors control when to read
from the video source(s). PPI_FS1 is an HSYNC output and
PPI_FS2 is a VSYNC output.
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Output Mode
Active Operating Mode—Moderate Dynamic Power
Savings
Output mode is used for transmitting video or other data with
up to three output frame syncs. Typically, a single frame sync is
appropriate for data converter applications, whereas two or
three frame syncs could be used for sending video with hard-
ware signaling.
In the active mode, the PLL is enabled but bypassed. Because the
PLL is bypassed, the processor’s core clock (CCLK) and system
clock (SCLK) run at the input clock (CLKIN) frequency. In this
mode, the CLKIN to CCLK multiplier ratio can be changed,
although the changes are not realized until the full-on mode is
entered. DMA access is available to appropriately configured
L1 memories.
ITU-R 656 Mode Descriptions
The ITU-R 656 modes of the PPI are intended to suit a wide
variety of video capture, processing, and transmission applica-
tions. Three distinct submodes are supported:
In the active mode, it is possible to disable the PLL through the
PLL control register (PLL_CTL). If disabled, the PLL must be
re-enabled before transitioning to the full-on or sleep modes.
1. Active video only mode
2. Vertical blanking only mode
3. Entire field mode
Sleep Operating Mode—High Dynamic Power Savings
The sleep mode reduces dynamic power dissipation by disabling
the clock to the processor core (CCLK). The PLL and system
clock (SCLK), however, continue to operate in this mode. Typi-
cally an external event or RTC activity wakes up the processor.
When in the sleep mode, asserting wake-up causes the processor
to sense the value of the BYPASS bit in the PLL control register
(PLL_CTL). If BYPASS is disabled, the processor transitions to
the full on mode. If BYPASS is enabled, the processor transi-
tions to the active mode.
Active Video Mode
Active video only mode is used when only the active video por-
tion of a field is of interest and not any of the blanking intervals.
The PPI does not read in any data between the end of active
video (EAV) and start of active video (SAV) preamble symbols,
or any data present during the vertical blanking intervals. In this
mode, the control byte sequences are not stored to memory;
they are filtered by the PPI. After synchronizing to the start of
Field 1, the PPI ignores incoming samples until it sees an SAV
code. The user specifies the number of active video lines per
frame (in PPI_COUNT register).
System DMA access to L1 memory is not supported in
sleep mode.
Table 4. Power Settings
Vertical Blanking Interval Mode
Core
Clock
System Internal
Clock Power
In this mode, the PPI only transfers vertical blanking interval
(VBI) data.
PLL
Mode
Full On
Active
PLL
Bypassed (CCLK) (SCLK) (VDDINT)
Entire Field Mode
Enabled No
Enabled Enabled On
Enabled Enabled On
Enabled/ Yes
Disabled
In this mode, the entire incoming bit stream is read in through
the PPI. This includes active video, control preamble sequences,
and ancillary data that may be embedded in horizontal and ver-
tical blanking intervals. Data transfer starts immediately after
synchronization to Field 1. Data is transferred to or from the
synchronous channels through eight DMA engines that work
autonomously from the processor core.
Sleep
Enabled
Disabled
—
—
Disabled Enabled On
Disabled Disabled On
Deep
Sleep
Hibernate Disabled
—
Disabled Disabled Off
Deep Sleep Operating Mode—Maximum Dynamic Power
Savings
DYNAMIC POWER MANAGEMENT
The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors pro-
vide five operating modes, each with a different performance
and power profile. In addition, dynamic power management
provides the control functions to dynamically alter the proces-
sor core supply voltage, further reducing power dissipation.
Control of clocking to each of the peripherals also reduces
power consumption. See Table 4 for a summary of the power
settings for each mode. Also, see Table 16, Table 15 and
Table 17.
The deep sleep mode maximizes dynamic power savings by dis-
abling the clocks to the processor core (CCLK) and to all
synchronous peripherals (SCLK). Asynchronous peripherals,
such as the RTC, may still be running but cannot access internal
resources or external memory. This powered-down mode can
only be exited by assertion of the reset interrupt (RESET) or by
an asynchronous interrupt generated by the RTC. When in deep
sleep mode, an RTC asynchronous interrupt causes the
processor to transition to the active mode. Assertion of RESET
while in deep sleep mode causes the processor to transition to
the full-on mode.
Full-On Operating Mode—Maximum Performance
In the full-on mode, the PLL is enabled and is not bypassed,
providing capability for maximum operational frequency. This
is the power-up default execution state in which maximum per-
formance can be achieved. The processor core and all enabled
peripherals run at full speed.
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these power savings are additive, in that if the clock frequency
Hibernate State—Maximum Static Power Savings
and supply voltage are both reduced, the power savings can be
dramatic, as shown in the following equations.
The hibernate state maximizes static power savings by disabling
the voltage and clocks to the processor core (CCLK) and to all of
the synchronous peripherals (SCLK). The internal voltage regu-
lator for the processor can be shut off by writing b#00 to the
FREQ bits of the VR_CTL register. This disables both CCLK
and SCLK. Furthermore, it sets the internal power supply volt-
age (VDDINT) to 0 V to provide the greatest power savings. To
preserve the processor state, prior to removing power, any criti-
cal information stored internally (memory contents, register
contents, etc.) must be written to a nonvolatile storage device.
The power savings factor (PSF) is calculated as:
2
fCCLKRED
---------------------
fCCLKNOM
VDDINTRED
--------------------------
VDDINTNOM
tRED
----------
tNOM
PSF =
where:
f
CCLKNOM is the nominal core clock frequency
CCLKRED is the reduced core clock frequency
Since VDDEXT is still supplied in this state, all of the external pins
three-state, unless otherwise specified. This allows other devices
that are connected to the processor to still have power applied
without drawing unwanted current.
f
V
V
DDINTNOM is the nominal internal supply voltage
DDINTRED is the reduced internal supply voltage
t
t
NOM is the duration running at fCCLKNOM
RED is the duration running at fCCLKRED
The Ethernet or CAN modules can wake up the internal supply
regulator. If the PH6 pin does not connect as the PHYINT sig-
nal to an external PHY device, it can be pulled low by any other
device to wake the processor up. The regulator can also be
woken up by a real-time clock wake-up event or by asserting the
RESET pin. All hibernate wake-up events initiate the hardware
reset sequence. Individual sources are enabled by the VR_CTL
register.
The percent power savings is calculated as
% power savings = 1 – PSF 100%
VOLTAGE REGULATION
With the exception of the VR_CTL and the RTC registers, all
internal registers and memories lose their content in the hiber-
nate state. State variables can be held in external SRAM or
SDRAM. The SCKELOW bit in the VR_CTL register provides a
means of waking from hibernate state without disrupting a self-
refreshing SDRAM, provided that there is also an external pull-
down on the SCKE pin.
The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors pro-
vide an on-chip voltage regulator that can generate appropriate
VDDINT voltage levels from the VDDEXT supply. See Operating
Conditions on Page 23 for regulator tolerances and acceptable
VDDEXT ranges for specific models.
SET OF DECOUPLING
CAPACITORS
V
DDEXT
(LOW-INDUCTANCE)
Power Savings
V
V
DDEXT
DDINT
As shown in Table 5, the processors support three different
power domains which maximizes flexibility, while maintaining
compliance with industry standards and conventions. By isolat-
ing the internal logic of the processor into its own power
domain, separate from the RTC and other I/O, the processor
can take advantage of dynamic power management, without
affecting the RTC or other I/O devices. There are no sequencing
requirements for the various power domains.
+
100μF
10μH
100nF
+
+
100μF
FDS9431A
100μF
10μF
ZHCS1000
LOW ESR
VR
VR
OUT
Table 5. Power Domains
SHORT AND LOW-
INDUCTANCE WIRE
OUT
Power Domain
VDD Range
VDDINT
All internal logic, except RTC
RTC internal logic and crystal I/O
All other I/O
NOTE: DESIGNER SHOULD MINIMIZE
TRACE LENGTH TO FDS9431A.
GND
VDDRTC
VDDEXT
Figure 5. Voltage Regulator Circuit
The dynamic power management feature allows both the pro-
cessor’s input voltage (VDDINT) and clock frequency (fCCLK) to be
dynamically controlled.
Figure 5 shows the typical external components required to
complete the power management system. The regulator con-
trols the internal logic voltage levels and is programmable with
the voltage regulator control register (VR_CTL) in increments
of 50 mV. To reduce standby power consumption, the internal
voltage regulator can be programmed to remove power to the
processor core while keeping I/O power supplied. While in
The power dissipated by a processor is largely a function of its
clock frequency and the square of the operating voltage. For
example, reducing the clock frequency by 25% results in a 25%
reduction in power dissipation, while reducing the voltage by
25% reduces power dissipation by more than 40%. Further,
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hibernate state, VDDEXT can still be applied, eliminating the need
shown in Figure 6. A design procedure for third-overtone oper-
ation is discussed in detail in the application note Using Third
Overtone Crystals with the ADSP-218x DSP (EE-168).
for external buffers. The voltage regulator can be activated from
this power-down state by asserting the RESET pin, which then
initiates a boot sequence. The regulator can also be disabled and
bypassed at the user’s discretion. For additional information on
voltage regulation, see Switching Regulator Design Consider-
ations for the ADSP-BF533 Blackfin Processors (EE-228).
The CLKBUF pin is an output pin, and is a buffer version of the
input clock. This pin is particularly useful in Ethernet applica-
tions to limit the number of required clock sources in the
system. In this type of application, a single 25 MHz or 50 MHz
crystal can be applied directly to the processors. The 25 MHz or
50 MHz output of CLKBUF can then be connected to an exter-
nal Ethernet MII or RMII PHY device.
CLOCK SIGNALS
The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors can
be clocked by an external crystal, a sine wave input, or a buff-
ered, shaped clock derived from an external clock oscillator.
Because of the default 10× PLL multiplier, providing a 50 MHz
CLKIN exceeds the recommended operating conditions of the
lower speed grades. Because of this restriction, an RMII PHY
requiring a 50 MHz clock input cannot be clocked directly from
the CLKBUF pin for the lower speed grades. In this case, either
provide a separate 50 MHz clock source, or use an RMII PHY
with 25 MHz clock input options. The CLKBUF output is active
by default and can be disabled using the VR_CTL register for
power savings.
If an external clock is used, it should be a TTL compatible signal
and must not be halted, changed, or operated below the speci-
fied frequency during normal operation. This signal is
connected to the processor’s CLKIN pin. When an external
clock is used, the XTAL pin must be left unconnected.
Alternatively, because the processors include an on-chip oscilla-
tor circuit, an external crystal can be used. For fundamental
frequency operation, use the circuit shown in Figure 6. A
parallel-resonant, fundamental frequency, microprocessor-
grade crystal is connected across the CLKIN and XTAL pins.
The on-chip resistance between CLKIN and the XTAL pin is in
the 500 k range. Further parallel resistors are typically not rec-
ommended. The two capacitors and the series resistor shown in
Figure 6 fine-tune phase and amplitude of the sine frequency.
The Blackfin core runs at a different clock rate than the on-chip
peripherals. As shown in Figure 7, the core clock (CCLK) and
system peripheral clock (SCLK) are derived from the input
clock (CLKIN) signal. An on-chip PLL is capable of multiplying
the CLKIN signal by a programmable 0.5× to 64× multiplication
factor (bounded by specified minimum and maximum VCO
frequencies). The default multiplier is 10×, but it can be modi-
fied by a software instruction sequence in the PLL_CTL register.
The capacitor and resistor values shown in Figure 6 are typical
values only. The capacitor values are dependent upon the crystal
manufacturers’ load capacitance recommendations and the PCB
physical layout. The resistor value depends on the drive level
specified by the crystal manufacturer. The user should verify the
customized values based on careful investigations of multiple
devices over temperature range.
“FINE” ADJUSTMENT
REQUIRES PLL SEQUENCING
“COARSE” ADJUSTMENT
ON-THE-FLY
CCLK
SCLK
÷ 1, 2, 4, 8
÷ 1 to 15
PLL
0.5u to 64u
CLKIN
VCO
BLACKFIN
CLKOUT
TO PLL CIRCUITRY
EN
SCLK d CCLK
SCLK d 133 MHz
CLKBUF
Figure 7. Frequency Modification Methods
350ꢀ
EN
On-the-fly CCLK and SCLK frequency changes can be effected
by simply writing to the PLL_DIV register. Whereas the maxi-
mum allowed CCLK and SCLK rates depend on the applied
voltages VDDINT and VDDEXT, the VCO is always permitted to run
up to the frequency specified by the part’s speed grade. The
CLKOUT pin reflects the SCLK frequency to the off-chip world.
It belongs to the SDRAM interface, but it functions as a refer-
ence signal in other timing specifications as well. While active
by default, it can be disabled using the EBIU_SDGCTL and
EBIU_AMGCTL registers.
XTAL
1Mꢀ
V
DDEXT
CLKIN
18 pF *
330ꢀ *
FOR OVERTONE
OPERATION ONLY:
18 pF *
NOTE: VALUES MARKED WITH * MUST BE CUSTOMIZED, DEPENDING
ON THE CRYSTAL AND LAYOUT. PLEASE ANALYZE CAREFULLY.
Figure 6. External Crystal Connections
All on-chip peripherals are clocked by the system clock (SCLK).
The system clock frequency is programmable by means of the
SSEL3–0 bits of the PLL_DIV register. The values programmed
into the SSEL fields define a divide ratio between the PLL output
A third-overtone crystal can be used for frequencies above
25 MHz. The circuit is then modified to ensure crystal operation
only at the third overtone, by adding a tuned inductor circuit as
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ADSP-BF534/ADSP-BF536/ADSP-BF537
(VCO) and the system clock. SCLK divider values are 1 through
15. Table 6 illustrates typical system clock ratios.
Table 8. Booting Modes (Continued)
BMODE2–0
101
Description
Table 6. Example System Clock Ratios
Boot from serial TWI memory (EEPROM/flash)
Boot from TWI host (slave mode)
Boot from UART host (slave mode)
110
Example Frequency Ratios
111
(MHz)
Signal Name Divider Ratio
SSEL3–0
VCO:SCLK
VCO
100
300
500
SCLK
The BMODE pins of the reset configuration register, sampled
during power-on resets and software-initiated resets, imple-
ment the following modes:
0001
1:1
100
50
0110
6:1
1010
10:1
50
• Execute from 16-bit external memory – Execution starts
from address 0x2000 0000 with 16-bit packing. The boot
ROM is bypassed in this mode. All configuration settings
are set for the slowest device possible (3-cycle hold time;
15-cycle R/W access times; 4-cycle setup).
Note that the divisor ratio must be chosen to limit the system
clock frequency to its maximum of fSCLK. The SSEL value can be
changed dynamically without any PLL lock latencies by writing
the appropriate values to the PLL divisor register (PLL_DIV).
• Boot from 8-bit and 16-bit external flash memory – The
8-bit or 16-bit flash boot routine located in Boot ROM
memory space is set up using asynchronous memory
bank 0. All configuration settings are set for the slowest
device possible (3-cycle hold time; 15-cycle R/W access
times; 4-cycle setup). The Boot ROM evaluates the first
byte of the boot stream at address 0x2000 0000. If it is 0x40,
8-bit boot is performed. A 0x60 byte assumes a 16-bit
memory device and performs 8-bit DMA. A 0x20 byte also
assumes 16-bit memory but performs 16-bit DMA.
The core clock (CCLK) frequency can also be dynamically
changed by means of the CSEL1–0 bits of the PLL_DIV register.
Supported CCLK divider ratios are 1, 2, 4, and 8, as shown in
Table 7. This programmable core clock capability is useful for
fast core frequency modifications.
Table 7. Core Clock Ratios
Example Frequency Ratios
(MHz)
Signal Name Divider Ratio
• Boot from serial SPI memory (EEPROM or flash) – 8-, 16-,
or 24-bit addressable devices are supported as well as
AT45DB041, AT45DB081, AT45DB161, AT45DB321,
AT45DB642, and AT45DB1282 DataFlash® devices from
Atmel. The SPI uses the PF10/SPI SSEL1 output pin to
select a single SPI EEPROM/flash device, submits a read
command and successive address bytes (0x00) until a valid
8-, 16-, or 24-bit, or Atmel addressable device is detected,
and begins clocking data into the processor.
CSEL1–0
VCO:CCLK
VCO
300
300
500
200
CCLK
00
01
10
11
1:1
2:1
4:1
8:1
300
150
125
25
The maximum CCLK frequency not only depends on the part’s
speed grade (see Ordering Guide on Page 67), it also depends on
the applied VDDINT voltage (see Table 10, Table 11, and Table 12
on Page 24 for details). The maximal system clock rate (SCLK)
depends on the chip package and the applied VDDEXT voltage (see
Table 14 on Page 24).
• Boot from SPI host device – The Blackfin processor oper-
ates in SPI slave mode and is configured to receive the bytes
of the .LDR file from an SPI host (master) agent. To hold
off the host device from transmitting while the boot ROM
is busy, the Blackfin processor asserts a GPIO pin, called
host wait (HWAIT), to signal the host device not to send
any more bytes until the flag is deasserted. The flag is cho-
sen by the user and this information is transferred to the
Blackfin processor via bits 10:5 of the FLAG header.
BOOTING MODES
The ADSP-BF534/ADSP-BF536/ADSP-BF537 processor has six
mechanisms (listed in Table 8) for automatically loading inter-
nal and external memory after a reset. A seventh mode is
provided to execute from external memory, bypassing the boot
sequence.
• Boot from UART – Using an autobaud handshake
sequence, a boot-stream-formatted program is downloaded
by the host. The host agent selects a baud rate within the
UART’s clocking capabilities. When performing the auto-
baud, the UART expects an “@” (boot stream) character
(8 bits data, 1 start bit, 1 stop bit, no parity bit) on the RXD
pin to determine the bit rate. It then replies with an
acknowledgement that is composed of 4 bytes: 0xBF, the
value of UART_DLL, the value of UART_DLH, and 0x00.
The host can then download the boot stream. When the
processor needs to hold off the host, it deasserts CTS.
Therefore, the host must monitor this signal.
Table 8. Booting Modes
BMODE2–0
Description
000
Executefrom16-bitexternalmemory(bypass
boot ROM)
001
Boot from 8-bit or 16-bit memory
(EPROM/flash)
010
011
100
Reserved
Boot from serial SPI memory (EEPROM/flash)
Boot from SPI host (slave mode)
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• Boot from serial TWI memory (EEPROM/flash) – The
• All registers, I/O, and memory are mapped into a unified
Blackfin processor operates in master mode and selects the
TWI slave with the unique ID 0xA0. It submits successive
read commands to the memory device starting at 2-byte
internal address 0x0000 and begins clocking data into the
processor. The TWI memory device should comply with
Philips I2C Bus Specification version 2.1 and have the capa-
bility to auto-increment its internal address counter such
that the contents of the memory device can be read
sequentially.
4G byte memory space, providing a simplified program-
ming model.
• Microcontroller features, such as arbitrary bit and bit-field
manipulation, insertion, and extraction; integer operations
on 8-, 16-, and 32-bit data-types; and separate user and
supervisor stack pointers.
• Code density enhancements, which include intermixing of
16-bit and 32-bit instructions (no mode switching, no code
segregation). Frequently used instructions are encoded
in 16 bits.
• Boot from TWI host – The TWI host agent selects the slave
with the unique ID 0x5F. The processor replies with an
acknowledgement and the host can then download the
boot stream. The TWI host agent should comply with
Philips I2C Bus Specification version 2.1. An I2C multi-
plexer can be used to select one processor at a time when
booting multiple processors from a single TWI.
DEVELOPMENT TOOLS
Analog Devices supports its processors with a complete line of
software and hardware development tools, including integrated
development environments (which include CrossCore® Embed-
ded Studio and/or VisualDSP++®), evaluation products,
emulators, and a wide variety of software add-ins.
For each of the boot modes, a 10-byte header is first brought in
from an external device. The header specifies the number of
bytes to be transferred and the memory destination address.
Multiple memory blocks can be loaded by any boot sequence.
Once all blocks are loaded, program execution commences from
the start of L1 instruction SRAM.
Integrated Development Environments (IDEs)
For C/C++ software writing and editing, code generation, and
debug support, Analog Devices offers two IDEs.
The newest IDE, CrossCore Embedded Studio, is based on the
TM
In addition, Bit 4 of the reset configuration register can be set by
application code to bypass the normal boot sequence during a
software reset. For this case, the processor jumps directly to the
beginning of L1 instruction memory.
Eclipse framework. Supporting most Analog Devices proces-
sor families, it is the IDE of choice for future processors,
including multicore devices. CrossCore Embedded Studio
seamlessly integrates available software add-ins to support real
time operating systems, file systems, TCP/IP stacks, USB stacks,
algorithmic software modules, and evaluation hardware board
support packages. For more information visit
To augment the boot modes, a secondary software loader can be
added to provide additional booting mechanisms. This second-
ary loader could provide the capability to boot from flash,
variable baud rate, and other sources. In all boot modes except
bypass, program execution starts from on-chip L1 memory
address 0xFFA0 0000.
www.analog.com/cces.
The other Analog Devices IDE, VisualDSP++, supports proces-
sor families introduced prior to the release of CrossCore
Embedded Studio. This IDE includes the Analog Devices VDK
real time operating system and an open source TCP/IP stack.
For more information visit www.analog.com/visualdsp. Note
that VisualDSP++ will not support future Analog Devices
processors.
INSTRUCTION SET DESCRIPTION
The Blackfin processor family assembly language instruction set
employs an algebraic syntax designed for ease of coding and
readability. The instructions have been specifically tuned to pro-
vide a flexible, densely encoded instruction set that compiles to
a very small final memory size. The instruction set also provides
fully featured multifunction instructions that allow the
programmer to use many of the processor core resources in a
single instruction. Coupled with many features more often seen
on microcontrollers, this instruction set is very efficient when
compiling C and C++ source code. In addition, the architecture
supports both user (algorithm/application code) and supervisor
(O/S kernel, device drivers, debuggers, ISRs) modes of opera-
tion, allowing multiple levels of access to core processor
resources.
EZ-KIT Lite Evaluation Board
For processor evaluation, Analog Devices provides wide range
of EZ-KIT Lite® evaluation boards. Including the processor and
key peripherals, the evaluation board also supports on-chip
emulation capabilities and other evaluation and development
features. Also available are various EZ-Extenders®, which are
daughter cards delivering additional specialized functionality,
including audio and video processing. For more information
visit www.analog.com and search on “ezkit” or “ezextender”.
EZ-KIT Lite Evaluation Kits
The assembly language, which takes advantage of the proces-
sor’s unique architecture, offers the following advantages:
For a cost-effective way to learn more about developing with
Analog Devices processors, Analog Devices offer a range of EZ-
KIT Lite evaluation kits. Each evaluation kit includes an EZ-KIT
Lite evaluation board, directions for downloading an evaluation
version of the available IDE(s), a USB cable, and a power supply.
The USB controller on the EZ-KIT Lite board connects to the
USB port of the user’s PC, enabling the chosen IDE evaluation
• Seamlessly integrated DSP/MCU features are optimized for
both 8-bit and 16-bit operations.
• A multi-issue load/store modified-Harvard architecture,
which supports two 16-bit MAC or four 8-bit ALU + two
load/store + two pointer updates per cycle.
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ADSP-BF534/ADSP-BF536/ADSP-BF537
suite to emulate the on-board processor in-circuit. This permits
the customer to download, execute, and debug programs for the
EZ-KIT Lite system. It also supports in-circuit programming of
the on-board Flash device to store user-specific boot code,
enabling standalone operation. With the full version of Cross-
Core Embedded Studio or VisualDSP++ installed (sold
separately), engineers can develop software for supported EZ-
KITs or any custom system utilizing supported Analog Devices
processors.
an operation is completed by the emulator, the DSP system is set
to run at full speed with no impact on system timing. The emu-
lators require the target board to include a header that supports
connection of the DSP’s JTAG port to the emulator.
For details on target board design issues including mechanical
layout, single processor connections, signal buffering, signal ter-
mination, and emulator pod logic, see the Engineer-to-Engineer
Note “Analog Devices JTAG Emulation Technical Reference”
(EE-68) on the Analog Devices website (www.analog.com)—use
site search on “EE-68.” This document is updated regularly to
keep pace with improvements to emulator support.
Software Add-Ins for CrossCore Embedded Studio
Analog Devices offers software add-ins which seamlessly inte-
grate with CrossCore Embedded Studio to extend its capabilities
and reduce development time. Add-ins include board support
packages for evaluation hardware, various middleware pack-
ages, and algorithmic modules. Documentation, help,
configuration dialogs, and coding examples present in these
add-ins are viewable through the CrossCore Embedded Studio
IDE once the add-in is installed.
ADDITIONAL INFORMATION
The following publications that describe the ADSP-BF534/
ADSP-BF536/ADSP-BF537 processors (and related processors)
can be ordered from any Analog Devices sales office or accessed
electronically on our website:
• Getting Started with Blackfin Processors
• ADSP-BF537 Blackfin Processor Hardware Reference
Board Support Packages for Evaluation Hardware
• ADSP-BF53x/ADSP-BF56x Blackfin Processor Program-
ming Reference
Software support for the EZ-KIT Lite evaluation boards and EZ-
Extender daughter cards is provided by software add-ins called
Board Support Packages (BSPs). The BSPs contain the required
drivers, pertinent release notes, and select example code for the
given evaluation hardware. A download link for a specific BSP is
located on the web page for the associated EZ-KIT or EZ-
Extender product. The link is found in the Product Download
area of the product web page.
• ADSP-BF534/ADSP-BF536/ADSP-BF537 Blackfin Proces-
sor Anomaly List
RELATED SIGNAL CHAINS
A signal chain is a series of signal-conditioning electronic com-
ponents that receive input (data acquired from sampling either
real-time phenomena or from stored data) in tandem, with the
output of one portion of the chain supplying input to the next.
Signal chains are often used in signal processing applications to
gather and process data or to apply system controls based on
analysis of real-time phenomena. For more information about
this term and related topics, see the "signal chain" entry in
Wikipedia or the Glossary of EE Terms on the Analog Devices
website.
Middleware Packages
Analog Devices separately offers middleware add-ins such as
real time operating systems, file systems, USB stacks, and
TCP/IP stacks. For more information see the following web
pages:
• www.analog.com/ucos3
• www.analog.com/ucfs
• www.analog.com/ucusbd
• www.analog.com/lwip
Analog Devices eases signal processing system development by
providing signal processing components that are designed to
work together well. A tool for viewing relationships between
specific applications and related components is available on the
www.analog.com website.
Algorithmic Modules
To speed development, Analog Devices offers add-ins that per-
form popular audio and video processing algorithms. These are
available for use with both CrossCore Embedded Studio and
VisualDSP++. For more information visit www.analog.com and
search on “Blackfin software modules” or “SHARC software
modules”.
The Application Signal Chains page in the Circuits from the
TM
Lab site (http://www.analog.com/signalchains) provides:
• Graphical circuit block diagram presentation of signal
chains for a variety of circuit types and applications
• Drill down links for components in each chain to selection
guides and application information
Designing an Emulator-Compatible DSP Board (Target)
• Reference designs applying best practice design techniques
For embedded system test and debug, Analog Devices provides
a family of emulators. On each JTAG DSP, Analog Devices sup-
plies an IEEE 1149.1 JTAG Test Access Port (TAP). In-circuit
emulation is facilitated by use of this JTAG interface. The emu-
lator accesses the processor’s internal features via the
processor’s TAP, allowing the developer to load code, set break-
points, and view variables, memory, and registers. The
processor must be halted to send data and commands, but once
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ADSP-BF534/ADSP-BF536/ADSP-BF537
PIN DESCRIPTIONS
The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors pin
definitions are listed in Table 9. In order to maintain maximum
functionality and reduce package size and pin count, some pins
have dual, multiplexed functions. In cases where pin function is
reconfigurable, the default state is shown in plain text, while the
alternate function is shown in italics. Pins shown with an aster-
isk after their name (*) offer high source/high sink current
capabilities.
control and address lines are driven high, with the exception of
CLKOUT, which toggles at the system clock rate. If BR is active
(whether or not RESET is asserted), the memory pins are also
three-stated. During hibernate, all outputs are three-stated
unless otherwise noted in Table 9.
All I/O pins have their input buffers disabled with the exception
of the pins noted in the data sheet that need pull-ups or pull-
downs if unused.
All pins are three-stated during and immediately after reset,
with the exception of the external memory interface, asynchro-
nous and synchronous memory control, and the buffered XTAL
output pin (CLKBUF). On the external memory interface, the
The SDA (serial data) and SCL (serial clock) pins are open drain
and therefore require a pull-up resistor. Consult version 2.1 of
the I2C specification for the proper resistor value.
Table 9. Pin Descriptions
Driver
Type1
Pin Name
Type Function
Memory Interface
ADDR19–1
O
Address Bus for Async Access
Data Bus for Async/Sync Access
A
A
A
DATA15–0
I/O
O
I
ABE1–0/SDQM1–0
Byte Enables/Data Masks for Async/Sync Access
Bus Request (This pin should be pulled high when not used.)
Bus Grant
BR
BG
O
O
A
A
BGH
Bus Grant Hang
Asynchronous Memory Control
AMS3–0
O
I
Bank Select (Require pull-ups if hibernate is used.)
Hardware Ready Control
Output Enable
A
ARDY
AOE
O
O
O
A
A
A
ARE
Read Enable
AWE
Write Enable
Synchronous Memory Control
SRAS
SCAS
SWE
O
O
O
O
Row Address Strobe
Column Address Strobe
Write Enable
A
A
A
A
SCKE
Clock Enable(Requires a pull-down if hibernate with SDRAM self-refresh is
used.)
CLKOUT
SA10
O
O
O
Clock Output
A10 Pin
B
A
A
SMS
Bank Select
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Table 9. Pin Descriptions (Continued)
Driver
Type1
Pin Name
Type Function
Port F: GPIO/UART1–0/Timer7–0/SPI/
External DMA Request/PPI
(* = High Source/High Sink Pin)
PF0* – GPIO/UART0 TX/DMAR0
I/O
GPIO/UART0 Transmit/DMA Request 0
C
C
C
C
C
C
C
C
C
C
C
C
C
PF1* – GPIO/UART0 RX/DMAR1/TACI1 I/O
GPIO/UART0 Receive/DMA Request 1/Timer1 Alternate Input Capture
GPIO/UART1 Transmit/Timer7
PF2* – GPIO/UART1 TX/TMR7
PF3* – GPIO/UART1 RX/TMR6/TACI6
PF4* – GPIO/TMR5/SPI SSEL6
PF5* – GPIO/TMR4/SPI SSEL5
PF6* – GPIO/TMR3/SPI SSEL4
PF7* – GPIO/TMR2/PPI FS3
PF8 – GPIO/TMR1/PPI FS2
PF9 – GPIO/TMR0/PPI FS1
PF10 – GPIO/SPI SSEL1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GPIO/UART1 Receive/Timer6/Timer6 Alternate Input Capture
GPIO/Timer5/SPI Slave Select Enable 6
GPIO/Timer4/SPI Slave Select Enable 5
GPIO/Timer3/SPI Slave Select Enable 4
GPIO/Timer2/PPI Frame Sync 3
GPIO/Timer1/PPI Frame Sync 2
GPIO/Timer0/PPI Frame Sync 1
GPIO/SPI Slave Select Enable 1
PF11 – GPIO/SPI MOSI
GPIO/SPI Master Out Slave In
PF12 – GPIO/SPI MISO
GPIO/SPI Master In Slave Out (This pin should be pulled high through a 4.7 k
resistor if booting via the SPI port.)
PF13 – GPIO/SPI SCK
PF14 – GPIO/SPI SS/TACLK0
PF15 – GPIO/PPI CLK/TMRCLK
Port G: GPIO/PPI/SPORT1
PG0 – GPIO/PPI D0
I/O
I/O
I/O
GPIO/SPI Clock
D
C
C
GPIO/SPI Slave Select/Alternate Timer0 Clock Input
GPIO/PPI Clock/External Timer Reference
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GPIO/PPI Data 0
C
C
C
C
C
C
C
C
C
C
D
C
C
D
C
C
PG1 – GPIO/PPI D1
GPIO/PPI Data 1
PG2 – GPIO/PPI D2
GPIO/PPI Data 2
PG3 – GPIO/PPI D3
GPIO/PPI Data 3
PG4 – GPIO/PPI D4
GPIO/PPI Data 4
PG5 – GPIO/PPI D5
GPIO/PPI Data 5
PG6 – GPIO/PPI D6
GPIO/PPI Data 6
PG7 – GPIO/PPI D7
GPIO/PPI Data 7
PG8 – GPIO/PPI D8/DR1SEC
PG9 – GPIO/PPI D9/DT1SEC
PG10 – GPIO/PPI D10/RSCLK1
PG11 – GPIO/PPI D11/RFS1
PG12 – GPIO/PPI D12/DR1PRI
PG13 – GPIO/PPI D13/TSCLK1
PG14 – GPIO/PPI D14/TFS1
PG15 – GPIO/PPI D15/DT1PRI
GPIO/PPI Data 8/SPORT1 Receive Data Secondary
GPIO/PPI Data 9/SPORT1 Transmit Data Secondary
GPIO/PPI Data 10/SPORT1 Receive Serial Clock
GPIO/PPI Data 11/SPORT1 Receive Frame Sync
GPIO/PPI Data 12/SPORT1 Receive Data Primary
GPIO/PPI Data 13/SPORT1 Transmit Serial Clock
GPIO/PPI Data 14/SPORT1 Transmit Frame Sync
GPIO/PPI Data 15/SPORT1 Transmit Data Primary
Rev. J
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Page 20 of 68
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February 2014
ADSP-BF534/ADSP-BF536/ADSP-BF537
Table 9. Pin Descriptions (Continued)
Driver
Type1
Pin Name
Type Function
Port H: GPIO/10/100 Ethernet MAC (On
ADSP-BF534, these pins are GPIO only)
PH0 – GPIO/ETxD0
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GPIO/Ethernet MII or RMII Transmit D0
E
E
E
E
E
E
E
PH1 – GPIO/ETxD1
GPIO/Ethernet MII or RMII Transmit D1
GPIO/Ethernet MII Transmit D2
PH2 – GPIO/ETxD2
PH3 – GPIO/ETxD3
GPIO/Ethernet MII Transmit D3
PH4 – GPIO/ETxEN
GPIO/Ethernet MII or RMII Transmit Enable
GPIO/Ethernet MII Transmit Clock/RMII Reference Clock
PH5 – GPIO/MII TxCLK/RMII REF_CLK
PH6 – GPIO/MII PHYINT/RMII MDINT
GPIO/Ethernet MII PHY Interrupt/RMII Management Data Interrupt (This pin
should be pulled high when used as a hibernate wake-up.)
PH7 – GPIO/COL
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GPIO/Ethernet Collision
E
E
E
E
E
E
E
E
E
PH8 – GPIO/ERxD0
GPIO/Ethernet MII or RMII Receive D0
PH9 – GPIO/ERxD1
GPIO/Ethernet MII or RMII Receive D1
PH10 – GPIO/ERxD2
GPIO/Ethernet MII Receive D2
PH11 – GPIO/ERxD3
GPIO/Ethernet MII Receive D3
PH12 – GPIO/ERxDV/TACLK5
PH13 – GPIO/ERxCLK/TACLK6
PH14 – GPIO/ERxER/TACLK7
PH15 – GPIO/MII CRS/RMII CRS_DV
GPIO/Ethernet MII Receive Data Valid/Alternate Timer5 Input Clock
GPIO/Ethernet MII Receive Clock/Alternate Timer6 Input Clock
GPIO/Ethernet MII or RMII Receive Error/Alternate Timer7 Input Clock
GPIO/Ethernet MII Carrier Sense/Ethernet RMII Carrier Sense and Receive Data
Valid
Port J: SPORT0/TWI/SPI Select/CAN
PJ0 – MDC
O
Ethernet Management Channel Clock (On ADSP-BF534 processors, do not
connect this pin.)
E
PJ1 – MDIO
PJ2 – SCL
PJ3 – SDA
I/O
I/O
I/O
EthernetManagement ChannelSerialData(OnADSP-BF534processors, tie this E
pin to ground.)
TWI Serial Clock (This pin is an open-drain output and requires a pull-up
resistor.)
F
TWI Serial Data (This pin is an open-drain output and requires a pull-up
resistor.)
F
PJ4 – DR0SEC/CANRX/TACI0
I
SPORT0 Receive Data Secondary/CAN Receive/Timer0 Alternate Input Capture
SPORT0 Transmit Data Secondary/CAN Transmit/SPI Slave Select Enable 7
SPORT0 Receive Serial Clock/Alternate Timer2 Clock Input
SPORT0 Receive Frame Sync/Alternate Timer3 Clock Input
SPORT0 Receive Data Primary/Alternate Timer4 Clock Input
SPORT0 Transmit Serial Clock/Alternate Timer1 Clock Input
SPORT0 Transmit Frame Sync/SPI Slave Select Enable 3
PJ5 – DT0SEC/CANTX/SPI SSEL7
O
C
D
C
PJ6 – RSCLK0/TACLK2
I/O
I/O
I
PJ7 – RFS0/TACLK3
PJ8 – DR0PRI/TACLK4
PJ9 – TSCLK0/TACLK1
I/O
I/O
O
D
C
C
PJ10 – TFS0/SPI SSEL3
PJ11 – DT0PRI/SPI SSEL2
SPORT0 Transmit Data Primary/SPI Slave Select Enable 2
Real-Time Clock
RTXI
I
RTC Crystal Input (This pin should be pulled low when not used.)
RTC Crystal Output (Does not three-state in hibernate.)
RTXO
JTAG Port
TCK
O
I
JTAG Clock
TDO
O
I
JTAG Serial Data Out
C
C
TDI
JTAG Serial Data In
TMS
I
JTAG Mode Select
TRST
I
JTAG Reset (This pin should be pulled low if the JTAG port is not used.)
Emulation Output
EMU
O
Rev. J
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Page 21 of 68
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February 2014
ADSP-BF534/ADSP-BF536/ADSP-BF537
Table 9. Pin Descriptions (Continued)
Driver
Type1
Pin Name
Clock
Type Function
CLKIN
I
Clock/Crystal Input
XTAL
O
O
Crystal Output (If CLKBUF is enabled, does not three-state during hibernate.)
Buffered XTAL Output (If enabled, does not three-state during hibernate.)
CLKBUF
Mode Controls
RESET
E
I
I
I
Reset
NMI
Nonmaskable Interrupt (This pin should be pulled high when not used.)
BMODE2–0
Boot Mode Strap 2-0 (These pins must be pulled to the state required for the
desired boot mode.)
Voltage Regulator
VROUT1–0
O
External FET Drive (These pins should be left unconnected when not used and
are driven high during hibernate.)
Supplies
VDDEXT
VDDINT
P
P
P
I/O Power Supply
Internal Power Supply
VDDRTC
Real-Time Clock Power Supply (This pin should be connected to VDDEXT when
not used and should remain powered at all times.)
GND
G
External Ground
1 See Output Drive Currents on Page 50 for more information about each driver types.
Rev. J
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Page 22 of 68
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February 2014
ADSP-BF534/ADSP-BF536/ADSP-BF537
SPECIFICATIONS
Note that component specifications are subject to change
without notice.
OPERATING CONDITIONS
Parameter
Conditions
Min
Nominal Max
Unit
VDDINT Internal Supply Voltage1
Nonautomotive 300 MHz, 400 MHz, and 500 MHz speed 0.8
grade models2
1.2
1.32
V
VDDINT Internal Supply Voltage1
VDDINT Internal Supply Voltage1
VDDINT Internal Supply Voltage1
Nonautomotive 533 MHz speed grade models2
Nonautomotive 600 MHz speed grade models2
0.8
1.25
1.3
1.375
1.43
1.32
V
V
V
0.8
Automotive grade models and +105°C nonautomotive
grade models2
0.95
1.2
VDDEXT External Supply Voltage
VDDEXT External Supply Voltage
Nonautomotive grade models2
2.25
2.7
2.5 or 3.3 3.6
3.0 or 3.3 3.6
V
V
Automotive grade models and +105°C nonautomotive
grade models2
VDDRTC Real-Time Clock Power
Supply Voltage
2.25
3.6
V
VIH
VIHCLKIN High Level Input Voltage5 VDDEXT = Maximum
High Level Input Voltage3, 4 VDDEXT = Maximum
2.0
V
V
V
2.2
VIH5V
5.0 V Tolerant Pins, High
Level Input Voltage6
0.7 × VDDEXT
VIH5V
5.0 V Tolerant Pins, High
Level Input Voltage7
VDDEXT = Maximum
2.0
V
VIL
Low Level Input Voltage3, 8 VDDEXT = Minimum
+0.6
V
V
VIL5V
5.0 V Tolerant Pins, Low
Level Input Voltage6
0.3 × VDDEXT
VIL5V
TJ
5.0 V Tolerant Pins, Low
Level Input Voltage7
VDDEXT = Minimum
+0.8
V
Junction Temperature
Junction Temperature
Junction Temperature
Junction Temperature
Junction Temperature
208-Ball Chip Scale Package Ball Grid Array (CSP_BGA) @ –40
TAMBIENT = –40°C to +105°C
+120
°C
°C
°C
°C
°C
TJ
208-Ball Chip Scale Package Ball Grid Array (CSP_BGA) @ –40
TAMBIENT = –40°C to +85°C
+105
TJ
208-Ball Chip Scale Package Ball Grid Array (CSP_BGA) @
TAMBIENT = 0°C to +70°C
0
+95
TJ
182-Ball Chip Scale Package Ball Grid Array (CSP_BGA) @ –40
TAMBIENT = –40°C to +85°C
+105
TJ
182-Ball Chip Scale Package Ball Grid Array (CSP_BGA) @
TAMBIENT = 0°C to +70°C
0
+100
1 The regulator can generate VDDINT at levels of 0.85 V to 1.2 V with –5% to +10% tolerance, 1.25 V with –4% to +10% tolerance, and 1.3 V with –0% to +10% tolerance. The
required VDDINT is a function of speed grade and operating frequency. See Table 10, Table 11, and Table 12 for details.
2 See Ordering Guide on Page 67.
3 Bidirectional pins (DATA15–0, PF15–0, PG15–0, PH15–0, TFS0, TSCLK0, RSCLK0, RFS0, MDIO) and input pins (BR, ARDY, DR0PRI, DR0SEC, RTXI, TCK, TDI, TMS,
TRST, CLKIN, RESET, NMI, and BMODE2–0) of the ADSP-BF534/ADSP-BF536/ADSP-BF537 are 3.3 V-tolerant (always accept up to 3.6 V maximum VIH). Voltage
compliance (on outputs, VOH) is limited by the VDDEXT supply voltage.
4 Parameter value applies to all input and bidirectional pins except CLKIN, SDA, and SCL.
5 Parameter value applies to CLKIN pin only.
6 Applies to pins PJ2/SCL and PJ3/SDA which are 5.0 V tolerant (always accept up to 5.5 V maximum VIH). Voltage compliance (on outputs, VOH) is limited by the VDDEXT supply
voltage.
7 Applies to pin PJ4/DR0SEC/CANRX/TACI0 which is 5.0 V tolerant (always accepts up to 5.5 V maximum VIH). Voltage compliance (on outputs, VOH) is limited by the VDDEXT
supply voltage.
8 Parameter value applies to all input and bidirectional pins except SDA and SCL.
Rev. J
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Page 23 of 68
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February 2014
ADSP-BF534/ADSP-BF536/ADSP-BF537
Table 10 through Table 12 describe the voltage/frequency
requirements for the ADSP-BF534/ADSP-BF536/ADSP-BF537
processor clocks. Take care in selecting MSEL, SSEL, and CSEL
ratios so as not to exceed the maximum core clock and system
clock. Table 13 describes phase-locked loop operating
conditions.
Table 10. Core Clock Requirements—500 MHz, 533 MHz, and 600 MHz Speed Grades1
Parameter Internal Regulator Setting
Max
600
533
500
444
400
333
250
Unit
MHz
MHz
MHz
MHz
MHz
MHz
MHz
fCCLK
fCCLK
fCCLK
fCCLK
fCCLK
fCCLK
fCCLK
Core Clock Frequency (VDDINT =1.30 V Minimum)2
1.30 V
1.25 V
1.20 V
1.10 V
1.00 V
0.90 V
0.85 V
Core Clock Frequency (VDDINT = 1.20 V Minimum)3
Core Clock Frequency (VDDINT =1.14 V Minimum)
Core Clock Frequency (VDDINT =1.045 V Minimum)
Core Clock Frequency (VDDINT = 0.95 V Minimum)
Core Clock Frequency (VDDINT = 0.85 V Minimum)
Core Clock Frequency (VDDINT = 0.8 V Minimum)
1 See Ordering Guide on Page 67.
2 Applies to 600 MHz models only. See Ordering Guide on Page 67.
3 Applies to 533 MHz and 600 MHz models only. See Ordering Guide on Page 67.
Table 11. Core Clock Requirements—400 MHz Speed Grade1
120°C TJ 105°C
Internal Regulator Setting Max
All2 Other TJ
Max
Parameter
Unit
fCCLK Core Clock Frequency (VDDINT =1.14 V Minimum) 1.20 V
fCCLK Core Clock Frequency (VDDINT =1.045 V Minimum) 1.10 V
fCCLK Core Clock Frequency (VDDINT = 0.95 V Minimum) 1.00 V
fCCLK Core Clock Frequency (VDDINT = 0.85 V Minimum) 0.90 V
fCCLK Core Clock Frequency (VDDINT = 0.8 V Minimum) 0.85 V
400
333
295
400
363
333
280
250
MHz
MHz
MHz
MHz
MHz
1 See Ordering Guide on Page 67.
2 See Operating Conditions on Page 23.
Table 12. Core Clock Requirements—300 MHz Speed Grade1
Parameter
Internal Regulator Setting
Max
Unit
MHz
MHz
MHz
MHz
MHz
fCCLK
fCCLK
fCCLK
fCCLK
fCCLK
Core Clock Frequency (VDDINT =1.14 V Minimum)
Core Clock Frequency (VDDINT =1.045 V Minimum)
Core Clock Frequency (VDDINT = 0.95 V Minimum)
Core Clock Frequency (VDDINT = 0.85 V Minimum)
Core Clock Frequency (VDDINT = 0.8 V Minimum)
1.20 V
1.10 V
1.00 V
0.90 V
0.85 V
300
255
210
180
160
1 See Ordering Guide on Page 67.
Table 13. Phase-Locked Loop Operating Conditions
Parameter
Min
Max
Max fCCLK
Unit
fVCO
Voltage Controlled Oscillator (VCO) Frequency
50
MHz
Table 14. System Clock Requirements
Parameter
Condition
Max
1332
100
Unit
MHz
MHz
1
fSCLK
VDDEXT 3.3 V or 2.5 V, VDDINT 1.14 V
VDDEXT 3.3 V or 2.5 V, VDDINT 1.14 V
1
fSCLK
1 fSCLK must be less than or equal to fCCLK and is subject to additional restrictions for SDRAM interface operation. See Table 27 on Page 34.
2 Rounded number. Actual test specification is SCLK period of 7.5 ns. See Table 27 on Page 34.
Rev. J
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Page 24 of 68
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February 2014
ADSP-BF534/ADSP-BF536/ADSP-BF537
ELECTRICAL CHARACTERISTICS
300 MHz/400 MHz1
500 MHz/533 MHz/600 MHz2
Parameter
Test Conditions
VDDEXT = 2.5 V/3.0 V/
Output Voltage 3.3 V 10%,
OH = –0.5 mA
Min
Typ
Max
Min
Typ
Max
Unit
3
VOH
High Level
VDDEXT – 0.5
VDDEXT – 0.5
V
I
4
VOH
VDDEXT = 3.3 V 10%, VDDEXT – 0.5
IOH = –8 mA
VDDEXT = 2.5 V/3.0 V
10%, IOH = –6 mA
VDDEXT – 0.5
V
V
V
V
DDEXT – 0.5
V
DDEXT – 0.5
5
VOH
VDDEXT = 2.5 V/3.0 V/
3.3 V 10%,
V
DDEXT – 0.5
VDDEXT – 0.5
IOH = –2.0 mA
6
IOH
High Level
Output Current
VOH = VDDEXT – 0.5 V Min
VOH = VDDEXT – 0.5 V Min
VDDEXT = 2.5 V/3.0 V/
–64
–144
0.4
–64
–144
0.4
mA
mA
V
7
IOH
3
VOL
Low Level
Output Voltage 3.3 V 10%,
IOL = 2.0 mA
4
VOL
VDDEXT = 3.3 V 10%,
0.5
0.5
0.5
0.5
0.5
0.5
V
V
V
IOL = 8 mA
VDDEXT = 2.5 V/3.0 V
10%, IOL = 6 mA
5
VOL
VDDEXT = 2.5 V/3.0 V/
3.3 V 10%,
IOL = 2.0 mA
6
IOL
Low Level
VOL = 0.5 V Max
64
64
mA
Output Current
7
IOL
VOL = 0.5 V Max
144
10
144
10
mA
μA
IIH
High Level Input VDDEXT =3.6 V, VIN = 3.6 V
Current8
IIH5V
IIL
IIHP
IOZH
High Level Input VDDEXT =3.6 V, VIN = 5.5 V
Current9
10
10
50
10
10
10
50
10
μA
μA
μA
μA
Low Level Input VDDEXT =3.6 V, VIN = 0 V
Current2
High Level Input VDDEXT = 3.6 V, VIN = 3.6 V
Current JTAG10
Three-State
Leakage
VDDEXT = 3.6 V, VIN = 3.6 V
VDDEXT =3.6 V, VIN = 5.5 V
VDDEXT = 3.6 V, VIN = 0 V
Current11
IOZH5V
Three-State
Leakage
10
10
10
10
μA
μA
Current12
IOZL
Three-State
Leakage
Current5
Rev. J
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Page 25 of 68
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February 2014
ADSP-BF534/ADSP-BF536/ADSP-BF537
300 MHz/400 MHz1
500 MHz/533 MHz/600 MHz2
Parameter
Test Conditions
Min
Typ
Max
Min
Typ
Max
Unit
CIN
Input
fIN = 1 MHz,
8
8
pF
Capacitance13, 14 TAMBIENT = 25°C,
VIN = 2.5 V
IDD-IDLE
IDD-TYP
IDD-TYP
VDDINT Current in VDDINT = 1.0 V,
14
24
mA
mA
mA
mA
mA
mA
mA
A
Idle
fCCLK = 50 MHz,
TJ = 25°C, ASF = 0.43
VDDINT Current
VDDINT = 1.14 V,
100
125
6
113
138
16
fCCLK = 300 MHz,
TJ = 25°C, ASF = 1.00
VDDINT Current
VDDINT = 1.14 V,
fCCLK = 400 MHz,
TJ = 25°C, ASF = 1.00
15
IDDDEEPSLEEP
VDDINT Current in VDDINT = 1.0 V,
Deep Sleep
Mode
fCCLK = 0 MHz,
TJ = 25°C, ASF = 0.00
IDDSLEEP
IDD-TYP
IDD-TYP
VDDINT Current in VDDINT = 1.0 V,
9.5
19.5
185
227
50
Sleep Mode
fSCLK = 25 MHz,
TJ = 25°C
VDDINT Current
VDDINT = 1.20 V,
fCCLK = 533 MHz,
TJ = 25°C, ASF = 1.00
VDDINT Current
VDDINT = 1.30 V,
fCCLK = 600 MHz,
TJ = 25°C, ASF = 1.00
15, 16
IDDHIBERNATE
VDDEXT Current in VDDEXT = 3.60 V,
Hibernate State CLKIN=0 MHz,
50
20
100
100
TJ = maximum, with
voltage regulator off
(VDDINT = 0 V)
IDDRTC
VDDRTC Current
VDDRTC = 3.3 V, TJ= 25°C
20
A
mA
15
IDDDEEPSLEEP
VDDINT Current in fCCLK = 0 MHz,
Table 16
Table 15
Deep Sleep
Mode
fSCLK =0 MHz
15, 17
IDDSLEEP
VDDINT Current in fCCLK = 0 MHz,
I
DDDEEPSLEEP + (0.14
× VDDINT × fSCLK
IDDSLEEP
(Table 18 × ASF)
I
DDDEEPSLEEP + (0.14 mA
× VDDINT × fSCLK
IDDSLEEP
(Table 18 × ASF)
Sleep Mode
fSCLK 0 MHz
fCCLK 0 MHz,
fSCLK 0 MHz
)
)
18
IDDINT
VDDINT Current
+
+
mA
1 Applies to all 300 MHz and 400 MHz speed grade models. See Ordering Guide on Page 67.
2 Applies to all 500 MHz, 533 MHz, and 600 MHz speed grade models. See Ordering Guide on Page 67.
3 Applies to all output and bidirectional pins except port F pins, port G pins, and port H pins.
4 Applies to port F pins PF7–0.
5 Applies to port F pins PF15–8, all port G pins, and all port H pins.
6 Maximum combined current for Port F7–0.
7 Maximum total current for all port F, port G, and port H pins.
8 Applies to all input pins except PJ4.
9 Applies to input pin PJ4 only.
10Applies to JTAG input pins (TCK, TDI, TMS, TRST).
11Applies to three-statable pins.
12Applies to bidirectional pins PJ2 and PJ3.
13Applies to all signal pins.
14Guaranteed, but not tested.
15See the ADSP-BF537 Blackfin Processor Hardware Reference Manual for definition of sleep, deep sleep, and hibernate operating modes.
16CLKIN must be tied to VDDEXT or GND during hibernate.
17In the equations, the fSCLK parameter is the system clock in MHz.
18See Table 17 for the list of IDDINT power vectors covered.
Rev. J
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Page 26 of 68
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February 2014
ADSP-BF534/ADSP-BF536/ADSP-BF537
System designers should refer to Estimating Power for the
current dissipation for internal circuitry (VDDINT). IDDDEEPSLEEP
ADSP-BF534/BF536/BF537 Blackfin Processors (EE-297), which
provides detailed information for optimizing designs for lowest
power. All topics discussed in this section are described in detail
in EE-297. Total power dissipation has two components:
specifies static power dissipation as a function of voltage
(VDDINT) and temperature (see Table 16 or Table 15), and IDDINT
specifies the total power specification for the listed test condi-
tions, including the dynamic component as a function of voltage
(VDDINT) and frequency (Table 18).
1. Static, including leakage current
The dynamic component is also subject to an Activity Scaling
Factor (ASF) which represents application code running on the
processor (Table 17).
2. Dynamic, due to transistor switching characteristics
Many operating conditions can also affect power dissipation,
including temperature, voltage, operating frequency, and pro-
cessor activity. Electrical Characteristics on Page 25 shows the
Table 15. Static Current–500 MHz, 533 MHz, and 600 MHz Speed Grade Devices (mA)1
Voltage (VDDINT
0.80 V 0.85 V 0.90 V 0.95 V 1.00 V 1.05 V 1.10 V 1.15 V 1.20 V 1.25 V 1.30 V 1.32 V 1.375 V 1.43 V
)
TJ (°C)
–40
0
3.9
4.7
6.8
8.2
9.9
12.0
14.6
17.3
20.3
24.1
27.1
28.6
36.3
44.4
17.0
35.0
53.0
76.7
110.1
150.1
202.3
223.8
19.2
39.2
59.2
84.6
120.0
164.5
219.2
241.4
21.9
44.3
65.3
93.6
130.9
178.7
236.5
260.4
25.0
28.2
32.1
36.9
41.8
47.7
53.8
61.0
63.8
73.2
84.1
25
50.8
56.1
63.3
69.1
76.4
84.7
93.5
104.5
142.6
194.4
259.8
341.1
440.4
477.8
109.1
148.5
201.4
268.8
351.2
453.4
492.2
123.4
166.5
223.7
295.9
384.6
494.3
535.1
138.8
185.6
247.5
325.2
420.3
538.2
581.5
40
71.9
79.1
88.0
96.6
108.0
148.3
201.7
268.8
351.2
381.7
120.0
162.8
220.6
291.4
378.8
410.8
130.7
178.4
239.7
314.1
407.5
443.6
55
103.1
142.2
193.2
255.8
282.0
113.7
156.5
210.4
277.8
303.4
123.9
171.3
228.9
299.8
328.7
136.3
185.2
247.7
323.8
354.5
70
85
100
105
1 Values are guaranteed maximum IDDDEEPSLEEP specifications.
Table 16. Static Current–300 MHz and 400 MHz Speed Grade Devices (mA)1
Voltage (VDDINT
)
TJ (°C)
–40
0
0.80 V
2.6
0.85 V
3.2
0.90 V
3.7
0.95 V
4.5
1.00 V
5.5
1.05 V
1.10 V
7.9
1.15 V
1.20 V
1.25 V
1.30 V
1.32 V
14.8
6.6
9.3
10.5
12.5
13.9
6.6
7.8
8.4
9.9
10.9
12.3
19.9
28.2
41.4
58.6
82.9
112.5
123.0
148.5
163.7
13.8
15.5
25.6
34.9
50.0
69.7
98.4
130.6
143.3
171.4
189.3
17.5
19.6
21.7
23.1
25
12.2
17.2
25.7
37.6
53.7
75.1
84.5
103.8
115.5
13.5
19.0
27.8
41.3
58.3
82.3
91.2
111.8
123.6
14.8
20.6
30.9
44.8
63.7
88.5
98.2
120.3
132.2
16.4
22.9
33.7
48.9
69.0
95.8
106.0
127.6
141.9
18.2
22.7
28.4
31.8
35.7
37.2
40
25.9
31.6
38.9
42.9
47.6
49.5
55
37.3
44.8
54.8
59.4
66.1
68.4
70
53.9
63.9
76.9
84.0
92.2
94.9
85
75.9
90.5
106.4
141.3
155.0
184.6
202.8
115.3
153.2
167.4
198.8
217.7
124.6
164.8
179.8
213.4
232.3
128.1
169.7
185.4
219.6
238.6
100
105
1152
1202
104.0
114.2
138.0
152.3
121.8
132.4
159.6
175.6
1 Values are guaranteed maximum IDDDEEPSLEEP specifications.
2 Applies to automotive grade models only.
Rev. J
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Page 27 of 68
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February 2014
ADSP-BF534/ADSP-BF536/ADSP-BF537
Table 17. Activity Scaling Factors
IDDINT Power Vector1
Activity Scaling Factor (ASF)2
IDD-PEAK
1.33
1.29
1.00
0.88
0.72
0.43
IDD-HIGH
IDD-TYP
IDD-APP
IDD-NOP
IDD-IDLE
1 See EE-297 for power vector definitions.
2 All ASF values determined using a 10:1 CCLK:SCLK ratio.
Table 18. Dynamic Current (mA, with ASF = 1.0)1
Voltage (VDDINT
)
Frequency
(MHz)
0.80 V 0.85 V 0.90 V 0.95 V 1.00 V 1.05 V 1.10 V 1.15 V 1.20 V 1.25 V 1.30 V 1.32 V 1.375 V 1.43 V
50
11.0
27.9
36.9
N/A
N/A
N/A
N/A
N/A
13.7
22.7
42.6
61.5
N/A
N/A
N/A
N/A
19.13 18.2
18.67 19.13 19.6
21.2
35.3
62.9
90.7
24.1
37.8
67.0
94.3
25.5
40.6
69.7
99.1
28.5
43.5
73.0
28.6
43.7
74.0
28.85
44.1
75.7
29.2
100
200
300
400
500
533
600
30.8
55.0
79.2
N/A
N/A
N/A
N/A
28.4
49.2
70.4
92.4
N/A
N/A
N/A
29.3
51.5
74.6
97.2
N/A
N/A
N/A
30.8
55.0
79.2
32.9
58.3
84.4
45.8
80.7
103.9 105.5 108.0
113.4
145.1
176.9
187.9
210.0
104.3 109.8 116.5 121.9 128.0 134.6 136.6 139.8
N/A
N/A
N/A
N/A
N/A
N/A
142.3 149.3 157.5 164.7 166.7 169.8
N/A
N/A
158.6 167.0 174.3 176.6 180.1
N/A N/A 193.7 196.5 200.7
1 The values are not guaranteed as stand-alone maximum specifications, they must be combined with static current per the equations of Electrical Characteristics on Page 25.
Rev. J
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February 2014
ADSP-BF534/ADSP-BF536/ADSP-BF537
ABSOLUTE MAXIMUM RATINGS
PACKAGE INFORMATION
Stresses greater than those listed in Table 19 may cause perma-
nent damage to the device. These are stress ratings only.
Functional operation of the device at these or any other condi-
tions greater than those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
The information presented in Figure 8 and Table 21 provide
details about the package branding for the Blackfin processors.
For a complete listing of product availability, see Ordering
Guide on Page 67.
a
ADSP-BF53x
tppZccc
Table 19. Absolute Maximum Ratings
Parameter
Rating
vvvvvv.x n.n
#yyww country_of_origin
Internal (Core) Supply Voltage (VDDINT
)
–0.3 V to +1.43 V
–0.3 V to +3.8 V
–0.5 V to +3.6 V
–0.5 V to +5.5 V
–0.5 V to VDDEXT + 0.5 V
–65°C to +150°C
+125°C
External (I/O) Supply Voltage (VDDEXT
Input Voltage1
)
B
Input Voltage1, 2
Figure 8. Product Information on Package
Output Voltage Swing
Table 21. Package Brand Information1
Storage Temperature Range
Junction Temperature While Biased
Brand Key
Field Description
Temperature Range
Package Type
1 Applies only when VDDEXT is within specifications. When VDDEXT is outside speci-
fications, the range is VDDEXT 0.2 V.
t
pp
2 Applies to 5 V tolerant pins SCL, SDA, and PJ4. For duty cycles, see Table 20.
Z
RoHS Compliant Designation
See Ordering Guide
Assembly Lot Code
Silicon Revision
Table 20. Maximum Duty Cycle for Input1 Transient Voltage
ccc
vvvvvv.x
n.n
VIN Min (V)2
–0.50
VIN Max (V)2
+3.80
Maximum Duty Cycle3
100%
40%
25%
15%
10%
#
RoHS Compliant Designation
Date Code
–0.70
+4.00
yyww
–0.80
+4.10
1 Nonautomotive only. For branding information specific to Automotive
products, contact Analog Devices Inc.
–0.90
+4.20
–1.00
+4.30
1 Applies to all signal pins with the exception of CLKIN, XTAL, and VROUT1–0.
2 The individual values cannot be combined for analysis of a single instance of
overshoot or undershoot. The worst case observed value must fall within one of
the voltages specified and the total duration of the overshoot or undershoot
(exceeding the 100% case) must be less than or equal to the corresponding
duty cycle.
3 Duty cycle refers to the percentage of time the signal exceeds the value for the
100% case. This is equivalent to the measured duration of a single instance of
overshoot or undershoot as a percentage of the period of occurrence.
ESD SENSITIVITY
ESD (electrostatic discharge) sensitive device.
Charged devices and circuit boards can discharge
without detection. Although this product features
patented or proprietary protection circuitry, damage
may occur on devices subjected to high energy ESD.
Therefore, proper ESD precautions should be taken to
avoid performance degradation or loss of functionality.
Rev. J
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Page 29 of 68
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February 2014
ADSP-BF534/ADSP-BF536/ADSP-BF537
TIMING SPECIFICATIONS
Component specifications are subject to change
without notice.
Clock and Reset Timing
Table 22. Clock Input and Reset Timing
Parameter
Min
Max
Unit
Timing Requirements
tCKIN
CLKIN Period1, 2, 3, 4
20.0
8.0
100.0
ns
ns
ns
ns
ns
ns
tCKINL
CLKIN Low Pulse
tCKINH
tBUFDLAY
tWRST
CLKIN High Pulse
8.0
CLKIN to CLKBUF Delay
10
RESET Asserted Pulse Width Low
RESET Deassertion to First External Access Delay5
11 × tCKIN
3 × tCKIN
tNOBOOT
5 × tCKIN
1 Combinations of the CLKIN frequency and the PLL clock multiplier must not exceed the allowed fVCO, fCCLK, and fSCLK settings discussed in Table 10 through Table 14. Since
by default the PLL is multiplying the CLKIN frequency by 10 MHz, 300 MHz, and 400 MHz speed grade parts can not use the full CLKIN period range.
2 Applies to PLL bypass mode and PLL non bypass mode.
3 CLKIN frequency must not change on the fly.
4 If the DF bit in the PLL_CTL register is set, then the maximum tCKIN period is 50 ns.
5 Applies when processor is configured in No Boot Mode (BMODE2-0 = b#000).
tCKIN
CLKIN
tBUFDLAY
tCKINL
tCKINH
tBUFDLAY
CLKBUF
tWRST
RESET
Figure 9. Clock and Reset Timing
Table 23. Power-Up Reset Timing
Parameter
Min
Max
Unit
Timing Requirements
tRST_IN_PWR RESET Deasserted After the VDDINT, VDDEXT, VDDRTC, and CLKIN Pins Are Stable and 3500 × tCKIN
Within Specification
ns
tRST_IN_PWR
RESET
CLKIN
V
DD_SUPPLIES
In Figure 10, VDD_SUPPLIES is VDDINT, VDDEXT, VDDRTC
Figure 10. Power-Up Reset Timing
Rev. J
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February 2014
ADSP-BF534/ADSP-BF536/ADSP-BF537
Asynchronous Memory Read Cycle Timing
Table 24. Asynchronous Memory Read Cycle Timing
Parameter
Min
Max
Unit
Timing Requirements
tSDAT
DATA15–0 Setup Before CLKOUT
DATA15–0 Hold After CLKOUT
ARDY Setup Before CLKOUT
ARDY Hold After CLKOUT
2.1
0.8
4.0
0.0
ns
ns
ns
ns
tHDAT
tSARDY
tHARDY
Switching Characteristics
tDO
tHO
Output Delay After CLKOUT1
Output Hold After CLKOUT 1
6.0
ns
ns
0.8
1 Output pins include AMS3–0, ABE1–0, ADDR19–1, AOE, ARE.
SETUP
PROGRAMMED READ
ACCESS 4 CYCLES
ACCESS EXTENDED
3 CYCLES
HOLD
1 CYCLE
2 CYCLES
CLKOUT
tDO
tHO
AMSx
ABE1–0
ADDR19–1
AOE
ARE
tDO
tHO
tSARDY
tHARDY
ARDY
tSARDY
tHARDY
tSDAT
tHDAT
DATA 15–0
Figure 11. Asynchronous Memory Read Cycle Timing
Rev. J
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February 2014
ADSP-BF534/ADSP-BF536/ADSP-BF537
Asynchronous Memory Write Cycle Timing
Table 25. Asynchronous Memory Write Cycle Timing
Parameter
Min
Max
Unit
Timing Requirements
tSARDY
tHARDY
ARDY Setup Before CLKOUT
ARDY Hold After CLKOUT
4.0
0.0
ns
ns
Switching Characteristics
tDDAT
tENDAT
tDO
DATA15–0 Disable After CLKOUT
6.0
6.0
ns
ns
ns
ns
DATA15–0 Enable After CLKOUT
Output Delay After CLKOUT1
Output Hold After CLKOUT 1
1.0
0.8
tHO
1 Output pins include AMS3–0, ABE1–0, ADDR19–1, AOE, AWE.
PROGRAMMED
WRITE
ACCESS
2 CYCLES
ACCESS
EXTEND HOLD
1 CYCLE 1 CYCLE
SETUP
2 CYCLES
CLKOUT
AMSx
tDO
tHO
ABE1–0
ADDR19–1
tDO
tHO
AWE
ARDY
tSARDY
tHARDY
tENDAT
tHARDY
tDDAT
tSARDY
DATA 15–0
Figure 12. Asynchronous Memory Write Cycle Timing
Rev. J
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February 2014
ADSP-BF534/ADSP-BF536/ADSP-BF537
External Port Bus Request and Grant Cycle Timing
Table 26 and Figure 13 describe external port bus request and
bus grant operations.
Table 26. External Port Bus Request and Grant Cycle Timing
Parameter1, 2
Min
Max
Unit
Timing Requirements
tBS
BR Asserted to CLKOUT Low Setup
4.6
0.0
ns
ns
tBH
CLKOUT Low to BR Deasserted Hold Time
Switching Characteristics
tSD
CLKOUT Low to AMSx, Address, and ARE/AWE Disable
4.5
4.5
3.6
3.6
3.6
3.6
ns
ns
ns
ns
ns
ns
tSE
CLKOUT Low to AMSx, Address, and ARE/AWE Enable
CLKOUT High to BG Asserted Setup
tDBG
tEBG
tDBH
tEBH
CLKOUT High to BG Deasserted Hold Time
CLKOUT High to BGH Asserted Setup
CLKOUT High to BGH Deasserted Hold Time
1 These timing parameters are based on worst-case operating conditions.
2 The pad loads for these timing parameters are 20 pF.
CLKOUT
tBH
tBS
BR
tSD
tSE
AMSx
tSD
tSE
ADDR 19-1
ABE1-0
tSD
tSE
AWE
ARE
tDBG
tEBG
BG
tDBH
tEBH
BGH
Figure 13. External Port Bus Request and Grant Cycle Timing
Rev. J
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Page 33 of 68
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February 2014
ADSP-BF534/ADSP-BF536/ADSP-BF537
SDRAM Interface Timing
Table 27. SDRAM Interface Timing
Parameter
Min
Max
Unit
Timing Requirements
tSSDAT
tHSDAT
DATA15–0 Setup Before CLKOUT
DATA15–0 Hold After CLKOUT
1.5
0.8
ns
ns
Switching Characteristics
tDCAD
tHCAD
tDSDAT
tENSDAT
COMMAND1, ADDR19–1, DATA15–0 Delay After CLKOUT
4.0
6.0
ns
ns
ns
ns
ns
ns
ns
ns
COMMAND1, ADDR19–1, DATA15–0 Hold After CLKOUT
DATA15–0 Disable After CLKOUT
DATA15–0 Enable After CLKOUT
CLKOUT Period when TJ +105°C
CLKOUT Period when TJ +105°C
CLKOUT Width High
1.0
0.5
7.5
10
2
tSCLK
2
tSCLK
tSCLKH
2.5
2.5
tSCLKL
CLKOUT Width Low
1 Command pins include: SRAS, SCAS, SWE, SDQM, SMS, SA10, SCKE.
2 These limits are specific to the SDRAM interface only. In addition, CLKOUT must always comply with the limits in Table 14 on Page 24.
tSCLK
CLKOUT
tSSDAT
tHSDAT
tSCLKL
tSCLKH
DATA (IN)
tDCAD
tDSDAT
tENSDAT
tHCAD
DATA (OUT)
tDCAD
tHCAD
COMMAND,
ADDRESS
(OUT)
NOTE: COMMAND = SRAS, SCAS, SWE, SDQM, SMS, SA10, SCKE.
Figure 14. SDRAM Interface Timing
Rev. J
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Page 34 of 68
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February 2014
ADSP-BF534/ADSP-BF536/ADSP-BF537
External DMA Request Timing
Table 28 and Figure 15 describe the external DMA request
operations.
Table 28. External DMA Request Timing
Parameter
Min
Max
Unit
Timing Requirements
tDS
DMARx Asserted to CLKOUT High Setup
CLKOUT High to DMARx Deasserted Hold Time
DMARx Active Pulse Width
6.0
ns
ns
ns
ns
tDH
0.0
tDMARACT
tDMARINACT
1.0 × tSCLK
1.75 × tSCLK
DMARx Inactive Pulse Width
CLKOUT
tDS
tDH
DMAR0/1
(ACTIVE LOW)
tDMARACT
tDMARINACT
DMAR0/1
(ACTIVE HIGH)
Figure 15. External DMA Request Timing
Rev. J
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Page 35 of 68
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February 2014
ADSP-BF534/ADSP-BF536/ADSP-BF537
Parallel Peripheral Interface Timing
Table 29 and Figure 16 on Page 36, Figure 20 on Page 39, and
Figure 23 on Page 41 describe parallel peripheral interface
operations.
Table 29. Parallel Peripheral Interface Timing
Parameter
Min
Max
Unit
Timing Requirements
tPCLKW
tPCLK
PPI_CLK Width1
PPI_CLK Period1
6.0
ns
ns
15.0
Timing Requirements—GP Input and Frame Capture Modes
tSFSPE
tHFSPE
tSDRPE
tHDRPE
External Frame Sync Setup Before PPI_CLK
External Frame Sync Hold After PPI_CLK
Receive Data Setup Before PPI_CLK
Receive Data Hold After PPI_CLK
6.7
1.0
3.5
1.5
ns
ns
ns
ns
Switching Characteristics—GP Output and Frame Capture Modes
tDFSPE
tHOFSPE
tDDTPE
tHDTPE
Internal Frame Sync Delay After PPI_CLK
Internal Frame Sync Hold After PPI_CLK
Transmit Data Delay After PPI_CLK
Transmit Data Hold After PPI_CLK
8.0
8.0
ns
ns
ns
ns
1.7
1.8
1 PPI_CLK frequency cannot exceed fSCLK/2.
FRAME SYNC
DRIVEN
DATA
SAMPLED
PPI_CLK
PPI_FS1/2
PPI_DATA
tDFSPE
tPCLKW
tHOFSPE
tPCLK
tSDRPE
tHDRPE
Figure 16. PPI GP Rx Mode with Internal Frame Sync Timing
DATA SAMPLED /
FRAME SYNC SAMPLED
DATA SAMPLED /
FRAME SYNC SAMPLED
PPI_CLK
tPCLKW
tSFSPE
tHFSPE
tPCLK
PPI_FS1/2
PPI_DATA
tSDRPE
tHDRPE
Figure 17. PPI GP Rx Mode with External Frame Sync Timing
Rev. J
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Page 36 of 68
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February 2014
ADSP-BF534/ADSP-BF536/ADSP-BF537
FRAME SYNC
DRIVEN
DATA
DRIVEN
tPCLK
DATA
DRIVEN
PPI_CLK
PPI_FS1/2
PPI_DATA
tDFSPE
tPCLKW
tHOFSPE
tDDTPE
tHDTPE
Figure 18. PPI GP Tx Mode with Internal Frame Sync Timing
DATA DRIVEN /
FRAME SYNC SAMPLED
PPI_CLK
PPI_FS1/2
PPI_DATA
tSFSPE
tHFSPE
tPCLKW
tPCLK
tDDTPE
tHDTPE
Figure 19. PPI GP Tx Mode with External Frame Sync Timing
Rev. J
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Page 37 of 68
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February 2014
ADSP-BF534/ADSP-BF536/ADSP-BF537
Serial Port Timing
Table 30 through Table 33 on Page 41 and Figure 20 on Page 39
through Figure 23 on Page 41 describe serial port operations.
Table 30. Serial Ports—External Clock
Parameter
Min
Max
Unit
Timing Requirements
tSFSE
TFSx/RFSx Setup Before TSCLKx/RSCLKx1
TFSx/RFSx Hold After TSCLKx/RSCLKx1
Receive Data Setup Before RSCLKx1
Receive Data Hold After RSCLKx1
3.0
ns
ns
ns
ns
ns
ns
ns
ns
tHFSE
3.0
tSDRE
3.0
tHDRE
tSCLKEW
tSCLKE
tSUDTE
tSUDRE
3.0
TSCLKx/RSCLKx Width
4.5
TSCLKx/RSCLKx Period
15.0
Start-Up Delay From SPORT Enable To First External TFSx2
Start-Up Delay From SPORT Enable To First External RFSx2
4.0 × tSCLKE
4.0 × tSCLKE
Switching Characteristics
tDFSE
tHOFSE
tDDTE
tHDTE
TFSx/RFSx Delay After TSCLKx/RSCLK (Internally Generated TFSx/RFSx)3
TFSx/RFSx Hold After TSCLKx/RSCLK (Internally Generated TFSx/RFSx)2
Transmit Data Delay After TSCLKx2
10.0
10.0
ns
ns
ns
ns
0
0
Transmit Data Hold After TSCLKx2
1 Referenced to sample edge.
2 Verified in design but untested. After being enabled, the serial port requires external clock pulses—before the first external frame sync edge—to initialize the serial port.
3 Referenced to drive edge.
Table 31. Serial Ports—Internal Clock
2.25 V VDDEXT < 2.70 V
or
0.80 V VDDINT < 0.95 V1
2.70 V VDDEXT 3.60 V
and
0.95 V VDDINT 1.43 V2, 3
Parameter
Min
Max
Min
Max
Unit
Timing Requirements
tSFSI
tHFSI
tSDRI
tHDRI
TFSx/RFSx Setup Before TSCLKx/RSCLKx4
8.5
8.0
ns
ns
ns
ns
TFSx/RFSx Hold After TSCLKx/RSCLKx4
Receive Data Setup Before RSCLKx4
Receive Data Hold After RSCLKx4
–1.5
8.5
–1.5
8.0
–1.5
–1.5
Switching Characteristics
tDFSI
TFSx/RFSx Delay After TSCLKx/RSCLKx (Internally Generated
TFSx/RFSx)5
3.0
3.0
3.0
3.0
ns
ns
tHOFSI
TFSx/RFSx Hold After TSCLKx/RSCLKx (Internally Generated 1.0
1.0
TFSx/RFSx)5
tDDTI
Transmit Data Delay After TSCLKx5
Transmit Data Hold After TSCLKx5
ns
ns
ns
tHDTI
1.0
4.5
1.0
4.5
tSCLKIW
TSCLKx/RSCLKx Width
1 Applies to all nonautomotive-grade devices when operated within either of these voltage ranges.
2 Applies to all nonautomotive-grade devices when operated within these voltage ranges.
3 All automotive-grade devices are within these specifications.
4 Referenced to sample edge.
5 Referenced to drive edge.
Rev. J
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Page 38 of 68
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February 2014
ADSP-BF534/ADSP-BF536/ADSP-BF537
DATA RECEIVE—INTERNAL CLOCK
DATA RECEIVE—EXTERNAL CLOCK
DRIVE EDGE
SAMPLE EDGE
DRIVE EDGE
SAMPLE EDGE
tSCLKE
tSCLKIW
tSCLKEW
RSCLKx
RSCLKx
tDFSI
tDFSE
tHOFSI
tHOFSE
RFSx
RFSx
(OUTPUT)
(OUTPUT)
tSFSI
tHFSI
tSFSE
tHFSE
RFSx
RFSx
(INPUT)
(INPUT)
tHDRE
tSDRI
tHDRI
tSDRE
DRx
DRx
DATA TRANSMIT—INTERNAL CLOCK
DRIVE EDGE
DATA TRANSMIT—EXTERNAL CLOCK
DRIVE EDGE SAMPLE EDGE
SAMPLE EDGE
tSCLKE
tSCLKIW
tSCLKEW
TSCLKx
TSCLKx
tDFSI
tDFSE
tHOFSI
tHOFSE
TFSx
TFSx
(OUTPUT)
(OUTPUT)
tSFSI
tHFSI
tSFSE
tHFSE
TFSx
TFSx
(INPUT)
(INPUT)
tDDTI
tDDTE
tHDTI
tHDTE
DTx
DTx
Figure 20. Serial Ports
TSCLKx
(INPUT)
tSUDTE
TFSx
(INPUT)
RSCLKx
(INPUT)
tSUDRE
RFSx
(INPUT)
FIRST
TSCLKx/RSCLKx
EDGE AFTER
SPORT ENABLED
Figure 21. Serial Port Start Up with External Clock and Frame Sync
Rev. J
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Page 39 of 68
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February 2014
ADSP-BF534/ADSP-BF536/ADSP-BF537
Table 32. Serial Ports—Enable and Three-State
Parameter
Min
0
Max
Unit
Switching Characteristics
tDTENE
tDDTTE
tDTENI
tDDTTI
Data Enable Delay from External TSCLKx1
Data Disable Delay from External TSCLKx1, 2
Data Enable Delay from Internal TSCLKx1
Data Disable Delay from Internal TSCLKx1, 2
ns
ns
ns
ns
10.0
3.0
–2.0
1 Referenced to drive edge.
2 Applicable to multichannel mode only. TSCLKx is tied to RSCLKx.
DRIVE EDGE
TSCLKx
DRIVE EDGE
tDTENE/I
tDDTTE/I
DTx
Figure 22. Enable and Three-State
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ADSP-BF534/ADSP-BF536/ADSP-BF537
Table 33. External Late Frame Sync
Parameter
Min
Max
Unit
Switching Characteristics
tDDTLFSE
tDTENLFS
Data Delay from Late External TFSx or External RFSx with MCMEN = 1, MFD = 01, 2
Data Enable from Late FS or MCMEN = 1, MFD = 01, 2
10.0
ns
ns
0
1 MCMEN = 1, TFSx enable and TFSx valid follow tDDTENFS and tDDTLFS
.
2 If external RFSx/TFSx setup to RSCLKx/TSCLKx > tSCLKE/2, then tDDTE/I and tDTENE/I apply, otherwise tDDTLFSE and tDTENLFS apply.
EXTERNAL RFSx IN MULTI-CHANNEL MODE
DRIVE
EDGE
SAMPLE
EDGE
DRIVE
EDGE
RSCLKx
RFSx
tDDTLFSE
tDTENLFSE
DTx
1ST BIT
LATE EXTERNAL TFSx
DRIVE
EDGE
SAMPLE
EDGE
DRIVE
EDGE
TSCLKx
TFSx
tDDTLFSE
DTx
1ST BIT
Figure 23. External Late Frame Sync
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February 2014
ADSP-BF534/ADSP-BF536/ADSP-BF537
Serial Peripheral Interface Port—Master Timing
Table 34 and Figure 24 describe SPI port master operations.
Table 34. Serial Peripheral Interface (SPI) Port—Master Timing
2.25 V VDDEXT 2.70 V
2.70 V VDDEXT 3.60 V
and
0.95 V VDDINT 1.43 V2, 3
or
0.80 V VDDINT 0.95 V1
Parameter
Min
Max
Min
Max
Unit
Timing Requirements
tSSPIDM
tHSPIDM
Switching Characteristics
Data Input Valid to SCK Edge (Data Input Setup)
8.7
7.5
ns
ns
SCK Sampling Edge to Data Input Invalid
–1.5
–1.5
tSDSCIM
tSPICHM
tSPICLM
tSPICLK
SPISELx Low to First SCK Edge
2 × tSCLK –1.5
2 × tSCLK –1.5
2 × tSCLK –1.5
4 × tSCLK –1.5
2 × tSCLK –1.5
2 × tSCLK –1.5
2 × tSCLK –1.5
2 × tSCLK –1.5
2 × tSCLK –1.5
4 × tSCLK –1.5
2 × tSCLK –1.5
2 × tSCLK –1.5
ns
ns
ns
ns
ns
ns
ns
ns
Serial Clock High Period
Serial Clock Low Period
Serial Clock Period
tHDSM
Last SCK Edge to SPISELx High
Sequential Transfer Delay
tSPITDM
tDDSPIDM
tHDSPIDM
SCK Edge to Data Out Valid (Data Out Delay)
6
6
SCK Edge to Data Out Invalid (Data Out Hold)
–1.0
–1.0
1 Applies to all nonautomotive-grade devices when operated within either of these voltage ranges.
2 Applies to all nonautomotive-grade devices when operated within these voltage ranges.
3 All automotive-grade devices are within these specifications.
SPIxSELy
(OUTPUT)
tSDSCIM
tSPICLM
tSPICHM
tSPICLK
tHDSM
tSPITDM
SPIxSCK
(OUTPUT)
tHDSPIDM
tDDSPIDM
SPIxMOSI
(OUTPUT)
tSSPIDM
CPHA = 1
tHSPIDM
SPIxMISO
(INPUT)
tHDSPIDM
tDDSPIDM
SPIxMOSI
(OUTPUT)
tSSPIDM
tHSPIDM
CPHA = 0
SPIxMISO
(INPUT)
Figure 24. Serial Peripheral Interface (SPI) Port—Master Timing
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February 2014
ADSP-BF534/ADSP-BF536/ADSP-BF537
Serial Peripheral Interface Port—Slave Timing
Table 35 and Figure 25 describe SPI port slave operations.
Table 35. Serial Peripheral Interface (SPI) Port—Slave Timing
Parameter
Min
Max
Unit
Timing Requirements
tSPICHS
tSPICLS
tSPICLK
tHDS
Serial Clock High Period
2 × tSCLK –1.5
2 × tSCLK –1.5
4 × tSCLK
ns
ns
ns
ns
ns
ns
ns
ns
Serial Clock Low Period
Serial Clock Period
Last SCK Edge to SPISS Not Asserted
Sequential Transfer Delay
2 × tSCLK –1.5
2 × tSCLK –1.5
2 × tSCLK –1.5
1.6
tSPITDS
tSDSCI
tSSPID
tHSPID
SPISS Assertion to First SCK Edge
Data Input Valid to SCK Edge (Data Input Setup)
SCK Sampling Edge to Data Input Invalid
1.6
Switching Characteristics
tDSOE
SPISS Assertion to Data Out Active
0
0
8
ns
ns
ns
ns
tDSDHI
tDDSPID
tHDSPID
SPISS Deassertion to Data High Impedance
SCK Edge to Data Out Valid (Data Out Delay)
SCK Edge to Data Out Invalid (Data Out Hold)
8
10
0
SPIxSS
(INPUT)
tSDSCI
tSPICLS
tSPICHS
tSPICLK
tHDS
tSPITDS
SPIxSCK
(INPUT)
tDSOE
tDDSPID
tHDSPID
tDDSPID
tDSDHI
SPIxMISO
(OUTPUT)
CPHA = 1
tSSPID
tHSPID
SPIxMOSI
(INPUT)
tDSOE
tHDSPID
tDDSPID
tDSDHI
SPIxMISO
(OUTPUT)
tHSPID
CPHA = 0
tSSPID
SPIxMOSI
(INPUT)
Figure 25. Serial Peripheral Interface (SPI) Port—Slave Timing
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February 2014
ADSP-BF534/ADSP-BF536/ADSP-BF537
General-Purpose Port Timing
Table 36 and Figure 26 describe general-purpose
port operations.
Table 36. General-Purpose Port Timing
Parameter
Min
tSCLK + 1
0
Max
Unit
ns
Timing Requirement
tWFI
Switching Characteristic
tGPOD General-Purpose Port Pin Output Delay from CLKOUT Low
General-Purpose Port Pin Input Pulse Width
6
ns
CLKOUT
GPIO OUTPUT
GPIO INPUT
tGPOD
tWFI
Figure 26. General-Purpose Port Timing
Universal Asynchronous Receiver-Transmitter
(UART) Ports—Receive and Transmit Timing
For information on the UART port receive and transmit opera-
tions, see the ADSP-BF537 Blackfin Processor Hardware
Reference.
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February 2014
ADSP-BF534/ADSP-BF536/ADSP-BF537
Timer Clock Timing
Table 37 and Figure 27 describe timer clock timing.
Table 37. Timer Clock Timing
Parameter
Min
Max
Unit
Switching Characteristic
tTODP
Timer Output Update Delay After PPI_CLK High
12
ns
PPI_CLK
tTODP
TMRx OUTPUT
Figure 27. Timer Clock Timing
Timer Cycle Timing
Table 38 and Figure 28 describe timer expired operations. The
input signal is asynchronous in “width capture mode” and
“external clock mode” and has an absolute maximum input fre-
quency of (fSCLK/2) MHz.
Table 38. Timer Cycle Timing
2.25 V VDDEXT 2.70 V
or
0.80 V VDDINT 0.95 V1
2.70 V VDDEXT 3.60 V
and
0.95 V VDDINT 1.43 V2, 3
Parameter
Min
Max
Min
Max
Unit
Timing Characteristics
tWL
tWH
tTIS
tTIH
Timer Pulse Width Input Low (Measured In SCLK Cycles)4
Timer Pulse Width Input High (Measured In SCLK Cycles)4 1 × tSCLK
1 × tSCLK
1 × tSCLK
1 × tSCLK
5.0
ns
ns
ns
ns
Timer Input Setup Time Before CLKOUT Low5
Timer Input Hold Time After CLKOUT Low5
5.5
1.5
1.5
Switching Characteristics
tHTO Timer Pulse Width Output (Measured In SCLK Cycles)
tTOD Timer Output Update Delay After CLKOUT High
1 × tSCLK
(232–1) × tSCLK 1 × tSCLK
6.5
(232–1) × tSCLK ns
6.0 ns
1 Applies to all nonautomotive-grade devices when operated within either of these voltage ranges.
2 Applies to all nonautomotive-grade devices when operated within these voltage ranges.
3 All automotive-grade devices are within these specifications.
4 The minimum pulse widths apply for TMRx signals in width capture and external clock modes. They also apply to the PF15 or PPI_CLK signals in PWM output mode.
5 Either a valid setup and hold time or a valid pulse width is sufficient. There is no need to resynchronize programmable flag inputs.
CLKOUT
tTOD
TMRx OUTPUT
tTIS
tTIH
tHTO
TMRx INPUT
tWH,tWL
Figure 28. Timer Cycle Timing
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February 2014
ADSP-BF534/ADSP-BF536/ADSP-BF537
JTAG Test and Emulation Port Timing
Table 39 and Figure 29 describe JTAG port operations.
Table 39. JTAG Port Timing
Parameter
Min
Max
Unit
Timing Parameters
tTCK
TCK Period
20
4
ns
tSTAP
tHTAP
tSSYS
tHSYS
tTRSTW
TDI, TMS Setup Before TCK High
TDI, TMS Hold After TCK High
System Inputs Setup Before TCK High1
System Inputs Hold After TCK High1
TRST Pulse Width2 (Measured in TCK Cycles)
ns
4
ns
4
ns
5
ns
4
TCK
Switching Characteristics
tDTDO TDO Delay From TCK Low
tDSYS
System Outputs Delay After TCK Low3
10
12
ns
ns
0
1 System Inputs = DATA15–0, BR, ARDY, SCL, SDA, TFS0, TSCLK0, RSCLK0, RFS0, DR0PRI, DR0SEC, PF15–0, PG15–0, PH15–0, MDIO, TCK, TRST, RESET, NMI, RTXI,
BMODE2–0.
2 50 MHz maximum.
3 System Outputs = DATA15–0, ADDR19–1, ABE1–0, BG, BGH, AOE, ARE, AWE, AMS3–0, SRAS, SCAS, SWE, SCKE, CLKOUT, SA10, SMS, SCL, SDA, MDC, MDIO,
TSCLK0, TFS0, RFS0, RSCLK0, DT0PRI, DT0SEC, PF15–0, PG15–0, PH15–0, RTXO, TDO, EMU, XTAL, VROUT1–0.
tTCK
TCK
tSTAP
tHTAP
TMS
TDI
tDTDO
TDO
tSSYS
tHSYS
SYSTEM
INPUTS
tDSYS
SYSTEM
OUTPUTS
Figure 29. JTAG Port Timing
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February 2014
ADSP-BF534/ADSP-BF536/ADSP-BF537
10/100 Ethernet MAC Controller Timing
Table 40 through Table 45 and Figure 30 through Figure 35
describe the 10/100 Ethernet MAC controller operations. This
feature is only available on the ADSP-BF536 and ADSP-BF537
processors.
Table 40. 10/100 Ethernet MAC Controller Timing: MII Receive Signal
Parameter1
Min
Max
Unit
fERXCLK
ERxCLK Frequency (fSCLK = SCLK Frequency)
None
25 + 1%
MHz
fSCLK + 1%
tERXCLKW
tERXCLKIS
tERXCLKIH
ERxCLK Width (tERxCLK = ERxCLK Period)
tERxCLK × 35%
tERxCLK × 65%
ns
ns
ns
Rx Input Valid to ERxCLK Rising Edge (Data In Setup)
7.5
7.5
ERxCLK Rising Edge to Rx Input Invalid (Data In Hold)
1 MII inputs synchronous to ERxCLK are ERxD3–0, ERxDV, and ERxER.
Table 41. 10/100 Ethernet MAC Controller Timing: MII Transmit Signal
Parameter1
Min
Max
Unit
fETXCLK
ETxCLK Frequency (fSCLK = SCLK Frequency)
None
25 + 1%
MHz
fSCLK + 1%
tETXCLKW
tETXCLKOV
tETXCLKOH
ETxCLK Width (tETXCLK = ETxCLK Period)
tETxCLK × 35%
0
tETxCLK × 65%
20
ns
ns
ns
ETxCLK Rising Edge to Tx Output Valid (Data Out Valid)
ETxCLK Rising Edge to Tx Output Invalid (Data Out Hold)
1 MII outputs synchronous to ETxCLK are ETxD3–0.
Table 42. 10/100 Ethernet MAC Controller Timing: RMII Receive Signal
Parameter1
Min
Max
Unit
fREFCLK
REF_CLK Frequency (fSCLK = SCLK Frequency)
None
50 + 1%
MHz
2 × fSCLK + 1%
tREFCLKW
tREFCLKIS
tREFCLKIH
REF_CLK Width (tREFCLK = REFCLK Period)
tREFCLK × 35%
tREFCLK × 65%
ns
ns
ns
Rx Input Valid to RMII REF_CLK Rising Edge (Data In Setup)
4
2
RMII REF_CLK Rising Edge to Rx Input Invalid (Data In Hold)
1 RMII inputs synchronous to RMII REF_CLK are ERxD1–0, RMII CRS_DV, and ERxER.
Table 43. 10/100 Ethernet MAC Controller Timing: RMII Transmit Signal
Parameter1
Min
Max
Unit
ns
tREFCLKOV
RMII REF_CLK Rising Edge to Tx Output Valid (Data Out Valid)
RMII REF_CLK Rising Edge to Tx Output Invalid (Data Out Hold)
7.5
tREFCLKOH
2
ns
1 RMII outputs synchronous to RMII REF_CLK are ETxD1–0.
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ADSP-BF534/ADSP-BF536/ADSP-BF537
Table 44. 10/100 Ethernet MAC Controller Timing: MII/RMII Asynchronous Signal
Parameter1, 2
Min
Max
Unit
tECOLH
COL Pulse Width High
COL Pulse Width Low
tETxCLK × 1.5
tERxCLK × 1.5
ns
ns
tECOLL
tETxCLK × 1.5
tERxCLK × 1.5
ns
ns
tECRSH
tECRSL
CRS Pulse Width High
CRS Pulse Width Low
tETxCLK × 1.5
ns
tETxCLK × 1.5
ns
1 MII/RMII asynchronous signals are COL, CRS. These signals are applicable in both MII and RMII modes. The asynchronous COL input is synchronized separately to both
the ETxCLK and the ERxCLK, and must have a minimum pulse width high or low at least 1.5 times the period of the slower of the two clocks.
2 The asynchronous CRS input is synchronized to the ETxCLK, and must have a minimum pulse width high or low at least 1.5 times the period of ETxCLK.
Table 45. 10/100 Ethernet MAC Controller Timing: MII Station Management
Parameter1
tMDIOS
Min
10
Max
Unit
ns
MDIO Input Valid to MDC Rising Edge (Setup)
MDC Rising Edge to MDIO Input Invalid (Hold)
MDC Falling Edge to MDIO Output Valid
tMDCIH
10
ns
tMDCOV
25
ns
tMDCOH
MDC Falling Edge to MDIO Output Invalid (Hold)
–1
ns
1 MDC/MDIO is a 2-wire serial bidirectional port for controlling one or more external PHYs. MDC is an output clock whose minimum period is programmable as a multiple
of the system clock SCLK. MDIO is a bidirectional data line.
tERXCLK
tERXCLKW
ERx_CLK
ERxD3–0
ERxDV
ERxER
tERXCLKIS tERXCLKIH
Figure 30. 10/100 Ethernet MAC Controller Timing: MII Receive Signal
tETXCLK
MIITxCLK
tETXCLKW
tETXCLKOH
ETxD3–0
ETxEN
tETXCLKOV
Figure 31. 10/100 Ethernet MAC Controller Timing: MII Transmit Signal
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February 2014
ADSP-BF534/ADSP-BF536/ADSP-BF537
tREFCLK
tREFCLKW
RMII_REF_CLK
ERxD1–0
ERxDV
ERxER
tREFCLKIS tREFCLKIH
Figure 32. 10/100 Ethernet MAC Controller Timing: RMII Receive Signal
tREFCLK
RMII_REF_CLK
tREFCLKOH
ETxD1–0
ETxEN
tREFCLKOV
Figure 33. 10/100 Ethernet MAC Controller Timing: RMII Transmit Signal
MIICRS, COL
tECRSH
tECOLH
tECRSL
tECOLL
Figure 34. 10/100 Ethernet MAC Controller Timing: Asynchronous Signal
MDC (OUTPUT)
MDIO (OUTPUT)
tMDCOH
tMDCOV
MDIO (INPUT)
tMDIOS
tMDCIH
Figure 35. 10/100 Ethernet MAC Controller Timing: MII Station Management
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February 2014
ADSP-BF534/ADSP-BF536/ADSP-BF537
OUTPUT DRIVE CURRENTS
Figure 36 through Figure 47 show typical current-voltage char-
acteristics for the output drivers of the processors. The curves
represent the current drive capability of the output drivers as a
function of output voltage. See Table 9 on Page 19 for informa-
tion about which driver type corresponds to a particular pin.
200
150
V
V
V
= 3.0V @ 95°C
= 3.3V @ 25°C
DDEXT
DDEXT
= 3.6V @ -40°C
DDEXT
100
50
V
OH
120
V
V
V
= 2.25V @ 95°C
= 2.50V @ 25°C
DDEXT
DDEXT
DDEXT
100
80
0
= 2.75V @ -40°C
-
50
100
150
200
60
V
40
20
OH
-
V
OL
-
0
- 20
- 40
-
4.0
3.0
4.0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
V
OL
SOURCE VOLTAGE (V)
- 60
- 80
Figure 39. Drive Current B (High VDDEXT
)
- 100
3.0
0
0.5
1.0
1.5
2.0
2.5
80
60
SOURCE VOLTAGE (V)
V
= 2.25V @ 95°C
= 2.50V @ 25°C
DDEXT
DDEXT
Figure 36. Drive Current A (Low VDDEXT
)
V
V
= 2.75V @ -40°C
DDEXT
150
100
50
40
20
0
V
V
V
= 3.0V @ 95°C
= 3.3V @ 25°C
DDEXT
DDEXT
DDEXT
V
OH
= 3.6V @ -40°C
V
OH
-20
0
V
OL
-40
-
50
V
-60
OL
0
0.5
1.0
1.5
2.0
2.5
-
100
SOURCE VOLTAGE (V)
-
150
Figure 40. Drive Current C (Low VDDEXT
)
4.0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
SOURCE VOLTAGE (V)
Figure 37. Drive Current A (High VDDEXT
)
100
80
V
V
V
= 3.0V @ 95°C
= 3.3V @ 25°C
DDEXT
DDEXT
150
100
V
= 2.25V @ 95°C
= 2.50V @ 25°C
DDEXT
= 3.6V @ -40°C
DDEXT
60
V
DDEXT
V
= 2.75V @ -40°C
DDEXT
40
V
OH
50
0
20
0
V
OH
-
20
40
60
80
-
50
-
V
OL
V
OL
-
-
100
-
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
-150
SOURCE VOLTAGE (V)
0
0.5
1.0
1.5
2.0
2.5
3.0
SOURCE VOLTAGE (V)
Figure 41. Drive Current C (High VDDEXT
)
Figure 38. Drive Current B (Low VDDEXT
)
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February 2014
ADSP-BF534/ADSP-BF536/ADSP-BF537
100
80
80
V
V
= 2.25V @ 95°C
= 2.50V @ 25°C
DDEXT
DDEXT
V
V
= 3.0V @ 95°C
= 3.3V @ 25°C
DDEXT
DDEXT
60
40
20
0
V
= 2.75V @ -40°C
DDEXT
60
V
= 3.6V @ -40°C
DDEXT
40
V
OH
V
20
0
OH
-
20
40
60
80
-
20
40
60
80
-
-
V
OL
V
OL
-
-
-
-
4.0
3.0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0
0.5
1.0
1.5
2.0
2.5
SOURCE VOLTAGE (V)
SOURCE VOLTAGE (V)
Figure 42. Drive Current D (Low VDDEXT
)
Figure 45. Drive Current E (High VDDEXT)
0
150
100
V
V
= 3.0V @ 95°C
= 3.3V @ 25°C
DDEXT
DDEXT
V
= 2.25V @ 95°C
= 2.50V @ 25°C
DDEXT
DDEXT
DDEXT
V
V
-
10
V
= 3.6V @ -40°C
DDEXT
= 2.75V @ -40°C
-
20
50
0
V
OH
-30
V
OL
-40
-50
V
OL
-50
-100
-150
-60
4.0
0
0.5
1.0
1.5
2.0
2.5
3.0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
SOURCE VOLTAGE (V)
SOURCE VOLTAGE (V)
Figure 43. Drive Current D (High VDDEXT
)
Figure 46. Drive Current F (Low VDDEXT)
0
10
20
30
40
50
60
70
80
50
40
30
20
10
0
V
V
V
= 2.25V @ 95°C
= 2.50V @ 25°C
V
V
= 3.0V @ 95°C
= 3.3V @ 25°C
DDEXT
DDEXT
DDEXT
DDEXT
DDEXT
-
= 2.75V @ -40°C
V
= 3.6V @ -40°C
DDEXT
-
V
-
OH
-
V
OL
-
10
20
30
40
50
-
-
-
-
V
OL
-
-
-
-
4.0
3.0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0.5
1.0
1.5
2.0
2.5
0
SOURCE VOLTAGE (V)
SOURCE VOLTAGE (V)
Figure 44. Drive Current E (Low VDDEXT
)
Figure 47. Drive Current F (High VDDEXT)
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February 2014
ADSP-BF534/ADSP-BF536/ADSP-BF537
Output Disable Time
TEST CONDITIONS
Output pins are considered to be disabled when they stop driv-
ing, go into a high impedance state, and start to decay from their
output high or low voltage. The time for the voltage on the bus
to decay by V is dependent on the capacitive load, CL, and the
load current, IL. This decay time can be approximated by
the equation:
All timing parameters appearing in this data sheet were
measured under the conditions described in this section.
Figure 48 shows the measurement point for ac measurements
(other than output enable/disable). The measurement point is
VMEAS = VDDEXT/2.
INPUT
OR
OUTPUT
tDECAY = CLV IL
V
V
MEAS
MEAS
The output disable time tDIS is the difference between tDIS_MEA-
SURED and tDECAY as shown in Figure 49. The time tDIS_MEASURED is
the interval from when the reference signal switches to when the
output voltage decays V from the measured output-high or
output-low voltage. The time tDECAY is calculated with the test
loads CL and IL, and with V equal to 0.5 V.
Figure 48. Voltage Reference Levels for AC Measurements (Except
Output Enable/Disable)
Output Enable Time
Output pins are considered to be enabled when they have made
a transition from a high impedance state to the point when they
start driving. The output enable time tENA is the interval from
the point when a reference signal reaches a high or low voltage
level to the point when the output starts driving as shown in the
Output Enable/Disable diagram (Figure 49). The time tENA_MEA-
SURED is the interval from when the reference signal switches to
when the output voltage reaches 2.0 V (output high) or 1.0 V
(output low). Time tTRIP is the interval from when the output
starts driving to when the output reaches the 1.0 V or 2.0 V trip
voltage. Time tENA is calculated as shown in
REFERENCE
SIGNAL
tDIS_MEASURED
tENA_MEASURED
tDIS
tENA
V
OH
V
(MEASURED)
OH
(MEASURED)
V
(MEASURED) ꢁ ꢂV
(MEASURED) + ꢂV
OH
V
(HIGH)
TRIP
V
(LOW)
V
V
TRIP
OL
V
OL
(MEASURED)
OL
(MEASURED)
tDECAY
tTRIP
the equation:
OUTPUT STOPS DRIVING
OUTPUT STARTS DRIVING
HIGH IMPEDANCE STATE
tENA = tENA_MEASURED – tTRIP
If multiple pins (such as the data bus) are enabled, the measure-
ment value is that of the first pin to start driving.
Figure 49. Output Enable/Disable
Example System Hold Time Calculation
To determine the data output hold time in a particular system,
first calculate tDECAY using the equation given above. Choose V
to be the difference between the processor’s output voltage and
the input threshold for the device requiring the hold time. A
typical V is 0.4 V. CL is the total bus capacitance (per data line),
and IL is the total leakage or three-state current (per data line).
The hold time is tDECAY plus the minimum disable time (for
example, tDSDAT for an SDRAM write cycle).
Rev. J
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Page 52 of 68
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February 2014
ADSP-BF534/ADSP-BF536/ADSP-BF537
Capacitive Loading
14
Output delays and holds are based on standard capacitive loads:
30 pF on all pins (see Figure 50). Figure 51 through Figure 60 on
Page 55 show how output rise time varies with capacitance. The
delay and hold specifications given should be derated by a factor
derived from these figures. The graphs in these figures may not
be linear outside the ranges shown.
12
RISE TIME
10
8
FALL TIME
6
4
TESTER PIN ELECTRONICS
50Ω
V
LOAD
T1
DUT
OUTPUT
2
0
45Ω
70Ω
0
50
100
150
200
250
LOAD CAPACITANCE (pF)
ZO = 50Ω (impedance)
TD = 4.04 1.18 ns
50Ω
0.5pF
4pF
Figure 51. Typical Output Delay or Hold for Driver A at VDDEXT Min
2pF
400Ω
12
10
NOTES:
RISE TIME
THE WORST CASE TRANSMISSION LINE DELAY IS SHOWN AND CAN BE USED
FOR THE OUTPUT TIMING ANALYSIS TO REFELECT THE TRANSMISSION LINE
EFFECT AND MUST BE CONSIDERED.THE TRANSMISSION LINE (TD) IS FOR
LOAD ONLY AND DOES NOT AFFECT THE DATA SHEET TIMING SPECIFICATIONS.
8
FALL TIME
6
4
2
0
ANALOG DEVICES RECOMMENDS USING THE IBIS MODEL TIMING FOR A GIVEN
SYSTEM REQUIREMENT. IF NECESSARY, A SYSTEM MAY INCORPORATE
EXTERNAL DRIVERS TO COMPENSATE FOR ANY TIMING DIFFERENCES.
Figure 50. Equivalent Device Loading for AC Measurements
(Includes All Fixtures)
0
50
100
150
200
250
LOAD CAPACITANCE (pF)
Figure 52. Typical Output Delay or Hold for Driver A at VDDEXT Max
Rev. J
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Page 53 of 68
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February 2014
ADSP-BF534/ADSP-BF536/ADSP-BF537
12
20
18
16
14
10
RISE TIME
RISE TIME
8
12
10
FALL TIME
FALL TIME
6
8
6
4
2
0
4
2
0
0
50
100
150
200
250
0
50
100
150
200
250
LOAD CAPACITANCE (pF)
LOAD CAPACITANCE (pF)
Figure 53. Typical Output Delay or Hold for Driver B at VDDEXT Min
Figure 56. Typical Output Delay or Hold for Driver C at VDDEXT Max
10
18
16
9
8
RISE TIME
7
14
RISE TIME
6
12
FALL TIME
5
4
3
2
1
0
10
FALL TIME
8
6
4
2
0
0
50
100
150
200
250
LOAD CAPACITANCE (pF)
0
50
100
150
200
250
LOAD CAPACITANCE (pF)
Figure 54. Typical Output Delay or Hold for Driver B at VDDEXT Max
Figure 57. Typical Output Delay or Hold for Driver D at VDDEXT Min
30
25
14
12
RISE TIME
20
RISE TIME
10
FALL TIME
15
8
FALL TIME
6
4
2
0
10
5
0
0
50
100
150
200
250
LOAD CAPACITANCE (pF)
0
50
100
150
200
250
LOAD CAPACITANCE (pF)
Figure 55. Typical Output Delay or Hold for Driver C at VDDEXT Min
Figure 58. Typical Output Delay or Hold for Driver D at VDDEXT Max
Rev. J
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Page 54 of 68
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February 2014
ADSP-BF534/ADSP-BF536/ADSP-BF537
36
36
32
32
28
28
RISE TIME
RISE TIME
24
20
24
20
16
12
8
FALL TIME
16
FALL TIME
12
8
4
0
4
0
0
50
100
150
200
250
0
50
100
150
200
250
LOAD CAPACITANCE (pF)
LOAD CAPACITANCE (pF)
Figure 59. Typical Output Delay or Hold for Driver E at VDDEXT Min
Figure 61. Typical Output Delay or Hold for Driver F at VDDEXT Min
36
32
36
32
28
28
RISE TIME
RISE TIME
24
20
24
20
16
16
FALL TIME
FALL TIME
12
12
8
4
0
8
4
0
0
50
100
150
200
250
0
50
100
150
200
250
LOAD CAPACITANCE (pF)
LOAD CAPACITANCE (pF)
Figure 62. Typical Output Delay or Hold for Driver F at VDDEXT Max
Figure 60. Typical Output Delay or Hold for Driver E at VDDEXT Max
Rev. J
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Page 55 of 68
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February 2014
ADSP-BF534/ADSP-BF536/ADSP-BF537
Table 46. Thermal Characteristics (182-Ball BGA)
THERMAL CHARACTERISTICS
To determine the junction temperature on the application
printed circuit board use:
Parameter Condition Typical Unit
JA
0 Linear m/s Airflow
32.80
29.30
28.00
20.10
7.92
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
JMA
JMA
JB
1 Linear m/s Airflow
2 Linear m/s Airflow
TJ = TCASE + JT PD
where:
JC
TJ = Junction temperature (°C)
JT
JT
JT
0 Linear m/s Airflow
1 Linear m/s Airflow
2 Linear m/s Airflow
0.19
T
CASE = Case temperature (°C) measured by customer at top
0.35
center of package.
0.45
JT = From Table 46
Table 47. Thermal Characteristics (208-Ball BGA without
Thermal Vias in PCB)
PD = Power dissipation (see the power dissipation discussion
and the tables on Page 27 for the method to calculate PD).
Values of JA are provided for package comparison and printed
circuit board design considerations. JA can be used for a first
order approximation of TJ by the equation:
Parameter Condition
Typical Unit
JA
0 Linear m/s Airflow
23.30
20.20
19.20
13.05
6.92
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
JMA
JMA
JB
1 Linear m/s Airflow
2 Linear m/s Airflow
TJ = TA + JA PD
JC
where:
JT
JT
JT
0 Linear m/s Airflow
1 Linear m/s Airflow
2 Linear m/s Airflow
0.18
TA = Ambient temperature (°C)
0.27
0.32
Values of JC are provided for package comparison and printed
circuit board design considerations when an external heat sink
is required. Values of JB are provided for package comparison
and printed circuit board design considerations.
Table 48. Thermal Characteristics (208-Ball BGA with
Thermal Vias in PCB)
In Table 46 through Table 48, airflow measurements comply
with JEDEC standards JESD51-2 and JESD51-6, and the junc-
tion-to-board measurement complies with JESD51-8. Test
board and thermal via design comply with JEDEC standards
JESD51-9 (BGA). The junction-to-case measurement complies
with MIL-STD-883 (Method 1012.1). All measurements use a
2S2P JEDEC test board.
Parameter Condition
Typical Unit
JA
0 Linear m/s Airflow
22.60
19.40
18.40
13.20
6.85
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
JMA
JMA
JB
1 Linear m/s Airflow
2 Linear m/s Airflow
JC
Industrial applications using the 208-ball BGA package require
thermal vias, to an embedded ground plane, in the PCB. Refer to
JEDEC standard JESD51-9 for printed circuit board thermal
ball land and thermal via design information.
JT
JT
JT
0 Linear m/s Airflow
1 Linear m/s Airflow
2 Linear m/s Airflow
0.16
0.27
0.32
Rev. J
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Page 56 of 68
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February 2014
ADSP-BF534/ADSP-BF536/ADSP-BF537
182-BALL CSP_BGA BALL ASSIGNMENT
Table 49 lists the CSP_BGA ball assignment by signal mne-
monic. Table 50 on Page 58 lists the CSP_BGA ball assignment
by ball number.
Table 49. 182-Ball CSP_BGA Ball Assignment (Alphabetically by Signal Mnemonic)
Mnemonic Ball No.
Mnemonic Ball No.
Mnemonic Ball No.
Mnemonic Ball No.
Mnemonic Ball No.
ABE0
H13
H12
J14
CLKOUT
DATA0
DATA1
DATA10
DATA11
DATA12
DATA13
DATA14
DATA15
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
DATA8
DATA9
EMU
B14
M9
N9
N6
P6
GND
GND
GND
GND
GND
GND
NMI
PF0
L6
PG8
PG9
PH0
PH1
PH10
PH11
PH12
PH13
PH14
PH15
PH2
PH3
PH4
PH5
PH6
PH7
PH8
PH9
PJ0
E3
SRAS
SWE
D13
D12
P2
ABE1
L8
E4
ADDR1
ADDR10
ADDR11
ADDR12
ADDR13
ADDR14
ADDR15
ADDR16
ADDR17
ADDR18
ADDR19
ADDR2
ADDR3
ADDR4
ADDR5
ADDR6
ADDR7
ADDR8
ADDR9
AMS0
L10
M4
M10
P14
B10
M1
L1
C2
TCK
M13
M14
N14
N13
N12
M11
N11
P13
P12
P11
K14
L14
J13
C3
TDI
M3
N3
B6
TDO
M5
N5
P5
A2
A3
A4
A5
A6
C4
TMS
N2
TRST
N1
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDRTC
VROUT0
VROUT1
XTAL
A1
P4
PF1
C12
E6
P9
PF10
PF11
PF12
PF13
PF14
PF15
PF2
J2
M8
N8
P8
J3
E11
F4
H1
H2
H3
H4
L2
C5
C6
F12
H5
M7
N7
P7
B1
B2
H10
J11
J12
K7
B3
K13
L13
K12
L12
M12
E14
F14
F13
G12
G13
E13
G14
H14
P10
N10
N4
M6
M2
A10
A14
D4
E7
PF3
L3
B4
PF4
L4
B5
GND
PF5
K1
K2
K3
K4
J1
C7
K9
GND
PF6
PJ1
B7
L7
GND
PF7
PJ10
PJ11
PJ2
D10
D11
B11
C11
D7
D8
C8
L9
GND
PF8
L11
P1
AMS1
GND
E9
PF9
AMS2
GND
F5
PG0
PG1
PG10
PG11
PG12
PG13
PG14
PG15
PG2
PG3
PG4
PG5
PG6
PG7
G1
G2
D1
D2
D3
D5
D6
C1
G3
F1
PJ3
E5
AMS3
GND
F6
PJ4
E8
AOE
GND
F10
F11
G4
G5
G11
H11
J4
PJ5
E10
G10
K5
ARDY
GND
PJ6
ARE
GND
PJ7
B8
AWE
GND
PJ8
D9
C9
K8
BG
GND
PJ9
K10
B9
BGH
GND
RESET
RTXO
RTXI
SA10
SCAS
SCKE
SMS
C10
A8
A9
E12
C14
B13
C13
BMODE0
BMODE1
BMODE2
BR
GND
A13
B12
A11
P3
GND
J5
L5
GND
J9
F2
D14
A7
GND
J10
K6
F3
CLKBUF
CLKIN
GND
E1
A12
GND
K11
E2
Rev. J
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Page 57 of 68
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February 2014
ADSP-BF534/ADSP-BF536/ADSP-BF537
Table 50. 182-Ball CSP_BGA Ball Assignment (Numerically by Ball Number)
Ball No.
A1
Mnemonic Ball No.
Mnemonic Ball No.
Mnemonic Ball No.
Mnemonic Ball No.
Mnemonic
DATA0
GND
VDDEXT
PH11
PH12
PH13
PH14
PH15
CLKBUF
RTXO
RTXI
GND
XTAL
CLKIN
VROUT0
GND
PH5
C10
C11
C12
C13
C14
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
E1
RESET
PJ3
F5
GND
GND
GND
GND
VDDEXT
AMS2
AMS1
PG0
J14
K1
ADDR1
PF5
M9
M10
M11
M12
M13
M14
N1
A2
F6
A3
VDDEXT
SMS
SCAS
PG10
PG11
PG12
GND
PG13
PG14
PJ4
F10
F11
F12
F13
F14
G1
K2
PF6
ADDR15
ADDR9
ADDR10
ADDR11
TRST
A4
K3
PF7
A5
K4
PF8
A6
K5
VDDINT
GND
A7
K6
A8
K7
VDDEXT
VDDINT
VDDEXT
VDDINT
GND
N2
TMS
A9
G2
PG1
K8
N3
TDO
A10
A11
A12
A13
A14
B1
G3
PG2
K9
N4
BMODE0
DATA13
DATA10
DATA7
DATA4
DATA1
BGH
G4
GND
GND
VDDINT
GND
AMS3
AOE
K10
K11
K12
K13
K14
L1
N5
G5
N6
PJ5
G10
G11
G12
G13
G14
H1
ADDR7
ADDR5
ADDR2
PF1
N7
PJ8
N8
PJ10
PJ11
SWE
SRAS
BR
N9
B2
PH6
N10
N11
N12
N13
N14
P1
B3
PH7
ARE
L2
PF2
ADDR16
ADDR14
ADDR13
ADDR12
VDDEXT
B4
PH8
PF12
PF13
PF14
PF15
VDDEXT
VDDEXT
GND
ABE1
ABE0
AWE
PF9
L3
PF3
B5
PH9
H2
L4
PF4
B6
PH10
PJ1
PG6
H3
L5
BMODE2
GND
B7
E2
PG7
H4
L6
B8
PJ7
E3
PG8
H5
L7
VDDEXT
GND
P2
TCK
B9
VDDRTC
NMI
E4
PG9
H10
H11
H12
H13
H14
J1
L8
P3
BMODE1
DATA15
DATA14
DATA11
DATA8
DATA5
DATA2
BG
B10
B11
B12
B13
B14
C1
E5
VDDINT
VDDEXT
GND
VDDINT
GND
VDDINT
VDDEXT
SA10
ARDY
AMS0
PG3
L9
VDDEXT
GND
P4
PJ2
E6
L10
L11
L12
L13
L14
M1
M2
M3
M4
M5
M6
M7
M8
P5
VROUT1
SCKE
CLKOUT
PG15
PH0
E7
VDDEXT
ADDR8
ADDR6
ADDR3
PF0
P6
E8
P7
E9
P8
E10
E11
E12
E13
E14
F1
J2
PF10
PF11
GND
GND
GND
GND
VDDEXT
VDDEXT
ADDR4
P9
C2
J3
P10
P11
P12
P13
P14
C3
PH1
J4
EMU
ADDR19
ADDR18
ADDR17
GND
C4
PH2
J5
TDI
C5
PH3
J9
GND
C6
PH4
J10
J11
J12
J13
DATA12
DATA9
DATA6
DATA3
C7
PJ0
F2
PG4
C8
PJ6
F3
PG5
C9
PJ9
F4
VDDEXT
Rev. J
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Page 58 of 68
|
February 2014
ADSP-BF534/ADSP-BF536/ADSP-BF537
Figure 63 shows the top view of the CSP_BGA
ball configuration. Figure 64 shows the bottom view of the CSP_
BGA ball configuration.
14 13 12 11 10
9
8
7
6
5
4
3
2
1
1
2
3
4
5
6
7
8
9
10 11 12 13 14
A
B
C
D
E
F
A
B
C
D
E
F
G
H
J
G
H
J
K
L
K
L
M
N
P
M
N
P
KEY:
KEY:
V
V
V
GND
I/O
DDINT
DDRTC
V
V
GND
I/O
DDINT
DDRTC
V
DDEXT
ROUT
V
V
DDEXT
ROUT
Figure 64. 182-Ball CSP_BGA Configuration (Bottom View)
Figure 63. 182-Ball CSP_BGA Configuration (Top View)
Rev. J
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Page 59 of 68
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February 2014
ADSP-BF534/ADSP-BF536/ADSP-BF537
208-BALL CSP_BGA BALL ASSIGNMENT
Table 51 lists the CSP_BGA ball assignment by signal mne-
monic. Table 52 on Page 61 lists the CSP_BGA ball assignment
by ball number.
Table 51. 208-Ball CSP_BGA Ball Assignment (Alphabetically by Signal Mnemonic)
Mnemonic Ball No.
Mnemonic Ball No.
Mnemonic Ball No.
Mnemonic Ball No.
Mnemonic Ball No.
ABE0
P19
P20
R19
W18
Y18
W17
Y17
W16
Y16
W15
Y15
W14
Y14
T20
T19
U20
U19
V20
V19
W20
Y19
M20
M19
G20
G19
N20
J19
DATA12
DATA13
DATA14
DATA15
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
DATA8
DATA9
EMU
Y4
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
NMI
PF0
M13
N9
N10
N11
N12
N13
P11
V2
PG6
PG7
PG8
PG9
PH0
PH1
PH10
PH11
PH12
PH13
PH14
PH15
PH2
PH3
PH4
PH5
PH6
PH7
PH8
PH9
PJ0
E2
TDI
V1
ABE1
W4
Y3
D1
TDO
Y2
ADDR1
ADDR10
ADDR11
ADDR12
ADDR13
ADDR14
ADDR15
ADDR16
ADDR17
ADDR18
ADDR19
ADDR2
ADDR3
ADDR4
ADDR5
ADDR6
ADDR7
ADDR8
ADDR9
AMS0
D2
TMS
U2
W3
Y9
C1
TRST
U1
B4
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDRTC
VROUT0
VROUT1
XTAL
G7
W9
Y8
A5
G8
B9
G9
W8
Y7
A10
B10
A11
B11
A12
B5
G10
H7
W2
W19
Y1
W7
Y6
H8
J7
W6
T1
Y13
Y20
C20
T2
J8
K7
GND
A1
A6
K8
GND
A13
A20
B2
B6
L7
GND
PF1
R1
A7
L8
GND
PF10
PF11
PF12
PF13
PF14
PF15
PF2
L2
B7
M7
M8
N7
GND
G11
H9
K1
A8
GND
K2
B8
GND
H10
H11
H12
H13
J9
J1
A9
N8
GND
J2
B12
B13
B19
C19
D19
E19
B18
A19
B15
B16
B17
B20
D20
A15
A14
L20
K20
H20
J20
K19
L19
W1
P7
GND
H1
R2
PJ1
P8
AMS1
GND
PJ10
PJ11
PJ2
P9
AMS2
GND
PF3
P1
P10
G12
G13
G14
H14
J14
K14
L14
M14
N14
P12
P13
P14
A16
E20
F20
A17
AMS3
GND
J10
J11
J12
J13
K9
PF4
P2
AOE
GND
PF5
N1
N2
M1
M2
L1
PJ3
ARDY
GND
PF6
PJ4
ARE
N19
R20
Y11
Y12
W13
W12
W11
F19
B14
A18
H19
Y10
W10
Y5
GND
PF7
PJ5
AWE
GND
PF8
PJ6
BG
GND
K10
K11
K12
K13
L9
PF9
PJ7
BGH
GND
PG0
H2
G1
C2
PJ8
BMODE0
BMODE1
BMODE2
BR
GND
PG1
PJ9
GND
PG10
PG11
PG12
PG13
PG14
PG15
PG2
RESET
RTXO
RTXI
SA10
SCAS
SCKE
SMS
SRAS
SWE
TCK
GND
B1
GND
L10
L11
L12
L13
M9
M10
M11
M12
A2
A3
B3
CLKBUF
CLKIN
GND
GND
CLKOUT
DATA0
DATA1
DATA10
DATA11
GND
A4
G2
F1
GND
GND
PG3
GND
PG4
F2
W5
GND
PG5
E1
Rev. J
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Page 60 of 68
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February 2014
ADSP-BF534/ADSP-BF536/ADSP-BF537
Table 52 lists the CSP_BGA ball assignment by ball number.
Table 51 on Page 60 lists the CSP_BGA ball assignment by sig-
nal mnemonic.
Table 52. 208-Ball CSP_BGA Ball Assignment (Numerically by Ball Number)
Ball No.
A1
Mnemonic Ball No.
Mnemonic Ball No.
Mnemonic Ball No.
Mnemonic Ball No.
Mnemonic
TCK
GND
PG12
PG13
PG15
PH1
C19
C20
D1
PJ11
J9
GND
GND
GND
GND
GND
VDDINT
ARDY
SMS
M19
M20
N1
AMS1
AMS0
PF5
W1
W2
W3
W4
W5
W6
W7
W8
W9
W10
W11
W12
W13
W14
W15
W16
W17
W18
W19
W20
Y1
A2
NMI
J10
J11
J12
J13
J14
J19
J20
K1
GND
A3
PG7
DATA15
DATA13
DATA11
DATA9
DATA7
DATA5
DATA3
DATA1
BMODE2
BMODE1
BMODE0
ADDR18
ADDR16
ADDR14
ADDR12
ADDR10
GND
A4
D2
PG8
N2
PF6
A5
D19
D20
E1
PJ2
N7
VDDEXT
VDDEXT
GND
GND
GND
GND
GND
VDDINT
ARE
A6
PH3
RESET
PG5
N8
A7
PH5
N9
A8
PH7
E2
PG6
N10
N11
N12
N13
N14
N19
N20
P1
A9
PH9
E19
E20
F1
PJ3
PF11
PF12
VDDEXT
VDDEXT
GND
GND
GND
GND
GND
VDDINT
SRAS
SCAS
PF9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
B1
PH11
PH13
PH15
GND
RTXI
RTXO
VDDRTC
XTAL
CLKIN
PJ5
VROUT0
PG3
K2
K7
F2
PG4
K8
F19
F20
G1
BR
K9
VROUT1
PG1
K10
K11
K12
K13
K14
K19
K20
L1
AOE
PF3
G2
PG2
P2
PF4
G7
VDDEXT
VDDEXT
VDDEXT
VDDEXT
GND
VDDINT
VDDINT
VDDINT
AMS3
AMS2
PF15
PG0
P7
VDDEXT
VDDEXT
VDDEXT
VDDEXT
GND
VDDINT
VDDINT
VDDINT
ABE0
ABE1
PF1
G8
P8
G9
P9
GND
PG11
GND
PG14
PH0
G10
G11
G12
G13
G14
G19
G20
H1
P10
P11
P12
P13
P14
P19
P20
R1
ADDR8
GND
B2
L2
PF10
VDDEXT
VDDEXT
GND
GND
GND
GND
GND
VDDINT
SWE
Y2
TDO
B3
L7
Y3
DATA14
DATA12
DATA10
DATA8
DATA6
DATA4
DATA2
DATA0
BG
B4
L8
Y4
B5
PH2
L9
Y5
B6
PH4
L10
L11
L12
L13
L14
L19
L20
M1
M2
M7
M8
M9
M10
M11
M12
M13
M14
Y6
B7
PH6
Y7
B8
PH8
H2
R2
PF2
Y8
B9
PH10
PH12
PH14
PJ0
H7
VDDEXT
VDDEXT
GND
GND
GND
GND
GND
VDDINT
CLKOUT
SCKE
PF13
PF14
VDDEXT
VDDEXT
R19
R20
T1
ADDR1
AWE
Y9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
C1
H8
Y10
Y11
Y12
Y13
Y14
Y15
Y16
Y17
Y18
Y19
Y20
H9
EMU
H10
H11
H12
H13
H14
H19
H20
J1
SA10
PF7
T2
PF0
BGH
PJ1
T19
T20
U1
ADDR3
ADDR2
TRST
TMS
GND
CLKBUF
PJ6
PF8
ADDR19
ADDR17
ADDR15
ADDR13
ADDR11
ADDR9
GND
VDDEXT
VDDEXT
GND
GND
GND
GND
GND
VDDINT
PJ7
U2
PJ8
U19
U20
V1
ADDR5
ADDR4
TDI
PJ4
PJ10
PJ9
J2
V2
GND
ADDR7
ADDR6
PG9
J7
V19
V20
C2
PG10
J8
Rev. J
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Page 61 of 68
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February 2014
ADSP-BF534/ADSP-BF536/ADSP-BF537
Figure 65 shows the top view of the CSP_BGA ball configura-
tion. Figure 66 shows the bottom view of the CSP_BGA ball
configuration.
20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20
A
B
C
D
E
F
A
B
C
D
E
F
G
H
J
G
H
J
K
L
K
L
M
N
P
R
T
M
N
P
R
T
U
V
W
Y
U
V
W
Y
KEY:
KEY:
V
V
V
GND
I/O
DDINT
DDRTC
V
V
V
GND
I/O
DDINT
DDRTC
ROUT
V
DDEXT
ROUT
V
DDEXT
Figure 66. 208-Ball CSP_BGA Configuration (Bottom View)
Figure 65. 208-Ball CSP_BGA Configuration (Top View)
Rev. J
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Page 62 of 68
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February 2014
ADSP-BF534/ADSP-BF536/ADSP-BF537
OUTLINE DIMENSIONS
Dimensions in Figure 67 and Figure 68 are shown in
millimeters.
A1 CORNER
INDEX AREA
12.00 BSC SQ
14 13 12 11 10
9 8 7 6 5 4 3 2 1
A
B
C
D
E
F
G
H
J
PIN A1
INDICATOR
LOCATION
10.40
BSC
SQ
0.80
BSC
TYP
K
L
M
N
P
TOP VIEW
BOTTOM VIEW
1.31
1.21
1.10
DETAIL A
1.70 MAX
0.25 MIN
0.50
0.45
0.40
0.12
COPLANARITY
SEATING
PLANE
NOTES:
1. COMPLIANT TO JEDEC STANDARD MO-205-AE,
EXCEPT FOR BALL DIAMETER.
(BALL
DIAMETER)
2. CENTER DIMENSIONS ARE NOMINAL.
3.THE ACTUAL POSITION OF THE BALL GRID IS
WITHIN 0.15 OF ITS IDEAL POSITION RELATIVE
TO THE PACKAGE EDGES
DETAIL A
Figure 67. 182-Ball Chip Scale Package Ball Grid Array [CSP_BGA]
(BC-182)
Dimensions shown in millimeters
Rev. J
|
Page 63 of 68
|
February 2014
ADSP-BF534/ADSP-BF536/ADSP-BF537
17.10
17.00 SQ
16.90
A1 CORNER
INDEX AREA
20 18 16 14 12 10
19 17 15 13 11
8
6
4
2
9
7
5
3
1
A
B
C
D
E
F
A1 BALL
CORNER
G
H
J
15.20
BSC SQ
K
L
M
N
P
R
T
0.80
BSC
U
V
W
Y
TOP VIEW
DETAIL A
BOTTOM VIEW
*
1.36
1.26
1.16
1.75
1.61
1.46
DETAIL A
0.35 NOM
0.30 MIN
*
0.50
0.45
0.40
COPLANARITY
0.12
SEATING
PLANE
BALL
DIAMETER
*
COMPLIANT TO JEDEC STANDARDS MO-205-AM WITH
EXCEPTION TO PACKAGE HEIGHT AND BALL DIAMETER.
Figure 68. 208-Ball Chip Scale Package Ball Grid Array [CSP_BGA]
(BC-208-2)
Dimensions shown in millimeters
Rev. J
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Page 64 of 68
|
February 2014
ADSP-BF534/ADSP-BF536/ADSP-BF537
SURFACE-MOUNT DESIGN
The following table is provided as an aid to PCB design. For
industry-standard design recommendations, refer to IPC-7351,
Generic Requirements for Surface Mount Design and Land Pat-
tern Standard.
Package Solder Mask
Opening
Package
Package Ball Attach Type
Package Ball Pad Size
0.55 mm diameter
0.55 mm diameter
182-Ball CSP_BGA (BC-182)
208-Ball CSP_BGA (BC-208-2)
Solder Mask Defined
Solder Mask Defined
0.40 mm diameter
0.40 mm diameter
Rev. J
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Page 65 of 68
|
February 2014
ADSP-BF534/ADSP-BF536/ADSP-BF537
AUTOMOTIVE PRODUCTS
The ADBF534W model is available with controlled manufactur-
ing to support the quality and reliability requirements of
automotive applications. Note that these automotive models
may have specifications that differ from the commercial models
and designers should review the Specifications section of this
data sheet carefully. Only the automotive grade products shown
in Table 53 are available for use in automotive applications.
Contact your local ADI account representative for specific
product ordering information and to obtain the specific Auto-
motive Reliability reports for these models.
Table 53. Automotive Products
Package
Option
Product Family1,2
Temperature Range3
–40°C to +85°C
Speed Grade (Max) Package Description
ADBF534WBBCZ4Axx
ADBF534WBBCZ4Bxx
ADBF534WYBCZ4Bxx
400 MHz
400 MHz
400 MHz
182-Ball CSP_BGA
208-Ball CSP_BGA
208-Ball CSP_BGA
BC-182
–40°C to +85°C
BC-208-2
BC-208-2
–40°C to +105°C
1 Z = RoHS compliant part.
2 xx denotes silicon revision.
3 Referenced temperature is ambient temperature.
Rev. J
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Page 66 of 68
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February 2014
ADSP-BF534/ADSP-BF536/ADSP-BF537
ORDERING GUIDE
In the following table CSP_BGA = Chip Scale Package Ball Grid
Array.
Package
Option
Model 1
Temperature Range2
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +105°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
0°C to +70°C
Speed Grade (Max)
400 MHz
400 MHz
500 MHz
500 MHz
400 MHz
400 MHz
500 MHz
300 MHz
300 MHz
400 MHz
400 MHz
300 MHz
300 MHz
400 MHz
500 MHz
500 MHz
500 MHz
533 MHz
533 MHz
600 MHz
600 MHz
Package Description
182-Ball CSP_BGA
182-Ball CSP_BGA
182-Ball CSP_BGA
182-Ball CSP_BGA
208-Ball CSP_BGA
208-Ball CSP_BGA
208-Ball CSP_BGA
182-Ball CSP_BGA
182-Ball CSP_BGA
182-Ball CSP_BGA
182-Ball CSP_BGA
208-Ball CSP_BGA
ADSP-BF534BBC-4A
ADSP-BF534BBCZ-4A
ADSP-BF534BBC-5A
ADSP-BF534BBCZ-5A
ADSP-BF534BBCZ-4B
ADSP-BF534YBCZ-4B
ADSP-BF534BBCZ-5B
ADSP-BF536BBC-3A
ADSP-BF536BBCZ-3A
ADSP-BF536BBC-4A
ADSP-BF536BBCZ-4A
ADSP-BF536BBCZ-3B
ADSP-BF536BBCZ3BRL
ADSP-BF536BBCZ-4B
ADSP-BF537BBC-5A
ADSP-BF537BBCZ-5A
ADSP-BF537BBCZ-5B
ADSP-BF537BBCZ-5AV
ADSP-BF537BBCZ-5BV
ADSP-BF537KBCZ-6AV
ADSP-BF537KBCZ-6BV
1 Z = RoHS compliant part.
BC-182
BC-182
BC-182
BC-182
BC-208-2
BC-208-2
BC-208-2
BC-182
BC-182
BC-182
BC-182
BC-208-2
208-Ball CSP_BGA, 13" Tape and Reel BC-208-2
208-Ball CSP_BGA
182-Ball CSP_BGA
182-Ball CSP_BGA
208-Ball CSP_BGA
182-Ball CSP_BGA
208-Ball CSP_BGA
182-Ball CSP_BGA
208-Ball CSP_BGA
BC-208-2
BC-182
BC-182
BC-208-2
BC-182
BC-208-2
BC-182
0°C to +70°C
BC-208-2
2 Referenced temperature is ambient temperature. The ambient temperature is not a specification. Please see Operating Conditions on Page 23 for junction temperature (TJ)
specification which is the only temperature specification.
Rev. J
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Page 67 of 68
|
February 2014
ADSP-BF534/ADSP-BF536/ADSP-BF537
©2014 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05317-0-2/14(J)
Rev. J
|
Page 68 of 68
|
February 2014
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