ADSP-BF536_技术文档

Blackfin^®

Embedded Processor

a

ADSP-BF534/ADSP-BF536/ADSP-BF537

FEATURES

PERIPHERALS

Up to 600 MHz high performance Blackfin processor

Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs,

40-bit shifter

RISC-like register and instruction model for ease of

programming and compiler-friendly support

Advanced debug, trace, and performance monitoring

0.8 V to 1.2 V core V_DDwith on-chip voltage regulation

2.5 V and 3.3 V-tolerant I/O with specific 5 V-tolerant pins

182-ball and 208-ball MBGA packages

IEEE 802.3-compliant 10/100 Ethernet MAC (ADSP-BF536 and

ADSP-BF537 only)

Controller area network (CAN) 2.0B interface

Parallel peripheral interface (PPI), supporting ITU-R 656

video data formats

Two dual-channel, full-duplex synchronous serial ports

(SPORTs), supporting eight stereo I²S channels

12 peripheral DMAs, 2 mastered by the Ethernet MAC

Two memory-to-memory DMAs with external request lines

Event handler with 32 interrupt inputs

Serial peripheral interface (SPI)-compatible

Two UARTs with IrDA^®support

MEMORY

Up to 132K bytes of on-chip memory comprised of:

Instruction SRAM/cache; instruction SRAM;

Two-wire interface (TWI) controller

data SRAM/cache; additional dedicated data SRAM;

scratchpad SRAM (see Table 1 on Page 3 for available

memory configurations)

Eight 32-bit timer/counters with PWM support

Real-time clock (RTC) and watchdog timer

32-bit core timer

48 general-purpose I/Os (GPIOs), 8 with high current drivers

On-chip PLL capable of 1

؋

to 63

؋

frequency multiplication

Debug/JTAG interface

External memory controller with glueless support for SDRAM

and asynchronous 8-bit and 16-bit memories

Flexible booting options from external flash, SPI and TWI

memory or from SPI, TWI, and UART host devices

Memory management unit providing memory protection

JTAG TEST AND EMULATION

VOLTAGE REGULATOR

PERIPHERAL ACCESS BUS

WATCHDOG TIMER

RTC

INTERRUPT

CONTROLLER

B

CAN

TWI

PORT

J

L1

DATA

MEMORY

SPORT0

SPORT1

PPI

DMA

CONTROLLER

INSTRUCTION

MEMORY

GPIO

PORT

G

EXTERNAL

ACCESS

BUS

DMA CORE BUS

UART 0-1

GPIO

PORT

F

EXTERNAL PORT

FLASH, SDRAM CONTROL

SPI

TIMERS 0-7

16

GPIO

PORT

H

ETHERNET MAC

(ADSP-BF536/

BF537 ONLY)

BOOT ROM

Figure 1. Functional Block Diagram

Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc.

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable.

However, no responsibility is assumed by Analog Devices for its use, nor for any

infringements of patents or other rights of third parties that may result from its use.

Specifications subject to change without notice. No license is granted by implication

or otherwise under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

ADSP-BF534/ADSP-BF536/ADSP-BF537

TABLE OF CONTENTS

General Description ................................................. 3

Portable Low Power Architecture ............................. 3

System Integration ................................................ 3

Blackfin Processor Peripherals ................................. 3

Blackfin Processor Core .......................................... 4

Memory Architecture ............................................ 5

DMA Controllers .................................................. 8

Real-Time Clock ................................................... 9

Watchdog Timer .................................................. 9

Timers ............................................................... 9

Serial Ports (SPORTs) .......................................... 10

Serial Peripheral Interface (SPI) Port ....................... 10

UART Ports ...................................................... 10

Controller Area Network (CAN) ............................ 11

TWI Controller Interface ...................................... 11

10/100 Ethernet MAC .......................................... 11

Ports ................................................................ 12

Parallel Peripheral Interface (PPI) ........................... 12

Dynamic Power Management ................................ 13

Voltage Regulation .............................................. 14

Clock Signals ..................................................... 14

Booting Modes ................................................... 16

Instruction Set Description ................................... 16

Development Tools ............................................. 17

Designing an Emulator-Compatible Processor Board .. 18

Related Documents ............................................. 18

Pin Descriptions .................................................... 19

Specifications ........................................................ 23

Operating Conditions .......................................... 23

Electrical Characteristics ....................................... 24

Absolute Maximum Ratings .................................. 25

ESD Sensitivity ................................................... 25

Package Information ............................................ 25

Timing Specifications ........................................... 26

Asynchronous Memory Read Cycle Timing ............ 28

Asynchronous Memory Write Cycle Timing ........... 29

External Port Bus Request and Grant Cycle Timing .. 30

SDRAM Interface Timing .................................. 31

External DMA Request Timing ............................ 32

Parallel Peripheral Interface Timing ...................... 33

Serial Ports ..................................................... 36

Serial Peripheral Interface Port—Master Timing ...... 40

Serial Peripheral Interface Port—Slave Timing ........ 41

Universal Asynchronous Receiver-Transmitter (UART)

Ports—Receive and Transmit Timing ................. 42

General-Purpose Port Timing ............................. 43

Timer Cycle Timing .......................................... 44

Timer Clock Timing ......................................... 45

JTAG Test and Emulation Port Timing .................. 46

10/100 Ethernet MAC Controller Timing ............... 47

Output Drive Currents ......................................... 50

Power Dissipation ............................................... 53

Test Conditions .................................................. 54

Capacitive Loading .............................................. 55

Thermal Characteristics ........................................ 58

182-Ball Mini-BGA Pinout ....................................... 59

208-Ball Sparse Mini-BGA Pinout .............................. 62

Outline Dimensions ................................................ 65

Surface Mount Design .......................................... 66

Ordering Guide ..................................................... 66

REVISION HISTORY

7/07—Revision B

Revised Figure 47, Figure 48, and Figure 49 Under

Test Conditions ..................................................... 54

For this revision of the data sheet, the ADSP-BF534,

ADSP-BF536, and ADSP-BF537 have been combined into

a single family data sheet. Because of this change, not all

processor features and attributes apply across all products. See

Table 1 on Page 3 for a breakdown of product offerings.

Added 208-Ball Mini BGA Thermal Characteristics on Page 58

and 208-Ball Sparse Mini-BGA Pinout on Page 62.

Added Table 10, Maximum Duty Cycle for Input Transient

Voltage ............................................................. 25

Added Universal Asynchronous Receiver-Transmitter (UART)

Ports—Receive and Transmit Timing ......................... 42

Rev. B

| Page 2 of 68 | July 2006

ADSP-BF534/ADSP-BF536/ADSP-BF537

GENERAL DESCRIPTION

The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors are

members of the Blackfin family of products, incorporating the

Analog Devices/Intel Micro Signal Architecture (MSA).

Blackfin processors combine a dual-MAC state-of-the-art signal

processing engine, the advantages of a clean, orthogonal RISC-

like microprocessor instruction set, and single-instruction,

multiple-data (SIMD) multimedia capabilities into a single

instruction-set architecture.

PORTABLE LOW POWER ARCHITECTURE

Blackfin processors provide world-class power management

and performance. They are produced with a low power and low

voltage design methodology and feature on-chip dynamic

power management, which is the ability to vary both the voltage

and frequency of operation to significantly lower overall power

consumption. This capability can result in a substantial reduc-

tion in power consumption, compared with just varying the

frequency of operation. This allows longer battery life for

portable appliances.

The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors are

completely code and pin compatible. They differ only with

respect to their performance, on-chip memory, and presence of

the Ethernet MAC module. Specific performance, memory, and

feature configurations are shown in Table 1.

SYSTEM INTEGRATION

The Blackfin processor is a highly integrated system-on-a-chip

solution for the next generation of embedded network-con-

nected applications. By combining industry-standard interfaces

with a high performance signal processing core, cost-effective

applications can be developed quickly, without the need for

costly external components. The system peripherals include an

IEEE-compliant 802.3 10/100 Ethernet MAC (ADSP-BF536 and

ADSP-BF537 only), a CAN 2.0B controller, a TWI controller,

two UART ports, an SPI port, two serial ports (SPORTs), nine

general-purpose 32-bit timers (eight with PWM capability), a

real-time clock, a watchdog timer, and a parallel peripheral

interface (PPI).

Table 1. Processor Comparison

Features

Ethernet MAC

—

1

2

1

8

1

48

1

2

1

8

1

48

CAN

TWI

1

SPORTs

2

BLACKFIN PROCESSOR PERIPHERALS

UARTs

2

The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors con-

tains a rich set of peripherals connected to the core via several

high bandwidth buses, providing flexibility in system configura-

tion as well as excellent overall system performance (see the

block diagram on Page 1). The processors contain dedicated

network communication modules and high speed serial and

parallel ports, an interrupt controller for flexible management

of interrupts from the on-chip peripherals or external sources,

and power management control functions to tailor the perfor-

mance and power characteristics of the processor and system to

many application scenarios.

SPI

1

GP Timers

8

Watchdog Timers

1

RTC

1

Parallel Peripheral Interface

GPIOs

1

48

L1 Instruction 16K bytes 16K bytes 16K bytes

SRAM/Cache

L1 Instruction 48K bytes 48K bytes 48K bytes

SRAM

Memory

Configuration

All of the peripherals, except for the general-purpose I/O, CAN,

TWI, real-time clock, and timers, are supported by a flexible

DMA structure. There are also separate memory DMA channels

dedicated to data transfers between the processor’s various

memory spaces, including external SDRAM and asynchronous

memory. Multiple on-chip buses running at up to 133 MHz

provide enough bandwidth to keep the processor core running

along with activity on all of the on-chip and external

peripherals.

L1 Data

32K bytes 32K bytes 32K bytes

SRAM/Cache

L1 Data SRAM 32K bytes

L1 Scratchpad 4K bytes

—

32K bytes

4K bytes 4K bytes

2K bytes 2K bytes

400 MHz 600 MHz

L3 Boot ROM

2K bytes

500 MHz

Maximum Speed Grade

Package Options:

Sparse Mini-BGA

Mini-BGA

208-Ball

182-Ball

208-Ball 208-Ball

182-Ball 182-Ball

The Blackfin processors include an on-chip voltage regulator in

support of the processors’ dynamic power management capabil-

ity. The voltage regulator provides a range of core voltage levels

when supplied from a single 2.25 V to 3.6 V input. The voltage

regulator can be bypassed at the user’s discretion.

By integrating a rich set of industry-leading system peripherals

and memory, the Blackfin processors are the platform of choice

for next-generation applications that require RISC-like pro-

grammability, multimedia support, and leading-edge signal

processing in one integrated package.

Rev. B

|

Page 3 of 68 | July 2006

ADSP-BF534/ADSP-BF536/ADSP-BF537

instructions include byte alignment and packing operations,

16-bit and 8-bit adds with clipping, 8-bit average operations,

and 8-bit subtract/absolute value/accumulate (SAA) operations.

Also provided are the compare/select and vector search

instructions.

BLACKFIN PROCESSOR CORE

As shown in Figure 2 on Page 4, the Blackfin processor core

contains two 16-bit multipliers, two 40-bit accumulators, two

40-bit ALUs, four video ALUs, and a 40-bit shifter. The compu-

tation units process 8-, 16-, or 32-bit data from the register file.

For certain instructions, two 16-bit ALU operations can be per-

formed simultaneously on register pairs (a 16-bit high half and

16-bit low half of a compute register). If the second ALU is used,

quad 16-bit operations are possible.

The compute register file contains eight 32-bit registers. When

performing compute operations on 16-bit operand data, the

register file operates as 16 independent 16-bit registers. All

operands for compute operations come from the multiported

register file and instruction constant fields.

The 40-bit shifter can perform shifts and rotates and is used to

support normalization, field extract, and field deposit

instructions.

Each MAC can perform a 16-bit by 16-bit multiply in each

cycle, accumulating the results into the 40-bit accumulators.

Signed and unsigned formats, rounding, and saturation

are supported.

The program sequencer controls the flow of instruction execu-

tion, including instruction alignment and decoding. For

program flow control, the sequencer supports PC relative and

indirect conditional jumps (with static branch prediction), and

subroutine calls. Hardware is provided to support zero-over-

head looping. The architecture is fully interlocked, meaning that

the programmer need not manage the pipeline when executing

instructions with data dependencies.

The ALUs perform a traditional set of arithmetic and logical

operations on 16-bit or 32-bit data. In addition, many special

instructions are included to accelerate various signal processing

tasks. These include bit operations such as field extract and pop-

ulation count, modulo 2³²multiply, divide primitives, saturation

and rounding, and sign/exponent detection. The set of video

ADDRESS ARITHMETIC UNIT

SP

FP

P5

P4

I3

I2

I1

I0

L3

L2

L1

L0

B3

B2

B1

B0

M3

M2

M1

M0

DAG1

P3

DAG0

P2

P1

P0

DA1 32

DA0 32

32

RAB

PREG

SD 32

LD1 32

LD0 32

ASTAT

32

SEQUENCER

R7.H

R6.H

R5.H

R4.H

R3.H

R2.H

R1.H

R0.H

R7.L

R6.L

R5.L

R4.L

R3.L

R2.L

R1.H

R0.L

ALIGN

16

8

DECODE

BARREL

SHIFTER

LOOP BUFFER

40

40 40

A0

A1

CONTROL

UNIT

32

DATA ARITHMETIC UNIT

Figure 2. Blackfin Processor Core

Rev. B

| Page 4 of 68 | July 2006

ADSP-BF534/ADSP-BF536/ADSP-BF537

The address arithmetic unit provides two addresses for simulta-

neous dual fetches from memory. It contains a multiported

register file consisting of four sets of 32-bit index, modify,

length, and base registers (for circular buffering), and eight

additional 32-bit pointer registers (for C-style indexed stack

manipulation).

The memory DMA controller provides high bandwidth data-

movement capability. It can perform block transfers of code or

data between the internal memory and the external

memory spaces.

Internal (On-Chip) Memory

The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors have

three blocks of on-chip memory providing high-bandwidth

access to the core.

Blackfin processors support a modified Harvard architecture in

combination with a hierarchical memory structure. Level 1 (L1)

memories are those that typically operate at the full processor

speed with little or no latency. At the L1 level, the instruction

memory holds instructions only. The two data memories hold

data, and a dedicated scratchpad data memory stores stack and

local variable information.

The first block is the L1 instruction memory, consisting of

64K bytes SRAM, of which 16K bytes can be configured as a

four-way set-associative cache. This memory is accessed at full

processor speed.

In addition, multiple L1 memory blocks are provided, offering a

configurable mix of SRAM and cache. The memory manage-

ment unit (MMU) provides memory protection for individual

tasks that may be operating on the core and can protect system

registers from unintended access.

The second on-chip memory block is the L1 data memory, con-

sisting of up to two banks of up to 32K bytes each. Each memory

bank is configurable, offering both cache and SRAM functional-

ity. This memory block is accessed at full processor speed.

The third memory block is a 4K byte scratchpad SRAM, which

runs at the same speed as the L1 memories, but is only accessible

as data SRAM, and cannot be configured as cache memory.

The architecture provides three modes of operation: user mode,

supervisor mode, and emulation mode. User mode has

restricted access to certain system resources, thus providing a

protected software environment, while supervisor mode has

unrestricted access to the system and core resources.

External (Off-Chip) Memory

External memory is accessed via the EBIU. This 16-bit interface

provides a glueless connection to a bank of synchronous DRAM

(SDRAM) as well as up to four banks of asynchronous memory

devices including flash, EPROM, ROM, SRAM, and memory

mapped I/O devices.

The Blackfin processor instruction set has been optimized so

that 16-bit opcodes represent the most frequently used instruc-

tions, resulting in excellent compiled code density. Complex

DSP instructions are encoded into 32-bit opcodes, representing

fully featured multifunction instructions. Blackfin processors

support a limited multi-issue capability, where a 32-bit instruc-

tion can be issued in parallel with two 16-bit instructions,

allowing the programmer to use many of the core resources in a

single instruction cycle.

The PC133-compliant SDRAM controller can be programmed

to interface to up to 512M bytes of SDRAM. A separate row can

be open for each SDRAM internal bank, and the SDRAM con-

troller supports up to 4 internal SDRAM banks, improving

overall performance.

The Blackfin processor assembly language uses an algebraic syn-

tax for ease of coding and readability. The architecture has been

optimized for use in conjunction with the C/C++ compiler,

resulting in fast and efficient software implementations.

The asynchronous memory controller can be programmed to

control up to four banks of devices with very flexible timing

parameters for a wide variety of devices. Each bank occupies a

1M byte segment regardless of the size of the devices used, so

that these banks are only contiguous if each is fully populated

with 1M byte of memory.

MEMORY ARCHITECTURE

The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors view

memory as a single unified 4G byte address space, using 32-bit

addresses. All resources, including internal memory, external

memory, and I/O control registers, occupy separate sections of

this common address space. The memory portions of this

address space are arranged in a hierarchical structure to provide

a good cost/performance balance of some very fast, low latency

on-chip memory as cache or SRAM, and larger, lower cost, and

performance off-chip memory systems. See Figure 3.

I/O Memory Space

The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors do

not define a separate I/O space. All resources are mapped

through the flat 32-bit address space. On-chip I/O devices have

their control registers mapped into memory-mapped registers

(MMRs) at addresses near the top of the 4G byte address space.

These are separated into two smaller blocks, one which contains

the control MMRs for all core functions, and the other which

contains the registers needed for setup and control of the on-

chip peripherals outside of the core. The MMRs are accessible

only in supervisor mode and appear as reserved space to on-

chip peripherals.

The on-chip L1 memory system is the highest performance

memory available to the Blackfin processor. The off-chip mem-

ory system, accessed through the external bus interface unit

(EBIU), provides expansion with SDRAM, flash memory, and

SRAM, optionally accessing up to 516M bytes of

physical memory.

Rev. B

|

Page 5 of 68 | July 2006

ADSP-BF534/ADSP-BF536/ADSP-BF537

ADSP-BF534/ADSP-BF537 MEMORY MAP

0xFFFF FFFF

ADSP-BF536 MEMORY MAP

0xFFFF FFFF

0xFFE0 0000

0xFFC0 0000

0xFFB0 1000

0xFFB0 0000

0xFFA1 4000

0xFFA1 0000

0xFFA0 C000

0xFFA0 8000

0xFFA0 0000

0xFF90 8000

0xFF90 4000

0xFF90 0000

0xFF80 8000

0xFF80 4000

0xFF80 0000

0xEF00 0800

0xEF00 0000

0x2040 0000

0x2030 0000

0x2020 0000

0x2010 0000

0x2000 0000

0x0000 0000

CORE MMR REGISTERS (2M BYTES)

SYSTEM MMR REGISTERS (2M BYTES)

RESERVED

CORE MMR REGISTERS (2M BYTES)

0xFFE0 0000

SYSTEM MMR REGISTERS (2M BYTES)

0xFFC0 0000

RESERVED

0xFFB0 1000

SCRATCHPAD SRAM (4K BYTES)

0xFFB0 0000

SCRATCHPAD SRAM (4K BYTES)

RESERVED

0xFFA1 4000

INSTRUCTION SRAM/CACHE (16K BYTES)

RESERVED

INSTRUCTION SRAM/CACHE (16K BYTES)

0xFFA1 0000

RESERVED

0xFFA0 C000

INSTRUCTION BANK B SRAM (16K BYTES)

0xFFA0 8000

INSTRUCTION BANK B SRAM (16K BYTES)

INSTRUCTION BANK A SRAM (32K BYTES)

RESERVED

INSTRUCTION BANK A SRAM (32K BYTES)

0xFFA0 0000

RESERVED

0xFF90 8000

DATA BANK B SRAM/CACHE (16K BYTES)

RESERVED

DATA BANK B SRAM/CACHE (16K BYTES)

0xFF90 4000

DATA BANK B SRAM (16K BYTES)

0xFF90 0000

RESERVED

0xFF80 8000

DATA BANK A SRAM/CACHE (16K BYTES)

0xFF80 4000

RESERVED

DATA BANK A SRAM/CACHE (16K BYTES)

RESERVED

DATA BANK A SRAM (16K BYTES)

0xFF80 0000

RESERVED

0xEF00 0800

BOOT ROM (2K BYTES)

0xEF00 0000

BOOT ROM (2K BYTES)

RESERVED

0x2040 0000

ASYNC MEMORY BANK 3 (1M BYTES)

ASYNC MEMORY BANK 2 (1M BYTES)

ASYNC MEMORY BANK 1 (1M BYTES)

ASYNC MEMORY BANK 0 (1M BYTES)

ASYNC MEMORY BANK 3 (1M BYTES)

0x2030 0000

ASYNC MEMORY BANK 2 (1M BYTES)

0x2020 0000

ASYNC MEMORY BANK 1 (1M BYTES)

0x2010 0000

ASYNC MEMORY BANK 0 (1M BYTES)

0x2000 0000

SDRAM MEMORY (16M BYTES TO 512M BYTES)

0x0000 0000

Figure 3. ADSP-BF534/ADSP-BF536/ADSP-BF537 Memory Maps

• Nonmaskable Interrupt (NMI) – The NMI event can be

Booting

generated by the software watchdog timer or by the NMI

input signal to the processor. The NMI event is frequently

used as a power-down indicator to initiate an orderly shut-

down of the system.

The Blackfin processor contains a small on-chip boot kernel,

which configures the appropriate peripheral for booting. If the

Blackfin processor is configured to boot from boot ROM mem-

ory space, the processor starts executing from the on-chip boot

ROM. For more information, see Booting Modes on Page 16.

• Exceptions – Events that occur synchronously to program

flow (in other words, the exception is taken before the

instruction is allowed to complete). Conditions such as

data alignment violations and undefined instructions cause

exceptions.

Event Handling

The event controller on the Blackfin processor handles all asyn-

chronous and synchronous events to the processor. The

Blackfin processor provides event handling that supports both

nesting and prioritization. Nesting allows multiple event service

routines to be active simultaneously. Prioritization ensures that

servicing of a higher priority event takes precedence over servic-

ing of a lower priority event. The controller provides support for

five different types of events:

• Interrupts – Events that occur asynchronously to program

flow. They are caused by input pins, timers, and other

peripherals, as well as by an explicit software instruction.

Each event type has an associated register to hold the return

address and an associated return-from-event instruction. When

an event is triggered, the state of the processor is saved on the

supervisor stack.

• Emulation – An emulation event causes the processor to

enter emulation mode, allowing command and control of

the processor via the JTAG interface.

The Blackfin processor event controller consists of two stages,

the core event controller (CEC) and the system interrupt con-

troller (SIC). The core event controller works with the system

interrupt controller to prioritize and control all system events.

• Reset – This event resets the processor.

Rev. B

| Page 6 of 68 | July 2006

ADSP-BF534/ADSP-BF536/ADSP-BF537

Conceptually, interrupts from the peripherals enter into the

SIC, and are then routed directly into the general-purpose inter-

rupts of the CEC.

Table 3. System Interrupt Controller (SIC)

Default

Peripheral

Interrupt ID

Peripheral Interrupt Event

PLL Wakeup

Mapping

Core Event Controller (CEC)

IVG7

0

1

2

The CEC supports nine general-purpose interrupts (IVG15–7),

in addition to the dedicated interrupt and exception events. Of

these general-purpose interrupts, the two lowest priority

interrupts (IVG15–14) are recommended to be reserved for

software interrupt handlers, leaving seven prioritized interrupt

inputs to support the peripherals of the Blackfin processor.

Table 2 describes the inputs to the CEC, identifies their names

in the event vector table (EVT), and lists their priorities.

DMA Error (generic)

DMAR0 Block Interrupt

DMAR1 Block Interrupt

DMAR0 Overflow Error

DMAR1 Overflow Error

CAN Error

Ethernet Error (ADSP-BF536 and

ADSP-BF537 only)

Table 2. Core Event Controller (CEC)

SPORT 0 Error

IVG7

2

Priority

SPORT 1 Error

IVG7

2

(0 Is Highest) Event Class

EVT Entry

EMU

PPI Error

IVG7

2

0

Emulation/Test Control

SPI Error

IVG7

2

1

Reset

RST

UART0 Error

IVG7

2

Nonmaskable Interrupt

Exception

NMI

UART1 Error

IVG7

2

3

EVX

Real-Time Clock

IVG8

3

4

Reserved

—

DMA Channel 0 (PPI)

DMA Channel 3 (SPORT 0 Rx)

DMA Channel 4 (SPORT 0 Tx)

DMA Channel 5 (SPORT 1 Rx)

DMA Channel 6 (SPORT 1 Tx)

TWI

IVG8

4

5

Hardware Error

IVHW

IVTMR

IVG7

IVG9

5

6

Core Timer

IVG9

6

7

General-Purpose Interrupt 7

General-Purpose Interrupt 8

General-Purpose Interrupt 9

General-Purpose Interrupt 10

General-Purpose Interrupt 11

General-Purpose Interrupt 12

General-Purpose Interrupt 13

General-Purpose Interrupt 14

General-Purpose Interrupt 15

IVG9

7

8

IVG8

IVG9

8

9

IVG9

IVG10

IVG11

9

10

11

12

13

14

15

IVG10

IVG11

IVG12

IVG13

IVG14

IVG15

DMA Channel 7 (SPI)

DMA Channel 8 (UART0 Rx)

DMA Channel 9 (UART0 Tx)

DMA Channel 10 (UART1 Rx)

DMA Channel 11 (UART1 Tx)

CAN Rx

10

11

12

13

14

15

16

17

CAN Tx

System Interrupt Controller (SIC)

DMA Channel 1 (Ethernet Rx,

The system interrupt controller provides the mapping and rout-

ing of events from the many peripheral interrupt sources to the

prioritized general-purpose interrupt inputs of the CEC.

Although the processor provides a default mapping, the user

can alter the mappings and priorities of interrupt events by writ-

ing the appropriate values into the interrupt assignment

registers (IAR). Table 3 describes the inputs into the SIC and the

default mappings into the CEC.

ADSP-BF536 and ADSP-BF537 only)

Port H Interrupt A

IVG11

17

18

DMA Channel 2 (Ethernet Tx,

ADSP-BF536 and ADSP-BF537 only)

Port H Interrupt B

Timer 0

IVG11

IVG12

18

19

20

21

22

23

24

25

26

27

28

Timer 1

Timer 2

Timer 3

Timer 4

Timer 5

Timer 6

Timer 7

Port F, G Interrupt A

Port G Interrupt B

Rev. B

|

Page 7 of 68 | July 2006

ADSP-BF534/ADSP-BF536/ADSP-BF537

Table 3. System Interrupt Controller (SIC) (Continued)

• SIC interrupt wakeup enable register (SIC_IWR) – By

enabling the corresponding bit in this register, a peripheral

can be configured to wake up the processor, should the

core be idled when the event is generated. (For more infor-

mation, see Dynamic Power Management on Page 13.)

Default

Peripheral

Peripheral Interrupt Event

Mapping

Interrupt ID

DMA Channels 12 and 13

(Memory DMA Stream 0)

IVG13

29

30

Because multiple interrupt sources can map to a single general-

purpose interrupt, multiple pulse assertions can occur simulta-

neously, before or during interrupt processing for an interrupt

event already detected on this interrupt input. The IPEND reg-

ister contents are monitored by the SIC as the interrupt

acknowledgement.

DMA Channels 14 and 15

(Memory DMA Stream 1)

Software Watchdog Timer

Port F Interrupt B

IVG13

31

Event Control

The appropriate ILAT register bit is set when an interrupt rising

edge is detected (detection requires two core clock cycles). The

bit is cleared when the respective IPEND register bit is set. The

IPEND bit indicates that the event has entered into the proces-

sor pipeline. At this point the CEC recognizes and queues the

next rising edge event on the corresponding event input. The

minimum latency from the rising edge transition of the general-

purpose interrupt to the IPEND output asserted is three core

clock cycles; however, the latency can be much higher, depend-

ing on the activity within and the state of the processor.

The Blackfin processor provides a very flexible mechanism to

control the processing of events. In the CEC, three registers are

used to coordinate and control events. Each register is

16 bits wide:

• CEC interrupt latch register (ILAT) – Indicates when

events have been latched. The appropriate bit is set when

the processor has latched the event and cleared when the

event has been accepted into the system. This register is

updated automatically by the controller, but it may be writ-

ten only when its corresponding IMASK bit is cleared.

DMA CONTROLLERS

• CEC interrupt mask register (IMASK) – Controls the

masking and unmasking of individual events. When a bit is

set in the IMASK register, that event is unmasked and is

processed by the CEC when asserted. A cleared bit in the

IMASK register masks the event, preventing the processor

from servicing the event even though the event may be

latched in the ILAT register. This register may be read or

written while in supervisor mode. (Note that general-pur-

pose interrupts can be globally enabled and disabled with

the STI and CLI instructions, respectively.)

The Blackfin processors have multiple, independent DMA con-

trollers that support automated data transfers with minimal

overhead for the processor core. DMA transfers can occur

between the processor’s internal memories and any of its DMA-

capable peripherals. Additionally, DMA transfers can be accom-

plished between any of the DMA-capable peripherals and

external devices connected to the external memory interfaces,

including the SDRAM controller and the asynchronous mem-

ory controller. DMA-capable peripherals include the Ethernet

MAC (ADSP-BF536 and ADSP-BF537 only), SPORTs, SPI port,

UARTs, and PPI. Each individual DMA-capable peripheral has

at least one dedicated DMA channel.

• CEC interrupt pending register (IPEND) – The IPEND

register keeps track of all nested events. A set bit in the

IPEND register indicates the event is currently active or

nested at some level. This register is updated automatically

by the controller but may be read while in supervisor mode.

The DMA controller supports both one-dimensional (1-D) and

two-dimensional (2-D) DMA transfers. DMA transfer initial-

ization can be implemented from registers or from sets of

parameters called descriptor blocks.

The SIC allows further control of event processing by providing

three 32-bit interrupt control and status registers. Each register

contains a bit corresponding to each of the peripheral interrupt

events shown in Table 3 on Page 7.

The 2-D DMA capability supports arbitrary row and column

sizes up to 64K elements by 64K elements, and arbitrary row

and column step sizes up to 32K elements. Furthermore, the

column step size can be less than the row step size, allowing

implementation of interleaved data streams. This feature is

especially useful in video applications where data can be de-

interleaved on the fly.

• SIC interrupt mask register (SIC_IMASK) – Controls the

masking and unmasking of each peripheral interrupt event.

When a bit is set in the register, that peripheral event is

unmasked and is processed by the system when asserted. A

cleared bit in the register masks the peripheral event, pre-

venting the processor from servicing the event.

Examples of DMA types supported by the DMA controller

include:

• SIC interrupt status register (SIC_ISR) – As multiple

peripherals can be mapped to a single event, this register

allows the software to determine which peripheral event

source triggered the interrupt. A set bit indicates the

peripheral is asserting the interrupt, and a cleared bit indi-

cates the peripheral is not asserting the event.

• A single, linear buffer that stops upon completion

• A circular, auto-refreshing buffer that interrupts on each

full or fractionally full buffer

• 1-D or 2-D DMA using a linked list of descriptors

• 2-D DMA using an array of descriptors, specifying only the

base DMA address within a common page.

Rev. B

| Page 8 of 68 | July 2006

ADSP-BF534/ADSP-BF536/ADSP-BF537

In addition to the dedicated peripheral DMA channels, there are

two memory DMA channels provided for transfers between the

various memories of the processor system. This enables trans-

fers of blocks of data between any of the memories—including

external SDRAM, ROM, SRAM, and flash memory—with mini-

mal processor intervention. Memory DMA transfers can be

controlled by a very flexible descriptor-based methodology or

by a standard register-based autobuffer mechanism.

RTXI

RTXO

R1

X1

C1

C2

The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors also

have an external DMA controller capability via dual external

DMA request pins when used in conjunction with the external

bus interface unit (EBIU). This functionality can be used when a

high speed interface is required for external FIFOs and high

bandwidth communications peripherals such as USB 2.0. It

allows control of the number of data transfers for memDMA.

The number of transfers per edge is programmable. This feature

can be programmed to allow memDMA to have an increased

priority on the external bus relative to the core.

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Figure 4. External Components for RTC

or general-purpose interrupt, if the timer expires before being

reset by software. The programmer initializes the count value of

the timer, enables the appropriate interrupt, then enables the

timer. Thereafter, the software must reload the counter before it

counts to zero from the programmed value. This protects the

system from remaining in an unknown state where software,

which would normally reset the timer, has stopped running due

to an external noise condition or software error.

REAL-TIME CLOCK

The real-time clock (RTC) provides a robust set of digital watch

features, including current time, stopwatch, and alarm. The

RTC is clocked by a 32.768 kHz crystal external to the

processor. The RTC peripheral has dedicated power supply pins

so that it can remain powered up and clocked even when the

rest of the processor is in a low-power state. The RTC provides

several programmable interrupt options, including interrupt

per second, minute, hour, or day clock ticks, interrupt on pro-

grammable stopwatch countdown, or interrupt at a

programmed alarm time.

If configured to generate a hardware reset, the watchdog timer

resets both the core and the processor peripherals. After a reset,

software can determine if the watchdog was the source of the

hardware reset by interrogating a status bit in the watchdog

timer control register.

The 32.768 kHz input clock frequency is divided down to a 1 Hz

signal by a prescaler. The counter function of the timer consists

of four counters: a 60-second counter, a 60-minute counter, a

24-hour counter, and an 32,768-day counter.

The timer is clocked by the system clock (SCLK), at a maximum

frequency of f_SCLK

.

TIMERS

When enabled, the alarm function generates an interrupt when

the output of the timer matches the programmed value in the

alarm control register. There are two alarms: The first alarm is

for a time of day, while the second alarm is for a day and time of

that day.

There are nine general-purpose programmable timer units in

the processor. Eight timers have an external pin that can be con-

figured either as a pulse width modulator (PWM) or timer

output, as an input to clock the timer, or as a mechanism for

measuring pulse widths and periods of external events. These

timers can be synchronized to an external clock input to the sev-

eral other associated PF pins, to an external clock input to the

PPI_CLK input pin, or to the internal SCLK.

The stopwatch function counts down from a programmed

value, with one-second resolution. When the stopwatch is

enabled and the counter underflows, an interrupt is generated.

Like the other peripherals, the RTC can wake up the processor

from sleep mode upon generation of any RTC wakeup event.

Additionally, an RTC wakeup event can wake up the processor

from deep sleep mode, and wake up the on-chip internal voltage

regulator from the hibernate operating mode.

The timer units can be used in conjunction with the two UARTs

and the CAN controller to measure the width of the pulses in

the data stream to provide a software auto-baud detect function

for the respective serial channels.

Connect RTC pins RTXI and RTXO with external components

as shown in Figure 4.

The timers can generate interrupts to the processor core provid-

ing periodic events for synchronization, either to the system

clock or to a count of external signals.

WATCHDOG TIMER

In addition to the eight general-purpose programmable timers,

a ninth timer is also provided. This extra timer is clocked by the

internal processor clock and is typically used as a system tick

clock for generating periodic interrupts in an operating system.

The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors

include a 32-bit timer that can be used to implement a software

watchdog function. A software watchdog can improve system

availability by forcing the processor to a known state through

generation of a hardware reset, nonmaskable interrupt (NMI),

Rev. B

|

Page 9 of 68 | July 2006

ADSP-BF534/ADSP-BF536/ADSP-BF537

port provides a full-duplex, synchronous serial interface, which

supports both master/slave modes and multimaster

environments.

SERIAL PORTS (SPORTs)

The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors

incorporate two dual-channel synchronous serial ports

(SPORT0 and SPORT1) for serial and multiprocessor commu-

nications. The SPORTs support the following features:

The SPI port’s baud rate and clock phase/polarities are pro-

grammable, and it has an integrated DMA controller,

configurable to support transmit or receive data streams. The

SPI’s DMA controller can only service unidirectional accesses at

any given time.

• I²S capable operation.

• Bidirectional operation – Each SPORT has two sets of inde-

pendent transmit and receive pins, enabling eight channels

of I²S stereo audio.

The SPI port’s clock rate is calculated as:

f_SCLK

2 × SPI_Baud

• Buffered (8-deep) transmit and receive ports – Each port

has a data register for transferring data words to and from

other processor components and shift registers for shifting

data in and out of the data registers.

--------------------------------

SPI Clock Rate =

Where the 16-bit SPI_Baud register contains a value of 2

to 65,535.

• Clocking – Each transmit and receive port can either use an

external serial clock or generate its own, in frequencies

ranging from (f_SCLK/131,070) Hz to (f_SCLK/2) Hz.

During transfers, the SPI port simultaneously transmits and

receives by serially shifting data in and out on its two serial data

lines. The serial clock line synchronizes the shifting and sam-

pling of data on the two serial data lines.

• Word length – Each SPORT supports serial data words

from 3 to 32 bits in length, transferred most significant bit

first or least significant bit first.

UART PORTS

• Framing – Each transmit and receive port can run with or

without frame sync signals for each data word. Frame sync

signals can be generated internally or externally, active high

or low, and with either of two pulse widths and early or late

frame sync.

The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors pro-

vide two full-duplex universal asynchronous receiver and

transmitter (UART) ports, which are fully compatible with PC-

standard UARTs. Each UART port provides a simplified UART

interface to other peripherals or hosts, supporting full-duplex,

DMA-supported, asynchronous transfers of serial data. A

UART port includes support for five to eight data bits, one or

two stop bits, and none, even, or odd parity. Each UART port

supports two modes of operation:

• Companding in hardware – Each SPORT can perform

A-law or μ-law companding according to ITU recommen-

dation G.711. Companding can be selected on the transmit

and/or receive channel of the SPORT without

additional latencies.

• PIO (programmed I/O) – The processor sends or receives

data by writing or reading I/O mapped UART registers.

The data is double-buffered on both transmit and receive.

• DMA operations with single-cycle overhead – Each SPORT

can automatically receive and transmit multiple buffers of

memory data. The processor can link or chain sequences of

DMA transfers between a SPORT and memory.

• DMA (direct memory access) – The DMA controller trans-

fers both transmit and receive data. This reduces the

number and frequency of interrupts required to transfer

data to and from memory. The UART has two dedicated

DMA channels, one for transmit and one for receive. These

DMA channels have lower default priority than most DMA

channels because of their relatively low service rates.

• Interrupts – Each transmit and receive port generates an

interrupt upon completing the transfer of a data word or

after transferring an entire data buffer, or buffers,

through DMA.

• Multichannel capability – Each SPORT supports 128 chan-

nels out of a 1024-channel window and is compatible with

the H.100, H.110, MVIP-90, and HMVIP standards.

Each UART port’s baud rate, serial data format, error code gen-

eration and status, and interrupts are programmable:

• Supporting bit rates ranging from (f_SCLK/1,048,576) to

(f_SCLK/16) bits per second.

SERIAL PERIPHERAL INTERFACE (SPI) PORT

The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors have

an SPI-compatible port that enables the processor to communi-

cate with multiple SPI-compatible devices.

• Supporting data formats from 7 to 12 bits per frame.

• Both transmit and receive operations can be configured to

generate maskable interrupts to the processor.

The SPI interface uses three pins for transferring data: two data

pins (Master Output-Slave Input, MOSI, and Master Input-

Slave Output, MISO) and a clock pin (serial clock, SCK). An SPI

chip select input pin (SPISS) lets other SPI devices select the

processor, and seven SPI chip select output pins (SPISEL7–1) let

the processor select other SPI devices. The SPI select pins are

reconfigured programmable flag pins. Using these pins, the SPI

The UART port’s clock rate is calculated as:

f_SCLK

16 × UART_Divisor

-----------------------------------------------

UART Clock Rate =

Where the 16-bit UARTx_Divisor comes from the DLH register

(most significant 8 bits) and UARTx_DLL register (least signifi-

cant 8 bits).

Rev. B

| Page 10 of 68 | July 2006

ADSP-BF534/ADSP-BF536/ADSP-BF537

In conjunction with the general-purpose timer functions, auto-

baud detection is supported.

10/100 ETHERNET MAC

The ADSP-BF536 and ADSP-BF537 processors offer the capa-

bility to directly connect to a network by way of an embedded

Fast Ethernet Media Access Controller (MAC) that supports

both 10-BaseT (10M bits/sec) and 100-BaseT (100M bits/sec)

operation. The 10/100 Ethernet MAC peripheral is fully compli-

ant to the IEEE 802.3-2002 standard, and it provides

The capabilities of the UARTs are further extended with sup-

port for the infrared data association (IrDA) serial infrared

physical layer link specification (SIR) protocol.

CONTROLLER AREA NETWORK (CAN)

The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors offer

a CAN controller that is a communication controller imple-

menting the CAN 2.0B (active) protocol. This protocol is an

asynchronous communications protocol used in both industrial

and automotive control systems. The CAN protocol is well-

suited for control applications due to its capability to communi-

cate reliably over a network, since the protocol incorporates

CRC checking message error tracking, and fault node

confinement.

programmable features designed to minimize supervision, bus

use, or message processing by the rest of the processor system.

Some standard features are:

• Support of MII and RMII protocols for external PHYs.

• Full duplex and half duplex modes.

• Data framing and encapsulation: generation and detection

of preamble, length padding, and FCS.

• Media access management (in half-duplex operation): col-

lision and contention handling, including control of

retransmission of collision frames and of back-off timing.

The CAN controller offers the following features:

• 32 mailboxes (eight receive only, eight transmit only, 16

configurable for receive or transmit).

• Flow control (in full-duplex operation): generation and

detection of PAUSE frames.

• Dedicated acceptance masks for each mailbox.

• Additional data filtering on first two bytes.

• Station management: generation of MDC/MDIO frames

for read-write access to PHY registers.

• Support for both the standard (11-bit) and extended

(29-bit) identifier (ID) message formats.

• SCLK operating range down to 25 MHz (active and sleep

operating modes).

• Support for remote frames.

• Internal loopback from Tx to Rx.

Some advanced features are:

• Active or passive network support.

• CAN wakeup from hibernation mode (lowest static power

consumption mode).

• Buffered crystal output to external PHY for support of a

single crystal system.

• Interrupts, including: Tx complete, Rx complete, error,

global.

• Automatic checksum computation of IP header and IP

payload fields of Rx frames.

The electrical characteristics of each network connection are

very demanding so the CAN interface is typically divided into

two parts: a controller and a transceiver. This allows a single

controller to support different drivers and CAN networks. The

CAN module represents only the controller part of the interface.

The controller interface supports connection to 3.3 V high-

speed, fault-tolerant, single-wire transceivers.

• Independent 32-bit descriptor-driven Rx and Tx DMA

channels.

• Frame status delivery to memory via DMA, including

frame completion semaphores, for efficient buffer queue

management in software.

• Tx DMA support for separate descriptors for MAC header

and payload to eliminate buffer copy operations.

TWI CONTROLLER INTERFACE

The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors

include a 2-wire interface (TWI) module for providing a simple

exchange method of control data between multiple devices. The

TWI is compatible with the widely used I²C^®bus standard. The

TWI module offers the capabilities of simultaneous master and

slave operation, support for both 7-bit addressing and multime-

dia data arbitration. The TWI interface utilizes two pins for

transferring clock (SCL) and data (SDA) and supports the

protocol at speeds up to 400k bits/sec. The TWI interface pins

are compatible with 5 V logic levels.

• Convenient frame alignment modes support even 32-bit

alignment of encapsulated Rx or Tx IP packet data in mem-

ory after the 14-byte MAC header.

• Programmable Ethernet event interrupt supports any com-

bination of:

• Any selected Rx or Tx frame status conditions.

• PHY interrupt condition.

• Wakeup frame detected.

• Any selected MAC management counter(s) at

half-full.

Additionally, the processor’s TWI module is fully compatible

with serial camera control bus (SCCB) functionality for easier

control of various CMOS camera sensor devices.

• DMA descriptor error.

• 47 MAC management statistics counters with selectable

clear-on-read behavior and programmable interrupts on

half maximum value.

Rev. B

| Page 11 of 68 | July 2006

ADSP-BF534/ADSP-BF536/ADSP-BF537

• Programmable Rx address filters, including a 64-bit

address hash table for multicast and/or unicast frames, and

programmable filter modes for broadcast, multicast, uni-

cast, control, and damaged frames.

GPIO pins defined as inputs can be configured to generate

hardware interrupts, while output pins can be triggered by

software interrupts.

• GPIO interrupt sensitivity registers – The two GPIO inter-

rupt sensitivity registers specify whether individual pins are

level- or edge-sensitive and specify—if edge-sensitive—

whether just the rising edge or both the rising and falling

edges of the signal are significant. One register selects the

type of sensitivity, and one register selects which edges are

significant for edge-sensitivity.

• Advanced power management supporting unattended

transfer of Rx and Tx frames and status to/from external

memory via DMA during low-power sleep mode.

• System wakeup from sleep operating mode upon magic

packet or any of four user-definable wakeup frame filters.

• Support for 802.3Q tagged VLAN frames.

PARALLEL PERIPHERAL INTERFACE (PPI)

• Programmable MDC clock rate and preamble suppression.

The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors pro-

vide a parallel peripheral interface (PPI) that can connect

directly to parallel A/D and D/A converters, ITU-R-601/656

video encoders and decoders, and other general-purpose

peripherals. The PPI consists of a dedicated input clock pin, up

to 3 frame synchronization pins, and up to 16 data pins.

• In RMII operation, 7 unused pins may be configured as

GPIO pins for other purposes.

PORTS

The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors

group the many peripheral signals to four ports—Port F, Port G,

Port H, and Port J. Most of the associated pins are shared by

multiple signals. The ports function as multiplexer controls.

Eight of the pins (Port F7–0) offer high source/high sink current

capabilities.

In ITU-R-656 modes, the PPI receives and parses a data stream

of 8-bit or 10-bit data elements. On-chip decode of embedded

preamble control and synchronization information

is supported.

Three distinct ITU-R-656 modes are supported:

General-Purpose I/O (GPIO)

• Active video only mode – The PPI does not read in any

data between the End of Active Video (EAV) and Start of

Active Video (SAV) preamble symbols, or any data present

during the vertical blanking intervals. In this mode, the

control byte sequences are not stored to memory; they are

filtered by the PPI.

The processors have 48 bidirectional, general-purpose I/O

(GPIO) pins allocated across three separate GPIO modules—

PORTFIO, PORTGIO, and PORTHIO, associated with Port F,

Port G, and Port H, respectively. Port J does not provide GPIO

functionality. Each GPIO-capable pin shares functionality with

other processor peripherals via a multiplexing scheme; however,

the GPIO functionality is the default state of the device upon

power-up. Neither GPIO output or input drivers are active by

default. Each general-purpose port pin can be individually con-

trolled by manipulation of the port control, status, and interrupt

registers:

• Vertical blanking only mode – The PPI only transfers verti-

cal blanking interval (VBI) data, as well as horizontal

blanking information and control byte sequences on

VBI lines.

• Entire field mode – The entire incoming bitstream is read

in through the PPI. This includes active video, control pre-

amble sequences, and ancillary data that may be embedded

in horizontal and vertical blanking intervals.

• GPIO direction control register – Specifies the direction of

each individual GPIO pin as input or output.

• GPIO control and status registers – The processors employ

a “write one to modify” mechanism that allows any combi-

nation of individual GPIO pins to be modified in a single

instruction, without affecting the level of any other GPIO

pins. Four control registers are provided. One register is

written in order to set pin values, one register is written in

order to clear pin values, one register is written in order to

toggle pin values, and one register is written in order to

specify a pin value. Reading the GPIO status register allows

software to interrogate the sense of the pins.

Though not explicitly supported, ITU-R-656 output functional-

ity can be achieved by setting up the entire frame structure

(including active video, blanking, and control information) in

memory and streaming the data out the PPI in a frame sync-less

mode. The processor’s 2-D DMA features facilitate this transfer

by allowing the static frame buffer (blanking and control codes)

to be placed in memory once, and simply updating the active

video information on a per-frame basis.

The general-purpose modes of the PPI are intended to suit a

wide variety of data capture and transmission applications. The

modes are divided into four main categories, each allowing up

to 16 bits of data transfer per PPI_CLK cycle:

• GPIO interrupt mask registers – The two GPIO interrupt

mask registers allow each individual GPIO pin to function

as an interrupt to the processor. Similar to the two GPIO

control registers that are used to set and clear individual

pin values, one GPIO interrupt mask register sets bits to

enable interrupt function, and the other GPIO interrupt

mask register clears bits to disable interrupt function.

• Data receive with internally generated frame syncs

• Data receive with externally generated frame syncs

• Data transmit with internally generated frame syncs

• Data transmit with externally generated frame syncs

Rev. B

| Page 12 of 68 | July 2006

ADSP-BF534/ADSP-BF536/ADSP-BF537

These modes support ADC/DAC connections, as well as video

communication with hardware signalling. Many of the modes

support more than one level of frame synchronization. If

desired, a programmable delay can be inserted between asser-

tion of a frame sync and reception/transmission of data.

System DMA access to L1 memory is not supported in

sleep mode.

Deep Sleep Operating Mode—Maximum Dynamic Power

Savings

The deep sleep mode maximizes dynamic power savings by dis-

abling the clocks to the processor core (CCLK) and to all

synchronous peripherals (SCLK). Asynchronous peripherals,

such as the RTC, may still be running but cannot access internal

resources or external memory. This powered-down mode can

only be exited by assertion of the reset interrupt (RESET) or by

an asynchronous interrupt generated by the RTC. When in deep

sleep mode, an RTC asynchronous interrupt causes the proces-

sor to transition to the active mode. Assertion of RESET while

in deep sleep mode causes the processor to transition to the full-

on mode.

DYNAMIC POWER MANAGEMENT

The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors pro-

vide five operating modes, each with a different performance

and power profile. In addition, dynamic power management

provides the control functions to dynamically alter the proces-

sor core supply voltage, further reducing power dissipation.

Control of clocking to each of the peripherals also reduces

power consumption. See Table 4 for a summary of the power

settings for each mode.

Full-On Operating Mode—Maximum Performance

Hibernate Operating Mode—Maximum Static Power

Savings

In the full-on mode, the PLL is enabled and is not bypassed,

providing capability for maximum operational frequency. This

is the power-up default execution state in which maximum per-

formance can be achieved. The processor core and all enabled

peripherals run at full speed.

The hibernate mode maximizes static power savings by dis-

abling the voltage and clocks to the processor core (CCLK) and

to all of the synchronous peripherals (SCLK). The internal volt-

age regulator for the processor can be shut off by writing b#00 to

the FREQ bits of the VR_CTL register. This disables both CCLK

and SCLK. Furthermore, it sets the internal power supply volt-

age (V_DDINT) to 0 V to provide the greatest power savings. To

preserve the processor state, prior to removing power, any criti-

cal information stored internally (memory contents, register

contents, etc.) must be written to a non volatile storage device.

Active Operating Mode—Moderate Power Savings

In the active mode, the PLL is enabled but bypassed. Because the

PLL is bypassed, the processor’s core clock (CCLK) and system

clock (SCLK) run at the input clock (CLKIN) frequency. In this

mode, the CLKIN to CCLK multiplier ratio can be changed,

although the changes are not realized until the full-on mode is

entered. DMA access is available to appropriately configured

L1 memories.

Since V_DDEXTis still supplied in this mode, all of the external pins

three-state, unless otherwise specified. This allows other devices

that are connected to the processor to still have power applied

without drawing unwanted current.

In the active mode, it is possible to disable the PLL through the

PLL control register (PLL_CTL). If disabled, the PLL must be

re-enabled before transitioning to the full-on or sleep modes.

The Ethernet or CAN modules can wake up the internal supply

regulator. The regulator can also be woken up by a real-time

clock wakeup event or by asserting the RESET pin, both of

which initiate the hardware reset sequence.

Table 4. Power Settings

Core

Clock

System

Clock

Internal

Power

PLL

With the exception of the VR_CTL and the RTC registers, all

(VDDINT) internal registers and memories lose their content in the hiber-

Mode

Full On

Active

PLL

Bypassed (CCLK)

(SCLK)

nate state. State variables may be held in external SRAM or

SDRAM. The CKELOW bit in the VR_CTL register controls

whether SDRAM operates in self-refresh mode which allows it

to retain its content while the processor is in reset.

Enabled

No

Enabled Enabled On

Enabled/ Yes

Disabled

Sleep

Enabled

—

Disabled Enabled On

Disabled Disabled On

Disabled Disabled Off

Power Savings

Deep Sleep Disabled

Hibernate Disabled

As shown in Table 5, the processors support three different

power domains which maximizes flexibility, while maintaining

compliance with industry standards and conventions. By isolat-

ing the internal logic of the processor into its own power

domain, separate from the RTC and other I/O, the processor

can take advantage of dynamic power management, without

affecting the RTC or other I/O devices. There are no sequencing

requirements for the various power domains.

Sleep Operating Mode—High Dynamic Power Savings

The sleep mode reduces dynamic power dissipation by disabling

the clock to the processor core (CCLK). The PLL and system

clock (SCLK), however, continue to operate in this mode. Typi-

cally an external event or RTC activity wakes up the processor.

When in the sleep mode, asserting wakeup causes the processor

to sense the value of the BYPASS bit in the PLL control register

(PLL_CTL). If BYPASS is disabled, the processor transitions to

the full on mode. If BYPASS is enabled, the processor transi-

tions to the active mode.

Rev. B

| Page 13 of 68 | July 2006

ADSP-BF534/ADSP-BF536/ADSP-BF537

Table 5. Power Domains

V

DDEXT

DDINT

Power Domain

V_DDRange

V_DDINT

100µF

2.25V TO 3.6V

INPUT VOLTAGE

RANGE

All internal logic, except RTC

RTC internal logic and crystal I/O

All other I/O

V_DDRTC

10µH

V_DDEXT

0.1µF

ZHCS1000

NDS8434

100µF

1µF

The dynamic power management feature allows both the pro-

cessor’s input voltage (V_DDINT) and clock frequency (f_CCLK) to be

dynamically controlled.

VR

1-0

OUT

The power dissipated by a processor is largely a function of its

clock frequency and the square of the operating voltage. For

example, reducing the clock frequency by 25% results in a 25%

reduction in power dissipation, while reducing the voltage by

25% reduces power dissipation by more than 40%. Further,

these power savings are additive, in that if the clock frequency

and supply voltage are both reduced, the power savings can be

dramatic, as shown in the following equations.

EXTERNAL COMPONENTS

1-0 SHOULD BE TIED TOGETHER EXTERNALLY

NOTE: VR

OUT

AND DESIGNER SHOULD MINIMIZE TRACE LENGTH TO NDS8434.

Figure 5. Voltage Regulator Circuit

CLOCK SIGNALS

The power savings factor is calculated as:

The ADSP-BF534/ADSP-BF536/ADSP-BF537 processor can be

clocked by an external crystal, a sine wave input, or a buffered,

shaped clock derived from an external clock oscillator.

power savings factor

2

f_CCLKRED

---------------------

f_CCLKNOM

V_DDINTRED

--------------------------

V_DDINTNOM

T_RED

------------

T_NOM

⎛

⎝

⎞

⎠

⎛

⎝

⎞

⎠

=

×

If an external clock is used, it should be a TTL compatible signal

and must not be halted, changed, or operated below the speci-

fied frequency during normal operation. This signal is

connected to the processor’s CLKIN pin. When an external

clock is used, the XTAL pin must be left unconnected.

where the variables in the equations are:

f

_CCLKNOMis the nominal core clock frequency

_CCLKREDis the reduced core clock frequency

f

Alternatively, because the processors include an on-chip oscilla-

tor circuit, an external crystal may be used. For fundamental

frequency operation, use the circuit shown in Figure 6. A

parallel-resonant, fundamental frequency, microprocessor-

grade crystal is connected across the CLKIN and XTAL pins.

The on-chip resistance between CLKIN and the XTAL pin is in

the 500 kΩ range. Further parallel resistors are typically not rec-

ommended. The two capacitors and the series resistor shown in

Figure 6 fine-tune phase and amplitude of the sine frequency.

V

_DDINTNOMis the nominal internal supply voltage

_DDINTREDis the reduced internal supply voltage

T

_NOMis the duration running at f_CCLKNOM

_REDis the duration running at f_CCLKRED

T

The percent power savings is calculated as:

% power savings = (1 – power savings factor) × 100%

The capacitor and resistor values shown in Figure 6 are typical

values only. The capacitor values are dependent upon the crystal

manufacturers’ load capacitance recommendations and the PCB

physical layout. The resistor value depends on the drive level

specified by the crystal manufacturer. The user should verify the

customized values based on careful investigations of multiple

devices over temperature range.

VOLTAGE REGULATION

The ADSP-BF534/ADSP-BF536/ADSP-BF537 processor pro-

vides an on-chip voltage regulator that can generate processor

core voltage levels (0.85 V to 1.2 V guaranteed from –5% to

+10%) from an external 2.25 V to 3.6 V supply. Figure 5 shows

the typical external components required to complete the power

management system. The regulator controls the internal logic

voltage levels and is programmable with the voltage regulator

control register (VR_CTL) in increments of 50 mV. To reduce

standby power consumption, the internal voltage regulator can

be programmed to remove power to the processor core while

keeping I/O power supplied. While in hibernate mode, V_DDEXT

can still be applied, eliminating the need for external buffers.

The voltage regulator can be activated from this power-down

state by asserting the RESET pin, which then initiates a boot

sequence. The regulator can also be disabled and bypassed at the

user’s discretion.

A third-overtone crystal can be used for frequencies above

25 MHz. The circuit is then modified to ensure crystal operation

only at the third overtone, by adding a tuned inductor circuit as

shown in Figure 6. A design procedure for third-overtone oper-

ation is discussed in detail in application note EE-168.

The CLKBUF pin is an output pin, and is a buffer version of the

input clock. This pin is particularly useful in Ethernet applica-

tions to limit the number of required clock sources in the

system. In this type of application, a single 25 MHz or 50 MHz

crystal may be applied directly to the processors. The 25 MHz or

50 MHz output of CLKBUF can then be connected to an exter-

nal Ethernet MII or RMII PHY device.

Rev. B

| Page 14 of 68 | July 2006

ADSP-BF534/ADSP-BF536/ADSP-BF537

BLACKFIN

“FINE” ADJUSTMENT

REQUIRES PLL SEQUENCING

“COURSE” ADJUSTMENT

ON THE FLY

CLKOUT

CLKBUF

TO PLL CIRCUITRY

EN

، 1, 2, 4, 8

، 1 TO 15

CCLK

PLL

0.5ϫ - 64ϫ

CLKIN

VCO

SCLK

CLKIN

18pF*

XTAL

330⍀*

SCLK ≤ CCLK

SCLK ≤ 133MHz

FOR OVERTONE

OPERATION ONLY:

Figure 7. Frequency Modification Methods

18pF*

Note that the divisor ratio must be chosen to limit the system

clock frequency to its maximum of f_SCLK. The SSEL value can be

changed dynamically without any PLL lock latencies by writing

the appropriate values to the PLL divisor register (PLL_DIV).

NOTE: VALUES MARKED WITH * MUST BE CUSTOMIZED

DEPENDING ON THE CRYSTAL AND LAYOUT. PLEASE

ANALYZE CAREFULLY.

Figure 6. External Crystal Connections

Table 6. Example System Clock Ratios

Because of the default 10x PLL multiplier, providing a 50 MHz

CLKIN exceeds the recommended operating conditions of the

lower speed grades. Because of this restriction, a 50 MHz RMII

PHY cannot be clocked directly from the CLKBUF pin. Either

provide a separate 50 MHz clock source, or use an RMII PHY

with 25 MHz clock input options. The CLKBUF output is active

by default and can be disabled using the VR_CTL register for

power savings.

Example Frequency Ratios

(MHz)

VCO

100

Signal Name Divider Ratio

SSEL3–0

VCO/SCLK

SCLK

100

50

0001

1:1

0110

6:1

300

1010

10:1

500

50

The Blackfin core runs at a different clock rate than the on-chip

peripherals. As shown in Figure 7, the core clock (CCLK) and

system peripheral clock (SCLK) are derived from the input

clock (CLKIN) signal. An on-chip PLL is capable of multiplying

the CLKIN signal by a programmable 0.5× to 64× multiplication

factor (bounded by specified minimum and maximum VCO

frequencies). The default multiplier is 10×, but it can be modi-

fied by a software instruction sequence in the PLL_CTL register.

The core clock (CCLK) frequency can also be dynamically

changed by means of the CSEL1–0 bits of the PLL_DIV register.

Supported CCLK divider ratios are 1, 2, 4, and 8, as shown in

Table 7. This programmable core clock capability is useful for

fast core frequency modifications.

Table 7. Core Clock Ratios

On-the-fly CCLK and SCLK frequency changes can be effected

by simply writing to the PLL_DIV register. Whereas the maxi-

mum allowed CCLK and SCLK rates depend on the applied

voltages V_DDINTand V_DDEXT, the VCO is always permitted to run

up to the frequency specified by the part’s speed grade. The

CLKOUT pin reflects the SCLK frequency to the off-chip world.

It belongs to the SDRAM interface, but it functions as reference

signal in other timing specifications as well. While active by

default, it can be disabled using the EBIU_SDGCTL and

EBIU_AMGCTL registers.

Example Frequency Ratios

(MHz)

VCO

300

Signal Name Divider Ratio

CSEL1–0

VCO/CCLK

CCLK

300

150

125

25

00

01

10

11

1:1

2:1

4:1

8:1

300

500

200

The maximum CCLK frequency not only depends on the part’s

speed grade (see Ordering Guide on Page 66), it also depends on

the applied V_DDINTvoltage. See Table 12 and Table 13 for details.

The maximal system clock rate (SCLK) depends on the chip

package and the applied V_DDEXTvoltage (see Table 16).

All on-chip peripherals are clocked by the system clock (SCLK).

The system clock frequency is programmable by means of the

SSEL3–0 bits of the PLL_DIV register. The values programmed

into the SSEL fields define a divide ratio between the PLL output

(VCO) and the system clock. SCLK divider values are 1 through

15. Table 6 illustrates typical system clock ratios.

Rev. B

| Page 15 of 68 | July 2006

ADSP-BF534/ADSP-BF536/ADSP-BF537

any more bytes until the flag is deasserted. The flag is cho-

sen by the user and this information is transferred to the

Blackfin processor via bits 10:5 of the FLAG header.

BOOTING MODES

The ADSP-BF534/ADSP-BF536/ADSP-BF537 processor has six

mechanisms (listed in Table 8) for automatically loading inter-

nal and external memory after a reset. A seventh mode is

provided to execute from external memory, bypassing the boot

sequence.

• Boot from UART – Using an autobaud handshake

sequence, a boot-stream-formatted program is downloaded

by the host. The host agent selects a baud rate within the

UART’s clocking capabilities. When performing the auto-

baud, the UART expects an “@” (boot stream) character

(8 bits data, 1 start bit, 1 stop bit, no parity bit) on the RXD

pin to determine the bit rate. It then replies with an

acknowledgement that is composed of 4 bytes: 0xBF, the

value of UART_DLL, the value of UART_DLH, and 0x00.

The host can then download the boot stream. When the

processor needs to hold off the host, it deasserts CTS.

Therefore, the host must monitor this signal.

Table 8. Booting Modes

BMODE2–0

Description

000

Executefrom16-bitexternalmemory(bypass

boot ROM)

001

Boot from 8-bit or 16-bit memory

(EPROM/flash)

010

011

100

101

110

111

Reserved

• Boot from serial TWI memory (EEPROM/flash) – The

Blackfin processor operates in master mode and selects the

TWI slave with the unique ID 0xA0. It submits successive

read commands to the memory device starting at two byte

internal address 0x0000 and begins clocking data into the

processor. The TWI memory device should comply with

Philips I²C Bus Specification version 2.1 and have the capa-

bility to auto-increment its internal address counter such

that the contents of the memory device can be read

sequentially.

Boot from serial SPI memory (EEPROM/flash)

Boot from SPI host (slave mode)

Boot from serial TWI memory (EEPROM/flash)

Boot from TWI host (slave mode)

Boot from UART host (slave mode)

The BMODE pins of the reset configuration register, sampled

during power-on resets and software-initiated resets, imple-

ment the following modes:

• Boot from TWI host – The TWI host agent selects the slave

with the unique ID 0x5F. The processor replies with an

acknowledgement and the host can then download the

boot stream. The TWI host agent should comply with

Philips I²C Bus Specification version 2.1. An I²C multi-

plexer can be used to select one processor at a time when

booting multiple processors from a single TWI.

• Execute from 16-bit external memory – Execution starts

from address 0x2000 0000 with 16-bit packing. The boot

ROM is bypassed in this mode. All configuration settings

are set for the slowest device possible (3-cycle hold time;

15-cycle R/W access times; 4-cycle setup).

• Boot from 8-bit and 16-bit external flash memory – The

8-bit or 16-bit flash boot routine located in Boot ROM

memory space is set up using asynchronous memory bank

0. All configuration settings are set for the slowest device

possible (3-cycle hold time; 15-cycle R/W access times;

4-cycle setup). The Boot ROM evaluates the first byte of the

boot stream at address 0x2000 0000. If it is 0x40, 8-bit boot

is performed. A 0x60 byte assumes a 16-bit memory device

and performs 8-bit DMA. A 0x20 byte also assumes 16-bit

memory but performs 16-bit DMA.

For each of the boot modes, a 10-byte header is first brought in

from an external device. The header specifies the number of

bytes to be transferred and the memory destination address.

Multiple memory blocks may be loaded by any boot sequence.

Once all blocks are loaded, program execution commences from

the start of L1 instruction SRAM.

In addition, Bit 4 of the reset configuration register can be set by

application code to bypass the normal boot sequence during a

software reset. For this case, the processor jumps directly to the

beginning of L1 instruction memory.

• Boot from serial SPI memory (EEPROM or flash) – 8-, 16-,

or 24-bit addressable devices are supported as well as

AT45DB041, AT45DB081, AT45DB161, AT45DB321,

AT45DB642, and AT45DB1282 DataFlash^®devices from

Atmel. The SPI uses the PF10/SPI SSEL1 output pin to

select a single SPI EEPROM/flash device, submits a read

command and successive address bytes (0x00) until a valid

8-, 16-, or 24-bit, or Atmel addressable device is detected,

and begins clocking data into the processor.

To augment the boot modes, a secondary software loader can be

added to provide additional booting mechanisms. This second-

ary loader could provide the capability to boot from flash,

variable baud rate, and other sources. In all boot modes except

bypass, program execution starts from on-chip L1 memory

address 0xFFA0 0000.

INSTRUCTION SET DESCRIPTION

• Boot from SPI host device – The Blackfin processor oper-

ates in SPI slave mode and is configured to receive the bytes

of the .LDR file from an SPI host (master) agent. To hold

off the host device from transmitting while the boot ROM

is busy, the Blackfin processor asserts a GPIO pin, called

host wait (HWAIT), to signal the host device not to send

The Blackfin processor family assembly language instruction set

employs an algebraic syntax designed for ease of coding and

readability. The instructions have been specifically tuned to pro-

vide a flexible, densely encoded instruction set that compiles to

a very small final memory size. The instruction set also provides

fully featured multifunction instructions that allow the

Rev. B

| Page 16 of 68 | July 2006

ADSP-BF534/ADSP-BF536/ADSP-BF537

programmer to use many of the processor core resources in a

single instruction. Coupled with many features more often seen

on microcontrollers, this instruction set is very efficient when

compiling C and C++ source code. In addition, the architecture

supports both user (algorithm/application code) and supervisor

(O/S kernel, device drivers, debuggers, ISRs) modes of opera-

tion, allowing multiple levels of access to core processor

resources.

designer’s development schedule, increasing productivity. Sta-

tistical profiling enables the programmer to nonintrusively poll

the processor as it is running the program. This feature, unique

to VisualDSP++, enables the software developer to passively

gather important code execution metrics without interrupting

the real-time characteristics of the program. Essentially, the

developer can identify bottlenecks in software quickly and effi-

ciently. By using the profiler, the programmer can focus on

those areas in the program that impact performance and take

corrective action.

The assembly language, which takes advantage of the proces-

sor’s unique architecture, offers the following advantages:

Debugging both C/C++ and assembly programs with the

VisualDSP++ debugger, programmers can:

• Seamlessly integrated DSP/MCU features are optimized for

both 8-bit and 16-bit operations.

• View mixed C/C++ and assembly code (interleaved source

and object information).

• A multi-issue load/store modified-Harvard architecture,

which supports two 16-bit MAC or four 8-bit ALU + two

load/store + two pointer updates per cycle.

• Insert breakpoints.

• All registers, I/O, and memory are mapped into a unified

4G byte memory space, providing a simplified program-

ming model.

• Set conditional breakpoints on registers, memory, and

stacks.

• Trace instruction execution.

• Microcontroller features, such as arbitrary bit and bit-field

manipulation, insertion, and extraction; integer operations

on 8-, 16-, and 32-bit data-types; and separate user and

supervisor stack pointers.

• Perform linear or statistical profiling of program execution.

• Fill, dump, and graphically plot the contents of memory.

• Perform source level debugging.

• Code density enhancements, which include intermixing of

16-bit and 32-bit instructions (no mode switching, no code

segregation). Frequently used instructions are encoded

in 16 bits.

• Create custom debugger windows.

The VisualDSP++ IDE lets programmers define and manage

software development. Its dialog boxes and property pages let

programmers configure and manage all development tools,

including color syntax highlighting in the VisualDSP++ editor.

These capabilities permit programmers to:

DEVELOPMENT TOOLS

The Blackfin is supported with a complete set of

• Control how the development tools process inputs and

generate outputs.

CROSSCORE^®^†software and hardware development tools,

‡

including Analog Devices emulators and the VisualDSP++^®

development environment. The same emulator hardware that

supports other Analog Devices processors also fully emulates

the Blackfin.

• Maintain a one-to-one correspondence with the tool’s

command line switches.

The VisualDSP++ Kernel (VDK) incorporates scheduling and

resource management tailored specifically to address the mem-

ory and timing constraints of embedded, real-time

The VisualDSP++ project management environment lets pro-

grammers develop and debug an application. This environment

includes an easy to use assembler that is based on an algebraic

syntax, an archiver (librarian/library builder), a linker, a loader,

a cycle-accurate instruction-level simulator, a C/C++ compiler,

and a C/C++ runtime library that includes DSP and mathemati-

cal functions. A key point for these tools is C/C++ code

efficiency. The compiler has been developed for efficient

translation of C/C++ code to Blackfin assembly. The Blackfin

processor has architectural features that improve the efficiency

of compiled C/C++ code.

programming. These capabilities enable engineers to develop

code more effectively, eliminating the need to start from the

very beginning when developing new application code. The

VDK features include threads, critical and unscheduled regions,

semaphores, events, and device flags. The VDK also supports

priority-based, pre-emptive, cooperative, and time-sliced sched-

uling approaches. In addition, the VDK was designed to be

scalable. If the application does not use a specific feature, the

support code for that feature is excluded from the target system.

The VisualDSP++ debugger has a number of important fea-

tures. Data visualization is enhanced by a plotting package that

offers a significant level of flexibility. This graphical representa-

tion of user data enables the programmer to quickly determine

the performance of an algorithm. As algorithms grow in com-

plexity, this capability can have increasing significance on the

Because the VDK is a library, a developer can decide whether to

use it or not. The VDK is integrated into the VisualDSP++

development environment, but can also be used with standard

command line tools. When the VDK is used, the development

environment assists the developer with many error prone tasks

and assists in managing system resources, automating the gen-

eration of various VDK-based objects, and visualizing the

system state when debugging an application that uses the VDK.

^†CROSSCORE is a registered trademark of Analog Devices, Inc.

^‡VisualDSP++ is a registered trademark of Analog Devices, Inc.

Rev. B

| Page 17 of 68 | July 2006

ADSP-BF534/ADSP-BF536/ADSP-BF537

VCSE is Analog Devices’ technology for creating, using, and

reusing software components (independent modules of sub-

stantial functionality) to quickly and reliably assemble software

applications. Components can be downloaded from the Web

and dropped into the application. Component archives can be

published from within VisualDSP++. VCSE supports compo-

nent implementation in C/C++ or assembly language.

(EE-68) on the Analog Devices website under

www.analog.com/ee-notes. This document is updated regularly

to keep pace with improvements to emulator support.


型号：	ADSP-BF536
厂家：	ADI
描述：	Blackfin Embedded Processor Blackfin嵌入式处理器
文件：	总68页 (文件大小：2430K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADSP-BF536 [ADI]

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