ADSP-BF538 [ADI]
Blackfin Embedded Processor; Blackfin嵌入式处理器型号: | ADSP-BF538 |
厂家: | ADI |
描述: | Blackfin Embedded Processor |
文件: | 总56页 (文件大小:3080K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Blackfin®
Embedded Processor
a
Preliminary Technical Data
FEATURES
Up to 500 MHz high performance Blackfin processor
Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs,
40-bit shifter
ADSP-BF538/ADSP-BF538F
Memory management unit providing memory protection
External memory controller with glueless support
for SDRAM, SRAM, flash, and ROM
Flexible memory booting options from SPI® and external
memory
RISC-like register and instruction model for ease of pro-
gramming and compiler friendly support
PERIPHERALS
Advanced debug, trace, and performance monitoring
0.8 V to 1.2 V core VDD with on-chip voltage regulation
3.3 V tolerant I/O with specific 5 V tolerant pins
316-ball Pb-free mini-BGA package
Parallel peripheral interface (PPI/GPIO)
supporting ITU-R 656 video data formats
Four dual-channel, full-duplex synchronous serial ports, sup-
porting 16 stereo I2S® channels
Two DMA controllers supporting 26 DMA channels
Controller area network (CAN) 2.0B controller
Three SPI-compatible ports
Three timer/counters with PWM support
Three UARTs with support for IrDA®
Two TWI controllers compatible with I2C® industry standard
Up to 54 general-purpose I/O pins (GPIO)
Real time clock, watchdog timer, and core timer
On-chip PLL capable of 0.5x To 64x frequency multiplication
Debug/JTAG interface
MEMORY
148K bytes of on-chip memory:
16K bytes of instruction SRAM/cache
64K bytes of instruction SRAM
32K bytes of data SRAM
32K bytes of data SRAM/cache
4K bytes of scratchpad SRAM
512K bytes or 1M byte of flash memory (ADSP-BF538F parts
only)
Four dual-channel memory DMA controllers
JTAG TEST AND EMULATION
VOLTAGE REGULATOR
INTERRUPT
WATCHDOG
CONTROLLER
TIMER
B
TWI0-1
RTC
CAN 2.0B
GPIO
PORT
C
L1
L1
DATA
MEMORY
PPI
GPIO
SPI1-2
INSTRUCTION
MEMORY
GPIO
PORT
F
TIMER0-2
SPI0
DMA CORE
BUS 1
DMA ACCESS
BUS 1
GPIO
PORT
D
DMA ACCESS
BUS 0
DMA CORE
BUS 0
UART1-2
UART0
SPORT0-1
DMA
CONTROLLER1
GPIO
PORT
E
EXTERNAL PORT
FLASH, SDRAM CONTROL
DMA
CONTROLLER0
SPORT2-3
DMA
EXTERNAL
BUS 1
DMA
EXTERNAL
BUS 0
512 KB OR 1 MB
FLASH MEMORY
BOOT ROM
(ADSP-BF538F ONLY)
Figure 1. Functional Block Diagram
Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc.
Rev. PrD
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
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registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
© 2006 Analog Devices, Inc. All rights reserved.
Preliminary Technical Data
ADSP-BF538/ADSP-BF538F
TABLE OF CONTENTS
Operating Conditions ........................................... 22
Operating Conditions—Applies to 5V Tolerant pins .... 22
Electrical Characteristics ....................................... 22
Absolute Maximum Ratings ................................... 23
Package Information ............................................ 23
ESD Sensitivity ................................................... 23
Timing Specifications ........................................... 24
Clock and Reset Timing ..................................... 24
Asynchronous Memory Read Cycle Timing ............ 25
Asynchronous Memory Write Cycle Timing ........... 27
SDRAM Interface Timing .................................. 29
External Port Bus Request and Grant Cycle Timing .. 30
Parallel Peripheral Interface Timing ...................... 32
Serial Port Timing ............................................ 35
Serial Peripheral Interface Port—Master Timing ...... 39
Serial Peripheral Interface Port—Slave Timing ........ 40
General-Purpose Port Timing ............................. 41
Timer Cycle Timing .......................................... 42
JTAG Test And Emulation Port Timing ................. 43
Output Drive Currents ......................................... 44
Power Dissipation ............................................... 46
Test Conditions .................................................. 46
Thermal Characteristics ........................................ 50
316-Ball Mini-BGA Pinout ....................................... 51
Outline Dimensions ................................................ 54
Surface Mount Design .......................................... 55
Ordering Guide ..................................................... 55
General Description ................................................. 3
Low Power Architecture ......................................... 3
System Integration ................................................ 3
ADSP-BF538/ADSP-BF538F Processor Peripherals ....... 3
Blackfin Processor Core .......................................... 4
Memory Architecture ............................................ 5
DMA Controllers .................................................. 8
Real Time Clock ................................................... 9
Watchdog Timer .................................................. 9
Timers ............................................................... 9
Serial Ports (SPORTs) .......................................... 10
Serial Peripheral Interface (SPI) Ports ...................... 10
Two Wire Interface ............................................. 10
UART Ports ...................................................... 10
General-Purpose Ports ......................................... 11
Parallel Peripheral Interface ................................... 11
Controller Area Network (CAN) Interface ................ 12
Dynamic Power Management ................................ 12
Voltage Regulation .............................................. 14
Clock Signals ..................................................... 14
Booting Modes ................................................... 15
Instruction Set Description ................................... 15
Development Tools ............................................. 16
Designing an Emulator Compatible Processor Board ... 17
Voltage Regulator Layout Guidelines ....................... 17
Pin Descriptions .................................................... 18
Specifications ........................................................ 22
REVISION HISTORY
5/06—Revision PrD:
For this revision, the following sections were changed.
Functional Block Diagram ......................................... 1
Booting Modes ...................................................... 15
Pin Descriptions .................................................... 18
Output Drive Currents ............................................ 44
Power Dissipation .................................................. 46
Test Conditions ..................................................... 46
316-Ball Mini-BGA Pinout ....................................... 51
Rev. PrD
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Page 2 of 56
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May 2006
Preliminary Technical Data
GENERAL DESCRIPTION
The ADSP-BF538/ADSP-BF538F processors are members of
the Blackfin family of products, incorporating the Analog
Devices/Intel Micro Signal Architecture (MSA). Blackfin pro-
cessors combine a dual-MAC state-of-the-art signal processing
engine, the advantages of a clean, orthogonal RISC-like micro-
processor instruction set, and single-instruction, multiple-data
(SIMD) multimedia capabilities into a single instruction set
architecture.
ADSP-BF538/ADSP-BF538F
substantial reduction in power consumption, compared with
just varying the frequency of operation. This translates into
longer battery life and lower heat dissipation.
SYSTEM INTEGRATION
The ADSP-BF538/ADSP-BF538F processors are highly inte-
grated system-on-a-chip solution for the next generation of
consumer and industrial applications including audio and video
signal processing. By combining advanced memory configura-
tions, such as on-chip flash memory, with industry-standard
interfaces with a high performance signal processing core, users
can develop cost-effective solutions quickly without the need for
costly external components. The system peripherals include
three UART ports, three SPI ports, four serial ports (SPORT),
one CAN interface, 2 two wire interfaces (TWI), four general-
purpose timers (three with PWM capability), a real-time clock, a
watchdog timer, a parallel peripheral interface, general-purpose
I/O, and general-purpose I/O pins.
The ADSP-BF538/ADSP-BF538F processors are completely
code compatible with other Blackfin processors, differing only
with respect to performance, peripherals, and on-chip memory.
Specific performance, peripherals, and memory configurations
are shown in Table 1.
Table 1. Processor Features
ADSP-BF538/ADSP-BF538F PROCESSOR
PERIPHERALS
Feature
The ADSP-BF538/ADSP-BF538F processors contain a rich set
of peripherals connected to the core via several high bandwidth
buses, providing flexibility in system configuration as well as
excellent overall system performance (see the block diagram
on Page 1). The general-purpose peripherals include functions
such as UART, Timers with PWM (pulse width modulation)
and pulse measurement capability, general-purpose I/O pins, a
real time clock, and a watchdog timer. This set of functions sat-
isfies a wide variety of typical system support needs and is
augmented by the system expansion capabilities of the device. In
addition to these general-purpose peripherals, the
ADSP-BF538/ADSP-BF538F processors contain high speed
serial and parallel ports for interfacing to a variety of audio,
video, and modem codec functions. A CAN 2.0B controller is
provided for automotive control networks. An interrupt con-
troller manages interrupts from the on-chip peripherals or
external sources. Power management control functions tailor
the performance and power characteristics of the processors
and system to many application scenarios.
Maximum Performance
Instruction SRAM/Cache
Instruction SRAM
Data SRAM/Cache
Data SRAM
500 MHz 1000 MMACs
16 K bytes
64 K bytes
32 K bytes
32 K bytes
4 K bytes
Scratchpad
Flash
NA
512 K bytes 1 M byte
4
SPORTs
SPIs
3
TWIs (connection to I2C
compatible devices)
2
3
1
1
UARTs
CAN
PPI
Package Option
See Ordering Guide on Page 55
All of the peripherals, except for general-purpose I/O, CAN,
TWI, real time clock, and timers, are supported by a flexible
DMA structure. There are also two separate memory DMA con-
trollers dedicated to data transfers between the processor's
various memory spaces, including external SDRAM and asyn-
chronous memory. Multiple on-chip buses running at up to
133 MHz provide enough bandwidth to keep the processor core
running along with activity on all of the on-chip and external
peripherals.
By integrating a rich set of industry-leading system peripherals
and memory, Blackfin processors are the platform of choice for
next generation applications that require RISC-like program-
mability, multimedia support and leading edge signal
processing in one integrated package.
LOW POWER ARCHITECTURE
Blackfin processors provide world class power management and
performance. Blackfin processors are designed in a low power
and low voltage design methodology and feature dynamic
power management, the ability to vary both the voltage and fre-
quency of operation to significantly lower overall power
consumption. Varying the voltage and frequency can result in a
The ADSP-BF538/ADSP-BF538F processors include an on-chip
voltage regulator in support of the ADSP-BF538/ADSP-BF538F
processor’s dynamic power management capability. The voltage
regulator provides a range of core voltage levels from a single
2.25 V to 3.6 V input. The voltage regulator can be bypassed at
the user's discretion.
Rev. PrD
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Page 3 of 56
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May 2006
Preliminary Technical Data
ADSP-BF538/ADSP-BF538F
bit and 8-bit adds with clipping, 8-bit average operations, and 8-
bit subtract/absolute value/accumulate (SAA) operations. Also
provided are the compare/select and vector search instructions.
BLACKFIN PROCESSOR CORE
As shown in Figure 2 on Page 4, the Blackfin processor core
contains two 16-bit multipliers, two 40-bit accumulators, two
40-bit ALUs, four video ALUs, and a 40-bit shifter. The compu-
tation units process 8-bit, 16-bit, or 32-bit data from the register
file.
For certain instructions, two 16-bit ALU operations can be per-
formed simultaneously on register pairs (a 16-bit high half and
16-bit low half of a compute register). By also using the second
ALU, quad 16-bit operations are possible.
The compute register file contains eight 32-bit registers. When
performing compute operations on 16-bit operand data, the
register file operates as 16 independent 16-bit registers. All
operands for compute operations come from the multiported
register file and instruction constant fields.
The 40-bit shifter can perform shifts and rotates and is used to
support normalization, field extract, and field deposit
instructions.
The program sequencer controls the flow of instruction execu-
tion, including instruction alignment and decoding. For
program flow control, the sequencer supports PC relative and
indirect conditional jumps (with static branch prediction), and
subroutine calls. Hardware is provided to support zero over-
head looping. The architecture is fully interlocked, meaning that
the programmer need not manage the pipeline when executing
instructions with data dependencies.
Each MAC can perform a 16-bit by 16-bit multiply in each
cycle, accumulating the results into the 40-bit accumulators.
Signed and unsigned formats, rounding, and saturation are
supported.
The ALUs perform a traditional set of arithmetic and logical
operations on 16-bit or 32-bit data. In addition, many special
instructions are included to accelerate various signal processing
tasks. These include bit operations such as field extract and pop-
ulation count, modulo 232 multiply, divide primitives, saturation
and rounding, and sign/exponent detection. The set of video
instructions include byte alignment and packing operations, 16-
The address arithmetic unit provides two addresses for simulta-
neous dual fetches from memory. It contains a multiported
register file consisting of four sets of 32-bit index, modify,
length, and base registers (for circular buffering), and eight
additional 32-bit pointer registers (for C style indexed stack
manipulation).
ADDRESS ARITHMETIC UNIT
SP
FP
P5
P4
P3
P2
P1
P0
I3
I2
I1
I0
L3
L2
L1
L0
B3
B2
B1
B0
M3
M2
M1
M0
DAG0
DAG1
SEQUENCER
ALIGN
DECODE
R7 R7 .H
R6 R6 .H
R5 R5 .H
R4 R4 .H
R3 R3 .H
R7.L
R6.L
R5.L
R4.L
R3.L
LD0 32 BITS
LD1 32 BITS
SD 32 BI TS
LOOPBUFFER
16
16
8
8
8
8
CONTROL
UNIT
R2 R2 .H
R1 R1 .H
R2.L
R1.L
BARREL
SHIFTER
R0 R0 .H
R0.L
40
40
A0
A1
DATA ARITHMETIC UNIT
Figure 2. Blackfin Processor Core
Rev. PrD
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Page 4 of 56
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May 2006
Preliminary Technical Data
ADSP-BF538/ADSP-BF538F
Blackfin processors support a modified Harvard architecture in
combination with a hierarchical memory structure. Level 1 (L1)
memories are those that typically operate at the full processor
speed with little or no latency. At the L1 level, the instruction
memory holds instructions only. The two data memories hold
data, and a dedicated scratchpad data memory stores stack and
local variable information.
0xFFFF FFFF
0xFFE0 0000
0xFFC0 0000
0xFFB0 1000
0xFFB0 0000
0xFFA1 4000
0xFFA1 0000
0xFFA0 8000
0xFF90 8000
0xFF90 4000
0xFF80 8000
0xFF80 4000
0xEF00 0000
0x2040 0000
CORE MMR REGISTERS (2M BYTE)
SYSTEM MMR REGISTERS (2M BYTE)
RESERVED
SCRATCHPAD SRAM (4K BYTE)
RESERVED
In addition, multiple L1 memory blocks are provided, offering a
configurable mix of SRAM and cache. The Memory Manage-
ment Unit (MMU) provides memory protection for individual
tasks that may be operating on the core and can protect system
registers from unintended access.
INSTRUCTION SRAM / CACHE (16K BYTE)
INSTRUCTION SRAM (32K BYTE)
RESERVED
DATA BANK B SRAM / CACHE (16K BYTE)
RESERVED
The architecture provides three modes of operation: User mode,
Supervisor mode, and Emulation mode. User mode has
restricted access to certain system resources, thus providing a
protected software environment, while supervisor mode has
unrestricted access to the system and core resources.
DATA BANK A SRAM / CACHE (16K BYTE)
RESERVED
RESERVED
ASYNC MEMORY BANK 3 (1M BYTE) OR
ON-CHIP FLASH
The Blackfin processor instruction set has been optimized so
that 16-bit opcodes represent the most frequently used instruc-
tions, resulting in excellent compiled code density. Complex
DSP instructions are encoded into 32-bit opcodes, representing
fully featured multifunction instructions. Blackfin processors
support a limited multi-issue capability, where a 32-bit instruc-
tion can be issued in parallel with two 16-bit instructions,
allowing the programmer to use many of the core resources in a
single instruction cycle.
0x2030 0000
0x2020 0000
0x2010 0000
ASYNC MEMORY BANK 2 (1M BYTE) OR
ON-CHIP FLASH
ASYNC MEMORY BANK 1 (1M BYTE) OR
ON-CHIP FLASH
ASYNC MEMORY BANK 0 (1M BYTE) OR
ON-CHIP FLASH
0x2000 0000
0x0800 0000
0x0000 0000
RESERVED
SDRAM MEMORY (16M BYTE - 128M BYTE)
The Blackfin processor assembly language uses an algebraic syn-
tax for ease of coding and readability. The architecture has been
optimized for use in conjunction with the C/C++ compiler,
resulting in fast and efficient software implementations.
Figure 3. ADSP-BF538/ADSP-BF538F Internal/External Memory Map
Internal (On-chip) Memory
MEMORY ARCHITECTURE
The ADSP-BF538/ADSP-BF538F processors have three blocks
of on-chip memory providing high bandwidth access to the
core.
The ADSP-BF538/ADSP-BF538F processors view memory as a
single unified 4 Gbyte address space, using 32-bit addresses. All
resources, including internal memory, external memory, and
I/O control registers, occupy separate sections of this common
address space. The memory portions of this address space are
arranged in a hierarchical structure to provide a good cost/per-
formance balance of some very fast, low latency on-chip
memory as cache or SRAM, and larger, lower cost and perfor-
mance off-chip memory systems. See Figure 3.
The first is the L1 instruction memory, consisting of 80 Kbytes
SRAM, of which 16 Kbytes can be configured as a four way set-
associative cache. This memory is accessed at full processor
speed.
The second on-chip memory block is the L1 data memory, con-
sisting of two banks of up to 32 Kbytes each. Each memory bank
is configurable, offering both two-way set-associative cache and
SRAM functionality. This memory block is accessed at full pro-
cessor speed.
The L1 memory system is the primary highest performance
memory available to the Blackfin processor. The off-chip mem-
ory system, accessed through the External Bus Interface Unit
(EBIU), provides expansion with SDRAM, flash memory, and
SRAM, optionally accessing up to 132 Mbytes of physical
memory.
The third memory block is a 4K byte scratchpad SRAM which
runs at the same speed as the L1 memories, but is only accessible
as data SRAM and cannot be configured as cache memory.
External (Off-Chip) Memory
The memory DMA controllers provide high bandwidth data
movement capability. They can perform block transfers of code
or data between the internal memory and the external memory
spaces.
External memory is accessed via the EBIU. This 16-bit interface
provides a glueless connection to a bank of synchronous DRAM
(SDRAM) as well as up to four banks of asynchronous memory
devices including flash, EPROM, ROM, SRAM, and memory
mapped I/O devices.
Rev. PrD
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Page 5 of 56
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May 2006
Preliminary Technical Data
ADSP-BF538/ADSP-BF538F
The PC133-compliant SDRAM controller can be programmed
to interface to up to 128 Mbytes of SDRAM. The SDRAM con-
troller allows one row to be open for each internal SDRAM
bank, for up to four internal SDRAM banks, improving overall
system performance.
When connected to AMS3–1 the flash memory will appear as
non-volatile memory in the processor memory map shown in
Figure 3 on Page 5.
Flash Memory Programming
The ADSP-BF538F4 and ADSP-BF538F8 flash memory may be
programmed before or after mounting on the printed circuit
board.
The asynchronous memory controller can be programmed to
control up to four banks of devices with very flexible timing
parameters for a wide variety of devices. Each bank occupies a
1 Mbyte segment regardless of the size of the devices used, so
that these banks will only be contiguous if each is fully popu-
lated with 1 Mbyte of memory.
To program the flash prior to mounting on the printed circuit
board, use a hardware programming tool that can provide the
data, address, and control stimuli to the flash die through the
external pins on the package. During this programming, VDDEXT
and GND must be provided to the package and the Blackfin
must be held in reset with bus request (BR) asserted and a
CLKIN provided.
Flash Memory
The ADSP-BF538F4 and ADSP-BF538F8 processors contain a
separate flash die, connected to the EBIU bus, within the pack-
age of the processors. Figure 4 on Page 6 shows how the flash
memory die and Blackfin processor die are connected.
The VisualDSP++® tools may be used to program the flash
memory after the device is mounted on a printed circuit board.
Flash Memory Sector Protection
To use the sector protection feature, a high voltage (+12 V nom-
inal) must be applied to the flash FRESET pin. Refer to the flash
datasheet for details.
I/O Memory Space
ADDR19-1
A18-0
OE
WE
ARE
AWE
Blackfin processors do not define a separate I/O space. All
resources are mapped through the flat 32-bit address space. On-
chip I/O devices have their control registers mapped into mem-
ory mapped registers (MMRs) at addresses near the top of the
4 Gbyte address space. These are separated into two smaller
blocks, one which contains the control MMRs for all core func-
tions, and the other which contains the registers needed for
setup and control of the on-chip peripherals outside of the core.
The MMRs are accessible only in supervisor mode and appear
as reserved space to on-chip peripherals.
ARDY
DATA15-0
RY/BY
DQ15-0
VSS
VCC
BYTE
CE
GND
DDEXT
V
AMS3-0
RESET
RESET
ADSP-BF538Fx
package
Booting
The ADSP-BF538/ADSP-BF538F processors contain a small
boot kernel, which configures the appropriate peripheral for
booting. If the processors are configured to boot from boot
ROM memory space, the processors start executing from the
on-chip boot ROM. For more information, see Booting Modes
on Page 15.
Figure 4. Internal Connection of Flash Memory (ADSP-BF538Fx)
The ADSP-BF538F4 contains a 512 Kbits bottom boot sector
flash memory. The ADSP-BF538F8 contains a 1 Mbit bottom
boot sector flash memory. Features include the following.
• access times as fast as 70 ns (EBIU registers must be set
appropriately)
Event Handling
The event controller on the ADSP-BF538/ADSP-BF538F pro-
cessors handle all asynchronous and synchronous events to the
processors. The processor provides event handling that sup-
ports both nesting and prioritization. Nesting allows multiple
event service routines to be active simultaneously. Prioritization
ensures that servicing of a higher priority event takes prece-
dence over servicing of a lower priority event. The controller
provides support for five different types of events:
• sector protection
• one million write cycles per sector
• 20 year data retention
The Blackfin processor connects to the flash memory die with
address, data, chip enable, write enable, and output enable con-
trols as if it were an external memory device.
The flash chip enable pin FCE must be connected to AMS0 or
AMS3–1 through a printed circuit board trace. When connected
to AMS0 the Blackfin processor can boot from the flash die.
• Emulation – An emulation event causes the processor to
enter emulation mode, allowing command and control of
the processor via the JTAG interface.
• Reset – This event resets the processor.
Rev. PrD
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Page 6 of 56
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May 2006
Preliminary Technical Data
ADSP-BF538/ADSP-BF538F
• Non-maskable interrupt (NMI) – The NMI event can be
generated by the software watchdog timer or by the NMI
input signal to the processor. The NMI event is frequently
used as a power-down indicator to initiate an orderly shut-
down of the system.
support the peripherals of the processor. Table 2 describes the
inputs to the CEC, identifies their names in the event vector
table (EVT), and lists their priorities.
System Interrupt Controllers (SIC)
The system interrupt controllers (SIC0, SIC1) provide the map-
ping and routing of events from the many peripheral interrupt
sources to the prioritized general-purpose interrupt inputs of
the CEC. Although the ADSP-BF538/ADSP-BF538F processors
provide a default mapping, the user can alter the mappings and
priorities of interrupt events by writing the appropriate values
into the interrupt assignment registers (IAR). Table 3 describes
the inputs into the SICs and the default mappings into the CEC.
• Exceptions – Events that occur synchronously to program
flow (the exception are taken before the instruction is
allowed to complete). Conditions such as data alignment
violations and undefined instructions cause exceptions.
• Interrupts – Events that occur asynchronously to program
flow. They are caused by input pins, timers, and other
peripherals, as well as by an explicit software instruction.
Each event type has an associated register to hold the return
address and an associated return-from-event instruction. When
an event is triggered, the state of the processors are saved on the
supervisor stack.
Table 3. System and Core Event Mapping
Core
Event Name
Event Source
The ADSP-BF538/ADSP-BF538F processor’s event controllers
consist of two stages, the core event controller (CEC) and the
system interrupt controller (SIC). the core event controller
works with the system interrupt controller to prioritize and con-
trol all system events. Conceptually, interrupts from the
peripherals enter into the SIC, and are then routed directly into
the general-purpose interrupts of the CEC.
PLL Wakeup Interrupt
IVG7
DMA Controller 0 Error
DMA Controller 1 Error
PPI Error Interrupt
IVG7
IVG7
IVG7
SPORT0 Error Interrupt
SPORT1 Error Interrupt
SPORT2 Error Interrupt
SPORT3 Error Interrupt
SPI0 Error Interrupt
IVG7
IVG7
Core Event Controller (CEC)
IVG7
IVG7
Table 2. Core Event Controller (CEC)
IVG7
Priority
SPI1 Error Interrupt
IVG7
(0 is Highest)
Event Class
EVT Entry
EMU
SPI2 Error Interrupt
IVG7
0
Emulation/Test Control
Reset
UART0 Error Interrupt
IVG7
1
RST
UART1 Error Interrupt
IVG7
2
Non-Maskable Interrupt
Exception
NMI
UART2 Error Interrupt
IVG7
3
EVX
CAN Error Interrupt
IVG7
4
Reserved
—
Real Time Clock Interrupts
DMA0 Interrupt (PPI)
IVG8
5
Hardware Error
IVHW
IVTMR
IVG7
IVG8
6
Core Timer
DMA1 Interrupt (SPORT0 RX)
DMA2 Interrupt (SPORT0 TX)
DMA3 Interrupt (SPORT1 RX)
DMA4 Interrupt (SPORT1 TX)
DMA8 Interrupt (SPORT2 RX)
DMA9 Interrupt (SPORT2 TX)
DMA10 Interrupt (SPORT3 RX)
DMA11 Interrupt (SPORT3 TX)
DMA5 Interrupt (SPI0)
DMA14 Interrupt (SPI1)
DMA15 Interrupt (SPI2)
DMA6 Interrupt (UART0 RX)
DMA7 Interrupt (UART0 TX)
DMA16 Interrupt (UART1 RX)
DMA17 Interrupt (UART1 TX)
IVG9
7
General Interrupt 7
General Interrupt 8
General Interrupt 9
General Interrupt 10
General Interrupt 11
General Interrupt 12
General Interrupt 13
General Interrupt 14
General Interrupt 15
IVG9
8
IVG8
IVG9
9
IVG9
IVG9
10
11
12
13
14
15
IVG10
IVG11
IVG12
IVG13
IVG14
IVG15
IVG9
IVG9
IVG9
IVG9
IVG10
IVG10
IVG10
IVG10
IVG10
IVG10
IVG10
The CEC supports nine general-purpose interrupts (IVG15–7),
in addition to the dedicated interrupt and exception events. Of
these general-purpose interrupts, the two lowest priority inter-
rupts (IVG15–14) are recommended to be reserved for software
interrupt handlers, leaving seven prioritized interrupt inputs to
Rev. PrD
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Page 7 of 56
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May 2006
Preliminary Technical Data
ADSP-BF538/ADSP-BF538F
Table 3. System and Core Event Mapping (Continued)
• SIC interrupt mask registers (SIC_IMASKx)– These regis-
ters control the masking and unmasking of each peripheral
interrupt event. When a bit is set in these registers, that
peripheral event is unmasked and will be processed by the
system when asserted. A cleared bit in these registers masks
the peripheral event, preventing the processor from servic-
ing the event.
Core
Event Source
Event Name
DMA18 Interrupt (UART2 RX)
DMA19 Interrupt (UART2 TX)
Timer0, Timer1, Timer2 Interrupts
TWI0 Interrupt
IVG10
IVG10
IVG11
IVG11
IVG11
IVG11
IVG11
IVG12
IVG13
IVG13
IVG13
IVG13
IVG13
• SIC interrupt status registers (SIC_ISRx) – As multiple
peripherals can be mapped to a single event, these registers
allow the software to determine which peripheral event
source triggered the interrupt. A set bit indicates the
peripheral is asserting the interrupt, and a cleared bit indi-
cates the peripheral is not asserting the event.
TWI1 Interrupt
CAN Receive Interrupt
CAN Transmit Interrupt
Port F GPIO Interrupts A and B
MDMA0 Stream 0 Interrupt
MDMA0 Stream 1 Interrupt
MDMA1 Stream 0 Interrupt
MDMA1 Stream 1 Interrupt
Software Watchdog Timer
• SIC interrupt wakeup enable registers (SIC_IWRx) – By
enabling the corresponding bit in these registers, a periph-
eral can be configured to wake up the processor, should the
core be idled when the event is generated. (For more infor-
mation, see Dynamic Power Management on Page 12.)
Because multiple interrupt sources can map to a single general-
purpose interrupt, multiple pulse assertions can occur simulta-
neously, before or during interrupt processing for an interrupt
event already detected on this interrupt input. The IPEND reg-
ister contents are monitored by the SIC as the interrupt
acknowledgement.
Event Control
The ADSP-BF538/ADSP-BF538F processors provide the user
with a very flexible mechanism to control the processing of
events. In the CEC, three registers are used to coordinate and
control events. Each register is 16 bits wide:
The appropriate ILAT register bit is set when an interrupt rising
edge is detected (detection requires two core clock cycles). The
bit is cleared when the respective IPEND register bit is set. The
IPEND bit indicates that the event has entered into the proces-
sor pipeline. At this point the CEC will recognize and queue the
next rising edge event on the corresponding event input. The
minimum latency from the rising edge transition of the general-
purpose interrupt to the IPEND output asserted is three core
clock cycles; however, the latency can be much higher, depend-
ing on the activity within and the state of the processor.
• CEC interrupt latch register (ILAT) – The ILAT register
indicates when events have been latched. The appropriate
bit is set when the processor has latched the event and
cleared when the event has been accepted into the system.
This register is updated automatically by the controller, but
it may also be written to clear (cancel) latched events. This
register may be read while in supervisor mode and may
only be written while in supervisor mode when the corre-
sponding IMASK bit is cleared.
DMA CONTROLLERS
• CEC interrupt mask register (IMASK) – The IMASK regis-
ter controls the masking and unmasking of individual
events. When a bit is set in the IMASK register, that event is
unmasked and will be processed by the CEC when asserted.
A cleared bit in the IMASK register masks the event, pre-
venting the processor from servicing the event even though
the event may be latched in the ILAT register. This register
may be read or written while in supervisor mode. (Note
that general-purpose interrupts can be globally enabled and
disabled with the STI and CLI instructions, respectively.)
The ADSP-BF538/ADSP-BF538F processors have multiple,
independent DMA controllers that support automated data
transfers with minimal overhead for the processor core. DMA
transfers can occur between the processor internal memories
and any of its DMA capable peripherals. Additionally, DMA
transfers can be accomplished between any of the DMA capable
peripherals and external devices connected to the external
memory interfaces, including the SDRAM controller and the
asynchronous memory controller. DMA capable peripherals
include the SPORTs, SPI port, UART, and PPI. Each individual
DMA capable peripheral has at least one dedicated DMA
channel.
• CEC interrupt pending register (IPEND) – The IPEND
register keeps track of all nested events. A set bit in the
IPEND register indicates the event is currently active or
nested at some level. This register is updated automatically
by the controller but may be read while in supervisor mode.
The DMA controllers support both 1-dimensional (1D) and 2-
dimensional (2D) DMA transfers. DMA transfer initialization
can be implemented from registers or from sets of parameters
called descriptor blocks.
The SIC allows further control of event processing by providing
three 32-bit interrupt control and status registers. Each register
contains a bit corresponding to each of the peripheral interrupt
events shown in Table 3 on Page 7.
The 2D DMA capability supports arbitrary row and column
sizes up to 64K elements by 64K elements, and arbitrary row
and column step sizes up to 32K elements. Furthermore, the
column step size can be less than the row step size, allowing
Rev. PrD
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Preliminary Technical Data
ADSP-BF538/ADSP-BF538F
implementation of interleaved data streams. This feature is
especially useful in video applications where data can be de-
interleaved on the fly.
RTXI
RTXO
R1
Examples of DMA types supported by the processor DMA con-
troller include:
X1
• A single, linear buffer that stops upon completion
C1
C2
• A circular, auto-refreshing buffer that interrupts on each
full or fractionally full buffer
• 1-D or 2-D DMA using a linked list of descriptors
SUGGESTED COMPONENTS:
ECLIPTEK EC38J (THROUGH-HOLE PACKAGE)
EPSON MC405 12 PF LOAD (SURFACE MOUNT PACKAGE)
C1 = 22 PF
• 2-D DMA using an array of descriptors, specifying only the
base DMA address within a common page
C2 = 22 PF
R1 = 10M OHM
In addition to the dedicated peripheral DMA channels, there are
four memory DMA channels provided for transfers between the
various memories of the ADSP-BF538/ADSP-BF538F proces-
sor’s systems. This enables transfers of blocks of data between
any of the memories—including external SDRAM, ROM,
SRAM, and flash memory—with minimal processor interven-
tion. Memory DMA transfers can be controlled by a very
flexible descriptor based methodology or by a standard register
based autobuffer mechanism.
NOTE: C1 AND C2 ARE SPECIFIC TO CRYSTAL SPECIFIED FOR X1.
CONTACT CRYSTAL MANUFACTURER FOR DETAILS. C1 AND C2
SPECIFICATIONS ASSUME BOARD TRACE CAPACITANCE OF 3 PF.
Figure 5. External Components for RTC
WATCHDOG TIMER
The ADSP-BF538/ADSP-BF538F processors include a 32-bit
timer that can be used to implement a software watchdog func-
tion. A software watchdog can improve system availability by
forcing the processor to a known state through generation of a
hardware reset, non-maskable interrupt (NMI), or general-pur-
pose interrupt, if the timer expires before being reset by
software. The programmer initializes the count value of the
timer, enables the appropriate interrupt, then enables the timer.
Thereafter, the software must reload the counter before it
counts to zero from the programmed value. This protects the
system from remaining in an unknown state where software,
which would normally reset the timer, has stopped running due
to an external noise condition or software error.
REAL TIME CLOCK
The ADSP-BF538/ADSP-BF538F processor’s real time clock
(RTC) provides a robust set of digital watch features, including
current time, stopwatch, and alarm. The RTC is clocked by a
32.768 KHz crystal external to the processor. The RTC periph-
eral has dedicated power supply pins so that it can remain
powered up and clocked even when the rest of the processors
are in a low power state. The RTC provides several programma-
ble interrupt options, including interrupt per second, minute,
hour, or day clock ticks, interrupt on programmable stopwatch
countdown, or interrupt at a programmed alarm time.
If configured to generate a hardware reset, the watchdog timer
resets both the core and the processor peripherals. After a reset,
software can determine if the watchdog was the source of the
hardware reset by interrogating a status bit in the watchdog
timer control register.
The 32.768 KHz input clock frequency is divided down to a
1 Hz signal by a prescaler. The counter function of the timer
consists of four counters: a 60 second counter, a 60 minute
counter, a 24 hour counter, and an 32,768 day counter.
When enabled, the alarm function generates an interrupt when
the output of the timer matches the programmed value in the
alarm control register. There are two alarms: The first alarm is
for a time of day. The second alarm is for a day and time of that
day.
The timer is clocked by the system clock (SCLK), at a maximum
frequency of fSCLK
.
TIMERS
There are four general-purpose programmable timer units in
the ADSP-BF538/ADSP-BF538F processors. Three timers have
an external pin that can be configured either as a pulse width
modulator (PWM) or timer output, as an input to clock the
timer, or as a mechanism for measuring pulse widths and peri-
ods of external events. These timers can be synchronized to an
external clock input to the PF1 pin, an external clock input to
the PPI_CLK pin, or to the internal SCLK.
The stopwatch function counts down from a programmed
value, with one second resolution. When the stopwatch is
enabled and the counter underflows, an interrupt is generated.
Like the other peripherals, the RTC can wake up the ADSP-
BF538/ADSP-BF538F processor from sleep mode upon genera-
tion of any RTC wakeup event. Additionally, an RTC wakeup
event can wake up the processor from deep sleep mode, and
wake up the on-chip internal voltage regulator from a powered
down state.
The timer units can be used in conjunction with the UART to
measure the width of the pulses in the data stream to provide an
auto-baud detect function for a serial channel.
Connect RTC pins RTXI and RTXO with external components
as shown in Figure 5.
The timers can generate interrupts to the processor core provid-
ing periodic events for synchronization, either to the system
clock or to a count of external signals.
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Preliminary Technical Data
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In addition to the three general-purpose programmable timers,
a fourth timer is also provided. This extra timer is clocked by the
internal processor clock and is typically used as a system tick
clock for generation of operating system periodic interrupts.
processor. For SPI0, seven SPI chip select output pins
(SPI0SEL7–1) let the processor select other SPI devices. The SPI
select pins are reconfigured GPIO pins. SPI1 and SPI2 have a
single SPI select for SPI point-to-point communication. Using
these pins, the SPI ports provide a full-duplex, synchronous
serial interface, which supports both master/slave modes and
multimaster environments.
SERIAL PORTS (SPORTs)
The ADSP-BF538/ADSP-BF538F processors incorporate four
dual-channel synchronous serial ports for serial and multipro-
cessor communications. The SPORTs support the following
features:
The SPI ports’ baud rate and clock phase/polarities are pro-
grammable, and it has an integrated DMA controller,
configurable to support transmit or receive data streams. Each
SPI’s DMA controller can only service unidirectional accesses at
any given time.
• I2S capable operation.
• Bidirectional operation – Each SPORT has two sets of inde-
pendent transmit and receive pins, enabling eight channels
of I2S stereo audio.
The SPI port’s clock rate is calculated as:
fSCLK
2 × SPIx_BAUD
--------------------------------------
SPI Clock Rate =
• Buffered (8-deep) transmit and receive ports – Each port
has a data register for transferring data words to and from
other processor components and shift registers for shifting
data in and out of the data registers.
Where the 16-bit SPIx_BAUD register contains a value of 2 to
65,535.
• Clocking – Each transmit and receive port can either use an
external serial clock or generate its own, in frequencies
ranging from (fSCLK/131,070) Hz to (fSCLK/2) Hz.
During transfers, the SPI port simultaneously transmits and
receives by serially shifting data in and out on its two serial data
lines. The serial clock line synchronizes the shifting and sam-
pling of data on the two serial data lines.
• Word length – Each SPORT supports serial data words
from 3 to 32 bits in length, transferred most significant bit
first or least significant bit first.
TWO WIRE INTERFACE
The ADSP-BF538/ADSP-BF538F processors have 2 two wire
interface (TWI) modules that are compatible with the Philips
Inter-IC bus standard. The TWI modules offer the capabilities
of simultaneous master and slave operation, support for 7-bit
addressing and multimedia data arbitration. The TWI also
includes master clock synchronization and support for clock
low extension.
• Framing – Each transmit and receive port can run with or
without frame sync signals for each data word. Frame sync
signals can be generated internally or externally, active high
or low, and with either of two pulsewidths and early or late
frame sync.
• Companding in hardware – Each SPORT can perform
A-law or μ-law companding according to ITU recommen-
dation G.711. Companding can be selected on the transmit
and/or receive channel of the SPORT without additional
latencies.
The TWI interface uses two pins for transferring clock (SCLx)
and data (SDAx) and supports the protocol at speeds up to
400 kbits/sec.
The TWI interface pins are compatible with 5V logic levels.
• DMA operations with single-cycle overhead – Each SPORT
can automatically receive and transmit multiple buffers of
memory data. The processor can link or chain sequences of
DMA transfers between a SPORT and memory.
UART PORTs
The ADSP-BF538/ADSP-BF538F processors incorporate three
full-duplex Universal Asynchronous Receiver/Transmitter
(UART) ports, which are fully compatible with PC standard
UARTs. The UART ports provide a simplified UART interface
to other peripherals or hosts, supporting full-duplex, DMA sup-
ported, asynchronous transfers of serial data. The UART ports
include support for 5 to 8 data bits, 1 or 2 stop bits, and none,
even, or odd parity. The UART ports support two modes of
operation:
• Interrupts – Each transmit and receive port generates an
interrupt upon completing the transfer of a data word or
after transferring an entire data buffer or buffers through
DMA.
• Multichannel capability – Each SPORT supports 128 chan-
nels out of a 1024 channel window and is compatible with
the H.100, H.110, MVIP-90, and HMVIP standards.
• PIO (programmed I/O) – The processor sends or receives
data by writing or reading I/O mapped UART registers.
The data is double buffered on both transmit and receive.
SERIAL PERIPHERAL INTERFACE (SPI) PORTS
The ADSP-BF538/ADSP-BF538F processors incorporate three
SPI compatible ports that enable the processor to communicate
with multiple SPI compatible devices.
• DMA (direct memory access) – The DMA controller trans-
fers both transmit and receive data. This reduces the
number and frequency of interrupts required to transfer
data to and from memory. Each UART has two dedicated
The SPI interface uses three pins for transferring data: two data
pins (master output-slave input, MOSIx, and master input-slave
output, MISOx) and a clock pin (serial clock, SCKx). An SPI
chip select input pin (SPIxSS) lets other SPI devices select the
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Preliminary Technical Data
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DMA channels, one for transmit and one for receive. These
DMA channels have lower default priority than most DMA
channels because of their relatively low service rates.
inputs can be configured to generate hardware interrupts,
while output PFx pins can be triggered by software
interrupts.
The UART port's baud rate, serial data format, error code gen-
eration and status, and interrupts are programmable:
• Flag interrupt sensitivity registers – The two flag interrupt
sensitivity registers specify whether individual PFx pins are
level- or edge-sensitive and specify—if edge-sensitive—
whether just the rising edge or both the rising and falling
edges of the signal are significant. One register selects the
type of sensitivity, and one register selects which edges are
significant for edge-sensitivity.
• Supporting bit rates ranging from (fSCLK/ 1,048,576) to
(fSCLK/16) bits per second.
• Supporting data formats from 7 to12 bits per frame.
• Both transmit and receive operations can be configured to
generate maskable interrupts to the processor.
Table 4. GPIO Ports
The UART port’s clock rate is calculated as:
Peripheral
PPI
Alternate GPIO Port Function
GPIO Port F15–0
GPIO Port E7–0
fSCLK
16 × UART_Divisor
-----------------------------------------------
UART Clock Rate =
SPORT2
SPORT3
SPI1
Where the 16-bit UART_Divisor comes from the UARTx_DLH
register (most significant 8 bits) and UARTx_DLL register (least
significant 8 bits).
GPIO Port E15–8
GPIO Port D4–0
SPI2
GPIO Port D9–5
In conjunction with the general-purpose timer functions, auto-
baud detection is supported.
UART1
UART2
CAN
GPIO Port D11–10
GPIO Port D13–12
GPIO Port C1–0
The capabilities of the UARTs are further extended with sup-
port for the Infrared Data Association (IrDA®) Serial Infrared
Physical Layer Link Specification (SIR) protocol.
GPIO
GPIO Port C9–4
GENERAL-PURPOSE PORTS
PARALLEL PERIPHERAL INTERFACE
The ADSP-BF538/ADSP-BF538F processors have up to 54 gen-
eral-purpose I/O pins that are multiplexed with other
peripherals. They are arranged into ports C, D, E, and F as
shown in Table 4.
The ADSP-BF538/ADSP-BF538F processors provide a parallel
peripheral interface (PPI) that can connect directly to parallel
A/D and D/A converters, video encoders and decoders, and
other general-purpose peripherals. The PPI consists of a dedi-
cated input clock pin, up to 3 frame synchronization pins, and
at up to 16 data pins. The input clock supports parallel data rates
at up to fSCLK/2 MHz, and the synchronization signals can be con-
figured as either inputs or outputs.
The general-purpose I/O pins may be individually controlled by
manipulation of the control and status registers. These pins may
be polled to determine their status.
• GPIO direction control register – Specifies the direction of
each individual GPIOx pin as input or output.
The PPI supports a variety of general-purpose and ITU-R 656
modes of operation. In general-purpose mode, the PPI provides
half-duplex, bi-directional data transfer with up to 16 bits of
data. Up to 3 frame synchronization signals are also provided.
In ITU-R 656 mode, the PPI provides half-duplex, bi-direc-
tional transfer of 8- or 10-bit video data. Additionally, on-chip
decode of embedded start-of-line (SOL) and start-of-field (SOF)
preamble packets is supported.
• GPIO control and status registers – The processor employs
a “write one to modify” mechanism that allows any combi-
nation of individual GPIO to be modified in a single
instruction, without affecting the level of any other GPIO.
Four control registers and a data register are provided for
each GPIO port. One register is written in order to set
GPIO values, one register is written in order to clear GPIO
values, one register is written in order to toggle GPIO val-
ues, and one register is written in order to specify a GPIO
input or output. Reading the GPIO Data allows software to
determine the state of the input GPIO pins.
General-Purpose Mode Descriptions
The general-purpose modes of the PPI are intended to suit a
wide variety of data capture and transmission applications.
Three distinct submodes are supported:
In addition to the GPIO function described above, the 16 port F
pins can be individually configured to generate interrupts.
• Input mode – frame syncs and data are inputs into the PPI.
• Flag interrupt mask registers – The two Flag interrupt
mask registers allow each individual PFx pin to function as
an interrupt to the processor. similar to the two flag control
registers that are used to set and clear individual flag values,
one flag interrupt mask register sets bits to enable interrupt
function, and the other flag interrupt mask register clears
bits to disable interrupt function. PFx pins defined as
• Frame capture mode – frame syncs are outputs from the
PPI, but data are inputs.
• Output mode – frame syncs and data are outputs from the
PPI.
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Preliminary Technical Data
ADSP-BF538/ADSP-BF538F
Input Mode
CONTROLLER AREA NETWORK (CAN) INTERFACE
Input mode is intended for ADC applications, as well as video
communication with hardware signaling. In its simplest form,
PPI_FS1 is an external frame sync input that controls when to
read data. The PPI_DELAY MMR allows for a delay (in
PPI_CLK cycles) between reception of this frame sync and the
initiation of data reads. The number of input data samples is
user programmable and defined by the contents of the
PPI_Count register. Data widths of 8-bits, and 10-bits through
16-bits are supported, and are programmed using the
PPI_CONTROL register.
The ADSP-BF538/ADSP-BF538F processors provide a CAN
controller that is a communication controller implementing the
Controller Area Network (CAN) V2.0B protocol. This protocol
is an asynchronous communications protocol used in both
industrial and automotive control systems. CAN is well suited
for control applications due to its capability to communicate
reliably over a network since the protocol incorporates CRC
checking message error tracking, and fault node confinement.
The CAN controller is based on a 32 entry mailbox RAM and
supports both the standard and extended identifier (ID) mes-
sage formats specified in the CAN protocol specification,
revision 2.0, part B.
Frame Capture Mode
Frame capture mode allows the video source(s) to act as a slave
(e.g., for frame capture). The ADSP-BF538/ADSP-BF538F pro-
cessors control when to read from the video source(s). PPI_FS1
is an HSYNC output and PPI_FS2 is a VSYNC output.
Each mailbox consists of eight 16-bit data words. The data is
divided into fields, which includes a message identifier, a time
stamp, a byte count, up to 8 bytes of data, and several control
bits. Each node monitors the messages being passed on the net-
work. If the identifier in the transmitted message matches an
identifier in one of it's mailboxes, then the module knows that
the message was meant for it, passes the data into it's appropri-
ate mailbox, and signals the processor of message arrival with an
interrupt.
Output Mode
Output mode is used for transmitting video or other data with
up to three output frame syncs. Typically, a single frame sync is
appropriate for data converter applications, whereas two or
three frame syncs could be used for sending video with hard-
ware signaling.
The CAN controller can wake up the processor from sleep mode
upon generation of a wakeup event, such that the processor can
be maintained in a low power mode during idle conditions.
Additionally, a CAN wakeup event can wake up the processor
from deep sleep, and wake up the on-chip internal voltage regu-
lator from a powered-down state.
ITU-R 656 Mode Descriptions
The ITU-R 656 modes of the PPI are intended to suit a wide
variety of video capture, processing, and transmission applica-
tions. Three distinct submodes are supported:
• Active video only mode
• Vertical blanking only mode
• Entire field mode
The electrical characteristics of each network connection are
very stringent, therefore the CAN interface is typically divided
into 2 parts: a controller and a transceiver. This allows a single
controller to support different drivers and CAN networks. The
ADSP-BF538/ADSP-BF538F CAN module represents the con-
troller part of the interface. This module's network I/O is a
single transmit output and a single receive input, which connect
to a line transceiver.
Active Video Only Mode
Active video only mode is used when only the active video por-
tion of a field is of interest and not any of the blanking intervals.
The PPI does not read in any data between the end of active
video (EAV) and start of active video (SAV) preamble symbols,
or any data present during the vertical blanking intervals. In this
mode, the control byte sequences are not stored to memory;
they are filtered by the PPI. After synchronizing to the start of
Field 1, the PPI ignores incoming samples until it sees an SAV
code. The user specifies the number of active video lines per
frame (in PPI_Count register).
The CAN clock is derived from the processor system clock
(SCLK) through a programmable divider and therefore does not
require an additional crystal.
DYNAMIC POWER MANAGEMENT
The ADSP-BF538/ADSP-BF538F processors provide five oper-
ating modes, each with a different performance/power profile.
In addition, dynamic power management provides the control
functions to dynamically alter the processor core supply voltage,
further reducing power dissipation. Control of clocking to each
of the processor peripherals also reduces power consumption.
See Table 5 for a summary of the power settings for each mode.
Vertical Blanking Interval Mode
In this mode, the PPI only transfers vertical blanking interval
(VBI) data.
Entire Field Mode
Full-On Operating Mode—Maximum Performance
In this mode, the entire incoming bit stream is read in through
the PPI. This includes active video, control preamble sequences,
and ancillary data that may be embedded in horizontal and ver-
tical blanking intervals. Data transfer starts immediately after
synchronization to Field 1. Data is transferred to or from the
synchronous channels through eight DMA engines that work
autonomously from the processor core.
In the full-on mode, the PLL is enabled and is not bypassed,
providing capability for maximum operational frequency. This
is the powerup default execution state in which maximum per-
formance can be achieved. The processor core and all enabled
peripherals run at full speed.
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FREQ bits of the VR_CTL register. This disables both CCLK
and SCLK. Furthermore, it sets the internal power supply volt-
age (VDDINT) to 0 V to provide the lowest static power dissipation.
Any critical information stored internally (memory contents,
register contents, etc.) must be written to a non-volatile storage
device prior to removing power if the processor state is to be
preserved. Since VDDEXT is still supplied in this mode, all of the
external pins three-state, unless otherwise specified. This allows
other devices that may be connected to the processor to have
power still applied without drawing unwanted current. The
internal supply regulator can be woken up either by a real time
clock wakeup, by CAN bus traffic, by asserting the RESET pin
or by an external source.
Active Operating Mode—Moderate Power Savings
In the active mode, the PLL is enabled but bypassed. Because the
PLL is bypassed, the processor’s core clock (CCLK) and system
clock (SCLK) run at the input clock (CLKIN) frequency. In this
mode, the CLKIN to CCLK multiplier ratio can be changed,
although the changes are not realized until the full-on mode is
entered. DMA access is available to appropriately configured L1
memories.
In the active mode, it is possible to disable the PLL through the
PLL Control register (PLL_CTL). If disabled, the PLL must be
re-enabled before transitioning to the Full-On or Sleep modes.
Table 5. Power Settings
Power Savings
Core
Clock
System
Clock
As shown in Table 6, the ADSP-BF538/ADSP-BF538F proces-
sors support three different power domains. The use of multiple
power domains maximizes flexibility, while maintaining com-
pliance with industry standards and conventions. By isolating
the internal logic of the processor into its own power domain,
separate from the RTC and other I/O, the processor can take
advantage of Dynamic Power Management, without affecting
the RTC or other I/O devices. There are no sequencing require-
ments for the various power domains.
PLL
Core
Power
Mode
Full On
Active
PLL
Bypassed (CCLK)
(SCLK)
Enabled
No
Enabled Enabled On
Enabled Enabled On
Enabled/
Disabled
Yes
Sleep
Enabled
Disabled Enabled On
Disabled Disabled On
Disabled Disabled Off
Deep Sleep Disabled
Hibernate Disabled
Table 6. Power Domains
Sleep Operating Mode—High Dynamic Power Savings
Power Domain
VDD Range
VDDRTC
VDDINT
The sleep mode reduces dynamic power dissipation by disabling
the clock to the processor core (CCLK). The PLL and system
clock (SCLK), however, continue to operate in this mode. Typi-
cally an external event or RTC activity will wake up the
RTC crystal I/O and logic
All internal logic except RTC
All I/O except RTC
VDDEXT
processor. When in the Sleep mode, assertion of wakeup causes
the processor to sense the value of the BYPASS bit in the PLL
control register (PLL_CTL). If BYPASS is disabled, the proces-
sor transitions to the full on mode. If BYPASS is enabled, the
processor will transition to the Active mode. When in the sleep
mode, system DMA access to L1 memory is not supported.
The power dissipated by a processors are largely a function of
the clock frequency of the processors and the square of the oper-
ating voltage. For example, reducing the clock frequency by 25%
results in a 25% reduction in power dissipation, while reducing
the voltage by 25% reduces power dissipation by more than
40%. Further, these power savings are additive, in that if the
clock frequency and supply voltage are both reduced, the power
savings can be dramatic.
Deep Sleep Operating Mode—Maximum Dynamic Power
Savings
The deep sleep mode maximizes dynamic power savings by dis-
abling the clocks to the processor core (CCLK) and to all
synchronous peripherals (SCLK). Asynchronous peripherals
such as the RTC may still be running, but will not be able to
access internal resources or external memory. This powered
down mode can only be exited by assertion of the reset interrupt
(RESET) or by an asynchronous interrupt generated by the
RTC. When in deep sleep mode, an RTC asynchronous inter-
rupt causes the processor to transition to the active mode.
Assertion of RESET while in deep sleep mode causes the proces-
sor to transition to the Full On mode.
The dynamic power management feature of the processor
allows both the processor’s input voltage (VDDINT) and clock fre-
quency (fCCLK) to be dynamically controlled.
The savings in power dissipation can be modeled using the
power savings factor and % power savings calculations.
The power savings factor is calculated as:
Power Savings Factor
2
fCCLKRED
-------------------------
fCCLKNOM
VDDINTRED
-------------------------------
VDDINTNOM
TRED
--------------
TNOM
⎛
⎝
⎞
⎠
⎛
⎝
⎞
⎠
=
×
×
Hibernate Operating Mode—Maximum Static Power
Savings
where the variables in the equations are:
The hibernate mode maximizes static power savings by dis-
abling the voltage and clocks to the processor core (CCLK) and
to all the synchronous peripherals (SCLK). The internal voltage
regulator for the processor can be shut off by writing b#00 to the
• fCCLKNOM is the nominal core clock frequency
• fCCLKRED is the reduced core clock frequency
• VDDINTNOM is the nominal internal supply voltage
Rev. PrD
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Preliminary Technical Data
ADSP-BF538/ADSP-BF538F
• VDDINTRED is the reduced internal supply voltage
• TNOM is the duration running at fCCLKNOM
• TRED is the duration running at fCCLKRED
The Power Savings Factor is calculated as:
Alternatively, because the ADSP-BF538/ADSP-BF538F proces-
sors include an on-chip oscillator circuit, an external crystal
may be used. The crystal should be connected across the CLKIN
and XTAL pins, with two capacitors connected as shown in
Figure 7. Capacitor values are dependent on crystal type and
should be specified by the crystal manufacturer. A parallel-reso-
nant, fundamental frequency, microprocessor-grade crystal
should be used.
% Power Savings = (1 – Power Savings Factor) × 100%
VOLTAGE REGULATION
The Blackfin processor provides an on-chip voltage regulator
that can generate processor core voltage levels 0.8 V to
1.2V(–5%/+10%) from an external 2.7 V to 3.6 V supply.
Figure 6 shows the typical external components required to
complete the power management system.† The regulator con-
trols the internal logic voltage levels and is programmable with
the voltage regulator control register (VR_CTL) in increments
of 50 mV. To reduce standby power consumption, the internal
voltage regulator can be programmed to remove power to the
processor core while I/O power (VDDRTC, VDDEXT) is still supplied.
While in hibernate mode, I/O power is still being applied, elimi-
nating the need for external buffers. The voltage regulator can
be activated from this power-down state either through an RTC
wakeup, a CAN wakeup, a general-purpose wakeup, or by
asserting RESET, which will then initiate a boot sequence. The
regulator can also be disabled and bypassed at the user’s
discretion.
XTAL
CLKOUT
CLKIN
BLACKFIN
PROCESSOR
Figure 7. External Crystal Connections
As shown in Figure 8 on Page 14, the core clock (CCLK) and
system peripheral clock (SCLK) are derived from the input
clock (CLKIN) signal. An on-chip PLL is capable of multiplying
the CLKIN signal by a user programmable 1× to 63× multiplica-
tion factor (bounded by specified minimum and maximum
VCO frequencies). The default multiplier is 10×, but it can be
modified by a software instruction sequence. On-the-fly fre-
quency changes can be effected by simply writing to the
PLL_DIV register.
V
DDEXT
“FINE” ADJUSTMENT
REQUIRES PLL SEQUENCING
“COURSE” ADJUSTMENT
ON-THE-FLY
100 µF
2.25V - 3.6V
INPUT VOLTAGE
RANGE
10 µH
0.1 µF
ZHCS1000
V
DDINT
، 1, 2, 4, 8
، 1:15
CCLK
FDS9431A
PLL
0.5x - 64x
CLKIN
VCO
100 µF
1 µF
SCLK
VR
1-0
OUT
SCLK ≤ CCLK
SCLK ≤ 133 MHz
EXTERNAL COMPONENTS
1-0 SHOULD BE TIED TOGETHER EXTERNALLY
NOTE: VR
OUT
Figure 8. Frequency Modification Methods
AND DESIGNER SHOULD MINIMIZE TRACE LENGTH TO FDS9431A.
Figure 6. Voltage Regulator Circuit
All on-chip peripherals are clocked by the system clock (SCLK).
The system clock frequency is programmable by means of the
SSEL3–0 bits of the PLL_DIV register. The values programmed
into the SSEL fields define a divide ratio between the PLL output
(VCO) and the system clock. SCLK divider values are 1 through
15. Table 7 illustrates typical system clock ratios:
CLOCK SIGNALS
The ADSP-BF538/ADSP-BF538F processors can be clocked by
an external crystal, a sine wave input, or a buffered, shaped
clock derived from an external clock oscillator.
If an external clock is used, it should be a TTL compatible signal
and must not be halted, changed, or operated below the speci-
fied frequency during normal operation. This signal is
connected to the processor’s CLKIN pin. When an external
clock is used, the XTAL pin must be left unconnected.
Table 7. Example System Clock Ratios
Example Frequency Ratios (MHz)
Signal Name Divider Ratio
SSEL3–0
VCO/SCLK
VCO
100
300
500
SCLK
100
50
0001
1:1
0110
6:1
† See EE-228: Switching Regulator Design Considerations for ADSP-BF533
Blackfin Processors.
1010
10:1
50
Rev. PrD
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Preliminary Technical Data
ADSP-BF538/ADSP-BF538F
The maximum frequency of the system clock is fSCLK. Note that
the divisor ratio must be chosen to limit the system clock fre-
quency to its maximum of fSCLK. The SSEL value can be changed
dynamically without any PLL lock latencies by writing the
appropriate values to the PLL divisor register (PLL_DIV).
ADSP-BF538F. All configuration settings are set for the
slowest device possible (3-cycle hold time; 15-cycle R/W
access times; 4-cycle setup).
• Boot from SPI serial EEPROM/flash (8-, 16-, or 24-bit
addressable, or Atmel AT45DB041, AT45DB081, or
AT45DB161) – The SPI uses the PF2 output pin to select a
single SPI EEPROM/flash device, submits a read command
and successive address bytes (0x00) until a valid 8-, 16-, or
24-bit, or Atmel addressable device is detected, and begins
clocking data into the processor at the beginning of L1
instruction memory.
Note that when the SSEL value is changed, it will affect all the
peripherals that derive their clock signals from the SCLK signal.
The core clock (CCLK) frequency can also be dynamically
changed by means of the CSEL1–0 bits of the PLL_DIV register.
Supported CCLK divider ratios are 1, 2, 4, and 8, as shown in
Table 8. This programmable core clock capability is useful for
fast core frequency modifications.
• Boot from SPI host device – The Blackfin processor oper-
ates in SPI slave mode and is configured to receive the bytes
of the .LDR file from an SPI host (master) agent. To hold
off the host device from transmitting while the boot ROM
is busy, the Blackfin processor asserts a GPIO pin, called
host wait (HWAIT), to signal the host device not to send
any more bytes until the flag is deasserted. The flag is cho-
sen by the user and this information is transferred to the
Blackfin processor via bits 10:5 of the FLAG header.
Table 8. Core Clock Ratios
Example Frequency Ratios
Signal Name Divider Ratio
CSEL1–0
VCO/CCLK
VCO
300
300
500
200
CCLK
300
150
125
25
00
01
10
11
1:1
2:1
4:1
8:1
For each of the boot modes, a 10-byte header is first read from
an external memory device. The header specifies the number of
bytes to be transferred and the memory destination address.
Multiple memory blocks may be loaded by any boot sequence.
Once all blocks are loaded, program execution commences from
the start of L1 instruction SRAM.
BOOTING MODES
The ADSP-BF538/ADSP-BF538F processors have three mecha-
nisms (listed in Table 9) for automatically loading internal L1
instruction memory after a reset. A fourth mode is provided to
execute from external memory, bypassing the boot sequence.
In addition, bit 4 of the reset configuration register can be set by
application code to bypass the normal boot sequence during a
software reset. For this case, the processor jumps directly to the
beginning of L1 instruction memory.
Table 9. Booting Modes
To augment the boot modes, a secondary software loader is pro-
vided that adds additional booting mechanisms. This secondary
loader provides the capability to boot from 16-bit flash memory,
fast flash, variable baud rate, and other sources. In all boot
modes except bypass, program execution starts from on-chip L1
memory address 0xFFA0 0000.
BMODE1–0 Description
00
Execute from 16-bit external memory
(bypass boot ROM)
01
Boot from 8-bit or 16-bit flash (ADSP-BF538 only) or
Boot from on board flash (ADSP-BF538F only)
10
11
Boot from SPI serial master
INSTRUCTION SET DESCRIPTION
Boot from SPI serial slave EEPROM /flash
(8-,16-, or 24-bit address range, or Atmel
AT45DB041, AT45DB081, or AT45DB161serial flash)
The Blackfin processor family assembly language instruction set
employs an algebraic syntax designed for ease of coding and
readability. The instructions have been specifically tuned to pro-
vide a flexible, densely encoded instruction set that compiles to
a very small final memory size. The instruction set also provides
fully featured multifunction instructions that allow the pro-
grammer to use many of the processor core resources in a single
instruction. Coupled with many features more often seen on
microcontrollers, this instruction set is very efficient when com-
piling C and C++ source code. In addition, the architecture
supports both user (algorithm/application code) and supervisor
(O/S kernel, device drivers, debuggers, ISRs) modes of opera-
tion, allowing multiple levels of access to core processor
resources.
The BMODE pins of the reset configuration register, sampled
during power-on resets and software initiated resets, implement
the following modes:
• Execute from 16-bit external memory – Execution starts
from address 0x2000 0000 with 16-bit packing. The boot
ROM is bypassed in this mode. All configuration settings
are set for the slowest device possible (3-cycle hold time;
15-cycle R/W access times; 4-cycle setup).
• Boot from 8-bit or 16-bit external flash memory – The 8-bit
flash boot routine located in boot ROM memory space is
set up using asynchronous memory bank 0. If FCE is con-
nected to AMS0, then the on-chip flash is booted from the
Rev. PrD
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Preliminary Technical Data
ADSP-BF538/ADSP-BF538F
The assembly language, which takes advantage of the proces-
sor’s unique architecture, offers the following advantages:
Debugging both C/C++ and assembly programs with the
VisualDSP++ debugger, programmers can:
• Seamlessly integrated DSP/CPU features are optimized for
both 8-bit and 16-bit operations.
• View mixed C/C++ and assembly code (interleaved source
and object information).
• A multi-issue load/store modified Harvard architecture,
which supports two 16-bit MAC or four 8-bit ALU plus
two load/store plus two pointer updates per cycle.
• Insert breakpoints.
• Set conditional breakpoints on registers, memory,
and stacks.
• All registers, I/O, and memory are mapped into a unified
4 Gbyte memory space, providing a simplified program-
ming model.
• Trace instruction execution.
• Perform linear or statistical profiling of program execution.
• Fill, dump, and graphically plot the contents of memory.
• Perform source level debugging.
• Microcontroller features, such as arbitrary bit and bit-field
manipulation, insertion, and extraction; integer operations
on 8-, 16-, and 32-bit data types; and separate user and
supervisor stack pointers.
• Create custom debugger windows.
The VisualDSP++ IDDE lets programmers define and manage
software development. Its dialog boxes and property pages let
programmers configure and manage all of the Blackfin develop-
ment tools, including the color syntax highlighting in the
VisualDSP++ editor. This capability permits programmers to:
• Code density enhancements, which include intermixing of
16- and 32-bit instructions (no mode switching, no code
segregation). Frequently used instructions are encoded in
16 bits.
DEVELOPMENT TOOLS
• Control how the development tools process inputs and
generate outputs.
The ADSP-BF538/ADSP-BF538F processors are supported with
a complete set of CROSSCORE® software and hardware devel-
opment tools, including Analog Devices emulators and
VisualDSP++® development environment. The same emulator
hardware that supports other Blackfin processors also fully
emulates the ADSP-BF538/ADSP-BF538F processors.
• Maintain a one-to-one correspondence with the tool’s
command line switches.
The VisualDSP++ Kernel (VDK) incorporates scheduling and
resource management tailored specifically to address the mem-
ory and timing constraints of DSP programming. These
capabilities enable engineers to develop code more effectively,
eliminating the need to start from the very beginning, when
developing new application code. The VDK features include
threads, critical and unscheduled regions, semaphores, events,
and device flags. The VDK also supports priority-based, pre-
emptive, cooperative, and time-sliced scheduling approaches. In
addition, the VDK was designed to be scalable. If the application
does not use a specific feature, the support code for that feature
is excluded from the target system.
The VisualDSP++ project management environment lets pro-
grammers develop and debug an application. This environment
includes an easy to use assembler (which is based on an alge-
braic syntax), an archiver (librarian/library builder), a linker, a
loader, a cycle-accurate instruction-level simulator, a C/C++
compiler, and a C/C++ runtime library that includes DSP and
mathematical functions. A key point for these tools is C/C++
code efficiency. The compiler has been developed for efficient
translation of C/C++ code to processor assembly. The proces-
sors have architectural features that improve the efficiency of
compiled C/C++ code.
Because the VDK is a library, a developer can decide whether to
use it or not. The VDK is integrated into the VisualDSP++
development environment, but can also be used via standard
command line tools. When the VDK is used, the development
environment assists the developer with many error prone tasks
and assists in managing system resources, automating the gen-
eration of various VDK based objects, and visualizing the
system state, when debugging an application that uses the VDK.
The VisualDSP++ debugger has a number of important fea-
tures. Data visualization is enhanced by a plotting package that
offers a significant level of flexibility. This graphical representa-
tion of user data enables the programmer to quickly determine
the performance of an algorithm. As algorithms grow in com-
plexity, this capability can have increasing significance on the
designer’s development schedule, increasing productivity. Sta-
tistical profiling enables the programmer to non intrusively poll
the processors as they are running the program. This feature,
unique to VisualDSP++, enables the software developer to pas-
sively gather important code execution metrics without
interrupting the real time characteristics of the program. Essen-
tially, the developer can identify bottlenecks in software quickly
and efficiently. By using the profiler, the programmer can focus
on those areas in the program that impact performance and take
corrective action.
Use the Expert Linker to visually manipulate the placement of
code and data on the embedded system. View memory utiliza-
tion in a color coded graphical form, easily move code and data
to different areas of the processor or external memory with the
drag of the mouse, examine run time stack and heap usage. The
Expert Linker is fully compatible with existing Linker Definition
File (LDF), allowing the developer to move between the graphi-
cal and textual environments.
Analog Devices emulators use the IEEE 1149.1 JTAG Test
Access Port of the ADSP-BF538/ADSP-BF538F processors to
monitor and control the target board processor during emula-
tion. The emulator provides full speed emulation, allowing
Rev. PrD
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May 2006
Preliminary Technical Data
ADSP-BF538/ADSP-BF538F
inspection and modification of memory, registers, and proces-
sor stacks. Non intrusive in-circuit emulation is assured by the
use of the processor’s JTAG interface—the emulator does not
affect target system loading or timing.
erence on the Analog Devices web site (www.analog.com)—use
site search on “EE-68.” This document is updated regularly to
keep pace with improvements to emulator support.
VOLTAGE REGULATOR LAYOUT GUIDELINES
In addition to the software and hardware development tools
available from Analog Devices, third parties provide a wide
range of tools supporting the Blackfin processor family. Hard-
ware tools include Blackfin processor PC plug-in cards. Third
party software tools include DSP libraries, real time operating
systems, and block diagram design tools.
Regulator external component placement, board routing, and
bypass capacitors all have a significant effect on noise injected
into the other analog circuits on-chip. The VROUT1-0 traces
and voltage regulator external components should be consid-
ered as noise sources when doing board layout and should not
be routed or placed near sensitive circuits or components on the
board. All internal and I/O power supplies should be well
bypassed with bypass capacitors placed as close to the ADSP-
BF538/ADSP-BF538F processors as possible.
Evaluation Kit
Analog Devices offers a range of EZ-KIT Lite® evaluation plat-
forms to use as a cost effective method to learn more about
developing or prototyping applications with Analog Devices
processors, platforms, and software tools. Each EZ-KIT Lite
includes an evaluation board along with an evaluation suite of
the VisualDSP++ development and debugging environment
with the C/C++ compiler, assembler, and linker. Also included
are sample application programs, power supply, and a USB
cable. All evaluation versions of the software tools are limited
for use only with the EZ-KIT Lite product.
For further details on the on-chip voltage regulator and related
board design guidelines, see the EE-228: Switching Regulator
Design Considerations for ADSP-BF533 Blackfin Processors
applications note on the Analog Devices web site (www.ana-
log.com)—use site search on “EE-228.”.
The USB controller on the EZ-KIT Lite board connects the
board to the USB port of the user’s PC, enabling the
VisualDSP++ evaluation suite to emulate the on-board proces-
sor in-circuit. This permits the customer to download, execute,
and debug programs for the EZ-KIT Lite system. It also allows
in-circuit programming of the on-board flash device to store
user-specific boot code, enabling the board to run as a standal-
one unit without being connected to the PC.
With a full version of VisualDSP++ installed (sold separately),
engineers can develop software for the EZ-KIT Lite or any cus-
tom defined system. Connecting one of Analog Devices JTAG
emulators to the EZ-KIT Lite board enables high-speed, non-
intrusive emulation.
DESIGNING AN EMULATOR COMPATIBLE
PROCESSOR BOARD
The Analog Devices family of emulators are tools that every sys-
tem developer needs to test and debug hardware and software
systems. Analog Devices has supplied an IEEE 1149.1 JTAG
Test Access Port (TAP) on each JTAG processor. The emulator
uses the TAP to access the internal features of the processor,
allowing the developer to load code, set breakpoints, observe
variables, observe memory, and examine registers. The proces-
sor must be halted to send data and commands, but once an
operation has been completed by the emulator, the processor
system is set running at full speed with no impact on system
timing.
To use these emulators, the target board must include a header
that connects the processor’s JTAG port to the emulator.
For details on target board design issues including mechanical
layout, single processor connections, multiprocessor scan
chains, signal buffering, signal termination, and emulator pod
logic, see EE-68: Analog Devices JTAG Emulation Technical Ref-
Rev. PrD
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May 2006
Preliminary Technical Data
ADSP-BF538/ADSP-BF538F
PIN DESCRIPTIONS
ADSP-BF538/ADSP-BF538F processor pin definitions are listed
in Table 10. In order to maintain maximum functionality and
reduce package size and pin count, some pins have dual, multi-
plexed functionality. In cases where pin functionality is
reconfigurable, the default state is shown in plain text, while
alternate functionality is shown in italics.
Table 10. Pin Descriptions
Pin Name
I/O
Function
Driver Type
Memory Interface
ADDR19–1
O
I/O
O
I
Address Bus for Async/Sync Access
Data Bus for Async/Sync Access
A
A
DATA15–0
ABE1–0/SDQM1–0
Byte Enables/Data Masks for Async/Sync Access
Bus Request (This pin should be pulled HIGH when not used.)
Bus Grant
A
BR
BG
O
O
A
A
BGH
Bus Grant Hang
Asynchronous Memory Control
AMS3–0
O
I
Bank Select
A
ARDY
Hardware Ready Control (This pin should always be pulled LOW when not used.)
AOE
O
O
O
Output Enable
Read Enable
Write Enable
A
A
A
ARE
AWE
Flash Control
FCE
I
I
Flash Enable (This pin should be left unconnected if not used.)
Flash Reset (This pin should be left unconnected if not used.)
FRESET
Synchronous Memory Control
SRAS
O
O
O
O
O
O
O
Row Address Strobe
Column Address Strobe
Write Enable
A
A
A
A
B
SCAS
SWE
SCKE
Clock Enable
CLKOUT
SA10
Clock Output
A10 Pin
A
A
SMS
Bank Select
Timers
TMR0
I/O
I/O
I/O
Timer 0
C
C
C
TMR1/PPI_FS1
Timer 1/PPI Frame Sync1
TMR2/PPI_FS2
Timer 2/PPI Frame Sync2
Two Wire Interface Port (These pins are open drain and require a pullup resistor. See version 2.1 of the I2C specification for
proper resistor values.)
SDA0
SCL0
SDA1
SCL1
I/O 5V
I/O 5V
I/O 5V
I/O 5V
TWI0 Serial Data
TWI0 Serial Clock
TWI1 Serial Data
TWI1 Serial Clock
E
E
E
E
Rev. PrD
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May 2006
Preliminary Technical Data
ADSP-BF538/ADSP-BF538F
Table 10. Pin Descriptions (Continued)
Pin Name
Serial Port0
RSCLK0
RFS0
I/O
Function
Driver Type
I/O
I/O
I
SPORT0 Receive Serial Clock
SPORT0 Receive Frame Sync
SPORT0 Receive Data Primary
SPORT0 Receive Data Secondary
SPORT0 Transmit Serial Clock
SPORT0 Transmit Frame Sync
SPORT0 Transmit Data Primary
SPORT0 Transmit Data Secondary
D
C
DR0PRI
DR0SEC
TSCLK0
TFS0
I
I/O
I/O
O
D
C
C
C
DT0PRI
DT0SEC
Serial Port1
RSCLK1
RFS1
O
I/O
I/O
I
SPORT1 Receive Serial Clock
SPORT1 Receive Frame Sync
SPORT1 Receive Data Primary
SPORT1 Receive Data Secondary
SPORT1 Transmit Serial Clock
SPORT1 Transmit Frame Sync
SPORT1 Transmit Data Primary
SPORT1 Transmit Data Secondary
D
C
DR1PRI
DR1SEC
TSCLK1
TFS1
I
I/O
I/O
O
D
C
C
C
DT1PRI
DT1SEC
SPI0 Port
MOSI0
O
I/O
I/O
SPI0 Master Out Slave In
C
MISO0
SPI0 Master In Slave Out (This pin should always be pulled HIGH through a 4.7 C
KΩ resistor if booting via the SPI port.)
SCK0
I/O
SPI0 Clock
D
UART0 Port
RX0
I
UART Receive
UART Transmit
TX0
O
C
C
PPI Port
PPI3–0
PPI_CLK
I/O
I
PPI3–0
PPI Clock
Port C: Controller Area Network/GPIO
CANTX/PC0
CANRX/PC1
PC[9:4]
I/O 5V
I/O 5V
I/O
CAN Transmit/GPIO
CAN Receive/GPIO
GPIO
C
C
Port D: SPI1/SPI2/UART1/UART2/GPIO
MOSI1/PD0
MISO1/PD1
SCK1/PD2
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SPI1 Master Out Slave In/GPIO
SPI1 Master In Slave Out/GPIO
SPI1 Clock/GPIO
C
C
D
C
C
C
C
SPI1SS/PD3
SPI1SEL/PD4
MOSI2/PD5
MISO2/PD6
SPI1 Slave Select Input/GPIO
SPI1 Slave Select Enable/GPIO
SPI2 Master Out Slave In/GPIO
SPI2 Master In Slave Out/GPIO
Rev. PrD
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May 2006
Preliminary Technical Data
ADSP-BF538/ADSP-BF538F
Table 10. Pin Descriptions (Continued)
Pin Name
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Function
Driver Type
SCK2/PD7
SPI2 Clock/GPIO
D
C
C
C
C
C
C
SPI2SS/PD8
SPI2SEL/PD9
RX1/PD10
SPI2 Slave Select Input/GPIO
SPI2 Slave Select Enable/GPIO
UART1 Receive/GPIO
UART1 Transmit/GPIO
UART2 Receive/GPIO
UART2 Transmit/GPIO
TX1/PD11
RX2/PD12
TX2/PD13
Port E: SPORT2/SPORT3/GPIO
RSCLK2/PE0
RFS2/PE1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SPORT2 Receive Serial Clock/GPIO
SPORT2 Receive Frame Sync/GPIO
SPORT2 Receive Data Primary/GPIO
SPORT2 Receive Data Secondary/GPIO
SPORT2 Transmit Serial Clock/GPIO
SPORT2 Transmit Frame Sync/GPIO
SPORT2 Transmit Data Primary/GPIO
SPORT2 Transmit Data Secondary/GPIO
SPORT3 Receive Serial Clock/GPIO
SPORT3 Receive Frame Sync/GPIO
SPORT3 Receive Data Primary/GPIO
SPORT3 Receive Data Secondary/GPIO
SPORT3 Transmit Serial Clock/GPIO
SPORT3 Transmit Frame Sync/GPIO
SPORT3 Transmit Data Primary/GPIO
SPORT3 Transmit Data Secondary/GPIO
D
C
C
C
D
C
C
C
D
C
C
C
D
C
C
C
DR2PRI /PE2
DR2SEC/PE3
TSCLK2/PE4
TFS2/PE5
DT2PRI/PE6
DT2SEC/PE7
RSCLK3/PE8
RFS3/PE9
DR3PRI/PE10
DR3SEC/PE11
TSCLK3/PE12
TFS3/PE13
DT3PRI/PE14
DT3SEC/PE15
Port F: Parallel Peripheral Interface Port/SPI0/Timers/GPIO
SPI0SS/PF0
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SPI Slave Select Input/GPIO
C
SPI0SEL1/TMRCLK/PF1
SPI0SEL2/PF2
PPI_FS3/SPI0SEL3/PF3
PPI15/SPI0SEL4/PF4
PPI14/SPI0SEL5/PF5
PPI13/SPI0SEL6/PF6
PPI12/SPI0SEL7/PF7
PPI11/PF8
SPI Slave Select Enable 1/External Timer Reference/GPIO
SPI Slave Select Enable 2/GPIO
PPI Frame Sync 3/SPI Slave Select Enable 3/GPIO
PPI 15/SPI Slave Select Enable 4/GPIO
PPI 14/SPI Slave Select Enable 5/GPIO
PPI 13/SPI Slave Select Enable 6/GPIO
PPI 12/SPI Slave Select Enable 7/GPIO
PPI 11/GPIO
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
PPI10/PF9
PPI 10/GPIO
PPI9/PF10
PPI 9/GPIO
PPI8/PF11
PPI 8/GPIO
PPI7/PF12
PPI 7/GPIO
PPI6/PF13
PPI 6/GPIO
PPI5/PF14
PPI 5/GPIO
PPI4/PF15
PPI 4/GPIO
Rev. PrD
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May 2006
Preliminary Technical Data
ADSP-BF538/ADSP-BF538F
Table 10. Pin Descriptions (Continued)
Pin Name
Real Time Clock
RTXI
I/O
Function
Driver Type
I
RTC Crystal Input
RTXO
O
RTC Crystal Output
JTAG Port
TCK
I
JTAG Clock
TDO
O
I
JTAG Serial Data Out
JTAG Serial Data In
JTAG Mode Select
C
TDI
TMS
I
TRST
I
JTAG Reset (This pin should be pulled LOW if the JTAG port will not be used.)
Emulation Output
EMU
O
C
Clock
CLKIN
I
Clock/Crystal Input
Crystal Output
XTAL
O
Mode Controls
RESET
I
I
I
Reset
NMI
Non-maskable Interrupt (This pin should be pulled HIGH when not used.)
Boot Mode Strap
BMODE1–0
Voltage Regulator
VROUT0
VROUT1
GPW
O
External FET Drive 0
External FET Drive 1
O
I/O
General-purpose regulator wakeup (This pin should be pulled HIGH when not
used)
Supplies
VDDEXT
VDDINT
VDDRTC
GND
P
P
P
G
I/O Power Supply
Internal Power Supply
Real Time Clock Power Supply
Ground
Rev. PrD
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May 2006
Preliminary Technical Data
ADSP-BF538/ADSP-BF538F
SPECIFICATIONS
Note that component specifications are subject to change
without notice.
OPERATING CONDITIONS
Parameter1
Min
0.8
Nominal
1.2
Max
1.32
3.6
Unit
V
VDDINT
VDDEXT
VDDRTC
VIH
Internal Supply Voltage
External Supply Voltage
2.25
2.25
2.0
3.3
V
Real Time Clock Power Supply Voltage
High Level Input Voltage2, @ VDDEXT =maximum
High Level Input Voltage3, @ VDDEXT =maximum
Low Level Input Voltage2, 4, @ VDDEXT =minimum
3.6
V
3.6
V
VIHCLKIN
VIL
2.2
3.6
V
–0.3
0.6
V
1 Specifications subject to change without notice.
2 The 3.3 V tolerant pins are capable of accepting up to 3.6 V maximum VIH The following bi-directional pins are 3.3 V tolerant: DATA15–0, MISO0, MOSI0, PF15–0, PPI3–0,
SCK1, MISO1, MOSI1, SPI1SS, SPI1SEL, SCK2, MISO2, MOSI2, SPI2SS, SPI2SEL, RX1, TX1, RX2, TX2, DT2PRI, DT2SEC, TSCLK2, DR2PRI, DT2SEC, RSCLK2, RFS2,
TFS2, DT3PRI, DT3SEC, DR3PRI, DR3SEC, RSCLK3, RFS3, TFS3, RFS0, RFS1, RSCLK0, RSCLK1, TSCLK0, TSCLK1, SCK0, TFS0, TFS1, and TMR2–0. The following
input-only pins are 3.3 V tolerant: RESET, RX0, TCK, TDI, TMS, TRST, ARDY, BMODE1–0, BR, DR0PRI, DR0SEC, DR1PRI, DR1SEC, NMI, PPI_CLK, RTXI, and GP.
3 Parameter value applies to the CLKIN pins.
4 Parameter value applies to all input and bi-directional pins.
OPERATING CONDITIONS—APPLIES TO 5V TOLERANT PINS
Parameter1
Min
2.0
Nominal
Max
5.5
Unit
V
2
VIH
5
High Level Input Voltage, @ VDDEXT =maximum
Low Level Input Voltage, @ VDDEXT =minimum
V
2
VIL
5
–0.3
0.8
V
V
1 Specifications subject to change without notice.
2 The 5.V tolerant pins are capable of accepting up to 5.5 V maximum VIH. The following bi-directional pins are 5 V tolerant: SCL0, SCL1, SDA0, SDA1, CANRX, CANTX.
ELECTRICAL CHARACTERISTICS
Parameter1
Test Conditions
Min
Max
Unit
V
VOH
VOL
IIH
High Level Output Voltage2
@ VDDEXT =3.0V, IOH = –0.5 mA
2.4
Low Level Output Voltage2
High Level Input Current3
Low Level Input Current4
Three-State Leakage Current4
Three-State Leakage Current5
Input Capacitance5, 6
@ VDDEXT =3.0V, IOL = 2.0 mA
0.4
V
@ VDDEXT =maximum, VIN = VDD maximum
@ VDDEXT =maximum, VIN = 0 V
@ VDDEXT = maximum, VIN = VDD maximum
@ VDDEXT = maximum, VIN = 0 V
fIN = 1 MHz, TAMBIENT = 25°C, VIN = 2.5 V
TBD
TBD
10
μA
μA
μA
μA
pF
IIL
IOZH
IOZL
CIN
10
TBD
1 Specifications subject to change without notice.
2 Applies to output and bidirectional pins.
3 Applies to input pins.
4 Applies to three-statable pins.
5 Applies to all signal pins.
6 Guaranteed, but not tested.
Rev. PrD
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May 2006
Preliminary Technical Data
ADSP-BF538/ADSP-BF538F
ABSOLUTE MAXIMUM RATINGS
PACKAGE INFORMATION
Stresses greater than those listed below may cause permanent
damage to the device. These are stress ratings only. Functional
operation of the device at these or any other conditions greater
than those indicated in the operational sections of this specifica-
tion is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
The information presented in Figure 9 and Table 12 provides
information about how to read the package brand and relate it
to specific product features. For a complete listing of product
offerings, see the Ordering Guide on Page 55.
a
ADSP-BF5xx
Parameter
Rating
Internal (Core) Supply Voltage (VDDINT
)
–0.3 V to +1.4 V
–0.3 V to +3.8 V
–0.5 V to +3.6 V
–0.5 V to +5.5 V
–0.5 V to VDDEXT +0.5 V
200 pF
tppZccc
vvvvvv.x n.n
External (I/O) Supply Voltage (VDDEXT
)
Input Voltage
Input Voltage1
yyww country_of_origin
B
Output Voltage Swing
Load Capacitance
Figure 9. Product Information on Package
Storage Temperature Range
–65°C to +150°C
+125°C
Junction Temperature Under bias
Table 12. Package Brand Information
1 The 5.V tolerant pins are capable of accepting up to 5.5 V maximum VIH. The
following bi-directional pins are 5 V tolerant: SCL0, SCL1, SDA0, SDA1,
CANRX, CANTX. For other duty cycles, see Table 11.
Brand Key
Field Description
Temperature Range
Package Type
t
pp
Table 11. Maximum Duty Cycle for Input1 Transient Voltage
Z
Lead Free Option (optional)
See Ordering Guide
Assembly Lot Code
Silicon Revision
VIN Max (V)2
3.63
VIN Min (V)
–0.33
Maximum Duty Cycle
ccc
100%
48%
30%
20%
10%
8%
vvvvvv.x
n.n
3.80
–0.50
3.90
–0.60
yyww
Date Code
4.00
–0.70
4.10
–0.80
4.20
–0.90
4.30
–1.00
5%
1 Applies to all signal pins with the exception of CLKIN, XTAL, and VROUT1–0.
2 Only one of the listed options can apply to a particular design.
ESD SENSITIVITY
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADSP-BF538/ADSP-BF538F processors feature proprietary ESD protection circuitry, permanent
damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper
ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. PrD
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May 2006
Preliminary Technical Data
ADSP-BF538/ADSP-BF538F
TIMING SPECIFICATIONS
Table 13 describes the timing requirements for the ADSP-
BF538/ADSP-BF538F processor clocks. Take care in selecting
MSEL, SSEL, and CSEL ratios so as not to exceed the maximum
core clock, system clock and Voltage Controlled Oscillator
(VCO) operating frequencies, as described in Absolute Maxi-
mum Ratings on Page 23. Table 14 describes Phase Locked
Loop operating conditions.
Table 13. Core and System Clock Requirements—ADSP-BF538/ADSP-BF538F—500 MHz
Parameter
fCCLK
Min
Max
500
444
400
333
Unit
MHz
MHz
MHz
MHz
Core Clock Frequency (VDDINT = 1.2 V minimum)
Core Clock Frequency (VDDINT = 1.045 V minimum)
Core Clock Frequency (VDDINT = 0.95 V minimum)
Core Clock Frequency (VDDINT = 0.85 V minimum)
fCCLK
fCCLK
fCCLK
Table 14. Phase Locked Loop Operating Conditions
Parameter
Min
Max
Unit
fVCO
Voltage Controlled Oscillator (VCO) Frequency
50
Max CCLK
MHz
Clock and Reset Timing
Table 15 and Figure 10 describe clock and reset operations. Per
Absolute Maximum Ratings on Page 23, combinations of
CLKIN and clock multipliers must not select core/peripheral
clocks in excess of 500/133 MHz.
Table 15. Clock and Reset Timing
Parameter
Min
Max
100.0
Unit
Timing Requirements
tCKIN
CLKIN Period
CLKIN Low Pulse1
CLKIN High Pulse1
RESET Asserted Pulsewidth Low2
20.0
8.0
ns
ns
ns
ns
tCKINL
tCKINH
tWRST
8.0
11 tCKIN
1 Applies to bypass mode and non-bypass mode.
2 Applies after power-up sequence is complete. At power-up, the processor’s internal phase locked loop requires no more than 2000 CLKIN cycles, while RESET is asserted,
assuming stable power supplies and CLKIN (not including startup time of external clock oscillator).
tCKIN
CLKIN
tCKINL
tCKINH
tWRST
RESET
Figure 10. Clock and Reset Timing
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May 2006
Preliminary Technical Data
ADSP-BF538/ADSP-BF538F
Asynchronous Memory Read Cycle Timing
Table 16 and Table 17 on Page 26 and Figure 11 and Figure 12
on Page 26 describe asynchronous memory read cycle opera-
tions for synchronous and for asynchronous ARDY.
Table 16. Asynchronous Memory Read Cycle Timing with Synchronous ARDY
Parameter
Min
Max
Unit
Timing Requirements
tSDAT
tHDAT
tSARDY
tHARDY
tDO
DATA15–0 Setup Before CLKOUT
DATA15–0 Hold After CLKOUT
2.1
ns
ns
ns
ns
ns
ns
0.8
ARDY Setup Before the Falling Edge of CLKOUT
ARDY Hold After the Falling Edge of CLKOUT
Output Delay After CLKOUT1
TBD
TBD
6.0
tHO
Output Hold After CLKOUT1
0.8
1 Output pins include AMS3–0, ABE1–0, ADDR19–1, AOE, ARE.
HOLD
1 CYCLE
SETUP
2 CYCLES
PROGRAMMED READ ACCESS
4 CYCLES
ACCESS EXTENDED
3 CYCLES
CLKOUT
tDO
tHO
AMSx
ABE1–0
BE, ADDRESS
ADDR19–1
AOE
tDO
tHO
ARE
tHARDY
tSARDY
tHARDY
ARDY
tSARDY
tSDAT
tHDAT
DATA15–0
READ
Figure 11. Asynchronous Memory Read Cycle Timing with Synchronous ARDY
Rev. PrD
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May 2006
Preliminary Technical Data
ADSP-BF538/ADSP-BF538F
Table 17. Asynchronous Memory Read Cycle Timing with Asynchronous ARDY
Parameter
Min
Max
Unit
Timing Requirements
tSDAT
tHDAT
tDANR
DATA15–0 Setup Before CLKOUT
DATA15–0 Hold After CLKOUT
ARDY Negated Delay from AMSx Asserted1
2.1
0.8
ns
ns
ns
(S + RA – 2) × tSCLK
tHAA
tDO
tHO
ARDY Asserted Hold After ARE Negated
Output Delay After CLKOUT2
Output Hold After CLKOUT2
0.0
0.8
ns
ns
ns
6.0
1 S = number of programmed setup cycles, RA = number of programmed read access cycles.
2 Output pins include AMS3–0, ABE1–0, ADDR19–1, AOE, ARE.
HOLD
1 CYCLE
SETUP
2 CYCLES
PROGRAMMED READ ACCESS
4 CYCLES
ACCESS EXTENDED
CLKOUT
tDO
tH
AMSx
ABE1–0
BE, ADDRESS
ADDR19–1
AOE
tDO
tHO
ARE
tHAA
tDANR
ARDY
tSDAT
tHDAT
DATA15–0
READ
Figure 12. Asynchronous Memory Read Cycle Timing with Asynchronous ARDY
Rev. PrD
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May 2006
Preliminary Technical Data
ADSP-BF538/ADSP-BF538F
Asynchronous Memory Write Cycle Timing
Table 18 and Table 19 on Page 28 and Figure 13 and Figure 14
on Page 28 describe asynchronous memory write cycle opera-
tions for synchronous and for asynchronous ARDY.
Table 18. Asynchronous Memory Write Cycle Timing with Synchronous ARDY
Parameter
Min
Max
Unit
Timing Requirements
tSARDY
tHARDY
Switching Characteristics
ARDY Setup Before the Falling Edge of CLKOUT
TBD
TBD
ns
ns
ARDY Hold After the Falling Edge of CLKOUT
tDDAT
tENDAT
tDO
DATA15–0 Disable After CLKOUT
6.0
6.0
ns
ns
ns
ns
DATA15–0 Enable After CLKOUT
Output Delay After CLKOUT1
Output Hold After CLKOUT1
1.0
0.8
tHO
1 Output pins include AMS3–0, ABE1–0, ADDR19–1, DATA15–0, AOE, AWE.
ACCESS
EXTENDED
1 CYCLE
SETUP
2 CYCLES
HOLD
1 CYCLE
PROGRAMMED WRITE
ACCESS 2 CYCLES
CLKOUT
AMSx
tDO
tHO
ABE1–0
BE, ADDRESS
ADDR19–1
tDO
tHO
AWE
tSARDY
ARDY
tSARDY
tHARDY
tHARDY
tDDAT
tENDAT
DATA15–0
WRITE DATA
Figure 13. Asynchronous Memory Write Cycle Timing with Synchronous ARDY
Rev. PrD
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May 2006
Preliminary Technical Data
ADSP-BF538/ADSP-BF538F
Table 19. Asynchronous Memory Write Cycle Timing with Asynchronous ARDY
Parameter
Min
Max
Unit
Timing Requirements
tDANR
tHAA
ARDY Negated Delay from AMSx Asserted1
ns
ns
(S + WA – 2) × tSCLK
ARDY Asserted Hold After ARE Negated
0.0
Switching Characteristics
tDDAT
tENDAT
tDO
DATA15–0 Disable After CLKOUT
6.0
6.0
ns
ns
ns
ns
DATA15–0 Enable After CLKOUT
Output Delay After CLKOUT2
Output Hold After CLKOUT2
1.0
0.8
tHO
1 S = number of programmed setup cycles, WA = number of programmed write access cycles.
2 Output pins include AMS3–0, ABE1–0, ADDR19–1, DATA15–0, AOE, AWE.
ACCESS
EXTENDED
SETUP
2 CYCLES
HOLD
1 CYCLE
PROGRAMMED WRITE
ACCESS 2 CYCLES
CLKOUT
AMSx
tDO
tHO
ABE1–0
BE, ADDRESS
ADDR19–1
tDO
tHO
AWE
tDANW
tHAA
ARDY
tENDAT
DATA15–0
WRITE DATA
Figure 14. Asynchronous Memory Write Cycle Timing with Asynchronous ARDY
Rev. PrD
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May 2006
Preliminary Technical Data
ADSP-BF538/ADSP-BF538F
SDRAM Interface Timing
Table 20. SDRAM Interface Timing
Parameter
Min
Max
Unit
Timing Requirements
tSSDAT
tHSDAT
DATA Setup Before CLKOUT
DATA Hold After CLKOUT
2.1
0.8
ns
ns
Switching Characteristics
tSCLK
CLKOUT Period
7.5
2.5
2.5
ns
ns
ns
ns
ns
ns
ns
tSCLKH
tSCLKL
tDCAD
tHCAD
tDSDAT
tENSDAT
CLKOUT Width High
CLKOUT Width Low
Command, ADDR, Data Delay After CLKOUT1
Command, ADDR, Data Hold After CLKOUT1
Data Disable After CLKOUT
Data Enable After CLKOUT
6.0
6.0
0.8
1.0
1 Command pins include: SRAS, SCAS, SWE, SDQM, SMS, SA10, SCKE.
tSCLK
tSCLKH
CLKOUT
tSSDAT
tSCLKL
tHSDAT
DATA (IN)
tDCAD
tDSDAT
tENSDAT
tHCAD
DATA(OUT)
tDCAD
CMND ADDR
(OUT)
tHCAD
NOTE: COMMAND = SRAS, SCAS, SWE, SDQM, SMS, SA10, SCKE.
Figure 15. SDRAM Interface Timing
Rev. PrD
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Page 29 of 56
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May 2006
Preliminary Technical Data
ADSP-BF538/ADSP-BF538F
External Port Bus Request and Grant Cycle Timing
Table 21 and Table 22 on Page 31 and Figure 16 and Figure 17
on Page 31 describe external port bus request and grant cycle
operations for synchronous and for asynchronous BR.
Table 21. External Port Bus Request and Grant Cycle Timing with Synchronous BR
Parameter
Min
Max
Unit
Timing Requirements
tBS
tBH
BR Setup to Falling Edge of CLKOUT
TBD
TBD
ns
ns
Falling Edge of CLKOUT to BR Deasserted Hold Time
Switching Characteristics
tSD
CLKOUT Low to xMS, Address, and RD/WR disable
4.5
4.5
3.6
3.6
3.6
3.6
ns
ns
ns
ns
ns
ns
tSE
CLKOUT Low to xMS, Address, and RD/WR enable
CLKOUT High to BG High Setup
tDBG
tEBG
tDBH
tEBH
CLKOUT High to BG Deasserted Hold Time
CLKOUT High to BGH High Setup
CLKOUT High to BGH Deasserted Hold Time
CLKOUT
tBH
tBS
BR
tSD
tSE
AMSx
tSD
tSE
ADDR19-1
ABE1-0
tSD
tSE
AWE
ARE
tDBG
tEBG
BG
tDBH
tEBH
BGH
Figure 16. External Port Bus Request and Grant Cycle Timing with Synchronous BR
Rev. PrD
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May 2006
Preliminary Technical Data
ADSP-BF538/ADSP-BF538F
Table 22. External Port Bus Request and Grant Cycle Timing with Asynchronous BR
Parameter
Min
Max
Unit
Timing Requirements
tWBR
BR Pulsewidth
2 x tSCLK
ns
Switching Characteristics
tSD
CLKOUT Low to xMS, Address, and RD/WR disable
4.5
4.5
3.6
3.6
3.6
3.6
ns
ns
ns
ns
ns
ns
tSE
CLKOUT Low to xMS, Address, and RD/WR enable
CLKOUT High to BG High Setup
tDBG
tEBG
tDBH
tEBH
CLKOUT High to BG Deasserted Hold Time
CLKOUT High to BGH High Setup
CLKOUT High to BGH Deasserted Hold Time
CLKOUT
tWBR
BR
tSD
tSE
AMSx
tSD
tSE
ADDR19-1
ABE1-0
tSD
tSE
AWE
ARE
tDBG
tEBG
BG
tDBH
tEBH
BGH
Figure 17. External Port Bus Request and Grant Cycle Timing with Asynchronous BR
Rev. PrD
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Page 31 of 56
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May 2006
Preliminary Technical Data
ADSP-BF538/ADSP-BF538F
Parallel Peripheral Interface Timing
Table 23 and Figure 18, Figure 19, Figure 20, and Figure 21
describe Parallel Peripheral Interface operations.
Table 23. Parallel Peripheral Interface Timing
Parameter
Min
Max
Unit
Timing Requirements
tPCLKW
tPCLK
PPI_CLK Width
PPI_CLK Period1
6.0
15.0
3.0
3.0
2.0
4.0
ns
ns
ns
ns
ns
ns
tSFSPE
External Frame Sync Setup Before PPI_CLK
External Frame Sync Hold After PPI_CLK
Receive Data Setup Before PPI_CLK
Receive Data Hold After PPI_CLK
tHFSPE
tSDRPE
tHDRPE
Switching Characteristics — GP Output and Frame Capture Modes
tDFSPE
tHOFSPE
tDDTPE
tHDTPE
Internal Frame Sync Delay After PPI_CLK
Internal Frame Sync Hold After PPI_CLK
Transmit Data Delay After PPI_CLK
Transmit Data Hold After PPI_CLK
10.0
10.0
ns
ns
ns
ns
0.0
0.0
1 PPI_CLK frequency cannot exceed fSCLK/2
FRAME
SYNC IS
DRIVEN
OUT
DATA0
IS
SAMPLED
POLC = 0
PPI_CLK
PPI_CLK
POLC = 1
t
DFSPE
t
HOFSPE
POLS = 1
PPI_FS1
POLS = 0
POLS = 1
PPI_FS2
POLS = 0
t
t
SDRPE
HDRPE
PPI_DATA
Figure 18. PPI GP Rx Mode with Internal Frame Sync Timing
Rev. PrD
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May 2006
Preliminary Technical Data
ADSP-BF538/ADSP-BF538F
FRAME
SYNC IS
SAMPLED
FOR
DATA0 IS
DATA1 IS
SAMPLED
DATA0
SAMPLED
PPI_CLK
POLC = 0
PPI_CLK
POLC = 1
t
HFSPE
t
SFSPE
POLS = 1
POLS = 0
PPI_FS1
POLS = 1
POLS = 0
PPI_FS2
t
t
SDRPE
HDRPE
PPI_DATA
Figure 19. PPI GP Rx Mode with External Frame Sync Timing
FRAME
SYNC IS
SAMPLED
DATA0 IS
DRIVEN
OUT
PPI_CLK
POLC = 0
PPI_CLK
POLC = 1
t
HFSPE
t
SFSPE
POLS = 1
POLS = 0
PPI_FS1
POLS = 1
POLS = 0
PPI_FS2
t
HDTPE
PPI_DATA
DATA0
t
DDTPE
Figure 20. PPI GP Tx Mode with External Frame Sync Timing
Rev. PrD
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May 2006
Preliminary Technical Data
ADSP-BF538/ADSP-BF538F
FRAME
SYNC IS
DATA0 IS
DRIVEN
OUT
REFERENCED
TO THIS CLOCK
EDGE
PPI_CLK
POLC = 0
PPI_CLK
POLC = 1
t
DFSPE
t
HOFSPE
POLS = 1
PPI_FS1
POLS = 0
POLS = 1
PPI_FS2
POLS = 0
t
DDTPE
t
HDTPE
PPI_DATA
DATA0
Figure 21. PPI GP Tx Mode with Internal Frame Sync Timing
Rev. PrD
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May 2006
Preliminary Technical Data
ADSP-BF538/ADSP-BF538F
Serial Port Timing
Table 24 through Table 27 on Page 36 and Figure 22 on Page 36
through Figure 24 on Page 38 describe Serial Port operations.
Table 24. Serial Ports—External Clock
Parameter
Min
Max
Unit
Timing Requirements
tSFSE
TFS/RFS Setup Before TSCLK/RSCLK (externally generated TFS/RFS)1
3.0
3.0
3.0
3.0
4.5
15.0
ns
ns
ns
ns
ns
ns
tHFSE
TFS/RFS Hold After TSCLK/RSCLK (externally generated TFS/RFS)1
Receive Data Setup Before RSCLK1
Receive Data Hold After RSCLK1
TSCLK/RSCLK Width
tSDRE
tHDRE
tSCLKEW
tSCLKE
TSCLK/RSCLK Period
Switching Characteristics
tDFSE
tHOFSE
tDDTE
tHDTE
TFS/RFS Delay After TSCLK/RSCLK (Internally Generated TFS/RFS)2
TFS/RFS Hold After TSCLK/RSCLK (Internally Generated TFS/RFS)2
Transmit Data Delay After TSCLK2
10.0
10.0
ns
ns
ns
ns
0.0
0.0
Transmit Data Hold After TSCLK2
1 Referenced to sample edge.
2 Referenced to drive edge.
Table 25. Serial Ports—Internal Clock
Parameter
Min
Max
Unit
Timing Requirements
tSFSI
TFS/RFS Setup Before TSCLK/RSCLK (externally generated TFS/RFS)1
8.0
ns
ns
ns
ns
ns
ns
tHFSI
TFS/RFS Hold After TSCLK/RSCLK (externally generated TFS/RFS)1
Receive Data Setup Before RSCLK1
Receive Data Hold After RSCLK1
TSCLK/RSCLK Width
–2.0
6.0
tSDRI
tHDRI
tSCLKEW
tSCLKE
0.0
4.5
TSCLK/RSCLK Period
15.0
Switching Characteristics
tDFSI
TFS/RFS Delay After TSCLK/RSCLK (Internally Generated TFS/RFS)2
TFS/RFS Hold After TSCLK/RSCLK (Internally Generated TFS/RFS)2
Transmit Data Delay After TSCLK2
3.0
3.0
ns
ns
ns
ns
ns
tHOFSI
tDDTI
–1.0
tHDTI
Transmit Data Hold After TSCLK2
–2.0
4.5
tSCLKIW
TSCLK/RSCLK Width
1 Referenced to sample edge.
2 Referenced to drive edge.
Table 26. Serial Ports—Enable and Three-State
Parameter
Min
0
Max
Unit
Switching Characteristics
tDTENE
tDDTTE
tDTENI
tDDTTI
Data Enable Delay from External TSCLK1
Data Disable Delay from External TSCLK1
Data Enable Delay from Internal TSCLK1
Data Disable Delay from Internal TSCLK1
ns
ns
ns
ns
10.0
3.0
–2.0
1 Referenced to drive edge.
Rev. PrD
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Preliminary Technical Data
ADSP-BF538/ADSP-BF538F
Table 27. External Late Frame Sync
Parameter
Min
Max
Unit
Switching Characteristics
tDDTLFSE
tDTENLFS
Data Delay from Late External TFS or External RFS with MCE = 1, MFD = 01, 2
Data Enable from late FS or MCE = 1, MFD = 01, 2
10.0
ns
ns
0
1 MCE = 1, TFS enable and TFS valid follow tDTENLFS and tDDTLFSE
2 If external RFS/TFS setup to RSCLK/TSCLK > tSCLKE/2, then tDDTE/I and tDTENE/I apply; otherwise tDDTLFSE and tDTENLFS apply.
.
DATA RECEIVE- INTERNAL CLOCK
DATA RECEIVE- EXTERNAL CLOCK
DRIVE
EDGE
SAMPLE
EDGE
DRIVE
EDGE
SAMPLE
EDGE
tSCLKIW
tSCLKEW
RSCLK
RSCLK
tDFSE
tDFSE
tHOFSE
RFS
tSFSI
tHFSI
tHOFSE
tSFSE
tHFSE
RFS
tSDRI
tHDRI
tSDRE
tHDRE
DR
DR
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK OR TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.
DATA TRANSMIT- INTERNAL CLOCK
DATA TRANSMIT- EXTERNAL CLOCK
DRIVE
EDGE
SAMPLE
EDGE
DRIVE
EDGE
SAMPLE
EDGE
tSCLKIW
tSCLKEW
TSCLK
TSCLK
tDFSI
tDFSE
tHOFSI
tSFSI
tHFSI
tHOFSE
tSFSE
tHFSE
TFS
DT
TFS
tDDTI
tDDTE
tHDTI
tHDTE
DT
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK OR TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.
DRIVE
EDGE
DRIVE
EDGE
TSCLK (EXT)
TFS ("LATE", EXT.)
TSCLK / RSCLK
tDDTTE
tDTENE
DT
DRIVE
EDGE
DRIVE
EDGE
TSCLK (INT)
TFS ("LATE", INT.)
TSCLK / RSCLK
tDTENI
tDDTTI
DT
Figure 22. Serial Ports
Rev. PrD
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May 2006
Preliminary Technical Data
ADSP-BF538/ADSP-BF538F
EXTERNAL RFS WITH MCE = 1, MFD = 0
DRIVE
SAMPLE
DRIVE
RSCLK
RFS
tHOFSE/I
tSFSE/I
tDDTE/I
tDTENLFSE
tHDTE/I
1ST BIT
2ND BIT
DT
tDDTLFSE
LATE EXTERNAL TFS
DRIVE
SAMPLE
DRIVE
TSCLK
TFS
tSFSE/I
tHOFSE/I
tDDTE/I
tDTENLFSE
tHDTE/I
DT
1ST BIT
2ND BIT
tDDTLFSE
Figure 23. External Late Frame Sync (Frame Sync Setup < tSCLKE/2)
Rev. PrD
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May 2006
Preliminary Technical Data
ADSP-BF538/ADSP-BF538F
EXTERNAL RFS WITH MCE = 1, MFD = 0
DRIVE
SAMPLE
DRIVE
RSCLK
RFS
tSFSE/I
tHOFSE/I
tDDTE/I
tHDTE/I
tDTENLSCK
1ST BIT
DT
2ND BIT
tDDTLSCK
LATE EXTERNAL TFS
DRIVE
SAMPLE
DRIVE
TSCLK
TFS
tSFSE/I
tHOFSE/I
tDDTE/I
tHDTE/I
tDTENLSCK
DT
1ST BIT
2ND BIT
tDDTLSCK
Figure 24. External Late Frame Sync (Frame Sync Setup > tSCLKE/2)
Rev. PrD
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May 2006
Preliminary Technical Data
ADSP-BF538/ADSP-BF538F
Serial Peripheral Interface Port—Master Timing
Table 28 and Figure 25 describe SPI port master operations.
Table 28. Serial Peripheral Interface (SPI) Port—Master Timing
Parameter
Min
Max
Unit
Timing Requirements
tSSPIDM
tHSPIDM
Switching Characteristics
Data Input Valid to SCK Edge (Data Input Setup)
7.5
ns
ns
SCK Sampling Edge to Data Input Invalid
–1.5
tSDSCIM
tSPICHM
tSPICLM
tSPICLK
SPI0SELx Low to First SCK edge (x=0 or 1)
2tSCLK –1.5
2tSCLK –1.5
2tSCLK –1.5
4tSCLK –1.5
2tSCLK –1.5
2tSCLK –1.5
0
ns
ns
ns
ns
ns
ns
ns
ns
Serial Clock High period
Serial Clock Low period
Serial Clock Period
tHDSM
Last SCK Edge to SPI0SELx High (x=0 or 1)
Sequential Transfer Delay
tSPITDM
tDDSPIDM
tHDSPIDM
SCK Edge to Data Out Valid (Data Out Delay)
SCK Edge to Data Out Invalid (Data Out Hold)
6
–1.0
4.0
SPISELx
(OUTPUT)
tSPICLK
tHDSM
tSPITDM
tSDSCIM
tSPICHM
tSPICLM
SCK
(CPOL = 0)
(OUTPUT)
tSPICLM
tSPICHM
SCK
(CPOL = 1)
(OUTPUT)
tDDSPIDM
tHDSPIDM
MOSI
(OUTPUT)
MSB
LSB
CPHA=1
tSSPIDM
tHSPIDM
tSSPIDM
tHSPIDM
MISO
(INPUT)
MSB VALID
LSB VALID
tDDSPIDM
tHDSPIDM
MOSI
(OUTPUT)
MSB
LSB
CPHA=0
tSSPIDM
tHSPIDM
MISO
(INPUT)
MSB VALID
LSB VALID
Figure 25. Serial Peripheral Interface (SPI) Port—Master Timing
Rev. PrD
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May 2006
Preliminary Technical Data
ADSP-BF538/ADSP-BF538F
Serial Peripheral Interface Port—Slave Timing
Table 29 and Figure 26 describe SPI port slave operations.
Table 29. Serial Peripheral Interface (SPI) Port—Slave Timing
Parameter
Min
Max
Unit
Timing Requirements
tSPICHS
tSPICLS
tSPICLK
tHDS
Serial Clock High Period
2tSCLK –1.5
2tSCLK –1.5
4tSCLK –1.5
2tSCLK –1.5
2tSCLK –1.5
2tSCLK –1.5
1.6
ns
ns
ns
ns
ns
ns
ns
ns
Serial Clock low Period
Serial Clock Period
Last SCK Edge to SPI0SS Not Asserted
Sequential Transfer Delay
tSPITDS
tSDSCI
tSSPID
tHSPID
SPI0SS Assertion to First SCK Edge
Data Input Valid to SCK Edge (Data Input Setup)
SCK Sampling Edge to Data Input Invalid
1.6
Switching Characteristics
tDSOE
SPI0SS Assertion to Data Out Active
0
0
0
0
8
ns
ns
ns
ns
tDSDHI
tDDSPID
tHDSPID
SPI0SS Deassertion to Data High impedance
SCK Edge to Data Out Valid (Data Out Delay)
SCK Edge to Data Out Invalid (Data Out Hold)
8
10
10
SPISS
(INPUT)
tSPICHS
tSPICLS
tSPICLK
tHDS
tSPITDS
SCK
(CPOL = 0)
(INPUT)
tSDSCI
tSPICLS
tSPICHS
SCK
(CPOL = 1)
(INPUT)
tDSOE
tDDSPID
tHDSPID
MSB
tDDSPID
tDSDHI
LSB
MISO
(OUTPUT)
tHSPID
tSSPID
CPHA=1
tSSPID
tHSPID
MOSI
(INPUT)
MSB VALID
LSB VALID
tDSOE
tDDSPID
tDSDHI
MISO
(OUTPUT)
MSB
LSB
tHSPID
CPHA=0
tSSPID
MOSI
(INPUT)
MSB VALID
LSB VALID
Figure 26. Serial Peripheral Interface (SPI) Port—Slave Timing
Rev. PrD
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May 2006
Preliminary Technical Data
ADSP-BF538/ADSP-BF538F
General-Purpose Port Timing
Table 30 and Figure 27 describe general-purpose operations.
Table 30. General-Purpose Port Timing
Parameter
Min
tSCLK + 1
0
Max
Unit
ns
Timing Requirement
tWFI
Switching Characteristic
tGPOD GP Port Pin Output Delay From CLKOUT Low
GP Port Pin Input Pulse Width
6
ns
CLKOUT
tGPOD
GPP OUTPUT
tWFI
GPP INPUT
Figure 27. Programmable Flags Cycle Timing
Rev. PrD
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May 2006
Preliminary Technical Data
ADSP-BF538/ADSP-BF538F
Timer Cycle Timing
Table 31 and Figure 28 describe timer expired operations. The
input signal is asynchronous in “width capture mode” and
“external clock mode” and has an absolute maximum input fre-
quency of fSCLK/2 MHz.
Table 31. Timer Cycle Timing
Parameter
Min
Max
Unit
Timing Characteristics
tWL
tWH
Timer Pulsewidth Input Low1 (measured in SCLK cycles)
Timer Pulsewidth Input High1 (measured in SCLK cycles)
1
1
SCLK
SCLK
Switching Characteristic
tHTO
Timer Pulsewidth Output2 (measured in SCLK cycles)
1
(232 – 1)
SCLK
1 The minimum pulsewidths apply for TMRx input pins in width capture and external clock modes. They also apply to the PF1 or PPI_CLK input pins in PWM output mode.
2 The minimum time for tHTO is one cycle, and the maximum time for tHTO equals (232–1) cycles.
CLKOUT
tHTO
TMRx
(PWM OUTPUT MODE)
TMRx
tWL
tWH
(WIDTH CAPTURE AND
EXTERNAL CLOCK MODES)
Figure 28. Timer PWM_OUT Cycle Timing
Rev. PrD
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May 2006
Preliminary Technical Data
ADSP-BF538/ADSP-BF538F
JTAG Test And Emulation Port Timing
Table 32 and Figure 29 describe JTAG port operations.
Table 32. JTAG Port Timing
Parameter
Min
Max
Unit
Timing Requirements
tTCK
TCK Period
20
4
ns
tSTAP
tHTAP
tSSYS
tHSYS
tTRSTW
TDI, TMS Setup Before TCK High
TDI, TMS Hold After TCK High
System Inputs Setup Before TCK High1
System Inputs Hold After TCK High1
TRST Pulsewidth2 (measured in TCK cycles)
ns
4
ns
4
ns
5
ns
4
TCK
Switching Characteristics
tDTDO TDO Delay from TCK Low
tDSYS
System Outputs Delay After TCK Low3
10
12
ns
ns
0
1 System Inputs=ARDY, BMODE1–0, BR, DATA15–0.DR0PRI, DR0SEC, DR1PRI, DR1SEC, MISO0, MOSI0, NMI, PF15–0, PPI_CLK, PPI3–0.SCL0, SCL1, SDA0, SDA1,
SCK, SCK1, MISO1, MOSI1, SPI1SS, SPI1SEL, SCK2, MISO2, MOSI2, SPI2SS, SPI2SEL, RX1, TX1, RX2, TX2, DT2PRI, DT2SEC, TSCLK2, DR2PRI, DT2SEC, RSCLK2,
RFS2, TFS2, DT3PRI, DT3SEC, DR3PRI, DR3SEC, RSCLK3, RFS3, TFS3, CANTX, CANRX, RESET, RFS0, RFS1, RSCLK0, RSCLK1, TSCLK0, TSCLK1, RX0,.SCK0, TFS0,
TFS1, and TMR2–0,
2 50 MHz Maximum
3 System Outputs = AMS, AOE, ARE, AWE, ABE, BG, DATA15–0, DT0PRI, DT0SEC, DT1PRI, DT1SEC, MISO0, MOSI0, PF15–0, PPI3–0, SCK1, MISO1, MOSI1, SPI1SS,
SPI1SEL, SCK2, MISO2, MOSI2, SPI2SS, SPI2SEL, RX1, TX1, RX2, TX2, DT2PRI, DT2SEC, TSCLK2, DR2PRI, DR2SEC, RSCLK2, RFS2, TFS2, DT3PRI, DT3SEC, TSCLK3,
DR3PRI, DR3SEC, RSCLK3, RFS3, TFS3, CANTX, CANRX, RFS0, RFS1, RSCLK0, RSCLK1, TSCLK0, TSCLK1, CLKOUT, TX0, SA10, SCAS, SCK0, SCKE, SMS, SRAS,
SWE, and TMR2–0.
tTCK
TCK
tSTAP
tHTAP
TMS
TDI
tDTDO
TDO
tSSYS
tHSYS
SYSTEM
INPUTS
tDSYS
SYSTEM
OUTPUTS
Figure 29. JTAG Port Timing
Rev. PrD
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Page 43 of 56
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May 2006
Preliminary Technical Data
ADSP-BF538/ADSP-BF538F
OUTPUT DRIVE CURRENTS
150
100
50
VDDEXT = 2.25V @ 95°C
VDD E XT = 2.50V @ 25°C
Figure 30 through Figure 37 on Page 45 shows typical current-
voltage characteristics for the output drivers of the ADSP-
BF538/ADSP-BF538F processors. The curves represent the cur-
rent drive capability of the output drivers as a function of output
voltage.
VDDEXT = 2.75V @
-40°C
VOH
0
120
-
50
VDDEXT = 2.25V @ 95°C
VDDEXT = 2.50V @ 25°C
VDDEXT = 2.75V @ 40°C
100
80
VOL
-
-
100
150
60
40
20
VOH
-
0
0.5
1.0
1.5
2.0
2.5
3.0
SOURCE VOLTAGE (V)
0
Figure 32. Drive Current B (Low VDDEXT
)
-20
-40
VOL
-
60
200
150
-80
VDDE XT = 3.0V @ 95°C
DDE XT = 3.3V @ 25°C
VDDEX T = 3.6V @ 40°C
-
100
V
3. 0
0
0.5
1.0
1.5
2.0
2.5
-
100
50
0
SOURCE VOLTAGE (V)
VO H
Figure 30. Drive Current A (Low VDDEXT
)
150
100
50
-50
VDDEXT = 3.0V @ 95°C
DDEXT = 3.3V @ 25°C
VDDEXT = 3.6V @ 40°C
-
-
-
100
150
200
V
VOL
-
VO H
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
0
SOURCE VOLTAGE (V)
Figure 33. Drive Current B (High VDDEXT
)
-50
VOL
-100
-150
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
SOURCE VOLTAGE (V)
Figure 31. Drive Current A (High VDDEXT
)
Rev. PrD
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May 2006
Preliminary Technical Data
ADSP-BF538/ADSP-BF538F
80
150
100
VDDEXT = 3.0V @ 95°C
VDDEXT = 3.3V @ 25°C
VDDEXT = 2.25V @ 95°C
VDDEXT = 2.50V @ 25°C
VDDEXT = 2.75V @ 40°C
60
40
20
0
V
DDE XT = 3.6V @ -40°C
-
50
0
VOH
VOH
-50
VOL
-20
VOL
-100
-40
-60
-150
0
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
3.0
4.0
0
0.5
1.0
1.5
2.0
2.5
3.0
SOURCE VOLTAGE (V)
SOURCE VOLTAGE (V)
Figure 34. Drive Current C (Low VDDEXT
)
Figure 37. Drive Current D (High VDDEXT)
100
80
0
-10
-20
-30
-40
-50
-60
VDDEX T = 3.0V @ 95°C
DDEX T = 3.3V @ 25°C
VDD E XT = 3.6V @ 40°C
VDD E XT = 2.25V @ 95°C
DD E XT = 2.50V @ 25°C
40°C
V
V
-
V
DDEX T = 2.75V @
-
60
40
VOH
20
0
VOL
-
20
40
60
80
-
VO L
-
-
0.5
1.0
1.5
2.0
2.5
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
SOURCE VOLTAGE (V)
SOURCE VOLTAGE (V)
Figure 35. Drive Current C (High VDDEXT
)
Figure 38. Drive Current E (Low VDDEXT
)
100
80
0
-10
-20
VDDEXT = 2.25V @ 95°C
VDDEXT = 2.50V @ 25°C
VDDEX T = 3.0V @ 95°C
DDEX T = 3.3V @ 25°C
VDDEXT = 3.6V @ 40°C
V
VDDEXT = 2.75V @ -40°C
60
-
40
-30
-40
VOH
20
0
VOL
-50
-60
-70
-80
-
20
40
60
80
-
VOL
-
-
0
0.5
1.0
1.5
2.0
2.5
3.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
SOURCE VOLTAGE (V)
SOURCE VOLTAGE (V)
Figure 36. Drive Current D (Low VDDEXT
)
Figure 39. Drive Current E (High VDDEXT
)
Rev. PrD
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Page 45 of 56
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May 2006
Preliminary Technical Data
ADSP-BF538/ADSP-BF538F
POWER DISSIPATION
TEST CONDITIONS
Total power dissipation has two components: one due to inter-
nal circuitry (PINT) and one due to the switching of external
output drivers (PEXT). Table 33 through Table 35 show the power
dissipation for internal circuitry (VDDINT).
All timing parameters appearing in this data sheet were mea-
sured under the conditions described in this section. Figure 40
shows the measurement point for AC measurements (except
output enable/disable). The measurement point VMEAS is 1.5 V
for VDDEXT (nominal) = 2.5/3.3 V.
See the ADSP-BF53x Blackfin Processor Hardware Reference
Manual for definitions of the various operating -modes and for
instructions on how to minimize system power.
INPUT
1.5V
1.5V
OR
OUTPUT
Many operating conditions can affect power dissipation. System
designers should refer to EE-TBD: Estimating Power for
ADSP-BF538/ADSP-BF538F Blackfin Processors.” This docu-
ment will provide detailed information for optimizing your
design for lowest power.
Figure 40. Voltage Reference Levels for AC
Measurements (Except Output Enable/Disable)
Table 33. Internal Power Dissipation (Hibernate mode)
Output Enable Time Measurement
IDD (nominal1)
TBD
Unit
μA
Output pins are considered to be enabled when they have made
a transition from a high impedance state to the point when they
start driving.
2
IDDHIBERNATE
3
IDDRTC
TBD
μA
The output enable time tENA is the interval from the point when a
reference signal reaches a high or low voltage level to the point
when the output starts driving as shown on the right side of Fig-
ure 41, “Output Enable/Disable,” on page 47.
1 Nominal assumes an operating temperature of 25°C.
2 Measured at VDDEXT = 3.65 V with voltage regulator off (VDDINT = 0 V).
3 Measured at VDDRTC = 3.3 V at 25°C.
The time tENA_MEASURED is the interval, from when the reference
signal switches, to when the output voltage reaches VTRIP(high)
or VTRIP(low). VTRIP(high) is 2.0 V and VTRIP(low) is 1.0 V for
Table 34. Internal Power Dissipation (Deep Sleep mode)
1
VDDINT
0.80
0.90
1.00
1.10
1.26
IDD (nominal2)
19.00
Unit
mA
mA
mA
mA
mA
V
DDEXT (nominal) = 2.5/3.3 V. Time tTRIP is the interval from
when the output starts driving to when the output reaches the
VTRIP(high) or VTRIP(low) trip voltage.
25.00
32.00
Time tENA is calculated as shown in the equation:
40.00
tENA = tENA_MEASURED – tTRIP
If multiple pins (such as the data bus) are enabled, the measure-
ment value is that of the first pin to start driving.
54.00
1 Assumes VDDINT is regulated externally.
2 Nominal assumes an operating temperature of 25°C.
Output Disable Time Measurement
Table 35. Internal Power Dissipation (Full On1 mode)
Output pins are considered to be disabled when they stop driv-
ing, go into a high impedance state, and start to decay from their
output high or low voltage. The output disable time tDIS is the
VDDINT2 @ fCCLK (MHz)
0.8 @ 50 MHz
IDD (nominal3)
32.00
Unit
mA
mA
mA
mA
mA
mA
difference between tDIS MEASURED and tDECAY as shown on the left
_
side of Figure 41.
0.8 @ 250 MHz
0.9 @ 300 MHz
1.0 @ 350 MHz
1.1 @ 444 MHz
1.26 @ 500 MHz
72.00
tDIS = tDIS_MEASURED – tDECAY
98.00
The time for the voltage on the bus to decay by ΔV is dependent
on the capacitive load CL and the load current IL. This decay time
can be approximated by the equation:
132.00
180.00
235.00
tDECAY = (CLΔV) ⁄ IL
1 Processor executing 75% dual MAC, 25% ADD with moderate data bus
activity.
The time tDECAY is calculated with test loads CL and IL, and with
2 Assumes VDDINT is regulated externally.
ΔV equal to 0.5 V for VDDEXT (nominal) = 2.5/3.3 V.
3 Nominal assumes an operating temperature of 25°C.
The time tDIS MEASURED is the interval from when the reference sig-
+_
nal switches, to when the output voltage decays ΔV from the
measured output high or output low voltage.
Rev. PrD
|
Page 46 of 56
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May 2006
Preliminary Technical Data
ADSP-BF538/ADSP-BF538F
Example System Hold Time Calculation
Capacitive Loading
To determine the data output hold time in a particular system,
first calculate tDECAY using the equation given above. Choose ΔV
to be the difference between the ADSP-BF538/ADSP-BF538F
processor’s output voltage and the input threshold for the
device requiring the hold time. CL is the total bus capacitance
(per data line), and IL is the total leakage or three-state current
(per data line). The hold time will be tDECAY plus the various out-
put disable times as specified in the Timing Specifications on
Page 24 (for example tDSDAT for an SDRAM write cycle as shown
in Table 20 on Page 29).
Output delays and holds are based on standard capacitive loads:
30 pF on all pins (see Figure 42). VLOAD is 1.5 V for VDDEXT
(nominal) = 2.5/3.3 V. Figure 43 through Figure 52 on Page 49
show how output rise time varies with capacitance. The delay
and hold specifications given should be derated by a factor
derived from these figures. The graphs in these figures may not
be linear outside the ranges shown.
ABE0 (133 MHz DRIVER), V
(MIN) = 2.25V,TEMPERATURE = 85°C
DDEXT
14
12
REFERENCE
SIGNAL
RISE TIME
10
tDIS_MEASURED
tENA-MEASURED
FALL TIME
tDIS
VOH
tENA
8
VOH
2.0V
(MEASURED)
VOH (MEASURED) ؊ ⌬V
VOL (MEASURED) + ⌬V
6
4
(MEASURED)
1.0V
VOL
VOL
(MEASURED)
(MEASURED)
tDECAY
tTRIP
2
0
OUTPUT STOPS DRIVING
OUTPUT STARTS DRIVING
HIGH IMPEDANCE STATE.
0
50
100
150
200
250
LOAD CAPACITANCE (pF)
TEST CONDITIONS CAUSE THIS
VOLTAGE TO BE APPROXIMATELY 1.5V.
Figure 43. Typical Output Delay or Hold for Driver A at VDDEXT MIN
Figure 41. Output Enable/Disable
50⍀
TO
OUTPUT
PIN
ABE0 (133 MHz DRIVER), V
(MAX) = 3.65V,TEMPERATURE = 85°C
DDEXT
1.5V
12
30pF
10
8
RISE TIME
Figure 42. Equivalent Device Loading for AC Measurements
(Includes All Fixtures)
FALL TIME
6
4
2
0
0
50
100
150
200
250
LOAD CAPACITANCE (pF)
Figure 44. Typical Output Delay or Hold for Driver A at VDDEXT MAX
Rev. PrD
|
Page 47 of 56
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May 2006
Preliminary Technical Data
ADSP-BF538/ADSP-BF538F
CLKOUT (CLKOUT DRIVER), V
(MIN) = 2.25V,TEMPERATURE = 85
°
C
PF9 (33 MHz DRIVER), V
(MIN) = 2.25V,TEMPERATURE = 85°C
DDEXT
DDEXT
12
10
30
25
20
15
10
5
RISE TIME
RISE TIME
8
6
4
2
0
FALL TIME
FALL TIME
0
0
50
100
150
200
250
0
50
100
150
200
250
LOAD CAPACITANCE (pF)
LOAD CAPACITANCE (pF)
Figure 45. Typical Output Delay or Hold for Driver B at VDDEXT MIN
Figure 47. Typical Output Delay or Hold for Driver C at VDDEXT MIN
CLKOUT (CLKOUT DRIVER), V
(MAX) = 3.65V,TEMPERATURE = 85°C
PF9 (33 MHz DRIVER), V
(MAX) = 3.65V,TEMPERATURE = 85°C
DDEXT
DDEXT
10
20
9
8
7
18
16
14
RISE TIME
RISE TIME
6
5
12
10
FALL TIME
FALL TIME
4
3
2
1
0
8
6
4
2
0
0
50
100
150
200
250
0
50
100
150
200
250
LOAD CAPACITANCE (pF)
LOAD CAPACITANCE (pF)
Figure 46. Typical Output Delay or Hold for Driver B at VDDEXT MAX
Figure 48. Typical Output Delay or Hold for Driver C at VDDEXT MAX
Rev. PrD
|
Page 48 of 56
|
May 2006
Preliminary Technical Data
ADSP-BF538/ADSP-BF538F
SCK (66 MHz DRIVER), V
(MIN) = 2.25V,TEMPERATURE = 85°C
DDEXT
PH0 V
(MAX) = 3.65V,TEMPERATURE = 85°C
18
16
14
12
10
8
DDEXT
36
32
RISE TIME
28
24
20
16
12
8
RISE TIME
FALL TIME
6
FALL TIME
4
2
4
0
0
50
100
150
200
250
0
LOAD CAPACITANCE (pF)
0
50
100
150
200
250
LOAD CAPACITANCE (pF)
Figure 49. Typical Output Delay or Hold for Driver D at VDDEXT MIN
Figure 51. Typical Output Delay or Hold for Driver E at VDDEXT MIN
SCK (66 MHz DRIVER), V
(MAX) = 3.65V,TEMPERATURE = 85°C
DDEXT
14
PH0 V
(MAX) = 3.65V,TEMPERATURE = 85°C
DDEXT
36
32
12
10
8
RISE TIME
28
24
20
16
12
8
RISE TIME
FALL TIME
6
4
2
0
FALL TIME
4
0
50
100
150
200
250
LOAD CAPACITANCE (pF)
0
0
50
100
150
200
250
LOAD CAPACITANCE (pF)
Figure 50. Typical Output Delay or Hold for Driver D at VDDEXT MAX
Figure 52. Typical Output Delay or Hold for Driver E at VDDEXT MAX
Rev. PrD
|
Page 49 of 56
|
May 2006
Preliminary Technical Data
ADSP-BF538/ADSP-BF538F
THERMAL CHARACTERISTICS
To determine the junction temperature on the application
printed circuit board use:
TJ = TCASE + (ΨJT × PD)
where:
TJ = Junction temperature (؇C)
TCASE = Case temperature (؇C) measured by customer at top
center of package.
ΨJT = From Table 36
PD = Power dissipation (see Power Dissipation on Page 46 for
the method to calculate PD)
Values of θJA are provided for package comparison and printed
circuit board design considerations. θJA can be used for a first
order approximation of TJ by the equation:
TJ = TA + (θJA × PD)
where:
TA = Ambient temperature (؇C)
Values of θJC are provided for package comparison and printed
circuit board design considerations when an external heatsink is
required.
Values of θJB are provided for package comparison and printed
circuit board design considerations.
In Table 36, airflow measurements comply with JEDEC stan-
dards JESD51-2 and JESD51-6, and the junction-to-board
measurement complies with JESD51-8. The junction-to-case
measurement complies with MIL-STD-883 (Method 1012.1).
All measurements use a 2S2P JEDEC test board.
Table 36. Thermal Characteristics 316-ball BGA
Parameter
Condition
Typical
TBD
Unit
؇C/W
؇C/W
؇C/W
؇C/W
؇C/W
؇C/W
θJA
0 linear m/s air flow
1 linear m/s air flow
2 linear m/s air flow
θJMA
θJMA
θJB
TBD
TBD
TBD
θJC
TBD
ψJT
0 linear m/s air flow
TBD
Rev. PrD
|
Page 50 of 56
|
May 2006
Preliminary Technical Data
316-BALL MINI-BGA PINOUT
ADSP-BF538/ADSP-BF538F
Table 37 on Page 52 lists the mini-BGA pinout by pin number.
Table 38 on Page 53 lists the mini-BGA pinout by signal.
A1 BALL
A1 BALL
A
B
C
D
E
F
A
B
C
D
E
F
G
H
J
G
H
J
K
L
K
L
M
N
P
R
T
M
N
P
R
T
U
V
W
Y
U
V
W
Y
1
2
3
4
5
6
7
8 9 10 11 12 13 14 15 16 17 18 19 20
GND
I/O
VDDRTC
VROUTx
NC
VDDINT
VDDEXT
20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
FLASH CONTROL
GND
VDDINT
VDDRTC
NC
VDDEXT
VROUTx
FLASH CONTROL
I/O
Figure 53. 316-Ball Mini-BGA Pin Configuration (Top View)
Figure 54. 316-Ball Mini-BGA Pin Configuration (Bottom View)
Rev. PrD
|
Page 51 of 56
|
May 2006
Preliminary Technical Data
ADSP-BF538/ADSP-BF538F
Table 37. 316-Ball Mini-BGA Pin Assignment (Numerically by Pin Number)
Ball No. Signal
Ball No. Signal Ball No. Signal Ball No. Signal Ball No. Signal Ball No. Signal
Ball No. Signal
A1
GND
PF10
PF11
C7
C8
C9
SPI2SEL F8
SPI2SS F9
MOSI2 F10
MISO2 F11
GND
GND
GND
GND
GND
GND
GND
J12
J13
J14
J18
J19
J20
K1
GND
GND
GND
AMS0
AMS2
SA10
RFS1
TMR2
M19
M20
N1
ABE0
ABE1
TFS0
T3
T7
T8
GND
W1
TCK
A2
VDDEXT W2
VDDEXT W3
VDDEXT W4
VDDEXT W5
VDDEXT W6
VDDINT W7
VDDINT W8
VDDINT W9
GND
A3
DATA15
DATA13
DATA11
DATA9
DATA7
DATA5
DATA3
DATA1
RSCK2
DR2PRI
DT2PRI
RX2
A4
PPI_CLK C10
N2
DR0PRI T9
A5
PPI0
PPI2
PF15
PF13
C11
C12
C13
C14
SCK2
F12
N3
GND
T10
A6
VDDINT F13
SPI1SEL F14
MISO1 F18
SPI1SS F19
MOSI1 F20
N7
VDDEXT T11
A7
N8
GND
GND
GND
GND
GND
GND
T12
T13
T14
T18
T19
T20
A8
DT3PRI K2
N9
A9
VDDRTC C15
PC4
K3
K7
K8
VDDEXT N10
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
B1
RTXO
RTXI
GND
CLKIN
XTAL
GND
NC
C16
C17
C18
C19
C20
D1
PC8
GND
GND
GND
GND
GND
GND
GND
GND
AMS3
AMS1
AOE
N11
N12
N13
N14
N18
N19
N20
P1
RFS3
W10
SCK1
GND
PC6
G1
G2
G3
G7
G8
G9
SCK0
ADDR7 W11
ADDR8 W12
MOSI0 K9
DT0SEC K10
VDDINT U1
DT3SEC U2
ADDR1 U3
ADDR2 U7
TRST
TMS
GND
W13
W14
W15
SCKE
PF4
GND
GND
GND
GND
GND
GND
GND
GND
BR
K11
K12
K13
K14
K18
K19
K20
L1
TX2
D2
PF5
VDDEXT W16
VDDEXT W17
VDDEXT W18
VDDEXT W19
VDDEXT W20
VDDINT Y1
VDDINT Y2
VDDINT Y3
ADDR18
ADDR15
ADDR13
GND
GND
GPW
D3
DT1SEC G10
TSCK0
RFS0
GND
U8
D7
GND
GND
GND
GND
GND
GND
GND
GND
GND
PC7
G11
G12
G13
G14
G18
G19
G20
H1
P2
U9
VROUT1 D8
P3
U10
GND
PF8
D9
P7
VDDEXT U11
ADDR14
GND
D10
D11
D12
D13
D14
D18
D19
D20
E1
RSCK1
TMR1
GND
GND
GND
GND
GND
GND
GND
GND
GND
TSCK3
ARE
P8
GND
GND
GND
GND
GND
GND
U12
U13
U14
U18
U19
U20
B2
GND
PF9
L2
P9
TDO
B3
CLKOUT L3
SRAS L7
DT1PRI L8
TSCK1 L9
DR1SEC L10
P10
P11
P12
P13
P14
P18
P19
P20
R1
DATA14
DATA12
DATA10
DATA8
DATA6
DATA4
DATA2
DATA0
RFS2
B4
PF3
RSCK3
Y4
B5
PPI1
ADDR9 Y5
ADDR10 Y6
B6
PPI3
H2
B7
PF14
PF12
SCL0
SDA0
CANRX
CANTX
NMI
H3
VDDINT V1
DR3SEC V2
ADDR3 V3
ADDR4 V4
TDI
Y7
Y8
Y9
B8
SMS
PF1
H7
GND
GND
GND
GND
GND
GND
GND
GND
FCE
L11
L12
L13
L14
L18
L19
L20
M1
M2
M3
M7
M8
GND
GND
B9
H8
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
C1
E2
PF2
H9
BMODE1 Y10
BMODE0 Y11
E3
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
PC5
H10
H11
H12
H13
H14
H18
H19
H20
J1
TX0
V5
V6
V7
E7
R2
RSCK0
GND
GND
Y12
TSCK2
TFS2
E8
R3
VDDEXT Y13
VDDEXT Y14
VDDEXT Y15
VDDEXT Y16
VDDEXT Y17
VDDINT Y18
DR2SEC Y19
RESET
E9
AWE
R7
VDDEXT V8
FRESET
SCL1
VDDEXT E10
DT0PRI R8
GND
GND
GND
GND
GND
GND
V9
GND
PC9
E11
E12
E13
E14
TMR0
GND
R9
V10
V11
V12
V13
V14
SDA1
SCAS
SWE
TFS1
R10
ADDR19
ADDR17
ADDR16
GND
GND
GND
VDDEXT R11
GND
GND
GND
GND
GND
GND
R12
R13
R14
R18
R19
R20
VROUT0 E18
J2
DR1PRI M9
DR0SEC M10
BG
Y20
PF6
E19
E20
F1
J3
VDDINT V15
DR3PRI V16
ADDR5 V17
ADDR6 V18
BGH
C2
PF7
ARDY
PF0
J7
GND
GND
GND
GND
GND
M11
M12
M13
M14
M18
DT2SEC
GND
C3
GND
GND
RX1
TX1
J8
C4
F2
MISO0 J9
GND
C5
F3
GND
GND
J10
J11
VDDINT T1
RX0
V19
V20
ADDR11
ADDR12
C6
F7
TFS3
T2
EMU
Rev. PrD
|
Page 52 of 56
|
May 2006
Preliminary Technical Data
ADSP-BF538/ADSP-BF538F
Table 38. 316-Ball Mini-BGA Pin Assignment (Alphabetically by Signal)
Signal
ABE0
Ball No. Signal Ball No. Signal Ball No. Signal Ball No. Signal
Ball No. Signal Ball No. Signal Ball No.
M19
M20
N19
U20
V19
V20
W18
W20
W17
Y19
Y18
W16
Y17
N20
P19
P20
R19
R20
T19
T20
U19
J18
DATA2 Y9
DATA3 W9
DATA4 Y8
DATA5 W8
DATA6 Y7
DATA7 W7
DATA8 Y6
DATA9 W6
DR0PRI N2
DR0SEC J3
DR1PRI J2
DR1SEC H3
DR2PRI W12
DR2SEC V13
DR3PRI R18
DR3SEC P18
DT0PRI M1
DT0SEC G3
DT1PRI H1
DT1SEC D3
DT2PRI W13
DT2SEC V16
DT3PRI F18
DT3SEC N18
GND
GND
GND
GND
GND
GND
E7
E8
E9
F8
F9
F10
GND
GND
GND
GND
GND
GND
K11
K12
K13
L13
L14
M3
GND
GND
GND
GND
GND
GND
GND
GND
GND
GPW
MISO0
MISO1
MISO2
MOSI0
MOSI1
MOSI2
NC
V17
V18
W2
W19
Y1
RFS0
RFS1
RFS2
RFS3
P2
TX0
TX1
TX2
R1
ABE1
K1
C6
ADDR1
ADDR10
ADDR11
ADDR12
ADDR13
ADDR14
ADDR15
ADDR16
ADDR17
ADDR18
ADDR19
ADDR2
ADDR3
ADDR4
ADDR5
ADDR6
ADDR7
ADDR8
ADDR9
AMS0
Y11
T18
W15
VDDEXT K3
VDDEXT B15
VDDEXT T8
VDDEXT T9
VDDEXT T10
VDDEXT T11
VDDEXT U7
VDDEXT U8
VDDEXT U9
VDDEXT U10
VDDEXT U11
VDDEXT V7
VDDEXT M7
VDDEXT N7
VDDEXT P7
VDDEXT R7
VDDEXT T7
VDDEXT V8
VDDEXT V9
VDDEXT V10
VDDEXT V11
VDDINT C12
VDDINT M14
VDDINT N14
VDDINT P14
VDDINT R14
VDDINT T12
VDDINT T13
VDDINT T14
VDDINT U12
VDDINT U13
VDDINT U14
VDDINT V12
VDDRTC A9
VROUT0 B20
VROUT1 A19
RSCK0 R2
RSCK1 L1
RSCK2 W11
RSCK3 U18
Y20
A15
B16
A17
A18
F2
GND F11
GND F12
GND M8
GND M9
GND
GND
GND
GND
GND
GND
F13
F14
G7
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
M10
RTXI
RTXO
RX0
A11
A10
T1
M11
M12
M13
N3
G8
C14
C10
G2
RX1
C5
G9
RX2
W14
J20
H19
G1
E10
K14
L3
SA10
SCAS
SCK0
SCK1
SCK2
SCKE
SCL0
SCL1
SDA0
SDA1
SMS
GND E11
C16
C9
GND
GND
GND
GND
GND
E12
E13
E14
E18
F3
L7
L8
A16
B13
F19
E19
C19
D19
F20
C17
F1
C17
C11
C20
B9
L9
NMI
L10
L11
PC4
PC5
GND F7
GND L12
PC6
Y15
B10
Y16
D20
GND
GND
GND
GND
GND
GND
GND
G10
GND
GND
GND
GND
GND
GND
GND
N8
PC7
AMS1
K19
J19
G11
G12
G13
G14
H7
N9
PC8
AMS2
N10
N11
N12
N13
P3
PC9
AMS3
K18
K20
E20
L19
L20
V14
V15
V5
EMU
FCE
T2
PF0
SPI1SEL C13
SPI1SS C15
SPI2SEL C7
SPI2SS C8
AOE
H18
PF1
E1
ARDY
FRESET Y14
PF10
PF11
PF12
PF13
PF14
PF15
PF2
A2
ARE
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
A1
H8
A3
AWE
A12
A20
B2
GND H9
GND P8
B8
SRAS
SWE
TCK
G20
H20
W1
V1
BG
GND
GND
GND
GND
GND
H10
GND
GND
GND
GND
GND
P9
A8
BGH
H11
H12
H13
H14
P10
P11
P12
P13
B7
BMODE0
BMODE1
BR
B18
B19
C3
A7
TDI
V4
E2
TDO
TFS0
TFS1
TFS2
TFS3
TMR0
TMR1
TMR2
TMS
Y2
G18
B11
B12
A13
G19
Y10
W10
Y5
PF3
B4
N1
J1
CANRX
CANTX
CLKIN
C4
GND J7
GND R3
PF4
D1
C18
D7
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
J8
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
R8
PF5
D2
Y13
M18
M2
L2
J9
R9
PF6
C1
CLKOUT
DATA0
DATA1
DATA10
DATA11
DATA12
DATA13
DATA14
DATA15
D8
J10
J11
J12
J13
J14
K7
R10
R11
R12
R13
T3
PF7
C2
D9
PF8
B1
D10
D11
D12
D13
D14
D18
E3
PF9
B3
K2
XTAL
A14
PPI_CLK A4
U2
W5
PPI0
PPI1
PPI2
PPI3
RESET
A5
B5
TRST
U1
Y4
U3
V2
TSCK0 P1
TSCK1 H2
TSCK2 Y12
TSCK3 L18
W4
K8
A6
B6
Y3
K9
V3
W3
K10
V6
B14
Rev. PrD
|
Page 53 of 56
|
May 2006
Preliminary Technical Data
ADSP-BF538/ADSP-BF538F
OUTLINE DIMENSIONS
Dimensions in Figure 55—316-Ball Mini Ball Grid Array
(BC-316) are shown in millimeters.
15.20 BSC SQ
17.00 BSC SQ
A1 BALL
0.80 BSC BALL PITCH
A1 BALL INDICATOR
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
20 19 18 17 16 1514 13 12 11 10
9 8 7 6 5 4 3 2 1
BOTTOM VIEW
TOP VIEW
0.30 MIN
0.12 MAX
COPLANARITY
1.70
1.61
SIDE VIEW
0.50
SEATING PLANE
1.46
BALL DIAMETER 0.45
0.40
DETAIL A
DETAIL A
NOTES:
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. COMPLIANT TO JEDEC REGISTERED OUTLINE MO-205, VARIATION AM,
WITH THE EXCEPTION OF BALL DIAMETER.
3. CENTER DIMENSIONS ARE NOMINAL.
Figure 55. 316-Ball Mini Ball Grid Array (BC-316)
Rev. PrD
|
Page 54 of 56
|
May 2006
Preliminary Technical Data
ADSP-BF538/ADSP-BF538F
SURFACE MOUNT DESIGN
Table 39 is provided as an aid to PCB design. For industry-
standard design recommendations, refer to IPC-7351,
Generic Requirements for Surface Mount Design and Land Pat-
tern Standard.
Table 39. BGA Data for Use with Surface Mount Design
Solder Mask
Package
Ball Attach Type
Opening
Ball Pad Size
316-Ball Mini Ball Grid Array Solder Mask Defined 0.40 mm diameter 0.50 mm diameter
(BC-316)
ORDERING GUIDE
Model 1
Temperature
Range2
Instruction Flash
Rate (Max) Memory
Operating Voltage
(Nominal)
Package
Package Description
Option
BC-316
BC-316
BC-316
BC-316
BC-316
BC-316
ADSP-BF538BBCZ-4A
ADSP-BF538BBCZ-4F4
ADSP-BF538BBCZ-4F8
ADSP-BF538BBCZ-5A
ADSP-BF538BBCZ-5F4
ADSP-BF538BBCZ-5F8
1 Z = Pb-free part.
–40ºC to +85ºC 400 MHz
–40ºC to +85ºC 400 MHz
–40ºC to +85ºC 400 MHz
–40ºC to +85ºC 500 MHz
–40ºC to +85ºC 500 MHz
–40ºC to +85ºC 500 MHz
NA
1.2 V internal, 2.5 V or 3.3 V I/O 316-Ball Mini BGA
512K byte 1.2 V internal, 2.5 V or 3.3 V I/O 316-Ball Mini BGA
1M byte
NA
1.2 V internal, 2.5 V or 3.3 V I/O 316-Ball Mini BGA
1.2 V internal, 2.5 V or 3.3 V I/O 316-Ball Mini BGA
512K byte 1.2 V internal, 2.5 V or 3.3 V I/O 316-Ball Mini BGA
1M byte 1.2 V internal, 2.5 V or 3.3 V I/O 316-Ball Mini BGA
2 Referenced temperature is ambient temperature.
Rev. PrD
|
Page 55 of 56
|
May 2006
Preliminary Technical Data
ADSP-BF538/ADSP-BF538F
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
PR06172-0-5/06(PrD)
Rev. PrD
|
Page 56 of 56
|
May 2006
相关型号:
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