ADSP-BF561SKBCZ600_技术文档

Blackfin^®Embedded

Symmetric Multi-Processor

a

Preliminary Technical Data

FEATURES

ADSP-BF561

PERIPHERALS

Dual Symmetric 600 Mhz High Performance Blackfin Core

328 KBytes of On-chip Memory (See Memory Info on Page 3)

Each Blackfin Core Includes:

Two 16-Bit MACs, Two 40-Bit ALUs, Four 8-Bit Video ALUs,

40-Bit Shifter

RISC-Like Register and Instruction Model for Ease of Pro-

gramming and Compiler-Friendly Support

Advanced Debug, Trace, and Performance- Monitoring

0.8 - 1.2V core V_DDwith On-Chip Voltage Regulation

3.3V and 2.5V Tolerant I/O

Two Parallel Input/Output Peripheral Interface Units Sup-

porting ITU-R 656 Video and Glueless Interface to ADI

Analog Front End ADCs

Two Dual Channel, Full Duplex Synchronous Serial Ports Sup-

porting Eight Stereo I²S Channels

Dual 16 Channel DMA Controllers and one internal memory

DMA controller

12 General Purpose 32-bit Timer/Counters, with PWM

Capability

SPI-Compatible Port

UART with Support for IrDA®

Dual Watchdog Timers

256-Ball Mini BGA and 297-Ball PBGA Package Options

48 Programable Flags

On-Chip Phase Locked Loop Capable of 1x to 63x Frequency

Multiplication

IRQ CTRL/

JTAG TEST

IRQ CTRL/

TIMER

EMULATION

B B

VOLTAGE

REGULATOR

UART

IRDA®

SPI

L1

DATA

MEMORY

L1

L2 SRAM

DATA

MMU

INSTRUCTION

MEMORY

INSTRUCTION

MEMORY

128 KBYTES

MEMORY

SPORT0

SPORT1

GPIO

IMDMA

CONTROLLER

CORE SYSTEM / BUS INTERFACE

EAB

DMA

CONTROLLER1

32

TIMERS

DMA

CONTROLLER2

DAB

PAB

16

BOOT ROM

16

32

DAB

EXTERNAL PORT

FLASH/SDRAM CONTROL

PPI

Figure 1. Functional Block Diagram

Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc.

Rev. PrC

Information furnished by Analog Devices is believed to be accurate and reliable.

However, no responsibility is assumed by Analog Devices for its use, nor for any

infringements of patents or other rights of third parties that may result from its use.

Specifications subject to change without notice. No license is granted by implication

or otherwise under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective owners.

One Technology Way, P.O.Box 9106, Norwood, MA 02062-9106 U.S.A.

Tel:781/329-4700

Fax:781/326-8703

www.analog.com

ADSP-BF561

Preliminary Technical Data

TABLE OF CONTENTS

General Description ................................................. 3

Portable Low-Power Architecture ............................. 3

Blackfin Processor Core .......................................... 3

Memory Architecture ............................................ 4

Internal (On-chip) Memory ................................. 4

External (Off-Chip) Memory ................................ 5

I/O Memory Space ............................................. 6

Booting ........................................................... 6

Event Handling ................................................. 6

Core Event Controller (CEC) ................................ 6

System Interrupt Controller (SIC) .......................... 6

Event Control ................................................... 7

DMA Controllers .................................................. 8

WatchDog Timers ................................................ 8

Serial Ports (SPORTs) ............................................ 9

Serial Peripheral Interface (SPI) Ports ........................ 9

UART Port .......................................................... 9

Programmable Flags (PFx) .................................... 10

Timers ............................................................. 10

Parallel Peripheral Interface ................................... 10

General Purpose Mode Descriptions .................... 10

Input Mode .................................................... 10

ITU -R 656 Mode Descriptions ........................... 10

Active Video Only Mode ................................... 10

Vertical Blanking Interval Mode .......................... 11

Entire Field Mode ............................................ 11

Dynamic Power Management ................................ 11

Full-On Operating Mode – Maximum Performance . 11

Active Operating Mode – Moderate Power Savings .. 11

Development Tools .............................................. 14

Designing an Emulator-Compatible

Processor Board (Target) ................................... 15

Additional Information ........................................ 15

Pin Descriptions .................................................... 16

Specifications ........................................................ 20

Recommended Operating Conditions ...................... 20

Electrical Characteristics ....................................... 20

Absolute Maximum Ratings ................................... 21

ESD Sensitivity ................................................... 21

Timing Specifications ........................................... 22

Clock and Reset Timing ..................................... 23

Asynchronous Memory Read Cycle Timing ............ 24

Asynchronous Memory Write Cycle Timing ........... 25

SDRAM Interface Timing .................................. 26

External Port Bus Request and Grant Cycle Timing .. 27

Parallel Peripheral Interface Timing ..................... 28

Serial Ports ..................................................... 29

Serial Peripheral Interface (SPI) Port—Master Timing 34

Serial Peripheral Interface (SPI) Port—Slave Timing . 36

Universal Asynchronous Receiver-Transmitter (UART)

Port—Receive and Transmit Timing .................. 38

Timer Cycle Timing .......................................... 39

Programmable Flags Cycle Timing ....................... 40

JTAG Test And Emulation Port Timing ................. 41

Power Dissipation ............................................... 42

Output Drive Currents ......................................... 42

Test Conditions .................................................. 42

Output Enable Time ......................................... 43

Output Disable Time ......................................... 43

Example System Hold Time Calculation ................... 43

Capacitive Loading .............................................. 44

256-ball MBGA Pin Configurations ............................ 45

297-ball PBGA Pin Configurations ............................. 47

Outline Dimensions ................................................ 50

Outline Dimensions ................................................ 51

Ordering Guide ..................................................... 51

Hibernate Operating Mode—Maximum Static Power

Savings ....................................................... 11

Sleep Operating Mode – High Power Savings ......... 11

Deep Sleep Operating Mode – Max. Power Savings .. 11

Power Savings ................................................. 12

Voltage Regulation .............................................. 12

Clock Signals ..................................................... 13

Booting Modes ................................................... 13

Instruction Set Description ................................... 14

REVISION HISTORY

Revision PrC:

• Edits made to pinlists and timing specification.

Rev. PrC

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April 2004

Preliminary Technical Data

ADSP-BF561

GENERAL DESCRIPTION

The ADSP-BF561 processor is a high-performance member of

the Blackfin family of products targeting a variety of multimedia

and telecommunications applications. At the heart of this device

are two independent Analog Devices Blackfin processors. These

Blackfin processors combine a dual-MAC state-of-the-art signal

processing engine, the advantage of a clean, orthogonal RISC-

like microprocessor instruction set, and single-instruction, mul-

tiple-data (SIMD) multimedia capabilities into a single

instruction-set architecture. The ADSP-BF561 device integrates

a general purpose set of digital imaging peripherals creating a

complete system on-chip solution for digital imaging and multi-

media applications.

Additional on-chip memory peripherals include:

• 128 KBytes of Low Latency On-chip SRAM

• Four Channel Internal Memory DMA Controller

• External Memory controller with glueless support for

SDRAM, SRAM, and Flash

PORTABLE LOW-POWER ARCHITECTURE

Blackfin processors provide world-class power management

and performance for embedded signal processing applications.

Blackfin processors are designed in a low power and low voltage

design methodology and feature Dynamic Power Management.

Dynamic Power Management is the ability to vary both the volt-

age and frequency of operation to significantly lower the overall

power dissipation. This translates into an exponential reduction

in power dissipation providing longer battery life to portable

applications.

The ADSP-BF561 processor has 328 KBytes of on-chip mem-

ory. Each Blackfin core includes:

• 16K Bytes of Instruction SRAM/Cache

• 16K Bytes of Instruction SRAM

• 32K Bytes of Data SRAM/Cache

• 32K Bytes of Data SRAM

BLACKFIN PROCESSOR CORE

As shown in Figure 2, each Blackfin core contains two multi-

plier/accumulators (MACs), two 40-bit ALUs, four video ALUs,

and a single shifter. The computational units process 8-bit, 16-

bit, or 32-bit data from the register file.

• 4K Bytes of Scratchpad SRAM

ADDRESS ARITHMETIC UNIT

SP

FP

I3

I2

I1

I0

L3

L2

L1

L0

B3

B2

B1

B0

M3

M2

M1

M0

DAG0

DAG1

P5

P4

P3

SEQUENCER

P2

P1

P0

ALIGN

DECODE

R7

R6

LOOP BUFFER

R5

R4

16

8

CONTROL

UNIT

R3

R2

R1

R0

BARREL

SHIFTER

40

A0

A1

DATA ARITHMETIC UNIT

Figure 2. Blackfin Processor Core

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ADSP-BF561

Preliminary Technical Data

Each MAC performs a 16-bit by 16-bit multiply in every cycle,

with an accumulation to a 40-bit result, providing 8 bits of

extended precision. The ALUs perform a standard set of arith-

metic and logical operations. With two ALUs capable of

operating on 16- or 32-bit data, the flexibility of the computa-

tion units covers the signal processing requirements of a varied

set of application needs.

port a limited multi-issue capability, where a 32-bit instruction

can be issued in parallel with two 16-bit instructions, allowing

the programmer to use many of the core resources in a single

instruction cycle.

The Blackfin assembly language uses an algebraic syntax for

ease of coding and readability. The architecture has been opti-

mized for use in conjunction with the VisualDSP C/C++

compiler, resulting in fast and efficient software

implementations.

Each of the two 32-bit input registers can be regarded as two 16-

bit halves, so each ALU can accomplish very flexible single 16-

bit arithmetic operations. By viewing the registers as pairs of 16-

bit operands, dual 16-bit or single 32-bit operations can be

accomplished in a single cycle. By further taking advantage of

the second ALU, quad 16-bit operations can be accomplished

simply, accelerating the per cycle throughput.

MEMORY ARCHITECTURE

The ADSP-BF561 views memory as a single unified 4G-byte

address space, using 32-bit addresses. All resources including

internal memory, external memory, and I/O control registers

occupy separate sections of this common address space. The

memory portions of this address space are arranged in a hierar-

chical structure to provide a good cost/performance balance of

some very fast, low-latency memory as cache or SRAM very

close to the processor, and larger, lower-cost and performance-

memory systems farther away from the processor. The ADSP-

BF561 memory map is shown in Figure 3.

The powerful 40-bit shifter has extensive capabilities for per-

forming shifting, rotating, normalization, extraction, and

depositing of data. The data for the computational units is

found in a multi-ported register file of sixteen 16-bit entries or

eight 32-bit entries.

A powerful program sequencer controls the flow of instruction

execution, including instruction alignment and decoding. The

sequencer supports conditional jumps and subroutine calls, as

well as zero-overhead looping. A loop buffer stores instructions

locally, eliminating instruction memory accesses for tight

looped code.

The L1 memory system in each core is the highest-performance

memory available to each Blackfin core. The L2 memory pro-

vides additional capacity with lower performance. Lastly, the

off-chip memory system, accessed through the External Bus

Interface Unit (EBIU), provides expansion with SDRAM, flash

memory, and SRAM, optionally accessing more than 768M

bytes of physical memory. The memory DMA controllers pro-

vide high-bandwidth data-movement capability. They can

perform block transfers of code or data between the internal

L1/L2 memories and the external memory spaces.

Two data address generators (DAGs) provide addresses for

simultaneous dual operand fetches from memory. The DAGs

share a register file containing four sets of 32-bit Index, Modify,

Length, and Base registers. Eight additional 32-bit registers pro-

vide pointers for general indexing of variables and stack

locations.

Internal (On-chip) Memory

Blackfin processors support a modified Harvard architecture in

combination with a hierarchical memory structure. Level 1 (L1)

memories are those that typically operate at the full processor

speed with little or no latency. Level 2 (L2) memories are other

memories, on-chip or off-chip, that may take multiple processor

cycles to access. At the L1 level, the instruction memory holds

instructions only. The two data memories hold data, and a dedi-

cated scratchpad data memory stores stack and local variable

information. At the L2 level, there is a single unified memory

space, holding both instructions and data.

The ADSP-BF561 has four blocks of on-chip memory providing

high-bandwidth access to the core.

The first is the L1 instruction memory of each Blackfin core

consisting of 16K bytes of 4-way set-associative cache memory

and 16K bytes of SRAM. The cache memory may also be config-

ured as an SRAM. This memory is accessed at full processor

speed. When configured as SRAM, each of the two 16K banks of

memory is broken into 4K sub-banks which can be indepen-

dently accessed by the processor and DMA.

In addition, half of L1 instruction memory and half of L1 data

memories may be configured as either Static RAMs (SRAMs) or

caches. The Memory Management Unit (MMU) provides mem-

ory protection for individual tasks that may be operating on the

core and may protect system registers from unintended access.

The second on-chip memory block is the L1 data memory of

each Blackfin core which consists of four banks of 16K bytes

each. Two of the L1 data memory banks can be configured as

one way of a two-way set associative cache or as an SRAM. The

other two banks are configured as SRAM. All banks are accessed

at full processor speed. When configured as SRAM, each of the

four 16K banks of memory is broken into 4K sub-banks which

can be independently accessed by the processor and DMA.

The architecture provides three modes of operation: User mode,

Supervisor mode, and Emulation mode. User mode has

restricted access to certain system resources, thus providing a

protected software environment, while supervisor mode has

unrestricted access to the system and core resources.

The third memory block associated with each core is a 4K-byte

scratchpad SRAM which runs at the same speed as the L1 mem-

ories, but is only accessible as data SRAM (it cannot be

The Blackfin instruction set has been optimized so that 16-bit

op-codes represent the most frequently used instructions,

resulting in excellent compiled code density. Complex DSP

instructions are encoded into 32-bit op-codes, representing fully

featured multifunction instructions. Blackfin processors sup-

configured as cache memory and is not accessible via DMA).

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Preliminary Technical Data

ADSP-BF561

COREAMEMORYMAP

COREBMEMORYMAP

0xFFFF FFFF

CORE MMR REGISTERS

0xFFE0 0000

0xFFC0 0000

0xFFB0 1000

0xFFB0 0000

0xFFA1 4000

0xFFA1 0000

0xFFA0 4000

0xFFA0 0000

0xFF90 8000

0xFF90 4000

0xFF90 0000

0xFF80 8000

0xFF80 4000

0xFF80 0000

SYSTEMMMR REGISTERS

RESERVED

L1 SCRATCHPAD SRAM (4K)

RESERVED

L1 INSTRUCTION SRAM/CACHE (16K)

RESERVED

L1 INSTRUCTION SRAM (16K)

RESERVED

L1 DATA BANK B SRAM/CACHE (16K)

L1 DATA BANK B SRAM (16K)

RESERVED

L1 DATA BANK A SRAM/CACHE (16K)

L1 DATA BANK A SRAM (16K)

0xFF80 0000

0xFF70 1000

INTERNAL MEMORY

RESERVED

L1 SCRATCHPAD SRAM(4K)

RESERVED

0xFF70 0000

0xFF61 4000

L1 INSTRUCTION SRAM/CACHE (16K)

RESERVED

0xFF61 0000

0xFF60 4000

L1 INSTRUCTION SRAM(16K)

RESERVED

0xFF60 0000

0xFF50 8000

L1 DATA BANK B SRAM/CACHE (16K)

L1 DATA BANK B SRAM (16K)

RESERVED

0xFF50 4000

0xFF50 0000

0xFF40 8000

0xFF40 4000

0xFF40 0000

L1 DATA BANK A SRAM/CACHE (16K)

L1 DATA BANK A SRAM (16K)

RESERVED

0xFEB2 0000

L2 SRAM(128K)

RESERVED

0xFEB0 0000

0xEF00 4000

0xEF00 0000

BOOT ROM

RESERVED

0x3000 0000

0x2C00 0000

ASYNC MEMORY BANK 3

ASYNC MEMORY BANK 2

ASYNC MEMORY BANK 1

ASYNC MEMORY BANK 0

0x2800 0000

EXTERNAL MEMORY

0x2400 0000

0x2000 0000

RESERVED

SDRAM BANK 3

SDRAM BANK 2

TopoflastSDRAMpage

SDRAM BANK 1

SDRAM BANK 0

0x0000 0000

Figure 3. Memory Map

The fourth on-chip memory system is the L2 SRAM memory

array which provides 128K bytes of high speed SRAM operating

at one half the bandwidth of the core, and slightly longer latency

than the L1 memory banks. The L2 memory is a unified instruc-

tion and data memory and can hold any mixture of code and

data required by the system design. The Blackfin cores share a

dedicated low-latency 64-bit wide data path port into the L2

SRAM memory.

(SDRAM) as well as up to four banks of asynchronous memory

devices including flash, EPROM, ROM, SRAM, and memory

mapped I/O devices.

The PC133-compliant SDRAM controller can be programmed

to interface to up to four banks of SDRAM, with each bank con-

taining between 16M bytes and 128M bytes providing access to

up to 512M bytes of SDRAM. Each bank is independently pro-

grammable and is contiguous with adjacent banks regardless of

the sizes of the different banks or their placement. This allows

flexible configuration and upgradability of system memory

while allowing the core to view all SDRAM as a single, contigu-

ous, physical address space.

Each Blackfin core processor has its own set of core Memory

Mapped Registers (MMRs) but share the same system MMR

registers and 128 KB L2 SRAM memory.

External (Off-Chip) Memory

The asynchronous memory controller can also be programmed

to control up to four banks of devices with very flexible timing

parameters for a wide variety of devices. Each bank occupies a

The ADSP-BF561 external memory is accessed via the External

Bus Interface Unit (EBIU). This interface provides a glueless

connection to up to four banks of synchronous DRAM

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ADSP-BF561

Preliminary Technical Data

64M-byte segment regardless of the size of the devices used so

that these banks will only be contiguous if fully populated with

64M bytes of memory.

The ADSP-BF561 event controller consists of two stages, the

Core Event Controller (CEC) and the System Interrupt Control-

ler (SIC). The Core Event Controller works with the System

Interrupt Controller to prioritize and control all system events.

Conceptually, interrupts from the peripherals enter into the

SIC, and are then routed directly into the general-purpose inter-

rupts of the CEC.

I/O Memory Space

Blackfin processors do not define a separate I/O space. All

resources are mapped through the flat 32-bit address space. On-

chip I/O devices have their control registers mapped into mem-

ory-mapped registers (MMRs) at addresses near the top of the

4G-byte address space. These are separated into two smaller

blocks, one which contains the control MMRs for all core func-

tions, and the other which contains the registers needed for

setup and control of the on-chip peripherals outside of the core.

The core MMRs are accessible only by the core and only in

supervisor mode and appear as reserved space by on-chip

peripherals. The system MMRs are accessible by the core in

supervisor mode and can be mapped as either visible or reserved

to other devices, depending on the system protection model

desired.

Core Event Controller (CEC)

The CEC supports nine general-purpose interrupts (IVG15–7),

in addition to the dedicated interrupt and exception events. Of

these general-purpose interrupts, the two lowest-priority inter-

rupts (IVG15–14) are recommended to be reserved for software

interrupt handlers, leaving seven prioritized interrupt inputs to

support the peripherals of the ADSP-BF561. Table 1 describes

the inputs to the CEC, identifies their names in the Event Vector

Table (EVT), and lists their priorities.

Table 1. Core Event Controller (CEC)

Booting

Priority

Event Class

EVT Entry

(0 is Highest)

The ADSP-BF561 contains a small boot kernel, which config-

ures the appropriate peripheral for booting. If the ADSP-BF561

is configured to boot from boot ROM memory space, the pro-

cessor starts executing from the on-chip boot ROM.

0

Emulation/Test

Reset

EMU

RST

1

2

Non-Maskable

NMI

3

Exceptions

EVX

Event Handling

4

Global Enable

-

The event controller on the ADSP-BF561 handles all asynchro-

nous and synchronous events to the processor. The ADSP-

BF561 provides event handling that supports both nesting and

prioritization. Nesting allows multiple event service routines to

be active simultaneously. Prioritization ensures that servicing of

a higher-priority event takes precedence over servicing of a

lower-priority event. The controller provides support for five

different types of events:

5

Hardware Error

Core Timer

IVHW

IVTMR

IVG7

IVG8

IVG9

IVG10

IVG11

IVG12

IVG13

IVG14

IVG15

6

7

General Interrupt 7

General Interrupt 8

General Interrupt 9

General Interrupt 10

General Interrupt 11

General Interrupt 12

General Interrupt 13

General Interrupt 14

General Interrupt 15

8

9

10

11

12

13

14

15

• Emulation – An emulation event causes the processor to

enter emulation mode, allowing command and control of

the processor via the JTAG interface.

• Reset – This event resets the processor.

• Non-Maskable Interrupt (NMI) – The NMI event can be

generated by the software watchdog timer or by the NMI

input signal to the processor. The NMI event is frequently

used as a power-down indicator to initiate an orderly shut

down of the system.

System Interrupt Controller (SIC)

The System Interrupt Controller provides the mapping and

routing of events from the many peripheral interrupt sources, to

the prioritized general-purpose interrupt inputs of the CEC.

Although the ADSP-BF561 provides a default mapping, the user

can alter the mappings and priorities of interrupt events by writ-

ing the appropriate values into the Interrupt Assignment

Registers (IAR). Table 2 describes the inputs into the SIC and

the default mappings into the CEC.

• Exceptions – Events that occur synchronously to program

flow, i.e., the exception will be taken before the instruction

is allowed to complete. Conditions such as data alignment

violations, undefined instructions, etc. cause exceptions.

• Interrupts – Events that occur asynchronously to program

flow. They are caused by timers, peripherals, input pins,

and an explicit software instruction.

Each event has an associated register to hold the return address

and an associated return-from-event instruction. When an

event is triggered, the state of the processor is saved on the

supervisor stack.

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Preliminary Technical Data

ADSP-BF561

Table 2. Peripheral Interrupt Source Reset State

Table 2. Peripheral Interrupt Source Reset State (Continued)

Peripheral Interrupt Source

PLL wakeup

Chan¹IVG²

Peripheral Interrupt Source

Timer11 interrupt

Chan¹IVG²

0

IVG07

IVG08

IVG09

IVG10

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

IVG10

IVG11

IVG08

IVG09

IVG12

IVG13

IVG07

DMA1 Error

1

FIO0 interrupt A

DMA2 Error

2

FIO0 interrupt B

IMDMA Error

3

FIO1 interrupt A

PPI1 Error

4

FIO1 interrupt B

PPI2 Error

5

FIO2 interrupt A

SPORT0 Error

6

FIO2 interrupt B

SPORT1 Error

7

DMA1 write/read 0 interrupt

DMA1 write/read1 interrupt

DMA2 write/read 0 interrupt

DMA2 write/read 1 interrupt

IMDMA write/read 0 interrupt

IMDMA write/read 1 interrupt

Watchdog Timer

SPI Error

8

UART Error

9

Reserved

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

DMA1 0 interrupt

DMA1 1 interrupt

DMA1 2 interrupt

DMA1 3 interrupt

DMA1 4 interrupt

DMA1 5 interrupt

DMA1 6 interrupt

DMA1 7 interrupt

DMA1 8 interrupt

DMA1 9 interrupt

DMA1 10 interrupt

DMA1 11 interrupt

DMA2 0 interrupt

DMA2 1 interrupt

DMA2 2 interrupt

DMA2 3 interrupt

DMA2 4 interrupt

DMA2 5 interrupt

DMA2 6 interrupt

DMA2 7 interrupt

DMA2 8 interrupt

DMA2 9 interrupt

DMA2 10 interrupt

DMA2 11 interrupt

Timer0 interrupt

Timer1 interrupt

Timer2 interrupt

Timer3 interrupt

Timer4 interrupt

Timer5 interrupt

Timer6 interrupt

Timer7 interrupt

Timer8 interrupt

Timer9 interrupt

Timer10 interrupt

Reserved

Supplemental 0

Supplemental 1

¹Peripheral Interrupt Channel Number

²Default User IVG Interrupt

Event Control

The ADSP-BF561 provides the user with a very flexible mecha-

nism to control the processing of events. In the CEC, three

registers are used to coordinate and control events. Each of the

registers, as follows, is 16-bits wide, while each bit represents a

particular event class:

• CEC Interrupt Latch Register (ILAT) – The ILAT register

indicates when events have been latched. The appropriate

bit is set when the processor has latched the event and

cleared when the event has been accepted into the system.

This register is updated automatically by the controller, but

may be written only when its corresponding IMASK bit is

cleared.

• CEC Interrupt Mask Register (IMASK) – The IMASK reg-

ister controls the masking and unmasking of individual

events. When a bit is set in the IMASK register, that event is

unmasked and will be processed by the CEC when asserted.

A cleared bit in the IMASK register masks the event

thereby preventing the processor from servicing the event

even though the event may be latched in the ILAT register.

This register may be read from or written to while in super-

visor mode. (Note that general-purpose interrupts can be

globally enabled and disabled with the STI and CLI instruc-

tions, respectively.)

• CEC Interrupt Pending Register (IPEND) – The IPEND

register keeps track of all nested events. A set bit in the

IPEND register indicates the event is currently active or

nested at some level. This register is updated automatically

by the controller but may be read while in supervisor mode.

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ADSP-BF561

Preliminary Technical Data

The SIC allows further control of event processing by providing

six 32-bit interrupt control and status registers. Each register

contains a bit corresponding to each of the peripheral interrupt

events shown in Table 2.

The 2D DMA capability supports arbitrary row and column

sizes up to 64K elements by 64K elements, and arbitrary row

and column step sizes up to +/- 32K elements. Furthermore, the

column step size can be less than the row step size, allowing

implementation of interleaved data streams. This feature is

especially useful in video applications where data can be de-

interleaved on the fly.

• SIC Interrupt Mask Register (SIC_IMASK0, SIC_IMASK1)

– This register controls the masking and unmasking of

each peripheral interrupt event. When a bit is set in the reg-

ister, that peripheral event is unmasked and will be

processed by the system when asserted. A cleared bit in the

register masks the peripheral event thereby preventing the

processor from servicing the event.

Examples of DMA types supported by the ADSP-BF561 DMA

controllers include:

• A single, linear buffer that stops upon completion

• A circular, auto-refreshing buffer that interrupts on each

full or fractionally full buffer

• SIC Interrupt Status Register (SIC_ISTAT0, SIC_ISTAT1)

– As multiple peripherals can be mapped to a single event,

this register allows the software to determine which periph-

eral event source triggered the interrupt. A set bit indicates

the peripheral is asserting the interrupt, a cleared bit indi-

cates the peripheral is not asserting the event.

• 1-D or 2-D DMA using a linked list of descriptors

• 2-D DMA using an array of descriptors, specifying only the

base DMA address within a common page

In addition to the dedicated peripheral DMA channels, each

DMA Controller has four memory DMA channels provided for

transfers between the various memories of the ADSP-BF561

system. These enable transfers of blocks of data between any of

the memories—including external SDRAM, ROM, SRAM, and

flash memory—with minimal processor intervention. Memory

DMA transfers can be controlled by a very flexible descriptor-

based methodology or by a standard register-based autobuffer

mechanism.

• SIC Interrupt Wakeup Enable Register (SIC_IWR0,

SIC_IWR1)– By enabling the corresponding bit in this reg-

ister, each peripheral can be configured to wake up the

processor, should the processor be in a powered down

mode when the event is generated. (For more information,

see Dynamic Power Management on Page 11.)

Because multiple interrupt sources can map to a single general-

purpose interrupt, multiple pulse assertions can occur simulta-

neously, before or during interrupt processing for an interrupt

event already detected on this interrupt input. The IPEND reg-

ister contents are monitored by the SIC as the interrupt

acknowledgement.

Further, the ADSP-BF561 has a four channel Internal Memory

DMA (IMDMA) Controller. The IMDMA Controller allows

data transfers between any of the internal L1 and L2 memories.

WATCHDOG TIMERS

The appropriate ILAT register bit is set when an interrupt rising

edge is detected (detection requires two core clock cycles). The

bit is cleared when the respective IPEND register bit is set. The

IPEND bit indicates that the event has entered into the proces-

sor pipeline. At this point the CEC will recognize and queue the

next rising edge event on the corresponding event input. The

minimum latency from the rising edge transition of the general-

purpose interrupt to the IPEND output asserted is three core

clock cycles; however, the latency can be much higher, depend-

ing on the activity within and the mode of the processor.

Each ADSP-BF561 core includes a 32-bit timer, which can be

used to implement a software watchdog function. A software

watchdog can improve system availability by forcing the proces-

sor to a known state, via generation of a hardware reset, non-

maskable interrupt (NMI), or general- purpose interrupt, if the

timer expires before being reset by software. The programmer

initializes the count value of the timer, enables the appropriate

interrupt, then enables the timer. Thereafter, the software must

reload the counter before it counts to zero from the pro-

grammed value. This protects the system from remaining in an

unknown state where software, which would normally reset the

timer, has stopped running due to an external noise condition

or software error.

DMA CONTROLLERS

The ADSP-BF561 has multiple, independent DMA controllers

that support automated data transfers with minimal overhead

for the DSP core. DMA transfers can occur between the ADSP-

BF561's internal memories and any of its DMA-capable periph-

erals. Additionally, DMA transfers can be accomplished

between any of the DMA-capable peripherals and external

devices connected to the external memory interfaces, including

the SDRAM controller and the asynchronous memory control-

ler. DMA-capable peripherals include the SPORTs, SPI port,

UART, and PPI. Each individual DMA-capable peripheral has

at least one dedicated DMA channel.

After a reset, software can determine if the watchdog was the

source of the hardware reset by interrogating a status bit in the

timer control register, which is set only upon a watchdog gener-

ated reset.

The timer is clocked by the system clock (SCLK), at a maximum

frequency of SCLK.

The ADSP-BF561 DMA controllers support both 1-dimen-

sional (1D) and 2-dimensional (2D) DMA transfers. DMA

transfer initialization can be implemented from registers or

from sets of parameters called descriptor blocks.

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ADSP-BF561

provide a full duplex, synchronous serial interface, which sup-

ports both master and slave modes and multimaster

environments.

SERIAL PORTS (SPORTS)

The ADSP-BF561 incorporates two dual-channel synchronous

serial ports (SPORT0 and SPORT1) for serial and multiproces-

sor communications. The SPORTs support the following

features:

Each SPI port’s baud rate and clock phase/polarities are pro-

grammable (see SPI Clock Rate equation), and each has an

integrated DMA controller, configurable to support transmit or

receive data streams. The SPI’s DMA controller can only service

unidirectional accesses at any given time.

• I²S capable operation.

• Bidirectional operation – Each SPORT has two sets of inde-

pendent transmit and receive pins, enabling eight channels

of I²S stereo audio.

f_SCLK

SPI Clock Rate = ----------------------------------

2 × SPIBAUD

• Buffered (8-deep) transmit and receive ports – Each port

has a data register for transferring data words to and from

other DSP components and shift registers for shifting data

in and out of the data registers.

During transfers, the SPI ports simultaneously transmit and

receive by serially shifting data in and out on their two serial

data lines. The serial clock line synchronizes the shifting and

sampling of data on the two serial data lines.

• Clocking – Each transmit and receive port can either use an

external serial clock or generate its own, in frequencies

ranging from (f_SCLK/131,070) Hz to (f_SCLK/2) Hz.

UART PORT

• Word length – Each SPORT supports serial data words

from 3 to 32 bits in length, transferred most-significant-bit

first or least-significant-bit first.

The ADSP-BF561 provides a full duplex Universal Asynchro-

nous Receiver/Transmitter (UART) ports (UART0 and

UART1) fully compatible with PC-standard UARTs. The UART

ports provide a simplified UART interface to other peripherals

or hosts, supporting full duplex, DMA supported, asynchronous

transfers of serial data. Each UART port includes support for 5

to 8 data bits; 1 or 2 stop bits; and none, even, or odd parity. The

UART ports support two modes of operation, as follows:

• Framing – Each transmit and receive port can run with or

without frame sync signals for each data word. Frame sync

signals can be generated internally or externally, active high

or low, and with either of two pulsewidths and early or late

frame sync.

• Companding in hardware – Each SPORT can perform

A-law or µ-law companding according to ITU recommen-

dation G.711. Companding can be selected on the transmit

and/or receive channel of the SPORT without additional

latencies.

• PIO (Programmed I/O) – The processor sends or receives

data by writing or reading I/O-mapped UATX or UARX

registers, respectively. The data is double-buffered on both

transmit and receive.

• DMA (Direct Memory Access) – The DMA controller

transfers both transmit and receive data. This reduces the

number and frequency of interrupts required to transfer

data to and from memory. Each UART has two dedicated

DMA channels, one for transmit and one for receive. These

DMA channels have lower priority than most DMA chan-

nels because of their relatively low service rates.

• DMA operations with single-cycle overhead – Each SPORT

can automatically receive and transmit multiple buffers of

memory data. The DSP can link or chain sequences of

DMA transfers between a SPORT and memory.

• Interrupts – Each transmit and receive port generates an

interrupt upon completing the transfer of a data word or

after transferring an entire data buffer or buffers through

DMA.

Each UART port’s baud rate (see UART Clock Rate equation),

serial data format, error code generation and status, and inter-

rupts are programmable. In the UART Clock Rate equation, the

divisor (D) can be 1 to 65536.

• Multichannel capability – Each SPORT supports 128 chan-

nels out of a 1024-channel window and is compatible with

the H.100, H.110, MVIP-90, and HMVIP standards.

f_SCLK

UART Clock Rate = ---------------

16 × D

SERIAL PERIPHERAL INTERFACE (SPI) PORTS

The ADSP-BF561 has one SPI-compatible ports that enable the

processor to communicate with multiple SPI-compatible

devices.

The UART programmable features include:

• Supporting bit rates ranging from (f_SCLK/ 1048576) to

(f_SCLK/16) bits per second.

The SPI interface uses three pins for transferring data: two data

pins (Master Output-Slave Input, MOSIx, and Master Input-

Slave Output, MISO) and a clock pin (Serial Clock, SCK). One

SPI chip select input pin (SPISS) let other SPI devices select the

DSP, and seven SPI chip select output pins (SPISEL7–1) let the

DSP select other SPI devices. The SPI select pins are reconfig-

ured Programmable Flag pins. Using these pins, the SPI ports

• Supporting data formats from 7 to12 bits per frame.

• Both transmit and receive operations can be configured to

generate maskable interrupts to the processor.

In conjunction with the general-purpose timer functions, auto-

baud detection is supported.

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Preliminary Technical Data

The capabilities of UART0 are further extended with support

for the InfraRed Data Association (IrDA®) Serial InfraRed Phys-

ical Layer Link Specification (SIR) protocol.

addition to the twelve general-purpose programmable timers,

another timer is also provided for each core. These extra timers

are clocked by the internal processor clock (CCLK) and is typi-

cally used as a system tick clock for generation of operating

system periodic interrupts.

PROGRAMMABLE FLAGS (PFX)

The ADSP-BF561 has 48 bi-directional, general-purpose I/O,

Programmable Flag (PF47–0) pins. The Programmable Flag

pins have special functions for SPI port operation. Each pro-

grammable flag can be individually controlled as follows by

manipulation of the flag control, status, and interrupt registers:

PARALLEL PERIPHERAL INTERFACE

The processor provides two Parallel Peripheral Interfaces (PPI)

that can connect directly to parallel A/D and D/A converters,

ITU-R-601/656 video encoders and decoders, and other general

purpose peripherals. Each PPI consists of a dedicated input

clock pin, up to 3 frame synchronization pins, and up to 16 data

pins.

• Flag Direction Control Register – Specifies the direction of

each individual PFx pin as input or output.

• Flag Control and Status Registers – Rather than forcing the

software to use a read-modify-write process to control the

setting of individual flags, the ADSP-BF561 employs a

"write one to set" and "write one to clear" mechanism that

allows any combination of individual flags to be set or

cleared in a single instruction, without affecting the level of

any other flags. Two control registers are provided, one

register is written to in order to set flag values while

another register is written to in order to clear flag values.

Reading the flag status register allows software to interro-

gate the sense of the flags.

In ITU-R 656 mode, the PPI receives and parses a data stream of

8- bit or 10-bit data elements. On-chip decode of embedded

preamble control and synchronization information is

supported.

General Purpose Mode Descriptions

The general-purpose modes of the PPI are intended to suit a

wide variety of data capture and transmission applications. The

modes are divided into four main categories, each allowing up

to 16 bits of data transfer per PPI_CLK cycle:

• Data Receive with Internally Generated Frame Syncs.

• Data Receive with Externally Generated Frame Syncs.

• Data Transmit with Internally Generated Frame Syncs.

• Data Transmit with Externally Generated Frame Syncs.

• Flag Interrupt Mask Registers – The Flag Interrupt Mask

Registers allow each individual PFx pin to function as an

interrupt to the processor. Similar to the Flag Control Reg-

isters that are used to set and clear individual flag values,

one Flag Interrupt Mask Register sets bits to enable inter-

rupt function, and the other Flag Interrupt Mask register

clears bits to disable interrupt function. PFx pins defined as

inputs can be configured to generate hardware interrupts,

while output PFx pins can be configured to generate soft-

ware interrupts.

Input Mode

These modes support ADC/DAC connections, as well as video

communication with hardware signaling. Many of the modes

support more than one level of frame synchronization. If

desired, a programmable delay can be inserted between asser-

tion of a frame sync and reception / transmission of data.

• Flag Interrupt Sensitivity Registers – The Flag Interrupt

Sensitivity Registers specify whether individual PFx pins

are level- or edge-sensitive and specify-if edge-sensitive-

whether just the rising edge or both the rising and falling

edges of the signal are significant. One register selects the

type of sensitivity, and one register selects which edges are

significant for edge-sensitivity.

ITU -R 656 Mode Descriptions

Three distinct ITU-R 656 modes are supported:

• Active Video Only Mode

• Vertical Blanking Only Mode

• Entire Field Mode

TIMERS

There are fourteen (14) programmable timer units in the ADSP-

BF561. Twelve general-purpose timers have an external pin that

can be configured either as a Pulse Width Modulator (PWM) or

timer output, as an input to lock the timer, or for measuring

pulse widths of external events. Each of the twelve general-pur-

pose timer units can be independently programmed as a PWM,

internally or externally clocked timer, or pulse width counter.

The general-purpose timer units can be used in conjunction

with the UART to measure the width of the pulses in the data

stream to provide an auto-baud detect function for a serial

channel.

Active Video Only Mode

In this mode, the PPI does not read in any data between the End

of Active Video (EAV) and Start of Active Video (SAV) pream-

ble symbols, or any data present during the vertical blanking

intervals. In this mode, the control byte sequences are not stored

to memory; they are filtered by the PPI.

Vertical Blanking Interval Mode

In this mode, the PPI only transfers vertical blanking interval

(VBI) data, as well as horizontal blanking information and con-

trol byte sequences on VBI lines.

The general-purpose timers can generate interrupts to the pro-

cessor core providing periodic events for synchronization,

either to the processor clock or to a count of external signals. In

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ADSP-BF561

Table 3. Power Settings (Continued)

Entire Field Mode

In this mode, the entire incoming bitstream is read in through

the PPI. This includes active video, control preamble sequences,

and ancillary data that may be embedded in horizontal and ver-

tical blanking intervals.

Mode

PLL

Bypassed Clock

(CCLK) (SCLK)

Core

System Core

Clock

Power

Sleep

Enabled

–

Disabled Enabled On

Disabled Disabled On

Disabled Disabled Off

Though not explicitly supported, ITU,-656 output functionality

can be achieved by setting up the entire frame structure (includ-

ing active video, blanking and control information) in memory

and streaming the data out of the PPI in a frame sync-less mode.

The processor’s 2D DMA features facilitate this transfer by

allowing the static frame buffer (blanking and control codes) to

be placed in memory once, and simply updating the active video

information on per-frame basis.

Deep Sleep Disabled –

Hibernate Disabled –

Hibernate Operating Mode—Maximum Static Power

Savings

The Hibernate mode maximizes static power savings by dis-

abling the voltage and clocks to the processor core (CCLK) and

to all the synchronous peripherals (SCLK). The internal voltage

regulator for the processor can be shut off by writing b#00 to the

FREQ bits of the VR_CTL register. This disables both CCLK

and SCLK. Furthermore, it sets the internal power supply volt-

age (V_DDINT) to 0 V to provide the lowest static power

dissipation. Any critical information stored internally (memory

contents, register contents, etc.) must be written to a non-vola-

tile storage device prior to removing power if the processor state

is to be preserved. Since V_DDEXTis still supplied in this mode, all

of the external pins tri-state, unless otherwise specified. This

allows other devices that may be connected to the processor to

have power still applied without drawing unwanted current.

The internal supply regulator can be woken up by asserting the

RESET pin.

These modes support ADC/DAC connections, as well as video

communication with hardware signaling. Many of the modes

support more than one level of frame synchronization. If

desired, a programmable delay can be inserted between asser-

tion of a frame sync and reception/transmission of data.

DYNAMIC POWER MANAGEMENT

The ADSP-BF561 provides four operating modes, each with a

different performance/power profile. In addition, Dynamic

Power Management provides the control functions to dynami-

cally alter the processor core supply voltage, further reducing

power dissipation. Control of clocking to each of the ADSP-

BF561 peripherals also reduces power consumption. See Table 3

for a summary of the power settings for each mode.

Sleep Operating Mode—High Dynamic Power Savings

Full-On Operating Mode – Maximum Performance

The Sleep mode reduces power dissipation by disabling the

clock to the processor core (CCLK). The PLL and system clock

(SCLK), however, continue to operate in this mode. Typically an

external event will wake up the processor. When in the Sleep

mode, assertion of wakeup will cause the processor to sense the

value of the BYPASS bit in the PLL Control register (PLL_CTL).

In the Full-On mode, the PLL is enabled and is not bypassed,

providing capability for maximum operational frequency. This

is the default execution state in which maximum performance

can be achieved. The processor cores and all enabled peripherals

run at full speed.

Active Operating Mode – Moderate Power Savings

When in the Sleep mode, system DMA access to L1 memory is

not supported.

In the Active mode, the PLL is enabled but bypassed. Because

the PLL is bypassed, the processor’s core clock (CCLK) and sys-

tem clock (SCLK) run at the input clock (CLKIN) frequency. In

this mode, the CLKIN to CCLK multiplier ratio can be changed,

although the changes are not realized until the Full-On mode is

entered. DMA access is available to appropriately configured L1

memories.

Deep Sleep Operating Mode—Maximum Dynamic Power

Savings

The Deep Sleep mode maximizes power savings by disabling the

clocks to the processor cores (CCLK) and to all synchronous

peripherals (SCLK). Asynchronous peripherals will not be able

to access internal resources or external memory. This powered-

down mode can only be exited by assertion of the reset interrupt

(RESET). If BYPASS is disabled, the processor will transition to

the Full On mode. If BYPASS is enabled, the processor will tran-

sition to the Active mode.

In the Active mode, it is possible to disable the PLL through the

PLL Control register (PLL_CTL). If disabled, the PLL must be

re-enabled before transitioning to the Full-On or Sleep modes.

Table 3. Power Settings

Power Savings

Mode

PLL

Core

System Core

Clock Power

Bypassed Clock

As shown in Table 4, the ADSP-BF561 supports two different

power domains. The use of multiple power domains maximizes

flexibility, while maintaining compliance with industry stan-

dards and conventions. By isolating the internal logic of the

ADSP-BF561 into its own power domain, separate from the I/O,

(CCLK) (SCLK)

Full On

Active

Enabled No

Enabled Enabled On

Enabled/ Yes

Disabled

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ADSP-BF561

Preliminary Technical Data

the processor can take advantage of Dynamic Power Manage-

ment, without affecting the I/O devices. There are no

sequencing requirements for the various power domains.

The Power Savings Factor is calculated as:

Power Savings Factor

2

Table 4. ADSP-BF561 Power Domains

f_CCLKRED

---------------------

f_CCLKNOM

V_DDINTRED

V_DDINTNOM

T_RED

------------

T_NOM

⎛

⎝

⎞

⎠

⎛

⎝

⎞

⎠

--------------------------

=

×

Power Domain

All internal logic

I/O

VDD Range

V_DDINT

V_DDEXT

where the variables in the equations are:

• f_CCLKNOMis the nominal core clock frequency

• f_CCLKREDis the reduced core clock frequency

• V_DDINTNOMis the nominal internal supply voltage

• V_DDINTREDis the reduced internal supply voltage

• T_NOMis the duration running at f_CCLKNOM

• T_REDis the duration running at f_CCLKRED

The percent power savings is calculated as:

The power dissipated by a processor is largely a function of the

clock frequency of the processor and the square of the operating

voltage. For example, reducing the clock frequency by 25%

results in a 25% reduction in dynamic power dissipation, while

reducing the voltage by 25% reduces dynamic power dissipation

by more than 40%. Further, these power savings are additive, in

that if the clock frequency and supply voltage are both reduced,

the power savings can be dramatic.

The Dynamic Power Management feature of the ADSP-BF561

allows both the processor’s input voltage (V_DDINT) and clock

frequency (f_CCLK) to be dynamically controlled.

% Power Savings = (1 – Power Savings Factor) × 100%

The savings in power dissipation can be modeled using the

Power Savings Factor and % Power Savings calculations.

VOLTAGE REGULATION

The ADSP-BF561 processor provides an on-chip voltage regula-

tor that can generate processor core voltage levels 0.85V(-5% /

+10%) to 1.2V(-5% / +10%) from an external 2.25 V to 3.6 V

supply. Figure 4 shows the typical external components

required to complete the power management system. The regu-

lator controls the internal logic voltage levels and is

programmable with the Voltage Regulator Control Register

(VR_CTL) in increments of 50 mV. To reduce standby power

consumption, the internal voltage regulator can be programmed

to remove power to the processor core while keeping I/O power

(V_DDEXT) supplied. While in hibernation, V_DDEXTcan still be

applied, eliminating the need for external buffers. The voltage

regulator can be activated from this powerdown state by assert-

ing RESET, which will then initiate a boot sequence. The

regulator can also be disabled and bypassed at the user’s

discretion.

Figure 4. Voltage Regulator Circuit

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ADSP-BF561

into the SSEL fields define a divide ratio between the PLL output

(VCO) and the system clock. SCLK divider values are 1 through

15. Table 5 illustrates typical system clock ratios:

CLOCK SIGNALS

The ADSP-BF561 can be clocked by an external crystal, a sine

wave input, or a buffered, shaped clock derived from an external

clock oscillator.

Table 5. Example System Clock Ratios

If an external clock is used, it should be a TTL compatible signal

and must not be halted, changed, or operated below the speci-

fied frequency during normal operation. This signal is

connected to the processor’s CLKIN pin. When an external

clock is used, the XTAL pin must be left unconnected.

Signal Name Divider Ratio Example Frequency Ratios

SSEL[3–0]

VCO/SCLK

(MHz)

VCO

100

SCLK

100

50

0001

0110

1010

1:1

Alternatively, because the ADSP-BF561 includes an on-chip

oscillator circuit, an external crystal may be used. The crystal

should be connected across the CLKIN and XTAL pins, with

two capacitors connected as shown in Figure 5

6:1

300

10:1

500

50

The maximum frequency of the system clock is f_SCLK. Note that

the divisor ratio must be chosen to limit the system clock fre-

quency to its maximum of f_SCLK. The SSEL value can be changed

dynamically without any PLL lock latencies by writing the

appropriate values to the PLL divisor register (PLL_DIV).

Capacitor values are dependent on crystal type and should be

specified by the crystal manufacturer. A parallel-resonant, fun-

damental frequency, microprocessor-grade crystal should be

used.

The core clock (CCLK) frequency can also be dynamically

changed by means of the CSEL[1–0] bits of the PLL_DIV regis-

ter. Supported CCLK divider ratios are 1, 2, 4, and 8, as shown

in Table 6. This programmable core clock capability is useful for

fast core frequency modifications.

XTAL

CLKOUT

CLKIN

Table 6. Core Clock Ratios

Signal Name Divider Ratio Example Frequency Ratios

CSEL[1–0]

VCO/CCLK

VCO

500

200

CCLK

500

250

50

Figure 5. External Crystal Connections

00

01

10

11

1:1

2:1

4:1

8:1

As shown in Figure 6, the core clock (CCLK) and system

peripheral clock (SCLK) are derived from the input clock

(CLKIN) signal. An on-chip PLL is capable of multiplying the

CLKIN signal by a user programmable 1x to 63x multiplication

factor. The default multiplier is 10x, but it can be modified by a

software instruction sequence. On-the-fly frequency changes

can be effected by simply writing to the PLL_DIV register.

25

BOOTING MODES

The ADSP-BF561 has three mechanisms (listed in Table 7) for

automatically loading internal L1 instruction memory after a

reset. A fourth mode is provided to execute from external mem-

ory, bypassing the boot sequence.

“FINE” ADJUSTMENT

“COARSE” ADJUSTMENT

ON-THE-FLY

REQUIRES PLL SEQUENCING

Table 7. Booting Modes

BMODE1–0

Description

CCLK

SCLK

× 1, 2, 4, 8

× 1:15

00

Executefrom16-bitexternalmemory(Bypass

Boot ROM)

PLL

1× - 63×

CLKIN

VCO

01

10

11

Boot from 8/16-bit flash

Reserved

Boot from SPI serial ROM (16-bit address

range)

SCLK ≤ CCLK

SCLK ≤ 133 MHZ

Figure 6. Frequency Modification Methods

All on-chip peripherals are clocked by the system clock (SCLK).

The system clock frequency is programmable by means of the

SSEL3–0 bits of the PLL_DIV register. The values programmed

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ADSP-BF561

Preliminary Technical Data

The BMODE pins of the Reset Configuration Register, sampled

during power-on resets and software-initiated resets, imple-

ment the following modes:

• All registers, I/O, and memory are mapped into a unified

4G-byte memory space providing a simplified program-

ming model.

• Execute from 16-bit external memory - Execution starts

from address 0x2000 0000 with 16-bit packing. The boot

ROM is bypassed in this mode. All configuration settings

are set for the slowest device possible (3-cycle hold time,

15-cycle R/W access times, 4-cycle setup).

• Microcontroller features, such as arbitrary bit and bit-field

manipulation, insertion, and extraction; integer operations

on 8-, 16-, and 32-bit data-types; and separate user and ker-

nel stack pointers.

• Code density enhancements, which include intermixing of

16- and 32-bit instructions (no mode switching, no code

segregation). Frequently used instructions are encoded as

16-bits.

• Boot from 8/16-bit external FLASH memory – The 8/16-bit

FLASH boot routine located in boot ROM memory space is

set up using Asynchronous Memory Bank 0. All configura-

tion settings are set for the slowest device possible (3-cycle

hold time; 15-cycle R/W access times; 4-cycle setup).

DEVELOPMENT TOOLS

The ADSP-BF561 is supported with a complete set of

CROSSCORE^TMsoftware and hardware development tools,

including Analog Devices emulators and the VisualDSP++®

development environment. The same emulator hardware that

supports other Analog Devices processors also fully emulates

the ADSP-BF561.

• Boot from SPI serial EEPROM (16-bit addressable) – The

SPI uses the PF2 output pin to select a single SPI EPROM

device, submits a read command at address 0x0000, and

begins clocking data into the beginning of L1 instruction

memory. A 16-bit addressable SPI-compatible EPROM

must be used.

The VisualDSP++ project management environment lets pro-

grammers develop and debug an application. This environment

includes an easy-to-use assembler that is based on an algebraic

syntax, an archiver (librarian/library builder), a linker, a loader,

a cycle-accurate instruction-level simulator, a C/C++ compiler,

and a C/C++ run-time library that includes DSP and mathemat-

ical functions. A key point for these tools is C/C++ code

efficiency. The compiler has been developed for efficient trans-

lation of C/C++ code to Blackfin assembly. The Blackfin

processor has architectural features that improve the efficiency

of compiled C/C++ code.

For each of the boot modes, a boot loading protocol is used to

transfer program and data blocks, from an external memory

device, to their specified memory locations. Multiple memory

blocks may be loaded by any boot sequence. Once all blocks are

loaded, Core A program execution commences from the start of

L1 instruction SRAM (0xFFA0 0000). Core B remains in a held-

off state until a certain register bit is cleared. After that, Core B

will start execution at address 0xFF60 0000.

In addition, bit 4 of the Reset Configuration Register can be set

by application code to bypass the normal boot sequence during

a software reset. For this case, the processor jumps directly to

the beginning of L1 instruction memory.

The VisualDSP++ debugger has a number of important fea-

tures. Data visualization is enhanced by a plotting package that

offers a significant level of flexibility. This graphical representa-

tion of user data enables the programmer to quickly determine

the performance of an algorithm. As algorithms grow in com-

plexity, this capability can have increasing significance on the

designer’s development schedule, increasing productivity. Sta-

tistical profiling enables the programmer to non intrusively poll

the processor as it is running the program. This feature, unique

to VisualDSP++, enables the software developer to passively

gather important code execution metrics without interrupting

the real-time characteristics of the program. Essentially, the

developer can identify bottlenecks in software quickly and effi-

ciently. By using the profiler, the programmer can focus on

those areas in the program that impact performance and take

corrective action.

INSTRUCTION SET DESCRIPTION

The Blackfin processor family assembly language instruction set

employs an algebraic syntax that was designed for ease of coding

and readability. The instructions have been specifically tuned to

provide a flexible, densely encoded instruction set that compiles

to a very small final memory size. The instruction set also pro-

vides fully featured multifunction instructions that allow the

programmer to use many of the processor core resources in a

single instruction. Coupled with many features more often seen

on microcontrollers, this instruction set is very efficient when

compiling C and C++ source code. In addition, the architecture

supports both a user (algorithm/application code) and a super-

visor (O/S kernel, device drivers, debuggers, ISRs) mode of

operations, allowing multiple levels of access to core processor

resources.

Debugging both C/C++ and assembly programs with the Visu-

alDSP++ debugger, programmers can:

The assembly language, which takes advantage of the proces-

sor’s unique architecture, offers the following advantages:

• View mixed C/C++ and assembly code (interleaved source

and object information)

• Seamlessly integrated DSP/CPU features are optimized for

both 8-bit and 16-bit operations.

• Insert breakpoints

• A multi-issue load/store modified-Harvard architecture,

which supports two 16-bit MAC or four 8-bit ALU + two

load/store + two pointer updates per cycle.

• Set conditional breakpoints on registers, memory, and

stacks

• Trace instruction execution

• Perform linear or statistical profiling of program execution

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Preliminary Technical Data

ADSP-BF561

• Fill, dump, and graphically plot the contents of memory

• Perform source level debugging

emulation is assured by the use of the processor’s JTAG inter-

face—the emulator does not affect target system loading or

timing.

• Create custom debugger windows

In addition to the software and hardware development tools

available from Analog Devices, third parties provide a wide

range of tools supporting the Blackfin processor family. Third

Party software tools include DSP libraries, real-time operating

systems, and block diagram design tools.

The VisualDSP++ IDE lets programmers define and manage

software development. Its dialog boxes and property pages let

programmers configure and manage all development tools,

including Color Syntax Highlighting in the VisualDSP++ edi-

tor. These capabilities permit programmers to:

DESIGNING AN EMULATOR-COMPATIBLE

PROCESSOR BOARD (TARGET)

• Control how the development tools process inputs and

generate outputs.

The Analog Devices family of emulators are tools that every sys-

tem developer needs to test and debug hardware and software

systems. Analog Devices has supplied an IEEE 1149.1 JTAG

Test Access Port (TAP) on the ADSP-BF561. The emulator uses

the TAP to access the internal features of the processor, allow-

ing the developer to load code, set breakpoints, observe

variables, observe memory, and examine registers. The proces-

sor must be halted to send data and commands, but once an

operation has been completed by the emulator, the processor is

set running at full speed with no impact on system timing.

• Maintain a one-to-one correspondence with the tool’s

command line switches.

The VisualDSP++ Kernel (VDK) incorporates scheduling and

resource management tailored specifically to address the mem-

ory and timing constraints of embedded, real-time

programming. These capabilities enable engineers to develop

code more effectively, eliminating the need to start from the

very beginning, when Developing new application code. The

VDK features include Threads, Critical and Unscheduled

regions, Semaphores, Events, and Device flags. The VDK also

supports Priority-based, Pre-emptive, Cooperative and Time-

Sliced scheduling approaches. In addition, the VDK was

designed to be scalable. If the application does not use a specific

feature, the support code for that feature is excluded from the

target system.

To use these emulators, the target board must include a header

that connects the processor’s JTAG port to the emulator.

For details on target board design issues including mechanical

layout, single processor connections, multiprocessor scan

chains, signal buffering, signal termination, and emulator pod

logic, see the EE-68: Analog Devices JTAG Emulation Technical

Reference on the Analog Devices web site (www.analog.com)—

use site search on “EE-68.” This document is updated regularly

to keep pace with improvements to emulator support.

Because the VDK is a library, a developer can decide whether to

use it or not. The VDK is integrated into the VisualDSP++

development environment, but can also be used with standard

command-line tools. When the VDK is used, the development

environment assists the developer with many error-prone tasks

and assists in managing system resources, automating the gen-

eration of various VDK based objects, and visualizing the

system state, when debugging an application that uses the VDK.

To use these emulators, the target board must include a header

that includes a header that connects the processor’s JTAG port

to the emulation.

ADDITIONAL INFORMATION

VCSE is Analog Devices technology for creating, using, and

reusing software components (independent modules of sub-

stantial functionality) to quickly and reliably assemble software

applications. Download components from the Web and drop

them into the application. Publish component archives from

within VisualDSP++. VCSE supports component implementa-

tion in C/C++ or assembly language.

This data sheet provides a general overview of the ADSP-BF561

architecture and functionality. For detailed information on the

Blackfin DSP family core architecture and instruction set, refer

to the ADSP-BF561 Hardware Reference and the Blackfin Family

Instruction Set Reference.

Use the Expert Linker to visually manipulate the placement of

code and data on the embedded system. View memory utiliza-

tion in a color-coded graphical form, easily move code and data

to different areas of the processor or external memory with the

drag of the mouse, examine run time stack and heap usage. The

Expert Linker is fully compatible with existing Linker Definition

File (LDF), allowing the developer to move between the graphi-

cal and textual environments.

Analog Devices’ emulators use the IEEE 1149.1 JTAG test access

port of the ADSP-BF561 to monitor and control the target

board processor during emulation. The emulator provides full-

speed emulation, allowing inspection and modification of mem-

ory, registers, and processor stacks. Non intrusive in-circuit

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ADSP-BF561

Preliminary Technical Data

PIN DESCRIPTIONS

ADSP-BF561 pin definitions are listed in Table 8. Unused

inputs should be tied or pulled to V_DDEXTor GND.

Table 8. Pin Descriptions

Block

Pin Name

Type Signals Function

Driver Pull-up/down requirement

Type

EBIU

ADDR[25:2]

O

24

32

4

Address Bus for Async/Sync Access

Data Bus for Async/Sync Access

none

A

DATA[31:0]

I/O

O

ABE[3:0]/SDQM[3:0]

Byte Enables/Data Masks for Async

/Sync Access

BG

O

I

1

4

1

8

1

8

1

Bus Grant

A

-

none

BR

Bus Request

pull-up required if function not used

BGH

O

I

Bus Grant Hang

Row Address Strobe

Column Address Strobe

Write Enable

A

B

A

-

none

EBIU

(SDRAM)

SRAS

none

SCAS

none

SWE

none

SCKE

Clock Enable

none

SCLK0/CLKOUT

SCLK1

SA10

Clock Output Pin 0

Clock Output Pin 1

SDRAM A10 Pin

Bank Select

none

SMS[3:0]

AMS[3:0]

ARDY

AOE

none

EBIU

(ASYNC)

Bank Select

none

Hardware Ready Control

Output Enable

Write Enable

pull-up required if function not used

none

O

A

C

-

AWE

none

ARE

Read Enable

none

PPI1

PPI2

JTAG

PPI1D[15:8] /PF[47:40] I/O

PPI Data / Programmable Flag Pins

PPI Data Pins

software configurable, none

none

PPI1D[7:0]

I/O

I

PPI1CLK

PPI Clock

PPI1SYNC1/ TMR8

PPI1SYNC2/ TMR9

PPI1SYNC3

I/O

PPI Sync / Timer

PPI Sync

C

-

PPI2D[15:8] /PF[39:32] I/O

PPI Data / Programmable Flag Pins

PPI Data Pins

PPI2D[7:0]

I/O

PPI2CLK

I

PPI Clock

PPI2SYNC1/ TMR10

I/O

PPI Sync / Timer

PPI Sync

C

-

PPI2SYNC2/ TMR11

I/O

PPI2SYNC3

EMU

I/O

O

I

Emulation Output

JTAG Clock

TCK

internal pull-down

none

TDO

O

I

JTAG Serial Data Out

JTAG Serial Data In

JTAG Mode Select

JTAG Reset

C

-

TDI

internal pull-down

TMS

I

-

TRST

I

-

external down necessary if JTAG not

used

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April 2004

Preliminary Technical Data

ADSP-BF561

Table 8. Pin Descriptions (Continued)

Block

Pin Name

RX/PF27

TX/PF26

MOSI

Type Signals Function

Driver Pull-up/down requirement

Type

UART

I/O

1

UART Receive

/ Programmable Flag

C

software configurable,

no pull-up/down necessary

UART Transmit

/ Programmable Flag

C

software configurable,

no pull-up/down necessary

SPI

Master Out Slave In

software configurable,

no pull-up/down necessary

MISO

SCK

I/O

1

Master In Slave Out

SPI Clock

C

pull-up is necessary if booting via SPI

D

software configurable,

no pull-up/down necessary

SPORT0

RSCLK0/PF28

RFS0/PF19

I/O

I

1

Sport0 / Programmable Flag

D

C

-

software configurable,

no pull-up/down necessary

Sport0 Receive Frame Sync

/ Programmable Flag

software configurable,

no pull-up/down necessary

DR0PRI

Sport0 Receive Data Primary

software configurable,

no pull-up/down necessary

DR0SEC/PF20

TSCLK0/PF29

TFS0/PF16

I/O

I

Sport0 Receive Data Secondary

/ Programmable Flag

C

D

C

D

C

-

software configurable,

no pull-up/down necessary

Sport0 Transmit Serial Clock

/ Programmable Flag

software configurable,

no pull-up/down necessary

Sport0 Transmit Frame Sync

/ Programmable Flag

software configurable,

no pull-up/down necessary

DT0PRI/PF18

DT0SEC/PF17

RSCLK1/PF30

RFS1/PF24

Sport0 Transmit Data Primary

/ Programmable Flag

software configurable,

no pull-up/down necessary

Sport0 Transmit Data Secondary

/ Programmable Flag

software configurable,

no pull-up/down necessary

SPORT1

Sport1 / Programmable Flag

software configurable,

no pull-up/down necessary

Sport1 Receive Frame Sync

/ Programmable Flag

software configurable,

no pull-up/down necessary

DR1PRI

Sport1 Receive Data Primary

software configurable,

no pull-up/down necessary

DR1SEC/PF25

TSCLK1/PF31

TFS1/PF21

I/O

Sport1 Receive Data Secondary

/ Programmable Flag

C

D

C

software configurable,

no pull-up/down necessary

Sport1 Transmit Serial Clock

/ Programmable Flag

software configurable,

no pull-up/down necessary

Sport1 Transmit Frame Sync

/ Programmable Flag

software configurable,

no pull-up/down necessary

DT1PRI/PF23

DT1SEC/PF22

Sport1 Transmit Data Primary

/ Programmable Flag

software configurable,

no pull-up/down necessary

Sport1 Transmit Data Secondary

/ Programmable Flag

software configurable,

no pull-up/down necessary

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April 2004

ADSP-BF561

Preliminary Technical Data

Table 8. Pin Descriptions (Continued)

Block

Pin Name

Type Signals Function

Driver Pull-up/down requirement

Type

PF/TIMER PF15/EXT CLK

I/O

I

1

Programmable Flag

/ external timer clock input

C

software configurable,

no pull-up/down necessary

PF14

PF13

PF12

PF11

PF10

PF9

Programmable Flag

software configurable,

no pull-up/down necessary

software configurable,

no pull-up/down necessary

software configurable,

no pull-up/down necessary

software configurable,

no pull-up/down necessary

software configurable,

no pull-up/down necessary

software configurable,

no pull-up/down necessary

PF8

software configurable,

no pull-up/down necessary

PF7/SPISEL7/

TMR7