ADSP-BF701_技术文档

Blackfin+ Core

Embedded Processor

ADSP-BF700/701/702/703/704/705/706/707

FEATURES

MEMORY

Blackfin+ core with up to 400 MHz performance

Dual 16-bit or single 32-bit MAC support per cycle

16-bit complex MAC and many other instruction set

enhancements

136 kB L1 SRAM with multi-parity-bit protection 

(64 kB instruction, 64 kB data, 8 kB scratchpad)

Large on-chip L2 SRAM with ECC protection

256 kB, 512 kB, 1 MB variants

Instruction set compatible with previous Blackfin products

Low-cost packaging

88-Lead LFCSP_VQ (QFN) package (12 mm × 12 mm), 

RoHS compliant

On-chip L2 ROM (512 kB)

L3 interface (CSP_BGA only) optimized for lowest system

power, providing 16-bit interface to DDR2 or LPDDR DRAM

devices (up to 200 MHz)

Security and one-time-programmable memory

Crypto hardware accelerators

184-Ball CSP_BGA package (12 mm × 12 mm × 0.8 mm

pitch), RoHS compliant

Low system power with < 100 mW core domain power at

400 MHz (< 0.25 mW/MHz) at 25°C T_JUNCTION

Fast secure boot for IP protection

memDMA encryption/decryption for fast run-time security

PERIPHERALS FEATURES

See Figure 1, Processor Block Diagram and Table 1, Processor

Comparison

SYSTEM CONTROL BLOCKS

PERIPHERALS

1× TWI

EMULATOR

TEST & CONTROL

PLL & POWER

MANAGEMENT

FAULT

MANAGEMENT

EVENT

CONTROL

WATCHDOG

8× TIMER

1× COUNTER

2× CAN

L2 MEMORY

UP TO

1M BYTE SRAM

2× UART

512K BYTE

ROM

B

ECC-PROTECTED

(& DMA MEMORY

PROTECTION)

SPI HOST PORT

2x QUAD SPI

136K BYTE PARITY BIT PROTECTED

L1 SRAM INSTRUCTION/DATA

GPIO

1x DUAL SPI

2× SPORT

1× MSI

(SD/SDIO)

SYSTEM FABRIC

1× PPI

EXTERNAL

BUS

INTERFACES

ANALOG

SUB

SYSTEM

HARDWARE

FUNCTIONS

STATIC MEMORY

CONTROLLER

MEMORY

PROTECTION

OTP

MEMORY

SYSTEM PROTECTION

2× CRC

3× MDMA

STREAMS

HADC

CRYPTO ENGINE (SECURITY)

DYNAMIC MEMORY

CONTROLLER

1× RTC

LPDDR

16

1× USB 2.0 HS OTG

DDR2

Figure 1. Processor Block Diagram

Blackfin+ is a trademark of Analog Devices, Inc.; Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc.

Rev. A Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable.

However, no responsibility is assumed by Analog Devices for its use, nor for any

infringements of patents or other rights of third parties that may result from its use.

Specifications subject to change without notice. No license is granted by implication

or otherwise under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.

Tel: 781.329.4700

Technical Support

www.analog.com

ADSP-BF700/701/702/703/704/705/706/707

TABLE OF CONTENTS

General Description ................................................. 3

Blackfin+ Processor Core ........................................ 4

Instruction Set Description ..................................... 5

Processor Infrastructure ......................................... 5

Memory Architecture ............................................ 7

Security Features .................................................. 8

Processor Safety Features ........................................ 8

Additional Processor Peripherals .............................. 9

Power and Clock Management ............................... 12

System Debug .................................................... 15

Development Tools ............................................. 15

Additional Information ........................................ 16

Related Signal Chains .......................................... 16

Security Features Disclaimer .................................. 17

ADSP-BF70x Detailed Signal Descriptions ................... 18

184-Ball CSP_BGA Signal Descriptions ....................... 22

GPIO Multiplexing for 184-Ball CSP_BGA .................. 29

ADSP-BF70x Designer Quick Reference ...................... 38

Specifications ........................................................ 50

Operating Conditions ........................................... 50

Electrical Characteristics ....................................... 53

HADC .............................................................. 58

Package Information ............................................ 59

Absolute Maximum Ratings ................................... 59

ESD Sensitivity ................................................... 59

Timing Specifications ........................................... 60

Output Drive Currents ....................................... 102

Test Conditions ................................................ 104

Environmental Conditions .................................. 106

ADSP-BF70x 184-Ball CSP_BGA Ball Assignments 

(Numerical by Ball Number) ................................ 107

ADSP-BF70x 12 mm × 12 mm 88-Lead LFCSP (QFN) 

Lead Assignments (Numerical by Lead Number) ...... 110

Outline Dimensions .............................................. 113

Surface-Mount Design ........................................ 114

Planned Automotive Production Products .................. 115

Ordering Guide ................................................... 116

12 mm × 12 mm 88-Lead LFCSP (QFN) 

Signal Descriptions ............................................. 31

GPIO Multiplexing for 12 mm × 12 mm 88-Lead 

LFCSP (QFN) .................................................... 36

REVISION HISTORY

9/15—Rev. 0 to Rev. A

Updated Processor Comparison .................................. 3

Updated Serial Ports (SPORTs) ................................. 10

Updated Mobile Storage Interface (MSI) ..................... 11

Updated External Components for RTC ...................... 13

Updated Development Tools .................................... 15

Updated SPI Port—SPI_RDY Timing ......................... 92

Added Models to Ordering Guide ............................. 116

Rev. A

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ADSP-BF700/701/702/703/704/705/706/707

GENERAL DESCRIPTION

The ADSP-BF70x processor is a member of the Blackfin^®

family of products. The Blackfin processor combines a dual-

MAC 16-bit state-of-the-art signal processing engine, the

advantages of a clean, orthogonal RISC-like microprocessor

instruction set, and single-instruction, multiple-data (SIMD)

multimedia capabilities into a single instruction-set architec-

ture. New enhancements to the Blackfin+ core add 32-bit MAC

and 16-bit complex MAC support, cache enhancements, branch

prediction and other instruction set improvements—all while

maintaining instruction set compatibility to previous Blackfin

products.

The processor offers performance up to 400 MHz, as well as low

static power consumption. Produced with a low-power and low-

voltage design methodology, they provide world-class power

management and performance.

By integrating a rich set of industry-leading system peripherals

and memory (shown in Table 1), the Blackfin processor is the

platform of choice for next-generation applications that require

RISC-like programmability, multimedia support, and leading-

edge signal processing in one integrated package. These applica-

tions span a wide array of markets, from automotive systems to

embedded industrial, instrumentation, video/image analysis,

biometric and power/motor control applications.

Table 1. Processor Comparison

ADSP-

BF700

ADSP-

BF701

ADSP-

BF702

ADSP-

BF703

ADSP-

BF704

ADSP-

BF705

ADSP-

BF706

ADSP-

BF707

Processor Feature

Maximum Speed Grade (MHz)¹

Maximum SYSCLK (MHz)

Package Options

200

100

400

200

88-Lead

LFCSP

184-Ball

CSP_BGA

88-Lead

LFCSP

184-Ball

CSP_BGA

88-Lead

LFCSP

184-Ball

CSP_BGA

88-Lead

LFCSP

184-Ball

CSP_BGA

GPIOs

43

47

43

47

43

47

43

47

L1 Instruction SRAM

L1 Instruction SRAM/Cache

L1 Data SRAM

48K

16K

32K

8K

L1 Data SRAM/Cache

L1 Scratchpad (L1 Data C)

L2 SRAM

128K

256K

512K

1024K

L2 ROM

512K

DDR2/LPDDR (16-bit)

I²C

No

Yes

No

Yes

No

Yes

No

Yes

1

Up/Down/Rotary Counter

GP Timer

8

Watchdog Timer

GP Counter

1

SPORTs

2

Quad SPI

2

Dual SPI

1

SPI Host Port

1

USB 2.0 HS OTG

Parallel Peripheral Interface

CAN

1

2

UART

2

Real-Time Clock

Static Memory Controller (SMC)

Security Crypto Engine

SD/SDIO (MSI)

1

Yes

4-bit

No

8-bit

Yes

4-bit

No

8-bit

Yes

4-bit

No

8-bit

Yes

4-bit

No

8-bit

Yes

4-Channel 12-Bit ADC

¹Other speed grades available.

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BLACKFIN+ PROCESSOR CORE

As shown in Figure 1, the processor integrates a Blackfin+

processor core. The core, shown in Figure 2, contains two 16-bit

multipliers, one 32-bit multiplier, two 40-bit accumulators

(which may be used together as a 72-bit accumulator), two 

40-bit ALUs, one 72-bit ALU, four video ALUs, and a 40-bit

shifter. The computation units process 8-, 16-, or 32-bit data

from the register file.

The compute register file contains eight 32-bit registers. When

performing compute operations on 16-bit operand data, the

register file operates as 16 independent 16-bit registers. All

operands for compute operations come from the multiported

register file and instruction constant fields.

The ALUs perform a traditional set of arithmetic and logical

operations on 16-bit or 32-bit data. In addition, many special

instructions are included to accelerate various signal processing

tasks. These include bit operations such as field extract and pop-

ulation count, divide primitives, saturation and rounding, and

sign/exponent detection. The set of video instructions include

byte alignment and packing operations, 16-bit and 8-bit adds

with clipping, 8-bit average operations, and 8-bit subtract/abso-

lute value/accumulate (SAA) operations. Also provided are the

compare/select and vector search instructions.

For certain instructions, two 16-bit ALU operations can be per-

formed simultaneously on register pairs (a 16-bit high half and

16-bit low half of a compute register). If a second ALU is used,

quad 16-bit operations are possible.

The 40-bit shifter can perform shifts and rotates and is used to

support normalization, field extract, and field deposit

instructions.

The core can perform two 16-bit by 16-bit multiply-accumu-

lates or one 32-bit multiply-accumulate in each cycle. Signed

and unsigned formats, rounding, saturation, and complex mul-

tiplies are supported.

ADDRESS ARITHMETIC UNIT

SP

FP

P5

P4

P3

P2

P1

P0

I3

I2

I1

I0

L3

L2

L1

L0

B3

B2

B1

B0

M3

M2

M1

M0

DAG1

DAG0

DA1 32

DA0 32

32

PREG

32

RAB

SD 32

LD1

LD0

ASTAT

32

SEQUENCER

ALIGN

R7.H

R6.H

R5.H

R4.H

R3.H

R2.H

R1.H

R0.H

R7.L

R6.L

R5.L

R4.L

R3.L

R2.L

R1.L

R0.L

16

40

16

32

8

DECODE

BARREL

SHIFTER

LOOP BUFFER

40

72

CONTROL

UNIT

40

A0

32

A1

32

40

DATA ARITHMETIC UNIT

Figure 2. Blackfin+ Processor Core

Rev. A

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ADSP-BF700/701/702/703/704/705/706/707

The program sequencer controls the flow of instruction execu-

The assembly language, which takes advantage of the proces-

sor’s unique architecture, offers the following advantages:

• Seamlessly integrated DSP/MCU features are optimized for

both 8-bit and 16-bit operations.

• A multi-issue load/store modified-Harvard architecture,

which supports two 16-bit MAC or four 8-bit ALU + two

load/store + two pointer updates per cycle.

tion, including instruction alignment and decoding. For

program flow control, the sequencer supports PC relative and

indirect conditional jumps (with dynamic branch prediction),

and subroutine calls. Hardware supports zero-overhead loop-

ing. The architecture is fully interlocked, meaning that the

programmer need not manage the pipeline when executing

instructions with data dependencies.

• All registers, I/O, and memory are mapped into a unified

4G byte memory space, providing a simplified program-

ming model.

• Control of all asynchronous and synchronous events to the

processor is handled by two subsystems: the core event

controller (CEC) and the system event controller (SEC).

The address arithmetic unit provides two addresses for simulta-

neous dual fetches from memory. It contains a multiported

register file consisting of four sets of 32-bit index, modify,

length, and base registers (for circular buffering), and eight

additional 32-bit pointer registers (for C-style indexed stack

manipulation).

The Blackfin processor supports a modified Harvard architec-

ture in combination with a hierarchical memory structure. Level

1 (L1) memories are those that typically operate at the full pro-

cessor speed with little or no latency. At the L1 level, the

instruction memory holds instructions only. The data memory

holds data, and a dedicated scratchpad data memory stores

stack and local variable information.

In addition, multiple L1 memory blocks are provided, offering a

configurable mix of SRAM and cache. The memory manage-

ment unit (MMU) provides memory protection for individual

tasks that may be operating on the core and can protect system

registers from unintended access.

• Microcontroller features, such as arbitrary bit and bit-field

manipulation, insertion, and extraction; integer operations

on 8-, 16-, and 32-bit data-types; and separate user and

supervisor stack pointers.

• Code density enhancements, which include intermixing of

16-bit and 32-bit instructions (no mode switching, no code

segregation). Frequently used instructions are encoded

in 16 bits.

PROCESSOR INFRASTRUCTURE

The following sections provide information on the primary

infrastructure components of the ADSP-BF70x processor.

The architecture provides three modes of operation: user mode,

supervisor mode, and emulation mode. User mode has

restricted access to certain system resources, thus providing a

protected software environment, while supervisor mode has

unrestricted access to the system and core resources.

DMA Controllers

The processor uses direct memory access (DMA) to transfer

data within memory spaces or between a memory space and a

peripheral. The processor can specify data transfer operations

and return to normal processing while the fully integrated DMA

controller carries out the data transfers independent of proces-

sor activity.

DMA transfers can occur between memory and a peripheral or

between one memory and another memory. Each memory-to-

memory DMA stream uses two channels, where one channel is

the source channel, and the second is the destination channel.

All DMAs can transport data to and from all on-chip and off-

chip memories. Programs can use two types of DMA transfers,

descriptor-based or register-based. Register-based DMA allows

the processor to directly program DMA control registers to ini-

tiate a DMA transfer. On completion, the control registers may

be automatically updated with their original setup values for

continuous transfer. Descriptor-based DMA transfers require a

set of parameters stored within memory to initiate a DMA

sequence. Descriptor-based DMA transfers allow multiple

DMA sequences to be chained together and a DMA channel can

be programmed to automatically set up and start another DMA

transfer after the current sequence completes.

INSTRUCTION SET DESCRIPTION

The Blackfin processor instruction set has been optimized so

that 16-bit opcodes represent the most frequently used instruc-

tions, resulting in excellent compiled code density. Complex

DSP instructions are encoded into 32-bit opcodes, representing

fully featured multifunction instructions. The Blackfin proces-

sor supports a limited multi-issue capability, where a 32-bit

instruction can be issued in parallel with two 16-bit instruc-

tions, allowing the programmer to use many of the core

resources in a single instruction cycle.

The Blackfin processor family assembly language instruction set

employs an algebraic syntax designed for ease of coding and

readability. The instructions have been specifically tuned to pro-

vide a flexible, densely encoded instruction set that compiles to

a very small final memory size. The instruction set also provides

fully featured multifunction instructions that allow the pro-

grammer to use many of the processor core resources in a single

instruction. Coupled with many features more often seen on

microcontrollers, this instruction set is very efficient when com-

piling C and C++ source code. In addition, the architecture

supports both user (algorithm/application code) and supervisor

(O/S kernel, device drivers, debuggers, ISRs) modes of opera-

tion, allowing multiple levels of access to core processor

resources.

The DMA controller supports the following DMA operations.

• A single linear buffer that stops on completion.

• A linear buffer with negative, positive, or zero stride length.

• A circular, auto-refreshing buffer that interrupts when each

buffer becomes full.

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• A similar buffer that interrupts on fractional buffers (for

Trigger Routing Unit (TRU)

example, 1/2, 1/4).

The TRU provides system-level sequence control without core

intervention. The TRU maps trigger masters (generators of trig-

gers) to trigger slaves (receivers of triggers). Slave endpoints can

be configured to respond to triggers in various ways. Common

applications enabled by the TRU include:

• Automatically triggering the start of a DMA sequence after

a sequence from another DMA channel completes

• 1D DMA—uses a set of identical ping-pong buffers defined

by a linked ring of two-word descriptor sets, each contain-

ing a link pointer and an address.

• 1D DMA—uses a linked list of 4 word descriptor sets con-

taining a link pointer, an address, a length, and a

configuration.

• 2D DMA—uses an array of one-word descriptor sets, spec-

ifying only the base DMA address.

• 2D DMA—uses a linked list of multi-word descriptor sets,

specifying everything.

• Software triggering

• Synchronization of concurrent activities

General-Purpose I/O (GPIO)

Each general-purpose port pin can be individually controlled by

manipulation of the port control, status, and interrupt registers:

• GPIO direction control register—Specifies the direction of

each individual GPIO pin as input or output.

• GPIO control and status registers—A write one to modify

mechanism allows any combination of individual GPIO

pins to be modified in a single instruction, without affect-

ing the level of any other GPIO pins.

• GPIO interrupt mask registers—Allow each individual

GPIO pin to function as an interrupt to the processor.

GPIO pins defined as inputs can be configured to generate

hardware interrupts, while output pins can be triggered by

software interrupts.

Event Handling

The processor provides event handling that supports both nest-

ing and prioritization. Nesting allows multiple event service

routines to be active simultaneously. Prioritization ensures that

servicing of a higher-priority event takes precedence over ser-

vicing of a lower-priority event. The processor provides support

for five different types of events:

• Emulation—An emulation event causes the processor to

enter emulation mode, allowing command and control of

the processor through the JTAG interface.

• Reset—This event resets the processor.

• Nonmaskable interrupt (NMI)—The NMI event can be

generated either by the software watchdog timer, by the

NMI input signal to the processor, or by software. The

NMI event is frequently used as a power-down indicator to

initiate an orderly shutdown of the system.

• GPIO interrupt sensitivity registers—Specify whether indi-

vidual pins are level- or edge-sensitive and specify—if

edge-sensitive—whether just the rising edge or both the ris-

ing and falling edges of the signal are significant.

• Exceptions—Events that occur synchronously to program

flow (in other words, the exception is taken before the

instruction is allowed to complete). Conditions such as

data alignment violations and undefined instructions cause

exceptions.

• Interrupts —Events that occur asynchronously to program

flow. They are caused by input signals, timers, and other

peripherals, as well as by an explicit software instruction.

Pin Interrupts

Every port pin on the processor can request interrupts in either

an edge-sensitive or a level-sensitive manner with programma-

ble polarity. Interrupt functionality is decoupled from GPIO

operation. Three system-level interrupt channels (PINT0–3) are

reserved for this purpose. Each of these interrupt channels can

manage up to 32 interrupt pins. The assignment from pin to

interrupt is not performed on a pin-by-pin basis. Rather, groups

of eight pins (half ports) can be flexibly assigned to interrupt

channels.

Every pin interrupt channel features a special set of 32-bit mem-

ory-mapped registers that enable half-port assignment and

interrupt management. This includes masking, identification,

and clearing of requests. These registers also enable access to the

respective pin states and use of the interrupt latches, regardless

of whether the interrupt is masked or not. Most control registers

feature multiple MMR address entries to write-one-to-set or

write-one-to-clear them individually.

System Event Controller (SEC)

The SEC manages the enabling, prioritization, and routing of

events from each system interrupt or fault source. Additionally,

it provides notification and identification of the highest priority

active system interrupt request to the core and routes system

fault sources to its integrated fault management unit. The SEC

triggers core general-purpose interrupt IVG11. It is recom-

mended that IVG11 be set to allow self-nesting. The four lower

priority interrupts (IVG15-12) may be used for software

interrupts.

Pin Multiplexing

The processor supports a flexible multiplexing scheme that mul-

tiplexes the GPIO pins with various peripherals. A maximum of

4 peripherals plus GPIO functionality is shared by each GPIO

pin. All GPIO pins have a bypass path feature—that is, when the

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output enable and the input enable of a GPIO pin are both

active, the data signal before the pad driver is looped back to the

receive path for the same GPIO pin.

PROCESSOR MEMORY MAP

0x FFFF FFFF -

MEMORY ARCHITECTURE

The processor views memory as a single unified 4G byte address

space, using 32-bit addresses. All resources, including internal

memory, external memory, and I/O control registers, occupy

separate sections of this common address space. The memory

portions of this address space are arranged in a hierarchical

structure to provide a good cost/performance balance of some

very fast, low-latency core-accessible memory as cache or

SRAM, and larger, lower-cost and performance interface-acces-

sible memory systems. See Figure 3.

Reserved

0x 9000 0000 -

0x 8000 0000 -

DDR2 or LPDDR Memory (256 MB)

Reserved

0x 7400 2000 -

0x 7400 0000 -

Static Memory Block 1 (8 KB)

Reserved

0x 7000 2000 -

0x 7000 0000 -

Internal (Core-Accessible) Memory

Static Memory Block 0 (8 KB)

The L1 memory system is the highest-performance memory

available to the Blackfin+ processor core.

Reserved

The core has its own private L1 memory. The modified Harvard

architecture supports two concurrent 32-bit data accesses along

with an instruction fetch at full processor speed which provides

high-bandwidth processor performance. In the core, a 64K byte

block of data memory partners with an 64K byte memory block

for instruction storage. Each data block is multibanked for effi-

cient data exchange through DMA and can be configured as

SRAM. Alternatively, 16K bytes of each block can be configured

in L1 cache mode. The four-way set-associative instruction

cache and the 2 two-way set-associative data caches greatly

accelerate memory access performance, especially when access-

ing external memories.

0x 4800 0000 -

0x 4000 0000 -

SPI2 Memory (128 MB)

Reserved

0x 3800 1000 -

0x 3800 0000 -

OTP Memory (4 KB)

Reserved

0x 2030 1000 -

0x 2030 0000 -

0x 2000 0000 -

0x 1FC0 0000 -

STM Memory (4 KB)

System MMR Registers (3 MB)

Core MMR Registers (4 MB)

Reserved

The L1 memory domain also features a 8K byte data SRAM

block which is ideal for storing local variables and the software

stack. All L1 memory is protected by a multi-parity-bit concept,

regardless of whether the memory is operating in SRAM or

cache mode.

0x 11B0 2000 -

0x 11B0 0000 -

L1 Data Block C (8 KB)

Reserved

0x 11A1 0000 -

0x 11A0 C000 -

0x 11A0 0000 -

L1 Instruction SRAM/Cache (16 KB)

L1 Instruction SRAM (48 KB)

Reserved

Outside of the L1 domain, L2 and L3 memories are arranged

using a Von Neumann topology. The L2 memory domain is a

unified instruction and data memory and can hold any mixture

of code and data required by the system design. The L2 memory

domain is accessible by the Blackfin+ core through a dedicated

64-bit interface. It operates at SYSCLK frequency.

The processor features up to 1M byte of L2 SRAM, which is

ECC-protected and organized in eight banks. Individual banks

can be made private to any system master. There is also a

512K byte single-bank ROM in the L2 domain. It contains boot

code, security code, and general-purpose ROM space.

0x 1190 8000 -

0x 1190 4000 -

0x 1190 0000 -

0x 1180 8000 -

0x 1180 4000 -

0x 1180 0000 -

L1 Data Block B SRAM/Cache (16 KB)

L1 Data Block B SRAM (16 KB)

Reserved

L1 Data Block A SRAM/Cache (16 KB)

L1 Data Block A SRAM (16 KB)

Reserved

0x 0810 0000 -

0x 0800 0000 -

L2 SRAM (1024 KB)

Reserved

0x 0408 0000 -

0x 0401 0000 -

L2 ROM (448 KB)

Boot ROM (64 KB)

Reserved

OTP Memory

0x 0400 0000 -

0x 0000 0000 -

The processor features 4 kB of one-time-programmable (OTP)

memory which is memory-map accessible. This memory stores

a unique chip identification and is used to support secure-boot

and secure operation.

Figure 3. ADSP-BF706/ADSP-BF707 Internal/External Memory Map

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The following hardware-accelerated cryptographic ciphers are

Static Memory Controller (SMC)

supported:

The SMC can be programmed to control up to two blocks of

external memories or memory-mapped devices, with very flexi-

ble timing parameters. Each block occupies a 8K byte segment

regardless of the size of the device used.

• AES in ECB, CBC, ICM, and CTR modes with 128-, 192-,

and 256-bit keys

• DES in ECB and CBC mode with 56-bit key

• 3DES in ECB and CBC mode with 3x 56-bit key

Dynamic Memory Controller (DMC)

The following hardware-accelerated hash functions are

supported:

• SHA-1

• SHA-2 with 224-bit and 256-bit digest

• HMAC transforms for SHA-1 and SHA-2

Public key accelerator is available to offload computation-inten-

sive public key cryptography operations.

Both a hardware-based nondeterministic random number gen-

erator and pseudo-random number generator are available. The

TRNG also provides HW post-processing to meet NIST

requirements of FIPS 140-2, while the PRNG is ANSI X9.31

compliant.

Secure boot is also available with 224-bit elliptic curve digital

signatures ensuring integrity and authenticity of the boot

stream. Optionally, confidentiality is also ensured through AES-

128 encryption.

The DMC includes a controller that supports JESD79-2E com-

patible double-data-rate (DDR2) SDRAM and JESD209A low-

power DDR (LPDDR) SDRAM devices. The DMC PHY fea-

tures on-die termination on all data and data strobe pins that

can be used during reads.

I/O Memory Space

The processor does not define a separate I/O space. All

resources are mapped through the flat 32-bit address space. On-

chip I/O devices have their control registers mapped into mem-

ory-mapped registers (MMRs) at addresses in a region of the

4G byte address space. These are separated into two smaller

blocks, one which contains the control MMRs for all core func-

tions, and the other which contains the registers needed for

setup and control of the on-chip peripherals outside of the core.

The MMRs are accessible only in supervisor mode and appear

as reserved space to on-chip peripherals.

Booting

The processor has several mechanisms for automatically loading

internal and external memory after a reset. The boot mode is

defined by the SYS_BMODE input pins dedicated for this pur-

pose. There are two categories of boot modes. In master boot

mode, the processor actively loads data from serial memories. In

slave boot modes, the processor receives data from external host

devices.

The boot modes are shown in Table 2. These modes are imple-

mented by the SYS_BMODE bits of the reset configuration

register and are sampled during power-on resets and software-

initiated resets.

CAUTION

This product includes security features that can be

used to protect embedded nonvolatile memory

contents and prevent execution of unauthorized

code. When security is enabled on this device

(either by the ordering party or the subsequent

receiving parties), the ability of Analog Devices to

conduct failure analysis on returned devices is

limited. Contact Analog Devices for details on the

failure analysis limitations for this device.

Secure debug is also employed to allow only trusted users to

access the system with debug tools.

Table 2. Boot Modes

PROCESSOR SAFETY FEATURES

SYS_BMODE Setting

Boot Mode

No Boot/Idle

SPI2 Master

SPI2 Slave

The ADSP-BF70x processor has been designed for functional

safety applications. While the level of safety is mainly domi-

nated by the system concept, the following primitives are

provided by the devices to build a robust safety concept.

00

01

10

11

UART0 Slave

Multi-Parity-Bit-Protected L1 Memories

In the processor’s L1 memory space, whether SRAM or cache,

each word is protected by multiple parity bits to detect the single

event upsets that occur in all RAMs. This applies both to L1

instruction and data memory spaces.

SECURITY FEATURES

The ADSP-BF70x processor supports standards-based hard-

ware-accelerated encryption, decryption, authentication, and

true random number generation.

ECC-Protected L2 Memories

Error correcting codes (ECC) are used to correct single event

upsets. The L2 memory is protected with a single error correct-

double error detect (SEC-DED) code. By default ECC is

enabled, but it can be disabled on a per-bank basis. Single-bit

errors are transparently corrected. Dual-bit errors can issue a

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system event or fault if enabled. ECC protection is fully trans-

parent to the user, even if L2 memory is read or written by 8-bit

or 16-bit entities.

Watchdog

The on-chip software watchdog timer can supervise the

Blackfin+ core.

CRC-Protected Memories

Bandwidth Monitor

While parity bit and ECC protection mainly protect against ran-

dom soft errors in L1 and L2 memory cells, the CRC engines can

be used to protect against systematic errors (pointer errors) and

static content (instruction code) of L1, L2, and even L3 memo-

ries (DDR2, LPDDR). The processor features two CRC engines

which are embedded in the memory-to-memory DMA

Memory-to-memory DMA channels are equipped with a band-

width monitor mechanism. They can signal a system event or

fault when transactions tend to starve because system buses are

fully loaded with higher-priority traffic.

Signal Watchdogs

controllers. CRC checksums can be calculated or compared on

the fly during memory transfers, or one or multiple memory

regions can be continuously scrubbed by a single DMA work

unit as per DMA descriptor chain instructions. The CRC engine

also protects data loaded during the boot process.

The eight general-purpose timers feature modes to monitor off-

chip signals. The watchdog period mode monitors whether

external signals toggle with a period within an expected range.

The watchdog width mode monitors whether the pulse widths

of external signals are within an expected range. Both modes

help to detect undesired toggling (or lack thereof) of 

system-level signals.

Memory Protection

The Blackfin+ core features a memory protection concept,

which grants data and/or instruction accesses to enabled mem-

ory regions only. A supervisor mode vs. user mode

programming model supports dynamically varying access

rights. Increased flexibility in memory page size options sup-

ports a simple method of static memory partitioning.

Up/Down Count Mismatch Detection

The GP counter can monitor external signal pairs, such as

request/grant strobes. If the edge count mismatch exceeds the

expected range, the GP counter can flag this to the processor or

to the fault management unit of the SEC.

System Protection

Fault Management

The system protection unit (SPU) guards against accidental or

unwanted access to the MMR space of a peripheral by providing

a write-protection mechanism. The user is able to choose and

configure the peripherals that are protected as well as configure

which ones of the four system MMR masters (core, memory

DMA, the SPI host port, and Coresight debug) the peripherals

are guarded against.

The SPU is also part of the security infrastructure. Along with

providing write-protection functionality, the SPU is employed

to define which resources in the system are secure or non-secure

and to block access to secure resources from non-secure

masters.

The fault management unit is part of the system event controller

(SEC). Any system event, whether a dual-bit uncorrectable ECC

error, or any peripheral status interrupt, can be defined as being

a fault. Additionally, the system events can be defined as an

interrupt to the core. If defined as such, the SEC forwards the

event to the fault management unit, which may automatically

reset the entire device for reboot, or simply toggle the 

SYS_FAULT output pin to signal off-chip hardware. Optionally,

the fault management unit can delay the action taken through a

keyed sequence, to provide a final chance for the Blackfin+ core

to resolve the issue and to prevent the fault action from being

taken.

Synonymously, the system memory protection unit (SMPU)

provides memory protection against read and/or write transac-

tions to defined regions of memory. There are two SMPU units

in the ADSP-BF70x processors. One is for the L2 memory and

the other is for the external DDR memory.

The SMPU is also part of the security infrastructure. It allows

the user to not only protect against arbitrary read and/or write

transactions, but it also allows regions of memory to be defined

as secure and prevent non-secure masters from accessing those

memory regions.

ADDITIONAL PROCESSOR PERIPHERALS

The processor contains a rich set of peripherals connected to the

core through several high-bandwidth buses, providing flexibility

in system configuration as well as excellent overall system per-

formance (see the block diagram on Page 1). The processor

contains high-speed serial and parallel ports, an interrupt con-

troller for flexible management of interrupts from the on-chip

peripherals or external sources, and power management control

functions to tailor the performance and power characteristics of

the processor and system to many application scenarios.

Watchpoint Protection

The following sections describe additional peripherals that were

not previously described.

The primary purpose of watchpoints and hardware breakpoints

is to serve emulator needs. When enabled, they signal an emula-

tor event whenever user-defined system resources are accessed

or the core executes from user-defined addresses. Watchpoint

events can be configured such that they signal the events to the

fault management unit of the SEC.

Timers

The processor includes several timers which are described in the

following sections.

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General-Purpose Timers

configuration, one SPORT provides two transmit signals while

the other SPORT provides the two receive signals. The frame

sync and clock are shared.

There is one GP timer unit, and it provides eight general-pur-

pose programmable timers. Each timer has an external pin that

can be configured either as a pulse width modulator (PWM) or

timer output, as an input to clock the timer, or as a mechanism

for measuring pulse widths and periods of external events.

These timers can be synchronized to an external clock input on

the TIMER_TMRx pins, an external TIMER_CLK input pin, or

to the internal SCLK0.

These timer units can be used in conjunction with the UARTs

and the CAN controller to measure the width of the pulses in

the data stream to provide a software auto-baud detect function

for the respective serial channels.

Serial ports operate in six modes:

• Standard DSP serial mode

• Multichannel (TDM) mode

• I²S mode

• Packed I²S mode

• Left-justified mode

• Right-justified mode

General-Purpose Counters

The GP timers can generate interrupts to the processor core,

providing periodic events for synchronization to either the sys-

tem clock or to external signals. Timer events can also trigger

other peripherals through the TRU (for instance, to signal a

fault). Each timer may also be started and/or stopped by any

TRU master without core intervention.

A 32-bit counter is provided that can operate in general-pur-

pose up/down count modes and can sense 2-bit quadrature or

binary codes as typically emitted by industrial drives or manual

thumbwheels. Count direction is either controlled by a level-

sensitive input pin or by two edge detectors.

A third counter input can provide flexible zero marker support

and can alternatively be used to input the push-button signal of

thumbwheel devices. All three pins have a programmable

debouncing circuit.

Internal signals forwarded to a GP timer enable this timer to

measure the intervals between count events. Boundary registers

enable auto-zero operation or simple system warning by inter-

rupts when programmed count values are exceeded.

Core Timer

The processor core also has its own dedicated timer. This extra

timer is clocked by the internal processor clock and is typically

used as a system tick clock for generating periodic operating

system interrupts.

Watchdog Timer

The core includes a 32-bit timer, which may be used to imple-

ment a software watchdog function. A software watchdog can

improve system availability by forcing the processor to a known

state, through generation of a hardware reset, nonmaskable

interrupt (NMI), or general-purpose interrupt, if the timer

expires before being reset by software. The programmer initial-

izes the count value of the timer, enables the appropriate

interrupt, then enables the timer. Thereafter, the software must

reload the counter before it counts down to zero from the pro-

grammed value. This protects the system from remaining in an

unknown state where software that would normally reset the

timer has stopped running due to an external noise condition or

software error.

Parallel Peripheral Interface (PPI)

The processor provides a parallel peripheral interface (PPI) that

supports data widths up to 18 bits. The PPI supports direct con-

nection to TFT LCD panels, parallel analog-to-digital and

digital-to-analog converters, video encoders and decoders,

image sensor modules, and other general-purpose peripherals.

The following features are supported in the PPI module:

• Programmable data length: 8 bits, 10 bits, 12 bits, 14 bits,

16 bits, and 18 bits per clock.

• Various framed, non-framed, and general-purpose operat-

ing modes. Frame syncs can be generated internally or can

be supplied by an external device.

• ITU-656 status word error detection and correction for

ITU-656 receive modes and ITU-656 preamble and status

word decode.

After a reset, software can determine if the watchdog was the

source of the hardware reset by interrogating a status bit in its

timer control register that is set only upon a watchdog-gener-

ated reset.

Serial Ports (SPORTs)

• Optional packing and unpacking of data to/from 32 bits

from/to 8 bits, 16 bits and 24 bits. If packing/unpacking is

enabled, endianness can be configured to change the order

of packing/unpacking of bytes/words.

• RGB888 can be converted to RGB666 or RGB565 for trans-

mit modes.

• Various de-interleaving/interleaving modes for receiv-

ing/transmitting 4:2:2 YCrCb data.

• Configurable LCD data enable (DEN) output available on

Frame Sync 3.

Two synchronous serial ports (comprised of four half-SPORTs)

provide an inexpensive interface to a wide variety of digital and

mixed-signal peripheral devices such as Analog Devices’ audio

codecs, ADCs, and DACs. Each half-SPORT is made up of two

data lines, a clock, and frame sync. The data lines can be pro-

grammed to either transmit or receive and each data line has a

dedicated DMA channel.

Serial port data can be automatically transferred to and from

on-chip memory/external memory through dedicated DMA

channels. Each of the serial ports can work in conjunction with

another serial port to provide TDM support. In this

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The UART ports support automatic hardware flow control

through the clear to send (CTS) input and request to send (RTS)

Serial Peripheral Interface (SPI) Ports

The processors have three industry-standard SPI-compatible

ports that allow it to communicate with multiple SPI-compati-

ble devices.

output with programmable assertion FIFO levels.

To help support the local interconnect network (LIN) protocols,

a special command causes the transmitter to queue a break

command of programmable bit length into the transmit buffer.

Similarly, the number of stop bits can be extended by a pro-

grammable inter-frame space.

The baseline SPI peripheral is a synchronous, four-wire inter-

face consisting of two data pins, one device select pin, and a

gated clock pin. The two data pins allow full-duplex operation

to other SPI-compatible devices. An additional two (optional)

data pins are provided to support quad SPI operation. Enhanced

modes of operation such as flow control, fast mode, and dual

I/O mode (DIOM) are also supported. In addition, a direct

memory access (DMA) mode allows for transferring several

words with minimal CPU interaction.

The capabilities of the UARTs are further extended with sup-

port for the Infrared Data Association (IrDA®) serial infrared

physical layer link specification (SIR) protocol.

2-Wire Controller Interface (TWI)

The processor includes a 2-wire interface (TWI) module for

providing a simple exchange method of control data between

multiple devices. The TWI module is compatible with the

widely used I²C bus standard. The TWI module offers the

capabilities of simultaneous master and slave operation and

support for both 7-bit addressing and multimedia data arbitra-

tion. The TWI interface utilizes two pins for transferring clock

(TWI_SCL) and data (TWI_SDA) and supports the protocol at

speeds up to 400k bits/sec. The TWI interface pins are compati-

ble with 5 V logic levels.

With a range of configurable options, the SPI ports provide a

glueless hardware interface with other SPI-compatible devices

in master mode, slave mode, and multimaster environments.

The SPI peripheral includes programmable baud rates, clock

phase, and clock polarity. The peripheral can operate in a multi-

master environment by interfacing with several other devices,

acting as either a master device or a slave device. In a multimas-

ter environment, the SPI peripheral uses open-drain outputs to

avoid data bus contention. The flow control features enable slow

slave devices to interface with fast master devices by providing

an SPI Ready pin which flexibly controls the transfers.

Additionally, the TWI module is fully compatible with serial

camera control bus (SCCB) functionality for easier control of

various CMOS camera sensor devices.

The SPI port’s baud rate and clock phase/polarities are pro-

grammable, and it has integrated DMA channels for both

transmit and receive data streams.

Mobile Storage Interface (MSI)

SPI Host Port (SPIHP)

The mobile storage interface (MSI) controller acts as the host

interface for multimedia cards (MMC), secure digital memory

cards (SD), and secure digital input/output cards (SDIO). The

following list describes the main features of the MSI controller:

• Support for a single MMC, SD memory, and SDIO card

• Support for 1-bit and 4-bit SD modes

• Support for 1-bit, 4-bit, and 8-bit MMC modes

• Support for eMMC 4.5 embedded NAND flash devices

• Support for power management and clock control

The processor includes one SPI host port which may be used in

conjunction with any available SPI port to enhance its SPI slave

mode capabilities. The SPIHP allows a SPI host device access to

memory-mapped resources of the processor through a SPI

SRAM/FLASH style protocol. The following features are

included:

• Direct read/write of memory and memory-mapped

registers

• Support for pre-fetch for faster reads

• An eleven-signal external interface with clock, command,

optional interrupt, and up to eight data lines

• Support for SPI controllers that implement hardware-

based SPI memory protocol

• Card interface clock generation from SCLK0 or SCLK1

• SDIO interrupt and read wait features

• Error capture and reporting for protocol errors, bus errors,

and over/underflow

UART Ports

Controller Area Network (CAN)

The processor provides two full-duplex universal asynchronous

receiver/transmitter (UART) ports, which are fully compatible

with PC-standard UARTs. Each UART port provides a simpli-

fied UART interface to other peripherals or hosts, supporting

full-duplex, DMA-supported, asynchronous transfers of serial

data. A UART port includes support for five to eight data bits,

and none, even, or odd parity. Optionally, an additional address

bit can be transferred to interrupt only addressed nodes in

multi-drop bus (MDB) systems. A frame is terminated by a con-

figurable number of stop bits.

A CAN controller implements the CAN 2.0B (active) protocol.

This protocol is an asynchronous communications protocol

used in both industrial and automotive control systems. The

CAN protocol is well suited for control applications due to its

capability to communicate reliably over a network. This is

because the protocol incorporates CRC checking, message error

tracking, and fault node confinement.

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The CAN controller offers the following features:

• 32 mailboxes (8 receive only, 8 transmit only, 16 configu-

rable for receive or transmit)

• Dedicated acceptance masks for each mailbox

• Additional data filtering on first two bytes

• Support for both the standard (11-bit) and extended

(29-bit) identifier (ID) message formats

• Support for remote frames

• Active or passive network support

• CAN wake-up from hibernation mode (lowest static power

consumption mode)

• Interrupts, including: TX complete, RX complete, error

and global

An additional crystal is not required to supply the CAN clock, as

the CAN clock is derived from a system clock through a pro-

grammable divider.

• Auto sequencing capability with up to 4 autoconversions in

a single session. Each conversion can be programmed to

select any input channel.

• Four data registers (individually addressable) to store con-

version values

System Crossbars (SCB)

The system crossbars (SCB) are the fundamental building

blocks of a switch-fabric style for (on-chip) system bus inter-

connection. The SCBs connect system bus masters to system

bus slaves, providing concurrent data transfer between multiple

bus masters and multiple bus slaves. A hierarchical model—

built from multiple SCBs—provides a power and area efficient

system interconnect, which satisfies the performance and flexi-

bility requirements of a specific system.

The SCBs provide the following features:

• Highly efficient, pipelined bus transfer protocol for sus-

tained throughput

• Full-duplex bus operation for flexibility and reduced

latency

USB 2.0 On-the-Go Dual-Role Device Controller

The USB 2.0 on-the-go (OTG) dual-role device controller pro-

vides a low-cost connectivity solution for the growing adoption

of this bus standard in industrial applications, as well as con-

sumer mobile devices such as cell phones, digital still cameras,

and MP3 players. The USB 2.0 controller allows these devices to

transfer data using a point-to-point USB connection without

the need for a PC host. The module can operate in a traditional

USB peripheral-only mode as well as the host mode presented

in the OTG supplement to the USB 2.0 specification.

The USB clock is provided through a dedicated external crystal

or crystal oscillator.

The USB OTG dual-role device controller includes a phase

locked loop with programmable multipliers to generate the nec-

essary internal clocking frequency for USB.

• Concurrent bus transfer support to allow multiple bus

masters to access bus slaves simultaneously

• Protection model (privileged/secure) support for selective

bus interconnect protection

POWER AND CLOCK MANAGEMENT

The processor provides three operating modes, each with a dif-

ferent performance/power profile. Control of clocking to each

of the processor peripherals also reduces power consumption.

See Table 5 for a summary of the power settings for each mode.

System Crystal Oscillator and USB Crystal Oscillator

The processor can be clocked by an external crystal (see

Figure 4), a sine wave input, or a buffered, shaped clock derived

from an external clock oscillator. If an external clock is used, it

should be a TTL compatible signal and must not be halted,

changed, or operated below the specified frequency during nor-

mal operation. This signal is connected to the SYS_CLKIN pin

of the processor. When an external clock is used, the SYS_XTAL

pin must be left unconnected. Alternatively, because the proces-

sor includes an on-chip oscillator circuit, an external crystal

may be used.

For fundamental frequency operation, use the circuit shown in

Figure 4. A parallel-resonant, fundamental frequency, micro-

processor grade crystal is connected across the SYS_CLKIN and

SYS_XTAL pins. The on-chip resistance between SYS_CLKIN

and the SYS_XTAL pin is in the 500 kΩ range. Further parallel

resistors are typically not recommended.

Housekeeping ADC (HADC)

The HADC provides a general-purpose, multichannel succes-

sive approximation analog-to-digital converter. It supports the

following features:

• 12-bit ADC core (10-bit accuracy) with built-in sample and

hold

• 4 single-ended input channels

• Throughput rates up to 1 MSPS

• Single external reference with analog inputs between 0 V

and 3.3 V

• Selectable ADC clock frequency including the ability to

program a prescaler

The two capacitors and the series resistor shown in Figure 4

fine-tune phase and amplitude of the sine frequency. The capac-

itor and resistor values shown in Figure 4 are typical values

only. The capacitor values are dependent upon the load capaci-

tance recommendations of the crystal manufacturer and the

PCB physical layout. The resistor value depends on the drive

• Adaptable conversion type: allows single or continuous

conversion with option of autoscan

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level specified by the crystal manufacturer. The user should ver-

ify the customized values based on careful investigations on

multiple devices over the required temperature range.

RTC_CLKIN

RTC_XTAL

R1

ꢁ0ȍ

X1

BLACKFIN

TO PLL

CIRCUITRY

NOTE: CRYSTAL LOAD CAPACITORS

ARE NOT NECESSARY IN MOST CASES.

ꢀꢁꢂȍ

Figure 5. External Components for RTC

SYS_CLKIN

18 pF*

SYS_XTAL

The stopwatch function counts down from a programmed

value, with one-second resolution. When the stopwatch inter-

rupt is enabled and the counter underflows, an interrupt is

generated.

ꢀꢂꢂȍ*

FOR OVERTONE

OPERATION ONLY:

18 pF*

Clock Generation

NOTE: VALUES MARKED WITH * MUST BE CUSTOMIZED, DEPENDING

ON THE CRYSTAL AND LAYOUT. ANALYZE CAREFULLY. FOR

FREQUENCIES ABOVE 33 MHz, THE SUGGESTED CAPACITOR VALUE

OF 18pF SHOULD BE TREATED AS A MAXIMUM.

The clock generation unit (CGU) generates all on-chip clocks

and synchronization signals. Multiplication factors are pro-

grammed to define the PLLCLK frequency. Programmable

values divide the PLLCLK frequency to generate the core clock

(CCLK), the system clocks (SYSCLK, SCLK0, and SCLK1), the

LPDDR or DDR2 clock (DCLK), and the output clock (OCLK).

Writing to the CGU control registers does not affect the behav-

ior of the PLL immediately. Registers are first programmed with

a new value, and the PLL logic executes the changes so that it

transitions smoothly from the current conditions to the new

ones.

Figure 4. External Crystal Connection

A third-overtone crystal can be used for frequencies above 

25 MHz. The circuit is then modified to ensure crystal operation

only at the third overtone by adding a tuned inductor circuit as

shown in Figure 4. A design procedure for third-overtone oper-

ation is discussed in detail in application note (EE-168) Using

Third Overtone Crystals with the ADSP-218x DSP (www.ana-

log.com/ee-168).

SYS_CLKIN oscillations start when power is applied to the

VDD_EXT pins. The rising edge of SYS_HWRST can be

applied after all voltage supplies are within specifications, and

SYS_CLKIN oscillations are stable.

The same recommendations may be used for the USB crystal

oscillator.

Real-Time Clock

The real-time clock (RTC) provides a robust set of digital watch

features, including current time, stopwatch, and alarm. The

RTC is clocked by a 32.768 kHz crystal external to the processor.

Connect RTC pins RTC_CLKIN and RTC_XTAL with external

components as shown in Figure 5.

The RTC peripheral has dedicated power supply pins so that it

can remain powered up and clocked even when the rest of the

processor is in a low power state. The RTC provides several pro-

grammable interrupt options, including interrupt per second,

minute, hour, or day clock ticks, interrupt on programmable

stopwatch countdown, or interrupt at a programmed alarm

time.

Clock Out/External Clock

The SYS_CLKOUT output pin has programmable options to

output divided-down versions of the on-chip clocks. By default,

the SYS_CLKOUT pin drives a buffered version of the SYS_

CLKIN input. Clock generation faults (for example, PLL

unlock) may trigger a reset by hardware. The clocks shown in

Table 3 can be output on the SYS_CLKOUT pin.

The 32.768 kHz input clock frequency is divided down to a 1 Hz

signal by a prescaler. The counter function of the timer consists

of four counters: a 60-second counter, a 60-minute counter, a

24-hour counter, and a 32,768-day counter. When the alarm

interrupt is enabled, the alarm function generates an interrupt

when the output of the timer matches the programmed value in

the alarm control register. There are two alarms. The first alarm

is for a time of day. The second alarm is for a specific day and

time of that day.

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Table 3. Clock Dividers

Deep Sleep Operating Mode—Maximum Dynamic Power

Savings

Divider (if Available on 

SYS_CLKOUT)

By 16

By 8

The deep sleep mode maximizes dynamic power savings by dis-

abling the clocks to the processor core and to all synchronous

peripherals. Asynchronous peripherals may still be running but

cannot access internal resources or external memory.

Clock Source

CCLK (Core Clock)

SYSCLK (System Clock)

SCLK0 (System Clock, All Periph- Not available on SYS_CLKOUT

erals not Covered by SCLK1)

Table 5. Power Settings

SCLK1 (System Clock for Crypto By 8

Engines and MDMA)

f_SYSCLK,

f_DCLK,

f_SCLK0,

DCLK (LPDDR/DDR2 Clock)

OCLK (Output Clock)

CLKBUF

By 8

PLL

Bypassed f_CCLK

Enabled No

Core

Power

On

Programmable

None, direct from SYS_CLKIN

Mode/State PLL

Full On

f_SCLK1

Enabled Enabled

Deep Sleep Disabled —

Disabled Disabled On

Disabled Disabled Off

Power Management

Hibernate

Disabled —

As shown in Table 4, the processor supports multiple power

domains, which maximizes flexibility while maintaining com-

pliance with industry standards and conventions. There are no

sequencing requirements for the various power domains, but all

domains must be powered according to the appropriate Specifi-

cations table for processor operating conditions; even if the

feature/peripheral is not used.

Hibernate State—Maximum Static Power Savings

The hibernate state maximizes static power savings by disabling

the voltage and clocks to the processor core and to all of the

peripherals. This setting signals the external voltage regulator

supplying the VDD_INT pins to shut off using the SYS_

EXTWAKE signal, which provides the lowest static power

dissipation.

Any critical information stored internally (for example, mem-

ory contents, register contents, and other information) must be

written to a nonvolatile storage device (or self-refreshed

DRAM) prior to removing power if the processor state is to be

preserved.

Table 4. Power Domains

Power Domain

All Internal Logic

DDR2/LPDDR

USB

V_DDRange

V_{DD_INT}

V_{DD_DMC}

V_{DD_USB}

Because the V_{DD_EXT}pins can still be supplied in this mode, all of

the external pins three-state, unless otherwise specified. This

allows other devices that may be connected to the processor to

still have power applied without drawing unwanted current.

OTP Memory

HADC

V_{DD_OTP}

V_{DD_HADC}

V_{DD_RTC}

RTC

All Other I/O (Includes SYS, JTAG, and Ports Pins) V_{DD_EXT}

Reset Control Unit

The dynamic power management feature of the processor

allows the processor’s core clock frequency (f_CCLK) to be dynam-

ically controlled.

The power dissipated by a processor is largely a function of its

clock frequency and the square of the operating voltage. For

example, reducing the clock frequency by 25% results in a 25%

reduction in dynamic power dissipation.

Reset is the initial state of the whole processor or the core and is

the result of a hardware- or software-triggered event. In this

state, all control registers are set to their default values and func-

tional units are idle. Exiting a full system reset starts with the

core being ready to boot.

The reset control unit (RCU) controls how all the functional

units enter and exit reset. Differences in functional require-

ments and clocking constraints define how reset signals are

generated. Programs must guarantee that none of the reset

functions puts the system into an undefined state or causes

resources to stall. This is particularly important when the core is

reset (programs must ensure that there is no pending system

activity involving the core when it is being reset).

See Table 5 for a summary of the power settings for each mode.

Full-On Operating Mode—Maximum Performance

In the full-on mode, the PLL is enabled and is not bypassed,

providing capability for maximum operational frequency. This

is the power-up default execution state in which maximum per-

formance can be achieved. The processor core and all enabled

peripherals run at full speed.

From a system perspective, reset is defined by both the reset tar-

get and the reset source described as follows in the following list.

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Target defined:

JTAG. The DAP provides an optional instrumentation trace for

both the core and system. It provides a trace stream that con-

• Hardware Reset—All functional units are set to their

default states without exception. History is lost.

forms to MIPI System Trace Protocol version 2 (STPv2).

• System Reset—All functional units except the RCU are set

to their default states.

• Core-only Reset—Affects the core only. The system soft-

ware should guarantee that the core, while in reset state, is

not accessed by any bus master.

DEVELOPMENT TOOLS

Analog Devices supports its processors with a complete line of

software and hardware development tools, including integrated

development environments (CrossCore^®Embedded Studio),

evaluation products, emulators, and a wide variety of software

add-ins.

Source defined:

• Hardware Reset—The SYS_HWRST input signal is

asserted active (pulled down).

Integrated Development Environments (IDEs)

TM

CrossCore Embedded Studio is based on the Eclipse frame-

• System Reset—May be triggered by software (writing to the

RCU_CTL register) or by another functional unit such as

the dynamic power management (DPM) unit (hibernate)

or any of the system event controller (SEC), trigger routing

unit (TRU), or emulator inputs.

• Core-only Reset—Triggered by software.

• Trigger request (peripheral).

work. Supporting most Analog Devices processor families, it is

the IDE of choice for future processors, including multicore

devices. CrossCore Embedded Studio seamlessly integrates

available software add-ins to support real time operating sys-

tems, file systems, TCP/IP stacks, USB stacks, algorithmic

software modules, and evaluation hardware board support

packages. For more information, visit www.analog.com/cces.

EZ-KIT Lite Evaluation Board

Voltage Regulation

For processor evaluation, Analog Devices provides a wide range

of EZ-KIT Lite^®evaluation boards. Including the processor and

key peripherals, the evaluation board also supports on-chip

emulation capabilities and other evaluation and development

features. Also available are various EZ-Extenders^®, which are

daughter cards delivering additional specialized functionality,

including audio and video processing. For more information,

visit www.analog.com and search on “ezkit” or “ezextender”.

The processor requires an external voltage regulator to power

the VDD_INT pins. To reduce standby power consumption, the

external voltage regulator can be signaled through 

SYS_EXTWAKE to remove power from the processor core.

This signal is high-true for power-up and may be connected

directly to the low-true shut-down input of many common

regulators.

While in the hibernate state, all external supply pins (VDD_

EXT, VDD_USB, and VDD_DMC) can still be powered, elimi-

nating the need for external buffers. The external voltage

regulator can be activated from this power down state by assert-

ing the SYS_HWRST pin, which then initiates a boot sequence.

SYS_EXTWAKE indicates a wake-up to the external voltage

regulator.

EZ-KIT Lite Evaluation Kits

For a cost-effective way to learn more about developing with

Analog Devices processors, Analog Devices offer a range of EZ-

KIT Lite evaluation kits. Each evaluation kit includes an EZ-KIT

Lite evaluation board, directions for downloading an evaluation

version of the available IDE, a USB cable, and a power supply.

The USB controller on the EZ-KIT Lite board connects to the

USB port of the user’s PC, enabling the chosen IDE evaluation

suite to emulate the on-board processor in-circuit. This permits

the customer to download, execute, and debug programs for the

EZ-KIT Lite system. It also supports in-circuit programming of

the on-board Flash device to store user-specific boot code,

enabling standalone operation. With the full version of Cross-

Core Embedded Studio installed (sold separately), engineers can

develop software for supported EZ-KITs or any custom system

utilizing supported Analog Devices processors.

SYSTEM DEBUG

The processor includes various features that allow for easy sys-

tem debug. These are described in the following sections.

System Watchpoint Unit

The system watchpoint unit (SWU) is a single module which

connects to a single system bus and provides for transaction

monitoring. One SWU is attached to the bus going to each

system slave. The SWU provides ports for all system bus address

channel signals. Each SWU contains four match groups of regis-

ters with associated hardware. These four SWU match groups

operate independently, but share common event (interrupt,

trigger, and others) outputs.

ADSP-BF706 EZ-KIT Mini

TM

The ADSP-BF706 EZ-KIT Mini product (ADZS-BF706-

EZMini) contains the ADSP-BF706 processor and is shipped

with all of the necessary hardware. Users can start their evalua-

tion immediately. The EZ-KIT Mini product includes the

standalone evaluation board and USB cable. The EZ-KIT Mini

ships with an on-board debug agent.

Debug Access Port

The debug access port (DAP) provides IEEE-1149.1 JTAG

interface support through its JTAG debug and serial wire debug

port (SWJ-DP). SWJ-DP is a combined JTAG-DP and SW-DP

that enables either serial wire debug (SWD) or a JTAG emulator

to be connected to a target. SWD signals share the same pins as

The evaluation board is designed to be used in conjunction with

the CrossCore Embedded Studio (CCES) development tools to

test capabilities of the ADSP-BF706 Blackfin processor.

Rev. A

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ADSP-BF700/701/702/703/704/705/706/707

registers. The emulators require the target board to include a

Blackfin Low Power Imaging Platform (BLIP)

header(s) that supports connection of the processor’s DAP to

the emulator for trace and debug.

The Blackfin low power imaging platform (BLIP) integrates the

ADSP-BF707 Blackfin processor and Analog Devices software

code libraries. The code libraries are optimized to detect the

presence and behavior of humans or vehicles in indoor and out-

door environments. The BLIP hardware platform is delivered

preloaded with the occupancy software module.

Analog Devices emulators actively drive JTG_TRST high.

Third-party emulators may expect a pull-up on JTG_TRST and

therefore will not drive JTG_TRST high. When using this type

of third-party emulator JTG_TRST must still be driven low

during power-up reset, but should subsequently be driven high

externally before any emulation or boundary-scan operations.

See Power-Up Reset Timing on Page 61 for more information

on POR specifications.

For more details on target board design issues including

mechanical layout, single processor connections, signal buffer-

ing, signal termination, and emulator pod logic, contact the

factory for more information.

Software Add-Ins for CrossCore Embedded Studio

Analog Devices offers software add-ins which seamlessly inte-

grate with CrossCore Embedded Studio to extend its capabilities

and reduce development time. Add-ins include board support

packages for evaluation hardware, various middleware pack-

ages, and algorithmic modules. Documentation, help,

configuration dialogs, and coding examples present in these

add-ins are viewable through the CrossCore Embedded Studio

IDE once the add-in is installed.

ADDITIONAL INFORMATION

The following publications that describe the ADSP-BF70x pro-

cessors can be accessed electronically on our website:

• ADSP-BF70x Blackfin+ Processor Hardware Reference

• ADSP-BF70x Blackfin+ Processor Programming Reference

• ADSP-BF70x Blackfin+ Processor Anomaly List

Board Support Packages for Evaluation Hardware

Software support for the EZ-KIT Lite evaluation boards and EZ-

Extender daughter cards is provided by software add-ins called

board support packages (BSPs). The BSPs contain the required

drivers, pertinent release notes, and select example code for the

given evaluation hardware. A download link for a specific BSP is

located on the web page for the associated EZ-KIT or EZ-

Extender product. The link is found in the Product Download

area of the product web page.

RELATED SIGNAL CHAINS

A signal chain is a series of signal-conditioning electronic com-

ponents that receive input (data acquired from sampling either

real-time phenomena or from stored data) in tandem, with the

output of one portion of the chain supplying input to the next.

Signal chains are often used in signal processing applications to

gather and process data or to apply system controls based on

analysis of real-time phenomena.

Middleware Packages

Analog Devices separately offers middleware add-ins such as

real time operating systems, file systems, USB stacks, and

TCP/IP stacks. For more information, see the following web

pages:

Analog Devices eases signal processing system development by

providing signal processing components that are designed to

work together well. A tool for viewing relationships between

specific applications and related components is available on the

www.analog.com website.

The application signal chains page in the Circuits from the Lab^®

site (http:\\www.analog.com\circuits) provides:

• www.analog.com/ucos3

• www.analog.com/ucfs

• www.analog.com/ucusbd

• www.analog.com/lwip

Algorithmic Modules

To speed development, Analog Devices offers add-ins that per-

form popular audio and video processing algorithms. These are

available for use with CrossCore Embedded Studio. For more

information, visit www.analog.com and search on “Blackfin

software modules” or “SHARC software modules”.

• Graphical circuit block diagram presentation of signal

chains for a variety of circuit types and applications

• Drill down links for components in each chain to selection

guides and application information

• Reference designs applying best practice design techniques

Designing an Emulator-Compatible DSP Board (Target)

For embedded system test and debug, Analog Devices provides

a family of emulators. On each DAP-enabled processor, Analog

Devices supplies an IEEE 1149.1 JTAG test access port (TAP),

serial wire debug port (SWJ-DP), and trace capabilities. 

In-circuit emulation is facilitated by use of the JTAG or SWD

interface. The emulator accesses the processor’s internal fea-

tures through the processor’s TAP, allowing the developer to

load code, set breakpoints, and view variables, memory, and

Rev. A

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ADSP-BF700/701/702/703/704/705/706/707

SECURITY FEATURES DISCLAIMER

To our knowledge, the Security Features, when used in accor-

dance with the data sheet and hardware reference manual

specifications, provide a secure method of implementing code

and data safeguards. However, Analog Devices does not guaran-

tee that this technology provides absolute security.

ACCORDINGLY, ANALOG DEVICES HEREBY DISCLAIMS

ANY AND ALL EXPRESS AND IMPLIED WARRANTIES

THAT THE SECURITY FEATURES CANNOT BE

BREACHED, COMPROMISED, OR OTHERWISE CIRCUM-

VENTED AND IN NO EVENT SHALL ANALOG DEVICES

BE LIABLE FOR ANY LOSS, DAMAGE, DESTRUCTION, OR

RELEASE OF DATA, INFORMATION, PHYSICAL PROP-

ERTY, OR INTELLECTUAL PROPERTY.

Rev. A

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ADSP-BF700/701/702/703/704/705/706/707

ADSP-BF70x DETAILED SIGNAL DESCRIPTIONS

Table 6 provides a detailed description of each pin.

Table 6. ADSP-BF70x Detailed Signal Descriptions

Port Name

CAN_RX

CAN_TX

Direction

Input

Description

Receive. Typically an external CAN transceiver's RX output.

Transmit. Typically an external CAN transceiver's TX input.

Count Down and Gate. Depending on the mode of operation this input acts either as a count down

signal or a gate signal Count Down - This input causes the GP counter to decrement Gate - Stops the

GP counter from incrementing or decrementing.

Output

Input

CNT_DG

CNT_UD

CNT_ZM

Input

Count Up and Direction. Depending on the mode of operation this input acts either as a count up

signal or a direction signal Count Up - This input causes the GP counter to increment Direction - Selects

whether the GP counter is incrementing or decrementing.

Count Zero Marker. Input that connects to the zero marker output of a rotary device or detects the

pressing of a pushbutton.

DMC_Ann

DMC_BAn

Output

Address n. Address bus.

Bank Address Input n. Defines which internal bank an ACTIVATE, READ, WRITE, or PRECHARGE

command is being applied to on the dynamic memory. Also defines which mode registers (MR, EMR,

EMR2, and/or EMR3) are loaded during the LOAD MODE REGISTER command.

DMC_CAS

Output

Column Address Strobe. Defines the operation for external dynamic memory to perform in

conjunction with other DMC command signals. Connect to the CAS input of dynamic memory.

DMC_CK

Output

I/O

Clock. Outputs DCLK to external dynamic memory.

Clock (Complement). Complement of DMC_CK.

Clock enable. Active high clock enables. Connects to the dynamic memory's CKE input.

Chip Select n. Commands are recognized by the memory only when this signal is asserted.

Data n. Bidirectional Data bus.

DMC_CK

DMC_CKE

DMC_CSn

DMC_DQnn

DMC_LDM

Output

Data Mask for Lower Byte. Mask for DMC_DQ07:DMC_DQ00 write data when driven high. Sampled

on both edges of the data strobe by the dynamic memory.

DMC_LDQS

I/O

Data Strobe for Lower Byte. DMC_DQ07:DMC_DQ00 data strobe. Output with Write Data. Input with

Read Data. May be single-ended or differential depending on register settings.

DMC_LDQS

DMC_ODT

I/O

Data Strobe for Lower Byte (complement). Complement of LDQS. Not used in single-ended mode.

On-die termination. Enables dynamic memory termination resistances when driven high (assuming

Output

the memory is properly configured). ODT is enabled/disabled regardless of read or write commands.

DMC_RAS

DMC_UDM

DMC_UDQS

Output

I/O

Row Address Strobe. Defines the operation for external dynamic memory to perform in conjunction

with other DMC command signals. Connect to the RAS input of dynamic memory.

Data Mask for Upper Byte. Mask for DMC_DQ15:DMC_DQ08 write data when driven high. Sampled

on both edges of the data strobe by the dynamic memory.

Data Strobe for Upper Byte. DMC_DQ15:DMC_DQ08 datastrobe. Output with Write Data. Input with

Read Data. May be single-ended or differential depending on register settings.

DMC_UDQS

DMC_VREF

DMC_WE

I/O

Data StrobeforUpperByte(complement). Complement ofUDQSb. Not usedin single-ended mode.

Voltage Reference. Connect to half of the VDD_DMC voltage.

Write Enable. Defines the operation for external dynamic memory to perform in conjunction with

Input

Output

other DMC command signals. Connect to the WE input of dynamic memory.

PPI_CLK

PPI_Dnn

PPI_FS1

I/O

Clock. Input in external clock mode, output in internal clock mode.

Data n. Bidirectional data bus.

Frame Sync 1 (HSYNC). Behavior depends on EPPI mode. See the EPPI HRM chapter for more details.

Frame Sync 2 (VSYNC). Behavior depends on EPPI mode. See the EPPI HRM chapter for more details.

Frame Sync 3 (FIELD). Behavior depends on EPPI mode. See the EPPI HRM chapter for more details.

Analog Input at channel n. Analog voltage inputs for digital conversion.

I/O

PPI_FS2

I/O

PPI_FS3

I/O

HADC_VINn

Input

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Table 6. ADSP-BF70x Detailed Signal Descriptions (Continued)

Port Name

Direction

Description

HADC_VREFN

Input

Ground Reference for ADC. Connect to an external voltage reference that meets data sheet

specifications.

HADC_VREFP

Input

External Reference for ADC. Connect to an external voltage reference that meets data sheet

specifications.

MSI_CD

MSI_CLK

MSI_CMD

MSI_Dn

MSI_INT

Input

Output

I/O

Card Detect. Connects to a pull-up resistor and to the card detect output of an SD socket.

Clock. The clock signal applied to the connected device from the MSI.

Command. Used to send commands to and receive responses from the connected device.

Data n. Bidirectional data bus.

I/O

Input

eSDIO Interrupt Input. Used only for eSDIO. Connects to an eSDIO card's interrupt output. An

interrupt may be sampled even when the MSI clock to the card is switched off.

Px_nn

I/O

Position n. General purpose input/output. See the GP Ports chapter of the HRM for programming

information.

RTC_CLKIN

RTC_XTAL

Input

Crystal input/external oscillator connection. Connect to an external clock source or crystal.

Crystal output. Drives an external crystal. Must be left unconnected if an external clock is driving

Output

RTC_CLKIN.

SMC_ABEn

Output

Byte Enable n. Indicate whether the lower or upper byte of a memory is being accessed. When an

asynchronous write is made to the upper byte of a 16-bit memory, SMC_ABE1b=0 and SMC_ABE0b=1.

When an asynchronous write is made to the lower byte of a 16-bit memory, SMC_ABE1b=1 and SMC_

ABE0b=0.

SMC_AMSn

SMC_AOE

Output

Input

Memory Select n. Typically connects to the chip select of a memory device.

Output Enable. Asserts at the beginning of the setup period of a read access.

Asynchronous Ready. Flow control signal used by memory devices to indicate to the SMC when

SMC_ARDY

further transactions may proceed.

SMC_ARE

SMC_AWE

SMC_Ann

SMC_Dnn

SPI_CLK

Output

I/O

Read Enable. Asserts at the beginning of a read access.

Write Enable. Asserts for the duration of a write access period.

Address n. Address bus.

Data n. Bidirectional data bus.

Clock. Input in slave mode, output in master mode.

I/O

SPI_D2

I/O

Data 2. Used to transfer serial data in Quad mode. Open-drain when ODM mode is enabled.

Data 3. Used to transfer serial data in Quad mode. Open-drain when ODM mode is enabled.

SPI_D3

I/O

SPI_MISO

I/O

Master In, Slave Out. Used to transfer serial data. Operates in the same direction as SPI_MOSI in Dual

and Quad modes. Open-drain when ODM mode is enabled.

SPI_MOSI

I/O

Master Out, Slave In. Used to transfer serial data. Operates in the same direction as SPI_MISO in Dual

and Quad modes. Open-drain when ODM mode is enabled.

SPI_RDY

SPI_SELn

SPI_SS

I/O

Ready. Optional flow signal. Output in slave mode, input in master mode.

Slave Select Output n. Used in Master mode to enable the desired slave.

Slave Select Input. Slave mode - Acts as the slave select input. Master mode- Optionally serves as an

Output

Input

error detection input for the SPI when there are multiple masters.

SPT_ACLK

SPT_AD0

SPT_AD1

SPT_AFS

SPT_ATDV

I/O

Channel A Clock. Data and Frame Sync are driven/sampled with respect to this clock. This signal can

be either internally or externally generated.

I/O

Channel A Data 0. Primary bidirectional data I/O. This signal can be configured as an output to

transmit serial data, or as an input to receive serial data.

I/O

Channel A Data 1. Secondary bidirectional data I/O. This signal can be configured as an output to

transmit serial data, or as an input to receive serial data.

I/O

Channel A Frame Sync. The frame sync pulse initiates shifting of serial data. This signal is either

generated internally or externally.

Output

Channel A Transmit Data Valid. This signal is optional and only active when SPORT is configured in

multichannel transmit mode. It is asserted during enabled slots.

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Table 6. ADSP-BF70x Detailed Signal Descriptions (Continued)

Port Name

Direction

Description

SPT_BCLK

I/O

Channel B Clock. Data and Frame Sync are driven/sampled with respect to this clock. This signal can

be either internally or externally generated.

SPT_BD0

SPT_BD1

SPT_BFS

SPT_BTDV

I/O

Channel B Data 0. Primary bidirectional data I/O. This signal can be configured as an output to

transmit serial data, or as an input to receive serial data.

I/O

Channel B Data 1. Secondary bidirectional data I/O. This signal can be configured as an output to

transmit serial data, or as an input to receive serial data.

I/O

Channel B Frame Sync. The frame sync pulse initiates shifting of serial data. This signal is either

generated internally or externally.

Output

Channel B Transmit Data Valid. This signal is optional and only active when SPORT is configured in

multi-channel transmit mode. It is asserted during enabled slots.

SYS_BMODEn

SYS_CLKIN

Input

Boot Mode Control n. Selects the boot mode of the processor.

Clock/Crystal Input. Connect to an external clock source or crystal.

Input

SYS_CLKOUT

Output

Processor Clock Output. Outputs internal clocks. Clocks may be divided down. See the CGU chapter

of the HRM for more details.

SYS_EXTWAKE

SYS_FAULT

Output

I/O

External Wake Control. Drives low during hibernate and high all other times. Typically connected to

the enable input of the voltage regulator controlling the VDD_INT supply.

Active-Low Fault Output. Indicates internal faults or senses external faults depending on the

operating mode.

SYS_HWRST

SYS_NMI

Input

Processor Hardware Reset Control. Resets the device when asserted.

Non-maskable Interrupt. See the processor hardware and programming references for more details.

Reset Output. Indicates that the device is in the reset or hibernate state.

Power Saving Mode Wakeup n. Wake-up source input for deep sleep and/or hibernate mode.

Crystal Output. Drives an external crystal. Must be left unconnected if an external clock is driving

Input

SYS_RESOUT

SYS_WAKEn

SYS_XTAL

Output

Input

Output

CLKIN.

JTG_SWCLK

JTG_SWDIO

JTG_SWO

JTG_TCK

I/O

Serial Wire Clock. Clocks data into and out of the target during debug.

Serial Wire DIO. Sends and receives serial data to and from the target during debug.

Serial Wire Out. Provides trace data to the emulator.

JTAG Clock. JTAG test access port clock.

JTAG Serial Data In. JTAG test access port data input.

JTAG Serial Data Out. JTAG test access port data output.

JTAG Mode Select. JTAG test access port mode select.

JTAG Reset. JTAG test access port reset.

Alternate Capture Input n. Provides an additional input for WIDCAP, WATCHDOG, and PININT modes.

Alternate Clock n. Provides an additional time base for use by an individual timer.

Clock. Provides an additional global time base for use by all the GP timers.

Timer n. The main input/output signal for each timer.

Trace Clock. Clock output.

I/O

Output

Input

Output

Input

I/O

JTG_TDI

JTG_TDO

JTG_TMS

JTG_TRST

TM_ACIn

TM_ACLKn

TM_CLK

TM_TMRn

TRACE_CLK

TRACE_Dnn

TWI_SCL

Output

I/O

Trace Data n. Unidirectional data bus.

Serial Clock. Clock output when master, clock input when slave.

Serial Data. Receives or transmits data.

Clear to Send. Flow control signal.

Request to Send. Flow control signal.

TWI_SDA

UART_CTS

UART_RTS

UART_RX

I/O

Input

Output

Input

Receive. Receive input. Typically connects to a transceiver that meets the electrical requirements of

the device being communicated with.

UART_TX

Output

Input

Transmit. Transmit output. Typically connects to a transceiver that meets the electrical requirements

of the device being communicated with.

USB_CLKIN

Clock/Crystal Input. This clock input is multiplied by a PLL to form the USB clock. See data sheet

specifications for frequency/tolerance information.

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Table 6. ADSP-BF70x Detailed Signal Descriptions (Continued)

Port Name

USB_DM

USB_DP

USB_ID

Direction

I/O

Description

Data –. Bidirectional differential data line.

Data +. Bidirectional differential data line.

OTG ID. Senses whether the controller is a host or device. This signal is pulled low when an A-type

plug is sensed (signifying that the USB controller is the A device), but the input is high when a B-type

plug is sensed (signifying that the USB controller is the B device).

I/O

Input

USB_VBC

Output

VBUS Control. Controls an external voltage source to supply VBUS when in host mode. May be

configured as open-drain. Polarity is configurable as well.

USB_VBUS

USB_XTAL

I/O

Bus Voltage. Connects to bus voltage in host and device modes.

Crystal. Drives an external crystal. Must be left unconnected if an external clock is driving USB_CLKIN.

Output

Rev. A

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ADSP-BF700/701/702/703/704/705/706/707

184-BALL CSP_BGA SIGNAL DESCRIPTIONS

The processor’s pin definitions are shown in Table 7. The col-

umns in this table provide the following information:

• Signal Name: The Signal Name column in the table

includes the signal name for every pin and (where applica-

ble) the GPIO multiplexed pin function for every pin.

• Description: The Description column in the table provides

a verbose (descriptive) name for the signal.

• General-Purpose Port: The Port column in the table shows

whether or not the signal is multiplexed with other signals

on a general-purpose I/O port pin.

• Pin Name: The Pin Name column in the table identifies the

name of the package pin (at power on reset) on which the

signal is located (if a single function pin) or is multiplexed

(if a general-purpose I/O pin).

Table 7. ADSP-BF70x 184-Ball CSP_BGA Signal Descriptions

Signal Name

CAN0_RX

Description

CAN0 Receive

Port

C

Pin Name

PC_02

CAN0_TX

CAN0 Transmit

C

PC_03

CAN1_RX

CAN1 Receive

A

PA_12

CAN1_TX

CAN1 Transmit

A

PA_13

CNT0_DG

CNT0 Count Down and Gate

CNT0 Count Up and Direction

CNT0 Count Zero Marker

DMC0 Address 0

A

PA_07

CNT0_UD

A

PA_15

CNT0_ZM

A

PA_13

DMC0_A00

DMC0_A01

DMC0_A02

DMC0_A03

DMC0_A04

DMC0_A05

DMC0_A06

DMC0_A07

DMC0_A08

DMC0_A09

DMC0_A10

DMC0_A11

DMC0_A12

DMC0_A13

DMC0_BA0

DMC0_BA1

DMC0_BA2

DMC0_CAS

DMC0_CK

Not Muxed

DMC0_A00

DMC0_A01

DMC0_A02

DMC0_A03

DMC0_A04

DMC0_A05

DMC0_A06

DMC0_A07

DMC0_A08

DMC0_A09

DMC0_A10

DMC0_A11

DMC0_A12

DMC0_A13

DMC0_BA0

DMC0_BA1

DMC0_BA2

DMC0_CAS

DMC0_CK

DMC0_CKE

DMC0_CK

DMC0_CS0

DMC0_DQ00

DMC0_DQ01

DMC0_DQ02

DMC0_DQ03

DMC0_DQ04

DMC0_DQ05

DMC0_DQ06

DMC0 Address 1

DMC0 Address 2

DMC0 Address 3

DMC0 Address 4

DMC0 Address 5

DMC0 Address 6

DMC0 Address 7

DMC0 Address 8

DMC0 Address 9

DMC0 Address 10

DMC0 Address 11

DMC0 Address 12

DMC0 Address 13

DMC0 Bank Address Input 0

DMC0 Bank Address Input 1

DMC0 Bank Address Input 2

DMC0 Column Address Strobe

DMC0 Clock

DMC0_CKE

DMC0_CK

DMC0 Clock enable

DMC0 Clock (complement)

DMC0 Chip Select 0

DMC0 Data 0

DMC0_CS0

DMC0_DQ00

DMC0_DQ01

DMC0_DQ02

DMC0_DQ03

DMC0_DQ04

DMC0_DQ05

DMC0_DQ06

DMC0 Data 1

DMC0 Data 2

DMC0 Data 3

DMC0 Data 4

DMC0 Data 5

DMC0 Data 6

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Table 7. ADSP-BF70x 184-Ball CSP_BGA Signal Descriptions (Continued)

Signal Name

DMC0_DQ07

DMC0_DQ08

DMC0_DQ09

DMC0_DQ10

DMC0_DQ11

DMC0_DQ12

DMC0_DQ13

DMC0_DQ14

DMC0_DQ15

DMC0_LDM

DMC0_LDQS

DMC0_ODT

DMC0_RAS

DMC0_UDM

DMC0_UDQS

DMC0_VREF

DMC0_WE

GND

Description

DMC0 Data 7

Port

Pin Name

Not Muxed

A

DMC0_DQ07

DMC0_DQ08

DMC0_DQ09

DMC0_DQ10

DMC0_DQ11

DMC0_DQ12

DMC0_DQ13

DMC0_DQ14

DMC0_DQ15

DMC0_LDM

DMC0_LDQS

DMC0_ODT

DMC0_RAS

DMC0_UDM

DMC0_UDQS

DMC0_VREF

DMC0_WE

GND

DMC0 Data 8

DMC0 Data 9

DMC0 Data 10

DMC0 Data 11

DMC0 Data 12

DMC0 Data 13

DMC0 Data 14

DMC0 Data 15

DMC0 Data Mask for Lower Byte

DMC0 Data Strobe for Lower Byte

DMC0 Data Strobe for Lower Byte (complement)

DMC0 On-die termination

DMC0 Row Address Strobe

DMC0 Data Mask for Upper Byte

DMC0 Data Strobe for Upper Byte

DMC0 Data Strobe for Upper Byte (complement)

DMC0 Voltage Reference

DMC0 Write Enable

Ground

GND_HADC

HADC0_VIN0

HADC0_VIN1

HADC0_VIN2

HADC0_VIN3

HADC0_VREFN

HADC0_VREFP

JTG_SWCLK

JTG_SWDIO

JTG_SWO

Ground HADC

GND_HADC

HADC0_VIN0

HADC0_VIN1

HADC0_VIN2

HADC0_VIN3

HADC0_VREFN

HADC0_VREFP

JTG_TCK_SWCLK

JTG_TMS_SWDIO

JTG_TDO_SWO

JTG_TCK_SWCLK

JTG_TDI

HADC0 Analog Input at channel 0

HADC0 Analog Input at channel 1

HADC0 Analog Input at channel 2

HADC0 Analog Input at channel 3

HADC0 Ground Reference for ADC

HADC0 External Reference for ADC

TAPC0 Serial Wire Clock

TAPC0 Serial Wire DIO

TAPC0 Serial Wire Out

TAPC0 JTAG Clock

JTG_TCK

JTG_TDI

TAPC0 JTAG Serial Data In

TAPC0 JTAG Serial Data Out

TAPC0 JTAG Mode Select

TAPC0 JTAG Reset

JTG_TDO

JTG_TDO_SWO

JTG_TMS_SWDIO

JTG_TRST

JTG_TMS

JTG_TRST

MSI0_CD

MSI0 Card Detect

PA_08

MSI0_CLK

MSI0 Clock

C

PC_09

MSI0_CMD

MSI0_D0

MSI0 Command

C

PC_05

MSI0 Data 0

C

PC_08

MSI0_D1

MSI0 Data 1

C

PC_04

MSI0_D2

MSI0 Data 2

C

PC_07

MSI0_D3

MSI0 Data 3

C

PC_06

MSI0_D4

MSI0 Data 4

C

PC_10

MSI0_D5

MSI0 Data 5

C

PC_11

MSI0_D6

MSI0 Data 6

C

PC_12

MSI0_D7

MSI0 Data 7

C

PC_13

Rev. A

|

Page 23 of 116

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ADSP-BF700/701/702/703/704/705/706/707

Table 7. ADSP-BF70x 184-Ball CSP_BGA Signal Descriptions (Continued)

Signal Name

MSI0_INT

Description

Port

C

Pin Name

PC_14

MSI0 eSDIO Interrupt Input

Position 00 through Position 15

Position 00 through Position 14

EPPI0 Clock

PA_00-PA_15

PB_00-PB_15

PC_00-PC_14

PPI0_CLK

A

PA_00-PA_15

PB_00-PB_15

PC_00-PC_14

PA_14

B

C

A

PPI0_D00

EPPI0 Data 0

B

PB_07

PPI0_D01

EPPI0 Data 1

B

PB_06

PPI0_D02

EPPI0 Data 2

B

PB_05

PPI0_D03

EPPI0 Data 3

B

PB_04

PPI0_D04

EPPI0 Data 4

B

PB_03

PPI0_D05

EPPI0 Data 5

B

PB_02

PPI0_D06

EPPI0 Data 6

B

PB_01

PPI0_D07

EPPI0 Data 7

B

PB_00

PPI0_D08

EPPI0 Data 8

A

PA_11

PPI0_D09

EPPI0 Data 9

A

PA_10

PPI0_D10

EPPI0 Data 10

A

PA_09

PPI0_D11

EPPI0 Data 11

A

PA_08

PPI0_D12

EPPI0 Data 12

C

PC_03

PPI0_D13

EPPI0 Data 13

C

PC_02

PPI0_D14

EPPI0 Data 14

C

PC_01

PPI0_D15

EPPI0 Data 15

C

PC_00

PPI0_D16

EPPI0 Data 16

B

PB_08

PPI0_D17

EPPI0 Data 17

B

PB_09

PPI0_FS1

EPPI0 Frame Sync 1 (HSYNC)

EPPI0 Frame Sync 2 (VSYNC)

EPPI0 Frame Sync 3 (FIELD)

RTC0 Crystal input/external oscillator connection

RTC0 Crystal output

SMC0 Address 1

A

PA_12

PPI0_FS2

A

PA_13

PPI0_FS3

A

PA_15

RTC0_CLKIN

RTC0_XTAL

SMC0_A01

SMC0_A02

SMC0_A03

SMC0_A04

SMC0_A05

SMC0_A06

SMC0_A07

SMC0_A08

SMC0_A09

SMC0_A10

SMC0_A11

SMC0_A12

SMC0_ABE0

SMC0_ABE1

SMC0_AMS0

SMC0_AMS1

SMC0_AOE

SMC0_ARDY

Not Muxed

RTC0_CLKIN

RTC0_XTAL

PA_08

Not Muxed

A

C

A

SMC0 Address 2

PA_09

SMC0 Address 3

PA_10

SMC0 Address 4

PA_11

SMC0 Address 5

PA_07

SMC0 Address 6

PA_06

SMC0 Address 7

PA_05

SMC0 Address 8

PA_04

SMC0 Address 9

PC_01

SMC0 Address 10

SMC0 Address 11

SMC0 Address 12

SMC0 Byte Enable 0

SMC0 Byte Enable 1

SMC0 Memory Select 0

SMC0 Memory Select 1

SMC0 Output Enable

SMC0 Asynchronous Ready

PC_02

PC_03

PC_04

PA_00

PA_01

PA_15

PA_02

PA_12

PA_03

Rev. A

|

Page 24 of 116

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September 2015

ADSP-BF700/701/702/703/704/705/706/707

Table 7. ADSP-BF70x 184-Ball CSP_BGA Signal Descriptions (Continued)

Signal Name

SMC0_ARE

SMC0_AWE

SMC0_D00

SMC0_D01

SMC0_D02

SMC0_D03

SMC0_D04

SMC0_D05

SMC0_D06

SMC0_D07

SMC0_D08

SMC0_D09

SMC0_D10

SMC0_D11

SMC0_D12

SMC0_D13

SMC0_D14

SMC0_D15

SPI0_CLK

Description

Port

A

B

Pin Name

PA_13

PA_14

PB_07

PB_06

PB_05

PB_04

PB_03

PB_02

PB_01

PB_00

PB_08

PB_09

PB_10

PB_11

PB_12

PB_13

PB_14

PB_15

PB_00

PC_04

PB_03

PC_08

PB_07

PC_09

PB_01

PC_06

PB_02

PC_07

PA_06

PA_05

PA_06

PC_11

PB_04

PB_05

PB_06

PA_05

PA_00

PA_01

PA_02

PA_03

PA_04

PA_03

PC_10

PA_14

PA_04

PB_10

SMC0 Read Enable

SMC0 Write Enable

SMC0 Data 0

SMC0 Data 1

B

SMC0 Data 2

B

SMC0 Data 3

B

SMC0 Data 4

B

SMC0 Data 5

B

SMC0 Data 6

B

SMC0 Data 7

B

SMC0 Data 8

B

SMC0 Data 9

B

SMC0 Data 10

B

SMC0 Data 11

B

SMC0 Data 12

B

SMC0 Data 13

B

SMC0 Data 14

B

SMC0 Data 15

B

SPI0 Clock

B

SPI0_CLK

SPI0 Clock

C

B

SPI0_D2

SPI0 Data 2

SPI0_D2

SPI0 Data 2

C

B

SPI0_D3

SPI0 Data 3

SPI0_D3

SPI0 Data 3

C

B

SPI0_MISO

SPI0_MOSI

SPI0_RDY

SPI0_SEL1

SPI0_SEL2

SPI0_SEL3

SPI0_SEL4

SPI0_SEL5

SPI0_SEL6

SPI0_SS

SPI0 Master In, Slave Out

SPI0 Master Out, Slave In

SPI0 Ready

C

B

C

A

C

B

SPI0 Slave Select Output 1

SPI0 Slave Select Output 2

SPI0 Slave Select Output 3

SPI0 Slave Select Output 4

SPI0 Slave Select Output 5

SPI0 Slave Select Output 6

SPI0 Slave Select Input

SPI1 Clock

B

A

C

A

B

SPI1_CLK

SPI1_MISO

SPI1_MOSI

SPI1_RDY

SPI1_SEL1

SPI1_SEL2

SPI1_SEL3

SPI1_SEL4

SPI1_SS

SPI1 Master In, Slave Out

SPI1 Master Out, Slave In

SPI1 Ready

SPI1 Slave Select Output 1

SPI1 Slave Select Output 2

SPI1 Slave Select Output 3

SPI1 Slave Select Output 4

SPI1 Slave Select Input

SPI2 Clock

SPI2_CLK

Rev. A

|

Page 25 of 116

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September 2015

ADSP-BF700/701/702/703/704/705/706/707

Table 7. ADSP-BF70x 184-Ball CSP_BGA Signal Descriptions (Continued)

Signal Name

SPI2_D2

Description

SPI2 Data 2

Port

B

Pin Name

PB_13

SPI2_D3

SPI2 Data 3

B

PB_14

SPI2_MISO

SPI2_MOSI

SPI2_RDY

SPI2 Master In, Slave Out

SPI2 Master Out, Slave In

SPI2 Ready

B

PB_11

B

PB_12

A

PA_04

SPI2_SEL1

SPI2_SEL2

SPI2_SEL3

SPI2_SS

SPI2 Slave Select Output 1

SPI2 Slave Select Output 2

SPI2 Slave Select Output 3

SPI2 Slave Select Input

B

PB_15

B

PB_08

B

PB_09

B

PB_15

SPT0_ACLK

SPT0_AD0

SPT0_AD1

SPT0_AFS

SPT0_ATDV

SPT0_BCLK

SPT0_BD0

SPT0_BD1

SPT0_BFS

SPORT0 Channel A Clock

SPORT0 Channel A Data 0

SPORT0 Channel A Data 1

SPORT0 Channel A Frame Sync

SPORT0 Channel A Transmit Data Valid

SPORT0 Channel B Clock

SPORT0 Channel B Data 0

SPORT0 Channel B Data 1

SPORT0 Channel B Frame Sync

SPORT0 Channel B Transmit Data Valid

SPORT1 Channel A Clock

SPORT1 Channel A Data 0

SPORT1 Channel A Data 1

SPORT1 Channel A Frame Sync

SPORT1 Channel A Transmit Data Valid

SPORT1 Channel B Clock

SPORT1 Channel B Data 0

SPORT1 Channel B Data 1

SPORT1 Channel B Frame Sync

SPORT1 Channel B Transmit Data Valid

Boot Mode Control 0

A

PA_13

C

PC_09

A

PA_14

C

PC_08

C

PC_00

A

PA_12

C

PC_05

A

PA_15

B

PB_04

C

PC_04

B

PB_05

C

PC_06

B

PB_07

C

PC_01

B

PB_06

SPT0_BFS

C

PC_07

SPT0_BTDV

SPT1_ACLK

SPT1_AD0

SPT1_AD1

SPT1_AFS

SPT1_ATDV

SPT1_BCLK

SPT1_BD0

SPT1_BD1

SPT1_BFS

A

PA_15

A

PA_08

A

PA_10

A

PA_11

A

PA_09

A

PA_07

B

PB_00

C

PC_10

B

PB_02

C

PC_12

B

PB_03

C

PC_13

B

PB_01

SPT1_BFS

C

PC_11

SPT1_BTDV

SYS_BMODE0

SYS_BMODE1

SYS_CLKIN

SYS_CLKOUT

SYS_EXTWAKE

A

PA_07

C

PC_14

Not Muxed

SYS_BMODE0

SYS_BMODE1

SYS_CLKIN

SYS_CLKOUT

SYS_EXTWAKE

Boot Mode Control 1

Clock/Crystal Input

Processor Clock Output

External Wake Control

Rev. A

|

Page 26 of 116

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September 2015

ADSP-BF700/701/702/703/704/705/706/707

Table 7. ADSP-BF70x 184-Ball CSP_BGA Signal Descriptions (Continued)

Signal Name

SYS_FAULT

SYS_HWRST

SYS_NMI

Description

Port

Not Muxed

Pin Name

SYS_FAULT

SYS_HWRST

SYS_NMI

SYS_RESOUT

PB_07

Active-Low Fault Output

Processor Hardware Reset Control

Nonmaskable Interrupt

Reset Output

Not Muxed

SYS_RESOUT

SYS_WAKE0

SYS_WAKE1

SYS_WAKE2

SYS_WAKE3

SYS_WAKE4

SYS_XTAL

Not Muxed

Power Saving Mode Wake-up 0

Power Saving Mode Wake-up 1

Power Saving Mode Wake-up 2

Power Saving Mode Wake-up 3

Power Saving Mode Wake-up 4

Crystal Output

B

PB_08

B

PB_12

C

PC_02

A

PA_12

Not Muxed

SYS_XTAL

PC_03

TM0_ACI0

TIMER0 Alternate Capture Input 0

TIMER0 Alternate Capture Input 1

TIMER0 Alternate Capture Input 2

TIMER0 Alternate Capture Input 3

TIMER0 Alternate Capture Input 4

TIMER0 Alternate Capture Input 5

TIMER0 Alternate Capture Input 6

TIMER0 Alternate Clock 0

TIMER0 Alternate Clock 1

TIMER0 Alternate Clock 2

TIMER0 Alternate Clock 3

TIMER0 Alternate Clock 4

TIMER0 Alternate Clock 5

TIMER0 Alternate Clock 6

TIMER0 Clock

C

TM0_ACI1

B

PB_01

TM0_ACI2

C

PC_07

TM0_ACI3

B

PB_09

TM0_ACI4

C

PC_01

TM0_ACI5

C

PC_02

TM0_ACI6

A

PA_12

TM0_ACLK0

TM0_ACLK1

TM0_ACLK2

TM0_ACLK3

TM0_ACLK4

TM0_ACLK5

TM0_ACLK6

TM0_CLK

C

PC_04

C

PC_10

C

PC_09

B

PB_00

B

PB_10

A

PA_14

B

PB_04

B

PB_06

TM0_TMR0

TM0_TMR1

TM0_TMR2

TM0_TMR3

TM0_TMR4

TM0_TMR5

TM0_TMR6

TM0_TMR7

TRACE0_CLK

TRACE0_D00

TRACE0_D01

TRACE0_D02

TRACE0_D03

TRACE0_D04

TRACE0_D05

TRACE0_D06

TRACE0_D07

TWI0_SCL

TIMER0 Timer 0

A

PA_05

TIMER0 Timer 1

A

PA_06

TIMER0 Timer 2

A

PA_07

TIMER0 Timer 3

C

PC_05

TIMER0 Timer 4

A

PA_09

TIMER0 Timer 5

A

PA_10

TIMER0 Timer 6

A

PA_11

TIMER0 Timer 7

A

PA_04

TPIU0 Trace Clock

B

PB_10

TPIU0 Trace Data 0

B

PB_15

TPIU0 Trace Data 1

B

PB_14

TPIU0 Trace Data 2

B

PB_13

TPIU0 Trace Data 3

B

PB_12

TPIU0 Trace Data 4

B

PB_11

TPIU0 Trace Data 5

A

PA_02

TPIU0 Trace Data 6

A

PA_01

TPIU0 Trace Data 7

A

PA_00

TWI0 Serial Clock

Not Muxed

TWI0_SCL

TWI0_SDA

PC_03

TWI0_SDA

UART0_CTS

UART0_RTS

TWI0 Serial Data

Not Muxed

UART0 Clear to Send

C

UART0 Request to Send

PC_02

Rev. A

|

Page 27 of 116

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ADSP-BF700/701/702/703/704/705/706/707

Table 7. ADSP-BF70x 184-Ball CSP_BGA Signal Descriptions (Continued)

Signal Name

UART0_RX

UART0_TX

UART1_CTS

UART1_RTS

UART1_RX

UART1_TX

USB0_CLKIN

USB0_DM

USB0_DP

Description

Port

B

Pin Name

PB_09

UART0 Receive

UART0 Transmit

UART1 Clear to Send

UART1 Request to Send

UART1 Receive

UART1 Transmit

USB0 Clock/Crystal Input

USB0 Data –

B

PB_08

B

PB_14

B

PB_13

C

PC_01

C

PC_00

Not Muxed

USB0_CLKIN

USB0_DM

USB0_DP

USB0_ID

USB0_VBC

USB0_VBUS

USB0_XTAL

VDD_DMC

VDD_EXT

VDD_HADC

VDD_INT

VDD_OTP

VDD_RTC

VDD_USB

USB0 Data +

USB0_ID

USB0 OTG ID

USB0_VBC

USB0_VBUS

USB0_XTAL

VDD_DMC

VDD_EXT

USB0 VBUS Control

USB0 Bus Voltage

USB0 Crystal

VDD for DMC

External VDD

VDD_HADC

VDD_INT

VDD for HADC

Internal VDD

VDD_OTP

VDD_RTC

VDD for OTP

VDD for RTC

VDD_USB

VDD for USB

Rev. A

|

Page 28 of 116

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September 2015

ADSP-BF700/701/702/703/704/705/706/707

GPIO MULTIPLEXING FOR 184-BALL CSP_BGA

Table 8 through Table 10 identify the pin functions that are

multiplexed on the general-purpose I/O pins of the 184-ball

CSP_BGA package.

Table 8. Signal Multiplexing for Port A

Multiplexed

Function 0

Multiplexed

Function 1

Multiplexed

Function 2

TRACE0_D07

TRACE0_D06

TRACE0_D05

Multiplexed

Function 3

Multiplexed

Function Input Tap

Signal Name

PA_00

PA_01

PA_02

PA_03

PA_04

PA_05

PA_06

PA_07

PA_08

PA_09

PA_10

PA_11

PA_12

SPI1_CLK

SPI1_MISO

SPI1_MOSI

SPI1_SEL2

SPI1_SEL1

TM0_TMR0

TM0_TMR1

TM0_TMR2

PPI0_D11

PPI0_D10

PPI0_D09

PPI0_D08

PPI0_FS1

SMC0_ABE0

SMC0_ABE1

SMC0_AMS1

SMC0_ARDY

SMC0_A08

SMC0_A07

SMC0_A06

SMC0_A05

SMC0_A01

SMC0_A02

SMC0_A03

SMC0_A04

SMC0_AOE

SPI1_RDY

TM0_TMR7

SPI0_SEL1

SPI0_SEL2

SPT1_BTDV

MSI0_CD

SPI2_RDY

SPI1_SS

SPI0_SS

SPI0_RDY

SPT1_ATDV

SPT1_ACLK

SPT1_AFS

SPT1_AD0

SPT1_AD1

SPT0_AFS

CNT0_DG

TM0_TMR4

TM0_TMR5

TM0_TMR6

CAN1_RX

TM0_ACI6/SYS_

WAKE4

PA_13

PA_14

PA_15

PPI0_FS2

PPI0_CLK

PPI0_FS3

CAN1_TX

SPI1_SEL4

SPT0_ATDV

SPT0_ACLK

SPT0_AD0

SPT0_BTDV

SMC0_ARE

SMC0_AWE

SMC0_AMS0

CNT0_ZM

TM0_ACLK5

CNT0_UD

Table 9. Signal Multiplexing for Port B

Multiplexed

Function 1

Multiplexed

Function 2

SPI0_CLK

Multiplexed

Function 3

Multiplexed

Function Input Tap

TM0_ACLK3

TM0_ACI1

Signal Name

PB_00

PB_01

PB_02

PB_03

PB_04

PB_05

PB_06

PB_07

PB_08

PB_09

PB_10

PB_11

PB_12

PB_13

PB_14

PB_15

Function 0

PPI0_D07

PPI0_D06

PPI0_D05

PPI0_D04

PPI0_D03

PPI0_D02

PPI0_D01

PPI0_D00

UART0_TX

UART0_RX

SPI2_CLK

SPI2_MISO

SPI2_MOSI

SPI2_D2

SPT1_BCLK

SPT1_BFS

SPT1_BD0

SPT1_BD1

SPT0_BCLK

SPT0_BD0

SPT0_BFS

SPT0_BD1

PPI0_D16

PPI0_D17

SMC0_D07

SMC0_D06

SMC0_D05

SMC0_D04

SMC0_D03

SMC0_D02

SMC0_D01

SMC0_D00

SMC0_D08

SMC0_D09

SMC0_D10

SMC0_D11

SMC0_D12

SMC0_D13

SMC0_D14

SMC0_D15

SPI0_MISO

SPI0_MOSI

SPI0_D2

SPI0_SEL4

SPI0_SEL5

SPI0_SEL6

SPI0_D3

TM0_ACLK6

TM0_CLK

SYS_WAKE0

SYS_WAKE1

TM0_ACI3

TM0_ACLK4

SPI2_SEL2

SPI2_SEL3

TRACE0_CLK

TRACE0_D04

TRACE0_D03

TRACE0_D02

TRACE0_D01

TRACE0_D00

SYS_WAKE2

SPI2_SS

UART1_RTS

UART1_CTS

SPI2_D3

SPI2_SEL1

Rev. A

|

Page 29 of 116

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September 2015

ADSP-BF700/701/702/703/704/705/706/707

Table 10. Signal Multiplexing for Port C

Multiplexed

Function 0

UART1_TX

UART1_RX

UART0_RTS

Multiplexed

Function 1

SPT0_AD1

SPT0_BD1

CAN0_RX

Multiplexed

Function 2

PPI0_D15

PPI0_D14

PPI0_D13

Multiplexed

Function 3

Multiplexed

Function Input Tap

Signal Name

PC_00

PC_01

SMC0_A09

SMC0_A10

TM0_ACI4

PC_02

TM0_ACI5/SYS_

WAKE3

PC_03

PC_04

PC_05

PC_06

PC_07

PC_08

PC_09

PC_10

PC_11

PC_12

PC_13

PC_14

UART0_CTS

SPT0_BCLK

SPT0_AFS

SPT0_BD0

SPT0_BFS

SPT0_AD0

SPT0_ACLK

SPT1_BCLK

SPT1_BFS

SPT1_BD0

SPT1_BD1

SPT1_BTDV

CAN0_TX

SPI0_CLK

TM0_TMR3

SPI0_MISO

SPI0_MOSI

SPI0_D2

PPI0_D12

MSI0_D1

MSI0_CMD

MSI0_D3

MSI0_D2

MSI0_D0

MSI0_CLK

SPI1_SEL3

SPI0_SEL3

SMC0_A11

SMC0_A12

TM0_ACI0

TM0_ACLK0

TM0_ACI2

SPI0_D3

TM0_ACLK2

TM0_ACLK1

MSI0_D4

MSI0_D5

MSI0_D6

MSI0_D7

MSI0_INT

Rev. A

|

Page 30 of 116

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September 2015

ADSP-BF700/701/702/703/704/705/706/707

12 mm × 12 mm 88-LEAD LFCSP (QFN) SIGNAL DESCRIPTIONS

The processor’s pin definitions are shown in Table 11. The col-

• General-Purpose Port: The Port column in the table shows

whether or not the signal is multiplexed with other signals

on a general-purpose I/O port pin.

• Pin Name: The Pin Name column in the table identifies the

name of the package pin (at power on reset) on which the

signal is located (if a single function pin) or is multiplexed

(if a general-purpose I/O pin).

umns in this table provide the following information:

• Signal Name: The Signal Name column in the table

includes the signal name for every pin and (where applica-

ble) the GPIO multiplexed pin function for every pin.

• Description: The Description column in the table provides

a verbose (descriptive) name for the signal.

Table 11. ADSP-BF70x 12 mm × 12 mm 88-Lead LFCSP (QFN) Signal Descriptions

Signal Name

CAN0_RX

CAN0_TX

CAN1_RX

CAN1_TX

CNT0_DG

CNT0_UD

CNT0_ZM

GND

Description

CAN0 Receive

Port

C

Pin Name

PC_02

CAN0 Transmit

C

PC_03

CAN1 Receive

A

PA_12

CAN1 Transmit

A

PA_13

CNT0 Count Down and Gate

CNT0 Count Up and Direction

CNT0 Count Zero Marker

Ground

A

PA_07

A

PA_15

A

PA_13

Not Muxed

GND

JTG_SWCLK

JTG_SWDIO

JTG_SWO

JTG_TCK

TAPC0 Serial Wire Clock

TAPC0 Serial Wire DIO

TAPC0 Serial Wire Out

TAPC0 JTAG Clock

TAPC0 JTAG Serial Data In

TAPC0 JTAG Serial Data Out

TAPC0 JTAG Mode Select

TAPC0 JTAG Reset

MSI0 Card Detect

MSI0 Clock

Not Muxed

JTG_TCK_SWCLK

JTG_TMS_SWDIO

JTG_TDO_SWO

JTG_TCK_SWCLK

JTG_TDI

JTG_TDO_SWO

JTG_TMS_SWDIO

JTG_TRST

PA_08

Not Muxed

JTG_TDI

Not Muxed

JTG_TDO

JTG_TMS

JTG_TRST

MSI0_CD

MSI0_CLK

MSI0_CMD

MSI0_D0

Not Muxed

A

C

A

B

C

A

B

PC_09

MSI0 Command

MSI0 Data 0

PC_05

PC_08

MSI0_D1

MSI0 Data 1

PC_04

MSI0_D2

MSI0 Data 2

PC_07

MSI0_D3

MSI0 Data 3

PC_06

MSI0_D4

MSI0 Data 4

PC_10

PA_00-PA_15

PB_00-PB_15

PC_00-PC_10

PPI0_CLK

PPI0_D00

PPI0_D01

PPI0_D02

PPI0_D03

PPI0_D04

PPI0_D05

PPI0_D06

PPI0_D07

Position 00 through Position 15

Position 00 through Position 10

EPPI0 Clock

PA_00-PA_15

PB_00-PB_15

PC_00-PC_10

PA_14

EPPI0 Data 0

PB_07

EPPI0 Data 1

PB_06

EPPI0 Data 2

PB_05

EPPI0 Data 3

PB_04

EPPI0 Data 4

PB_03

EPPI0 Data 5

PB_02

EPPI0 Data 6

PB_01

EPPI0 Data 7

PB_00

Rev. A

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Table 11. ADSP-BF70x 12 mm × 12 mm 88-Lead LFCSP (QFN) Signal Descriptions (Continued)

Signal Name

PPI0_D08

Description

EPPI0 Data 8

Port

A

Pin Name

PA_11

PA_10

PA_09

PA_08

PC_03

PC_02

PC_01

PC_00

PB_08

PB_09

PA_12

PA_13

PA_15

RTC0_CLKIN

RTC0_XTAL

PA_08

PA_09

PA_10

PA_11

PA_07

PA_06

PA_05

PA_04

PC_01

PC_02

PC_03

PC_04

PA_00

PA_01

PA_15

PA_02

PA_12

PA_03

PA_13

PA_14

PB_07

PB_06

PB_05

PB_04

PB_03

PB_02

PB_01

PB_00

PB_08

PB_09

PB_10

PPI0_D09

EPPI0 Data 9

A

PPI0_D10

EPPI0 Data 10

A

PPI0_D11

EPPI0 Data 11

A

PPI0_D12

EPPI0 Data 12

C

PPI0_D13

EPPI0 Data 13

C

PPI0_D14

EPPI0 Data 14

C

PPI0_D15

EPPI0 Data 15

C

PPI0_D16

EPPI0 Data 16

B

PPI0_D17

EPPI0 Data 17

B

PPI0_FS1

EPPI0 Frame Sync 1 (HSYNC)

EPPI0 Frame Sync 2 (VSYNC)

EPPI0 Frame Sync 3 (FIELD)

RTC0 Crystal input/external oscillator connection

RTC0 Crystal output

SMC0 Address 1

SMC0 Address 2

SMC0 Address 3

SMC0 Address 4

SMC0 Address 5

SMC0 Address 6

SMC0 Address 7

SMC0 Address 8

SMC0 Address 9

SMC0 Address 10

SMC0 Address 11

SMC0 Address 12

SMC0 Byte Enable 0

SMC0 Byte Enable 1

SMC0 Memory Select 0

SMC0 Memory Select 1

SMC0 Output Enable

SMC0 Asynchronous Ready

SMC0 Read Enable

SMC0 Write Enable

SMC0 Data 0

A

PPI0_FS2

A

PPI0_FS3

A

RTC0_CLKIN

RTC0_XTAL

SMC0_A01

SMC0_A02

SMC0_A03

SMC0_A04

SMC0_A05

SMC0_A06

SMC0_A07

SMC0_A08

SMC0_A09

SMC0_A10

SMC0_A11

SMC0_A12

SMC0_ABE0

SMC0_ABE1

SMC0_AMS0

SMC0_AMS1

SMC0_AOE

SMC0_ARDY

SMC0_ARE

SMC0_AWE

SMC0_D00

SMC0_D01

SMC0_D02

SMC0_D03

SMC0_D04

SMC0_D05

SMC0_D06

SMC0_D07

SMC0_D08

SMC0_D09

SMC0_D10

Not Muxed

A

C

A

B

SMC0 Data 1

SMC0 Data 2

SMC0 Data 3

SMC0 Data 4

SMC0 Data 5

SMC0 Data 6

SMC0 Data 7

SMC0 Data 8

SMC0 Data 9

SMC0 Data 10

Rev. A

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ADSP-BF700/701/702/703/704/705/706/707

Table 11. ADSP-BF70x 12 mm × 12 mm 88-Lead LFCSP (QFN) Signal Descriptions (Continued)

Signal Name

SMC0_D11

SMC0_D12

SMC0_D13

SMC0_D14

SMC0_D15

SPI0_CLK

SPI0_D2

Description

SMC0 Data 11

Port

B

Pin Name

PB_11

PB_12

PB_13

PB_14

PB_15

PB_00

PC_04

PB_03

PC_08

PB_07

PC_09

PB_01

PC_06

PB_02

PC_07

PA_06

PA_05

PA_06

PB_04

PB_05

PB_06

PA_05

PA_00

PA_01

PA_02

PA_03

PA_04

PA_03

PC_10

PA_14

PA_04

PB_10

PB_13

PB_14

PB_11

PB_12

PA_04

PB_15

PB_08

PB_09

PB_15

PA_13

PC_09

PA_14

PC_08

PC_00

SMC0 Data 12

B

SMC0 Data 13

B

SMC0 Data 14

B

SMC0 Data 15

B

SPI0 Clock

B

SPI0 Clock

C

B

SPI0 Data 2

SPI0_D2

SPI0 Data 2

C

B

SPI0_D3

SPI0 Data 3

SPI0_D3

SPI0 Data 3

C

B

SPI0_MISO

SPI0_MOSI

SPI0_RDY

SPI0_SEL1

SPI0_SEL2

SPI0_SEL4

SPI0_SEL5

SPI0_SEL6

SPI0_SS

SPI0 Master In, Slave Out

SPI0 Master Out, Slave In

SPI0 Ready

C

B

C

A

B

SPI0 Slave Select Output 1

SPI0 Slave Select Output 2

SPI0 Slave Select Output 4

SPI0 Slave Select Output 5

SPI0 Slave Select Output 6

SPI0 Slave Select Input

SPI1 Clock

B

A

C

A

B

SPI1_CLK

SPI1_MISO

SPI1_MOSI

SPI1_RDY

SPI1_SEL1

SPI1_SEL2

SPI1_SEL3

SPI1_SEL4

SPI1_SS

SPI1 Master In, Slave Out

SPI1 Master Out, Slave In

SPI1 Ready

SPI1 Slave Select Output 1

SPI1 Slave Select Output 2

SPI1 Slave Select Output 3

SPI1 Slave Select Output 4

SPI1 Slave Select Input

SPI2 Clock

SPI2_CLK

SPI2_D2

SPI2 Data 2

B

SPI2_D3

SPI2 Data 3

B

SPI2_MISO

SPI2_MOSI

SPI2_RDY

SPI2_SEL1

SPI2_SEL2

SPI2_SEL3

SPI2_SS

SPI2 Master In, Slave Out

SPI2 Master Out, Slave In

SPI2 Ready

B

A

B

SPI2 Slave Select Output 1

SPI2 Slave Select Output 2

SPI2 Slave Select Output 3

SPI2 Slave Select Input

SPORT0 Channel A Clock

SPORT0 Channel A Data 0

SPORT0 Channel A Data 1

B

SPT0_ACLK

SPT0_AD0

SPT0_AD1

A

C

A

C

Rev. A

|

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ADSP-BF700/701/702/703/704/705/706/707

Table 11. ADSP-BF70x 12 mm × 12 mm 88-Lead LFCSP (QFN) Signal Descriptions (Continued)

Signal Name

SPT0_AFS

Description

Port

A

Pin Name

PA_12

SPORT0 Channel A Frame Sync

SPORT0 Channel A Transmit Data Valid

SPORT0 Channel B Clock

SPT0_AFS

C

PC_05

SPT0_ATDV

SPT0_BCLK

SPT0_BD0

SPT0_BD1

SPT0_BFS

A

PA_15

B

PB_04

SPORT0 Channel B Clock

C

PC_04

SPORT0 Channel B Data 0

SPORT0 Channel B Data 1

SPORT0 Channel B Frame Sync

SPORT0 Channel B Transmit Data Valid

SPORT1 Channel A Clock

B

PB_05

C

PC_06

B

PB_07

C

PC_01

B

PB_06

SPT0_BFS

C

PC_07

SPT0_BTDV

SPT1_ACLK

SPT1_AD0

SPT1_AD1

SPT1_AFS

A

PA_15

A

PA_08

SPORT1 Channel A Data 0

SPORT1 Channel A Data 1

SPORT1 Channel A Frame Sync

SPORT1 Channel A Transmit Data Valid

SPORT1 Channel B Clock

A

PA_10

A

PA_11

A

PA_09

SPT1_ATDV

SPT1_BCLK

SPT1_BD0

SPT1_BD1

SPT1_BFS

A

PA_07

B

PB_00

SPORT1 Channel B Clock

C

PC_10

SPORT1 Channel B Data 0

SPORT1 Channel B Data 1

SPORT1 Channel B Frame Sync

SPORT1 Channel B Transmit Data Valid

Boot Mode Control 0

B

PB_02

B

PB_03

B

PB_01

SPT1_BTDV

SYS_BMODE0

SYS_BMODE1

SYS_CLKIN

SYS_CLKOUT

SYS_EXTWAKE

SYS_FAULT

SYS_HWRST

SYS_NMI

A

PA_07

Not Muxed

SYS_BMODE0

SYS_BMODE1

SYS_CLKIN

SYS_CLKOUT

SYS_EXTWAKE

SYS_FAULT

SYS_HWRST

SYS_NMI

SYS_RESOUT

PB_07

Boot Mode Control 1

Not Muxed

Clock/Crystal Input

Not Muxed

Processor Clock Output

Not Muxed

External Wake Control

Not Muxed

Active-Low Fault Output

Not Muxed

Processor Hardware Reset Control

Non-maskable Interrupt

Not Muxed

SYS_RESOUT

SYS_WAKE0

SYS_WAKE1

SYS_WAKE2

SYS_WAKE3

SYS_WAKE4

SYS_XTAL

Reset Output

Not Muxed

Power Saving Mode Wake-up 0

Power Saving Mode Wake-up 1

Power Saving Mode Wake-up 2

Power Saving Mode Wake-up 3

Power Saving Mode Wake-up 4

Crystal Output

B

PB_08

B

PB_12

C

PC_02

A

PA_12

Not Muxed

SYS_XTAL

PC_03

TM0_ACI0

TM0_ACI1

TM0_ACI2

TM0_ACI3

TM0_ACI4

TM0_ACI5

TM0_ACI6

TM0_ACLK0

TIMER0 Alternate Capture Input 0

TIMER0 Alternate Capture Input 1

TIMER0 Alternate Capture Input 2

TIMER0 Alternate Capture Input 3

TIMER0 Alternate Capture Input 4

TIMER0 Alternate Capture Input 5

TIMER0 Alternate Capture Input 6

TIMER0 Alternate Clock 0

C

B

C

B

C

A

C

PB_01

PC_07

PB_09

PC_01

PC_02

PA_12

PC_04

Rev. A

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ADSP-BF700/701/702/703/704/705/706/707

Table 11. ADSP-BF70x 12 mm × 12 mm 88-Lead LFCSP (QFN) Signal Descriptions (Continued)

Signal Name

TM0_ACLK1

TM0_ACLK2

TM0_ACLK3

TM0_ACLK4

TM0_ACLK5

TM0_ACLK6

TM0_CLK

Description

Port

C

Pin Name

PC_10

TIMER0 Alternate Clock 1

TIMER0 Alternate Clock 2

TIMER0 Alternate Clock 3

TIMER0 Alternate Clock 4

TIMER0 Alternate Clock 5

TIMER0 Alternate Clock 6

TIMER0 Clock

C

PC_09

B

PB_00

B

PB_10

A

PA_14

B

PB_04

B

PB_06

TM0_TMR0

TM0_TMR1

TM0_TMR2

TM0_TMR3

TM0_TMR4

TM0_TMR5

TM0_TMR6

TM0_TMR7

TRACE0_CLK

TRACE0_D00

TRACE0_D01

TRACE0_D02

TRACE0_D03

TRACE0_D04

TRACE0_D05

TRACE0_D06

TRACE0_D07

TWI0_SCL

TIMER0 Timer 0

A

PA_05

TIMER0 Timer 1

A

PA_06

TIMER0 Timer 2

A

PA_07

TIMER0 Timer 3

C

PC_05

TIMER0 Timer 4

A

PA_09

TIMER0 Timer 5

A

PA_10

TIMER0 Timer 6

A

PA_11

TIMER0 Timer 7

A

PA_04

TPIU0 Trace Clock

TPIU0 Trace Data 0

TPIU0 Trace Data 1

TPIU0 Trace Data 2

TPIU0 Trace Data 3

TPIU0 Trace Data 4

TPIU0 Trace Data 5

TPIU0 Trace Data 6

TPIU0 Trace Data 7

TWI0 Serial Clock

TWI0 Serial Data

UART0 Clear to Send

UART0 Request to Send

UART0 Receive

B

PB_10

B

PB_15

B

PB_14

B

PB_13

B

PB_12

B

PB_11

A

PA_02

A

PA_01

A

PA_00

Not Muxed

C

TWI0_SCL

TWI0_SDA

PC_03

TWI0_SDA

UART0_CTS

UART0_RTS

UART0_RX

UART0_TX

UART1_CTS

UART1_RTS

UART1_RX

UART1_TX

USB0_CLKIN

USB0_DM

C

PC_02

B

PB_09

UART0 Transmit

B

PB_08

UART1 Clear to Send

UART1 Request to Send

UART1 Receive

B

PB_14

B

PB_13

C

PC_01

UART1 Transmit

C

PC_00

USB0 Clock/Crystal Input

USB0 Data –

Not Muxed

USB0_CLKIN

USB0_DM

USB0_DP

USB0_ID

USB0_VBC

USB0_VBUS

USB0_XTAL

VDD_EXT

VDD_INT

VDD_OTP

VDD_RTC

VDD_USB

USB0_DP

USB0 Data +

USB0_ID

USB0 OTG ID

USB0_VBC

USB0_VBUS

USB0_XTAL

VDD_EXT

USB0 VBUS Control

USB0 Bus Voltage

USB0 Crystal

External VDD

VDD_INT

Internal VDD

VDD_OTP

VDD for OTP

VDD_RTC

VDD for RTC

VDD_USB

VDD for USB

Rev. A

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Page 35 of 116

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September 2015

ADSP-BF700/701/702/703/704/705/706/707

GPIO MULTIPLEXING FOR 12 mm × 12 mm 88-LEAD LFCSP (QFN)

Table 12 through Table 14 identify the pin functions that are

multiplexed on the general-purpose I/O pins of the 

12 mm  12 mm 88-Lead LFCSP (QFN) package.

Table 12. Signal Multiplexing for Port A

Multiplexed

Function 0

Multiplexed

Function 1

Multiplexed

Function 2

TRACE0_D07

TRACE0_D06

TRACE0_D05

Multiplexed

Function 3

Multiplexed

Function Input Tap

Signal Name

PA_00

PA_01

PA_02

PA_03

PA_04

PA_05

PA_06

PA_07

PA_08

PA_09

PA_10

PA_11

PA_12

SPI1_CLK

SPI1_MISO

SPI1_MOSI

SPI1_SEL2

SPI1_SEL1

TM0_TMR0

TM0_TMR1

TM0_TMR2

PPI0_D11

PPI0_D10

PPI0_D09

PPI0_D08

PPI0_FS1

SMC0_ABE0

SMC0_ABE1

SMC0_AMS1

SMC0_ARDY

SMC0_A08

SMC0_A07

SMC0_A06

SMC0_A05

SMC0_A01

SMC0_A02

SMC0_A03

SMC0_A04

SMC0_AOE

SPI1_RDY

TM0_TMR7

SPI0_SEL1

SPI0_SEL2

SPT1_BTDV

MSI0_CD

SPI2_RDY

SPI1_SS

SPI0_SS

SPI0_RDY

SPT1_ATDV

SPT1_ACLK

SPT1_AFS

SPT1_AD0

SPT1_AD1

SPT0_AFS

CNT0_DG

TM0_TMR4

TM0_TMR5

TM0_TMR6

CAN1_RX

TM0_ACI6/SYS_

WAKE4

PA_13

PA_14

PA_15

PPI0_FS2

PPI0_CLK

PPI0_FS3

CAN1_TX

SPI1_SEL4

SPT0_ATDV

SPT0_ACLK

SPT0_AD0

SPT0_BTDV

SMC0_ARE

SMC0_AWE

SMC0_AMS0

CNT0_ZM

TM0_ACLK5

CNT0_UD

Table 13. Signal Multiplexing for Port B

Multiplexed

Function 1

Multiplexed

Function 2

SPI0_CLK

Multiplexed

Function 3

Multiplexed

Function Input Tap

TM0_ACLK3

TM0_ACI1

Signal Name

PB_00

PB_01

PB_02

PB_03

PB_04

PB_05

PB_06

PB_07

PB_08

PB_09

PB_10

PB_11

PB_12

PB_13

PB_14

PB_15

Function 0

PPI0_D07

PPI0_D06

PPI0_D05

PPI0_D04

PPI0_D03

PPI0_D02

PPI0_D01

PPI0_D00

UART0_TX

UART0_RX

SPI2_CLK

SPI2_MISO

SPI2_MOSI

SPI2_D2

SPT1_BCLK

SPT1_BFS

SPT1_BD0

SPT1_BD1

SPT0_BCLK

SPT0_BD0

SPT0_BFS

SPT0_BD1

PPI0_D16

PPI0_D17

SMC0_D07

SMC0_D06

SMC0_D05

SMC0_D04

SMC0_D03

SMC0_D02

SMC0_D01

SMC0_D00

SMC0_D08

SMC0_D09

SMC0_D10

SMC0_D11

SMC0_D12

SMC0_D13

SMC0_D14

SMC0_D15

SPI0_MISO

SPI0_MOSI

SPI0_D2

SPI0_SEL4

SPI0_SEL5

SPI0_SEL6

SPI0_D3

TM0_ACLK6

TM0_CLK

SYS_WAKE0

SYS_WAKE1

TM0_ACI3

TM0_ACLK4

SPI2_SEL2

SPI2_SEL3

TRACE0_CLK

TRACE0_D04

TRACE0_D03

TRACE0_D02

TRACE0_D01

TRACE0_D00

SYS_WAKE2

SPI2_SS

UART1_RTS

UART1_CTS

SPI2_D3

SPI2_SEL1

Rev. A

|

Page 36 of 116

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September 2015

ADSP-BF700/701/702/703/704/705/706/707

Table 14. Signal Multiplexing for Port C

Multiplexed

Function 1

SPT0_AD1

SPT0_BD1

CAN0_RX

Multiplexed

Function 2

PPI0_D15

PPI0_D14

PPI0_D13

Multiplexed

Function 3

Multiplexed

Function Input Tap

Signal Name

PC_00

Function 0

UART1_TX

UART1_RX

UART0_RTS

PC_01

SMC0_A09

SMC0_A10

TM0_ACI4

PC_02

TM0_ACI5/SYS_

WAKE3

PC_03

PC_04

PC_05

PC_06

PC_07

PC_08

PC_09

PC_10

UART0_CTS

SPT0_BCLK

SPT0_AFS

SPT0_BD0

SPT0_BFS

SPT0_AD0

SPT0_ACLK

SPT1_BCLK

CAN0_TX

SPI0_CLK

TM0_TMR3

SPI0_MISO

SPI0_MOSI

SPI0_D2

PPI0_D12

MSI0_D1

MSI0_CMD

MSI0_D3

MSI0_D2

MSI0_D0

MSI0_CLK

SPI1_SEL3

SMC0_A11

SMC0_A12

TM0_ACI0

TM0_ACLK0

TM0_ACI2

SPI0_D3

TM0_ACLK2

TM0_ACLK1

MSI0_D4

Rev. A

|

Page 37 of 116

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September 2015

ADSP-BF700/701/702/703/704/705/706/707

ADSP-BF70x DESIGNER QUICK REFERENCE

Table 15 provides a quick reference summary of pin related

information for circuit board design. The columns in this table

provide the following information:

• Power Domain: The Power Domain column in the table

specifies the power supply domain in which the signal

resides.

• Signal Name: The Signal Name column in the table

includes the signal name for every pin and (where applica-

ble) the GPIO multiplexed pin function for every pin.

• Pin Type: The Type column in the table identifies the I/O

type or supply type of the pin. The abbreviations used in

this column are na (none), I/O (input/output), a (analog), s

(supply), and g (ground).

• Driver Type: The Driver Type column in the table identi-

fies the driver type used by the pin. The driver types are

defined in the output drive currents section of this data

sheet.

• Internal Termination: The Int Term column in the table

specifies the termination present when the processor is not

in the reset or hibernate state. The abbreviations used in

this column are wk (weak keeper, weakly retains previous

value driven on the pin), pu (pull-up), or pd (pull-down).

• Reset Termination: The Reset Term column in the table

specifies the termination present when the processor is in

the reset state. The abbreviations used in this column are

wk (weak keeper, weakly retains previous value driven on

the pin), pu (pull-up), or pd (pull-down).

• Reset Drive: The Reset Drive column in the table specifies

the active drive on the signal when the processor is in the

reset state.

• Hibernate Termination: The Hiber Term column in the

table specifies the termination present when the processor

is in the hibernate state. The abbreviations used in this col-

umn are wk (weak keeper, weakly retains previous value

driven on the pin), pu (pull-up), or pd (pull-down).

• Hibernate Drive: The Hiber Drive column in the table

specifies the active drive on the signal when the processor is

in the hibernate state.

• Description and Notes: The Description and Notes column

in the table identifies any special requirements or charac-

teristics for the signal. If no special requirements are listed

the signal may be left unconnected if it is not used. Also, for

multiplexed general-purpose I/O pins, this column identi-

fies the functions available on the pin.

If an external pull-up or pull-down resistor is required for any

signal, 100 kΩ is the maximum value that can be used unless

otherwise noted.

Note that for Port A, Port B, and Port C (PA_00 to PC_14),

when SYS_HWRST is low, these pads are three-state. After 

SYS_HWRST is released, but before code execution begins,

these pins are internally pulled up. Subsequently, the state

depends on the input enable and output enable which are

controlled by software.

Software control of internal pull-ups works according to the

following settings in the PADS_PCFG0 register. When 

PADS_PCFG0 = 0: For PA_15:PA_00, PB_15:PB_00, and 

PC_14:PC_00, the internal pull-up is enabled when both the

input enable and output enable of a particular pin are 

deasserted. When PADS_PCFG0 = 1: For PA_15:PA_00, 

PB_15:PB_00, and PC_14:PC_00, the internal pull-up is

enabled as long as the output enable of a particular pin is 

deasserted.

There are some exceptions to this scheme:

• Internal pull-ups are always disabled if MSI mode is

selected for that signal.

• The following signals enabled the internal pull-down when

the output enable is de-asserted: SMC0_AMS[1:0], 

SMC0_ARE, SMC0_AWE, SMC0_AOE, SMC0_ARDY,

SPI0_SEL[6:1], SPI1_SEL[4:1], and SPI2_SEL[3:1].

Table 15. ADSP-BF70x Designer Quick Reference

Driver

Type

Int 

Term

Reset

Term

Reset

Drive

Hiber

Term

Hiber

Drive

Power

Domain

Description

and Notes

Signal Name Type

DMC0_A00

DMC0_A01

DMC0_A02

DMC0_A03

DMC0_A04

DMC0_A05

I/O

B

none

VDD_DMC

Desc: DMC0 Address 0

Notes: No notes.

Desc: DMC0 Address 1

Notes: No notes.

Desc: DMC0 Address 2

Notes: No notes.

Desc: DMC0 Address 3

Notes: No notes.

Desc: DMC0 Address 4

Notes: No notes.

Desc: DMC0 Address 5

Notes: No notes.

Rev. A

|

Page 38 of 116

|

September 2015

ADSP-BF700/701/702/703/704/705/706/707

Table 15. ADSP-BF70x Designer Quick Reference (Continued)

Driver

Type

Int 

Term

Reset

Term

Reset

Drive

Hiber

Term

Hiber

Drive

Power

Domain

Description

and Notes

Signal Name Type

DMC0_A06

DMC0_A07

DMC0_A08

DMC0_A09

DMC0_A10

DMC0_A11

DMC0_A12

DMC0_A13

DMC0_BA0

DMC0_BA1

DMC0_BA2

DMC0_CAS

DMC0_CK

I/O

B

C

B

none

L

none

L

VDD_DMC

Desc: DMC0 Address 6

Notes: No notes.

Desc: DMC0 Address 7

Notes: No notes.

Desc: DMC0 Address 8

Notes: No notes.

Desc: DMC0 Address 9

Notes: No notes.

Desc: DMC0 Address 10

Notes: No notes.

Desc: DMC0 Address 11

Notes: No notes.

Desc: DMC0 Address 12

Notes: No notes.

Desc: DMC0 Address 13

Notes: No notes.

Desc: DMC0 Bank Address Input 0

Notes: No notes.

Desc: DMC0 Bank Address Input 1

Notes: No notes.

Desc: DMC0 Bank Address Input 2

Notes: For LPDDR, leave unconnected.

Desc: DMC0 Column Address Strobe

Notes: No notes.

Desc: DMC0 Clock

Notes: No notes.

DMC0_CK

L

Desc: DMC0 Clock (complement)

Notes: No notes.

DMC0_CKE

DMC0_CS0

DMC0_DQ00

DMC0_DQ01

DMC0_DQ02

DMC0_DQ03

DMC0_DQ04

DMC0_DQ05

DMC0_DQ06

DMC0_DQ07

L

Desc: DMC0 Clock enable

Notes: No notes.

none

Desc: DMC0 Chip Select 0

Notes: No notes.

Desc: DMC0 Data 0

Notes: No notes.

Desc: DMC0 Data 1

Notes: No notes.

Desc: DMC0 Data 2

Notes: No notes.

Desc: DMC0 Data 3

Notes: No notes.

Desc: DMC0 Data 4

Notes: No notes.

Desc: DMC0 Data 5

Notes: No notes.

Desc: DMC0 Data 6

Notes: No notes.

Desc: DMC0 Data 7

Notes: No notes.

Rev. A

|

Page 39 of 116

|

September 2015

ADSP-BF700/701/702/703/704/705/706/707

Table 15. ADSP-BF70x Designer Quick Reference (Continued)

Driver

Type

Int 

Term

Reset

Term

Reset

Drive

Hiber

Term

Hiber

Drive

Power

Domain

Description

and Notes

Signal Name Type

DMC0_DQ08

DMC0_DQ09

DMC0_DQ10

DMC0_DQ11

DMC0_DQ12

DMC0_DQ13

DMC0_DQ14

DMC0_DQ15

DMC0_LDM

DMC0_LDQS

I/O

B

C

none

VDD_DMC

Desc: DMC0 Data 8

Notes: No notes.

Desc: DMC0 Data 9

Notes: No notes.

Desc: DMC0 Data 10

Notes: No notes.

Desc: DMC0 Data 11

Notes: No notes.

Desc: DMC0 Data 12

Notes: No notes.

Desc: DMC0 Data 13

Notes: No notes.

Desc: DMC0 Data 14

Notes: No notes.

Desc: DMC0 Data 15

Notes: No notes.

Desc: DMC0 Data Mask for Lower Byte

Notes: No notes.

Desc: DMC0 Data Strobe for Lower Byte

Notes: For LPDDR, a pull-down is

required.

DMC0_LDQS

I/O

C

none

VDD_DMC

Desc: DMC0 Data Strobe for Lower Byte

(complement)

Notes: For single ended DDR2, connect

to DMC0_VREF. For LPDDR, leave

unconnected.

DMC0_ODT

DMC0_RAS

DMC0_UDM

I/O

B

C

none

VDD_DMC

Desc: DMC0 On-die termination

Notes: For LPDDR, leave unconnected.

Desc: DMC0 Row Address Strobe

Notes: No notes.

Desc: DMC0 Data Mask for Upper Byte

Notes: No notes.

DMC0_UDQS I/O

Desc: DMC0 Data Strobe for Upper Byte

Notes: For LPDDR, a pull-down is

required.

C

none

VDD_DMC

Desc: DMC0 Data Strobe for Upper Byte

(complement)

Notes: For single ended DDR2, connect

to DMC0_VREF. For LPDDR, leave

unconnected.

DMC0_VREF

a

na

Desc: DMC0 Voltage Reference

Notes: For LPDDR, leave unconnected.

If the DMC is not used, connect to

ground.

DMC0_WE

GND

I/O

g

B

none

VDD_DMC

na

Desc: DMC0 Write Enable

Notes: No notes.

Desc: Ground

na

Notes: No notes.

Rev. A

|

Page 40 of 116

|

September 2015

ADSP-BF700/701/702/703/704/705/706/707

Table 15. ADSP-BF70x Designer Quick Reference (Continued)

Driver

Type

Int 

Term

Reset

Term

Reset

Drive

Hiber

Term

Hiber

Drive

Power

Domain

Description

and Notes

Signal Name Type

GND_HADC

HADC0_VIN0

HADC0_VIN1

HADC0_VIN2

HADC0_VIN3

g

a

na

none

na

Desc: Ground HADC

Notes: If HADC is not used, connect to

ground.

VDD_HADC Desc: HADC0 Analog Input at channel 0

Notes: If HADC is not used, connect to

ground.

VDD_HADC Desc: HADC0 Analog Input at channel 1

Notes: If HADC is not used, connect to

ground.

VDD_HADC Desc: HADC0 Analog Input at channel 2

Notes: If HADC is not used, connect to

ground.

VDD_HADC Desc: HADC0 Analog Input at channel 3

Notes: If HADC is not used, connect to

ground.

HADC0_VREFN a

HADC0_VREFP a

VDD_HADC Desc: HADC0 Ground Reference for

ADC

Notes: If HADC is not used, connect to

ground.

na

none

VDD_HADC Desc: HADC0 External Reference for

ADC

Notes: If HADC is not used, connect to

ground.

JTG_TCK_

SWCLK

I/O

na

A

pd

none

VDD_EXT

Desc: JTAG Clock | Serial Wire Clock

Notes: Functional during reset.

Desc: JTAG Serial Data In

JTG_TDI

pu

Notes: Functional during reset.

JTG_TDO_SWO I/O

none

Desc: JTAG Serial Data Out | Serial Wire

Out

Notes: Functional during reset, three-

state when JTG_TRST is asserted.

JTG_TMS_

SWDIO

I/O

A

pu

pd

none

VDD_EXT

Desc: JTAG Mode Select | Serial Wire DIO

Notes: Functional during reset.

JTG_TRST

na

Desc: JTAG Reset

Notes: Functional during reset, a 10k

external pull-down may be used to

shorten the t_{VDDEXT_RST}timing

requirement.

PA_00

I/O

A

none

VDD_EXT

Desc: SPI1 Clock | TRACE0 Trace Data 7 |

SMC0 Byte Enable 0

Notes: SPI clock requires a pull-down

when controlling most SPI flash

devices.

PA_01

Desc: SPI1 Master In, Slave Out | TRACE0

Trace Data 6 | SMC0 Byte Enable 1

Notes: Pull-up required for SPI_MISO if

SPI master boot is used.

Rev. A

|

Page 41 of 116

|

September 2015

ADSP-BF700/701/702/703/704/705/706/707

Table 15. ADSP-BF70x Designer Quick Reference (Continued)

Driver

Type

Int 

Term

Reset

Term

Reset

Drive

Hiber

Term

Hiber

Drive

Power

Domain

Description

and Notes

Signal Name Type

PA_02

I/O

A

none

VDD_EXT

Desc: SPI1 Master Out, Slave In | TRACE0

Trace Data 5 | SMC0 Memory Select 1

Notes: May require a pull-up if used as

an SMC memory select. Check the data

sheetrequirementsofthe ICit connects

to.

PA_03

I/O

A

none

VDD_EXT

Desc: SPI1 Slave Select Output 2 | SPI1

Ready | SMC0 Asynchronous Ready

Notes: May require a pull-up or pull-

down if used as an SMC asynchronous

ready. Check the data sheet require-

ments of the IC it connects to and the

programmed polarity.

PA_04

PA_05

I/O

A

none

VDD_EXT

Desc: SPI1 Slave Select Output 1 | TM0

Timer 7 | SPI2 Ready | SMC0 Address 8 |

SPI1 Slave Select Input

Notes: SPI slave select outputs require a

pull-up when used.

Desc: TM0 Timer 0 | SPI0 Slave Select

Output 1 | SMC0 Address 7 | SPI0 Slave

Select Input

Notes: SPI slave select outputs require a

pull-up when used.

PA_06

PA_07

I/O

A

none

VDD_EXT

Desc: TM0 Timer 1 | SPI0 Slave Select

Output 2 | SPI0 Ready | SMC0 Address 6

Notes: SPI slave select outputs require a

pull-up when used.

Desc: TM0 Timer 2 | SPT1 Channel B

Transmit Data Valid | SPT1 Channel A

Transmit Data Valid | SMC0 Address 5 |

CNT0 Count Down and Gate

Notes: No notes.

PA_08

I/O

A

none

VDD_EXT

Desc: PPI0 Data 11 | MSI0 Card Detect |

SPT1 Channel A Clock | SMC0 Address 1

Notes: An external pull-up may be

required for MSI modes, see the MSI

chapter in the hardware reference for

details.

PA_09

PA_10

PA_11

I/O

A

none

VDD_EXT

Desc: PPI0 Data 10 | TM0 Timer 4 | SPT1

Channel A Frame Sync | SMC0 Address 2

Notes: No notes.

Desc: PPI0 Data 9 | TM0 Timer 5 | SPT1

Channel A Data 0 | SMC0 Address 3

Notes: No notes.

Desc: PPI0 Data 8 | TM0 Timer 6 | SPT1

Channel A Data 1 | SMC0 Address 4

Notes: No notes.

Rev. A

|

Page 42 of 116

|

September 2015

ADSP-BF700/701/702/703/704/705/706/707

Table 15. ADSP-BF70x Designer Quick Reference (Continued)

Driver

Type

Int 

Term

Reset

Term

Reset

Drive

Hiber

Term

Hiber

Drive

Power

Domain

Description

and Notes

Signal Name Type

PA_12

I/O

A

none

VDD_EXT

Desc:PPI0FrameSync1(HSYNC)|CAN1

Receive|SPORT0ChannelAFrameSync

|SMC0 Output Enable |SYS Power

Saving Mode Wakeup 4 | TM0 Alternate

Capture Input 6

Notes: If hibernate mode is used one of

the following must be true during

hibernate. Either this pin must be

actively driven by another IC, or it must

have a pull-up or pull-down.

PA_13

PA_14

I/O

A

none

VDD_EXT

Desc: PPI0FrameSync2(VSYNC)|CAN1

Transmit | SPORT0 Channel A Clock |

SMC0 Read Enable | CNT0 Count Zero

Marker

Notes: No notes.

Desc: PPI0 Clock | SPI1 Slave Select

Output 4 | SPORT0 Channel A Data 0 |

SMC0 Write Enable | TM0 Alternate

Clock 5

Notes: SPI slave select outputs require a

pull-up when used.

PA_15

I/O

A

none

VDD_EXT

Desc: PPI0 Frame Sync 3 (FIELD) | SPT0

Channel A Transmit Data Valid | SPT0

Channel B Transmit Data Valid | SMC0

Memory Select 0 | CNT0 Count Up and

Direction

Notes: May require a pull-up if used as

an SMC memory select. Check the data

sheetrequirementsofthe ICitconnects

to.

PB_00

PB_01

I/O

A

none

VDD_EXT

Desc: PPI0Data7|SPT1Channel BClock

| SPI0 Clock | SMC0 Data 7 | TM0

Alternate Clock 3

Notes: SPI clock requires a pull-down

when controlling most SPI flash

devices.

Desc: PPI0 Data 6 | SPT1 Channel B

Frame Sync | SPI0 Master In, Slave Out |

SMC0 Data 6 | TM0 Alternate Capture

Input 1

Notes: Pull-up required for SPI_MISO if

SPI master boot is used.

PB_02

PB_03

I/O

A

none

VDD_EXT

Desc: PPI0 Data 5 | SPT1 Channel B Data

0 | SPI0 Master Out, Slave In | SMC0 Data

5

Notes: No notes.

Desc: PPI0 Data 4 | SPT1 Channel B Data

1 | SPI0 Data 2 | SMC0 Data 4

Notes: No notes.

Rev. A

|

Page 43 of 116

|

September 2015

ADSP-BF700/701/702/703/704/705/706/707

Table 15. ADSP-BF70x Designer Quick Reference (Continued)

Driver

Type

Int 

Term

Reset

Term

Reset

Drive

Hiber

Term

Hiber

Drive

Power

Domain

Description

and Notes

Signal Name Type

PB_04

PB_05

PB_06

PB_07

I/O

A

none

VDD_EXT

Desc: PPI0Data3|SPT0Channel BClock

| SPI0 Slave Select Output 4 | SMC0 Data

3 | TM0 Alternate Clock 6

Notes: SPI slave select outputs require a

pull-up when used.

Desc: PPI0 Data 2 | SPT0 Channel B Data

0 | SPI0 Slave Select Output 5 | SMC0

Data 2

Notes: SPI slave select outputs require a

pull-up when used.

Desc: PPI0 Data 1 | SPT0 Channel B

Frame Sync | SPI0 Slave Select Output 6

| SMC0 Data 1 | TM0 Clock

Notes: SPI slave select outputs require a

pull-up when used.

Desc: PPI0 Data 0 | SPT0 Channel B Data

1 | SPI0 Data 3 | SMC0 Data 0 | SYS Power

Saving Mode Wakeup 0

Notes: If hibernate mode is used, one of

the following must be true during

hibernate. Either this pin must be

actively driven by another IC, or it must

have a pull-up or pull-down.

PB_08

I/O

A

none

VDD_EXT

Desc: UART0 Transmit | PPI0 Data 16 |

SPI2 Slave Select Output 2 | SMC0 Data

8 | SYS Power Saving Mode Wakeup 1

Notes: SPI slave select outputs require a

pull-up when used. If hibernate mode is

used, one of the following must be true

during hibernate. Either this pin must

be actively driven by another IC, or it

must have a pull-up or pull-down.

PB_09

PB_10

PB_11

I/O

A

none

VDD_EXT

Desc: UART0 Receive | PPI0 Data 17 |

SPI2 Slave Select Output 3 | SMC0 Data

9 | TM0 Alternate Capture Input 3

Notes: SPI slave select outputs require a

pull-up when used.

Desc: SPI2 Clock | TRACE0 Trace Clock |

SMC0 Data 10 | TM0 Alternate Clock 4

Notes: SPI clock requires a pull-down

when controlling most SPI flash

devices.

Desc: SPI2 Master In, Slave Out | TRACE0

Trace Data 4 | SMC0 Data 11

Notes: Pull-up required for SPI_MISO if

SPI master boot is used.

Rev. A

|

Page 44 of 116

|

September 2015

ADSP-BF700/701/702/703/704/705/706/707

Table 15. ADSP-BF70x Designer Quick Reference (Continued)

Driver

Type

Int 

Term

Reset

Term

Reset

Drive

Hiber

Term

Hiber

Drive

Power

Domain

Description

and Notes

Signal Name Type

PB_12

I/O

A

none

VDD_EXT

Desc: SPI2 Master Out, Slave In | TRACE0

Trace Data 3 | SMC0 Data 12 | SYS Power

Saving Mode Wakeup 2

Notes: If hibernate mode is used, one of

the following must be true during

hibernate. Either this pin must be

actively driven by another IC, or it must

have a pull-up or pull-down.

PB_13

I/O

A

none

VDD_EXT

Desc: SPI2 Data 2 | UART1 Request to

Send | TRACE0 Trace Data 2 | SMC0 Data

13

Notes: No notes.

PB_14

PB_15

I/O

A

none

VDD_EXT

Desc: SPI2 Data 3 | UART1 Clear to Send

| TRACE0 Trace Data 1 | SMC0 Data 14

Notes: No notes.

Desc: SPI2 Slave Select Output 1 |

TRACE0 Trace Data 0 | SMC0 Data 15 |

SPI2 Slave Select Input

Notes: SPI slave select outputs require a

pull-up when used.

PC_00

PC_01

I/O

A

none

VDD_EXT

Desc: UART1 Transmit | SPT0 Channel A

Data 1 | PPI0 Data 15

Notes: No notes.

Desc: UART1 Receive | SPT0 Channel B

Data 1 | PPI0 Data 14 | SMC0 Address 9 |

TM0 Alternate Capture Input 4

Notes: No notes.

PC_02

I/O

A

none

VDD_EXT

Desc: UART0 Request to Send | CAN0

Receive | PPI0 Data 13 | SMC0 Address

10 | SYS Power Saving Mode Wakeup 3 |

TM0 Alternate Capture Input 5

Notes: If hibernate mode is used, one of

the following must be true during

hibernate. Either this pin must be

actively driven by another IC, or it must

have a pull-up or pull-down.

PC_03

PC_04

I/O

A

none

VDD_EXT

Desc: UART0 Clear to Send | CAN0

Transmit | PPI0 Data 12 | SMC0 Address

11 | TM0 Alternate Capture Input 0

Notes: No notes.

Desc: SPT0 Channel B Clock | SPI0 Clock

| MSI0 Data 1 | SMC0 Address 12 | TM0

Alternate Clock 0

Notes: An external pull-up may be

required for MSI modes, see the MSI

chapter in the hardware reference for

details.

Rev. A

|

Page 45 of 116

|

September 2015

ADSP-BF700/701/702/703/704/705/706/707

Table 15. ADSP-BF70x Designer Quick Reference (Continued)

Driver

Type

Int 

Term

Reset

Term

Reset

Drive

Hiber

Term

Hiber

Drive

Power

Domain

Description

and Notes

Signal Name Type

PC_05

PC_06

PC_07

I/O

A

none

VDD_EXT

Desc: SPT0 Channel A Frame Sync | TM0

Timer 3 | MSI0 Command

Notes: An external pull-up may be

required for MSI modes, see the MSI

chapter in the hardware reference for

details.

Desc: SPT0 Channel B Data 0 | SPI0

Master In, Slave Out | MSI0 Data 3

Notes: An external pull-up may be

required for MSI modes, see the MSI

chapter in the hardware reference for

details.

Desc: SPT0 Channel B Frame Sync | SPI0

Master Out, Slave In | MSI0 Data 2 | TM0

Alternate Capture Input 2

Notes: An external pull-up may be

required for MSI modes, see the MSI

chapter in the hardware reference for

details.

PC_08

I/O

A

none

VDD_EXT

Desc: SPT0 Channel A Data 0 | SPI0 Data

2 | MSI0 Data 0

Notes: An external pull-up may be

required for MSI modes, see the MSI

chapter in the hardware reference for

details.

PC_09

PC_10

I/O

A

none

VDD_EXT

Desc: SPT0 Channel A Clock | SPI0 Data

3 | MSI0 Clock | TM0 Alternate Clock 2

Notes: No notes.

Desc: SPT1 Channel B Clock | MSI0 Data

4 | SPI1 Slave Select Output 3 | TM0

Alternate Clock 1

Notes: An external pull-up may be

required for MSI modes, see the MSI

chapter in the hardware reference for

details. SPI slave select outputs require

a pull-up when used.

PC_11

PC_12

I/O

A

none

VDD_EXT

Desc: SPT1 Channel B Frame Sync | MSI0

Data 5 | SPI0 Slave Select Output 3

Notes: An external pull-up may be

required for MSI modes, see the MSI

chapter in the hardware reference for

details. SPI slave select outputs require

a pull-up when used.

Desc: SPT1 Channel B Data 0 | MSI0 Data

6

Notes: An external pull-up may be

required for MSI modes, see the MSI

chapter in the hardware reference for

details.

Rev. A

|

Page 46 of 116

|

September 2015

ADSP-BF700/701/702/703/704/705/706/707

Table 15. ADSP-BF70x Designer Quick Reference (Continued)

Driver

Type

Int 

Term

Reset

Term

Reset

Drive

Hiber

Term

Hiber

Drive

Power

Domain

Description

and Notes

Signal Name Type

PC_13

I/O

A

none

VDD_EXT

Desc: SPT1 Channel B Data 1 | MSI0 Data

7

Notes: An external pull-up may be

required for MSI modes, see the MSI

chapter in the hardware reference for

details.

PC_14

I/O

a

A

none

VDD_EXT

VDD_RTC

Desc: SPT1 Channel B Transmit Data

Valid | MSI0 eSDIO Interrupt Input

Notes: No notes.

RTC0_CLKIN

na

Desc: RTC0 Crystal input / external oscil-

lator connection

Notes: If RTC is not used, connect to

ground.

RTC0_XTAL

a

na

none

VDD_RTC

VDD_EXT

Desc: RTC0 Crystal output

Notes: No notes.

SYS_BMODE0 I/O

Desc: SYS Boot Mode Control 0

Notes: A pull-down is required for

setting to 0 and a pull-up is required for

setting to 1.

SYS_BMODE1 I/O

na

none

VDD_EXT

Desc: SYS Boot Mode Control 1

Notes: A pull-down is required for

setting to 0 and a pull-up is required for

setting to 1.

SYS_CLKIN

a

na

A

none

L

none

VDD_EXT

Desc: SYS Clock/Crystal Input

Notes: No notes.

SYS_CLKOUT

I/O

Desc: SYS Processor Clock Output

Notes: During reset, SYS_CLKOUT

drives out SYS_CLKIN Frequency.

SYS_EXTWAKE I/O

A

none

H

none

L

VDD_EXT

Desc: SYS External Wake Control

Notes: Drives low during hibernate and

high all other times including reset.

SYS_FAULT

I/O

A

none

Desc: SYS Complementary Fault Output

Notes: Open drain, requires an external

pull-up resistor.

SYS_HWRST

na

Desc: SYS Processor Hardware Reset

Control

Notes: Active during reset, must be

externally driven.

SYS_NMI

I/O

na

none

VDD_EXT

Desc: SYS Non-maskable Interrupt

Notes: Requires an external pull-up

resistor.

SYS_RESOUT

SYS_XTAL

I/O

a

A

none

L

none

VDD_EXT

Desc: SYS Reset Output

Notes: Active during reset.

na

none

Desc: SYS Crystal Output

Notes: Leave unconnected if an oscil-

lator is used to provide SYS_CLKIN.

Active during reset. State during

hibernate is controlled by DPM_HIB_

DIS.

Rev. A

|

Page 47 of 116

|

September 2015

ADSP-BF700/701/702/703/704/705/706/707

Table 15. ADSP-BF70x Designer Quick Reference (Continued)

Driver

Type

Int 

Term

Reset

Term

Reset

Drive

Hiber

Term

Hiber

Drive

Power

Domain

Description

and Notes

Signal Name Type

TWI0_SCL

I/O

D

none

VDD_EXT

Desc: TWI0 Serial Clock

Notes: Open drain, requires external

pull up. Consult version 2.1 of the I2C

specification for the proper resistor

value. If TWI is not used, connect to

ground.

TWI0_SDA

I/O

D

none

VDD_EXT

Desc: TWI0 Serial Data

Notes: Open drain, requires external

pull up. Consult version 2.1 of the I2C

specification for the proper resistor

value. If TWI is not used, connect to

ground.

USB0_CLKIN

USB0_DM

a

na

F

none

VDD_USB

Desc: USB0 Clock/Crystal Input

Notes: If USB is not used, connect to

ground. Active during reset

I/O

Desc: USB0 Data –

Notes: Pull low if not using USB. For

complete documentation of hibernate

behavior when USB is used, see the USB

chapter in the HRM.

USB0_DP

USB0_ID

I/O

F

none

VDD_USB

Desc: USB0 Data +

Notes: Pull low if not using USB. For

complete documentation of hibernate

behavior when USB is used, see the USB

chapter in the HRM.

na

Desc: USB0 OTG ID

Notes: If USB is not used connect to

ground. When USB is being used, the

internal pull-up that is present during

hibernate is programmable. See the

USB chapter in the HRM. Active during

reset.

USB0_VBC

I/O

E

none

VDD_USB

Desc: USB0 VBUS Control

Notes: If USB is not, used pull low.

USB0_VBUS

G

Desc: USB0 Bus Voltage

Notes: If USB is not used, connect to

ground.

USB0_XTAL

VDD_DMC

a

s

na

none

VDD_USB

na

Desc: USB0 Crystal

Notes: No notes.

Desc: VDD for DMC

Notes: If the DMC is not used, connect

to VDD_INT.

VDD_EXT

s

na

none

na

Desc: External VDD

Notes: Must be powered.

VDD_HADC

Desc: VDD for HADC

Notes: If HADC is not used, connect to

ground.

VDD_INT

s

na

none

na

Desc: Internal VDD

Notes: Must be powered.

Rev. A

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ADSP-BF700/701/702/703/704/705/706/707

Table 15. ADSP-BF70x Designer Quick Reference (Continued)

Driver

Type

Int 

Term

Reset

Term

Reset

Drive

Hiber

Term

Hiber

Drive

Power

Domain

Description

and Notes

Signal Name Type

VDD_OTP

s

na

none

na

Desc: VDD for OTP

Notes: Must be powered.

VDD_RTC

s

na

none

Desc: VDD for RTC

Notes: If RTC is not used, connect to

ground.

VDD_USB

s

na

none

na

Desc: VDD for USB

Notes: If USB is not used, connect to

VDD_EXT.

Rev. A

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ADSP-BF700/701/702/703/704/705/706/707

SPECIFICATIONS

For information about product specifications, contact your Analog Devices, Inc. representative.

OPERATING CONDITIONS

Parameter

Test Conditions/Comments Min

Nominal

1.100

1.8

Max

1.155

1.9

Unit

V

V_{DD_INT}

Internal Supply Voltage

External Supply Voltage

DDR2/LPDDR Supply Voltage

USB Supply Voltage

CCLK ≤ 400 MHz

1.045

1.7

1

V_{DD_EXT}

V

1

V_{DD_EXT}

3.13

1.7

3.30

3.47

1.9

V

V_{DD_DMC}

1.8

V

2

V_{DD_USB}

3.13

2.00

3.13

3.30

3.47

V

V_{DD_RTC}

Real-Time Clock Supply Voltage

3.30

V

V_{DD_HADC}

Housekeeping ADC Supply

Voltage

3.30

V

1

V_{DD_OTP}

OTP Supply Voltage

For Reads

2.25

3.30

3.47

V

°C

For Writes

3.13

3.30

3.47

V_{DDR_VREF}

DDR2 Reference Voltage

HADC Reference Voltage

High Level Input Voltage

0.49 × V_{DD_DMC}

2.5

0.50 × V_{DD_DMC}

3.30

0.51 × V_{DD_DMC}

V_{DD_HADC}

3

V_{HADC_REF}

4

V_IH

V_{DD_EXT}= 3.47 V

2.0

4

V_IH

V_{DD_EXT}= 1.9 V

0.7 × V_{DD_EXT}

0.7 × V_VBUSTWI

V_{DDR_REF}+ 0.25

0.8 × V_{DD_DMC}

0.50

5, 6

V_IHTWI

V_{DD_EXT}= maximum

V_{DD_DMC}= 1.9 V

V_VBUSTWI

7

V_{IH_DDR2}

8

V_{IH_LPDDR}

V_{DD_DMC}= 1.9 V

9

V_{ID_DDR2}

Differential Input Voltage

Low Level Input Voltage

V_IX= 1.075 V

9

V_{ID_DDR2}

V_IX= 0.725 V

0.55

4

V_IL

V_{DD_EXT}= 3.13 V

0.8

4

V_IL

V_{DD_EXT}= 1.7 V

0.3 × V_{DD_EXT}

0.3 × V_VBUSTWI

V_{DDR_REF}– 0.25

0.2 × V_{DD_DMC}

105

5, 6

V_ILTWI

V_{DD_EXT}= minimum

V_{DD_DMC}= 1.7 V

7

V_{IL_DDR2}

8

V_{IL_LPDDR}

V_{DD_DMC}= 1.7 V

T_J

Junction Temperature

T_AMBIENT= 0°C to +70°C

T_AMBIENT= –40°C to +85°C

T_AMBIENT= –40°C to +105°C

0

–40

+105

+125

¹Must remain powered (even if the associated function is not used).

²If not used, connect to 1.8 V or 3.3 V.

³V_{HADC_VREF}should always be less than V_{DD_HADC}

.

⁴Parameter value applies to all input and bidirectional signals except RTC signals, TWI signals, DMC0 signals, and USB0 signals.

⁵Parameter applies to TWI signals.

⁶TWI signals are pulled up to V_BUSTWI. See Table 16.

⁷Parameter applies to DMC0 signals in DDR2 mode.

⁸Parameter applies to DMC0 signals in LPDDR mode.

⁹Parameter applies to signals DMC0_LDQS, DMC0_LDQS, DMC0_UDQS, DMC0_UDQS when used in DDR2 differential input mode.

Rev. A

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ADSP-BF700/701/702/703/704/705/706/707

Table 16. TWI_VSEL Selections and V_{DD_EXT}/V_BUSTWI

TWI_DT Setting

TWI000¹

V_{DD_EXT}Nominal

V_BUSTWIMin

3.13

V_BUSTWINominal

V_BUSTWIMax

3.47

Unit

3.30

1.80

3.30

1.80

3.30

5.00

V

TWI001

1.70

1.90

TWI011

3.13

3.47

TWI100

4.75

5.25

¹Designs must comply with the V_{DD_EXT}and V_BUSTWIvoltages specified for the default TWI_DT setting for correct JTAG boundary scan operation during reset.

Clock Related Operating Conditions

Table 17 and Table 18 describe the core clock, system clock, and peripheral clock timing requirements. The data presented in the tables

applies to all speed grades (found in the Ordering Guide) except where expressly noted. Figure 6 provides a graphical representation of the

various clocks and their available divider values.

Table 17. Core and System Clock Operating Conditions

Parameter

Ratio Restriction

f_CCLK≥ f_SYSCLK

PLLCLK Restriction

PLLCLK = 800

Min

Max

400

Unit

MHz

f_CCLK

Core Clock Frequency

f_CCLK≥ f_SYSCLK

600 ≤ PLLCLK < 800

380 ≤ PLLCLK < 600

230.2 ≤ PLLCLK < 380

PLLCLK = 800

390

f_CCLK≥ f_SYSCLK

380

f_CCLK≥ f_SYSCLK

PLLCLK

200

f_SYSCLKSYSCLK Frequency¹

60

30

600 ≤ PLLCLK < 800

380 ≤ PLLCLK < 600

230.2 ≤ PLLCLK < 380

195

190

PLLCLK ÷ 2 MHz

f_SCLK0

f_SCLK1

f_DCLK

SCLK0 Frequency¹

f_SYSCLK≥ f_SCLK0

f_SYSCLK≥ f_SCLK1

f_SYSCLK≥ f_DCLK

100

200

MHz

SCLK1 Frequency

DDR2 Clock Frequency

125

10

LPDDR Clock Frequency

¹The minimum frequency for SYSCLK and SCLK0 applies only when the USB is used.

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ADSP-BF700/701/702/703/704/705/706/707

Table 18. Peripheral Clock Operating Conditions

Parameter

f_OCLK

Restriction

Min

Typ

Max

Unit

MHz

%

Output Clock Frequency

SYS_CLKOUT Period Jitter^{1, 2}

50

f_{SYS_CLKOUTJ}

f_PCLKPROG

f_PCLKEXT

2

Programmed PPI Clock When Transmitting Data and Frame Sync

Programmed PPI Clock When Receiving Data or Frame Sync

External PPI Clock When Receiving Data and Frame Sync^{3, 4}

External PPI Clock Transmitting Data or Frame Sync^{3, 4}

Programmed SPT Clock When Transmitting Data and Frame Sync

Programmed SPT Clock When Receiving Data or Frame Sync

External SPT Clock When Receiving Data and Frame Sync^{3, 4}

External SPT Clock Transmitting Data or Frame Sync^{3, 4}

Programmed SPI Clock When Transmitting Data

Programmed SPI Clock When Receiving Data

External SPI Clock When Receiving Data^{3, 4}

50

MHz

f_PCLKEXT≤ f_SCLK0

f_PCLKEXT

f_SPTCLKPROG

f_SPTCLKEXT

f_SPICLKPROG

f_SPICLKEXT

f_MSICLKPROG

f_SPTCLKEXT≤ f_SCLK0

f_SPICLKEXT≤ f_SCLK0

External SPI Clock When Transmitting Data^{3, 4}

Programmed MSI Clock

¹SYS_CLKOUT jitter is dependent on the application system design including pin switching activity, board layout, and the jitter characteristics of the SYS_CLKIN source. Due

to the dependency on these factors the measured jitter may be higher or lower than this typical specification for each end application.

²The value in the Typ field is the percentage of the SYS_CLKOUT period.

³The maximum achievable frequency for any peripheral in external clock mode is dependent on being able to meet the setup and hold times in the ac timing specifications

section for that peripheral. Pay particular attention to setup and hold times for VDD_EXT = 1.8 V which may preclude the maximum frequency listed here.

⁴The peripheral external clock frequency must also be less than or equal to the f_SCLKthat clocks the peripheral.

CSEL

CCLK

(1-32)

SCLK0

S0SEL

(1 8)

(ALL OTHER PERIPHERALS)

-

SYSCLK

SYSSEL

(1 32)

-

SYS_CLKIN

PLLCLK

PLL

SCLK1

S1SEL

(1 8)

(MDMA1, MDMA2, CRYPTOGRAPHIC ACCELERATORS)

-

DSEL

(1 32)

DCLK

-

OSEL

(1 128)

OCLK

-

Figure 6. Clock Relationships and Divider Values

Table 19. Phase-Locked Loop Operating Conditions

Parameter

f_PLLCLK

CGU_CTL.MSEL¹

Min

230.2

8

Max

800

41

Unit

MHz

PLL Clock Frequency

PLL Multiplier

¹The CGU_CTL.MSEL setting must also be chosen to ensure that the f_PLLCLKspecification is not violated.

Rev. A

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September 2015

ADSP-BF700/701/702/703/704/705/706/707

ELECTRICAL CHARACTERISTICS

Parameter

Test Conditions/Comments

V_{DD_EXT}= 1 . 7 V, I _OH= –1.0 mA

V_{DD_EXT}= 3 . 13 V, I_OH= –2.0 mA

Min

Typ

Max

Unit

1

V_OH

High Level Output Voltage

0.8 × V_{DD_EXT}

0.9 × V_{DD_EXT}

V_{DD_DMC}– 0.320

V

1

2

V_{OH_DDR2}

High Level Output Voltage, DDR2, V_{DD_DMC}= 1.70 V, I_OH= –7.1 mA

Programmed Impedance = 34 Ω

High Level Output Voltage, DDR2, V_{DD_DMC}= 1.70 V, I_OH= –5.8 mA

Programmed Impedance = 40 Ω

High Level Output Voltage, DDR2, V_{DD_DMC}= 1.70 V, I_OH= –4.1 mA

Programmed Impedance = 50 Ω

High Level Output Voltage, DDR2, V_{DD_DMC}= 1.70 V, I_OH= –3.4 mA

Programmed Impedance = 60 Ω

V_{DD_DMC}– 0.320

V

2

V_{OH_LPDDR}

High Level Output Voltage, LPDDR V_{DD_DMC}= 1.70 V, I_OH= –2.0 mA

V

3

V_OL

Low Level Output Voltage

Low Level Output Voltage, DDR2,

Programmed Impedance = 34 Ω

Low Level Output Voltage, DDR2,

Programmed Impedance = 40 Ω

Low Level Output Voltage, DDR2,

Programmed Impedance = 50 Ω

V_{DD_EXT}= 1 . 7 V, I _OL= 1.0 mA

V_{DD_EXT}= 3.13 V, I_OL= 2.0 mA

V_{DD_DMC}= 1.70 V, I_OL= 7.1 mA

0.400

0.320

3

2

V_{OL_DDR2}

2

V_{OL_DDR2}

V_{DD_DMC}= 1.70 V, I_OL= 5.8 mA

V_{DD_DMC}= 1.70 V, I_OL= 4.1 mA

V_{DD_DMC}= 1.70 V, I_OL= 3.4 mA

0.320

V

2

V_{OL_DDR2}

2

V_{OL_DDR2}

Low Level Output Voltage, DDR2,

Programmed Impedance = 60 Ω

2

V_{OL_LPDDR}

I_IH

Low Level Output Voltage, LPDDR V_{DD_DMC}= 1.70 V, I_OL= 2.0 mA

0.320

10

V

μA

4

High Level Input Current

V_{DD_EXT}= 3.47 V, V_{DD_DMC}= 1.9 V, 

V_{DD_USB}= 3.47 V, V_IN= 3.47 V

V_{DD_EXT}= 3.47 V, V_{DD_DMC}= 1.9 V, 

5

I_{IH_DMC0_VREF}

High Level Input Current

1

μA

kꢀ

μA

kꢀ

μA

V_{DD_USB}= 3.47 V, V_IN= 3.47 V

High Level Input Current with Pull- V_{DD_EXT}= 3.47 V, V_{DD_DMC}= 1.9 V, 

6

I_{IH_PD}

100

130

10

down Resistor

Internal Pull-down Resistance

V_{DD_USB}= 3.47 V, V_IN= 3.47 V

V_{DD_EXT}= 3.47 V, V_{DD_DMC}= 1.9 V, 

V_{DD_USB}= 3.47 V, V_IN= 3.47 V

V_{DD_EXT}= 3.47 V, V_{DD_DMC}= 1.9 V, 

V_{DD_USB}= 3.47 V, V_IN= 0 V

V_{DD_EXT}= 3.47 V, V_{DD_DMC}= 1.9 V, 

V_{DD_USB}= 3.47 V, V_IN= 0 V

6

R_PD

57

53

7

I_IL

Low Level Input Current

5

I_{IL_DMC0_VREF}

1

8

I_{IL_PU}

Low Level Input Current with Pull-up V_{DD_EXT}= 3.47 V, V_{DD_DMC}= 1.9 V, 

100

129

10

Resistor

Internal Pull-up Resistance

V_{DD_USB}= 3.47 V, V_IN= 0 V

V_{DD_EXT}= 3.47 V, V_{DD_DMC}= 1.9 V, 

V_{DD_USB}= 3.47 V, V_IN= 0 V

V_{DD_EXT}= 3.47 V, V_{DD_DMC}= 1.9 V, 

V_{DD_USB}= 3.47 V, V_IN= 3.47 V

V_{DD_EXT}= 3.47 V, V_{DD_DMC}= 1.9 V, 

V_{DD_USB}= 3.47 V, V_IN= 0 V

V_{DD_EXT}= 3.47 V, V_{DD_DMC}= 1.9 V, 

V_{DD_USB}= 3.47 V, V_IN= 3.47 V

V_{DD_EXT}= 3.47 V, V_{DD_DMC}= 1.9 V, 

V_{DD_USB}= 3.47 V, V_IN= 1.9 V

V_{DD_EXT}= 3.47 V, V_{DD_DMC}= 1.9 V, 

V_{DD_USB}= 3.47 V, V_IN= 0 V

V_{DD_EXT}= 3.47 V, V_{DD_DMC}= 1.9 V, 

8

R_PU

9

I_{IH_USB0}

High Level Input Current

9

I_{IL_USB0}

Low Level Input Current

10

I_OZH

Three-State Leakage Current

10

11

I_OZH

10

12

I_OZL

10

13

I_{OZH_PD}

100

V_{DD_USB}= 3.47 V, V_IN= 3.47 V

Rev. A

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September 2015

ADSP-BF700/701/702/703/704/705/706/707

Parameter

I_{OZH_TWI}

Test Conditions/Comments

V_{DD_EXT}= 3.47 V, V_{DD_DMC}= 1.9 V, 

Min

Typ

Max

10

Unit

μA

14

Three-State Leakage Current

V_{DD_USB}= 3.47 V, V_IN= 5.5 V

ADSP-BF701/703/705/707 Input Capacitance

C_IN(GPIO)¹⁵

Input Capacitance

T_AMBIENT= 25°C

5.2

6.9

6.1

6.0

7.4

6.9

pF

14

C_{IN_TWI}

16

C_{IN_DDR}

ADSP-BF700/702/704/706 Input Capacitance

C_IN(GPIO)¹⁵

Input Capacitance

V_{DD_INT}Current in Deep Sleep Mode Clocks disabled

T_J= 25°C

T_AMBIENT= 25°C

5.0

6.8

1.4

5.3

7.4

pF

mA

14

C_{IN_TWI}

I_{DD_DEEPSLEEP}

17, 18

18

I_{DD_IDLE}

V_{DD_INT}Current in Idle

V_{DD_INT}Current

f_PLLCLK= 300 MHz

_CCLK= 100 MHz

ASF = 0.05 (idle)

_SYSCLK= f_SCLK0= 25 MHz

13

90

66

49

30

mA

f

USBCLK = DCLK = OUTCLK = 

SCLK1 = DISABLED

Peripherals disabled

T_J= 25°C

18

I_{DD_TYP}

f_PLLCLK= 800 MHz

f

_CCLK= 400 MHz

ASF = 1.0 (full-on typical)

_SYSCLK= f_SCLK0= 25 MHz

f

USBCLK = DCLK = OUTCLK = 

SCLK1 = DISABLED

Peripherals disabled

T_J= 25°C

18

I_{DD_TYP}

f_PLLCLK= 300 MHz

f

_CCLK= 300 MHz

ASF = 1.0 (full-on typical)

_SYSCLK= f_SCLK0= 25 MHz

f

USBCLK = DCLK = OUTCLK = 

SCLK1 = DISABLED

Peripherals disabled

T_J= 25°C

18

I_{DD_TYP}

f_PLLCLK= 400 MHz

f

_CCLK= 200 MHz

ASF = 1.0 (full-on typical)

_SYSCLK= f_SCLK0= 25 MHz

f

USBCLK = DCLK = OUTCLK = 

SCLK1 = DISABLED

Peripherals disabled

T_J= 25°C

18

I_{DD_TYP}

f_PLLCLK= 300 MHz

f

_CCLK= 100 MHz

ASF = 1.0 (full-on typical)

_SYSCLK= f_SCLK0= 25 MHz

f

USBCLK = DCLK = OUTCLK = 

SCLK1 = DISABLED

Peripherals disabled

T_J= 25°C

Rev. A

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September 2015

ADSP-BF700/701/702/703/704/705/706/707

Parameter

I_{DD_HIBERNATE}

Test Conditions/Comments

V_{DD_INT}= 0 V,

Min

Typ

33

Max

Unit

A

17, 19

Hibernate State Current

V

_{DD_DMC}= 1.8 V,

V

_{DD_EXT}= V_{DD_HADC}= V_{DD_OTP}= 

V_{DD_RTC}= V_{DD_USB}= 3.3 V,

T_J= 25°C,

f

_CLKIN= 0

17, 19

I_{DD_HIBERNATE}

Hibernate State Current

Without USB

V_{DD_INT}= 0 V,

V

15

A

_{DD_DMC}= 1.8 V,

_{DD_EXT}= V_{DD_HADC}= V_{DD_OTP}= 

V_{DD_RTC}= V_{DD_USB}= 3.3 V,

T_J= 25°C,

f

_CLKIN= 0,

USB protection disabled 

(USB_PHY_CTLDIS = 1)

V_{DD_INT}within operating conditions

table specifications

18

I_{DD_INT}

V_{DD_INT}Current

I_{DD_RTC}Current

See I_{DDINT_TOT}mA

equation on

on Page 56

I_{DD_RTC}

V_{DD_RTC}= 3.3 V, T_J= 125°C

10

A

¹Applies to all output and bidirectional signals except DMC0 signals, TWI signals, and USB0 signals.

²Applies to DMC0_Axx, DMC0_CAS, DMC0_CKE, DMC0_CK, DMC0_CK, DMC0_CS, DMC0_DQxx, DMC0_LDM, DMC0_LDQS, DMC0_LDQS, 

DMC0_ODT, DMC0_RAS, DMC0_UDM, DMC0_UDQS, DMC0_UDQS, and DMC0_WE signals.

³Applies to all output and bidirectional signals except DMC0 signals and USB0 signals.

⁴Applies to SMC0_ARDY, SYS_BMODEx, SYS_CLKIN, SYS_HWRST, JTG_TDI, and JTG_TMS_SWDIO signals.

⁵Applies to DMC0_VREF signal.

⁶Applies to JTG_TCK_SWCLK and JTG_TRST signals.

⁷Applies to SMC0_ARDY, SYS_BMODEx, SYS_CLKIN, SYS_HWRST, JTG_TCK, and JTG_TRST signals.

⁸Applies to JTG_TDI, JTG_TMS_SWDIO, PA_xx, PB_xx, and PC_xx signals when internal GPIO pull-ups are enabled. For information on when internal pull-ups are enabled

for GPIOs. See ADSP-BF70x Designer Quick Reference on Page 38.

⁹Applies to USB0_CLKIN signal.

¹⁰Applies to PA_xx, PB_xx, PC_xx, SMC0_AMS0, SMC0_ARE, SMC0_AWE, SMC0_A0E, SMC0_Axx, SMC0_Dxx, SYS_FAULT, JTG_TDO_SWO, USB0_DM, USB0_DP,

USB0_ID, and USB0_VBC signals.

¹¹Applies to DMC0_Axx, DMC0_BAxx, DMC0_CAS, DMC0_CS0, DMC0_DQxx, DMC0_LDQS, DMC0_LDQS, DMC0_UDQS, DMC0_UDQS, DMC0_LDM, DMC0_

UDM, DMC0_ODT, DMC0_RAS, and DMC0_WE signals.

¹²Applies to PA_xx, PB_xx, PC_xx, SMC0_A0E, SMC0_Axx, SMC0_Dxx, SYS_FAULT, JTG_TDO_SWO, USB0_DM, USB0_DP, USB0_ID, USB0_VBC, USB0_VBUS, 

DMC0_Axx, DMC0_BAx, DMC0_CAS, DMC0_CS0, DMC0_DQxx, DMC0_LDQS, DMC0_LDQS, DMC0_UDQS, DMC0_UDQS, DMC0_LDM, 

DMC0_UDM, DMC0_ODT, DMC0_RAS, DMC0_WE, and TWI signals.

¹³Applies to USB0_VBUS signals.

¹⁴Applies to all TWI signals.

¹⁵Applies to all signals, except DMC0 and TWI signals.

¹⁶Applies to all DMC0 signals.

¹⁷See the ADSP-BF70x Blackfin+ Processor Hardware Reference for definition of deep sleep and hibernate operating modes.

¹⁸Additional information can be found at Total Internal Power Dissipation.

¹⁹Applies to VDD_EXT, VDD_DMC, and VDD_USB supply signals only. Clock inputs are tied high or low.

Rev. A

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ADSP-BF700/701/702/703/704/705/706/707

Clock Current

Total Internal Power Dissipation

The dynamic clock currents provide the total power dissipated

by all transistors switching in the clock paths. The power dissi-

pated by each clock domain is dependent on voltage (V_{DD_INT}),

operating frequency and a unique scaling factor.

Total power dissipation has two components:

1. Static, including leakage current (deep sleep)

2. Dynamic, due to transistor switching characteristics for

each clock domain

Many operating conditions can also affect power dissipation,

including temperature, voltage, operating frequency, and pro-

cessor activity. The following equation describes the internal

current consumption.

I

_{DDINT_PLLCLK_DYN}(mA) = 0.012 × f_PLLCLK(MHz) × V_{DD_INT}(V)

_{DDINT_SYSCLK_DYN}(mA) = 0.120 × f_SYSCLK(MHz) × V_{DD_INT}(V)

_{DDINT_SCLK0_DYN}(mA) = 0.110 × f_SCLK0(MHz) × V_{DD_INT}(V)

_{DDINT_SCLK1_DYN}(mA) = 0.068 × f_SCLK1(MHz) × V_{DD_INT}(V)

_{DDINT_DCLK_DYN}(mA) = 0.055 × f_DCLK(MHz) × V_{DD_INT}(V)

I

_{DDINT_TOT}= I_{DDINT_DEEPSLEEP}+ I_{DDINT_CCLK_DYN}+

I

_{DDINT_PLLCLK_DYN}+ I_{DDINT_SYSCLK_DYN}+ 

_{DDINT_SCLK0_DYN}+ I_{DDINT_SCLK1_DYN}+ 

_{DDINT_DCLK_DYN}+ I_{DDINT_DMA_DR_DYN}+ 

The dynamic component of the USB clock is a unique case. The

USB clock contributes a near constant current value when used.

I_{DDINT_USBCLK_DYN}

Table 20. I_{DDINT_USBCLK_DYN}Current

I_{DDINT_DEEPSLEEP}is the only item present that is part of the static

power dissipation component. I_{DDINT_DEEPSLEEP}is specified as a

function of voltage (V_{DD_INT}) and temperature (see Table 21).

There are eight different items that contribute to the dynamic

power dissipation. These components fall into three broad cate-

gories: application-dependent currents, clock currents, and data

transmission currents.

Is USB Enabled?

Yes – High-Speed Mode

Yes – Full-Speed Mode

Yes – Suspend Mode

No

I_{DDINT_USBCLK_DYN}(mA)

13.94

10.83

5.2

0.34

Application-Dependent Current

The application-dependent currents include the dynamic cur-

rent in the core clock domain.

Core clock (CCLK) use is subject to an activity scaling factor

(ASF) that represents application code running on the processor

cores and L1/L2 memories (Table 22). The ASF is combined

with the CCLK frequency and V_{DD_INT}dependent data in

Table 23 to calculate this portion.

Data Transmission Current

The data transmission current represents the power dissipated

when transmitting data. This current is expressed in terms of

data rate. The calculation is performed by adding the data rate

(MB/s) of each DMA-driven access to peripherals, L1, L2, and

external memory. This number is then multiplied by a weighted

data-rate coefficient and V_{DD_INT}

_{DDINT_DMADR_DYN}(mA) = Weighted DRC × Total Data Rate

(MB/s) × V_{DD_INT}(V)

:

I

_{DDINT_CCLK_DYN}(mA) = Table 23 × ASF

A weighted data-rate coefficient is used because different coeffi-

cients exist depending on the source and destination of the

transfer. For details on using this equation and calculating the

weighted DRC, see the related Engineer Zone material. For a

quick maximum calculation, the weighted DRC can be assumed

to be 0.0497, which is the coefficient for L1 to L1 transfers.

Rev. A

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September 2015

ADSP-BF700/701/702/703/704/705/706/707

Table 21. Static Current—I_{DD_DEEPSLEEP}(mA)

Voltage (V_{DD_INT}

)

T_J(°C)

–40

–20

0

1.045

0.6

1.050

0.6

1.060

0.7

1.070

0.7

1.080

0.7

1.090

0.8

1.100

0.8

1.110

0.8

1.120

0.9

1.130

0.9

1.140

0.9

1.150

1.0

1.155

1.0

1.1

1.2

1.3

1.4

1.5

1.6

1.7

2.0

2.1

2.2

2.3

2.4

2.5

2.6

2.7

2.8

3.0

25

4.3

4.5

4.7

4.8

5.0

5.2

5.3

5.5

5.7

5.9

6.1

6.2

40

6.7

6.8

7.0

7.3

7.5

7.8

8.0

8.3

8.6

8.8

9.1

9.4

9.6

55

10.3

15.7

23.3

34.2

38.7

48.9

61.5

10.5

15.9

23.6

34.6

39.2

49.5

62.1

10.8

16.4

24.3

35.5

40.2

50.7

63.6

11.2

16.8

25.0

36.5

41.3

52.0

65.1

11.5

17.4

25.7

37.5

42.4

53.4

66.7

11.9

17.9

26.4

38.5

43.5

54.7

68.3

12.3

18.4

27.2

39.5

44.6

56.0

69.9

12.6

18.9

27.9

40.6

45.8

57.5

71.7

13.0

19.5

28.7

41.7

47.0

59.0

73.4

13.4

20.1

29.5

42.8

48.2

60.5

75.2

13.9

20.7

30.4

43.9

49.5

62.0

77.0

14.3

21.3

31.2

45.1

50.8

63.6

79.0

14.5

21.6

31.7

45.7

51.5

64.4

79.9

70

85

100

105

115

125

Table 22. Activity Scaling Factors (ASF)

I_DDINTPower Vector

I_DD-IDLE1

ASF

0.05

0.56

0.59

0.78

0.79

0.83

1.00

1.01

1.03

1.39

1.54

I_DD-IDLE2

I_DD-NOP1

I_DD-NOP2

I_DD-APP3

I_DD-APP1

I_DD-APP2

I_DD-TYP1

I_DD-TYP3

I_DD-TYP2

I_DD-HIGH1

I_DD-HIGH3

I_DD-HIGH2

Table 23. CCLK Dynamic Current per core (mA, with ASF = 1)

Voltage (V_{DD_INT}

)

f_CCLK(MHz)

400

1.045 1.050 1.060 1.070 1.080 1.090 1.100

1.110

71.8

1.120

72.6

1.130

73.4

1.140

74.2

1.150

74.9

1.155

75.4

66.7

58.6

50.2

42.1

33.7

25.4

17.0

67.2

59.0

50.5

42.3

33.9

25.5

17.1

67.9

59.6

51.1

42.8

34.3

25.8

17.3

68.7

60.3

51.7

43.3

34.7

26.1

17.5

69.4

61.0

52.3

43.8

35.1

26.4

17.7

70.2

61.7

52.9

44.3

35.5

26.7

17.9

71.1

62.4

53.5

44.7

35.9

27.0

18.1

350

63.0

54.1

45.3

36.3

27.3

18.3

63.7

54.7

45.8

36.7

27.6

18.5

64.4

55.3

46.3

37.1

27.9

18.6

65.1

55.9

46.8

37.5

28.2

18.8

65.8

56.4

47.4

37.9

28.5

19.0

66.1

56.8

47.6

38.0

28.8

19.1

300

250

200

150

100

Rev. A

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Page 57 of 116

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September 2015

ADSP-BF700/701/702/703/704/705/706/707

HADC

HADC Electrical Characteristics

Table 24. HADC Electrical Characteristics

Parameter Test Conditions

Typ

Unit

I_{DD_HADC_IDLE}Current Consumption on V_{DD_HADC}

HADC is powered on, but not

converting.

.

2.0

mA

I_{DD_HADC_ACTIVE}Current Consumption on V_{DD_HADC}2.5

during a conversion.

mA

μA

I_{DD_HADC_}

Current Consumption on V_{DD_HADC}

Analog circuitry of the HADC is

powered down

.

10

POWERDOWN

HADC DC Accuracy

Table 25. HADC DC Accuracy

Parameter

Resolution

Typ

12

10

2

Unit

Bits

No Missing Codes (NMC)

Integral Nonlinearity (INL)

Differential Nonlinearity (DNL)

Offset Error

Bits

LSB¹

2

8

Offset Error Matching

Gain Error

10

4

Gain Error Matching

¹LSB = HADC0_VREFP ÷ 4096

4

HADC Timing Specifications

Table 26. HADC Timing Specifications

Parameter

Typ

20 × T_SAMPLE

Max

Unit

μs

Conversion Time

Throughput Range

T_WAKEUP

1

MSPS

μs

100

Rev. A

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Page 58 of 116

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September 2015

ADSP-BF700/701/702/703/704/705/706/707

Table 28. Absolute Maximum Ratings (Continued)

PACKAGE INFORMATION

The information presented in Figure 7 and Table 27 provides

details about package branding. For a complete listing of prod-

uct availability, see the Ordering Guide.

Parameter

Rating

DDR2 Reference Voltage (V_{DDR_REF}

)

–0.33 V to +1.90 V

–0.33 V to +3.60 V

–0.33 V to +5.50 V

–0.33 V to +5.25 V

–0.33 V to +6 V

–0.33 V to +1.90 V

–0.33 V to V_{DD_EXT}+ 0.5 V

4 mA (max)

Input Voltage^{1, 2}

TWI Input Voltage^{2, 3}

USB0_Dx Input Voltage⁴

USB0_VBUS Input Voltage⁵

DDR2 Input Voltage⁵

a

ADSP-BF70x

tppZccc

Output Voltage Swing

I_OH/I_OLCurrent per Signal¹

Storage Temperature Range

vvvvvv.x n.n

–65°C to +150°C

+125°C

#yyww country_of_origin

Junction Temperature While Biased

B

¹Applies to 100% transient duty cycle.

²Applies only when V_{DD_EXT}is within specifications. When V_{DD_EXT}is outside

specifications, the range is V_{DD_EXT}0.2 V.

Figure 7. Product Information on Package¹

¹Exact brand may differ, depending on package type.

³Applies to balls TWI_SCL and TWI_SDA.

⁴Ifthe USB is not used, connectUSB0_Dx andUSB0_VBUS accordingtoTable 15

on Page 38.

⁵Applies only when V_{DD_DMC}is within specifications. When V_{DD_DMC}is outside

specifications, the range is V_{DD_DMC}0.2 V.

Table 27. Package Brand Information

Brand Key

ADSP-BF70x

Field Description

Product model

ESD SENSITIVITY

t

Temperature range

Package type

pp

ESD (electrostatic discharge) sensitive device.

Charged devices and circuit boards can discharge

without detection. Although this product features

patented or proprietary protection circuitry, damage

may occur on devices subjected to high energy ESD.

Therefore, proper ESD precautions should be taken to

avoid performance degradation or loss of functionality.

Z

RoHS compliant designation

See Ordering Guide

Assembly lot code

Silicon revision

ccc

vvvvvv.x

n.n

yyww

Date code

ABSOLUTE MAXIMUM RATINGS

Stresses at or above those listed in Table 28 may cause perma-

nent damage to the product. This is a stress rating only;

functional operation of the product at these or any other condi-

tions above those indicated in the operational section of this

specification is not implied. Operation beyond the maximum

operating conditions for extended periods may affect product

reliability.

Table 28. Absolute Maximum Ratings

Parameter

Rating

Internal Supply Voltage (V_{DD_INT}

)

–0.33 V to +1.20 V

External (I/O) Supply Voltage (V_{DD_EXT}) –0.33 V to +3.60 V

DDR2 Controller Supply Voltage 

(V_{DD_DMC}

USB PHY Supply Voltage (V_{DD_USB}

Real-Time Clock Supply Voltage 

(V_{DD_RTC}

Housekeeping ADC Supply Voltage

(V_{DD_HADC}

One-Time Programmable Memory

Supply Voltage (V_{DD_OTP}

HADC Reference Voltage (V_{HADC_REF}

–0.33 V to +1.90 V

)

–0.33 V to +3.60 V

)

–0.33 V to +3.60 V

)

Rev. A

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Page 59 of 116

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September 2015

ADSP-BF700/701/702/703/704/705/706/707

TIMING SPECIFICATIONS

Specifications are subject to change without notice.

Clock and Reset Timing

Table 29 and Figure 8 describe clock and reset operations related to the clock generation unit (CGU). Per the CCLK, SYSCLK, SCLK0,

SCLK1, DCLK, and OCLK timing specifications in Table 17 on Page 51 and Table 18 on Page 52, combinations of SYS_CLKIN and clock

multipliers must not select clock rates in excess of the processor’s maximum instruction rate.

Table 29. Clock and Reset Timing

V_{DD_EXT}

1.8V Nominal

V_{DD_EXT}

3.3V Nominal

Parameter

Min

Max

Min

Max

Unit

Timing Requirement

f_CKIN

t_CKINL

t_CKINH

t_WRST

SYS_CLKIN Crystal Frequency (CGU_CTL.DF = 0)^{1, 2, 3}

SYS_CLKIN Crystal Frequency (CGU_CTL.DF = 1)^{1, 2, 3}

SYS_CLKIN External Source Frequency (CGU_CTL.DF = 0)^{1, 2, 3}19.2

SYS_CLKIN External Source Frequency (CGU_CTL.DF = 1)^{1, 2, 3}38.4

SYS_CLKIN Low Pulse¹

SYS_CLKIN High Pulse¹

19.2

N/A

35

19.2

38.4

19.2

38.4

8.33

50

60

MHz

ns

N/A

60

8.33

ns

SYS_HWRST Asserted Pulse Width Low⁴

11 × t_CKIN

ns

¹Applies to PLL bypass mode and PLL nonbypass mode.

²The t_CKINperiod (see Figure 8) equals 1/f_CKIN

.

³Combinations of the CLKIN frequency and the PLL clock multiplier must not exceed the allowed f_PLLCLKsetting discussed in Table 19.

⁴Applies after power-up sequence is complete. See Table 30 and Figure 9 for power-up reset timing.

t_CKIN

SYS_CLKIN

t_CKINL

t_CKINH

t_WRST

SYS_HWRST

Figure 8. Clock and Reset Timing

Rev. A

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Page 60 of 116

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September 2015

ADSP-BF700/701/702/703/704/705/706/707

Power-Up Reset Timing

A power-up reset is required to place the processor in a known state after power-up. A power-up reset is initiated by asserting 

SYS_HWRST and JTG_TRST. During power-up reset, all pins are high impedance except for those noted in the ADSP-BF70x Designer

Quick Reference on Page 38.

Both JTG_TRST and SYS_HWRST need to be asserted upon power-up, but only SYS_HWRST needs to be released for the device to boot

properly. JTG_TRST may be asserted indefinitely for normal operation. JTG_TRST only needs to be released when using an emulator to

connect to the DAP for debug or boundary scan. There is an internal pull-down on JTG_TRST to ensure internal emulation logic will

always be properly initialized during power-up reset.

Table 30 and Figure 9 show the relationship between power supply startup and processor reset timing, related to the clock generation unit

(CGU) and reset control unit (RCU). In Figure 9, V_{DD_SUPPLIES}are V_{DD_INT}, V_{DD_EXT}, V_{DD_DMC}, V_{DD_USB}, V_{DD_RTC}, V_{DD_OTP}, and V_{DD_HADC}

.

There is no power supply sequencing requirement for the ADSP-BF70x processor. However, if saving power during power-on is import-

ant, bringing up V_{DD_INT}last is recommended. This avoids a small current drain in the V_{DD_INT}domain during the transition period of I/O

voltages from 0 V to within the voltage specification.

Table 30. Power-Up Reset Timing

Parameter

Min

Max

Unit

Timing Requirement

t_{RST_IN_PWR}SYS_HWRST and JTG_TRST Deasserted After V_{DD_INT}, V_{DD_DMC}, V_{DD_USB}, 

11 × t_CKIN

ns

μs

V_{DD_RTC}, V_{DD_OTP}, V_{DD_HADC}, and SYS_CLKIN are Stable and Within Specification

t_{VDDEXT_RST}SYS_HWRST Deasserted After V_{DD_EXT}is Stable and Within Specifications 

10

1

(No External Pull-Down on JTG_TRST)

t_{VDDEXT_RST}SYS_HWRST Deasserted After V_{DD_EXT}is Stable and Within Specifications (10k

External Pull-Down on JTG_TRST)

SYS_HWRST

AND

JTG_TRST

t_{RST_IN_PWR}

CLKIN

V

DD_SUPPLIES

(EXCEPT V

)

DD_EXT

V

DD_EXT

t_{VDDEXT_RST}

Figure 9. Power-Up Reset Timing

Rev. A

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Page 61 of 116

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September 2015

ADSP-BF700/701/702/703/704/705/706/707

Asynchronous Read

Table 31 and Figure 10 show asynchronous memory read timing, related to the static memory controller (SMC).

Table 31. Asynchronous Memory Read (BxMODE = b#00)

V_{DD_EXT}

1.8V Nominal

V_{DD_EXT}

3.3V Nominal

Parameter

Min

Max

Min

Max

Unit

Timing Requirements

t_SDATARE

t_HDATARE

t_DARDYARE

DATA in Setup Before

SMC0_ARE High

11.8

0

10.8

0

ns

DATA in Hold After

SMC0_ARE High

SMC0_ARDY Valid After

SMC0_ARE Low^{1, 2}

(RAT – 2.5) × 

t_SCLK0– 17.5

(RAT – 2.5) × 

t_SCLK0– 17.5

Switching Characteristics

t_AMSARE

SMC0_Ax/SMC0_AMSx (PREST + RST + PREAT)

(PREST + RST + PREAT)

× t_SCLK0– 2

ns

Assertion Before 

× t_SCLK0– 2

SMC0_ARE Low³

t_DADVARE

t_AOEARE

t_HARE

SMC0_ARE Low Delay

From ADV High

PREAT × t_SCLK0– 2

ns

SMC0_AOE Assertion

Before SMC0_ARE Low

(RST + PREAT) ×

t_SCLK0– 2

(RST + PREAT) ×

t_SCLK0– 2

Output⁴Hold After

RHT × t_SCLK0– 2

RAT × t_SCLK0– 2

RHT × t_SCLK0– 2

RAT × t_SCLK0– 2

SMC0_ARE High⁵

t_WARE

SMC0_ARE Active Low

Width⁶

t_DAREARDY

SMC0_ARE High Delay

After SMC0_ARDY

Assertion¹

3.5 × t_SCLK0+ 17.5

¹SMC0_BxCTL.ARDYEN bit = 1.

²RAT value set using the SMC_BxTIM.RAT bits.

³PREST, RST, and PREAT values set using the SMC_BxETIM.PREST bits, SMC_BxTIM.RST bits, and the SMC_BxETIM.PREAT bits.

⁴Output signals are SMC0_Ax, SMC0_AMSx, SMC0_AOE, and SMC0_ABEx.

⁵RHT value set using the SMC_BxTIM.RHT bits.

⁶SMC0_BxCTL.ARDYEN bit = 0.

Rev. A

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Page 62 of 116

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September 2015

ADSP-BF700/701/702/703/704/705/706/707

SMC0_ARE

t_WARE

t_HARE

t_ADDRARE

SMC0_AMSx

SMC0_Ax

t_AOEARE

SMC0_AOE

t_DARDYARE

t_DAREARDY

SMC0_ARDY

t_SDATARE

t_HDATARE

SMC0_Dx (DATA)

Figure 10. Asynchronous Read

Rev. A

|

Page 63 of 116

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September 2015

ADSP-BF700/701/702/703/704/705/706/707

SMC Read Cycle Timing With Reference to SYS_CLKOUT

The following SMC specifications with respect to SYS_CLKOUT are given to accommodate the connection of the SMC to 

programmable logic devices. These specifications assume that SYS_CLKOUT is outputting a buffered version of SCLK0 by 

setting CGU_CLKOUTSEL.CLKOUTSEL = 0x3. However, SCLK0 must not run faster than the maximum f_OCLKspecification. 

For this example, RST = 0x2, RAT = 0x4, and RHT = 0x1.

Table 32. SMC Read Cycle Timing With Reference to SYS_CLKOUT (BxMODE = b#00)

V_{DD_EXT}

1.8V Nominal

V_{DD_EXT}

3.3V Nominal

Parameter

Min

Max

Min

Max

Unit

Timing Requirements

t_SDAT

SMC0_Dx Setup Before SYS_CLKOUT

5.3

4.3

ns

t_HDAT

t_SARDY

t_HARDY

SMC0_Dx Hold After SYS_CLKOUT

SMC0_ARDY Setup Before SYS_CLKOUT

SMC0_ARDY Hold After SYS_CLKOUT

1.5

16.6

0.7

14.4

0.7

Switching Characteristics

t_DO

Output Delay After SYS_CLKOUT¹

Output Hold After SYS_CLKOUT ¹

7

ns

t_HO

–2.5

¹Output signals are SMC0_Ax, SMC0_AMSx, SMC0_AOE, and SMC0_ABEx.

SETUP

PROGRAMMED READ

ACCESS 4 CYCLES

ACCESS EXTENDED

3 CYCLES

HOLD

2 CYCLES

1 CYCLE

SYS_CLKOUT

SMC0_AMSx

t_DO

t_HO

SMC0_ABEx

SMC0_Ax

SMC0_AOE

SMC0_ARE

SMC0_ARDY

t_DO

t_HO

t_SARDY

t_HARDY

t_SARDY

t_HARDY

t_SDAT

t_HDAT

DATA 15–0

Figure 11. Asynchronous Memory Read Cycle Timing

Rev. A

|

Page 64 of 116

|

September 2015

ADSP-BF700/701/702/703/704/705/706/707

Asynchronous Flash Read

Table 33 and Figure 12 show asynchronous flash memory read timing, related to the static memory controller (SMC).

Table 33. Asynchronous Flash Read

V_{DD_EXT}

1.8 V/3.3V Nominal

Parameter

Min

Max

Unit

Switching Characteristics

t_AMSADV

SMC0_Ax (Address)/SMC0_AMSx Assertion Before SMC0_NORDV

PREST × t_SCLK0– 2

ns

Low¹

t_WADV

SMC0_NORDV Active Low Width²

SMC0_ARE Low Delay From SMC0_NORDV High³

Output⁴Hold After SMC0_ARE High⁵

SMC0_ARE Active Low Width⁷

RST × t_SCLK0– 2

PREAT × t_SCLK0– 2

RHT × t_SCLK0– 2

RAT × t_SCLK0– 2

ns

t_DADVARE

t_HARE

6

t_WARE

¹PREST value set using the SMC_BxETIM.PREST bits.

²RST value set using the SMC_BxTIM.RST bits.

³PREAT value set using the SMC_BxETIM.PREAT bits.

⁴Output signals are SMC0_Ax, SMC0_AMS, SMC0_AOE.

⁵RHT value set using the SMC_BxTIM.RHT bits.

⁶SMC0_BxCTL.ARDYEN bit = 0.

⁷RAT value set using the SMC_BxTIM.RAT bits.

SMC0_Ax

SMC0_AMSx

(NOR_CE)

t_AMSADV

t_WADV

SMC0_NORDV

t_WARE

t_HARE

t_DADVARE

SMC0_ARE

(NOR_OE)

SMC0_Dx

(DATA)

READ LATCHED

DATA

Figure 12. Asynchronous Flash Read

Rev. A

|

Page 65 of 116

|

September 2015

ADSP-BF700/701/702/703/704/705/706/707

Asynchronous Page Mode Read

Table 34 and Figure 13 show asynchronous memory page mode read timing, related to the static memory controller (SMC).

Table 34. Asynchronous Page Mode Read

V_{DD_EXT}

1.8V /3.3V Nominal

Parameter

Min

Max

Unit

Switching Characteristics

t_AV

SMC0_Ax (Address) Valid for First Address Min Width¹(PREST + RST + PREAT + RAT) × t_SCLK0– 2

ns

t_AV1

SMC0_Ax (Address) Valid for Subsequent SMC0_Ax

(Address) Min Width

PGWS × t_SCLK0– 2

t_WADV

t_HARE

SMC0_NORDV Active Low Width²

Output³Hold After SMC0_ARE High⁴

SMC0_ARE Active Low Width⁶

RST × t_SCLK0– 2

ns

RHT × t_SCLK0– 2

5

t_WARE

(RAT + (Nw – 1) × PGWS) × t_SCLK0– 2

¹PREST, RST, PREAT and RAT values set using the SMC_BxETIM.PREST bits, SMC_BxTIM.RST bits, SMC_BxETIM.PREAT bits, and the SMC_BxTIM.RAT bits.

²RST value set using the SMC_BxTIM.RST bits.

³Output signals are SMC0_Ax, SMC0_AMSx, SMC0_AOE.

⁴RHT value set using the SMC_BxTIM.RHT bits.

⁵SMC_BxCTL.ARDYEN bit = 0.

⁶RAT value set using the SMC_BxTIM.RAT bits.

READ

LATCHED

DATA

READ

LATCHED

DATA

READ

LATCHED

DATA

READ

LATCHED

DATA

t_AV

A0

t_AV1

SMC0_Ax

(ADDRESS)

A0 + 1

A0 + 2

A0 + 3

SMC0_AMSx

(NOR_CE)

SMC0_AOE

NOR_ADV

t_WADV

SMC0_ARE

(NOR_OE)

t_WARE

t_HARE

SMC0_Dx

(DATA)

D0

D1

D2

D3

Figure 13. Asynchronous Page Mode Read

Rev. A

|

Page 66 of 116

|

September 2015

ADSP-BF700/701/702/703/704/705/706/707

Asynchronous Write

Table 35 and Figure 14 show asynchronous memory write timing, related to the static memory controller (SMC).

Table 35. Asynchronous Memory Write (BxMODE = b#00)

V_{DD_EXT}

1.8V Nominal

V_{DD_EXT}

3.3V Nominal

Parameter

Min

Max

Min

Max

Unit

Timing Requirement

1

t_DARDYAWE

SMC0_ARDY Valid After 

SMC0_AWE Low²

Switching Characteristics

t_ENDATDATA Enable After SMC0_AMSx

(WAT – 2.5) ×

t_SCLK0– 17.5

(WAT – 2.5) ×

t_SCLK0– 17.5

ns

–3

–2

ns

Assertion

t_DDAT

t_AMSAWE

DATA Disable After SMC0_AMSx

Deassertion

4.5

4

SMC0_Ax/SMC0_AMSx Assertion

(PREST + WST +

PREAT) × t_SCLK0– 2

(PREST + WST +

PREAT) × t_SCLK0– 4

Before SMC0_AWE Low³

t_HAWE

Output⁴Hold After SMC0_AWE High⁵WHT × t_SCLK0

WHT × t_SCLK0

ns

6

t_WAWE

SMC0_AWE Active Low Width⁶

WAT × t_SCLK0– 2

1

t_DAWEARDY

SMC0_AWE High Delay After 

3.5 × t_SCLK0+ 17.5

3.5 × t_SCLK0+ 17.5 ns

SMC0_ARDY Assertion

¹SMC_BxCTL.ARDYEN bit = 1.

²WAT value set using the SMC_BxTIM.WAT bits.

³PREST, WST, PREAT values set using the SMC_BxETIM.PREST bits, SMC_BxTIM.WST bits, SMC_BxETIM.PREAT bits, and the SMC_BxTIM.RAT bits.

⁴Output signals are DATA, SMC0_Ax, SMC0_AMSx, SMC0_ABEx.

⁵WHT value set using the SMC_BxTIM.WHT bits.

⁶SMC_BxCTL.ARDYEN bit = 0.

SMC0_AWE

SMC0_ABEx

SMC0_Ax

t_AMSAWE

t_WAWE

t_HAWE

SMC0_ARDY

t_DARDYAWE

t_DAWEARDY

SMC0_AMSx

SMC0_Dx (DATA)

t_DDAT

t_ENDAT

Figure 14. Asynchronous Write

Rev. A

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ADSP-BF700/701/702/703/704/705/706/707

SMC Write Cycle Timing With Reference to SYS_CLKOUT

The following SMC specifications with respect to SYS_CLKOUT are given to accommodate the connection of the SMC to 

programmable logic devices. These specifications assume that SYS_CLKOUT is outputting a buffered version of SCLK0 by 

setting CGU_CLKOUTSEL.CLKOUTSEL = 0x3. However, SCLK0 must not run faster than the maximum f_OCLKspecification. 

For this example WST = 0x2, WAT = 0x2, and WHT = 0x1.

Table 36. SMC Write Cycle Timing With Reference to SYS_CLKOUT (BxMODE = b#00)

V_{DD_EXT}

1.8V/3.3V Nominal

Parameter

Min

Max

Unit

Timing Requirements

t_SARDY

t_HARDY

Switching Characteristics

SMC0_ARDY Setup Before SYS_CLKOUT

14.4

0.7

ns

SMC0_ARDY Hold After SYS_CLKOUT

t_DDAT

t_ENDAT

t_DO

SMC0_Dx Disable After SYS_CLKOUT

7

ns

SMC0_Dx Enable After SYS_CLKOUT

Output Delay After SYS_CLKOUT¹

Output Hold After SYS_CLKOUT ¹

–2.5

t_HO

¹Output pins/balls include SMC0_AMSx, SMC0_ABEx, SMC0_Ax, SMC0_Dx, SMC0_AOE, and SMC0_AWE.

PROGRAMMED

WRITE

ACCESS

2 CYCLES

ACCESS

EXTEND HOLD

1 CYCLE 1 CYCLE

SETUP

2 CYCLES

SYS_CLKOUT

SMC0_AMSx

t_DO

t_HO

SMC0_ABEx

SMC0_Ax

t_DO

t_HO

SMC0_AWE

SMC0_ARDY

SMC0_Dx

t_SARDY

t_HARDY

t_ENDAT

t_HARDY

t_DDAT

t_SARDY

Figure 15. SMC Write Cycle Timing With Reference to SYS_CLKOUT Timing

Rev. A

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ADSP-BF700/701/702/703/704/705/706/707

Asynchronous Flash Write

Table 37 and Figure 16 show asynchronous flash memory write timing, related to the static memory controller (SMC).

Table 37. Asynchronous Flash Write

V_{DD_EXT}

1.8V/3.3V Nominal

Parameter

Min

Max

Unit

Switching Characteristics

t_AMSADV

t_DADVAWE

t_WADV

SMC0_Ax/SMC0_AMSx Assertion Before ADV Low¹

SMC0_AWE Low Delay From ADV High²

NR_ADV Active Low Width³

Output⁴Hold After SMC0_AWE High⁵

SMC0_AWE Active Low Width⁷

PREST × t_SCLK0– 2

PREAT × t_SCLK0– 4

WST × t_SCLK0– 2

WHT × t_SCLK0

ns

t_HAWE

6

t_WAWE

WAT × t_SCLK0– 2

¹PREST value set using the SMC_BxETIM.PREST bits.

²PREAT value set using the SMC_BxETIM.PREAT bits.

³WST value set using the SMC_BxTIM.WST bits.

⁴Output signals are DATA, SMC0_Ax, SMC0_AMSx, SMC0_ABEx.

⁵WHT value set using the SMC_BxTIM.WHT bits.

⁶SMC_BxCTL.ARDYEN bit = 0.

⁷WAT value set using the SMC_BxTIM.WAT bits.

NOR_A x-1

(SMC0_Ax)

NR_CE

(SMC0_AMSx)

t_AMSADV

t_WADV

NR_ADV

(SMC0_AOE)

t_WAWE

t_HAWE

t_DADVAWE

NR_WE

(SMC0_AWE)

NR_DQ 15

-0

(SMC0_Dx)

Figure 16. Asynchronous Flash Write

All Accesses

Table 38 describes timing that applies to all memory accesses, related to the static memory controller (SMC).

Table 38. All Accesses

V_{DD_EXT}

1.8V Nominal

V_{DD_EXT}

3.3V Nominal

Parameter

Min

Max

Min

Max

Unit

ns

Switching Characteristic

t_TURN

SMC0_AMSx Inactive Width

(IT + TT) × t_SCLK0– 2

Rev. A

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ADSP-BF700/701/702/703/704/705/706/707

DDR2 SDRAM Clock and Control Cycle Timing

Table 39 and Figure 17 show DDR2 SDRAM clock and control cycle timing, related to the dynamic memory controller (DMC).

Table 39. DDR2 SDRAM Read Cycle Timing, V_{DD_DMC}Nominal 1.8 V

200 MHz

Parameter

Min

Max

Unit

Switching Characteristics

t_CK

t_CH

t_CL

t_IS

Clock Cycle Time (CL = 2 Not Supported)

5

ns

t_CK

ps

High Clock Pulse Width

0.45

350

475

0.55

Low Clock Pulse Width

Control/Address Setup Relative to DMC0_CK Rise

Control/Address Hold Relative to DMC0_CK Rise

t_IH

t_CK

t_CH

t_CL

DMC0_CK

t_IS

t_IH

ADDRESS

CONTROL

NOTE: CONTROL = DMC0_CS0, DMC0_CKE, DMC0_RAS, DMC0_CAS, AND DMC0_WE.

ADDRESS = DMC0_A00 13, AND DMC0_BA0 2.

-

Figure 17. DDR2 SDRAM Clock and Control Cycle Timing

Rev. A

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DDR2 SDRAM Read Cycle Timing

Table 40 and Figure 18 show DDR2 SDRAM read cycle timing, related to the dynamic memory controller (DMC).

Table 40. DDR2 SDRAM Read Cycle Timing, V_{DD_DMC}Nominal 1.8 V

200 MHz¹

Parameter

Timing Requirements

t_DQSQ

Min

Max

Unit

DMC0_DQS-DMC0_DQ Skew for DMC0_DQS and Associated DMC0_

DQ Signals

0.35

ns

t_QH

DMC0_DQ, DMC0_DQS Output Hold Time From DMC0_DQS

1.8

0.9

0.4

ns

t_CK

t_RPRE

Read Preamble

t_RPST

Read Postamble

¹To ensure proper operation of the DDR2, all the DDR2 guidelines have to be strictly followed.

DMC0_CKx

DMC0_Ax

DMC0 CONTROL

t_RPRE

DMC0_DQSn

t_DQSQ

t_RPST

t_QH

t_DQSQ

t_QH

DMC0_DQx

Figure 18. DDR2 SDRAM Controller Input AC Timing

Rev. A

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DDR2 SDRAM Write Cycle Timing

Table 41 and Figure 19 show DDR2 SDRAM write cycle timing, related to the dynamic memory controller (DMC).

Table 41. DDR2 SDRAM Write Cycle Timing, V_{DD_DMC}Nominal 1.8 V

200 MHz¹

Parameter

Min

Max

Unit

Switching Characteristics

2

t_DQSS

t_DS

DMC0_DQS Latching Rising Transitions to Associated Clock Edges

–0.25

0.15

0.275

0.2

+0.25

t_CK

ns

t_CK

Last Data Valid to DMC0_DQS Delay

DMC0_DQS to First Data Invalid Delay

DMC0_DQS Falling Edge to Clock Setup Time

DMC0_DQS Falling Edge Hold Time From DMC0_CK

DMC0_DQS Output High Pulse Width

DMC0_DQS Output Low Pulse Width

Write Preamble

t_DH

t_DSS

t_DSH

t_DQSH

t_DQSL

t_WPRE

t_WPST

t_IPW

0.2

0.35

0.4

Write Postamble

Address and Control Output Pulse Width

0.6

t_DIPW

DMC0_DQ and DMC0_DM Output Pulse Width

0.35

¹To ensure proper operation of the DDR2, all the DDR2 guidelines have to be strictly followed.

²Write command to first DMC0_DQS delay = WL × t_CK+ t_DQSS

.

DMC0_CK

t_IPW

DMC0_Ax

DMC0 CONTROL

t_DSH

t_DSS

t_DQSS

DMC0_LDQS

DMC0_UDQS

t_WPRE

t_DQSL

t_DQSH

t_WPST

t_DS

t_DH

t_DIPW

DMC0_LDM

DMC0_UDM

DMC0_DQx

Figure 19. DDR2 SDRAM Controller Output AC Timing

Rev. A

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ADSP-BF700/701/702/703/704/705/706/707

Mobile DDR SDRAM Clock and Control Cycle Timing

Table 42 and Figure 20 show mobile DDR SDRAM clock and control cycle timing, related to the dynamic memory controller (DMC).

Table 42. Mobile DDR SDRAM Clock and Control Cycle Timing, V_{DD_DMC}Nominal 1.8 V

200 MHz

Parameter

Min

Max

Unit

Switching Characteristics

t_CK

t_CH

t_CL

t_IS

Clock Cycle Time (CL = 2 Not Supported)

5

ns

t_CK

ns

Minimum Clock Pulse Width

0.45

1.5

0.55

Maximum Clock Pulse Width

Control/Address Setup Relative to DMC0_CK Rise

Control/Address Hold Relative to DMC0_CK Rise

t_IH

t_CK

t_CH

t_CL

DMC0_CK

t_IS

t_IH

ADDRESS

CONTROL

NOTE: CONTROL = DMC0_CS0, DMC0_CKE, DMC0_RAS, DMC0_CAS, AND DMC0_WE.

ADDRESS = DMC0_A00 13, AND DMC0_BA0 2.

-

Figure 20. Mobile DDR SDRAM Clock and Control Cycle Timing

Rev. A

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ADSP-BF700/701/702/703/704/705/706/707

Mobile DDR SDRAM Read Cycle Timing

Table 43 and Figure 21 show mobile DDR SDRAM read cycle timing, related to the dynamic memory controller (DMC).

Table 43. Mobile DDR SDRAM Read Cycle Timing, V_{DD_DMC}Nominal 1.8 V

200 MHz

Parameter

Min

Max

Unit

Timing Requirements

t_QH

DMC0_DQ, DMC0_DQS Output Hold Time From DMC0_DQS

1.5

ns

t_DQSQ

DMC0_DQS-DMC0_DQ Skew for DMC0_DQS and Associated

DMC0_DQ Signals

0.7

t_RPRE

t_RPST

Read Preamble

Read Postamble

0.9

0.4

1.1

0.6

t_CK

DMC0_CK

t

RPST

RPRE

DMC0_DQS

t

QH

DMC0_DQS

(DATA)

Dn

Dn+1

Dn+2

Dn+3

t

DQSQ

Figure 21. Mobile DDR SDRAM Controller Input AC Timing

Rev. A

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ADSP-BF700/701/702/703/704/705/706/707

Mobile DDR SDRAM Write Cycle Timing

Table 44 and Figure 22 show mobile DDR SDRAM write cycle timing, related to the dynamic memory controller (DMC).

Table 44. Mobile DDR SDRAM Write Cycle Timing, V_{DD_DMC}Nominal 1.8 V

200 MHz

Parameter

Min

Max

Unit

Switching Characteristics

1

t_DQSS

t_DS

DMC0_DQS Latching Rising Transitions to Associated Clock Edges

0.75

0.48

0.2

1.25

t_CK

ns

t_CK

ns

Last Data Valid to DMC0_DQS Delay (Slew > 1 V/ns)

DMC0_DQS to First Data Invalid Delay (Slew > 1 V/ns)

DMC0_DQS Falling Edge to Clock Setup Time

DMC0_DQS Falling Edge Hold Time From DMC0_CK

DMC0_DQS Input High Pulse Width

DMC0_DQS Input Low Pulse Width

t_DH

t_DSS

t_DSH

t_DQSH

t_DQSL

t_WPRE

t_WPST

t_IPW

0.2

0.4

Write Preamble

0.25

0.4

Write Postamble

Address and Control Output Pulse Width

2.3

t_DIPW

DMC0_DQ and DMC0_DM Output Pulse Width

1.8

¹Write command to first DMC0_DQS delay = WL × t_CK+ t_DQSS

.

DMC0_CK

t

DSS

DSH

t

DQSS

DMC0_DQS0-1

t

WPRE

t

WPST

DQSL

DQSH

t

DH

DS

t

DIPW

DMC0_DQ0

-

15/

Dn

Dn+1

Dn+2

Dn+3

DMC0_DQM0

-

1

t

DIPW

Write CMD

CONTROL

NOTE: CONTROL = DMC0_CS0, DMC0_CKE, DMC0_RAS, DMC0_CAS, AND DMC0_WE.

ADDRESS = DMC0_A00 13, AND DMC0_BA0 1.

-

t

IPW

Figure 22. Mobile DDR SDRAM Controller Output AC Timing

Rev. A

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ADSP-BF700/701/702/703/704/705/706/707

General-Purpose I/O Port Timing (GPIO)

Table 45 and Figure 23 describe I/O timing, related to the general-purpose ports (PORT).

Table 45. General-Purpose I/O Port Timing

V_{DD_EXT}

1.8 V/3.3V Nominal

Parameter

Min

Max

Unit

Timing Requirement

t_WFI

General-Purpose Port Pin Input Pulse Width

2 × t_SCLK0– 1.5

ns

t_WFI

GPIO INPUT

Figure 23. General-Purpose I/O Port Timing

Timer Cycle Timing

Table 46 and Figure 24 describe timer expired operations, related to the general-purpose timer (TIMER). The input signal is asynchro-

nous in width capture mode and external clock mode and has an ideal maximum input frequency of (f_SCLK0/4) MHz. The Period Value

(VALUE) is the timer period assigned in the TMx_TMRn_PER register and can range from 2 to 2³²– 1.

Table 46. Timer Cycle Timing

V_{DD_EXT}

1.8V Nominal

V_{DD_EXT}

3.3V Nominal

Parameter

Min

Max

Min

Max

Unit

Timing Requirements

t_WL

t_WH

Timer Pulse Width Input Low¹

Timer Pulse Width Input High¹

2 × t_SCLK0– 1.5

ns

Switching Characteristic

t_HTOTimer Pulse Width Output

t_SCLK0× VALUE – 1

ns

¹This specification indicates the minimum instantaneous width that can be tolerated due to duty cycle variation or jitter for TMx signals in width capture and external clock

modes. The ideal maximum frequency for TMx signals is listed in Timer Cycle Timing on this page.

TMR OUTPUT

t_HTO

TMR INPUT

t_WH, t_WL

Figure 24. Timer Cycle Timing

Rev. A

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Up/Down Counter/Rotary Encoder Timing

Table 47 and Figure 25 describe timing, related to the general-purpose counter (CNT).

Table 47. Up/Down Counter/Rotary Encoder Timing

V_{DD_EXT}

1.8V Nominal

V_{DD_EXT}

3.3V Nominal

Parameter

Min

Max

Min

Max

Unit

Timing Requirement

t_WCOUNT

Up/Down Counter/Rotary Encoder Input Pulse Width 2 × t_SCLK0

2 × t_SCLK0

ns

CNT_UD

CNT_DG

CNT_ZM

t_WCOUNT

Figure 25. Up/Down Counter/Rotary Encoder Timing

Rev. A

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Debug Interface (JTAG Emulation Port) Timing

Table 48 and Figure 26 provide I/O timing, related to the debug interface (JTAG emulator port).

Table 48. JTAG Port Timing

V_{DD_EXT}

1.8V Nominal

V_{DD_EXT}

3.3V Nominal

Parameter

Min

Max

Min

Max

Unit

Timing Requirements

t_TCK

JTG_TCK Period

20

5

20

4

ns

t_TCK

t_STAP

t_HTAP

t_SSYS

t_HSYS

t_TRSTW

JTG_TDI, JTG_TMS Setup Before JTG_TCK High

JTG_TDI, JTG_TMS Hold After JTG_TCK High

System Inputs Setup Before JTG_TCK High¹

System Inputs Hold After JTG_TCK High¹

4

JTG_TRST Pulse Width (Measured in JTG_TCK Cycles)²

4

Switching Characteristics

t_DTDO

t_DSYS

t_DTMS

JTG_TDO Delay From JTG_TCK Low

System Outputs Delay After JTG_TCK Low³

16.5

18

14.5

16.5

14.5

ns

TMS Delay After TCK High in SWD Mode

3.5

16.5

3.5

¹System inputs = DMC0_DQxx, DMC0_LDQS, DMC0_LDQS, DMC0_UDQS, DMC0_UDQS, PA_xx, PB_xx, PC_xx, SYS_BMODEx, SYS_HWRST, SYS_FAULT, 

SYS_NMI, TWI0_SCL, TWI0_SDA, and SYS_EXTWAKE.

²50 MHz maximum.

³System outputs = DMC0_Axx, DMC0_BAx, DMC0_CAS, DMC0_CK, DMC0_CK, DMC0_CKE, DMC0_CS0, DMC0_DQxx, DMC0_LDM, DMC0_LDQS, DMC0_LDQS,

DMC0_ODT, DMC0_RAS, DMC0_UDM, DMC0_UDQS, DMC0_UDQS, DMC0_WE, PA_xx, PB_xx, PC_xx, SYS_CLKOUT, SYS_FAULT, SYS_RESOUT, and SYS_NMI.

t_TCK

JTG_TCK

t_STAP

t_HTAP

JTG_TMS

JTG_TDI

t_DTDO

JTG_TDO

t_SSYS

t_HSYS

SYSTEM

INPUTS

t_DSYS

SYSTEM

OUTPUTS

Figure 26. JTAG Port Timing

Rev. A

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ADSP-BF700/701/702/703/704/705/706/707

Serial Ports

To determine whether serial port (SPORT) communication is possible between two devices at clock speed n, the following specifications

must be confirmed: 1) frame sync delay and frame sync setup and hold, 2) data delay and data setup and hold, and 3) serial clock 

(SPT_CLK) width. In Figure 27 either the rising edge or the falling edge of SPT_CLK (external or internal) can be used as the active

sampling edge.

When externally generated the SPORT clock is called f_SPTCLKEXT

:

1

t

= ------------------------------

SPTCLKEXT

f

SPTCLKEXT

When internally generated, the programmed SPORT clock (f_SPTCLKPROG) frequency in MHz is set by the following equation where CLKDIV

is a field in the SPORT_DIV register that can be set from 0 to 65,535:

f

SCLK0

f

= ------------------------------------

SPTCLKPROG

CLKDIV + 1

1

t

= ----------------------------------

SPTCLKPROG

f

SPTCLKPROG

Table 49. Serial Ports—External Clock

V_{DD_EXT}

1.8V Nominal

V_{DD_EXT}

3.3V Nominal

Parameter

Min

Max

Min

Max

Unit

Timing Requirements

t_SFSE

Frame Sync Setup Before SPT_CLK 

(Externally Generated Frame Sync in Either

Transmit or Receive Mode)¹

1.5

1

ns

t_HFSE

Frame Sync Hold After SPT_CLK 

(Externally Generated Frame Sync in Either

Transmit or Receive Mode)¹

3

ns

t_SDRE

Receive Data Setup Before Receive SPT_CLK¹1.5

1

3

ns

t_HDRE

Receive Data Hold After SPT_CLK¹

SPT_CLK Width²

SPT_CLK Period²

3

t_SCLKW

t_SPTCLKE

(0.5 × t_SPTCLKEXT) – 1

t_SPTCLKEXT– 1

(0.5 × t_SPTCLKEXT) – 1

t_SPTCLKEXT– 1

Switching Characteristics

t_DFSE

Frame Sync Delay After SPT_CLK 

18

15

ns

(Internally Generated Frame Sync in Either

Transmit or Receive Mode)³

t_HOFSE

Frame Sync Hold After SPT_CLK 

(Internally Generated Frame Sync in Either

Transmit or Receive Mode)³

Transmit Data Delay After Transmit SPT_CLK³

Transmit Data Hold After Transmit SPT_CLK³2.5

2.5

t_DDTE

t_HDTE

ns

¹Referenced to sample edge.

²This specification indicates the minimum instantaneous width or period that can be tolerated due to duty cycle variation or jitter on the external SPT_CLK. For the external

SPT_CLK ideal maximum frequency, see the f_SPTCLKEXTspecification in Table 18 on Page 52 in Clock Related Operating Conditions.

³Referenced to drive edge.

Rev. A

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Table 50. Serial Ports—Internal Clock

V_{DD_EXT}

1.8V Nominal

V_{DD_EXT}

3.3V Nominal

Parameter

Min

Max

Min

Max

Unit

Timing Requirements

t_SFSI

Frame Sync Setup Before SPT_CLK

17

14.5

ns

(Externally Generated Frame Sync in Either

Transmit or Receive Mode)¹

t_HFSI

Frame Sync Hold After SPT_CLK

(Externally Generated Frame Sync in Either

Transmit or Receive Mode)¹

–0.5

ns

t_SDRI

t_HDRI

Receive Data Setup Before SPT_CLK¹

Receive Data Hold After SPT_CLK¹

6.5

1.5

5

1

ns

Switching Characteristics

t_DFSI

Frame Sync Delay After SPT_CLK (Internally

2

ns

Generated Frame Sync in Transmit or

Receive Mode)²

t_HOFSI

Frame Sync Hold After SPT_CLK (Internally –4.5

Generated Frame Sync in Transmit or

Receive Mode)²

Transmit Data Delay After SPT_CLK²

Transmit Data Hold After SPT_CLK²

SPT_CLK Width³

SPT_CLK Period³

–3.5

t_DDTI

ns

t_HDTI

–5

t_SCLKIW

0.5 × t_SPTCLKPROG– 1.5

t_SPTCLKPROG– 1.5

0.5 × t_SPTCLKPROG– 1.5

t_SPTCLKPROG– 1.5

t_SPTCLKI

¹Referenced to the sample edge.

²Referenced to drive edge.

³See Table 18 on Page 52 in Clock Related Operating Conditions for details on the minimum period that may be programmed for t_SPTCLKPROG

.

Rev. A

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Page 80 of 116

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DATA RECEIVE—INTERNAL CLOCK

DATA RECEIVE—EXTERNAL CLOCK

DRIVE EDGE SAMPLE EDGE

t_SCLKIW

t_SCLKW

SPT_A/BCLK

(SPORT CLOCK)

SPT_A/BCLK

(SPORT CLOCK)

t_DFSI

t_DFSE

t_HOFSI

t_SFSI

t_HFSI

t_HOFSE

t_SFSE

t_HFSE

SPT_A/BFS

(FRAME SYNC)

SPT_A/BFS

(FRAME SYNC)

t_SDRI

t_HDRI

t_SDRE

t_HDRE

SPT_A/BDx

(DATA CHANNEL A/B)

SPT_A/BDx

(DATA CHANNEL A/B)

DATA TRANSMIT—INTERNAL CLOCK

DRIVE EDGE SAMPLE EDGE

DATA TRANSMIT—EXTERNAL CLOCK

DRIVE EDGE SAMPLE EDGE

t_SCLKIW

t_SCLKW

SPT_A/BCLK

(SPORT CLOCK)

SPT_A/BCLK

(SPORT CLOCK)

t_DFSI

t_DFSE

t_HOFSI

t_SFSI

t_HFSI

t_HOFSE

t_SFSE

t_HFSE

SPT_A/BFS

(FRAME SYNC)

SPT_A/BFS

(FRAME SYNC)

t_DDTI

t_DDTE

t_HDTI

t_HDTE

SPT_A/BDx

(DATA CHANNEL A/B)

SPT_A/BDx

(DATA CHANNEL A/B)

Figure 27. Serial Ports

Rev. A

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Table 51. Serial Ports—Enable and Three-State

V_{DD_EXT}

1.8V Nominal

V_{DD_EXT}

3.3V Nominal

Parameter

Switching Characteristics

Min

1

Max

Min

1

Max

Unit

t_DDTEN

t_DDTTE

t_DDTIN

t_DDTTI

Data Enable from External Transmit SPT_CLK¹

ns

Data Disable from External Transmit SPT_CLK¹

Data Enable from Internal Transmit SPT_CLK¹

Data Disable from Internal Transmit SPT_CLK¹

14

–1.12

–1

2.8

¹Referenced to drive edge.

DRIVE EDGE

SPT_CLK

(SPORT CLOCK

EXTERNAL)

t_DDTEN

t_DDTTE

SPT_A/BDx

(DATA

CHANNEL A/B)

DRIVE EDGE

SPT_CLK

(SPORT CLOCK

INTERNAL)

t_DDTIN

t_DDTTI

SPT_A/BDx

(DATA

CHANNEL A/B)

Figure 28. Serial Ports—Enable and Three-State

Rev. A

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The SPT_TDV output signal becomes active in SPORT multichannel mode. During transmit slots (enabled with active channel selection

registers) the SPT_TDV is asserted for communication with external devices.

Table 52. Serial Ports—Transmit Data Valid (TDV)

V_{DD_EXT}

1.8V Nominal

Max

V_{DD_EXT}

3.3V Nominal

Parameter

Switching Characteristics

Min

2.5

Max

Unit

t_DRDVEN

t_DFDVEN

t_DRDVIN

t_DFDVIN

Data-Valid Enable Delay from Drive Edge of External Clock¹2.5

Data-Valid Disable Delay from Drive Edge of External Clock¹

Data-Valid Enable Delay from Drive Edge of Internal Clock¹–4.5

ns

17.5

2

14.5

2

–3.5

Data-Valid Disable Delay from Drive Edge of Internal Clock¹

¹Referenced to drive edge.

DRIVE EDGE

SPT_CLK

(SPORT CLOCK

EXTERNAL)

t_DRDVEN

t_DFDVEN

SPT_A/BTDV

DRIVE EDGE

SPT_CLK

(SPORT CLOCK

INTERNAL)

t_DRDVIN

t_DFDVIN

SPT_A/BTDV

Figure 29. Serial Ports—Transmit Data Valid Internal and External Clock

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Table 53. Serial Ports—External Late Frame Sync

V_{DD_EXT}

1.8V Nominal

V_{DD_EXT}

3.3V Nominal

Parameter

Min

Max

Min

Max

Unit

Switching Characteristics

t_DDTLFSE

Data Delay from Late External Transmit Frame Sync or External

19

15.5

ns

Receive Frame Sync with MCE = 1, MFD = 0¹

Data Enable for MCE = 1, MFD = 0¹

t_DDTENFS

0.5

ns

¹The t_DDTLFSEand t_DDTENFSparameters apply to left-justified as well as standard serial mode, and MCE = 1, MFD = 0.

DRIVE

SAMPLE

DRIVE

SPT_A/BCLK

(SPORT CLOCK)

t_HFSE/I

t_SFSE/I

SPT_A/BFS

(FRAME SYNC)

t_DDTE/I

t_DDTENFS

t_HDTE/I

SPT_A/BDx

(DATA CHANNEL A/B)

1ST BIT

2ND BIT

t_DDTLFSE

Figure 30. External Late Frame Sync

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Serial Peripheral Interface (SPI) Port—Master Timing

Table 54 and Figure 31 describe serial peripheral interface (SPI) port master operations.

When internally generated, the programmed SPI clock (f_SPICLKPROG) frequency in MHz is set by the following equation where BAUD is a

field in the SPI_CLK register that can be set from 0 to 65,535:

f

SCLK0

f

= -------------------------------

SPICLKPROG

BAUD + 1

1

t

= ---------------------------------

SPICLKPROG

f

SPICLKPROG

Note that:

• In dual mode data transmit, the SPI_MISO signal is also an output.

• In quad mode data transmit, the SPI_MISO, SPI_D2, and SPI_D3 signals are also outputs.

• In dual mode data receive, the SPI_MOSI signal is also an input.

• In quad mode data receive, the SPI_MOSI, SPI_D2, and SPI_D3 signals are also inputs.

• To add additional frame delays, see the documentation for the SPI_DLY register in the hardware reference manual.

Table 54. Serial Peripheral Interface (SPI) Port—Master Timing

V_{DD_EXT}

1.8V Nominal

V_{DD_EXT}

3.3V Nominal

Parameter

Min

Max

Min

Max

Unit

Timing Requirements

t_SSPIDM

Data Input Valid to SPI_CLK Edge(DataInput 6.5

Setup)

SPI_CLK Sampling Edge to Data Input Invalid 1

Switching Characteristics

5.5

1

ns

t_HSPIDM

t_SDSCIM

t_SPICHM

t_SPICLM

t_SPICLK

SPI_SEL low to First SPI_CLK Edge

SPI_CLK High Period¹

SPI_CLK Low Period¹

SPI_CLK Period¹

0.5 × t_SCLK0– 2.5

0.5 × t_SCLK0– 1.5

ns

0.5 × t_SPICLKPROG– 1.5

t_SPICLKPROG– 1.5

0.5 × t_SPICLKPROG– 1.5

t_SPICLKPROG– 1.5

t_HDSM

Last SPI_CLK Edge to SPI_SEL High

Sequential Transfer Delay²

(0.5 × t_SCLK0) –2.5

(STOP × t_SPICLK) –1.5

(0.5 × t_SCLK0) –1.5

(STOP × t_SPICLK) –1.5

t_SPITDM

t_DDSPIDM

SPI_CLK Edge to Data Out Valid (Data Out

Delay)

2.5

2

t_HDSPIDM

SPI_CLK Edge to Data Out Invalid (Data Out –4.5

Hold)

–3.5

ns

¹See Table 18 on Page 52 in Clock Related Operating Conditions for details on the minimum period that may be programmed for t_SPICLKPROG

.

²STOP value set using the SPI_DLY.STOP bits.

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SPI_SEL

(OUTPUT)

t_SDSCIM

t_SPICLM

t_SPICHM

t_SPICLK

t_HDSM

t_SPITDM

SPI_CLK

(OUTPUT)

t_HDSPIDM

t_DDSPIDM

DATA OUTPUTS

(SPI_MOSI)

t_SSPIDM

CPHA = 1

t_HSPIDM

DATA INPUTS

(SPI_MISO)

t_HDSPIDM

t_DDSPIDM

DATA OUTPUTS

(SPI_MOSI)

t_SSPIDM

t_HSPIDM

CPHA = 0

DATA INPUTS

(SPI_MISO)

Figure 31. Serial Peripheral Interface (SPI) Port—Master Timing

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Serial Peripheral Interface (SPI) Port—Slave Timing

Table 55 and Figure 32 describe serial peripheral interface (SPI) port slave operations. Note that:

• In dual mode data transmit, the SPI_MOSI signal is also an output.

• In quad mode data transmit, the SPI_MOSI, SPI_D2, and SPI_D3 signals are also outputs.

• In dual mode data receive, the SPI_MISO signal is also an input.

• In quad mode data receive, the SPI_MISO, SPI_D2, and SPI_D3 signals are also inputs.

• In SPI slave mode, the SPI clock is supplied externally and is called f_SPICLKEXT

:

1

t

= -----------------------------

SPICLKEXT

f

SPICLKEXT

Table 55. Serial Peripheral Interface (SPI) Port—Slave Timing

V_{DD_EXT}

1.8V Nominal

V_{DD_EXT}

3.3V Nominal

Parameter

Min

Max

Min

Max

Unit

Timing Requirements

t_SPICHS

t_SPICLS

t_SPICLK

t_HDS

SPI_CLK High Period¹

SPI_CLK Low Period¹

SPI_CLK Period¹

(0.5 × t_SPICLKEXT) – 1.5

t_SPICLKEXT– 1.5

5

ns

(0.5 × t_SPICLKEXT) – 1.5

t_SPICLKEXT– 1.5

5

Last SPI_CLK Edge to SPI_SS Not Asserted

(NonSPIHP)

t_HDS

Last SPI_CLK Edge to SPI_SS Not Asserted 

1.5 × t_SCLK0

ns

(Using SPIHP)

t_SPITDS

t_SDSCI

t_SSPID

Sequential Transfer Delay (NonSPIHP)

Sequential Transfer Delay (Using SPIHP)

SPI_SS Assertion to First SPI_CLK Edge

0.5 × t_SPICLK– 1.5

3 × t_SCLK0

11.5

0.5 × t_SPICLK– 1.5

ns

3 × t_SCLK0

11.5

1

Data Input Valid to SPI_CLK Edge (Data Input

Setup)

1.5

t_HSPID

SPI_CLK Sampling Edge to Data Input Invalid

3.3

3

ns

Switching Characteristics

t_DSOE

SPI_SS Assertion to Data Out Active

0

17.5

13

0

14.5

11.5

14.5

ns

t_DSDHI

t_DDSPID

t_HDSPID

SPI_SS Deassertion to Data High Impedance

SPI_CLK Edge to Data Out Valid (Data Out Delay)

17.5

SPI_CLK Edge to Data Out Invalid (Data Out Hold) 2.5

2.5

¹This specification indicates the minimum instantaneous width or period that can be tolerated due to duty cycle variation or jitter on the external SPI_CLK. For the external

SPI_CLK ideal maximum frequency see the f_SPICLKTEXTspecification in Table 18 on Page 52 of Clock Related Operating Conditions.

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SPI_SS

(INPUT)

t_SDSCI

t_SPICLS

t_SPICHS

t_SPICLK

t_HDS

t_SPITDS

SPI_CLK

(INPUT)

t_DSOE

t_DDSPID

t_HDSPID

t_DDSPID

t_DSDHI

DATA OUTPUTS

(SPI_MISO)

CPHA = 1

t_SSPID

t_HSPID

DATA INPUTS

(SPI_MOSI)

t_DSOE

t_HDSPID

t_DDSPID

t_DSDHI

DATA OUTPUTS

(SPI_MISO)

t_HSPID

CPHA = 0

t_SSPID

DATA INPUTS

(SPI_MOSI)

Figure 32. Serial Peripheral Interface (SPI) Port—Slave Timing

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Serial Peripheral Interface (SPI) Port—SPI_RDY Slave Timing

Table 56. SPI Port—SPI_RDY Slave Timing

V_{DD_EXT}

1.8 V/3.3V Nominal

Parameter

Min

Max

Unit

Switching Characteristics

t_DSPISCKRDYSRSPI_RDY De-assertion from Valid Input SPI_CLK Edge in Slave Mode Receive 2.5 × t_SCLK0+ t_HDSPID3.5 × t_SCLK0+ t_DDSPIDns

t_DSPISCKRDYSTSPI_RDY De-assertion from Valid Input SPI_CLK Edge in Slave Mode Transmit 3.5 × t_SCLK0+ t_HDSPID4.5 × t_SCLK0+ t_DDSPIDns

t_DSPISCKRDYSR

SPI_CLK

(CPOL = 0)

CPHA = 0

SPI_CLK

(CPOL = 1)

SPI_CLK

(CPOL = 0)

CPHA = 1

SPI_CLK

(CPOL = 1)

SPI_RDY (O)

Figure 33. SPI_RDY De-assertion from Valid Input SPI_CLK Edge in Slave Mode Receive (FCCH = 0)

t_DSPISCKRDYST

SPI_CLK

(CPOL = 1)

CPHA = 0

SPI_CLK

(CPOL = 0)

SPI_CLK

(CPOL = 1)

CPHA = 1

SPI_CLK

(CPOL = 0)

SPI_RDY (O)

Figure 34. SPI_RDY De-assertion from Valid Input SPI_CLK Edge in Slave Mode Transmit (FCCH = 1)

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Serial Peripheral Interface (SPI) Port—Open Drain Mode (ODM) Timing

In Figure 35 and Figure 36, the outputs can be SPI_MOSI SPI_MISO, SPI_D2, and/or SPI_D3 depending on the mode of operation.

Table 57. SPI Port ODM Master Mode Timing

V_{DD_EXT}

1.8V Nominal

V_{DD_EXT}

3.3V Nominal

Parameter

Min

Max

Min

Max

Unit

Switching Characteristics

t_HDSPIODMM

t_DDSPIODMM

SPI_CLK Edge to High Impedance from Data Out Valid

–4.5

–3.5

ns

SPI_CLK Edge to Data Out Valid from High Impedance

2.5

2

t_HDSPIODMM

SPI_CLK

(CPOL = 0)

SPI_CLK

(CPOL = 1)

OUTPUT

(CPHA = 1)

OUTPUT

(CPHA = 0)

t_DDSPIODMM

Figure 35. ODM Master

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Table 58. SPI Port—ODM Slave Mode

V_{DD_EXT}

1.8V Nominal

V_{DD_EXT}

3.3V Nominal

Parameter

Min

Max

Min

Max

Unit

Switching Characteristics

t_HDSPIODMS

t_DDSPIODMS

SPI_CLK Edge to High Impedance from Data Out Valid

2.5

ns

SPI_CLK Edge to Data Out Valid from High Impedance

17.5

14.5

t_HDSPIODMS

SPI_CLK

(CPOL = 0)

SPI_CLK

(CPOL = 1)

OUTPUT

(CPHA = 1)

OUTPUT

(CPHA = 0)

t_DDSPIODMS

Figure 36. ODM Slave

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Serial Peripheral Interface (SPI) Port—SPI_RDY Timing

SPI_RDY is used to provide flow control. The CPOL and CPHA bits are set in SPI_CTL, while LEADX, LAGX, and STOP are in 

SPI_DLY.

Table 59. SPI Port—SPI_RDY Timing

V_{DD_EXT}

1.8 V/3.3V Nominal

Parameter

Min

Max

Unit

Timing Requirements

t_SRDYSCKM0Minimum Setup Time for SPI_RDY De-assertion in (2.5 + 1.5 × BAUD¹) × t_SCLK0+ 14.5

Master Mode Before Last SPI_CLK Edge of Valid

Data Transfer to Block Subsequent Transfer with

CPHA = 0

ns

t_SRDYSCKM1Minimum Setup Time for SPI_RDY De-assertion in (2.5 + BAUD¹) × t_SCLK0+ 14.5

Master Mode Before Last SPI_CLK Edge of Valid

Data Transfer to Block Subsequent Transfer with

CPHA = 1

ns

Switching Characteristic

t_SRDYSCKM

Time Between Assertion of SPI_RDY by Slave and 3 × t_SCLK0

First Edge of SPI_CLK for New SPI Transfer with

4 × t_SCLK0+ 17.5

ns

CPHA = 0 and BAUD = 0 (STOP, LEADX, LAGX = 0)

Time Between Assertion of SPI_RDY by Slave and (4 + 1.5 × BAUD¹) × t_SCLK0

First Edge of SPI_CLK for New SPI Transfer with

CPHA = 0 and BAUD ≥ 1 (STOP, LEADX, LAGX = 0)

Time Between Assertion of SPI_RDY by Slave and (3 + 0.5 × BAUD¹) × t_SCLK0

First Edge of SPI_CLK for New SPI Transfer with

(5 + 1.5 × BAUD¹) × t_SCLK0+ 17.5 ns

(4 + 0.5 × BAUD¹) × t_SCLK0+ 17.5 ns

CPHA = 1 (STOP, LEADX, LAGX = 0)

¹BAUD value set using the SPI_CLK.BAUD bits.

t_SRDYSCKM0

SPI_RDY

SPI_CLK

(CPOL = 0)

SPI_CLK

(CPOL = 1)

Figure 37. SPI_RDY Setup Before SPI_CLK with CPHA = 0

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t_SRDYSCKM1

SPI_RDY

SPI_CLK

(CPOL = 0)

SPI_CLK

(CPOL = 1)

Figure 38. SPI_RDY Setup Before SPI_CLK with CPHA = 1

t_SRDYSCKM

SPI_RDY

SPI_CLK

(CPOL = 0)

SPI_CLK

(CPOL = 1)

Figure 39. SPI_CLK Switching Diagram after SPI_RDY Assertion, CPHA = x

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Enhanced Parallel Peripheral Interface Timing

The following tables and figures describe enhanced parallel peripheral interface timing operations. The POLC bits in the EPPI_CTL

register may be used to set the sampling/driving edges of the EPPI clock.

When internally generated, the programmed PPI clock (f_PCLKPROG) frequency in MHz is set by the following equation where VALUE is a

field in the EPPI_CLKDIV register that can be set from 0 to 65,535:

f_SCLK0

f_PCLKPROG= --------------------------------

VALUE + 1

1

t_PCLKPROG= ------------------------

f_PCLKPROG

When externally generated the EPPI_CLK is called f_PCLKEXT

:

1

t_PCLKEXT= ---------------------

f_PCLKEXT

Table 60. Enhanced Parallel Peripheral Interface—Internal Clock

V_{DD_EXT}

1.8V Nominal

V_{DD_EXT}

3.3V Nominal

Parameter

Min

Max

Min

Max

Unit

Timing Requirements

t_SFSPI

t_HFSPI

t_SDRPI

t_HDRPI

t_SFS3GI

External FS Setup Before EPPI_CLK

6.5

1.5

6.4

1

5

ns

External FS Hold After EPPI_CLK

Receive Data Setup Before EPPI_CLK

Receive Data Hold After EPPI_CLK

1

5

1

External FS3 Input Setup Before EPPI_CLK 16.5

Fall Edge in Clock Gating Mode

14

t_HFS3GI

External FS3 Input Hold Before EPPI_CLK 1.5

Fall Edge in Clock Gating Mode

0

ns

Switching Characteristics

t_PCLKW

t_PCLK

EPPI_CLK Width¹

0.5 × t_PCLKPROG– 2

t_PCLKPROG– 2

ns

EPPI_CLK Period¹

t_PCLKPROG– 2

t_DFSPI

t_HOFSPI

t_DDTPI

t_HDTPI

Internal FS Delay After EPPI_CLK

Internal FS Hold After EPPI_CLK

Transmit Data Delay After EPPI_CLK

Transmit Data Hold After EPPI_CLK

2

–4

–3

¹See Table 18 on Page 52 in Clock Related Operating Conditions for details on the minimum period that may be programmed for t_PCLKPROG

.

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FRAME SYNC

DRIVEN

DATA

SAMPLED

POLC[1:0] = 10

EPPI_CLK

POLC[1:0] = 01

t_DFSPI

t_PCLKW

t_HOFSPI

t_PCLK

EPPI_FS1/2

EPPI_Dx

t_SDRPI

t_HDRPI

Figure 40. PPI Internal Clock GP Receive Mode with Internal Frame Sync Timing

FRAME SYNC

DRIVEN

DATA

DRIVEN

DATA

DRIVEN

t_PCLK

POLC[1:0] = 11

EPPI_CLK

POLC[1:0] = 00

t_DFSPI

t_PCLKW

t_HOFSPI

EPPI_FS1/2

EPPI_Dx

t_HDTPI

t_DDTPI

Figure 41. PPI Internal Clock GP Transmit Mode with Internal Frame Sync Timing

DATA SAMPLED /

FRAME SYNC SAMPLED

POLC[1:0] = 11

EPPI_CLK

POLC[1:0] = 00

t_PCLKW

t_SFSPI

t_HFSPI

t_PCLK

EPPI_FS1/2

EPPI_Dx

t_SDRPI

t_HDRPI

Figure 42. PPI Internal Clock GP Receive Mode with External Frame Sync Timing

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DATA DRIVEN /

FRAME SYNC SAMPLED

POLC[1:0] = 11

EPPI_CLK

POLC[1:0] = 00

t_SFSPI

t_HFSPI

t_PCLKW

t_PCLK

EPPI_FS1/2

EPPI_Dx

t_DDTPI

t_HDTPI

Figure 43. PPI Internal Clock GP Transmit Mode with External Frame Sync Timing

EPPI_CLK

EPPI_FS3

t_HFS3GI

t_SFS3GI

Figure 44. Clock Gating Mode with Internal Clock and External Frame Sync Timing

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Table 61. Enhanced Parallel Peripheral Interface—External Clock

V_{DD_EXT}

1.8V Nominal

V_{DD_EXT}

3.3V Nominal

Parameter

Min

Max

Min

Max

Unit

Timing Requirements

t_PCLKW

t_PCLK

EPPI_CLK Width¹

(0.5 × t_PCLKEXT) – 1

ns

EPPI_CLK Period¹

t_PCLKEXT– 1

t_SFSPE

t_HFSPE

t_SDRPE

t_HDRPE

External FS Setup Before EPPI_CLK

External FS Hold After EPPI_CLK

Receive Data Setup Before EPPI_CLK

Receive Data Hold After EPPI_CLK

1.5

3.3

1

3

1

3

Switching Characteristics

t_DFSPE

t_HOFSPE

t_DDTPE

t_HDTPE

Internal FS Delay After EPPI_CLK

17.5

14.5

ns

Internal FS Hold After EPPI_CLK

Transmit Data Delay After EPPI_CLK

Transmit Data Hold After EPPI_CLK

2.5

¹This specification indicates the minimum instantaneous width or period that can be tolerated due to duty cycle variation or jitter on the external EPPI_CLK. For the external

EPPI_CLK ideal maximum frequency, see the f_PCLKEXTspecification in Table 18 on Page 52 in Clock Related Operating Conditions.

FRAME SYNC

DRIVEN

DATA

SAMPLED

POLC[1:0] = 10

EPPI_CLK

POLC[1:0] = 01

t_DFSPE

t_PCLKW

t_HOFSPE

t_PCLK

EPPI_FS1/2

EPPI_Dx

t_SDRPE

t_HDRPE

Figure 45. PPI External Clock GP Receive Mode with Internal Frame Sync Timing

FRAME SYNC

DRIVEN

DATA

DRIVEN

DATA

DRIVEN

t_PCLK

POLC[1:0] = 11

EPPI_CLK

POLC[1:0] = 00

t_DFSPE

t_PCLKW

t_HOFSPE

EPPI_FS1/2

EPPI_Dx

t_DDTPE

t_HDTPE

Figure 46. PPI External Clock GP Transmit Mode with Internal Frame Sync Timing

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DATA SAMPLED/

FRAME SYNC SAMPLED

POLC[1:0] = 11

EPPI_CLK

POLC[1:0] = 00

t_PCLKW

t_SFSPE

t_HFSPE

t_PCLK

EPPI_FS1/2

EPPI_Dx

t_SDRPE

t_HDRPE

Figure 47. PPI External Clock GP Receive Mode with External Frame Sync Timing

DATA DRIVEN/

FRAME SYNC SAMPLED

POLC[1:0] = 11

EPPI_CLK

POLC[1:0] = 00

t_SFSPE

t_HFSPE

t_PCLKW

t_PCLK

EPPI_FS1/2

EPPI_Dx

t_DDTPE

t_HDTPE

Figure 48. PPI External Clock GP Transmit Mode with External Frame Sync Timing

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Universal Asynchronous Receiver-Transmitter 

(UART) Ports—Receive and Transmit Timing

The universal asynchronous receiver-transmitter (UART) ports receive and transmit operations are described in the ADSP-BF70x

Blackfin+ Processor Hardware Reference.

Controller Area Network (CAN) Interface

The controller area network (CAN) interface timing is described in the ADSP-BF70x Blackfin+ Processor Hardware Reference.

Universal Serial Bus (USB) On-The-Go—Receive and Transmit Timing

Table 62 describes the universal serial bus (USB) on-the-go receive and transmit operations.

Table 62. USB On-The-Go—Receive and Transmit Timing

V_{DD_USB}

3.3V Nominal

Parameter

Min

Max

Unit

Timing Requirements

f_USBS

fs_USB

USB_XI Frequency

24

MHz

ppm

USB_XI Clock Frequency Stability

–50

+50

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Mobile Storage Interface (MSI) Controller Timing

Table 64 and Figure 49 show I/O timing, related to the mobile storage interface (MSI).

The MSI timing depends on the period of the input clock that has been routed to the MSI peripheral (t_MSICLKIN) by setting the 

MSI0_UHS_EXT register. See Table 63 for this information.

Table 63. t_MSICLKINSettings

EXT_CLK_MUX_CTRL[31:30] t_MSICLKIN

00

01

10

t_SCLK0× 2

t_SCLK0

t_SCLK1× 3

1

t_MSICLKIN= ----------------------

f_MSICLKIN

(f_MSICLKPROG) frequency in MHz is set by the following equation where DIV0 is a field in the MSI_CLKDIV register that can be set from 0 to

255. When DIV0 is set between 1 and 255, the following equation is used to determine f_MSICLKPROG

:

f

f_MSICLKPROG= --^M-----^S--^I--^C----^L---^K---^I--^N--

DIV0  2

When DIV0 = 0,

f_MSICLKPROG= f_MSICLKIN

Also note the following:

1

t_MSICLKPROG= -----------------------------

f_MSICLKPROG

Table 64. MSI Controller Timing

V_{DD_EXT}

1.8V Nominal

V_{DD_EXT}

3.3V Nominal

Parameter

Min

Max

Min

Max

Unit

Timing Requirements

t_ISU

t_IH

Input Setup Time

Input Hold Time

5.5

2

4.7

0.5

ns

Switching Characteristics

t_MSICLKClock Period Data Transfer Mode¹

t_MSICLKPROG– 1.5

7

t_MSICLKPROG– 1.5

7

ns

t_WL

Clock Low Time

Clock High Time

Clock Rise Time

Clock Fall Time

t_WH

t_TLH

t_THL

3

t_ODLYOutput Delay Time During Data Transfer Mode

t_OHOutput Hold Time

(0.5 × t_MSICLKIN) + 3.2

(0.5 × t_MSICLKIN) + 3 ns

ns

(0.5 × t_MSICLKIN) – 4

(0.5 × t_MSICLKIN) – 3

¹See Table 18 on Page 52 in Clock Related Operating Conditions for details on the minimum period that may be programmed for t_MSICLKPROG

.

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V_{OH (MIN)}

t_MSICLK

MSI_CLK

INPUT

t_THL

t_TLH

t_ISU

t_IH

V_{OL (MAX)}

t_WL

t_WH

t_ODLY

t_OH

OUTPUT

NOTES:

1 INPUT INCLUDES MSI_Dx AND MSI_CMD SIGNALS.

2 OUTPUT INCLUDES MSI_Dx AND MSI_CMD SIGNALS.

Figure 49. MSI Controller Timing

Rev. A

|

Page 101 of 116

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September 2015

ADSP-BF700/701/702/703/704/705/706/707

OUTPUT DRIVE CURRENTS

0

Figure 50 through Figure 61 show typical current-voltage char-

–2

acteristics for the output drivers of the ADSP-BF70x Blackfin

–4

processors. The curves represent the current drive capability of

the output drivers as a function of output voltage.

V

OL

–6

V

= 1.7V @ 125°C

= 1.8V @ 25°C

DD_EXT

25

20

–8

–10

–12

–14

–16

V

= 1.9V @ –40°C

= 1.8V @ 25°C

= 1.7V @ 125°C

DD_EXT

V

OH

15

10

5

V

= 1.9V @ –40°C

2.0

DD_EXT

1.5

0

V

OL

–5

0

0.5

1.0

2.5

4.0

2.0

SOURCE VOLTAGE (V)

–10

–15

–20

–25

–30

Figure 52. Driver Type D Current (1.8 V V_{DD_EXT}

)

V

= 1.9V @ –40°C

= 1.8V @ 25°C

= 1.7V @ 125°C

DD_EXT

5

0

–5

0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8 2.0

SOURCE VOLTAGE (V)

–10

–15

–20

–25

–30

–35

–40

–45

–50

V

OL

Figure 50. Driver Type A Current (1.8 V V_{DD_EXT}

)

60

40

V

= 3.13V @ 125°C

DD_EXT

V

= 3.47V @ –40°C

= 3.30V @ 25°C

= 3.13V @ 125°C

DD_EXT

V

= 3.30V @ 25°C

= 3.47V @ –40°C

OH

DD_EXT

20

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

V

OL

SOURCE VOLTAGE (V)

–20

–40

–60

Figure 53. Driver Type D Current (3.3 V V_{DD_EXT}

)

V

= 3.47V @ –40°C

= 3.30V @ 25°C

= 3.13V @ 125°C

DD_EXT

5

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

SOURCE VOLTAGE (V)

–5

V

OL

V

= 1.7V @ 125°C

= 1.8V @ 25°C

= 1.9V @ –40°C

Figure 51. Driver Type A Current (3.3 V V_{DD_EXT}

)

DD_DMC

–10

–15

–20

–25

–30

–35

0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

SOURCE VOLTAGE (V)

Figure 54. Driver Type B and Driver Type C (DDR Drive Strength 34 Ω)

Rev. A

|

Page 102 of 116

|

September 2015

ADSP-BF700/701/702/703/704/705/706/707

5

0

35

V

= 1.7V @ 125°C

= 1.8V @ 25°C

= 1.9V @ –40°C

DD_DMC

30

25

20

15

10

5

V

OL

–5

V

= 1.7V @ 125°C

= 1.8V @ 25°C

= 1.9V @ –40°C

DD_DMC

–10

–15

–20

–25

–30

V

OH

0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

SOURCE VOLTAGE (V)

Figure 55. Driver Type B and Driver Type C (DDR Drive Strength 40 Ω)

Figure 58. Driver Type B and Driver Type C (DDR Drive Strength 34 Ω)

5

30

V

= 1.7V @ 125°C

= 1.8V @ 25°C

= 1.9V @ –40°C

DD_DMC

0

25

20

15

10

5

V

OL

V

= 1.7V @ 125°C

= 1.8V @ 25°C

= 1.9V @ –40°C

–5

–10

–15

–20

–25

DD_DMC

V

OH

0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

SOURCE VOLTAGE (V)

Figure 56. Driver Type B and Driver Type C (DDR Drive Strength 50 Ω)

Figure 59. Driver Type B and Driver Type C (DDR Drive Strength 40 Ω)

2

0

25

V

= 1.7V @ 125°C

= 1.8V @ 25°C

= 1.9V @ –40°C

DD_DMC

–2

20

15

10

5

V

OL

–4

–6

V

= 1.7V @ 125°C

DD_DMC

V

@ 25°C

= 1.8V

= 1.9V

@ –4 0°C

–8

V

OH

–10

–12

–14

–16

–18

0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

SOURCE VOLTAGE (V)

Figure 57. Driver Type B and Driver Type C (DDR Drive Strength 60 Ω)

Figure 60. Driver Type B and Driver Type C (DDR Drive Strength 50 Ω)

Rev. A

|

Page 103 of 116

|

September 2015

ADSP-BF700/701/702/703/704/705/706/707

The time t_{ENA_MEASURED}is the interval from when the reference

20

18

16

14

12

10

8

V

= 1.7V @ 125°C

= 1.8V @ 25°C

= 1.9V @ –40°C

DD_DMC

signal switches to when the output voltage reaches V_TRIP(high)

or V_TRIP(low). For V_{DD_EXT}(nominal) = 1.8 V, V_TRIP(high) is

1.05 V, and V_TRIP(low) is 0.75 V. For V_{DD_EXT}(nominal) = 3.3 V,

V_TRIP(high) is 1.9 V, and V_TRIP(low) is 1.4 V. Time t_TRIPis the

interval from when the output starts driving to when the output

reaches the V_TRIP(high) or V_TRIP(low) trip voltage.

V

Time t_ENAis calculated as shown in the equation:

OH

t_ENA= t_{ENA_MEASURED}– t_TRIP

6

If multiple balls (such as the data bus) are enabled, the measure-

ment value is that of the first ball to start driving.

4

2

Output Disable Time Measurement

0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

Output balls are considered to be disabled when they stop driv-

ing, go into a high impedance state, and start to decay from their

output high or low voltage. The output disable time t_DISis the

difference between t_{DIS_MEASURED}and t_DECAYas shown on the left

side of Figure 63.

SOURCE VOLTAGE (V)

Figure 61. Driver Type B and Device Driver C (DDR Drive Strength 60 Ω)

TEST CONDITIONS

All timing requirements appearing in this data sheet were mea-

sured under the conditions described in this section. Figure 62

shows the measurement point for ac measurements (except out-

put enable/disable). The measurement point V_MEASis V_{DD_EXT}/2

for V_{DD_EXT}(nominal) = 1.8 V/3.3 V.

t_DIS= t_{DIS_MEASURED}– t_DECAY



The time for the voltage on the bus to decay by ΔV is dependent

on the capacitive load, C_Land the load current, I_L. This decay

time can be approximated by the equation:



t_DECAY= C_LV  I_L

INPUT

OR

OUTPUT

V

MEAS

The time t_DECAYis calculated with test loads C_Land I_L, and with

V equal to 0.25 V for V_{DD_EXT}(nominal) = 3.3 V and 0.15 V for

V_{DD_EXT}(nominal) = 1.8V.

Figure 62. Voltage Reference Levels for AC Measurements

(Except Output Enable/Disable)

The time t_{DIS_MEASURED}is the interval from when the reference

signal switches, to when the output voltage decays ΔV from the

measured output high or output low voltage.

Output Enable Time Measurement

Example System Hold Time Calculation

Output balls are considered to be enabled when they have made

a transition from a high impedance state to the point when they

start driving.

The output enable time t_ENAis the interval from the point when

a reference signal reaches a high or low voltage level to the point

when the output starts driving as shown on the right side of

Figure 63.

To determine the data output hold time in a particular system,

first calculate t_DECAYusing the previous equation. Choose ΔV to

be the difference between the processor’s output voltage and the

input threshold for the device requiring the hold time. C_Lis the

total bus capacitance (per data line), and I_Lis the total leakage or

three-state current (per data line). The hold time will be t_DECAY

plus the various output disable times as specified in the Timing

Specifications on Page 60.

REFERENCE

SIGNAL

t_{DIS_MEASURED}

t_{ENA_MEASURED}

t_DIS

t_ENA

V

OH

V

OH

(MEASURED)

V

(MEASURED) 2 DV

(MEASURED) + DV

OH

V

(HIGH)

TRIP

V

(LOW)

V

TRIP

OL

V

OL

V

OL

(MEASURED)

t_TRIP

t_DECAY

OUTPUT STOPS DRIVING

OUTPUT STARTS DRIVING

HIGH IMPEDANCE STATE

Figure 63. Output Enable/Disable

Rev. A

|

Page 104 of 116

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September 2015

ADSP-BF700/701/702/703/704/705/706/707

Capacitive Loading

35

Output delays and holds are based on standard capacitive loads

of an average of 6 pF on all balls (see Figure 64). V_LOADis equal

to V_{DD_EXT}/2. The graphs of Figure 65 through Figure 68 show

how output rise time varies with capacitance. The delay and

hold specifications given should be derated by a factor derived

from these figures. The graphs in these figures may not be linear

outside the ranges shown.

30

25

20

15

10

5

t_RISE= 3.3V @ 25°C

t_FALL= 3.3V @ 25°C

TESTER PIN ELECTRONICS

50Ω

V

LOAD

T1

DUT

OUTPUT

0

45Ω

0

50

100

150

200

250

70Ω

LOAD CAPACITANCE (pF)

ZO = 50Ω (impedance)

TD = 4.04 1.18 ns

50Ω

Figure 66. Driver Type A Typical Rise and Fall Times (10% to 90%) vs. Load

Capacitance (V_{DD_EXT}= 3.3 V)

0.5pF

4pF

2pF

400Ω

1.4

t_FALL= 1.8V @ 25°C

1.2

1.0

0.8

0.6

0.4

0.2

0

NOTES:

THE WORST CASE TRANSMISSION LINE DELAY IS SHOWN AND CAN BE USED

FOR THE OUTPUT TIMING ANALYSIS TO REFELECT THE TRANSMISSION LINE

EFFECT AND MUST BE CONSIDERED.THE TRANSMISSION LINE (TD) IS FOR

LOAD ONLY AND DOES NOT AFFECT THE DATA SHEET TIMING SPECIFICATIONS.

t_RISE= 1.8V @ 25°C

ANALOG DEVICES RECOMMENDS USING THE IBIS MODEL TIMING FOR A GIVEN

SYSTEM REQUIREMENT. IF NECESSARY, A SYSTEM MAY INCORPORATE

EXTERNAL DRIVERS TO COMPENSATE FOR ANY TIMING DIFFERENCES.

Figure 64. Equivalent Device Loading for AC Measurements

(Includes All Fixtures)

40

35

0

2

4

6

8

10

12

LOAD CAPACITANCE (pF)

t_RISE= 1.8V @ 25°C

Figure 67. Driver Type B & C Typical Rise and Fall Times (10% to 90%)

vs. Load Capacitance (V_{DD_DMC}= 1.8 V)

30

25

0.9

0.8

t_FALL= 1.8V @ 25°C

20

15

10

5

0.7

t_RISE= 1.8V @ 25°C

0.6

t_FALL= 1.8V @ 25°C

0.5

0.4

0.3

0.2

0.1

0

50

100

150

200

250

LOAD CAPACITANCE (pF)

Figure 65. Driver Type A Typical Rise and Fall Times (10% to 90%) vs. Load

Capacitance (V_{DD_EXT}= 1.8 V)

0

2

4

6

8

10

12

LOAD CAPACITANCE (pF)

Figure 68. Driver Type B and Driver Type C Typical Rise and Fall Times

(10% to 90%) vs. Load Capacitance (V_{DD_DMC}= 1.8 V) for LPDDR

Rev. A

|

Page 105 of 116

|

September 2015

ADSP-BF700/701/702/703/704/705/706/707

ENVIRONMENTAL CONDITIONS

To determine the junction temperature on the application

printed circuit board, use the following equation:



T_J= T_CASE+ _JT P_D



where:

T_J= Junction temperature (°C).

T

_CASE= Case temperature (°C) measured by customer at top

center of package.

_JT= From Table 65 and Table 66.

P_D= Power dissipation (see Total Internal Power Dissipation

on Page 56 for the method to calculate P_D).

Values of _JAare provided for package comparison and printed

circuit board design considerations. _JAcan be used for a first

order approximation of T_Jby the equation:



T_J= T_A+ _JA P_D



where:

T_A= Ambient temperature (°C).

Values of _JCare provided for package comparison and printed

circuit board design considerations when an external heat sink

is required.

In Table 65 and Table 66, airflow measurements comply with

JEDEC standards JESD51-2 and JESD51-6. The junction-to-

case measurement complies with MIL-STD-883 (Method

1012.1). All measurements use a 2S2P JEDEC test board.

Table 65. Thermal Characteristics for CSP_BGA

Parameter Condition

Typical Unit

_JA

0 linear m/s air flow

28.7

26.2

25.2

10.1

0.24

0.40

0.51

°C/W

_JMA

_JC

_JT

1 linear m/s air flow

2 linear m/s air flow

0 linear m/s air flow

1 linear m/s air flow

2 linear m/s air flow

Table 66. Thermal Characteristics for LFCSP (QFN)

Parameter Condition Typical Unit

_JA

0 linear m/s air flow

22.9

17.9

16.4

2.26

0.14

0.27

0.30

°C/W

_JMA

_JC

_JT

1 linear m/s air flow

2 linear m/s air flow

0 linear m/s air flow

1 linear m/s air flow

2 linear m/s air flow

Rev. A

|

Page 106 of 116

|

September 2015

ADSP-BF700/701/702/703/704/705/706/707

ADSP-BF70x 184-BALL CSP_BGA BALL ASSIGNMENTS 

(NUMERICAL BY BALL NUMBER)

Figure 69 shows an overview of signal placement on the 

184-ball CSP_BGA.

Table 67 lists the 184-ball CSP_BGA package by ball number for

the ADSP-BF70x. Table 68 lists the 184-ball CSP_BGA package

by signal.

TOP VIEW

GND

A1 BALL

CORNER

2

4

6

8

10 12

11 13

14

H

GND_HADC

I/O SIGNALS

1

3

5

7

9

A

B

C

D

E

F

V

DD_EXT

D

V

DD_INT

D

H

D

V

DD_DMC

G

H

O

R

U

V

DD_HADC

R

O

J

H

K

L

V

DD_OTP

U

M

N

P

V

DD_RTC

V

DD_USB

BOTTOM VIEW

A1 BALL

CORNER

14 12 10

13 11

8

6

4

2

9

7

5

3

1

A

B

C

D

E

F

D

O

D

G

H

R

J

K

L

U

M

N

P

Figure 69. 184-Ball CSP_BGA Configuration

Rev. A

|

Page 107 of 116

|

September 2015

ADSP-BF700/701/702/703/704/705/706/707

Table 67. 184-Ball CSP_BGA Ball Assignment (Numerical by Ball Number)

Ball No. Signal Name

A01

A02

A03

A04

A05

A06

A07

A08

A09

A10

A11

A12

A13

A14

B01

B02

B03

B04

B05

B06

B07

B08

B09

B10

B11

B12

B13

B14

C01

C02

C03

C04

C05

C06

C07

C08

C09

C10

C11

C12

C13

C14

D01

D02

D03

D06

D07

GND

D08

D09

D12

D13

D14

E01

E02

E03

E05

E06

E07

E08

E09

E10

E12

E13

E14

F01

F02

F03

F04

F05

F06

F07

F08

F09

F10

F11

F12

F13

F14

G01

G02

G03

G04

G05

G06

G07

G08

G09

G10

G11

G12

G13

G14

H01

H02

VDD_DMC

PA_08

DMC0_DQ06

DMC0_DQ05

DMC0_A06

DMC0_A05

JTG_TDI

VDD_INT

VDD_DMC

DMC0_VREF

SYS_BMODE0

DMC0_DQ08

DMC0_DQ07

DMC0_A01

DMC0_A02

PC_09

H03

H04

H05

H06

H07

H08

H09

H10

H11

H12

H13

H14

J01

J02

J03

J04

J05

J06

J07

J08

J09

J10

J11

J12

J13

J14

K01

K02

K03

K05

K06

K07

K08

K09

K10

K12

K13

K14

L01

L02

L03

L06

L07

L08

L09

L12

L13

SYS_CLKOUT

VDD_INT

GND

VDD_DMC

PA_10

L14

GND

PC_00

RTC0_CLKIN

PB_15

PB_12

DMC0_A09

DMC0_BA0

DMC0_BA1

DMC0_BA2

DMC0_CAS

DMC0_RAS

DMC0_A13

PA_03

DMC0_CK

DMC0_LDQS

GND

DMC0_A07

DMC0_A08

DMC0_A11

DMC0_A10

DMC0_A12

DMC0_WE

DMC0_CS0

DMC0_ODT

DMC0_CKE

DMC0_DQ00

DMC0_DQ02

DMC0_DQ01

DMC0_DQ04

DMC0_DQ03

JTG_TDO_SWO

JTG_TMS_SWDIO

JTG_TCK_SWCLK

PA_01

SYS_EXTWAKE

PA_02

SYS_NMI

GND

PA_04

PA_05

PA_06

PA_07

SYS_HWRST

SYS_BMODE1

DMC0_A00

DMC0_A04

JTG_TRST

M01

M02

M03

M04

M05

M06

M07

M08

M09

M10

M11

M12

M13

M14

N01

N02

N03

N04

N05

N06

N07

N08

N09

N10

N11

N12

N13

N14

P01

P02

P03

P04

P05

P06

P07

P08

P09

P10

P11

P12

P13

P14

PC_12

USB0_VBUS

USB0_VBC

PB_09

PB_05

PB_04

PB_01

PB_03

DMC0_LDM

SYS_CLKIN

RTC0_XTAL

PB_14

PB_11

PC_14

PC_11

USB0_ID

USB0_DP

PB_08

PB_06

PB_00

HADC0_VIN2

HADC0_VIN1

PA_15

SYS_XTAL

GND

PB_13

PB_10

PC_13

USB0_XTAL

USB0_CLKIN

USB0_DM

PB_07

HADC0_VREFN

HADC0_VREFP

HADC0_VIN3

HADC0_VIN0

PA_14

PA_11

DMC0_UDQS

PC_05

PC_06

SYS_RESOUT

VDD_INT

VDD_RTC

GND

VDD_INT

GND

GND_HADC

VDD_OTP

PA_13

DMC0_DQ13

DMC0_UDQS

PC_04

GND

VDD_DMC

SYS_FAULT

DMC0_DQ10

DMC0_DQ09

DMC0_A03

PA_00

PC_08

VDD_INT

GND

VDD_DMC

PA_09

DMC0_DQ11

DMC0_DQ12

PC_07

PC_01

PC_02

VDD_EXT

VDD_HADC

PA_12

DMC0_DQ15

DMC0_DQ14

PC_03

TWI0_SDA

TWI0_SCL

VDD_USB

VDD_EXT

PB_02

GND

VDD_DMC

PC_10

DMC0_UDM

Rev. A

|

Page 108 of 116

|

September 2015

ADSP-BF700/701/702/703/704/705/706/707

Table 68. ADSP-BF70x 184-Ball CSP_BGA Ball Assignments (Alphabetical by Signal Name)

Signal Name

DMC0_A00

DMC0_A01

DMC0_A02

DMC0_A03

DMC0_A04

DMC0_A05

DMC0_A06

DMC0_A07

DMC0_A08

DMC0_A09

DMC0_A10

DMC0_A11

DMC0_A12

DMC0_A13

DMC0_BA0

DMC0_BA1

DMC0_BA2

DMC0_CAS

DMC0_CK

Ball No. Signal Name Ball No. Signal Name Ball No. Signal Name

Ball No.

C13

C07

J03

D01

F01

F02

G01

D02

E02

E01

B01

B02

A02

B04

B03

B05

A08

A03

A04

A05

A06

A10

B09

A11

B07

B10

B12

B11

B14

B13

D14

D13

E14

E13

F14

F13

G13

G14

J13

DMC0_WE

GND

B06

C08

A01

A14

F06

F07

F08

F09

G05

G06

G07

G08

G09

G10

H05

H06

H07

H08

H09

H10

J06

PA_08

PA_09

PA_10

PA_11

PA_12

PA_13

PA_14

PA_15

PB_00

PB_01

PB_02

PB_03

PB_04

PB_05

PB_06

PB_07

PB_08

PB_09

PB_10

PB_11

PB_12

PB_13

PB_14

PB_15

PC_00

PC_01

PC_02

PC_03

PC_04

PC_05

PC_06

PC_07

D12

G12

H12

H13

K12

J12

P13

N13

N10

M11

L12

M12

M10

M09

N09

P08

N08

M08

P03

N03

M04

P02

N02

M03

M01

K02

K03

L01

SYS_HWRST

SYS_NMI

SYS_RESOUT

SYS_XTAL

TWI0_SCL

TWI0_SDA

USB0_CLKIN

USB0_DM

USB0_DP

USB0_ID

N14

L03

L02

P06

P07

N07

N06

M07

M06

P05

D06

D07

D08

D09

E06

E07

E08

E09

F10

F11

G11

H11

K05

K06

K07

K08

K09

L07

L08

L09

K10

E05

F04

F05

G04

H04

J04

USB0_VBC

USB0_VBUS

USB0_XTAL

VDD_DMC

VDD_EXT

VDD_HADC

VDD_INT

DMC0_CKE

DMC0_CK

DMC0_CS0

DMC0_DQ00

DMC0_DQ01

DMC0_DQ02

DMC0_DQ03

DMC0_DQ04

DMC0_DQ05

DMC0_DQ06

DMC0_DQ07

DMC0_DQ08

DMC0_DQ09

DMC0_DQ10

DMC0_DQ11

DMC0_DQ12

DMC0_DQ13

DMC0_DQ14

DMC0_DQ15

DMC0_LDM

DMC0_LDQS

DMC0_ODT

DMC0_RAS

DMC0_UDM

DMC0_UDQS

DMC0_VREF

J07

J08

J09

L14

P01

P14

J10

GND

GND_HADC

HADC0_VIN0

HADC0_VIN1

HADC0_VIN2

HADC0_VIN3

HADC0_VREFN

HADC0_VREFP

JTG_TCK_SWCLK

JTG_TDI

JTG_TDO_SWO

JTG_TMS_SWDIO

JTG_TRST

PA_00

P12

N12

N11

P11

P09

P10

C03

E03

C01

C02

D03

G02

C04

C06

A09

C09

C10

C11

C12

K01

J01

J02

H01

G03

F03

H02

N05

M05

P04

N04

M02

N01

E12

C14

M14

H03

C05

F12

PC_08

PC_09

PC_10

PC_11

VDD_INT

K14

K13

M13

A12

A13

B08

A07

L13

J14

PC_12

PC_13

PC_14

VDD_INT

VDD_OTP

VDD_RTC

VDD_USB

RTC0_CLKIN

RTC0_XTAL

SYS_BMODE0

SYS_BMODE1

SYS_CLKIN

SYS_CLKOUT

SYS_EXTWAKE

SYS_FAULT

PA_01

PA_02

PA_03

PA_04

PA_05

PA_06

PA_07

J11

J05

L06

H14

E10

Rev. A

|

Page 109 of 116

|

September 2015

ADSP-BF700/701/702/703/704/705/706/707

ADSP-BF70x 12 mm × 12 mm 88-LEAD LFCSP (QFN) LEAD ASSIGNMENTS 

(NUMERICAL BY LEAD NUMBER)

Figure 70 shows an overview of signal placement on the 

12 mm × 12 mm 88-lead LFCSP (QFN).

PIN 88

PIN 67

PIN 1

PIN 66

PIN 1

INDICATOR

ADSP-BF70x

88-LEAD LFCSP (QFN)

TOP VIEW

PIN 22

PIN 45

PIN 23

PIN 67

PIN 44

PIN 88

PIN 66

PIN 1

INDICATOR

GND PAD

(PIN 89)

BOTTOM VIEW

PIN 45

PIN 22

PIN 23

PIN 44

Figure 70. 12 mm × 12 mm 88-Lead LFCSP (QFN) Configuration

Rev. A

|

Page 110 of 116

|

September 2015

ADSP-BF700/701/702/703/704/705/706/707

Table 69 lists the 12 mm × 12 mm 88-Lead LFCSP (QFN) pack-

age by lead number for the ADSP-BF70x. Table 70 lists the 

12 mm ×12 mm 88-Lead LFCSP (QFN) package by signal.

Table 69. 12 mm × 12 mm 88-Lead LFCSP (QFN) Lead Assignment (Numerical by Lead Number)

Lead No. Signal Name

1

PC_10

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

PB_14

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

PB_02

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89*

PA_07

2

PC_09

PB_13

PB_01

PA_06

3

PC_08

VDD_EXT

PB_12

VDD_OTP

VDD_EXT

VDD_INT

PB_00

VDD_EXT

PA_05

4

VDD_EXT

PC_07

5

PB_11

PA_04

6

PC_06

PB_10

PA_03

7

PC_05

VDD_INT

USB0_XTAL

USB0_CLKIN

USB0_ID

USB0_VBUS

USB0_DP

VDD_USB

USB0_DM

USB0_VBC

PB_09

PA_15

GND

8

PC_04

PA_14

SYS_NMI

PA_02

9

PC_03

VDD_EXT

SYS_XTAL

SYS_CLKIN

PA_13

10

11

12

13

14

15

16

17

18

19

20

21

22

23

PC_02

SYS_EXTWAKE

PA_01

VDD_EXT

SYS_CLKOUT

PC_01

VDD_INT

VDD_EXT

JTG_TDO_SWO

JTG_TMS_SWDIO

JTG_TCK_SWCLK

JTG_TDI

JTG_TRST

PA_00

PA_12

VDD_INT

SYS_RESOUT

PC_00

PA_11

VDD_INT

VDD_EXT

PA_10

VDD_EXT

TWI0_SDA

TWI0_SCL

RTC0_XTAL

RTC0_CLKIN

VDD_RTC

PB_15

PB_08

VDD_EXT

PB_07

PA_09

SYS_FAULT

SYS_BMODE0

SYS_BMODE1

SYS_HWRST

PA_08

PB_06

GND

PB_05

PB_04

PB_03

*Pin no. 89 is the GND supply (see Figure 70) for the processor; this pad must connect to GND.

Rev. A

|

Page 111 of 116

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September 2015

ADSP-BF700/701/702/703/704/705/706/707

Table 70. ADSP-BF70x 12 mm × 12 mm 88 -Lead LFCSP (QFN) Lead Assignments (Alphabetical by Signal Name)

Signal Name

GND

Lead No. Signal Name

Lead No.

34

76

89

85

86

83

84

87

88

80

78

75

74

73

71

70

69

64

63

60

59

58

54

53

PB_00

PB_01

PB_02

PB_03

PB_04

PB_05

PB_06

PB_07

PB_08

PB_09

PB_10

PB_11

PB_12

PB_13

PB_14

PB_15

PC_00

PC_01

PC_02

PC_03

PC_04

PC_05

PC_06

52

48

47

46

45

44

43

42

40

39

29

28

27

25

24

23

16

13

10

9

PC_07

5

USB0_VBUS

USB0_XTAL

VDD_EXT

VDD_INT

VDD_OTP

VDD_RTC

VDD_USB

GND

PC_08

3

31

JTG_TCK_SWCLK

JTG_TDI

JTG_TDO_SWO

JTG_TMS_SWDIO

JTG_TRST

PA_00

PC_09

2

4

PC_10

1

11

RTC0_CLKIN

RTC0_XTAL

SYS_BMODE0

SYS_BMODE1

SYS_CLKIN

SYS_CLKOUT

SYS_EXTWAKE

SYS_FAULT

SYS_HWRST

SYS_NMI

21

20

66

67

57

12

79

65

68

77

15

56

19

18

32

37

35

33

38

17

26

41

50

PA_01

55

PA_02

62

PA_03

72

PA_04

82

PA_05

14

PA_06

30

PA_07

SYS_RESOUT

SYS_XTAL

TWI0_SCL

TWI0_SDA

USB0_CLKIN

USB0_DM

USB0_DP

51

PA_08

61

PA_09

81

PA_10

49

PA_11

22

PA_12

36

PA_13

8

PA_14

7

USB0_ID

PA_15

6

USB0_VBC

Rev. A

|

Page 112 of 116

|

September 2015

ADSP-BF700/701/702/703/704/705/706/707

OUTLINE DIMENSIONS

Dimensions for the 12 mm × 12 mm CSP_BGA package in

Figure 71 are shown in millimeters.

12.10

12.00 SQ

11.90

A1 BALL

CORNER

A1 BALL

CORNER

14 12 10

13 11

8

6

4

2

9

7

5

3

1

A

B

C

D

E

F

G

H

J

10.40

REF SQ

0.80

BSC

K

L

M

N

P

0.80

REF

TOP VIEW

DETAIL A

BOTTOM VIEW

1.70

1.54

1.39

1.29

1.19

1.09

DETAIL A

0.39

0.35

0.30

0.50

0.45

0.40

COPLANARITY

0.12

SEATING

PLANE

BALL DIAMETER

COMPLIANT TO JEDEC STANDARDS MO-275-GGAA-1

Figure 71. 184-Ball Chip Scale Package Ball Grid Array [CSP_BGA]

(BC-184-1)

Dimensions shown in millimeters

Rev. A

|

Page 113 of 116

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September 2015

ADSP-BF700/701/702/703/704/705/706/707

Dimensions for the 12 mm × 12 mm LFCSP_VQ package in

Figure 72 are shown in millimeters.

12.10

12.00 SQ

11.90

0.28

0.23

0.18

0.60 MAX

0.60

MAX

67

88

PIN 1

66

1

INDICATOR

PIN 1

INDICATOR

11.85

11.75 SQ

11.65

0.50

BSC

6.00

5.90 SQ

5.80

EXPOSED

PAD

0.50

0.40

0.30

45

22

23

44

TOP VIEW

BOTTOM VIEW

10.50

REF

0.70

0.65

0.60

12° MAX

0.90

0.85

0.80

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

0.045

0.025

0.005

SECTION OF THIS DATA SHEET.

COPLANARITY

SEATING

PLANE

0.08

0.190~0.245 REF

COMPLIANT TO JEDEC STANDARDS MO-220

Figure 72. 88-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

(CP-88-8)

Dimensions shown in millimeters

SURFACE-MOUNT DESIGN

Table 71 is provided as an aid to PCB design. For industry-

standard design recommendations, refer to IPC-7351, Generic

Requirements for Surface-Mount Design and Land Pattern

Standard.

Table 71. CSP_BGA Data for Use with Surface-Mount Design

Package 

Ball Attach Type

Package 

Solder Mask Opening

Package 

Ball Pad Size

Package

BC-184-1

Solder Mask Defined

0.4 mm Diameter

0.5 mm Diameter

Rev. A

|

Page 114 of 116

|

September 2015

ADSP-BF700/701/702/703/704/705/706/707

PLANNED AUTOMOTIVE PRODUCTION PRODUCTS

Temperature

Package

Option

Model ^{1, 2, 3}

Max. Core Clock L2 SRAM

Grade⁴

Package Description

ADBF702WCCPZ3xx

ADBF702WCCPZ4xx

ADBF703WCBCZ3xx

ADBF703WCBCZ4xx

ADBF704WCCPZ3xx

ADBF704WCCPZ4xx

ADBF705WCBCZ3xx

ADBF705WCBCZ4xx

ADBF706WCCPZ3xx

ADBF706WCCPZ4xx

ADBF707WCBCZ3xx

ADBF707WCBCZ4xx

300 MHz

400 MHz

300 MHz

400 MHz

300 MHz

400 MHz

300 MHz

400 MHz

300 MHz

400 MHz

300 MHz

400 MHz

256K bytes

512K bytes

1024K bytes

–40°C to +105°C 88-Lead LFCSP_VQ

–40°C to +105°C 184-Ball CSP_BGA

–40°C to +105°C 88-Lead LFCSP_VQ

–40°C to +105°C 184-Ball CSP_BGA

–40°C to +105°C 88-Lead LFCSP_VQ

–40°C to +105°C 184-Ball CSP_BGA

CP-88-8

BC-184-1

CP-88-8

BC-184-1

CP-88-8

BC-184-1

¹Select Automotive grade products, supporting –40°C to +105°C T_AMBIENTcondition, will be available when they appear in the Automotive Products table.

²Z = RoHS Compliant Part.

³xx denotes the current die revision.

⁴Referenced temperature is ambient temperature. The ambient temperature is not a specification. See Operating Conditions on Page 50 for the junction temperature (T_J)

specification which is the only temperature specification.

Rev. A

|

Page 115 of 116

|

September 2015

ADSP-BF700/701/702/703/704/705/706/707

ORDERING GUIDE

Temperature

Package

Option

Model¹

Max. Core Clock L2 SRAM

Grade²

Package Description

88-Lead LFCSP_VQ

ADSP-BF700KCPZ-1

ADSP-BF700KCPZ-2

ADSP-BF700BCPZ-2

ADSP-BF701KBCZ-1

ADSP-BF701KBCZ-2

ADSP-BF701BBCZ-2

ADSP-BF702KCPZ-3

ADSP-BF702BCPZ-3

ADSP-BF702KCPZ-4

ADSP-BF702BCPZ-4

ADSP-BF703KBCZ-3

ADSP-BF703BBCZ-3

ADSP-BF703KBCZ-4

ADSP-BF703BBCZ-4

ADSP-BF704KCPZ-3

ADSP-BF704BCPZ-3

ADSP-BF704KCPZ-4

ADSP-BF704BCPZ-4

ADSP-BF705KBCZ-3

ADSP-BF705BBCZ-3

ADSP-BF705KBCZ-4

ADSP-BF705BBCZ-4

ADSP-BF706KCPZ-3

ADSP-BF706BCPZ-3

ADSP-BF706KCPZ-4

ADSP-BF706BCPZ-4

ADSP-BF707KBCZ-3

ADSP-BF707BBCZ-3

ADSP-BF707KBCZ-4

ADSP-BF707BBCZ-4

¹Z = RoHS Compliant Part.

100 MHz

200 MHz

100 MHz

200 MHz

300 MHz

400 MHz

300 MHz

400 MHz

300 MHz

400 MHz

300 MHz

400 MHz

300 MHz

400 MHz

300 MHz

400 MHz

128K bytes

256K bytes

512K bytes

1024K bytes

0°C to +70°C

CP-88-8

BC-184-1

CP-88-8

BC-184-1

CP-88-8

BC-184-1

CP-88-8

BC-184-1

–40°C to +85°C 88-Lead LFCSP_VQ

0°C to +70°C

184-Ball CSP_BGA

–40°C to +85°C 184-Ball CSP_BGA

0°C to +70°C 88-Lead LFCSP_VQ

–40°C to +85°C 88-Lead LFCSP_VQ

0°C to +70°C 88-Lead LFCSP_VQ

–40°C to +85°C 88-Lead LFCSP_VQ

0°C to +70°C 184-Ball CSP_BGA

–40°C to +85°C 184-Ball CSP_BGA

0°C to +70°C 184-Ball CSP_BGA

–40°C to +85°C 184-Ball CSP_BGA

0°C to +70°C 88-Lead LFCSP_VQ

–40°C to +85°C 88-Lead LFCSP_VQ

0C to +70C 88-Lead LFCSP_VQ

–40°C to +85°C 88-Lead LFCSP_VQ

0°C to +70°C 184-Ball CSP_BGA

–40°C to +85°C 184-Ball CSP_BGA

0C to +70C 184-Ball CSP_BGA

–40°C to +85°C 184-Ball CSP_BGA

0°C to +70°C 88-Lead LFCSP_VQ

–40°C to +85°C 88-Lead LFCSP_VQ

0°C to +70°C 88-Lead LFCSP_VQ

–40°C to +85°C 88-Lead LFCSP_VQ

0°C to +70°C 184-Ball CSP_BGA

–40°C to +85°C 184-Ball CSP_BGA

0°C to +70°C 184-Ball CSP_BGA

–40°C to +85°C 184-Ball CSP_BGA

²Referenced temperature is ambient temperature. The ambient temperature is not a specification. See Operating Conditions on Page 50 for the junction temperature (T_J)

specification which is the only temperature specification.

registered trademarks are the property of their respective owners.

D12396-0-9/15(A)

Rev. A

|

Page 116 of 116

|

September 2015


型号：	ADSP-BF701
厂家：	ADI
描述：	低功耗 200MHz BLACKFIN+嵌入式处理器，带128KB L2 SRAM和DDR2/LPDDR接口双倍数据速率静态存储器光电二极管
文件：	总116页 (文件大小：2960K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADSP-BF701 [ADI]

相关型号：

ADSP-BF701BBCZ-2

ADSP-BF701KBCZ-1

ADSP-BF701KBCZ-2

ADSP-BF702

ADSP-BF702BCPZ-3

ADSP-BF702BCPZ-4

ADSP-BF702KCPZ-3

ADSP-BF702KCPZ-4

ADSP-BF703

ADSP-BF703BBCZ-3

ADSP-BF703BBCZ-4

ADSP-BF703KBCZ-3