ADSP-SC592KBPZ10 [ADI]
SHARC Dual-Core DSP with Arm Cortex-A5;型号: | ADSP-SC592KBPZ10 |
厂家: | ADI |
描述: | SHARC Dual-Core DSP with Arm Cortex-A5 |
文件: | 总143页 (文件大小:3261K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
SHARC+ Dual-Core
DSP with Arm Cortex-A5
ADSP-21591/21593/21594/ADSP-SC591/SC592/SC594
Preliminary Technical Data
SYSTEM FEATURES
MEMORY
Dual-enhanced SHARC+ floating-point cores
High performance SHARC+ cores (up to 1 GHz each)
Up to 5 Mb (640 kB) L1 SRAM memory per core with parity
(optional ability to configure as cache)
32-bit, 40-bit, and 64-bit floating-point support
32-bit fixed-point support
Byte, short word, word, and long word addressability
Arm Cortex-A5 core
Up to 1 GHz/1600 DMIPS with NEON/VFPv4-D16
32 kB L1 instruction and data caches with parity
256 kB L2 cache with parity
Large on-chip Level 2 (L2) SRAM with ECC protection, up to
2 MB
One Level 3 (L3) interface providing 16-bit interface to
DDR3/ DDR3L SDRAM devices
ADDITIONAL FEATURES
ADSP-2156x pin-compatible package options
Enhanced FIR and IIR accelerators running up to 1 GHz
Security and protection
Cryptographic hardware accelerators
Fast secure boot with IP protection
Support for Arm TrustZone
Powerful DMA system with 8 MemDMAs
On-chip memory protection
APPLICATIONS
Integrated safety features
17 mm × 17 mm, 400-ball BGA_ED (0.8 mm pitch),
RoHS compliant
Automotive: audio amplifier, head unit, ANC/RNC, rear seat
entertainment, digital cockpit, ADAS
Consumer: AVRs, mixing consoles, microphone arrays,
conferencing systems
CORE 1
CORE 2
PERIPHERALS
SYSTEM CONTROL
SECURITY AND PROTECTION
SRU
DAI0
8× PRECISION CLOCK
GENERATORS
SYSTEM PROTECTION UNIT (SPU)
S
S
SYSTEM MEMORY
PROTECTION UNIT (SMPU)
(UP TO 1 GHz)
(UP TO 1 GHz)
ASRC
8× PAIRS
FULL SPORT
0-7
DRU
DAI1
ACCELERATORS
FIR 4× IIR
ACCELERATORS
FIR 4× IIR
ENCRYPTION/DECRYPTION
2× S/PDIF Rx/Tx
UP TO
40
FAULT MANAGEMENT UNIT (FMU)
L1 SRAM (PARITY)
L1 SRAM (PARITY)
2× 4-CHANNEL
PDM MIC INPUT
®
®
Arm TrustZone SECURITY
DUAL CRC (WITH MemDMA)
WATCHDOGS
(UP TO (UP TO
1 GHz) 1 GHz)
(UP TO (UP TO
1 GHz) 1 GHz)
5 Mb (640 kB)
SRAM/CACHE
5 Mb (640 kB)
SRAM/CACHE
6× I2C
2× LINK PORTS
OTP MEMORY
2× SPI + 2× QUAD SPI +
1× OCTAL SPI
THERMAL MONITOR UNIT (TMU)
SYSTEM CROSSBAR AND DMA SUBSYSTEM
4× UARTs
1× EPPI
PROGRAM FLOW
SYS EVENT CORE 0 (GIC)
G
P
I
SYS EVENT CORES 1-2 (SEC)
TRIGGER ROUTING (TRU)
16× TIMERS + 1× COUNTER
2× CAN FD
UP TO
135
O
CORE 0
L3 MEMORY
INTERFACE
SYSTEM
L2 MEMORY
2× EMAC
CLOCK, RESET, AND POWER
L2 CACHE
256 kB (PARITY)
CLOCK GENERATION UNIT (CGU)
1× USB 2.0 HS OTG
CONTROLLER
SRAM
(ECC)
DDR3/DDR3L
L1 CACHE (PARITY)
32 kB L1 I-CACHE
32 kB L1 D-CACHE
CLOCK DISTRIBUTION
UNIT (CDU)
UP TO 2 MB
32x CORE FLAGS I/O
MLB 3-PIN
RESET CONTROL UNIT (RCU)
BOOT ROM
16
6
Arm®
DYNAMIC POWER MANAGEMENT
(DPM)
MLB 6-PIN
DATA
Cortex®-A5
(UP TO 1 GHz)
HADC (8-CHANNEL, 12-BIT)
DEBUG UNIT
UP TO
8
TM
®
Arm CoreSight
SYSTEM WATCHPOINT UNIT
(SWU)
Figure 1. ADSP-SC594 (Full-Featured Model) Processor Block Diagram
SHARC, SHARC+, and the SHARC logo are registered trademarks of Analog Devices, Inc.
Rev. PrD Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.
Tel: 781.329.4700
Technical Support
©2021 Analog Devices, Inc. All rights reserved.
www.analog.com
ADSP-21591/21593/21594/ADSP-SC591/SC592/SC594 Preliminary Technical Data
TABLE OF CONTENTS
System Features ....................................................... 1
Memory ................................................................ 1
Additional Features .................................................. 1
Applications ........................................................... 1
Table of Contents ..................................................... 2
Revision History ...................................................... 3
General Description ................................................. 4
ARM Cortex-A5 Processor ...................................... 6
SHARC Processor ................................................. 7
SHARC+ Core Architecture .................................... 9
System Infrastructure ........................................... 11
System Memory Map ........................................... 12
Security Features ................................................ 15
Security Features Disclaimer .................................. 15
Safety Features ................................................... 16
Processor Peripherals ........................................... 16
System Acceleration ............................................ 21
System Design .................................................... 21
System Debug .................................................... 23
Development Tools ............................................. 24
Additional Information ........................................ 25
Related Signal Chains .......................................... 25
ADSP-2159x/ADSP-SC59x Designer Quick Reference .... 52
Preliminary Specifications ........................................ 68
Preliminary Operating Conditions .......................... 68
Preliminary Electrical Characteristics ....................... 71
HADC .............................................................. 75
TMU ................................................................ 76
Absolute Maximum Ratings ................................... 76
ESD Caution ...................................................... 76
Timing Specifications ........................................... 77
Output Drive Currents ....................................... 123
Test Conditions ................................................ 124
Environmental Conditions .................................. 125
ADSP-SC59x 400-Ball High Peripheral Count (HPC)
BGA Ball Assignments ........................................ 127
Numerical by Ball Number .................................. 127
Alphabetical by Pin Name ................................... 130
Configuration of the ADSP-SC59x 400-Ball High
Peripheral Count (HPC) BGA ........................... 133
ADSP-2159x 400-Ball Low Peripheral Count (LPC)
BGA Ball Assignments ........................................ 134
Numerical by Ball Number .................................. 134
Alphabetical by Pin Name ................................... 137
Configuration of the ADSP-2159x 400-Ball Low
Peripheral Count (LPC) BGA ............................ 140
ADSP-2159x/ADSP-SC59x Detailed Signal
Descriptions ...................................................... 26
Outline Dimensions .............................................. 141
Surface-Mount Design ........................................ 141
Planned Automotive Production Products .................. 142
Planned Production Products .................................. 142
Pre Release Products ............................................. 143
400-Ball High Peripheral Count (HPC) BGA Signal
Descriptions ...................................................... 30
GPIO Multiplexing for 400-Ball High Peripheral
Count (HPC) BGA Package ................................... 39
400-Ball Low Peripheral Count (LPC) BGA Signal
Descriptions ...................................................... 44
GPIO Multiplexing 400-Ball Low Peripheral
Count (LPC) BGA Package ................................... 50
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Preliminary Technical Data ADSP-21591/21593/21594/ADSP-SC591/SC592/SC594
REVISION HISTORY
5/2021—Rev. PrC to Rev. PrD
Added Core Flags I/O Pins ....................................... 21
Changes to Power-Up and Power-Down Sequencing ...... 23
Changes to Development Tools ................................. 24
Analog Devices is in the process of updating documentation to
provide terminology and language that is culturally appropriate.
This is a process with a wide scope and will be phased in as
quickly as possible. Thank you for your patience.
Changes to ADSP-2159x/ADSP-SC59x Detailed Signal Descrip-
tions .................................................................... 26
Changes to ADSP-SC594 (Full-Featured Model) Processor
Block Diagram ........................................................ 1
Changes to
ADSP-SC59x 400-Ball HPC BGA Signal Descriptions ..... 30
Changes to Processor Features .................................... 5
Changes to L1 Requester and Completer Ports ................ 9
Changes to ADSP-2159x/ADSP-SC59x Memory Map ....... 9
Added SHARC Fabric .............................................. 11
Change to footnote in L2 Memory Addressing Map ........ 12
Changes to ADSP-SC59x Signal Multiplexing for Port C .. 40
Changes to
ADSP-2159x 400-Ball LPC BGA Signal Descriptions ...... 44
Changes to ADSP-2159x Signal Multiplexing for Port C .. 51
Changes to ADSP-2159x/ADSP-SC59x Designer Quick Refer-
ence .................................................................... 52
Changes to Cyclic Redundancy Check (CRC) Protected Memo-
ries ...................................................................... 16
Added Preliminary Specifications ............................... 68
Added Planned Automotive Production Products ......... 142
Added Planned Production Products ......................... 142
Changes to
Asynchronous Sample Rate Converter (ASRC) .............. 17
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ADSP-21591/21593/21594/ADSP-SC591/SC592/SC594 Preliminary Technical Data
GENERAL DESCRIPTION
The ADSP-2159x/ADSP-SC59x processors are members of the
SHARC® family of products. The ADSP-SC59x processors are
based on the SHARC+® dual-core and the Arm® Cortex®-A5
core. The ADSP-2159x/ADSP-SC59x SHARC processors are
members of the single-instruction, multiple data (SIMD)
SHARC family of digital signal processors (DSPs) that feature
Analog Devices, Inc., Super Harvard Architecture. These 32-
bit/40-bit/64-bit floating-point processors are optimized for
high performance audio/floating-point applications with large
on-chip static random-access memory (SRAM), multiple inter-
nal buses that eliminate input/output (I/O) bottlenecks, and
innovative digital audio interfaces (DAI). New additions to the
SHARC+ core include cache enhancements and branch predic-
tion, while maintaining instruction set compatibility to previous
SHARC products.
By integrating a set of industry leading system peripherals and
memory, the Arm Cortex-A5 and SHARC processor is the plat-
form of choice for applications that require programmability
similar to reduced instruction set computing (RISC), multime-
dia support, and leading edge signal processing in one
integrated package. These applications span a wide array of
markets, including automotive, professional audio, and indus-
trial-based applications that require high floating-point
performance.
Table 1 provides comparison information for features that vary
across the standard processors.
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Preliminary Technical Data ADSP-21591/21593/21594/ADSP-SC591/SC592/SC594
Table 1. Processor Features1
Processor Feature
Arm Cortex-A5 (MHz, Maximum)2
Arm Core L1 Cache (I, D kB)
Arm Core L2 Cache (kB)
SHARC+ Core1 (MHz, Maximum)2
SHARC+ Core2 (MHz, Maximum)2
SHARC L1 SRAM (kB)
System Memory
L2 SRAM (Shared) (MB)
DDR3/DDR3L Controller (16-Bit)
Hardware Accelerators
FIRs Per SHARC+ Core
IIRs Per SHARC+ Core
Security Cryptographic Engine
DAI (Includes SRU and DRU)
Full SPORTs
ADSP-21591
ADSP-21593
ADSP-21594
ADSP-SC591
600, 800
ADSP-SC592
1000
ADSP-SC594
800, 1000
N/A
32, 32
256
1000
600, 800
800
1
800, 1000
800, 1000
2 × 640
N/A
1 × 640
2 × 640
2
1
2
1
1
4
Yes
2
8 (4 per DAI)
2 (1 per DAI)
8 (4 per DAI)
8 (4 per DAI)
2 (1 per DAI)
S/PDIF Receive/Transmit
ASRCs
PCGs
4-Channel PDM MIC Input
Pin Buffers
28 (14 per DAI)
40 (20 per DAI)
Multiplexed Peripherals
MLB 3-Pin
Link Ports
Yes3
2
GP Counter
I2C (TWI)
1
6
Watchdog Timers
GP Timers
Octal SPI
3
164
1
Quad-Data Bit SPI
Dual-Data Bit SPI
UARTs
2
1
3
N/A
2
4
1
ePPI
USB 2.0 HS OTG Controller
EMAC Std
EMAC Std/AVB + Timer IEEE 1588
CAN FD
1
10/100
10/100/1000
23
N/A
MLB 6-Pin
N/A
Yes3
Multichannel 12-Bit ADC
GPIO Ports
GPIO + DAI Pins
4-channel
Port A to Port C
40 + 28
8-channel5
Port A to Port I
135 + 40
Package Options
ADSP-2156x Pin-Compatible
400- ball BGA_ED
Yes6
No
1 N/A means not applicable.
2 Multiple values indicate various speed grades. See Planned Production Products.
3 Applies to automotive models only. See Planned Automotive Production Products.
4 For the ADSP-21591 and ADSP-21593 models, GP timer instances TIMER10-TIMER15 are not brought out to package pins and must only be configured for internal modes
of operation.
5 The HADC can support up to 7 additional channels using an external multiplexer.
6 Pin compatible with the ADSP-21566, ADSP-21567, and ADSP-21569.
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ADSP-21591/21593/21594/ADSP-SC591/SC592/SC594 Preliminary Technical Data
• Harvard L1 memory system with a memory management
unit (MMU)
• Arm v7TM debug architecture
ARM CORTEX-A5 PROCESSOR
The Arm Cortex-A5 processor (see Figure 2) is a high perfor-
mance processor with the following features:
• Trace support through an embedded trace macrocell
(ETM) interface
• Instruction cache unit (32 kB) and data Level 1 (L1) cache
unit (32 kB)
• Extension—vector floating-point unit (IEEE754) with
trapless execution
• Extension—media processing engine (MPE) with NEONTM
technology
• Extension—Jazelle® hardware acceleration
• In order pipeline with dynamic branch prediction
• Arm, Thumb®, and ThumbEE instruction set support
• Arm TrustZone® security extensions
EMBEDDED TRACE MACROCELL
(ETM) INTERFACE
CoreSightTM INTERFACE
Arm® Cortex®-A5
PROCESSOR
NEONTM MEDIA
DEBUG
CP15
PROCESSING
ENGINE
DATA PROCESSING UNIT (DPU)
PREFETCH UNIT AND BRANCH PREDICTOR (PFU)
INSTRUCTION MICRO-TLB
DATA MICRO-TLB
INSTRUCTION CACHE
DATA CACHE
UNIT (DCU)
MAIN TRANSMISSION
LOOKINSIDE BUFFER (TLB)
DATA STORE
BUFFER (STB)
UNIT (ICU)
32 kB
32 kB
BUS INTERFACE UNIT (BIU)
Arm® Cortex®-A5 BUS REQUESTER PORT
L2 CACHE
GENERIC INTERRUPT
CONTROLLER
DATA REQUESTER PORTS
SHARC PROCESSORS
TM
CONTROLLER
(CoreLink PL-310)
(PrimeCell® PL-390)
256 kB
SYSTEM FABRIC
TO OTHER CORES
Figure 2. Arm Cortex-A5 Processor Block Diagram
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Preliminary Technical Data ADSP-21591/21593/21594/ADSP-SC591/SC592/SC594
Generic Interrupt Controller (GIC), PL390
(ADSP-SC59x Only)
L2 Cache Controller, PL310 (ADSP-SC59x Only)
The Level 2 (L2) cache controller, PL310 (see Figure 2), works
efficiently with the Arm Cortex-A5 processors that implement
system fabric. The cache controller directly interfaces on the
data and instruction interface. The internal pipelining of the
cache controller is optimized to enable the processors to operate
at the same clock frequency. The cache controller supports the
following:
The generic interrupt controller (GIC) is a centralized resource
for supporting and managing interrupts. The GIC splits into the
distributor block (GICPORT0) and the central processing unit
(CPU) interface block (GICPORT1).
Generic Interrupt Controller Port0 (GICPORT0)
The GICPORT0 distributor block performs interrupt prioritiza-
tion and distribution to the GICPORT1 CPU interface blocks
that connect to the processors in the system. It centralizes all
interrupt sources, determines the priority of each interrupt, and
forwards the interrupt with the highest priority to the interface,
for priority masking and preemption handling.
• Two read/write 64-bit completer ports, one connected to
the Arm Cortex-A5 instruction and data interfaces, and
one connecting the Arm Cortex-A5 and SHARC+ cores for
data coherency
• Two read/write 64-bit requester ports for interfacing with
the system fabric
Generic Interrupt Controller Port1 (GICPORT1)
SHARC PROCESSOR
The GICPORT1 CPU interface block performs priority masking
and preemption handling for a connected processor in the sys-
tem. GICPORT1 supports 8 software generated interrupts
(SGIs) and 326 shared peripheral interrupts (SPIs).
The SHARC processor integrates a SHARC+ SIMD core, L1
memory crossbar, I-cache/D-cache controller, L1 memory
blocks, and the requester/completer ports, as shown in Figure 3.
The SHARC+ SIMD core block diagram is shown in Figure 4.
The SHARC processor supports a modified Harvard architec-
ture in combination with a hierarchical memory structure. L1
memories typically operate at the full processor speed with little
or no latency.
I-CACHE
D-CACHE
D-CACHE
B0
RAM
S
SIMD Processor
B3
RAM
B2
RAM
B1
RAM
CCLK DOMAIN
I/O (32)
I/O (32)
I/O (32)
COMPLETER
PORT 1
INTERNAL MEMORY INTERFACE (IMIF)
I-CACHE/D-CACHE CONTROL
COMPLETER
I/O (32)
PORT 2
(MDMA AND
ACCELERATORS)
SYSTEM FABRIC
CORE
MMR
SYSCLK
DOMAIN
(32)
DM (64)
PM (64)
CMD (64)
CMI (64)
REQUESTER
PORT DATA
SHARC+®
SIMD CORE
PS (64/48)
REQUESTER
PORT INSTRUCTION
INTERRUPT
SYSTEM
EVENT
CONTROLLER
Figure 3. SHARC Processor Block Diagram
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S
DEBUG
TRACE
BTB
BP
CONFLICT
CACHE
CEC
FLAGS
SIMD Core
PM DATA 48
DMD/PMD 64
11-STAGE
PROGRAM SEQUENCER
PM ADDRESS 24
DAG2
16 × 32
DAG1
16 × 32
PM ADDRESS 32
SYSTEM
I/F
DM ADDRESS 32
PM DATA 64
TO
IMIF
USTAT
PX
DM DATA 64
DATA
SWAP
PEx
PEy
DATA
DATA
ALU
SHIFTER
MULTIPLIER
ALU
SHIFTER MULTIPLIER
REGISTER
Rx
16 × 40-BIT
REGISTER
Sx
16 × 40-BIT
ASTATy
STYKy
ASTATx
STYKx
MSB
80-BIT
MSF
80-BIT
MRB
80-BIT
MRF
80-BIT
Figure 4. SHARC+ SIMD Core Block Diagram
The SRAM of the processor can be configured as a maximum of
160k words of 32-bit data, 320k words of 16-bit data,
106.7k words of 48-bit instructions (or 40-bit data), or combi-
nations of different word sizes up to 5 Mb. All of the memory
can be accessed as 8-bit, 16-bit, 32-bit, 48-bit, or 64-bit words.
Support of a 16-bit floating-point storage format doubles the
amount of data that can be stored on chip.
L1 Memory
Figure 5 shows the ADSP-2159x/ADSP-SC59x memory map.
Each SHARC+ core has a tightly coupled 5 Mb L1 SRAM. Each
SHARC+ core can access code and data in a single cycle from
this memory space. The Arm Cortex-A5 core can also access
this memory space with multicycle accesses.
In the SHARC+ core private address space, both cores have L1
memory.
Conversion between the 32-bit floating-point and 16-bit float-
ing-point formats is performed in a single instruction. Whereas
each memory block can store combinations of code and data,
accesses are most efficient when one block stores data using the
DM bus for transfers, and the other block stores instructions
and data using the PM bus for transfers.
SHARC+ core memory-mapped register (CMMR) address
space is 0x00000000 through 0x0003FFFF in normal word
(32-bit). Each block can be configured for different combina-
tions of code and data storage. Of the 5 Mb SRAM, up to 1 Mb
can be configured for data memory (DM), program memory
(PM), and instruction cache. Each memory block supports sin-
gle-cycle, independent accesses by the core processor and I/O
processor. The memory architecture, in combination with its
separate on-chip buses, allows two data transfers from the core
and one from the direct memory access (DMA) engine in a
single cycle.
Using the DM and PM buses, with each bus dedicated to a
memory block, assures single-cycle execution with two data
transfers. In this case, the instruction must be available in the
cache.
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Preliminary Technical Data ADSP-21591/21593/21594/ADSP-SC591/SC592/SC594
The system configuration is flexible, but a typical configuration
0x FFFF FFFF
is 512 kb DM, 128 kb PM, and 128 kb of instruction cache, with
RESERVED
0x C000 0000
the remaining L1 memory configured as SRAM. Each address-
DMC0 (1GB)
able memory space outside the L1 memory can be accessed
either directly or via cache.
0x 8000 0000
SPI2/OSPI0 FLASH ADDRESS SPACE (512MB)
0x 6000 0000
0x 5000 0000
The memory map in Table 2 gives the L1 memory address space
and shows multiple L1 memory blocks offering a configurable
0x 4C00 0000
RESERVED
mix of SRAM and cache.
0x 4800 0000
0x 4400 0000
L1 Requester and Completer Ports
0x 4000 0000
Each SHARC+ core has two requester/completer ports to and
SYSTEM MMR
0x 3000 0000
from the system fabric. One requester port fetches instructions.
RESERVED
The second requester port drives data to the system world.
0x 28BA 0000
SHARC2 L1 ADDRESS SPACE VIA
COMPLETER PORT 1/COMPLETER PORT 2
Completer Port 1 together with Completer Port 2 memory
0x 28A4 0000
RESERVED
direct memory access (high speed MDMA and accelerators) run
0x 2840 0000
SHARC1 L1 ADDRESS SPACE VIA
COMPLETER PORT 1/COMPLETER PORT 2
conflict free access to the individual memory blocks. For the
0x 2824 0000
completer port address, refer to the L1 memory address map in
Table 2.
RESERVED
L1 On-Chip Memory Bandwidth
0x 2023 0000
L2 BOOT ROM 2 (0.5Mb)
The internal memory architecture allows programs to have four
0x 2022 0000
L2 BOOT ROM 1 (0.5Mb)
accesses at the same time to any of the four blocks, assuming no
0x 2021 0000
L2 BOOT ROM 0 (0.5Mb)
(ARM BOOT ALIAS ADDRESS SPACE)
block conflicts. The total bandwidth is realized using both the
0x 2020 0000
DMD and PMD buses (2 × 64-bits CCLK speed and 2 × 32-bit
L2 SRAM (16Mb)
**
0x 2000 0000
SYSCLK speed).
0x 2000 0000
RESERVED
0x 0039 FFFF
Instruction and Data Cache
L1 BLOCK 3 SRAM (1Mb)
0x 0038 0000
RESERVED
The ADSP-2159x/ADSP-SC59x processors also include a
RESERVED
0x 0031 FFFF
traditional instruction cache (I-cache) and two data caches
(D-caches, one each for PM/DM) with parity support for all
caches. These caches support one instruction access and two
data accesses over the DM and PM buses per CCLK cycle. The
cache controllers automatically manage the configured L1
memory. The system can configure part of the L1 memory for
automatic management by the cache controllers. The sizes of
these caches are independently configurable from 0 to 128 kB
each. The memory not managed by the cache controllers is
directly addressable by the processors. The controllers ensure
the data coherence between the two data caches. The caches
provide user controllable features such as full and partial lock-
ing, range bound invalidation, and flushing.
L1 BLOCK 2 SRAM (1Mb)
RESERVED
0x 0030 0000
0x 002E FFFF
L1 BLOCK 1 SRAM (1.5Mb)
0x 002C 0000
0x 0026 FFFF
0x 1000 1000
0x 1000 0000
ARM L2 CONFIG REGS (4KB)
RESERVED
RESERVED
L1 BLOCK 0 SRAM (1.5Mb)
0x 0000 FFFF
0x 0000 0000
0x 0024 0000
0x 0000 0000
RESERVED/CORE MMRs/
OTHER MEMORY ALIASES
ARM BOOT (64KB)
FOR THE ADSP-21591,THE 1MB (8Mb) L2 SRAM RANGE IS 0x20100000–0x201FFFFF.
**
Figure 5. ADSP-2159x/ADSP-SC59x Memory Map
The SIMD architecture featured on the ADSP-2159x/ADSP-
SC59x processors is identical to all previous SIMD SHARC pro-
cessors, namely the ADSP-2116x, ADSP-2126x, ADSP-213xx,
ADSP-214xx, and ADSP-SC5xx/ADSP-215xx processors, as
shown in Figure 4 and as described in the following sections.
Core Memory-Mapped Registers (CMMR)
The core memory-mapped registers (CMMR) control the
L1 instruction and data cache, branch target buffer (BTB),
L2 cache, parity error, system control, debug, and monitor
functions.
Single-Instruction, Multiple Data (SIMD) Computational
Engine
The SHARC+ core contains two computational processing ele-
ments that operate as a single-instruction, multiple data (SIMD)
engine.
SHARC+ CORE ARCHITECTURE
The ADSP-2159x/ADSP-SC59x processors are assembly code
compatible with all previous SHARC processors featuring the
SHARC or SHARC+ core, beginning with the first generation
ADSP-2106x SHARC processors and including the ADSP-
2116x, ADSP-2126x, ADSP-213xx, ADSP-214xx, and ADSP-
SC5xx/ADSP-215xx processors.
The processing elements are referred to as PEx and PEy, each
containing an arithmetic logic unit (ALU), multiplier, shifter,
and register file. PEx is always active, and PEy is enabled by set-
ting the PEYEN mode bit in the mode control register
(MODE1).
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SIMD mode allows the processors to execute the same instruc-
tion in both processing elements, but each processing element
operates on different data. This architecture efficiently executes
math intensive DSP algorithms. In addition to all the features of
previous generation SHARC cores, the SHARC+ core also pro-
vides a new and simpler way to execute an instruction only on
the PEy data register.
Universal Registers
General-purpose tasks use the universal registers. The four uni-
versal status (USTAT) registers allow easy bit manipulations
(set, clear, toggle, test, XOR) for all control and status peripheral
registers.
The data bus exchange register (PX) permits data to pass
between the 64-bit PM data bus and the 64-bit DM data bus or
between the 40-bit register file and the PM or DM data bus.
These registers contain hardware to handle the data width
difference.
SIMD mode doubles the bandwidth between memory and the
processing elements, as required for sustained computational
operation of two processing elements. When using the data
address generators (DAGs) to transfer data in SIMD mode, two
data values transfer with each memory or register file access.
Data Address Generators (DAG) With Zero Overhead
Hardware Circular Buffer Support
Independent Parallel Computation Units
For indirect addressing and implementing circular data buffers
in hardware, the ADSP-2159x/ADSP-SC59x processors use two
data address generators (DAGs). Circular buffers allow efficient
programming of delay lines and other data structures required
in digital signal processing and are commonly used in digital fil-
ters and fast Fourier transforms (FFT). The DAGs contain
sufficient registers to allow the creation of up to 32 circular buf-
fers (16 primary register sets and 16 secondary sets). The DAGs
automatically handle address pointer wraparound, reduce over-
head, increase performance, and simplify implementation.
Circular buffers can start and end at any memory location.
Within each processing element is a set of pipelined computa-
tional units. The computational units consist of a multiplier, an
ALU, and a shifter. These units are arranged in parallel, maxi-
mizing computational throughput. These computational units
support IEEE 32-bit single-precision floating-point; 40-bit
extended-precision floating-point; IEEE 64-bit double-preci-
sion floating-point; and 32-bit fixed-point data formats.
A multifunction instruction set supports parallel execution of
the ALU and multiplier operations. In SIMD mode, the parallel
ALU and multiplier operations occur in both processing ele-
ments per core.
Flexible Instruction Set Architecture (ISA)
All processing operations take one cycle to complete. For all
floating-point operations, the processor takes two cycles to
complete in case of data dependency. Double-precision float-
ing-point data take two to six cycles to complete. The processor
stalls for the appropriate number of cycles for an interlocked
pipeline plus data dependency check.
The flexible instruction set architecture (ISA), a 48-bit instruc-
tion word, accommodates various parallel operations for
concise programming. For example, the processors can condi-
tionally execute a multiply, an add, and a subtract in both
processing elements while branching and fetching up to four
32-bit values from memory—all in a single instruction. Addi-
tionally, the double-precision floating-point instruction set is
new to the SHARC+ core, as compared with the previous
SHARC core.
Core Timer
Each SHARC+ processor core includes an extra timer. This
extra timer is clocked by the internal processor clock and is typ-
ically used as a system tick clock for generating periodic
operating system interrupts.
Variable Instruction Set Architecture (VISA)
In addition to supporting the standard 48-bit instructions from
previous SHARC core processors, the SHARC+ core processors
support 16-bit and 32-bit opcodes for many instructions, for-
merly 48-bit in the ISA. This variable instruction set
architecture (VISA) feature drops redundant or unused bits
within the 48-bit instruction to create more efficient and com-
pact code. The program sequencer supports fetching these
16-bit and 32-bit instructions from both internal and external
memories. VISA is not an operating mode; rather, it is address
dependent (refer to the ISA/VISA address spaces in Table 5).
Finally, the processor allows jumps between ISA and VISA
instruction fetches.
Data Register File
Each processing element contains a general-purpose data regis-
ter file. The register files transfer data between the computation
units and the data buses, and store intermediate results. These
10-port, 32-register register files (16 primary, 16 secondary),
combined with the enhanced Harvard architecture of the pro-
cessor, allow unconstrained data flow between computation
units and internal memory. The registers in the PEx data regis-
ter file are referred to as R0–R15 and in the PEy data register file
as S0–S15.
Context Switch
Single-Cycle Fetch of Instructional Four Operands
Many of the registers of the processor have secondary registers
that can activate during interrupt servicing for a fast context
switch. The data, DAG, and multiplier result registers have sec-
ondary registers. The primary registers are active at reset,
whereas control bits in MODE1 activate the secondary registers.
The ADSP-2159x/ADSP-SC59x processors feature an enhanced
Harvard architecture in which the DM bus transfers data and
the PM bus transfers both instructions and data.
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With the separate program memory bus, data memory buses,
and on-chip instruction conflict cache, the processor can simul-
taneously fetch four operands (two over each data bus) and one
instruction from the conflict cache in a single cycle.
programming. To enhance the reliability of the application, L1
data RAMs support parity error detection for every byte, and
illegal opcodes are also detected (core interrupts flag both
errors). Requester ports of the core also detect failed external
accesses.
Core Event Controller (CEC)
SYSTEM INFRASTRUCTURE
The SHARC+ core event controller (CEC) can be configured to
service various interrupts generated by the core (including
arithmetic and circular buffer instruction flow exceptions) and
system event controller (SEC) events (peripheral interrupt
request, debug or monitor, and software-raised), responding
only to interrupts enabled in the IMASK register. The output of
the SEC is forwarded to the CEC to respond directly to any
enabled system interrupts. For all SEC channels, the processor
automatically stacks the arithmetic status (ASTATx and
ASTATy) registers and mode (MODE1) register in parallel with
interrupt servicing.
The following sections describe the system infrastructure of the
ADSP-2159x/ADSP-SC59x processors.
System L2 Memory
A system L2 SRAM memory of up to 16 Mb (2 MB) is available
to both SHARC+ cores, the Arm Cortex-A5 core, and the sys-
tem DMA channels (see Table 3). The L2 SRAM block is
subdivided into up to eight banks to support concurrent access
to the L2 memory ports. Memory accesses to the L2 memory
space are multicycle accesses by both the Arm Cortex-A5 and
SHARC+ cores.
Instruction Conflict Cache
The memory space is used for various situations including
The processors include a 32-entry instruction cache that enables
three-bus operation for fetching an instruction and four data
values. The cache is selective—only the instructions that require
fetches conflict with the PM bus data access cache. This cache
allows full speed execution of core looped operations, such as
digital filter multiply accumulates and FFT butterfly processing.
The conflict cache serves for on-chip bus conflicts only.
• Arm Cortex-A5 to SHARC+ core data sharing and
intercore communications
• Accelerator and peripheral sources and destination mem-
ory to avoid accessing data in the external memory
• A location for DMA descriptors
• Storage for additional data for either the Arm Cortex-A5 or
SHARC+ cores to avoid external memory latencies and
reduce external memory bandwidth
Branch Target Buffer (BTB)/Branch Predictor (BP)
Implementation of a hardware-based branch predictor (BP) and
branch target buffer (BTB) reduce branch delay. The program
sequencer supports efficient branching using the BTB for condi-
tional and unconditional instructions.
• Storage for incoming Ethernet traffic to improve
performance
• Storage for data coefficient tables cached by the
SHARC+ core
Addressing Spaces
See the System Memory Protection Unit (SMPU) section for
options in limiting access by specific cores and DMA requesters.
In addition to traditionally supported long word, normal word,
extended precision word, and short word addressing aliases, the
processors support byte addressing for the data and instruction
accesses. The enhanced ISA/VISA provides new instructions for
accessing all sizes of data from byte space, as well as converting
word addresses to byte addresses and byte addresses to word
addresses.
The Arm Cortex-A5 core has an L1 instruction and data cache,
each of which is 32 kB in size. The core also has an L2 cache
controller of 256 kB. When enabling the caches, accesses to all
other memory spaces (internal and external) go through the
cache.
SHARC Fabric
SHARC+ Core L1 Memory in Multiprocessor Space
The FIR/IIR accelerators on the ADSP-2159x/ADSP-SC59x
processors are integrated closely with the SHARC+ core with
the help of a dedicated SHARC fabric and run at CCLK speed.
This allows the FIR/IIR accelerator requester ports to directly
access the SHARC L1 memory with reduced latency, as these
accesses do not go through the main system fabric. These
accesses are arbitrated between both the SHARC+ core com-
pleter ports. The SHARC+ core can also access the FIR/IIR
accelerator MMR registers directly.
The Arm Cortex-A5 core can access the L1 memory of the
SHARC+ core. See Table 4 for the L1 memory address in multi-
processor space. The SHARC+ core can access the L1 memory
of the other SHARC+ core in the multiprocessor space.
One Time Programmable Memory (OTP)
The processors feature 7 kb of one time programmable (OTP)
memory that is memory-map accessible. This memory can be
programmed with custom keys and supports secure boot and
secure operation.
Additional Features
I/O Memory Space
The enhanced ISA/VISA of the ADSP-2159x/ADSP-SC59x pro-
cessors provides a memory barrier instruction for data
synchronization, exclusive data access support for multicore
data sharing, and exclusive data access to enable multiprocessor
Mapped I/Os include SPI2/OSPI0 memory address space (see
Table 5).
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SYSTEM MEMORY MAP
Table 2. L1 Block 0, Block 1, Block 2, and Block 3 SHARC+® Addressing Memory Map (Private Address Space)
Extended Precision/
Short Word/
Memory
Long Word (64 Bits) ISA Code (48 Bits)
Normal Word (32 Bits) VISA Code (16 Bits) Byte Access (8 Bits)
L1 Block 0 SRAM
(192 KB)
0x00048000–
0x0004DFFF
0x00090000–
0x00097FFF
0x00090000–
0x0009BFFF
0x00120000–
0x00137FFF
0x00240000–
0x0026FFFF
L1 Block 1 SRAM
(192 KB)
0x00058000–
0x0005DFFF
0x000B0000–
0x000B7FFF
0x000B0000–
0x000BBFFF
0x00160000–
0x00177FFF
0x002C0000–
0x002EFFFF
L1 Block 2 SRAM
(128 KB)
0x00060000–
0x00063FFF
0x000C0000–
0x000C5554
0x000C0000–
0x000C7FFF
0x00180000–
0x0018FFFF
0x00300000–
0x0031FFFF
L1 Block 3 SRAM
(128 KB)
0x00070000–
0x00073FFF
0x000E0000–
0x000E5554
0x000E0000–
0x000E7FFF
0x001C0000–
0x001CFFFF
0x00380000–
0x0039FFFF
Table 3. L2 Memory Addressing Map
Byte Address Space
Arm Cortex-A5: Data Access
and Instruction Fetch
SHARC+: Data Access
Normal Word Address Space VISA Address Space
ISA Address Space
Memory
SHARC+ Data Access
SHARC+ Instruction Fetch SHARC+ Instruction Fetch
Arm:
0x00000000–0x0000FFFF
SHARC+/DMA:
L2 Boot ROM01 0x20200000–0x2020FFFF
L2 RAM (2 MB)2 0x20000000–0x201FFFFF
L2 RAM (1 MB)2 0x20100000–0x201FFFFF
L2 Boot ROM1 0x20210000–0x2021FFFF
L2 Boot ROM2 0x20220000–0x2022FFFF
0x08080000–0x08083FFF
0x08000000–0x0807FFFF
0x08040000–0x0807FFFF
0x08084000–0x08087FFF
0x08088000–0x0808BFFF
0x00C20000–0x00C27FFF 0x00520000–0x00522AA9
0x00B00000–0x00BFFFFF 0x00580000–0x005D5554
0x00B80000–0x00BFFFFF 0x005AAAAB–0x005D5554
0x00C00000–0x00C07FFF 0x00500000–0x00502AA9
0x00C40000–0x00C47FFF 0x00540000–0x00542AA9
1 For ADSP-SC59x products, the L2 Boot ROM0 byte address space is 0x00000000–0x0000FFFF.
2 All L2 RAM blocks are subdivided into 256 KB banks. All models feature 2 MB of L2 SRAM (8 banks) except for the ADSP-21591/ADSP-SC591 models, which feature 1 MB
(4 banks). See Planned Automotive Production Products, Planned Production Products, and Pre Release Products.
Table 4. SHARC+® L1 Memory in Multiprocessor Space
Memory Byte Address Space
Normal Word Address Space
SHARC+
Block
Arm Cortex-A5 and SHARC+
L1 memory of SHARC1 in Address via Completer 1 Port Block 0
0x28240000–0x2826FFFF
0x282C0000–0x282EFFFF
0x28300000–0x2831FFFF
0x28380000–0x2839FFFF
0x28A40000–0x28A6FFFF
0x28AC0000–0x28AEFFFF
0x28B00000–0x28B1FFFF
0x28B80000–0x28B9FFFF
0x0A090000–0x0A09BFFF
0x0A0B0000–0x0A0BBFFF
0x0A0C0000–0x0A0C7FFF
0x0A0E0000–0x0A0E7FFF
0x0A290000–0x0A29BFFF
0x0A2B0000–0x0A2BBFFF
0x0A2C0000–0x0A2C7FFF
0x0A2E0000–0x0A2E7FFF
multiprocessor space
Block 1
Block 2
Block 3
L1 memory of SHARC2 in Address via Completer 1 Port Block 0
multiprocessor space
Block 1
Block 2
Block 3
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Table 5. Memory Map of Mapped I/Os1
Byte Address Space
Arm Cortex-A5:
Data Access and
Instruction Fetch
Normal Word Address Space VISA Address Space
ISA Address Space
SHARC+: Data Access
SHARC+ Data Access
SHARC+ Instruction Fetch SHARC+ Instruction Fetch
SPI2/OSPI0 Memory 0x60000000–0x600FFFFF
0x00F80000–0x00FFFFFF 0x00780000–0x007AAAAA
(512 MB)2
0x60100000–0x602FFFFF
Not available
0x007AAAAB–0x007FFFFF
0x60300000–0x603FFFFF 0x04000000–0x07FFFFFF
0x60400000–0x605FFFFF
0x00E80000–0x00EFFFFF 0x00680000–0x006AAAAA
Not available
Not available
Not available
0x006AAAAB–0x006FFFFF
Not available
0x60600000–0x6FFFFFFF
0x70000000–0x7FFFFFFF Not available
Not available
1 The Arm Cortex-A5 can access the entire byte address space. The SHARC+ VISA/ISA address space for instruction fetch and the normal word address space for data access
do not cover the entire byte address space.
2 For the ADSP-SC592/SC594/21594 processors, the SPI2/OSPI0 memory-mapped I/O space can be configured to be shared between the OSPI0 and SPI2 peripherals using
the REG_SCB5_REMAP.REMAP field. See the ADSP-2159x/ADSP-SC591/592/594 SHARC+ Processor Hardware Reference for details.
Table 6. DMC Memory Map1
Byte Address Space
Arm Cortex-A5: Data Access
and Instruction Fetch
SHARC+: Data Access
Normal Word Address Space VISA Address Space
ISA Address Space
SHARC+ Data Access
0x10000000–0x17FFFFFF
Not applicable
SHARC+ Instruction Fetch SHARC+ Instruction Fetch
DMC0 (1 GB) 0x80000000–0x805FFFFF
0x80600000–0x809FFFFF
Not applicable
0x00400000–0x004FFFFF
Not applicable
Not applicable
0x80A00000–0x80FFFFFF
0x00800000–0x00AFFFFF
Not applicable
Not applicable
0x81000000–0x9FFFFFFF
Not applicable
0xA0000000–0xBFFFFFFF
Not applicable
Not applicable
1 The Arm Cortex-A5 can access the entire byte address space. The SHARC+ VISA/ISA address space for instruction fetch and the normal word address space for data access
do not cover the entire byte address space.
and return to normal processing while the fully integrated DMA
controller carries out the data transfers independent of proces-
sor activity.
System Crossbars (SCBs)
The system crossbars (SCBs) are the fundamental building
blocks of a switch fabric style for on-chip system bus intercon-
nection. The SCBs connect system bus requesters to system bus
completers, providing concurrent data transfer between multi-
ple bus requesters and multiple bus completers. A hierarchical
model—built from multiple SCBs—provides a power and area
efficient system interconnection.
DMA transfers can occur between memory and a peripheral or
between one memory and another memory. Each memory to
memory DMA stream uses two channels: the source channel
and the destination channel.
All DMA channels can transport data to and from all on-chip
and off-chip memories. Programs can use two types of DMA
transfers: descriptor-based or register-based. Register-based
DMA allows the processors to program DMA control registers
directly to initiate a DMA transfer. On completion, the DMA
control registers automatically update with original setup values
for continuous transfer. Descriptor-based DMA transfers
require a set of parameters stored within memory to initiate a
DMA sequence. Descriptor-based DMA transfers allow
multiple DMA sequences to be chained together. Program a
DMA channel to set up and start another DMA transfer auto-
matically after the current sequence completes.
The SCBs provide the following features:
• Highly efficient, pipelined bus transfer protocol for sus-
tained throughput
• Full-duplex bus operation for flexibility and reduced
latency
• Concurrent bus transfer support to allow multiple bus
requesters to access bus completers simultaneously
• Protection model (privileged/secure) support for selective
bus interconnect protection
Direct Memory Access (DMA)
The DMA engine supports the following DMA operations:
• A single linear buffer that stops on completion
The processors use direct memory access (DMA) to transfer
data within memory spaces or between a memory space and a
peripheral. The processors can specify data transfer operations
• A linear buffer with negative, positive, or zero stride length
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• A circular autorefreshing buffer that interrupts when each
buffer becomes full
• Data fill mode
• User-programmable CRC32 polynomial
• Bit and byte mirroring option (endianness)
• Fault and error interrupt mechanisms
• 1D and 2D fill block to initialize an array with constants
• A similar circular buffer that interrupts on fractional buf-
fers, such as at the halfway point
• The 1D DMA uses a set of identical ping pong buffers
defined by a linked ring of two-word descriptor sets, each
containing a link pointer and an address
• 32-bit CRC signature of a block of memory or an MMR
block
• The 1D DMA uses a linked list of four-word descriptor sets
containing a link pointer, an address, a length, and a
configuration
Event Handling
The processors provide event handling that supports both nest-
ing and prioritization. Nesting allows multiple event service
routines to be active simultaneously. Prioritization ensures that
servicing a higher priority event takes precedence over servicing
a lower priority event.
• The 2D DMA uses an array of one-word descriptor sets,
specifying only the base DMA address
• The 2D DMA uses a linked list of multiword descriptor
sets, specifying all configurable parameters
The processors provide support for four different types of
events:
Memory Direct Memory Access (MDMA)
The processor supports various memory direct memory access
(MDMA) operations, including,
• An emulation event causes the processors to enter emula-
tion mode, allowing command and control of the
processors through the JTAG interface.
• Enhanced bandwidth MDMA channels with cyclic redun-
dancy check (CRC) protection (32-bit bus width, run on
SYSCLK)
• A reset event resets the processors.
• An exception event occurs synchronously to program flow
(in other words, the exception is taken before the instruc-
tion is allowed to complete). Conditions triggered by the
SHARC+ core, such as data alignment (SIMD or long
word) or compute violations (fixed or floating point) and
illegal instructions, cause core exceptions. Conditions trig-
gered by the SEC, such as error correcting code (ECC),
parity, watchdog, or system clock, cause system exceptions.
• Enhanced bandwidth MDMA channel (32-bit bus width,
runs on SYSCLK)
• Maximum bandwidth MDMA channel (64-bit bus width,
runs on SYSCLK)
Extended Memory DMA
Extended memory DMA supports various operating modes,
such as delay line (which allows processor reads and writes to
external delay line buffers and to the external memory), with
limited core interaction and scatter/gather DMA (writes to and
from noncontiguous memory blocks).
• An interrupt event occurs asynchronously to program
flow. The interrupts are caused by input signals, timers,
and other peripherals, as well as by an explicit software
instruction.
Cyclic Redundancy Check (CRC) Protection
System Event Controller (SEC)
The cyclic redundancy check (CRC) protection modules allow
system software to calculate the signature of code, data, or both
in memory, the content of memory-mapped registers, or
periodic communication message objects. Dedicated hardware
circuitry compares the signature with precalculated values and
triggers appropriate fault events.
Each SHARC+ core event controller receives interrupt requests
from the system event controller (SEC). The SEC features
include the following:
• Comprehensive system event source management, includ-
ing interrupt enable, fault enable, priority, core mapping,
and source grouping
For example, the system software initiates the signature calcula-
tion of the entire memory contents every 100 ms and compares
this with expected, precalculated values. If a mismatch occurs, a
fault condition is generated through the processor core or the
trigger routing unit.
• A distributed programming model where each system
event source control and all status fields are independent of
each other
• Determinism where all system events have the same propa-
gation delay and provide unique identification of a specific
system event source
The CRC is a hardware module based on a CRC32 engine that
computes the CRC value of the 32-bit data-words presented to
it. The source channel of the memory to memory DMA (in
memory scan mode) provides data. The data can be optionally
forwarded to the destination channel (memory transfer mode).
The main features of the CRC peripheral are as follows:
• A completer control port that provides access to all SEC
registers for configuration, status, and interrupt and fault
services
• Global locking that supports a register level protection
model to prevent writes to locked registers
• Memory scan mode
• Memory transfer mode
• Data verify mode
• Fault management including fault action configuration,
time out, external indication, and system reset
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Employ secure debug to allow only trusted users to access the
system with debug tools.
Trigger Routing Unit (TRU)
The trigger routing unit (TRU) provides system level sequence
control without core intervention. The TRU maps trigger gener-
ators to trigger receivers. Trigger receivers can be configured to
respond to triggers in various ways. Common applications
enabled by the TRU include,
CAUTION
This product includes security features that can be
used to protect embedded nonvolatile memory
contents and prevent execution of unauthorized
code. When security is enabled on this device
(either by the ordering party or the subsequent
receiving parties), the ability of Analog Devices to
conduct failure analysis on returned devices is
limited. Contact Analog Devices for details on the
failure analysis limitations for this device.
• Automatically triggering the start of a DMA sequence after
a sequence from another DMA channel completes
• Software triggering
• Synchronization of concurrent activities
SECURITY FEATURES
The following sections describe the security features of the
ADSP-2159x/ADSP-SC59x processors.
System Protection Unit (SPU)
The system protection unit (SPU) guards against accidental or
unwanted access to an MMR space of the peripheral by provid-
ing a write protection mechanism. The user can choose and
configure the protected peripherals as well as configure which of
the six system MMR requesters (Arm Cortex-A5, two SHARC+
cores, two memory DMA, and Arm® CoreSightTM debug) the
peripherals are guarded against.
Arm TrustZone
The ADSP-SC59x processors provide TrustZone technology
that is integrated into the Arm Cortex-A5 processors. The
TrustZone technology enables a secure state that is extended
throughout the system fabric.
Cryptographic Hardware Accelerators
The SPU is also part of the security infrastructure. Along with
providing write protection functionality, the SPU is employed
to define which resources in the system are secure or nonsecure
as well as block access to secure resources from nonsecure
requesters.
The ADSP-2159x/ADSP-SC59x processors support standards-
based hardware accelerated encryption, decryption, authentica-
tion, and true random number generation.
Support for the hardware accelerated cryptographic ciphers
includes the following:
System Memory Protection Unit (SMPU)
• AES in ECB, CBC, ICM, and CTR modes with 128-bit,
192-bit, and 256-bit keys
The system memory protection unit (SMPU) provides memory
protection against read and/or write transactions to defined
regions of memory. There are SMPU units in the ADSP-
2159x/ADSP-SC59x processors for each memory space, except
for SHARC L1.
• DES in ECB and CBC mode with 56-bit key
• 3DES in ECB and CBC mode with 3x 56-bit key
• ARC4 in stateful, stateless mode, up to 128-bit key
The SMPU is also part of the security infrastructure. It allows
the user to protect against arbitrary read and/or write transac-
tions and allows regions of memory to be defined as secure and
prevent nonsecure requesters from accessing those memory
regions.
Support for the hardware accelerated hash functions includes
the following:
• SHA-1
• SHA-2 with 224-bit and 256-bit digests
• HMAC transforms for SHA-1 and SHA-2
• MD5
SECURITY FEATURES DISCLAIMER
Analog Devices does not guarantee that the Security Features
described herein provide absolute security. ACCORDINGLY,
ANALOG DEVICES HEREBY DISCLAIMS ANY AND ALL
EXPRESS AND IMPLIED WARRANTIES THAT THE
SECURITY FEATURES CANNOT BE BREACHED,
COMPROMISED, OR OTHERWISE CIRCUMVENTED AND
IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR
ANY LOSS, DAMAGE, DESTRUCTION, OR RELEASE OF
DATA, INFORMATION, PHYSICAL PROPERTY, OR
INTELLECTUAL PROPERTY.
Public key accelerator (PKA) is available to offload computation
intensive public key cryptography operations.
Both a hardware-based nondeterministic random number gen-
erator and pseudorandom number generator are available.
Secure boot is also available with 224-bit and 256-bit elliptic
curve digital signatures ensuring integrity and authenticity of
the boot stream. Optionally, ensuring confidentiality through
AES-128 encryption is available.
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Signal Watchdogs
SAFETY FEATURES
The 16 general-purpose (GP) timers feature modes to monitor
off-chip signals. The watchdog period mode monitors whether
external signals toggle with a period within an expected range.
The ADSP-2159x/ADSP-SC59x processors are designed to sup-
port functional safety applications. Whereas the level of safety is
mainly dominated by the system concept, the following primi-
tives are provided by the processors to build a robust safety
concept.
The watchdog width mode monitors whether the pulse widths
of external signals are within an expected range. Both modes
help detect undesired toggling or lack of toggling of system level
signals.
Multiparity Bit Protected SHARC+ Core L1 Memories
In the SHARC+ core L1 memory space, whether SRAM or
cache, multiple parity bits protect each word to detect the single
event upsets that occur in all RAMs. Parity also protects the
cache tags and BTB.
System Event Controller (SEC)
Besides system events, the system event controller (SEC) further
supports fault management, including fault action configura-
tion as timeout, internal indication by system interrupt, or
external indication through the SYS_FAULT pin and system
reset.
Parity Protected Arm L1 Cache
In the Arm Cortex-A5 L1 cache space, each word is protected by
multiple parity bits to detect the single event upsets that occur in
all RAMs. Parity also protects the cache tags.
Memory Error Controller (MEC)
The memory error controller (MEC) manages memory par-
ity/ECC errors and warnings from the cores and peripherals
and sends out interrupts and triggers.
Error Correcting Code (ECC) Protected L2 Memories
Error correcting code (ECC) corrects single event upsets. A sin-
gle error correct/double error detect (SEC/DED) code protects
the L2 memory. By default, ECC is enabled, but it can be dis-
abled on a per bank basis. Single-bit errors correct
transparently. If enabled, dual-bit errors can issue a system
event or fault. ECC protection is fully transparent to the user,
even if L2 memory is read or written by 8-bit or 16-bit entities.
PROCESSOR PERIPHERALS
The following sections describe the peripherals of the ADSP-
2159x/ADSP-SC59x processors.
Dynamic Memory Controller (DMC)
The 16-bit dynamic memory controller (DMC) interfaces to
• DDR3 (JESD79-3), 512 Mb to 8 Gb
Parity and ECC Protected Peripheral Memories
Parity protection is added to the following peripheral memories:
• DDR3L (JESD79-3-1A), 512 Mb to 8 Gb
See Table 6 for the DMC memory map.
• ASRC
• IIR
• FIR
Digital Audio Interface (DAI)
• USB
The processors support two identical digital audio interface
(DAI) units. The DAI can connect various peripherals to any of
the DAI pins.
• CRYPTO
• EMAC
The application code makes these connections using the signal
routing unit (SRU), shown in Figure 1.
• MLB
• TRACE
The SRU is a matrix routing unit (or group of multiplexers) that
enables the peripherals provided by each DAI instance to inter-
connect under software control. This functionality allows easy
use of the DAI associated peripherals for a wider variety of
applications by using a larger set of algorithms than is possible
with nonconfigurable signal paths.
CAN FD memory is ECC protected.
Cyclic Redundancy Check (CRC) Protected Memories
Whereas parity bit and ECC protection mainly protect against
random soft errors in L1 and L2 memory cells, the CRC engines
can protect against systematic errors (pointer errors) and static
content (instruction code) of L1, L2, and even Level 3 (L3)
memories (DDR3, DDR3L). The processors feature four CRC
engines that are embedded in the memory to memory DMA
controllers.
The DAI includes the peripherals described in the following
sections (SPORTs, ASRC, S/PDIF, and PCG). DAI Pin Buffer 20
and DAI Pin Buffer 19 can change the polarity of the input
signals.
The DAI_PINx pin buffers can also be used as GPIO pins. DAI
input signals allow the triggering of interrupts on the rising
edge, falling edge, or both.
CRC checksums can be calculated or compared automatically
during memory transfers. Alternatively, single or multiple
memory regions can be continuously scrubbed by a single DMA
work unit as per DMA descriptor chain instructions. The CRC
engine also protects data loaded during the boot process.
See the Digital Audio Interface (DAI) chapter of the ADSP-
2159x/ADSP-SC591/592/594 SHARC+ Processor Hardware
Reference for complete information on the use of the DAIs and
SRUs.
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The S/PDIF interface supports one stereo channel or com-
pressed audio streams. The S/PDIF transmitter and receiver are
AES3 compliant and support the sample rate from 24 kHz to
192 kHz. The S/PDIF receiver supports professional jitter
standards.
DAI Routing Unit (DRU)
The DAI routing unit (DRU) provides flexibility when routing
signals across the two DAI units. All DAI0 SRU source signals
are available as source signals for the DAI1 SRU, and all DAI1
SRU source signals are available as source signals for the DAI0
SRU.
The S/PDIF receiver/transmitter has no separate DMA chan-
nels. It receives audio data in serial format and converts it into a
biphase encoded signal. The serial data input to the receiver/
transmitter can be formatted as left justified, I2S, or right justi-
fied with word widths of 16, 18, 20, or 24 bits. The serial data,
clock, and frame sync inputs to the S/PDIF receiver/transmitter
are routed through the SRU. They can come from various
sources, such as the SPORTs, external pins, and the precision
clock generators (PCGs), and are controlled by the SRU control
registers.
Serial Port (SPORT)
The processors feature eight synchronous serial ports
(SPORTs), providing an inexpensive interface to a wide variety
of digital and mixed-signal peripheral devices. These devices
include Analog Devices AD19xx and ADAU19xx families of
audio codecs, analog-to-digital converters (ADCs) and digital-
to-analog converters (DACs). Two data lines, a clock, and a
frame sync comprise a SPORT half. The data lines can be pro-
grammed to either transmit or receive data, and each data line
has a dedicated DMA channel.
Precision Clock Generators (PCG)
The precision clock generators (PCG) consist of eight units
located in the two DAI blocks. The PCG can generate a pair of
signals (clock and frame sync) derived from a clock input signal
(CLKIN, SCLK0, or DAI pin buffer). Both units are identical in
functionality and operate independently of each other. The two
signals generated by each unit are normally used as a serial bit
clock/frame sync pair.
An individual SPORT module consists of two independently
configurable SPORT halves with identical functionality. Two
bidirectional data lines—primary (0) and secondary (1)—are
available per SPORT half and are configurable as either trans-
mitters or receivers. Therefore, each SPORT half permits two
unidirectional streams into or out of the same SPORT. This
bidirectional functionality provides greater flexibility for serial
communications. For full-duplex configuration, one half
SPORT provides two transmit data signals, and the other half
SPORT provides two receive data signals. The frame sync and
clock are shared.
Pulse Density Modulation (PDM) Microphone Interface
The pulse density modulation (PDM) interface is used to con-
vert digital PDM microphone data to I2S/TDM format. The
microphone data in I2S/TDM format is then routed internally to
the serial port/ASRC or externally via the DAI pins. The PDM
microphone inputs include an internal decimation filter. Up to
eight PDM microphones can be connected to the two dedicated
digital microphone interfaces (one per DAI). Each PDM inter-
face consists of one clock line and two data lines. Two
microphones can share a single data line and be used along with
a clock line to create a dual-input microphone port. Two dual-
input lines can share a single clock line to support four micro-
phone inputs.
Serial ports operate in the following six modes:
• Standard DSP serial mode
• Multichannel time division multiplexing (TDM) mode
• I2S mode
• Packed I2S mode
• Left justified mode
• Right justified mode
Asynchronous Sample Rate Converter (ASRC)
Enhanced Parallel Peripheral Interface (EPPI)
The asynchronous sample rate converter (ASRC) contains eight
ASRC blocks. The ASRC provides up to 140 dB signal-to-noise
ratio (SNR). The ASRC block performs synchronous or asyn-
chronous sample rate conversion across independent stereo
channels, without using internal processor resources. The ASRC
blocks can also be configured to operate together to convert
multichannel audio data without phase mismatches. Finally, the
ASRC can clean up audio data from jittery clock sources such as
the S/PDIF receiver.
The processors provide an enhanced parallel peripheral inter-
face (EPPI) that supports data widths up to 24 bits. The EPPI
supports direct connection to thin film transistor (TFT) LCD
panels, parallel ADCs and DACs, video encoders and decoders,
image sensor modules, and other general-purpose peripherals.
The features supported in the EPPI module include the
following:
• Programmable data length of 8 bits, 10 bits, 12 bits, 14 bits,
16 bits, 18 bits, and 24 bits per clock
S/PDIF-Compatible Digital Audio Receiver/Transmitter
• Various framed, nonframed, and general-purpose operat-
ing modes. Frame syncs can be generated internally or can
be supplied by an external device.
The Sony/Philips Digital Interface Format (S/PDIF) is a stan-
dard audio data transfer format that allows the transfer of digital
audio signals from one device to another. There are two S/PDIF
transmit/receive blocks on the processor. The digital audio
interface carries three types of information: audio data, nonau-
dio data (compressed data), and timing information.
• ITU-656 status word error detection and correction for
ITU-656 receive modes and ITU-656 preamble and status
word decoding
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• Optional packing and unpacking of data to/from 32 bits
from/to 8 bits, 16 bits, and 24 bits. If packing/unpacking is
enabled, configure endianness to change the order of pack-
ing/unpacking of bytes or words.
slave devices to interface with fast master devices by providing
an SPI ready pin (SPI_RDY), which flexibly controls the
transfers.
The baud rate and clock phase and polarities of the SPI port are
programmable. The port has integrated DMA channels for both
transmit and receive data streams.
• RGB888 can be converted to RGB666 or RGB565 for trans-
mit modes.
• Various deinterleaving/interleaving modes for receiving or
transmitting 4:2:2 YCrCb data
Octal Serial Peripheral Interface (OSPI) Port
The octal serial peripheral interface (OSPI) port provides an
increased external memory data bus width (up to eight bits in
parallel). The OSPI port supports dual data rate (DDR) modes
of operation, which enable the transfer of up to 16 bits of data
each clock cycle. The OSPI port provides overall data through-
put and performance improvement, including faster boot time.
• Configurable LCD data enable output available on Frame
Sync 3
Universal Asynchronous Receiver/Transmitter
(UART) Ports
The processors provide four full-duplex universal asynchronous
receiver/transmitter (UART) ports, fully compatible with PC
standard UARTs. Each UART port provides a simplified UART
interface to other peripherals or hosts, supporting full-duplex,
DMA supported, asynchronous transfers of serial data. A UART
port includes support for five to eight data bits as well as no par-
ity, even parity, or odd parity.
Features of the OSPI port include:
• Support for single-, dual-, quad-, or octal-I/O transfers
• Multiple modes of operation including direct and software
triggered instruction generator (STIG)
• Support for execute in place (XIP): continuous mode
• Programmable page and block sizes
• Programmable write protected regions
• Programmable memory timing
Optionally, an additional address bit can be transferred to inter-
rupt only addressed nodes in multidrop bus (MDB) systems. A
frame is terminated by a configurable number of stop bits.
The UART ports support automatic hardware flow control
through the clear to send (CTS) input and request to send (RTS)
output with programmable assertion first in, first out (FIFO)
levels.
• Support for DDR commands
• Support for PHY mode of operation to enable high speed
transfers
• Support for DQS to increase robustness of data sampling at
higher speeds
To help support the Local Interconnect Network (LIN) proto-
cols, a special command causes the transmitter to queue a break
command of programmable bit length into the transmit buffer.
Similarly, the number of stop bits can be extended by a pro-
grammable interframe space.
Link Port (LP)
Two 8-bit wide link ports (LPs) can connect to the link ports of
other DSPs or peripherals. Link ports are bidirectional and have
eight data lines, an acknowledge line, and a clock line.
Serial Peripheral Interface (SPI) Ports
The processors have four industry-standard SPI-compatible
ports that allow the processors to communicate with multiple
SPI-compatible devices.
Link ports can operate in reduced pin mode, thereby reducing
the number of pins required to interface between two proces-
sors. For example, two processors can be connected using the
link port in 4-bit single data rate (SDR) and dual data rate
(DDR) modes.
The baseline SPI peripheral is a synchronous, 4-wire interface
consisting of two data pins, one device select pin, and a gated
clock pin. The two data pins allow full-duplex operation to
other SPI-compatible devices. An extra two (optional) data pins
are provided to support quad-SPI operation. Enhanced modes
of operation, such as flow control, fast mode, and dual-I/O
mode (DIOM), are also supported. DMA mode allows for trans-
ferring several words with minimal central processing unit
(CPU) interaction.
Ethernet Media Access Controller (EMAC)
The processor features an ethernet media access controller
(EMAC): 10/100/1000 AVB Ethernet with precision time proto-
col (IEEE 1588).
The processors can directly connect to a network through
embedded fast EMAC that supports 10Base-T (10 Mb/sec),
100Base-T (100 Mb/sec) and 1000Base-T (1 Gb/sec) operations.
With a range of configurable options, the SPI ports provide a
glueless hardware interface with other SPI-compatible devices
in master mode, slave mode, and multimaster environments.
The SPI peripheral includes programmable baud rates, clock
phase, and clock polarity. The peripheral can operate in a multi-
master environment by interfacing with several other devices,
acting as either a master device or a slave device. In a multimas-
ter environment, the SPI peripheral uses open-drain outputs to
avoid data bus contention. The flow control features enable slow
Some standard features of the EMAC are as follows:
• Support of MII/RMII/RGMII protocols for external PHYs
• Full-duplex and half-duplex modes
• Media access management (in half-duplex operation)
• Flow control
• Station management, including the generation of
MDC/MDIO frames for read/write access to PHY registers
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Some advanced features of the EMAC include the following:
• Automatic detection of IPv4 and IPv6 packets, as well as
PTP messages
• Automatic checksum computation of IP header and IP
payload fields of receive frames
• Multiple input clock sources (SCLK0, RGMII, RMII, MII
clock, and external clock)
• Independent 32-bit descriptor driven receive and transmit
DMA channels
• Programmable pulse per second (PPS) output
• Auxiliary snapshot to time stamp external events
• Frame status delivery to memory through DMA, including
frame completion semaphores for efficient buffer queue
management in software
Controller Area Network with Flexible Data-Rate
(CAN FD)
• Transmit DMA support for separate descriptors for MAC
header and payload fields to eliminate buffer copy
operations
There are two controller area network (CAN) modules. A CAN
controller implements the CAN with flexible data-rate (CAN
FD) and the CAN 2.0B protocol supporting both standard and
extended message frames and long payloads up to 64 bytes,
transferred at rates of up to 8 Mbps. This protocol is an
asynchronous communications protocol used in both industrial
and automotive control systems. The CAN protocol is well
suited for control applications due to the capability to commu-
nicate reliably over a network. This is because the protocol
incorporates CRC checking, message error tracking, and fault
node confinement.
• Convenient frame alignment modes
• 47 MAC management statistics counters with selectable
clear on read behavior and programmable interrupts on
half maximum value
• Advanced power management
• Magic packet detection and wakeup frame filtering
• Support for 802.3Q tagged VLAN frames
• Programmable MDC clock rate and preamble suppression
The CAN FD controller offers the following features:
• Flexible mailboxes configurable to store 0 to 8, 16, 32, or 64
bytes
Audio Video Bridging (AVB) Support
The 10/100/1000 EMAC supports the following audio video
bridging (AVB) features:
• Dedicated receiver masks for each mailbox
• Flexible message buffers up to 64 buffers of 8 bytes length
each, configurable as receive or transmit
• Separate channels or queues for AV data transfer in
100 Mbps and 1000 Mbps modes
• Programmable transmission priority scheme
• IEEE 802.1-Qav specified credit-based shaper (CBS) algo-
rithm for the additional transmit channels
• Transceiver delay compensation when transmitting CAN
FD messages at faster data rates
• Configuring up to two additional channels (Channel 1 and
Channel 2) on the transmit and receive paths for AV traffic.
Channel 0 is available by default and carries the legacy best
effort Ethernet traffic on the transmit side.
• Memory read accesses error detection and correction
An additional crystal is not required to supply the CAN clock
because it is derived from a system clock through a programma-
ble divider.
• Separate DMA, transmit and receive FIFO for AVB latency
class
Timers
• Programmable control to route received VLAN tagged non
AV packets to channels or queues
The processors include several timers that are described in the
following sections.
Precision Time Protocol (PTP) IEEE 1588 Support
General-Purpose (GP) Timers (TIMER)
The IEEE 1588 standard is a precision clock synchronization
protocol for networked measurement and control systems. The
processors include hardware support for IEEE 1588 with an
integrated precision time protocol synchronization engine
(PTP_TSYNC).
There is one general-purpose (GP) timer unit, providing 16 GP
programmable timers. Each timer has an external pin that can
be configured as PWM or timer output, as an input to clock the
timer, or as a mechanism for measuring pulse widths and peri-
ods of external events. These timers can be synchronized to an
external clock input on the TM_TMR[n] pins, an external
TM_CLK input pin, or to the internal SCLK0.
This engine provides hardware assisted time stamping to
improve the accuracy of clock synchronization between PTP
nodes. The main features of the engine include the following:
These timer units can be used in conjunction with the UARTs
and the CAN controller to measure the width of the pulses in
the data stream to provide a software autobaud detect function
for the respective serial channels.
• Support for both IEEE 1588-2002 and IEEE 1588-2008 pro-
tocol standards
• Hardware assisted time stamping capable of up to 12.5 ns
resolution
The GP timers can generate interrupts to the processor core,
providing periodic events for synchronization to either the sys-
tem clock or to external signals. Timer events can also trigger
other peripherals via the TRU (for instance, to signal a fault).
• Lock adjustment
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Each timer can also be started and stopped by any trigger gener-
ator without core intervention. While the ADSP-21591 and
ADSP-21593 processors feature 16 GP timers, timer units TIM-
ER10-TIMER15 have no external pins and can only be
configured for internal modes of operation.
For the ADSP-SC592 and ADSP-SC594 processors, the follow-
ing features extend the baseline features above:
• Total of eight single-ended input channels that can be fur-
ther extended to 15 channels by connecting the
HADC_MUX_PIN_NAME pin(s) to an external channel
multiplexer
Watchdog Timer (WDT)
• Autosequencing capability with up to a total of eight auto-
conversions in a single session. Each conversion can be
programmed to select one to fifteen input channels.
Three on-chip software watchdog timers (WDT) can be used by
the Arm Cortex-A5 and/or SHARC+ cores. A software watch-
dog can improve system availability by forcing the processors to
a known state, via a general-purpose interrupt, or a fault, if the
timer expires before being reset by software.
• 16 data registers (individually addressable) to store conver-
sion values
The programmer initializes the count value of the timer, enables
the appropriate interrupt, then enables the timer. Thereafter,
the software must reload the counter before it counts down to
zero from the programmed value, protecting the system from
remaining in an unknown state where software that normally
resets the timer stops running due to an external noise condi-
tion or software error.
USB 2.0 High Speed (HS) On the Go (OTG) Controller
The USB supports high speed/full speed/low speed (HS/FS/LS)
USB2.0 on the go (OTG) and UTMI+ low pin interface (USBC).
The USB 2.0 OTG dual-role device controller provides a low
cost connectivity solution in industrial applications, as well as
consumer mobile devices such as cell phones, digital still
cameras, and MP3 players. The USB 2.0 controller allows these
devices to transfer data using a point to point USB connection
without the need for a PC host. The module can operate in a tra-
ditional USB peripheral only mode as well as the host mode
presented in the OTG supplement to the USB 2.0 specification.
General-Purpose Counters (CNT)
A 32-bit general-purpose counter (CNT) is provided that can
operate in general-purpose up/down count modes and can
sense 2-bit quadrature or binary codes as typically emitted by
industrial drives or manual thumbwheels. Count direction is
controlled by a level-sensitive input pin or by two edge
detectors.
The USB controller does not have an integrated on-chip PHY
and must connect to an external PHY on the board through an
USBC 8-bit interface supported by the USB controller.
A third counter input can provide flexible zero marker support
and can input the push button signal of thumbwheel devices. All
three CNT0 pins have a programmable debouncing circuit.
Media Local Bus (MediaLB)
The automotive model has a Microchip MediaLB (MLB) device
interface that allows the processors to function as a media local
bus device. It includes support for both 3-pin and 6-pin media
local bus protocols. The MLB 3-pin configuration supports
speeds up to 1024 × FS. The MLB 6-pin configuration supports
speed of 2048 × FS. The MLB also supports up to 64 logical
channels with up to 468 bytes of data per MLB frame.
Internal signals forwarded to a GP timer enable the timer to
measure the intervals between count events. Boundary registers
enable auto-zero operation or simple system warning by inter-
rupts when programmed count values are exceeded.
Housekeeping Analog-to-Digital Converter (HADC)
The housekeeping analog-to-digital converter (HADC) pro-
vides a general-purpose, multichannel, successive
approximation ADC. The following baseline HADC features
apply to all models:
The MLB interface supports MOST25, MOST50, and MOST150
data rates and operates in device mode only.
2-Wire Controller Interface (TWI)
The processors include six 2-wire interface (TWI) modules that
provide a simple exchange method of control data between mul-
tiple devices. The TWI module is compatible with the widely
used I2C bus standard. The TWI module offers the capabilities
of simultaneous controller and target operation and support for
both 7-bit addressing and multimedia data arbitration. The
TWI interface utilizes two pins for transferring clock
(TWI_SCL) and data (TWI_SDA) and supports the protocol at
speeds up to 400 kbps. The TWI interface pins are compatible
with 3.3 V logic levels.
• 12-bit ADC core with built in sample and hold
• Throughput rates up to 1 MSPS
• Single external reference with analog inputs between
0 V and 1.8 V
• Selectable ADC clock frequency including the ability to
program a prescaler
• Adaptable conversion type; allows single or continuous
conversion with option of autoscan
• Four single-ended input channels
Additionally, the TWI module is fully compatible with serial
camera control bus (SCCB) functionality for easier control of
various CMOS camera sensor devices.
• Autosequencing capability with up to four autoconversions
in a single session. Each conversion can be programmed to
select one to four input channels.
• Four data registers (individually addressable) to store con-
version values
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SHARC core clock frequency. The FIR accelerator can access all
memory spaces and can run concurrently with the other accel-
erators on the processor.
General-Purpose I/O (GPIO)
Each general-purpose port pin can be individually controlled by
manipulating the port control, status, and interrupt registers:
Infinite Impulse Response (IIR) Accelerator
• The GPIO direction control register specifies the direction
of each individual GPIO pin as input or output.
The infinite impulse response (IIR) accelerator consists of a
1440 word coefficient memory for storage of biquad coeffi-
cients, a data memory for storing the intermediate data, and one
MAC unit. A controller manages the accelerator. The IIR
accelerator runs at the SHARC core clock frequency. The IIR
accelerator can access all memory spaces and run concurrently
with the other accelerators on the processor.
• GPIO control and status registers have a write-one-to-
modify mechanism that allows any combination of individ-
ual GPIO pins to be modified in a single instruction,
without affecting the level of any other GPIO pins.
• GPIO interrupt mask registers allow each individual GPIO
pin to function as an interrupt to the processors. GPIO pins
defined as inputs can be configured to generate hardware
interrupts, whereas output pins can be triggered by soft-
ware interrupts.
Note: There are four IIR accelerators per SHARC core.
SYSTEM DESIGN
The following sections provide an introduction to system design
features and power supply issues.
• GPIO interrupt sensitivity registers specify whether indi-
vidual pins are level or edge sensitive and specify, if edge
sensitive, whether the rising edge or both the rising and
falling edges of the signal are significant.
Clock Management
The processors provide three operating modes, each with a dif-
ferent performance and power profile. Control of clocking to
each of the processor peripherals reduces power consumption.
The processors do not support any low power operation modes.
Control of clocking to each of the processor peripherals can
reduce the power consumption.
Pin Interrupts
Every port pin on the processors can request interrupts in either
an edge sensitive or a level sensitive manner with programmable
polarity. Interrupt functionality is decoupled from GPIO opera-
tion. Eight system level interrupt channels (PINT0–PINT7) are
reserved for this purpose. Each of these interrupt channels can
manage up to 32 interrupt pins. The assignment from pin to
interrupt is not performed on a pin by pin basis. Rather, groups
of eight pins (half ports) are flexibly assigned to interrupt
channels.
Reset Control Unit (RCU)
Reset is the initial state of the whole processor, or the core, and
is the result of a hardware or software triggered event. In this
state, all control registers are set to default values and functional
units are idle. Exiting a full system reset begins with the core
ready to boot.
Every pin interrupt channel features a special set of 32-bit mem-
ory-mapped registers that enable half port assignment and
interrupt management. This functionality includes masking,
identification, and clearing of requests. These registers also
enable access to the respective pin states and use of the interrupt
latches, regardless of whether the interrupt is masked. Most
control registers feature multiple MMR address entries to write
one to set or write one to clear them individually.
The reset control unit (RCU) controls how all the functional
units enter and exit reset. Differences in functional require-
ments and clocking constraints define how reset signals are
generated. Programs must guarantee that none of the reset
functions put the system into an undefined state or cause
resources to stall. This requirement is particularly important
when the core resets (programs must ensure that there is no
pending system activity involving the core when it is reset).
Core Flags I/O Pins
The processor features 32 flag I/O pins (16 per SHARC+ core),
which allow for external control and monitoring of the
SHARC+ core FLAGS register. User code can write to bits in
this register to be driven to pins configured as outputs, and code
execution can be made conditional based on the settings of the
pins configured as inputs.
From a system perspective, reset is defined by both the reset tar-
get and the reset source.
The reset target is defined as the following:
• System reset—all functional units except the RCU are set to
default states.
• Hardware reset—all functional units are set to default states
without exception. History is lost.
SYSTEM ACCELERATION
The following sections describe the system acceleration blocks
of the ADSP-2159x/ADSP-SC59x processors.
• Core only reset—affects the core only. When in reset state,
the core is not accessed by any bus requester.
Finite Impulse Response (FIR) Accelerator
The reset source is defined as the following:
The finite impulse response (FIR) accelerator consists of a
1024 word coefficient memory, a 1024 word deep delay line for
the data, and four multiplier-accumulator (MAC) units. A con-
troller manages the accelerator. The FIR accelerator runs at the
• System reset—can be triggered by software (writing to the
RCU_CTL register) or by another functional unit, such as
the dynamic power management (DPM) unit or any of the
SEC, TRU, or emulator inputs.
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• Hardware reset—the SYS_HWRST input signal asserts
active (pulled down).
SHARC® PROCESSOR
TO PLL
CIRCUITRY
• Core only reset—affects only the core. The core is not
accessed by any bus requester when in reset state.
• Trigger request (peripheral).
Clock Generation Unit (CGU)
The ADSP-2159x/ADSP-SC59x processors support two inde-
pendent PLLs. Each PLL is part of a clock generation unit
(CGU). Each CGU can be either driven externally by the same
clock source or driven by separate sources, thus providing flexi-
bility in determining the internal clocking frequencies for each
clock domain.
SYS_CLKIN
7%'ꢀNȍ*
SYS_XTAL
7%'ꢀNȍ*
TBD pF*
TBD pF*
Frequencies generated by each CGU are derived from a com-
mon multiplier with different divider values available for each
output.
NOTE: VALUES MARKED WITH * MUST BE CUSTOMIZED, DEPENDING
ON THE CRYSTAL AND LAYOUT. ANALYZE CAREFULLY. VALID
FREQUENCY RANGE IS 20 MHz TO 30 MHz FOR SYS_CLKIN.
The CGU generates all on-chip clocks and synchronization sig-
nals. Multiplication factors are programmed to define the
PLLCLK frequency.
Figure 6. External Crystal Connection
Programmable values divide the PLLCLK frequency to generate
the core clock (CCLK), the system clocks, the DDR3/DDR3L
clock (DCLK), and the output clock (OCLK). For more infor-
mation on clocking, see the ADSP-2159x/ADSP-SC591/592/594
SHARC+ Processor Hardware Reference.
facturer. The user must verify the customized values based on
careful investigations on multiple devices over the required
temperature range.
Clock Distribution Unit (CDU)
Writing to the CGU control registers does not affect the behav-
ior of the PLL immediately. Registers are first programmed with
a new value and the PLL logic executes the changes to ensure
smooth transitions from the current conditions to the new
conditions.
The two clock generation units each provide outputs that feed a
clock distribution unit (CDU). The clock outputs
CLKO0–CLKO12 are connected to various targets. For more
information, refer to the ADSP-2159x/ADSP-SC591/592/594
SHARC+ Processor Hardware Reference.
System Crystal Oscillator
Clock Out/External Clock
The processor can be clocked by an external crystal
The SYS_CLKOUT output pin has programmable options to
output divided down versions of the on-chip clocks. By default,
the SYS_CLKOUT pin drives a buffered version of the
SYS_ CLKIN0 input. Refer to the ADSP-2159x/ADSP-
SC591/592/594 SHARC+ Processor Hardware Reference to
change the default mapping of clocks.
(see Figure 6), a sine wave input, or a buffered, shaped clock
derived from an external clock oscillator. If using an external
clock, it must be compatible with the VIHCLKIN and VILCLKIN
specifications and must not be halted, changed, or operated
below the specified frequency during normal operation (see the
Preliminary Operating Conditions section). This signal is con-
nected to the SYS_CLKINx pin of the processor. When using an
external clock, the SYS_XTALx pin must be left unconnected.
Alternatively, because the processor includes an on-chip oscilla-
tor circuit, an external crystal can be used.
Booting
The processors have several mechanisms for automatically load-
ing internal and external memory after a reset. The boot mode is
defined by the SYS_BMODE[n] input pins. There are two cate-
gories of boot modes. In flash boot modes, the processors
actively load data from serial memories. In external host boot
modes, the processors receive data over a serial interface from
an external host device.
For fundamental frequency operation, use the circuit shown in
Figure 6. A parallel resonant, fundamental frequency, micro-
processor grade crystal is connected across the SYS_CLKINx
pin and the SYS_XTALx pin.
The two capacitors and the series resistor, shown in Figure 6,
fine tune phase and amplitude of the sine frequency. The capac-
itor and resistor values shown in Figure 6 are typical values
only. The capacitor values are dependent upon the load capaci-
tance recommendations of the crystal manufacturer and the
physical layout of the printed circuit board (PCB). The resistor
value depends on the drive level specified by the crystal manu-
The boot modes are shown in Table 7. These modes are imple-
mented by the SYS_BMODE[n] bits of the reset configuration
register and are sampled during power-on resets and software
initiated resets.
In the ADSP-SC59x processors, the Arm Cortex-A5 (Core 0)
controls the boot process, including loading all internal and
external memory. Likewise, in the ADSP-2159x processors, the
SHARC+ (Core 1) controls the boot function. The option for
secure boot is available on all models.
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Preliminary Technical Data ADSP-21591/21593/21594/ADSP-SC591/SC592/SC594
Table 7. Boot Modes
Table 8. Power Domains
SYS_BMODE[n] Setting
Boot Mode
Power Domain
All Internal Logic
DDR3/DDR3L
HADC/TMU
VDD Range
VDD_INT
000
001
010
011
100
101
110
No boot
SPI2 flash
VDD_DMC
External SPI2 host
External UART0 host
External LP0 host
Octal SPI flash
Reserved
VDD_ANA
1
SYS_CLKIN0/1
PLL0/1
VDD_REF
VDD_PLL
All Other I/O (Includes SYS, JTAG, and VDD_EXT
Ports Pins)
1 VDD_REF requires a minimum of 10 nF and 100 nF decoupling capacitance to
meet source/sink requirements.
Thermal Monitoring Unit (TMU)
The thermal monitoring unit (TMU) provides on-chip tem-
perature measurement for applications that require substantial
power consumption. The TMU is integrated into the processor
die and digital infrastructure using an MMR-based system
access to measure the die temperature variations in real-time.
Power-Up and Power-Down Sequencing
At all times (including during power-up/power-down sequenc-
ing), the VDD_REF, VDD_ANA, and VDD_EXT supplies must
stay within the VDELTA_EXT_REF specification listed in the Pre-
liminary Operating Conditions table. SYS_XTAL0 and
SYS_XTAL1 oscillations (SYS_CLKIN0 and SYS_CLKIN1)
start when power is applied to the VDD_REF pins. The rising
edge of SYS_HWRST initiates the PLL locking sequence. The
rising edge of SYS_HWRST must occur after all voltage supplies
and SYS_CLKIN0 and SYS_CLKIN1 oscillations are valid. For
further details and information, see the Power-Up Reset Timing
section.
TMU features include the following:
• On-chip temperature sensing
• Programmable over temperature and under temperature
limits
• Programmable conversion rate
• Averaging feature available
Power Supplies
Target Board JTAG Emulator Connector
The processors have separate power supply connections for
• Internal (VDD_INT)
The Analog Devices DSP tools product line of JTAG emulators
uses the IEEE 1149.1 JTAG test access port of the processors to
monitor and control the target board processor during emula-
tion. The Analog Devices DSP tools product line of JTAG
emulators provides emulation at full processor speed, allowing
inspection and modification of memory, registers, and proces-
sor stacks. The processor JTAG interface ensures the emulator
does not affect target system loading or timing.
• External (VDD_EXT)
• External (VDD_REF)
• HADC/TMU (VDD_ANA)
• DMC (VDD_DMC)
• PLL (VDD_PLL)
For information on JTAG emulator operation, see the appropri-
ate emulator hardware user’s guide at SHARC Processors
Software and Tools.
All power supplies must meet the specifications provided in the
Preliminary Operating Conditions section. All external supply
pins must be connected to the same power supply.
SYSTEM DEBUG
Power Management
The processors include various features that allow easy system
debug. These are described in the following sections.
As shown in Table 8, the processors support six different power
domains, which maximizes flexibility while maintaining com-
pliance with industry standards and conventions.
System Watchpoint Unit (SWU)
The system watchpoint unit (SWU) is a single module that
connects to a single system bus and provides transaction moni-
toring. One SWU is attached to the bus going to each system
completer. The SWU provides ports for all system bus address
channel signals. Each SWU contains four match groups of
registers with associated hardware. These four SWU match
groups operate independently but share common event (for
example, interrupt and trigger) outputs.
The power dissipated by a processor is largely a function of the
clock frequency and the square of the operating voltage. For
example, reducing the clock frequency by 25% results in a 25%
reduction in dynamic power dissipation.
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ADSP-21591/21593/21594/ADSP-SC591/SC592/SC594 Preliminary Technical Data
Devices processors. The full CCES license type also enables use
of ICE-2000 or ICE-1000 emulators for higher performance
debugging via JTAG.
Debug Access Port (DAP)
The debug access port (DAP) provides IEEE 1149.1 JTAG inter-
face support through the JTAG debug. The DAP provides an
optional instrumentation trace for both the core and system. It
provides a trace stream that conforms to MIPI System Trace
Protocol version 2 (STPv2).
When a SOM board is mounted to a SOM carrier board,
embedded system evaluation can be performed. The EZ-KIT
SOM carrier board provides an evaluation platform for various
system peripherals including audio, S/PDIF, CAN, MLB, USB,
10/100/1000 Ethernet, and A2B, as well as an OSPI flash mem-
ory. The EZ-KIT SOM carrier board also features the USB
Debug Agent, which allows for debug and evaluation of the full
system (including the processor/memory on the SOM module)
without an emulator.
DEVELOPMENT TOOLS
Analog Devices supports its processors with a complete line of
software and hardware development tools, including an inte-
grated development environment, evaluation products,
emulators, and a variety of software add-ins.
For further information, see:
Integrated Development Environment
• www.analog.com/cces
For C/C++ software writing and editing, code generation, and
debug support, Analog Devices offers the CrossCore® Embed-
ded Studio (CCES) integrated development environment (IDE).
• www.analog.com/EV-21593-SOM (TBD)
• www.analog.com/EV-SC594-SOM (TBD)
• www.analog.com/EV-SOMCRR-EZKIT
CCES is based on the Eclipse framework. Supporting most Ana-
log Devices processor families, CCES is the IDE of choice for
processors, including multicore devices.
Software Add-Ins for CCES
Analog Devices offers software add-ins which seamlessly inte-
grate with CCES to extend the capabilities and reduce
development time. Add-ins include BSPs for evaluation hard-
ware, various middleware packages, and algorithmic modules.
Documentation, help, configuration dialogs, and coding exam-
ples present in these add-ins are viewable through the CCES
IDE upon add-in installation.
CCES seamlessly integrates available software add-ins to sup-
port real-time operating systems, file systems, TCP/IP stacks,
USB stacks, algorithmic software modules, and evaluation hard-
ware board support packages (BSPs). For more information,
visit www.analog.com/cces.
EZ-KIT Evaluation Systems
For processor evaluation, Analog Devices provides EZ-KIT®
evaluation systems (EV-SC594-EZKIT and EV-21593-EZKIT),
which are bundles comprised of a System on Module (SOM)
board (EV-SC594-SOM or EV-21593-SOM) and an EZ-KIT
SOM carrier board (EV-SOMCRR-EZKIT).
Board Support Packages (BSPs) for Evaluation Hardware
Software support for the EZ-KIT evaluation systems is provided
by software add-ins called board support packages (BSPs). The
BSPs contain the required drivers, pertinent release notes, and
select example code for the given evaluation hardware. A down-
load link for a specific BSP is located on the web page for the
associated SOM product.
SOM boards are small and low cost. The EV-SC594-SOM and
EV-21593-SOM boards either have the ADSP-SC594 or ADSP-
21593 processor, SDRAM and QSPI flash memories, JTAG
debug connection, FTDI USB-to-UART, and USB power. SOM
boards can be used alone or in combination with a SOM carrier
board. SOM carrier boards have high speed connectors for the
SOM, a comprehensive set of peripherals, and an on-board
emulator. Each SOM carrier board also comes with a power
supply.
Middleware Packages
Analog Devices offers middleware add-ins such as real-time
operating systems, file systems, USB stacks, and TCP/IP stacks.
For more information, see the Operating Systems and Middle-
ware page.
Algorithmic Modules
The USB controller on the SOM carrier board connects to the
USB port of the user’s PC, enabling CCES to emulate the on-
board processor in circuit. This permits users to download, exe-
cute, and debug programs. It also supports in-circuit
programming of the on-board flash memory device to store
user-specific boot code, enabling standalone operation.
To speed development, Analog Devices offers add-ins that per-
form popular audio and video processing algorithms. These are
available for use with CCES. For more information, visit the
Design Center.
Designing an Emulator-Compatible DSP Board (Target)
Each EZ-KIT purchased includes an evaluation license for
CCES. The CCES evaluation license type restricts CCES features
to specific evaluation systems. With the full CCES license type
(sold separately), engineers can develop software for any of the
CCES-supported evaluation boards (including the SOM when
used standalone or when connected to a different carrier board)
or any custom system designed around supported Analog
For embedded system test and debug, Analog Devices provides
a family of emulators. On each JTAG DSP, Analog Devices sup-
plies an IEEE 1149.1 JTAG test access port (TAP). In-circuit
emulation is facilitated by use of this JTAG interface. The
emulator accesses the internal features of the processor via the
TAP, allowing the developer to load code, set breakpoints, and
view variables, memory, and registers.
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Preliminary Technical Data ADSP-21591/21593/21594/ADSP-SC591/SC592/SC594
The processor must be halted to send data and commands, but
after an operation is completed by the emulator, the DSP system
is set to run at full speed with no impact on system timing. The
emulators require the target board to include a header that sup-
ports connection of the JTAG port of the DSP to the emulator.
For details on target board design issues including mechanical
layout, single processor connections, signal buffering, signal ter-
mination, and emulator pod logic, see Analog Devices JTAG
Emulation Technical Reference (EE-68).
ADDITIONAL INFORMATION
This data sheet provides a general overview of the ADSP-
2159x/ADSP-SC59x architecture and functionality. For detailed
information on the core architecture and instruction set, refer to
the SHARC+ Core Programming Reference.
RELATED SIGNAL CHAINS
A signal chain is a series of signal conditioning electronic com-
ponents that receive input (data acquired from sampling either
real-time phenomena or from stored data) in tandem, with the
output of one portion of the chain supplying input to the next.
Signal chains are often used in signal processing applications to
gather and process data or to apply system controls based on
analysis of real-time phenomena.
Analog Devices eases signal processing system development by
providing signal processing components that are designed to
work together. A tool for viewing relationships between specific
applications and related components is available at
www.analog.com\circuits.
The application signal chains page in the Circuits from the Lab®
site (www.analog.com\circuits) provides the following:
• Graphical circuit block diagram presentation of signal
chains for a variety of circuit types and applications
• Drill down links for components in each chain to selection
guides and application information
• Reference designs applying best practice design techniques
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ADSP-2159x/ADSP-SC59x DETAILED SIGNAL DESCRIPTIONS
Table 9 provides a detailed description of each pin.
Table 9. ADSP-2159x/ADSP-SC59x Detailed Signal Descriptions
Signal Name
C1_FLG[n]
C2_FLG[n]
CANFD_RX
CANFD_TX
CNT_DG
Direction Description
InOut
InOut
Input
Output
Input
Core 1 FLAGS I/O n. External pins associated with the core FLAGS register on SHARC+ core 1.
Core 2 FLAGS I/O n. External pins associated with the core FLAGS register on SHARC+ core 2.
Receive. Typically an external CAN transceiver RX output.
Transmit. Typically an external CAN transceiver TX input.
Count Down and Gate. Depending on the mode of operation, this input acts either as a count down
signal or a gate signal.
Count Down—this input causes the GP counter to decrement.
Gate—stops the GP counter from incrementing or decrementing.
CNT_UD
Input
Count Up and Direction. Depending on the mode of operation this input acts either as a count up
signal or a direction signal.
Count Up—this input causes the GP counter to increment.
Direction—selects whether the GP counter is incrementing or decrementing.
CNT_ZM
Input
InOut
Count Zero Marker. Input that connects to the zero marker output of a rotary device or detects the
pressing of a pushbutton.
DAI_PIN[nn]
Pin n. The digital applications interface (DAI0) connects various peripherals to any of the DAI0_PINxx
pins. Programs make these connections using the signal routing unit (SRU/DRU). DRU allows routing
of any signal across the DAIs.
DMC_A[nn]
DMC_BA[n]
Output
Output
Address n. Address bus.
Bank Address Input n. Defines which internal bank an activate, read, write, or precharge command
is applied to on the dynamic memory. Bank Address n also defines which mode registers (MR, EMR,
EMR2, and/or EMR3) load during the load mode register command.
DMC_CAS
Output
Column Address Strobe. Defines the operation for external dynamic memory to perform in
conjunction with other DMC command signals. Connect to the CAS input of dynamic memory.
DMC_CK
Output
Output
Output
Output
InOut
Clock. Outputs DCLK to external dynamic memory.
DMC_CK
Clock (Complement). Complement of DMC_CK.
DMC_CKE
DMC_CS[n]
DMC_DQ[nn]
DMC_LDM
Clock Enable. Active high clock enables. Connects to the CKE input of the dynamic memory.
Chip Select n. Commands are recognized by the memory only when this signal is asserted.
Data n. Bidirectional data bus.
Output
Data Mask for Lower Byte. Mask for DMC_DQ07:DMC_DQ00 write data when driven high. Sampled
on both edges of the data strobe by the dynamic memory.
DMC_LDQS
DMC_LDQS
DMC_ODT
DMC_RAS
InOut
Data Strobe for Lower Byte. DMC_DQ07:DMC_DQ00 data strobe. Output with write data. Input with
read data. Can be single-ended or differential depending on register settings.
InOut
Data Strobe for Lower Byte (Complement). Complement of DMC_LDQS. Not used in single-ended
mode.
Output
Output
On Die Termination. Enables dynamic memory termination resistances when driven high (assuming
the memory is properly configured). ODT is enabled or disabled regardless of read or write commands.
Row Address Strobe. Defines the operation for external dynamic memory to perform in conjunction
with other DMC command signals. Connect to the RAS input of dynamic memory.
DMC_RESET
DMC_RZQ
DMC_UDM
Output
InOut
Reset.
External Calibration Resistor Connection.
Output
Data Mask for Upper Byte. Mask for DMC_DQ15:DMC_DQ08 write data when driven high. Sampled
on both edges of the data strobe by the dynamic memory.
DMC_UDQS
DMC_UDQS
InOut
InOut
Data Strobe for Upper Byte. DMC_DQ15:DMC_DQ08 data strobe. Output with write data. Input with
read data. Can be single-ended or differential depending on register settings.
Data Strobe for Upper Byte (Complement). Complement of DMC_UDQS. Not used in single-ended
mode.
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Table 9. ADSP-2159x/ADSP-SC59x Detailed Signal Descriptions (Continued)
Signal Name
DMC_VREF[n]
DMC_WE
Direction Description
Input
Voltage Reference. Connects to half of the VDD_DMC voltage.
Output
Write Enable. Defines the operation for external dynamic memory to perform in conjunction with
other DMC command signals. Connect to the WE input of dynamic memory.
ETH_COL
ETH_CRS
Input
Input
MII Collision Detect. Collision detect input signal valid only in MII.
MII Carrier Sense. Asserted by the PHY when either the transmit or receive medium is not idle.
Deasserted when both are idle. This signal is not used in RMII/RGMII modes.
ETH_MDC
Output
InOut
Input
Management Channel Clock. Clocks the MDC input of the PHY for RMII/RGMII.
ETH_MDIO
Management Channel Serial Data. Bidirectional data bus for PHY control for RMII/RGMII.
ETH_PTPAUXIN[n]
PTP Auxiliary Trigger Input. Assert this signal to take an auxiliary snapshot of the time and store it
in the auxiliary time stamp FIFO.
ETH_PTPCLKIN[n]
ETH_PTPPPS[n]
Input
PTP Clock Input. Optional external PTP clock input.
Output
PTP Pulse Per Second Output. When the advanced time stamp feature enables, this signal is asserted
based on the PPS mode selected. Otherwise, this signal is asserted every time the seconds counter is
incremented.
ETH_REFCLK
Input
Input
Reference Clock. Externally supplied Ethernet clock.
ETH_RXCLK_REFCLK
RXCLK (10/100/1000) or REFCLK (10/100).
ETH_RXCTL_CRSRX_DV InOut
RXCTL (10/100/1000) or CRSRX_DV (10/100). In RGMII mode, RXCTL multiplexes receive data valid
and receiver error. In RMII mode, CRSRX_DV is carrier sense and receive data valid (CRS_DV), multi-
plexed on alternating clock cycles. In MII mode, CRSRX_DV is receive data valid (RX_DV), asserted by
the PHY when the data on ETH_RXD[n] is valid.
ETH_RXD[n]
Input
Receive Data n. Receive data bus.
ETH_RXERR
Input
Receive Error.
ETH_TXCLK
Input
Reference Clock. Externally supplied Ethernet clock.
TXCTL (10/100/1000) or TXEN (10/100).
Transmit Data n. Transmit data bus.
ETH_TXCTL_TXEN
ETH_TXD[n]
Output
Output
Output
Output
ETH_TXEN
Transmit Enable. When asserted, this signal indicates the data on ETH_TXD[n] is valid.
HADC_EOC_DOUT
End of Conversion/Serial Data Out. Transitions high for one cycle of the HADC internal clock at the
end of every conversion. Alternatively, HADC serial data out can be seen by setting the appropriate
bit in HADC_CTL.
HADC_MUX[n]
Output
Controls to External Multiplexer. Allows additional input channels when connected to an external
multiplexer.
HADC_VIN[n]
HADC_VREFN
Input
Input
Analog Input at Channel n. Analog voltage inputs for digital conversion.
Ground Reference for ADC. Connect to an external voltage reference that meets data sheet
specifications.
HADC_VREFP
Input
External Reference for ADC. Connect to an external voltage reference that meets data sheet
specifications.
JTG_TCK
JTG_TDI
JTG_TDO
JTG_TMS
JTG_TRST
LP_ACK
Input
Input
Output
Input
Input
InOut
JTAG Clock. JTAG test access port clock.
JTAG Serial Data In. JTAG test access port data input.
JTAG Serial Data Out. JTAG test access port data output.
JTAG Mode Select. JTAG test access port mode select.
JTAG Reset. JTAG test access port reset.
Acknowledge. Provides handshaking. When the link port is configured as a receiver, ACK is an output.
When the link port is configured as a transmitter, ACK is an input.
LP_CLK
InOut
Clock. When the link port is configured as a receiver, CLK is an input. When the link port is configured
as a transmitter, CLK is an output.
LP_D[n]
InOut
Input
Input
Output
Data n Data bus. Input when receiving, output when transmitting.
Single Ended Clock.
MLB_CLK
MLB_CLKN
MLB_CLKOUT
Differential Clock (–).
Single Ended Clock Out.
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Table 9. ADSP-2159x/ADSP-SC59x Detailed Signal Descriptions (Continued)
Signal Name
MLB_CLKP
MLB_DAT
MLB_DATN
MLB_DATP
MLB_SIG
Direction Description
Differential Clock (+).
Input
InOut
InOut
InOut
InOut
InOut
InOut
Output
InOut
InOut
InOut
InOut
InOut
InOut
Input
InOut
Single Ended Data.
Differential Data (–).
Differential Data (+).
Single Ended Signal.
MLB_SIGN
MLB_SIGP
OSPI_CLK
OSPI_D2
Differential Signal (–).
Differential Signal (+).
Clock Output. SPI clock output.
Data 2. Transfers serial data in quad and octal mode.
Data 3. Transfers serial data in quad and octal mode.
Data 4. Transfers serial data in octal mode.
Data 5. Transfers serial data in octal mode.
Data 6. Transfers serial data in octal mode.
Data 7. Transfers serial data in octal mode.
Data Strobe. Data strobe input from an external flash device.
OSPI_D3
OSPI_D4
OSPI_D5
OSPI_D6
OSPI_D7
OSPI_DQS
OSPI_MISO
Master In, Slave Out. Transfers serial data. Operates in the same direction as SPI_MOSI in dual, quad,
and octal modes.
OSPI_MOSI
InOut
Master Out, Slave Input. Transfers serial data. Operates in the same direction as SPI_MISO in dual,
quad, and octal modes.
OSPI_SEL[n]
PPI_CLK
Output
InOut
InOut
InOut
Slave Select Output n. Used in master mode to enable the desired slave.
Clock. Input in external clock mode, output in internal clock mode.
Data n. Bidirectional data bus.
PPI_D[nn]
PPI_FS1
Frame Sync 1 (HSYNC). Behavior depends on EPPI mode. See the EPPI chapter of the ADSP-
2159x/ADSP-SC591/592/594 SHARC+ Processor Hardware Reference for more details.
PPI_FS2
PPI_FS3
P_[nn]
InOut
InOut
InOut
Frame Sync 2 (VSYNC). Behavior depends on EPPI mode. See the EPPI chapter of the ADSP-
2159x/ADSP-SC591/592/594 SHARC+ Processor Hardware Reference for more details.
Frame Sync 3 (FIELD). Behavior depends on EPPI mode. See the EPPI chapter of the ADSP-
2159x/ADSP-SC591/592/594 SHARC+ Processor Hardware Reference for more details.
Position n. General-purpose input/output. See the GP Ports chapter of the ADSP-2159x/ADSP-
SC591/592/594 SHARC+ Processor Hardware Reference for more details.
SPI_CLK
SPI_D2
InOut
InOut
InOut
InOut
Clock. Input in slave mode, output in master mode.
Data 2. Transfers serial data in quad mode. Open-drain when ODM mode is enabled.
Data 3. Transfers serial data in quad mode. Open-drain when ODM mode is enabled.
SPI_D3
SPI_MISO
Master In, Slave Out. Transfers serial data. Operates in the same direction as SPI_MOSI in dual and
quad modes. Open-drain when ODM mode is enabled.
SPI_MOSI
InOut
Master Out, Slave In. Transfers serial data. Operates in the same direction as SPI_MISO in dual and
quad modes. Open-drain when ODM mode is enabled.
SPI_RDY
SPI_SEL[n]
SPI_SS
InOut
Output
Input
Ready. Optional flow signal. Output in slave mode, input in master mode.
Slave Select Output n. Used in master mode to enable the desired slave.
Slave Select Input.
Slave mode—acts as the slave select input.
Master mode—optionally serves as an error detection input for the SPI when there are multiple
masters.
SPT_ACLK
SPT_AD0
SPT_AD1
InOut
InOut
InOut
Channel A Clock. Data and frame sync are driven or sampled with respect to this clock. This signal
can be either internally or externally generated.
Channel A Data 0. Primary bidirectional data I/O. This signal can be configured as an output to
transmit serial data or as an input to receive serial data.
Channel A Data 1. Secondary bidirectional data I/O. This signal can be configured as an output to
transmit serial data or as an input to receive serial data.
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Table 9. ADSP-2159x/ADSP-SC59x Detailed Signal Descriptions (Continued)
Signal Name
Direction Description
SPT_AFS
InOut
Output
InOut
InOut
InOut
InOut
Output
Channel A Frame Sync. The frame sync pulse initiates shifting of serial data. This signal is either
generated internally or externally.
SPT_ATDV
SPT_BCLK
SPT_BD0
SPT_BD1
SPT_BFS
Channel A Transmit Data Valid. This signal is optional and only active when SPORT is configured in
multichannel transmit mode. It is asserted during enabled slots.
Channel B Clock. Data and frame sync are driven or sampled with respect to this clock. This signal
can be either internally or externally generated.
Channel B Data 0. Primary bidirectional data I/O. This signal can be configured as an output to
transmit serial data or as an input to receive serial data.
Channel B Data 1. Secondary bidirectional data I/O. This signal can be configured as an output to
transmit serial data or as an input to receive serial data.
Channel B Frame Sync. The frame sync pulse initiates shifting of serial data. This signal is either
generated internally or externally.
SPT_BTDV
Channel B Transmit Data Valid. This signal is optional and only active when SPORT is configured in
multichannel transmit mode. It is asserted during enabled slots.
SYS_BMODE[n]
SYS_CLKIN0
SYS_CLKIN1
SYS_CLKOUT
Input
Input
Input
Output
Boot Mode Control n. Selects the boot mode of the processor.
Clock/Crystal Input.
Clock/Crystal Input.
Processor Clock Output. Outputs internal clocks. Clocks may be divided down. See the CGU chapter
of the ADSP-2159x/ADSP-SC591/592/594 SHARC+ Processor Hardware Reference for more details.
SYS_FAULT
SYS_FAULT
InOut
InOut
Active-High Fault Output. Indicates internal faults or senses external faults depending on the
operating mode.
Active-Low Fault Output. Indicates internal faults or senses external faults depending on the
operating mode.
SYS_HWRST
SYS_RESOUT
SYS_XTAL0
SYS_XTAL1
TM_ACI[n]
TM_ACLK[n]
TM_CLK
Input
Processor Hardware Reset Control. Resets the device when asserted.
Reset Output. Indicates the device is in the reset state.
Crystal Output.
Output
Output
Output
Input
Crystal Output.
Alternate Capture Input n. Provides an additional input for WIDCAP, WATCHDOG, and PININT modes.
Alternate Clock n. Provides an additional time base for an individual timer.
Clock. Provides an additional global time base for all GP timers.
Timer n. The main input/output signal for each timer.
Trace Clock. Clock output.
Input
Input
TM_TMR[n]
TRACE_CLK
TRACE_D[nn]
TWI_SCL
InOut
Output
Output
InOut
InOut
Input
Trace Data n. Unidirectional data bus.
Serial Clock. Clock output when controller, clock input when target.
Serial Data. Receives or transmits data.
TWI_SDA
UART_CTS
UART_RTS
UART_RX
Clear to Send. Flow control signal.
Output
Input
Request to Send. Flow control signal.
Receive. Receives input. Typically connects to a transceiver that meets the electrical requirements of
the device being communicated with.
UART_TX
Output
Transmit. Transmits output. Typically connects to a transceiver that meets the electrical requirements
of the device being communicated with.
USBC_CLK
Input
InOut
Input
Input
Output
USBC Clock.
USBC_DATA[n]
USBC_DIR
USBC Data.
USBC Data Bus Control. Controls the direction of data bus.
USBC Next Data Control.
USBC Stop Output Control.
USBC_NXT
USBC_STOP
Rev. PrD
|
Page 29 of 143
|
May 2021
ADSP-21591/21593/21594/ADSP-SC591/SC592/SC594 Preliminary Technical Data
400-BALL HIGH PERIPHERAL COUNT (HPC) BGA SIGNAL DESCRIPTIONS
The processor pin definitions are shown in Table 10 for the 400-
ball HPC BGA package. The columns in this table provide the
following information:
• The pin name column identifies the name of the package
pin (at power on reset) on which the signal is located (if a
single function pin) or is multiplexed (if a GPIO pin).
• The signal name column includes the signal name for every
pin and the GPIO multiplexed pin function, where
applicable.
• The DAI pins and their associated signal routing units
(SRUs) connect inputs and outputs of the DAI peripherals
(SPORT, ASRC, S/PDIF, and PCG). See the Digital Audio
Interface (DAI) chapter of the ADSP-2159x/ADSP-
SC591/592/594 SHARC+ Processor Hardware Reference
for complete information on the use of the DAI and SRUs.
• The description column provides a descriptive name for
each signal.
• The port column shows whether or not a signal is
multiplexed with other signals on a GPIO port pin.
Table 10. ADSP-SC59x 400-Ball HPC BGA Signal Descriptions
Signal Name
C1_FLG00
C1_FLG01
C1_FLG02
C1_FLG03
C1_FLG04
C1_FLG05
C1_FLG06
C1_FLG07
C1_FLG08
C1_FLG09
C1_FLG10
C1_FLG11
C1_FLG12
C1_FLG13
C1_FLG14
C1_FLG15
C2_FLG00
C2_FLG01
C2_FLG02
C2_FLG03
C2_FLG04
C2_FLG05
C2_FLG06
C2_FLG07
C2_FLG08
C2_FLG09
C2_FLG10
C2_FLG11
C2_FLG12
C2_FLG13
C2_FLG14
C2_FLG15
CANFD0_RX
CANFD0_TX
CANFD1_RX
CANFD1_TX
Description
Port
A
H
B
B
I
Pin Name
PA_12
PH_02
PB_03
PB_02
PI_03
SHARC+ Core 1 FLAGS I/O 0
SHARC+ Core 1 FLAGS I/O 1
SHARC+ Core 1 FLAGS I/O 2
SHARC+ Core 1 FLAGS I/O 3
SHARC+ Core 1 FLAGS I/O 4
SHARC+ Core 1 FLAGS I/O 5
SHARC+ Core 1 FLAGS I/O 6
SHARC+ Core 1 FLAGS I/O 7
SHARC+ Core 1 FLAGS I/O 8
SHARC+ Core 1 FLAGS I/O 9
SHARC+ Core 1 FLAGS I/O 10
SHARC+ Core 1 FLAGS I/O 11
SHARC+ Core 1 FLAGS I/O 12
SHARC+ Core 1 FLAGS I/O 13
SHARC+ Core 1 FLAGS I/O 14
SHARC+ Core 1 FLAGS I/O 15
SHARC+ Core 2 FLAGS I/O 0
SHARC+ Core 2 FLAGS I/O 1
SHARC+ Core 2 FLAGS I/O 2
SHARC+ Core 2 FLAGS I/O 3
SHARC+ Core 2 FLAGS I/O 4
SHARC+ Core 2 FLAGS I/O 5
SHARC+ Core 2 FLAGS I/O 6
SHARC+ Core 2 FLAGS I/O 7
SHARC+ Core 2 FLAGS I/O 8
SHARC+ Core 2 FLAGS I/O 9
SHARC+ Core 2 FLAGS I/O 10
SHARC+ Core 2 FLAGS I/O 11
SHARC+ Core 2 FLAGS I/O 12
SHARC+ Core 2 FLAGS I/O 13
SHARC+ Core 2 FLAGS I/O 14
SHARC+ Core 2 FLAGS I/O 15
CANFD0 Receive
I
PI_04
F
PF_02
PF_01
PE_12
PF_09
PF_03
PD_03
PF_13
PF_12
PG_09
PI_05
F
E
F
F
D
F
F
G
I
I
PI_01
I
PI_02
F
PF_06
PF_07
PF_10
PF_11
PG_13
PE_11
PF_08
PD_14
PD_02
PG_12
PF_14
PE_13
PG_10
PG_11
PF_15
PG_00
PG_01
PG_02
F
F
F
G
E
F
D
D
G
F
E
G
G
F
CANFD0 Transmit
G
G
G
CANFD1 Receive
CANFD1 Transmit
Rev. PrD
|
Page 30 of 143
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May 2021
Preliminary Technical Data ADSP-21591/21593/21594/ADSP-SC591/SC592/SC594
Table 10. ADSP-SC59x 400-Ball HPC BGA Signal Descriptions (Continued)
Signal Name
CNT0_DG
Description
CNT0 Count Down and Gate
CNT0 Count Up and Direction
CNT0 Count Zero Marker
DAI0 Pin 1
Port
Pin Name
B
PB_05
CNT0_UD
B
PB_03
CNT0_ZM
B
PB_04
DAI0_PIN01
DAI0_PIN02
DAI0_PIN03
DAI0_PIN04
DAI0_PIN05
DAI0_PIN06
DAI0_PIN07
DAI0_PIN08
DAI0_PIN09
DAI0_PIN10
DAI0_PIN11
DAI0_PIN12
DAI0_PIN13
DAI0_PIN14
DAI0_PIN15
DAI0_PIN16
DAI0_PIN17
DAI0_PIN18
DAI0_PIN19
DAI0_PIN20
DAI1_PIN01
DAI1_PIN02
DAI1_PIN03
DAI1_PIN04
DAI1_PIN05
DAI1_PIN06
DAI1_PIN07
DAI1_PIN08
DAI1_PIN09
DAI1_PIN10
DAI1_PIN11
DAI1_PIN12
DAI1_PIN13
DAI1_PIN14
DAI1_PIN15
DAI1_PIN16
DAI1_PIN17
DAI1_PIN18
DAI1_PIN19
DAI1_PIN20
DMC0_A00
DMC0_A01
DMC0_A02
DMC0_A03
DMC0_A04
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
DAI0_PIN01
DAI0_PIN02
DAI0_PIN03
DAI0_PIN04
DAI0_PIN05
DAI0_PIN06
DAI0_PIN07
DAI0_PIN08
DAI0_PIN09
DAI0_PIN10
DAI0_PIN11
DAI0_PIN12
DAI0_PIN13
DAI0_PIN14
DAI0_PIN15
DAI0_PIN16
DAI0_PIN17
DAI0_PIN18
DAI0_PIN19
DAI0_PIN20
DAI1_PIN01
DAI1_PIN02
DAI1_PIN03
DAI1_PIN04
DAI1_PIN05
DAI1_PIN06
DAI1_PIN07
DAI1_PIN08
DAI1_PIN09
DAI1_PIN10
DAI1_PIN11
DAI1_PIN12
DAI1_PIN13
DAI1_PIN14
DAI1_PIN15
DAI1_PIN16
DAI1_PIN17
DAI1_PIN18
DAI1_PIN19
DAI1_PIN20
DMC0_A00
DMC0_A01
DMC0_A02
DMC0_A03
DMC0_A04
DAI0 Pin 2
DAI0 Pin 3
DAI0 Pin 4
DAI0 Pin 5
DAI0 Pin 6
DAI0 Pin 7
DAI0 Pin 8
DAI0 Pin 9
DAI0 Pin 10
DAI0 Pin 11
DAI0 Pin 12
DAI0 Pin 13
DAI0 Pin 14
DAI0 Pin 15
DAI0 Pin 16
DAI0 Pin 17
DAI0 Pin 18
DAI0 Pin 19
DAI0 Pin 20
DAI1 Pin 1
DAI1 Pin 2
DAI1 Pin 3
DAI1 Pin 4
DAI1 Pin 5
DAI1 Pin 6
DAI1 Pin 7
DAI1 Pin 8
DAI1 Pin 9
DAI1 Pin 10
DAI1 Pin 11
DAI1 Pin 12
DAI1 Pin 13
DAI1 Pin 14
DAI1 Pin 15
DAI1 Pin 16
DAI1 Pin 17
DAI1 Pin 18
DAI1 Pin 19
DAI1 Pin 20
DMC0 Address 0
DMC0 Address 1
DMC0 Address 2
DMC0 Address 3
DMC0 Address 4
Rev. PrD
|
Page 31 of 143
|
May 2021
ADSP-21591/21593/21594/ADSP-SC591/SC592/SC594 Preliminary Technical Data
Table 10. ADSP-SC59x 400-Ball HPC BGA Signal Descriptions (Continued)
Signal Name
DMC0_A05
DMC0_A06
DMC0_A07
DMC0_A08
DMC0_A09
DMC0_A10
DMC0_A11
DMC0_A12
DMC0_A13
DMC0_A14
DMC0_A15
DMC0_BA0
DMC0_BA1
DMC0_BA2
DMC0_CAS
DMC0_CK
Description
Port
Pin Name
DMC0 Address 5
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
D
DMC0_A05
DMC0_A06
DMC0_A07
DMC0_A08
DMC0_A09
DMC0_A10
DMC0_A11
DMC0_A12
DMC0_A13
DMC0_A14
DMC0_A15
DMC0_BA0
DMC0_BA1
DMC0_BA2
DMC0_CAS
DMC0_CK
DMC0 Address 6
DMC0 Address 7
DMC0 Address 8
DMC0 Address 9
DMC0 Address 10
DMC0 Address 11
DMC0 Address 12
DMC0 Address 13
DMC0 Address 14
DMC0 Address 15
DMC0 Bank Address Input 0
DMC0 Bank Address Input 1
DMC0 Bank Address Input 2
DMC0 Column Address Strobe
DMC0 Clock
DMC0_CK
DMC0 Clock (Complement)
DMC0 Clock Enable
DMC0 Chip Select 0
DMC0 Data 0
DMC0_CK
DMC0_CKE
DMC0_CS0
DMC0_DQ00
DMC0_DQ01
DMC0_DQ02
DMC0_DQ03
DMC0_DQ04
DMC0_DQ05
DMC0_DQ06
DMC0_DQ07
DMC0_DQ08
DMC0_DQ09
DMC0_DQ10
DMC0_DQ11
DMC0_DQ12
DMC0_DQ13
DMC0_DQ14
DMC0_DQ15
DMC0_LDM
DMC0_LDQS
DMC0_LDQS
DMC0_ODT
DMC0_RAS
DMC0_RESET
DMC0_RZQ
DMC0_UDM
DMC0_UDQS
DMC0_UDQS
DMC0_VREF0
DMC0_WE
DMC0_CKE
DMC0_CS0
DMC0_DQ00
DMC0_DQ01
DMC0_DQ02
DMC0_DQ03
DMC0_DQ04
DMC0_DQ05
DMC0_DQ06
DMC0_DQ07
DMC0_DQ08
DMC0_DQ09
DMC0_DQ10
DMC0_DQ11
DMC0_DQ12
DMC0_DQ13
DMC0_DQ14
DMC0_DQ15
DMC0_LDM
DMC0_LDQS
DMC0_LDQS
DMC0_ODT
DMC0_RAS
DMC0_RESET
DMC0_RZQ
DMC0_UDM
DMC0_UDQS
DMC0_UDQS
DMC0_VREF0
DMC0_WE
DMC0 Data 1
DMC0 Data 2
DMC0 Data 3
DMC0 Data 4
DMC0 Data 5
DMC0 Data 6
DMC0 Data 7
DMC0 Data 8
DMC0 Data 9
DMC0 Data 10
DMC0 Data 11
DMC0 Data 12
DMC0 Data 13
DMC0 Data 14
DMC0 Data 15
DMC0 Data Mask for Lower Byte
DMC0 Data Strobe for Lower Byte
DMC0 Data Strobe for Lower Byte (Complement)
DMC0 On-Die Termination
DMC0 Row Address Strobe
DMC0 Reset
DMC0 External Calibration Resistor Connection
DMC0 Data Mask for Upper Byte
DMC0 Data Strobe for Upper Byte
DMC0 Data Strobe for Upper Byte (Complement)
DMC0 Voltage Reference
DMC0 Write Enable
EMAC0 MII Collision Detect
ETH0_COL
PD_07
Rev. PrD
|
Page 32 of 143
|
May 2021
Preliminary Technical Data ADSP-21591/21593/21594/ADSP-SC591/SC592/SC594
Table 10. ADSP-SC59x 400-Ball HPC BGA Signal Descriptions (Continued)
Signal Name
ETH0_CRS
Description
Port
Pin Name
PD_02
EMAC0 MII Carrier Sense
D
ETH0_MDC
EMAC0 Serial Management Clock
EMAC0 Serial Management Bidirectional Data
EMAC0 PTP Auxiliary Trigger Input 0
EMAC0 PTP Auxiliary Trigger Input 1
EMAC0 PTP Auxiliary Trigger Input 2
EMAC0 PTP Auxiliary Trigger Input 3
EMAC0 PTP Clock Input 0
H
PH_03
ETH0_MDIO
H
PH_04
ETH0_PTPAUXIN0
ETH0_PTPAUXIN1
ETH0_PTPAUXIN2
ETH0_PTPAUXIN3
ETH0_PTPCLKIN0
ETH0_PTPPPS0
ETH0_PTPPPS1
ETH0_PTPPPS2
ETH0_PTPPPS3
ETH0_RXCLK_REFCLK
ETH0_RXCTL_CRSRX_DV
ETH0_RXD0
I
PI_02
D
PD_05
D
PD_03
E
PE_09
I
PI_01
EMAC0 Pulse Per Second Output 0
EMAC0 Pulse Per Second Output 1
EMAC0 Pulse Per Second Output 2
EMAC0 Pulse Per Second Output 3
EMAC0 RXCLK (10/100/1000) or REFCLK (10/100)
EMAC0 RXCTL (RGMII) or CRS_DV (GMII) or RX_DV (MII)
EMAC0 Receive Data 0
I
PI_04
I
PI_03
I
PI_05
I
PI_06
H
PH_07
H
PH_08
H
PH_05
ETH0_RXD1
EMAC0 Receive Data 1
H
PH_06
ETH0_RXD2
EMAC0 Receive Data 2
H
PH_11
ETH0_RXD3
EMAC0 Receive Data 3
H
PH_12
ETH0_RXERR
ETH0_TXCLK
ETH0_TXCTL_TXEN
ETH0_TXD0
EMAC0 Receive Error
D
PD_06
EMAC0 Transmit Clock
H
PH_14
EMAC0 TXCTL (10/100/1000) or TXEN (10/100)
EMAC0 Transmit Data 0
H
PH_13
H
PH_09
ETH0_TXD1
EMAC0 Transmit Data 1
H
PH_10
ETH0_TXD2
EMAC0 Transmit Data 2
H
PH_15
ETH0_TXD3
EMAC0 Transmit Data 3
I
PI_00
ETH1_CRS
EMAC1 Carrier Sense
F
PF_03
ETH1_MDC
EMAC1 Serial Management Clock
EMAC1 Serial Management Bidirectional Data
EMAC1 Reference Clock
F
PF_02
ETH1_MDIO
F
PF_01
ETH1_REFCLK
ETH1_RXD0
E
PE_11
EMAC1 Receive Data 0
E
PE_15
ETH1_RXD1
EMAC1 Receive Data 1
F
PF_00
ETH1_TXD0
EMAC1 Transmit Data 0
E
PE_13
ETH1_TXD1
EMAC1 Transmit Data 1
E
PE_14
ETH1_TXEN
EMAC1 Transmit Enable
E
PE_12
HADC0_EOC_DOUT
HADC0_MUX0
HADC0_MUX1
HADC0_MUX2
HADC0_VIN0
HADC0_VIN1
HADC0_VIN2
HADC0_VIN3
HADC0_VIN4
HADC0_VIN5
HADC0_VIN6
HADC0_VIN7
HADC0_VREFN
HADC0_VREFP
HADC0 End of Conversion
A
PA_11
HADC0 MUX0
E
PE_02
HADC0 MUX1
E
PE_04
HADC0 MUX2
E
PE_03
HADC0 Analog Input at Channel 0
HADC0 Analog Input at Channel 1
HADC0 Analog Input at Channel 2
HADC0 Analog Input at Channel 3
HADC0 Analog Input at Channel 4
HADC0 Analog Input at Channel 5
HADC0 Analog Input at Channel 6
HADC0 Analog Input at Channel 7
HADC0 Ground Reference for ADC
HADC0 External Reference for ADC
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
HADC0_VIN0
HADC0_VIN1
HADC0_VIN2
HADC0_VIN3
HADC0_VIN4
HADC0_VIN5
HADC0_VIN6
HADC0_VIN7
HADC0_VREFN
HADC0_VREFP
Rev. PrD
|
Page 33 of 143
|
May 2021
ADSP-21591/21593/21594/ADSP-SC591/SC592/SC594 Preliminary Technical Data
Table 10. ADSP-SC59x 400-Ball HPC BGA Signal Descriptions (Continued)
Signal Name
JTG_TCK
Description
Port
Pin Name
JTG_TCK
JTG_TDI
JTG_TDO
JTG_TMS
JTG_TRST
PB_04
JTAG Clock
Not Muxed
JTG_TDI
JTAG Serial Data In
JTAG Serial Data Out
JTAG Mode Select
JTAG Reset
Not Muxed
JTG_TDO
JTG_TMS
JTG_TRST
LP0_ACK
LP0_CLK
Not Muxed
Not Muxed
Not Muxed
LP0 Acknowledge
LP0 Clock
B
B
PB_06
LP0_D0
LP0 Data 0
B
PB_07
LP0_D1
LP0 Data 1
B
PB_08
LP0_D2
LP0 Data 2
B
PB_09
LP0_D3
LP0 Data 3
B
PB_10
LP0_D4
LP0 Data 4
B
PB_11
LP0_D5
LP0 Data 5
B
PB_12
LP0_D6
LP0 Data 6
B
PB_13
LP0_D7
LP0 Data 7
B
PB_14
LP1_ACK
LP1_CLK
LP1 Acknowledge
LP1 Clock
B
PB_02
C
PC_07
LP1_D0
LP1 Data 0
B
PB_15
LP1_D1
LP1 Data 1
C
PC_00
LP1_D2
LP1 Data 2
C
PC_01
LP1_D3
LP1 Data 3
C
PC_02
LP1_D4
LP1 Data 4
C
PC_03
LP1_D5
LP1 Data 5
C
PC_04
LP1_D6
LP1 Data 6
C
PC_05
LP1_D7
LP1 Data 7
C
PC_06
MLB0_CLK
MLB0_CLKN
MLB0_CLKOUT
MLB0_CLKP
MLB0_DAT
MLB0_DATN
MLB0_DATP
MLB0_SIG
MLB0_SIGN
MLB0_SIGP
OSPI0_CLK
OSPI0_D2
OSPI0_D3
OSPI0_D4
OSPI0_D5
OSPI0_D6
OSPI0_D7
OSPI0_DQS
OSPI0_MISO
OSPI0_MOSI
OSPI0_SEL1
OSPI0_SEL2
OSPI0_SEL3
MLB0 Single-Ended Clock
MLB0 Differential Clock (–)
MLB0 Clock Single-Ended Clock Out
MLB0 Differential Clock (+)
MLB0 Single-Ended Data
MLB0 Differential Data (–)
MLB0 Differential Clock (+)
MLB0 Single-Ended Signal
MLB0 Differential Signal (–)
MLB0 Differential Signal (+)
OSPI0 Clock
B
PB_02
Not Muxed
MLB0_CLKN
PF_05
F
Not Muxed
MLB0_CLKP
PB_00
B
Not Muxed
MLB0_DATN
MLB0_DATP
PB_01
Not Muxed
B
Not Muxed
MLB0_SIGN
MLB0_SIGP
PC_08
Not Muxed
C
A
A
D
C
A
C
D
C
C
A
I
OSPI0 Data 2
PA_02
OSPI0 Data 3
PA_03
OSPI0 Data 4
PD_00
OSPI0 Data 5
PC_15
OSPI0 Data 6
PA_08
OSPI0 Data 7
PC_13
OSPI0 Data Strobe
OSPI0 Master In, Slave Out
OSPI0 Master Out, Slave In
OSPI0 Slave Select Output 1
OSPI0 Slave Select Output 2
OSPI0 Slave Select Output 3
PD_04
PC_12
PC_11
PA_05
PI_05
G
PG_12
Rev. PrD
|
Page 34 of 143
|
May 2021
Preliminary Technical Data ADSP-21591/21593/21594/ADSP-SC591/SC592/SC594
Table 10. ADSP-SC59x 400-Ball HPC BGA Signal Descriptions (Continued)
Signal Name
OSPI0_SEL4
PPI0_CLK
PPI0_D00
PPI0_D01
PPI0_D02
PPI0_D03
PPI0_D04
PPI0_D05
PPI0_D06
PPI0_D07
PPI0_D08
PPI0_D09
PPI0_D10
PPI0_D11
PPI0_D12
PPI0_D13
PPI0_D14
PPI0_D15
PPI0_D16
PPI0_D17
PPI0_D18
PPI0_D19
PPI0_D20
PPI0_D21
PPI0_D22
PPI0_D23
PPI0_FS1
PPI0_FS2
PPI0_FS3
SPI0_CLK
SPI0_MISO
SPI0_MOSI
SPI0_RDY
SPI0_SEL1
SPI0_SEL2
SPI0_SEL3
SPI0_SEL4
SPI0_SEL5
SPI0_SEL6
SPI0_SEL7
SPI0_SS
Description
Port
G
E
Pin Name
PG_13
PE_04
PE_05
PE_06
PE_07
PE_08
PE_09
PE_10
PD_01
PD_04
PD_05
PD_10
PD_11
PD_12
PD_13
PD_14
PD_15
PE_00
PC_08
PC_09
PC_10
PC_11
PC_12
PC_13
PC_14
PC_15
PE_01
PE_02
PE_03
PA_06
PA_07
PA_08
PB_11
PA_09
PB_05
PB_14
PB_15
PG_02
PE_15
PF_00
PA_09
PA_10
PA_14
PA_15
PA_11
PA_12
PC_06
PA_13
OSPI0 Slave Select Output 4
EPPI0 Clock
EPPI0 Data 0
E
EPPI0 Data 1
E
EPPI0 Data 2
E
EPPI0 Data 3
E
EPPI0 Data 4
E
EPPI0 Data 5
E
EPPI0 Data 6
D
D
D
D
D
D
D
D
D
E
EPPI0 Data 7
EPPI0 Data 8
EPPI0 Data 9
EPPI0 Data 10
EPPI0 Data 11
EPPI0 Data 12
EPPI0 Data 13
EPPI0 Data 14
EPPI0 Data 15
EPPI0 Data 16
C
C
C
C
C
C
C
C
E
EPPI0 Data 17
EPPI0 Data 18
EPPI0 Data 19
EPPI0 Data 20
EPPI0 Data 21
EPPI0 Data 22
EPPI0 Data 23
EPPI0 Frame Sync 1 (HSYNC)
EPPI0 Frame Sync 2 (VSYNC)
EPPI0 Frame Sync 3 (FIELD)
SPI0 Clock
E
E
A
A
A
B
SPI0 Mater In, Slave Out
SPI0 Master Out, Slave In
SPI0 Ready
SPI0 Slave Select Output 1
SPI0 Slave Select Output 2
SPI0 Slave Select Output 3
SPI0 Slave Select Output 4
SPI0 Slave Select Output 5
SPI0 Slave Select Output 6
SPI0 Slave Select Output 7
SPI0 Slave Select Input
SPI1 Clock
A
B
B
B
G
E
F
A
A
A
A
A
A
C
A
SPI1_CLK
SPI1_D2
SPI1 Data 2
SPI1_D3
SPI1 Data 3
SPI1_MISO
SPI1_MOSI
SPI1_RDY
SPI1_SEL1
SPI1 Master In, Slave Out
SPI1 Master Out, Slave In
SPI1 Ready
SPI1 Slave Select Output 1
Rev. PrD
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ADSP-21591/21593/21594/ADSP-SC591/SC592/SC594 Preliminary Technical Data
Table 10. ADSP-SC59x 400-Ball HPC BGA Signal Descriptions (Continued)
Signal Name
SPI1_SEL2
SPI1_SEL3
SPI1_SEL4
SPI1_SEL5
SPI1_SEL6
SPI1_SEL7
SPI1_SS
Description
Port
Pin Name
PB_10
SPI1 Slave Select Output 2
SPI1 Slave Select Output 3
SPI1 Slave Select Output 4
SPI1 Slave Select Output 5
SPI1 Slave Select Output 6
SPI1 Slave Select Output 7
SPI1 Slave Select Input
SPI2 Clock
B
B
PB_13
E
PE_02
B
PB_06
G
PG_09
B
PB_08
A
PA_13
SPI2_CLK
A
PA_04
SPI2_D2
SPI2 Data 2
A
PA_02
SPI2_D3
SPI2 Data 3
A
PA_03
SPI2_MISO
SPI2_MOSI
SPI2_RDY
SPI2 Master In, Slave Out
SPI2 Master Out, Slave In
SPI2 Ready
A
PA_00
A
PA_01
B
PB_05
SPI2_SEL1
SPI2_SEL2
SPI2_SEL3
SPI2_SEL4
SPI2_SEL5
SPI2_SEL6
SPI2_SEL7
SPI2_SS
SPI2 Slave Select Output 1
SPI2 Slave Select Output 2
SPI2 Slave Select Output 3
SPI2 Slave Select Output 4
SPI2 Slave Select Output 5
SPI2 Slave Select Output 6
SPI2 Slave Select Output 7
SPI2 Slave Select Input
SPI3 Clock
A
PA_05
H
PH_02
B
PB_12
G
PG_12
B
PB_07
G
PG_01
E
PE_14
A
PA_05
SPI3_CLK
G
PG_05
SPI3_MISO
SPI3_MOSI
SPI3_RDY
SPI3 Master In, Slave Out
SPI3 Master Out, Slave In
SPI3 Ready
G
PG_06
G
PG_07
F
PF_00
SPI3_SEL1
SPI3_SEL2
SPI3_SEL3
SPI3_SEL4
SPI3_SEL5
SPI3_SEL6
SPI3_SEL7
SPI3_SS
SPI3 Slave Select Output 1
SPI3 Slave Select Output 2
SPI3 Slave Select Output 3
SPI3 Slave Select Output 4
SPI3 Slave Select Output 5
SPI3 Slave Select Output 6
SPI3 Slave Select Output 7
SPI3 Slave Select Input
Boot Mode Control Pin 0
Boot Mode Control Pin 1
Boot Mode Control Pin 2
Clock/Crystal Input 0
G
PG_08
F
PF_07
E
PE_00
E
PE_01
G
PG_15
F
PF_08
H
PH_00
G
PG_08
SYS_BMODE0
SYS_BMODE1
SYS_BMODE2
SYS_CLKIN0
SYS_CLKIN1
SYS_CLKOUT
SYS_FAULT
SYS_HWRST
SYS_RESOUT
SYS_XTAL0
SYS_XTAL1
TM0_ACI00
TM0_ACI01
TM0_ACI02
TM0_ACI03
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
D
SYS_BMODE0
SYS_BMODE1
SYS_BMODE2
SYS_CLKIN0
SYS_CLKIN1
SYS_CLKOUT
SYS_FAULT
SYS_HWRST
SYS_RESOUT
SYS_XTAL0
SYS_XTAL1
PD_08
Clock/Crystal Input 1
Processor Clock Output
Active-Low Fault Output
Processor Hardware Reset Control
Reset Output
Crystal Output 0
Crystal Output 1
TIMER0 Alternate Capture Input 0
TIMER0 Alternate Capture Input 1
TIMER0 Alternate Capture Input 2
TIMER0 Alternate Capture Input 3
D
PD_04
B
PB_11
B
PB_00
Rev. PrD
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Preliminary Technical Data ADSP-21591/21593/21594/ADSP-SC591/SC592/SC594
Table 10. ADSP-SC59x 400-Ball HPC BGA Signal Descriptions (Continued)
Signal Name
TM0_ACI04
Description
Port
A
G
G
H
H
A
A
G
B
Pin Name
PA_11
PG_14
PG_01
PH_00
PH_01
PA_06
PA_08
PG_10
PB_02
PG_00
PG_05
PG_07
PF_04
PI_06
TIMER0 Alternate Capture Input 4
TIMER0 Alternate Capture Input 10
TIMER0 Alternate Capture Input 11
TIMER0 Alternate Capture Input 12
TIMER0 Alternate Capture Input 13
TIMER0 Alternate Clock 1
TIMER0 Alternate Clock 2
TIMER0 Alternate Clock 3
TIMER0 Alternate Clock 4
TIMER0 Alternate Clock 10
TIMER0 Alternate Clock 11
TIMER0 Alternate Clock 12
TIMER0 Alternate Clock 13
TIMER0 Alternate Clock 14
TIMER0 Alternate Clock 15
TIMER0 Clock
TM0_ACI10
TM0_ACI11
TM0_ACI12
TM0_ACI13
TM0_ACLK01
TM0_ACLK02
TM0_ACLK03
TM0_ACLK04
TM0_ACLK10
TM0_ACLK11
TM0_ACLK12
TM0_ACLK13
TM0_ACLK14
TM0_ACLK15
TM0_CLK
G
G
G
F
I
E
PE_01
PF_05
PA_10
PA_12
PE_10
PB_03
PB_04
PB_05
PB_08
PB_09
PC_05
PC_07
PG_14
PG_15
PH_00
PH_01
PH_02
PD_15
PB_06
PB_07
PB_08
PB_09
PB_10
PC_00
PC_01
PC_02
PC_03
PH_03
PH_04
PH_05
PH_06
PH_07
PH_08
PH_09
F
TM0_TMR00
TM0_TMR01
TM0_TMR02
TM0_TMR03
TM0_TMR04
TM0_TMR05
TM0_TMR06
TM0_TMR07
TM0_TMR08
TM0_TMR09
TM0_TMR10
TM0_TMR11
TM0_TMR12
TM0_TMR13
TM0_TMR14
TM0_TMR15
TRACE0_CLK
TRACE0_D00
TRACE0_D01
TRACE0_D02
TRACE0_D03
TRACE0_D04
TRACE0_D05
TRACE0_D06
TRACE0_D07
TRACE0_D08
TRACE0_D09
TRACE0_D10
TRACE0_D11
TRACE0_D12
TRACE0_D13
TRACE0_D14
TIMER0 Timer 0
A
A
E
TIMER0 Timer 1
TIMER0 Timer 2
TIMER0 Timer 3
B
TIMER0 Timer 4
B
TIMER0 Timer 5
B
TIMER0 Timer 6
B
TIMER0 Timer 7
B
TIMER0 Timer 8
C
C
G
G
H
H
H
D
B
TIMER0 Timer 9
TIMER0 Timer 10
TIMER0 Timer 11
TIMER0 Timer 12
TIMER0 Timer 13
TIMER0 Timer 14
TIMER0 Timer 15
TRACE0 Trace Clock
TRACE0 Trace Data 0
TRACE0 Trace Data 1
TRACE0 Trace Data 2
TRACE0 Trace Data 3
TRACE0 Trace Data 4
TRACE0 Trace Data 5
TRACE0 Trace Data 6
TRACE0 Trace Data 7
TRACE0 Trace Data 8
TRACE0 Trace Data 9
TRACE0 Trace Data 10
TRACE0 Trace Data 11
TRACE0 Trace Data 12
TRACE0 Trace Data 13
TRACE0 Trace Data 14
B
B
B
B
C
C
C
C
H
H
H
H
H
H
H
Rev. PrD
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Page 37 of 143
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May 2021
ADSP-21591/21593/21594/ADSP-SC591/SC592/SC594 Preliminary Technical Data
Table 10. ADSP-SC59x 400-Ball HPC BGA Signal Descriptions (Continued)
Signal Name
TRACE0_D15
TWI0_SCL
Description
Port
H
E
Pin Name
PH_10
PE_02
PE_03
PB_00
PB_01
PE_04
PE_05
PA_02
PI_02
TRACE0 Trace Data 15
TWI0 Serial Clock
TWI0 Serial Data
TWI1 Serial Clock
TWI1 Serial Data
TWI2 Serial Clock
TWI2 Serial Data
TWI3 Serial Clock
TWI3 Serial Data
TWI4 Serial Clock
TWI4 Serial Data
TWI5 Serial Clock
TWI5 Serial Data
UART0 Clear to Send
UART0 Request to Send
UART0 Receive
TWI0_SDA
E
TWI1_SCL
B
B
E
TWI1_SDA
TWI2_SCL
TWI2_SDA
E
TWI3_SCL
A
I
TWI3_SDA
TWI4_SCL
D
C
C
E
PD_14
PC_01
PC_02
PE_01
PD_06
PD_07
PA_07
PD_09
PD_03
PB_00
PD_04
PD_05
PB_14
PD_12
PD_10
PD_11
PG_10
PG_09
PG_04
PG_03
PF_14
PF_13
PF_12
PF_11
PF_10
PF_07
PF_06
PF_05
PF_04
PF_09
PF_08
PF_03
TWI4_SDA
TWI5_SCL
TWI5_SDA
UART0_CTS
UART0_RTS
UART0_RX
D
D
A
D
D
B
D
D
B
D
D
D
G
G
G
G
F
UART0_TX
UART0 Transmit
UART1_CTS
UART1_RTS
UART1_RX
UART1 Clear to Send
UART1 Request to Send
UART1 Receive
UART1_TX
UART1 Transmit
UART2_CTS
UART2_RTS
UART2_RX
UART2 Clear to Send
UART2 Request to Send
UART2 Receive
UART2_TX
UART2 Transmit
UART3_CTS
UART3_RTS
UART3_RX
UART3 Clear to Send
UART3 Request to Send
UART3 Receive
UART3_TX
UART3 Transmit
USBC0_CLK
USBC0_DATA0
USBC0_DATA1
USBC0_DATA2
USBC0_DATA3
USBC0_DATA4
USBC0_DATA5
USBC0_DATA6
USBC0_DATA7
USBC0_DIR
USBC0_NXT
USBC0_STOP
USBC0 Clock Signal
USBC0 Data 0
F
USBC0 Data 1
F
USBC0 Data 2
F
USBC0 Data 3
F
USBC0 Data 4
F
USBC0 Data 5
F
USBC0 Data 6
F
USBC0 Data 7
F
USBC0 Data Direction Control
USBC0 Next Data Control
USBC0 Stop Output Control
F
F
F
Rev. PrD
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Page 38 of 143
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May 2021
Preliminary Technical Data ADSP-21591/21593/21594/ADSP-SC591/SC592/SC594
GPIO MULTIPLEXING FOR 400-BALL HIGH PERIPHERAL COUNT (HPC) BGA PACKAGE
Table 11 through Table 19 identify the pin functions that are
multiplexed on the GPIO pins of the 400-ball HPC BGA
package.
Table 11. ADSP-SC59x Signal Multiplexing for Port A
Multiplexed
Function 0
SPI2_MISO
SPI2_MOSI
SPI2_D2
Multiplexed
Function 1
Multiplexed
Function 2
Multiplexed
Function 3
Multiplexed
Function Input Tap
Signal Name
PA_00
PA_01
PA_02
PA_03
PA_04
PA_05
PA_06
PA_07
PA_08
PA_09
PA_10
PA_11
PA_12
PA_13
PA_14
PA_15
OSPI0_MISO1
OSPI0_MOSI1
OSPI0_D21
OSPI0_D31
OSPI0_CLK1
OSPI0_SEL12
UART0_TX1
UART0_RX1
UART0_RTS1
UART0_CTS1
SPI1_CLK
TWI3_SCL1
TWI3_SDA1
TM0_ACLK03
SPI2_D3
SPI2_CLK
SPI2_SEL1
SPI0_CLK
SPI0_MISO
SPI0_MOSI
SPI0_SEL1
T WI0_SCL1
T WI0_SDA1
C1_FLG00
C1_FLG01
T WI2_SCL1
T WI2_SDA1
SPI2_SS
OSPI0_D41
TM0_ACLK01
TM0_ACI00
TM0_ACLK02
SPI0_SS
OSPI0_D51
OSPI0_D61
OSPI0_D71
TM0_TMR00
HADC0_EOC_DOUT
TM0_TMR01
TM0_TMR02
UART1_RX1
UART1_TX1
SPI1_MISO
SPI1_MOSI
SPI1_SEL1
SPI1_D2
TM0_ACI04
SPI1_SS
TM0_ACI01
SPI1_D3
1 To ensure proper timing, for peripherals whose signals are available at multiple places in the pin mux, care must be taken to select all needed signals of the peripheral so that
their associated pins are as close as possible to each other.
2 These peripheral signals are available at multiple places in the pin mux. These signals can be selected from either of the two locations in pin mux, regardless of proximity to
other associated signals of the same peripheral.
Table 12. ADSP-SC59x Signal Multiplexing for Port B
Multiplexed
Function 0
Multiplexed
Function 1
Multiplexed
Function 2
UART1_RTS1
UART1_CTS1
LP1_ACK
SPI2_SEL22
LP0_ACK
Multiplexed
Function 3
Multiplexed
Function Input Tap
TM0_ACI03
TM0_CLK
Signal Name
PB_00
PB_01
PB_02
PB_03
PB_04
PB_05
PB_06
PB_07
PB_08
PB_09
PB_10
PB_11
PB_12
PB_13
PB_14
PB_15
MLB0_DAT
MLB0_SIG
MLB0_CLK
TM0_TMR03
TM0_TMR04
TM0_TMR05
LP0_CLK
LP0_D0
TWI1_SCL1
TWI1_SDA1
C1_FLG03
C1_FLG02
SPI1_RDY2
SPI2_RDY2
SPI1_SEL5
SPI2_SEL5
SPI1_SEL72
SPI2_SEL72
SPI1_SEL2
SPI0_RDY2
SPI2_SEL32
SPI1_SEL3
SPI0_SEL3
SPI0_SEL4
TM0_ACLK04
CNT0_UD
CNT0_ZM
CNT0_DG
SPI0_SEL2
TRACE0_CLK
TRACE0_D00
TRACE0_D01
TRACE0_D02
TRACE0_D03
UART2_RX1
UART2_TX1
LP0_D1
TM0_TMR06
TM0_TMR07
LP0_D2
LP0_D3
LP0_D4
TM0_ACI02
LP0_D5
LP0_D6
OSPI0_DQS1
UART2_RTS1
UART2_CTS1
LP0_D7
LP1_D0
1 To ensure proper timing, for peripherals whose signals are available at multiple places in the pin mux, care must be taken to select all needed signals of the peripheral so that
their associated pins are as close as possible to each other
2 These peripheral signals are available at multiple places in the pin mux. These signals can be selected from either of the two locations in pin mux, regardless of proximity to
other associated signals of the same peripheral.
Rev. PrD
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Page 39 of 143
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May 2021
ADSP-21591/21593/21594/ADSP-SC591/SC592/SC594 Preliminary Technical Data
Table 13. ADSP-SC59x Signal Multiplexing for Port C
Multiplexed
Function 0
LP1_D1
Multiplexed
Function 1
Multiplexed
Function 2
TRACE0_D04
TRACE0_D05
TRACE0_D06
TRACE0_D07
Multiplexed
Function 3
SPI1_SEL4
SPI2_SEL42
SPI1_SEL62
SPI2_SEL62
Multiplexed
Function Input Tap
Signal Name
PC_00
PC_01
PC_02
PC_03
PC_04
PC_05
PC_06
PC_07
PC_08
PC_09
PC_10
PC_11
PC_12
PC_13
PC_14
PC_15
TWI4_SCL1
TWI4_SDA1
TWI5_SCL1
TWI5_SDA1
OSPI0_SEL22
OSPI0_SEL32
SPI1_RDY
LP1_D2
LP1_D3
LP1_D4
LP1_D5
LP1_D6
TM0_TMR08
TM0_TMR09
LP1_D7
LP1_CLK
SYS_FAULT
PPI0_D16
PPI0_D17
PPI0_D18
PPI0_D19
PPI0_D20
PPI0_D21
PPI0_D22
PPI0_D23
OSPI0_CLK1
OSPI0_D31
OSPI0_D21
OSPI0_MOSI1
OSPI0_MISO1
OSPI0_D71
OSPI0_D61
OSPI0_D51
1 To ensure proper timing, for peripherals whose signals are available at multiple places in the pin mux, care must be taken to select all needed signals of the peripheral so that
their associated pins are as close as possible to each other
2 These peripheral signals are available at multiple places in the pin mux. These signals can be selected from either of the two locations in pin mux, regardless of proximity to
other associated signals of the same peripheral.
Table 14. ADSP-SC59x Signal Multiplexing for Port D
Multiplexed
Function 0
Multiplexed
Function 1
Multiplexed
Function 2
Multiplexed
Function 3
Multiplexed
Function Input Tap
Signal Name
PD_00
PD_01
PD_02
PD_03
PD_04
PD_05
PD_06
PD_07
PD_08
PD_09
PD_10
PD_11
PD_12
PD_13
PD_14
PD_15
OSPI0_D41
OSPI0_SEL12
UART1_RTS1
UART1_CTS1
UART1_RX1
UART1_TX1
UART0_CTS1
UART0_RTS1
UART0_RX1
UART0_TX1
PPI0_D06
C2_FLG10
C1_FLG11
ETH0_CRS
LP0_ACK
PPI0_D07
PPI0_D08
ETH0_PTPAUXIN2
TM0_ACI01
OSPI0_DQS1
ETH0_PTPAUXIN1
ETH0_RXERR
ETH0_COL
TM0_ACI00
TM0_ACI02
UART2_RX1
UART2_TX1
UART2_RTS1
UART2_CTS1
LP1_ACK
PPI0_D09
PPI0_D10
PPI0_D11
PPI0_D12
PPI0_D13
PPI0_D14
TM0_TMR06
TM0_TMR07
TWI4_SCL1
TWI4_SDA1
C2_FLG09
TM0_TMR15
1 To ensure proper timing, for peripherals whose signals are available at multiple places in the pin mux, care must be taken to select all needed signals of the peripheral so that
their associated pins are as close as possible to each other
2 These peripheral signals are available at multiple places in the pin mux. These signals can be selected from either of the two locations in pin mux, regardless of proximity to
other associated signals of the same peripheral.
Rev. PrD
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Page 40 of 143
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May 2021
Preliminary Technical Data ADSP-21591/21593/21594/ADSP-SC591/SC592/SC594
Table 15. ADSP-SC59x Signal Multiplexing for Port E
Multiplexed
Function 0
Multiplexed
Function 1
Multiplexed
Function 2
SPI3_SEL3
Multiplexed
Function 3
Multiplexed
Function Input Tap
Signal Name
PE_00
PE_01
PE_02
PE_03
PE_04
PE_05
PE_06
PE_07
PE_08
PE_09
PE_10
PE_11
PE_12
PE_13
PE_14
PE_15
TWI5_SCL1
TWI5_SDA1
TWI0_SCL1
TWI0_SDA1
TWI2_SCL1
TWI2_SDA1
TM0_TMR08
TM0_TMR09
TM0_TMR00
TM0_TMR01
TM0_TMR02
ETH1_REFCLK
ETH1_TXEN
ETH1_TXD0
ETH1_TXD1
ETH1_RXD0
PPI0_D15
PPI0_FS1
PPI0_FS2
PPI0_FS3
PPI0_CLK
PPI0_D00
PPI0_D01
PPI0_D02
PPI0_D03
PPI0_D04
PPI0_D05
SPI3_SEL4
TM0_ACLK15
TM0_ACLK04
SPI1_SEL4
SPI2_SEL32
HADC0_MUX0
HADC0_MUX2
HADC0_MUX1
C1_FLG02
C1_FLG03
SPI1_RDY2
ETH0_PTPAUXIN3
SPI0_SEL4
C2_FLG07
C1_FLG08
C2_FLG13
SPI2_SEL72
SPI0_SEL6
1 To ensure proper timing, for peripherals whose signals are available at multiple places in the pin mux, care must be taken to select all needed signals of the peripheral so that
their associated pins are as close as possible to each other.
2 These peripheral signals are available at multiple places in the pin mux. These signals can be selected from either of the two locations in pin mux, regardless of proximity to
other associated signals of the same peripheral.
Table 16. ADSP-SC59x Signal Multiplexing for Port F
Multiplexed
Function 0
ETH1_RXD1
ETH1_MDIO
ETH1_MDC
ETH1_CRS
Multiplexed
Function 1
SPI3_RDY
Multiplexed
Function 2
SPI0_SEL7
Multiplexed
Function 3
Multiplexed
Function Input Tap
Signal Name
PF_00
PF_01
PF_02
PF_03
PF_04
PF_05
PF_06
PF_07
PF_08
PF_09
PF_10
PF_11
PF_12
PF_13
PF_14
PF_15
C1_FLG07
C1_FLG06
C1_FLG10
USBC0_STOP
USBC0_DATA7
USBC0_DATA6
USBC0_DATA5
USBC0_DATA4
USBC0_NXT
USBC0_DIR
TM0_ACLK13
TM0_CLK
MLB0_CLKOUT
C2_FLG02
SPI1_SEL71
SPI3_SEL2
C2_FLG08
C1_FLG09
C2_FLG04
C2_FLG05
C1_FLG13
C1_FLG12
C2_FLG12
C2_FLG03
SPI3_SEL6
TM0_TMR11
USBC0_DATA3
USBC0_DATA2
USBC0_DATA1
USBC0_DATA0
USBC0_CLK
CANFD0_RX
TM0_ACI04
1 These peripheral signals are available at multiple places in the pin mux. These signals can be selected from either of the two locations in pin mux, regardless of proximity to
other associated signals of the same peripheral.
Rev. PrD
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Page 41 of 143
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May 2021
ADSP-21591/21593/21594/ADSP-SC591/SC592/SC594
Preliminary Technical Data
Table 17. ADSP-SC59x Signal Multiplexing for Port G
Multiplexed
Function 0
Multiplexed
Function 1
Multiplexed
Function 2
Multiplexed
Function 3
Multiplexed
Function Input Tap
TM0_ACLK10
TM0_ACI11
Signal Name
PG_00
PG_01
PG_02
PG_03
PG_04
PG_05
PG_06
PG_07
PG_08
PG_09
PG_10
PG_11
PG_12
PG_13
PG_14
PG_15
CANFD0_TX
CANFD1_RX
CANFD1_TX
UART3_TX
UART3_RX
SPI3_CLK
SPI2_SEL61
SPI0_SEL5
TM0_ACI03
TM0_ACLK11
SPI3_MISO
SPI3_MOSI
SPI3_SEL1
UART3_RTS
UART3_CTS
TM0_ACLK12
SPI3_SS
SPI1_SEL61
SPI2_SEL41
C1_FLG14
C2_FLG14
C2_FLG15
C2_FLG11
C2_FLG06
TM0_ACLK01
TM0_ACLK03
TM0_TMR03
C1_FLG00
OSPI0_SEL31
OSPI0_SEL41
TM0_TMR10
TM0_TMR11
SPI0_SEL2
SPI2_RDY1
TM0_ACI10
SPI3_SEL5
1 These peripheral signals are available at multiple places in the pin mux. These signals can be selected from either of the two locations in pin mux, regardless of proximity to
other associated signals of the same peripheral.
Table 18. ADSP-SC59x Signal Multiplexing for Port H
Multiplexed
Function 0
TM0_TMR12
TM0_TMR13
C1_FLG01
Multiplexed
Function 1
Multiplexed
Function 2
SPI3_SEL7
Multiplexed
Function 3
Multiplexed
Function Input Tap
TM0_ACI12
TM0_ACI13
Signal Name
PH_00
PH_01
PH_02
PH_03
PH_04
PH_05
PH_06
PH_07
PH_08
PH_09
PH_10
PH_11
PH_12
PH_13
PH_14
PH_15
SPI0_RDY1
SPI2_SEL21
TM0_TMR14
ETH0_MDC
ETH0_MDIO
ETH0_RXD0
ETH0_RXD1
TRACE0_D08
TRACE0_D09
TRACE0_D10
TRACE0_D11
ETH0_RXCLK_REFCLK TRACE0_D12
ETH0_RXCTL_RXDV TRACE0_D13
ETH0_TXD0
TRACE0_D14
TRACE0_D15
ETH0_TXD1
ETH0_RXD2
ETH0_RXD3
ETH0_TXCTL_TXEN
ETH0_TXCLK
ETH0_TXD2
1 These peripheral signals are available at multiple places in the pin mux. These signals can be selected from either of the two locations in pin mux, regardless of proximity to
other associated signals of the same peripheral.
Rev. PrD
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May 2021
Preliminary Technical Data ADSP-21591/21593/21594/ADSP-SC591/SC592/SC594
Table 19. ADSP-SC59x Signal Multiplexing for Port I
Multiplexed
Function 0
Multiplexed
Function 1
Multiplexed
Function 2
Multiplexed
Function 3
Multiplexed
Function Input Tap
Signal Name
PI_00
ETH0_TXD3
C2_FLG00
PI_01
ETH0_PTPCLKIN0
ETH0_PTPAUXIN0
C1_FLG04
TWI3_SCL1
PI_02
C2_FLG01
TWI1_SCL1
TWI1_SDA1
ETH0_PTPPPS2
ETH0_PTPPPS3
TWI3_SDA1
ETH0_PTPPPS1
ETH0_PTPPPS0
C1_FLG15
PI_03
PI_04
C1_FLG05
OSPI0_SEL22
PI_05
TM0_ACLK02
TM0_ACLK14
PI_06
1 To ensure proper timing, for peripherals whose signals are available at multiple places in the pin mux, care must be taken to select all needed signals of the peripheral so that
their associated pins are as close as possible to each other
2 These peripheral signals are available at multiple places in the pin mux. These signals can be selected from either of the two locations in pin mux, regardless of proximity to
other associated signals of the same peripheral.
Table 20 shows the internal timer signal routing. This table
applies to both the HPC and LPC 400-ball BGA packages.
Table 20. ADSP-2159x/ADSP-SC59x Internal Timer Signal
Routing
Timer Input Signal
TM0_ACLK0
TM0_ACI5
TM0_ACLK5
TM0_ACI6
Internal Source
SYS_CLKIN0
DAI0_PB04
DAI0_PB03
DAI1_PB04
DAI1_PB03
CNT0_TO
TM0_ACLK6
TM0_ACI7
TM0_ACLK7
TM0_ACI8
TM0_ACLK8
TM0_ACI9
TM0_ACLK9
TM0_ACI14
TM0_ACI15
SYS_CLKIN1
DAI0_PB06
DAI0_PB05
DAI1_PB06
DAI1_PB05
DAI0 Group C
DAI1 Group C
Rev. PrD
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Page 43 of 143
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May 2021
ADSP-21591/21593/21594/ADSP-SC591/SC592/SC594 Preliminary Technical Data
400-BALL LOW PERIPHERAL COUNT (LPC) BGA SIGNAL DESCRIPTIONS
The processor pin definitions are shown in Table 21 for the 400-
ball LPC BGA package. The columns in this table provide the
following information:
• The pin name column identifies the name of the package
pin (at power on reset) on which the signal is located (if a
single function pin) or is multiplexed (if a GPIO pin).
• The signal name column includes the signal name for every
pin and the GPIO multiplexed pin function, where
applicable.
• The DAI pins and their associated signal routing units
(SRUs) connect inputs and outputs of the DAI peripherals
(SPORT, ASRC, S/PDIF, and PCG). See the Digital Audio
Interface (DAI) chapter of the ADSP-2159x/ADSP-
SC591/592/594 SHARC+ Processor Hardware Reference
for complete information on the use of the DAI and SRUs.
• The description column provides a descriptive name for
each signal.
• The port column shows whether or not a signal is
multiplexed with other signals on a GPIO port pin.
Table 21. ADSP-2159x 400-Ball LPC BGA Signal Descriptions
Signal Name
C1_FLG00
Description
Port
Pin Name
PA_12
SHARC+ Core 1 FLAGS I/O 0
SHARC+ Core 1 FLAGS I/O 1
SHARC+ Core 1 FLAGS I/O 2
SHARC+ Core 1 FLAGS I/O 3
CNT0 Count Down and Gate
CNT0 Count Up and Direction
CNT0 Count Zero Marker
DAI0 Pin 1
A
C1_FLG01
A
PA_13
C1_FLG02
B
PB_03
C1_FLG03
B
PB_02
CNT0_DG
B
PB_05
CNT0_UD
B
PB_03
CNT0_ZM
B
PB_04
DAI0_PIN01
DAI0_PIN02
DAI0_PIN03
DAI0_PIN04
DAI0_PIN05
DAI0_PIN06
DAI0_PIN07
DAI0_PIN08
DAI0_PIN09
DAI0_PIN10
DAI0_PIN11
DAI0_PIN12
DAI0_PIN19
DAI0_PIN20
DAI1_PIN01
DAI1_PIN02
DAI1_PIN03
DAI1_PIN04
DAI1_PIN05
DAI1_PIN06
DAI1_PIN07
DAI1_PIN08
DAI1_PIN09
DAI1_PIN10
DAI1_PIN11
DAI1_PIN12
DAI1_PIN19
DAI1_PIN20
DMC0_A00
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
DAI0_PIN01
DAI0_PIN02
DAI0_PIN03
DAI0_PIN04
DAI0_PIN05
DAI0_PIN06
DAI0_PIN07
DAI0_PIN08
DAI0_PIN09
DAI0_PIN10
DAI0_PIN11
DAI0_PIN12
DAI0_PIN19
DAI0_PIN20
DAI1_PIN01
DAI1_PIN02
DAI1_PIN03
DAI1_PIN04
DAI1_PIN05
DAI1_PIN06
DAI1_PIN07
DAI1_PIN08
DAI1_PIN09
DAI1_PIN10
DAI1_PIN11
DAI1_PIN12
DAI1_PIN19
DAI1_PIN20
DMC0_A00
DAI0 Pin 2
DAI0 Pin 3
DAI0 Pin 4
DAI0 Pin 5
DAI0 Pin 6
DAI0 Pin 7
DAI0 Pin 8
DAI0 Pin 9
DAI0 Pin 10
DAI0 Pin 11
DAI0 Pin 12
DAI0 Pin 19
DAI0 Pin 20
DAI1 Pin 1
DAI1 Pin 2
DAI1 Pin 3
DAI1 Pin 4
DAI1 Pin 5
DAI1 Pin 6
DAI1 Pin 7
DAI1 Pin 8
DAI1 Pin 9
DAI1 Pin 10
DAI1 Pin 11
DAI1 Pin 12
DAI1 Pin 19
DAI1 Pin 20
DMC0 Address 0
Rev. PrD
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Preliminary Technical Data ADSP-21591/21593/21594/ADSP-SC591/SC592/SC594
Table 21. ADSP-2159x 400-Ball LPC BGA Signal Descriptions (Continued)
Signal Name
DMC0_A01
DMC0_A02
DMC0_A03
DMC0_A04
DMC0_A05
DMC0_A06
DMC0_A07
DMC0_A08
DMC0_A09
DMC0_A10
DMC0_A11
DMC0_A12
DMC0_A13
DMC0_A14
DMC0_A15
DMC0_BA0
DMC0_BA1
DMC0_BA2
DMC0_CAS
DMC0_CK
Description
Port
Pin Name
DMC0 Address 1
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
DMC0_A01
DMC0_A02
DMC0_A03
DMC0_A04
DMC0_A05
DMC0_A06
DMC0_A07
DMC0_A08
DMC0_A09
DMC0_A10
DMC0_A11
DMC0_A12
DMC0_A13
DMC0_A14
DMC0_A15
DMC0_BA0
DMC0_BA1
DMC0_BA2
DMC0_CAS
DMC0_CK
DMC0 Address 2
DMC0 Address 3
DMC0 Address 4
DMC0 Address 5
DMC0 Address 6
DMC0 Address 7
DMC0 Address 8
DMC0 Address 9
DMC0 Address 10
DMC0 Address 11
DMC0 Address 12
DMC0 Address 13
DMC0 Address 14
DMC0 Address 15
DMC0 Bank Address Input 0
DMC0 Bank Address Input 1
DMC0 Bank Address Input 2
DMC0 Column Address Strobe
DMC0 Clock
DMC0_CK
DMC0 Clock (Complement)
DMC0 Clock Enable
DMC0 Chip Select 0
DMC0 Data 0
DMC0_CK
DMC0_CKE
DMC0_CS0
DMC0_DQ00
DMC0_DQ01
DMC0_DQ02
DMC0_DQ03
DMC0_DQ04
DMC0_DQ05
DMC0_DQ06
DMC0_DQ07
DMC0_DQ08
DMC0_DQ09
DMC0_DQ10
DMC0_DQ11
DMC0_DQ12
DMC0_DQ13
DMC0_DQ14
DMC0_DQ15
DMC0_LDM
DMC0_LDQS
DMC0_LDQS
DMC0_ODT
DMC0_RAS
DMC0_RESET
DMC0_RZQ
DMC0_UDM
DMC0_UDQS
DMC0_CKE
DMC0_CS0
DMC0_DQ00
DMC0_DQ01
DMC0_DQ02
DMC0_DQ03
DMC0_DQ04
DMC0_DQ05
DMC0_DQ06
DMC0_DQ07
DMC0_DQ08
DMC0_DQ09
DMC0_DQ10
DMC0_DQ11
DMC0_DQ12
DMC0_DQ13
DMC0_DQ14
DMC0_DQ15
DMC0_LDM
DMC0_LDQS
DMC0_LDQS
DMC0_ODT
DMC0_RAS
DMC0_RESET
DMC0_RZQ
DMC0_UDM
DMC0_UDQS
DMC0 Data 1
DMC0 Data 2
DMC0 Data 3
DMC0 Data 4
DMC0 Data 5
DMC0 Data 6
DMC0 Data 7
DMC0 Data 8
DMC0 Data 9
DMC0 Data 10
DMC0 Data 11
DMC0 Data 12
DMC0 Data 13
DMC0 Data 14
DMC0 Data 15
DMC0 Data Mask for Lower Byte
DMC0 Data Strobe for Lower Byte
DMC0 Data Strobe for Lower Byte (Complement)
DMC0 On-Die Termination
DMC0 Row Address Strobe
DMC0 Reset
DMC0 External Calibration Resistor Connection
DMC0 Data Mask for Upper Byte
DMC0 Data Strobe for Upper Byte
Rev. PrD
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Page 45 of 143
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May 2021
ADSP-21591/21593/21594/ADSP-SC591/SC592/SC594 Preliminary Technical Data
Table 21. ADSP-2159x 400-Ball LPC BGA Signal Descriptions (Continued)
Signal Name
DMC0_UDQS
DMC0_VREF0
DMC0_VREF1
DMC0_WE
HADC0_EOC_DOUT
HADC0_VIN0
HADC0_VIN1
HADC0_VIN2
HADC0_VIN3
HADC0_VREFN
HADC0_VREFP
JTG_TCK
Description
Port
Pin Name
DMC0_UDQS
DMC0_VREF0
DMC0_VREF1
DMC0_WE
PA_11
DMC0 Data Strobe for Upper Byte (Complement)
DMC0 Voltage Reference
DMC0 Voltage Reference
DMC0 Write Enable
HADC0 End of Conversion
HADC0 Analog Input at Channel 0
HADC0 Analog Input at Channel 1
HADC0 Analog Input at Channel 2
HADC0 Analog Input at Channel 3
HADC0 Ground Reference for ADC
HADC0 External Reference for ADC
JTAG Clock
Not Muxed
Not Muxed
Not Muxed
Not Muxed
A
Not Muxed
HADC0_VIN0
HADC0_VIN1
HADC0_VIN2
HADC0_VIN3
HADC0_VREFN
HADC0_VREFP
JTG_TCK
JTG_TDI
JTG_TDO
JTG_TMS
JTG_TRST
PB_04
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
JTG_TDI
JTAG Serial Data In
JTAG Serial Data Out
JTAG Mode Select
JTAG Reset
Not Muxed
JTG_TDO
JTG_TMS
Not Muxed
Not Muxed
JTG_TRST
LP0_ACK
Not Muxed
LP0 Acknowledge
LP0 Clock
B
B
B
B
B
B
B
B
B
B
B
C
B
C
C
C
C
C
C
C
B
B
B
A
A
A
A
A
A
A
B
A
LP0_CLK
PB_06
LP0_D0
LP0 Data 0
PB_07
LP0_D1
LP0 Data 1
PB_08
LP0_D2
LP0 Data 2
PB_09
LP0_D3
LP0 Data 3
PB_10
LP0_D4
LP0 Data 4
PB_11
LP0_D5
LP0 Data 5
PB_12
LP0_D6
LP0 Data 6
PB_13
LP0_D7
LP0 Data 7
PB_14
LP1_ACK
LP1 Acknowledge
LP1 Clock
PB_02
LP1_CLK
PC_07
LP1_D0
LP1 Data 0
PB_15
LP1_D1
LP1 Data 1
PC_00
LP1_D2
LP1 Data 2
PC_01
LP1_D3
LP1 Data 3
PC_02
LP1_D4
LP1 Data 4
PC_03
LP1_D5
LP1 Data 5
PC_04
LP1_D6
LP1 Data 6
PC_05
LP1_D7
LP1 Data 7
PC_06
MLB0_CLK
MLB0_DAT
MLB0_SIG
OSPI0_CLK
OSPI0_D2
OSPI0_D3
OSPI0_D4
OSPI0_D5
OSPI0_D6
OSPI0_D7
OSPI0_DQS
OSPI0_MISO
MLB0 Single-Ended Clock
MLB0 Single-Ended Data
MLB0 Single-Ended Signal
OSPI0 Clock
PB_02
PB_00
PB_01
PA_04
OSPI0 Data 2
PA_02
OSPI0 Data 3
PA_03
OSPI0 Data 4
PA_06
OSPI0 Data 5
PA_07
OSPI0 Data 6
PA_08
OSPI0 Data 7
PA_09
OSPI0 Data Strobe
OSPI0 Master In, Slave Out
PB_13
PA_00
Rev. PrD
|
Page 46 of 143
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May 2021
Preliminary Technical Data ADSP-21591/21593/21594/ADSP-SC591/SC592/SC594
Table 21. ADSP-2159x 400-Ball LPC BGA Signal Descriptions (Continued)
Signal Name
OSPI0_MOSI
OSPI0_SEL1
OSPI0_SEL2
OSPI0_SEL3
SPI0_CLK
Description
Port
Pin Name
PA_01
OSPI0 Master Out, Slave In
OSPI0 Slave Select Output 1
OSPI0 Slave Select Output 2
OSPI0 Slave Select Output 3
SPI0 Clock
A
A
PA_05
C
PC_04
C
PC_05
A
PA_06
SPI0_MISO
SPI0_MOSI
SPI0_RDY
SPI0_SEL1
SPI0_SEL2
SPI0_SEL3
SPI0_SEL4
SPI0_SS
SPI0 Master In, Slave Out
SPI0 Master Out, Slave In
SPI0 Ready
A
PA_07
A
PA_08
B
PB_11
SPI0 Slave Select Output 1
SPI0 Slave Select Output 2
SPI0 Slave Select Output 3
SPI0 Slave Select Output 4
SPI0 Slave Select Input
SPI1 Clock
A
PA_09
B
PB_05
B
PB_14
B
PB_15
A
PA_09
SPI1_CLK
A
PA_10
SPI1_D2
SPI1 Data 2
A
PA_14
SPI1_D3
SPI1 Data 3
A
PA_15
SPI1_MISO
SPI1_MOSI
SPI1_RDY
SPI1_SEL1
SPI1_SEL2
SPI1_SEL3
SPI1_SEL4
SPI1_SEL5
SPI1_SEL6
SPI1_SEL7
SPI1_SS
SPI1 Master In, Slave Out
SPI1 Master Out, Slave In
SPI1 Ready
A
PA_11
A
PA_12
C
PC_06
SPI1 Slave Select Output 1
SPI1 Slave Select Output 2
SPI1 Slave Select Output 3
SPI1 Slave Select Output 4
SPI1 Slave Select Output 5
SPI1 Slave Select Output 6
SPI1 Slave Select Output 7
SPI1 Slave Select Input
SPI2 Clock
A
PA_13
B
PB_10
B
PB_13
C
PC_00
B
PB_06
C
PC_02
B
PB_08
A
PA_13
SPI2_CLK
A
PA_04
SPI2_D2
SPI2 Data 2
A
PA_02
SPI2_D3
SPI2 Data 3
A
PA_03
SPI2_MISO
SPI2_MOSI
SPI2_RDY
SPI2_SEL1
SPI2_SEL2
SPI2_SEL3
SPI2_SEL4
SPI2_SEL5
SPI2_SEL6
SPI2_SEL7
SPI2_SS
SPI2 Master In, Slave Out
SPI2 Master Out, Slave In
SPI2 Ready
A
PA_00
A
PA_01
B
PB_05
SPI2 Slave Select Output 1
SPI2 Slave Select Output 2
SPI2 Slave Select Output 3
SPI2 Slave Select Output 4
SPI2 Slave Select Output 5
SPI2 Slave Select Output 6
SPI2 Slave Select Output 7
SPI2 Slave Select Input
Boot Mode Control Pin 0
Boot Mode Control Pin 1
Boot Mode Control Pin 2
Clock/Crystal Input
A
PA_05
B
PB_03
B
PB_12
C
PC_01
B
PB_07
C
PC_03
B
PB_09
A
PA_05
SYS_BMODE0
SYS_BMODE1
SYS_BMODE2
SYS_CLKIN0
SYS_CLKOUT
SYS_FAULT
SYS_HWRST
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
SYS_BMODE0
SYS_BMODE1
SYS_BMODE2
SYS_CLKIN0
SYS_CLKOUT
SYS_FAULT
SYS_HWRST
Processor Clock Output
Active-Low Fault Output
Processor Hardware Reset Control
Rev. PrD
|
Page 47 of 143
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May 2021
ADSP-21591/21593/21594/ADSP-SC591/SC592/SC594 Preliminary Technical Data
Table 21. ADSP-2159x 400-Ball LPC BGA Signal Descriptions (Continued)
Signal Name
SYS_RESOUT
SYS_XTAL0
TM0_ACI00
TM0_ACI01
TM0_ACI02
TM0_ACI03
TM0_ACI04
TM0_ACLK01
TM0_ACLK02
TM0_ACLK03
TM0_ACLK04
TM0_CLK
Description
Port
Pin Name
SYS_RESOUT
SYS_XTAL0
PA_07
PA_14
PB_11
PB_00
PA_11
PA_06
PA_08
PA_02
PB_02
PB_01
PA_10
PA_12
PA_13
PB_03
PB_04
PB_05
PB_08
PB_09
PC_05
PC_07
PB_06
PB_07
PB_08
PB_09
PB_10
PC_00
PC_01
PC_02
PC_03
PA_10
PA_11
PB_00
PB_01
PA_14
PA_15
PA_02
PA_03
PC_00
PC_01
PC_02
PC_03
PA_09
PA_08
PA_07
PA_06
PB_01
Reset Output
Not Muxed
Crystal Output
Not Muxed
TIMER0 Alternate Capture Input 0
TIMER0 Alternate Capture Input 1
TIMER0 Alternate Capture Input 2
TIMER0 Alternate Capture Input 3
TIMER0 Alternate Capture Input 4
TIMER0 Alternate Clock 1
TIMER0 Alternate Clock 2
TIMER0 Alternate Clock 3
TIMER0 Alternate Clock 4
TIMER0 Timer Clock
TIMER0 Timer 0
A
A
B
B
A
A
A
A
B
B
A
A
A
B
B
B
B
B
C
C
B
B
B
B
B
C
C
C
C
A
A
B
B
A
A
A
A
C
C
C
C
A
A
A
A
B
TM0_TMR00
TM0_TMR01
TM0_TMR02
TM0_TMR03
TM0_TMR04
TM0_TMR05
TM0_TMR06
TM0_TMR07
TM0_TMR08
TM0_TMR09
TRACE0_CLK
TRACE0_D00
TRACE0_D01
TRACE0_D02
TRACE0_D03
TRACE0_D04
TRACE0_D05
TRACE0_D06
TRACE0_D07
TWI0_SCL
TIMER0 Timer 1
TIMER0 Timer 2
TIMER0 Timer 3
TIMER0 Timer 4
TIMER0 Timer 5
TIMER0 Timer 6
TIMER0 Timer 7
TIMER0 Timer 8
TIMER0 Timer 9
TRACE0 Trace Clock
TRACE0 Trace Data 0
TRACE0 Trace Data 1
TRACE0 Trace Data 2
TRACE0 Trace Data 3
TRACE0 Trace Data 4
TRACE0 Trace Data 5
TRACE0 Trace Data 6
TRACE0 Trace Data 7
TWI0 Serial Clock
TWI0_SDA
TWI0 Serial Data
TWI1_SCL
TWI1 Serial Clock
TWI1_SDA
TWI1 Serial Data
TWI2_SCL
TWI2 Serial Clock
TWI2_SDA
TWI2 Serial Data
TWI3_SCL
TWI3 Serial Clock
TWI3_SDA
TWI3 Serial Data
TWI4_SCL
TWI4 Serial Clock
TWI4_SDA
TWI4 Serial Data
TWI5_SCL
TWI5 Serial Clock
TWI5_SDA
TWI5 Serial Data
UART0_CTS
UART0_RTS
UART0_RX
UART0 Clear to Send
UART0 Request to Send
UART0 Receive
UART0_TX
UART0 Transmit
UART1_CTS
UART1 Clear to Send
Rev. PrD
|
Page 48 of 143
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May 2021
Preliminary Technical Data ADSP-21591/21593/21594/ADSP-SC591/SC592/SC594
Table 21. ADSP-2159x 400-Ball LPC BGA Signal Descriptions (Continued)
Signal Name
UART1_RTS
UART1_RX
UART1_TX
UART2_CTS
UART2_RTS
UART2_RX
UART2_TX
Description
Port
B
Pin Name
PB_00
PA_14
PA_15
PB_14
PB_13
PB_11
PB_12
UART1 Request to Send
UART1 Receive
A
UART1 Transmit
A
UART2 Clear to Send
UART2 Request to Send
UART2 Receive
B
B
B
UART2 Transmit
B
Rev. PrD
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Page 49 of 143
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May 2021
ADSP-21591/21593/21594/ADSP-SC591/SC592/SC594 Preliminary Technical Data
GPIO MULTIPLEXING 400-BALL LOW PERIPHERAL COUNT (LPC) BGA PACKAGE
Table 22 through Table 24 identify the pin functions that are
multiplexed on the GPIO pins of the 400-ball LPC BGA
package.
Table 22. ADSP-2159x Signal Multiplexing for Port A
Multiplexed
Function 0
Multiplexed
Function 1
Multiplexed
Function 2
Multiplexed
Function 3
Multiplexed
Function Input Tap
Signal Name
PA_00
PA_01
PA_02
PA_03
PA_04
PA_05
PA_06
PA_07
PA_08
PA_09
PA_10
PA_11
PA_12
PA_13
PA_14
PA_15
SPI2_MISO
SPI2_MOSI
SPI2_D2
OSPI0_MISO
OSPI0_MOSI
OSPI0_D2
OSPI0_D3
OSPI0_CLK
OSPI0_SEL1
UART0_TX
UART0_RX
UART0_RTS
UART0_CTS
SPI1_CLK
TWI3_SCL
TWI3_SDA
TM0_ACLK03
SPI2_D3
SPI2_CLK
SPI2_SEL1
SPI0_CLK
SPI0_MISO
SPI0_MOSI
SPI0_SEL1
TWI0_SCL
TWI0_SDA
C1_FLG00
C1_FLG01
TWI2_SCL
TWI2_SDA
SPI2_SS
OSPI0_D4
TM0_ACLK01
TM0_ACI00
TM0_ACLK02
SPI0_SS
OSPI0_D5
OSPI0_D6
OSPI0_D7
TM0_TMR00
HADC0_EOC_DOUT
TM0_TMR01
TM0_TMR02
UART1_RX
SPI1_MISO
SPI1_MOSI
SPI1_SEL1
SPI1_D2
TM0_ACI04
SPI1_SS
TM0_ACI01
SPI1_D3
UART1_TX
Table 23. ADSP-2159x Signal Multiplexing for Port B
Multiplexed
Function 0
Multiplexed
Function 1
Multiplexed
Function 2
Multiplexed
Function 3
Multiplexed
Function Input Tap
Signal Name
PB_00
PB_01
PB_02
PB_03
PB_04
PB_05
PB_06
PB_07
PB_08
PB_09
PB_10
PB_11
PB_12
PB_13
PB_14
PB_15
MLB0_DAT
MLB0_SIG
MLB0_CLK
TM0_TMR03
TM0_TMR04
TM0_TMR05
LP0_CLK
LP0_D0
TWI1_SCL
TWI1_SDA
C1_FLG03
C1_FLG02
SPI1_RDY
SPI2_RDY
SPI1_SEL5
SPI2_SEL5
SPI1_SEL7
SPI2_SEL7
SPI1_SEL2
SPI0_RDY
SPI2_SEL3
SPI1_SEL3
SPI0_SEL3
SPI0_SEL4
UART1_RTS
UART1_CTS
LP1_ACK
TM0_ACI03
TM0_CLK
TM0_ACLK04
CNT0_UD
CNT0_ZM
CNT0_DG
SPI2_SEL2
LP0_ACK
SPI0_SEL2
TRACE0_CLK
TRACE0_D00
TRACE0_D01
TRACE0_D02
TRACE0_D03
UART2_RX
LP0_D1
TM0_TMR06
TM0_TMR07
LP0_D2
LP0_D3
LP0_D4
TM0_ACI02
LP0_D5
UART2_TX
LP0_D6
OSPI0_DQS
UART2_RTS
UART2_CTS
LP0_D7
LP1_D0
Rev. PrD
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Page 50 of 143
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May 2021
Preliminary Technical Data ADSP-21591/21593/21594/ADSP-SC591/SC592/SC594
Table 24. ADSP-2159x Signal Multiplexing for Port C
Multiplexed
Function 0
Multiplexed
Function 1
Multiplexed
Function 2
Multiplexed
Function 3
Multiplexed
Function Input Tap
Signal Name
PC_00
LP1_D1
LP1_D2
LP1_D3
LP1_D4
LP1_D5
LP1_D6
LP1_D7
LP1_CLK
TWI4_SCL
TWI4_SDA
TWI5_SCL
TWI5_SDA
OSPI0_SEL2
OSPI0_SEL3
SPI1_RDY
TRACE0_D04
TRACE0_D05
TRACE0_D06
TRACE0_D07
SPI1_SEL4
SPI2_SEL4
SPI1_SEL6
SPI2_SEL6
PC_01
PC_02
PC_03
PC_04
PC_05
TM0_TMR08
TM0_TMR09
PC_06
PC_07
SYS_FAULT
Rev. PrD
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Page 51 of 143
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May 2021
ADSP-21591/21593/21594/ADSP-SC591/SC592/SC594 Preliminary Technical Data
ADSP-2159x/ADSP-SC59x DESIGNER QUICK REFERENCE
Table 25 provides a quick reference summary of pin related
information for circuit board design. The columns in this table
provide the following information:
• The reset termination column specifies the termination
present when the processor is in the reset state.
• The reset drive column specifies the active drive on the sig-
nal when the processor is in the reset state.
• The signal name column includes the signal name for every
pin and the GPIO multiplexed pin function, where
applicable.
• The power domain column specifies the power supply
domain in which the signal resides.
• The type column identifies the I/O type or supply type of
the pin. The abbreviations used in this column are analog
(a), supply (s), ground (g) and Input, Output, and InOut.
• The description and notes column identifies any special
requirements or characteristics for a signal. These recom-
mendations apply whether or not the hardware block
associated with the signal is featured on the product. If no
special requirements are listed, the signal can be left uncon-
nected if it is not used. For multiplexed GPIO pins, this
column identifies the functions available on the pin.
• The driver type column identifies the driver type used by
the corresponding pin. The driver types are defined in the
Output Drive Currents section of this data sheet.
• The internal termination column specifies the termination
present after the processor is powered up (both during
reset and after reset).
Table 25. ADSP-2159x/ADSP-SC59x Designer Quick Reference
Driver Internal
Reset
Reset Power
Signal Name
Type
Type Termination
Termination Drive Domain
Description and Notes
DAI0_PIN01
InOut
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
Programmable
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None VDD_EXT Desc: DAI0 Pin 1
pull-up/pull-down1
Notes: See note2
DAI0_PIN02
DAI0_PIN03
DAI0_PIN04
DAI0_PIN05
DAI0_PIN06
DAI0_PIN07
DAI0_PIN08
DAI0_PIN09
DAI0_PIN10
DAI0_PIN11
DAI0_PIN12
DAI0_PIN13
DAI0_PIN14
DAI0_PIN15
InOut
InOut
InOut
InOut
InOut
InOut
InOut
InOut
InOut
InOut
InOut
InOut
InOut
InOut
Programmable
None VDD_EXT Desc: DAI0 Pin 2
pull-up/pull-down1
Notes: See note2
Programmable
None VDD_EXT Desc: DAI0 Pin 3
Notes: See note2
pull-up/pull-down1
Programmable
None VDD_EXT Desc: DAI0 Pin 4
Notes: See note2
pull-up/pull-down1
Programmable
None VDD_EXT Desc: DAI0 Pin 5
Notes: See note2
pull-up/pull-down1
Programmable
None VDD_EXT Desc: DAI0 Pin 6
Notes: See note2
pull-up/pull-down1
Programmable
None VDD_EXT Desc: DAI0 Pin 7
Notes: See note2
pull-up/pull-down1
Programmable
None VDD_EXT Desc: DAI0 Pin 8
Notes: See note2
pull-up/pull-down1
Programmable
None VDD_EXT Desc: DAI0 Pin 9
Notes: See note2
pull-up/pull-down1
Programmable
None VDD_EXT Desc: DAI0 Pin 10
Notes: See note2
pull-up/pull-down1
Programmable
None VDD_EXT Desc: DAI0 Pin 11
Notes: See note2
pull-up/pull-down1
Programmable
None VDD_EXT Desc: DAI0 Pin 12
Notes: See note2
pull-up/pull-down1
Programmable
None VDD_EXT Desc: DAI0 Pin 13
Notes: See note2
pull-up/pull-down1
Programmable
None VDD_EXT Desc: DAI0 Pin 14
Notes: See note2
pull-up/pull-down1
Programmable
None VDD_EXT Desc: DAI0 Pin 15
Notes: See note2
pull-up/pull-down1
Rev. PrD
|
Page 52 of 143
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May 2021
Preliminary Technical Data ADSP-21591/21593/21594/ADSP-SC591/SC592/SC594
Table 25. ADSP-2159x/ADSP-SC59x Designer Quick Reference (Continued)
Driver Internal
Reset
Reset Power
Signal Name
Type
Type Termination
Termination Drive Domain
Description and Notes
DAI0_PIN16
InOut
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
Programmable
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None VDD_EXT Desc: DAI0 Pin 16
pull-up/pull-down1
Notes: See note2
DAI0_PIN17
DAI0_PIN18
DAI0_PIN19
DAI0_PIN20
DAI1_PIN01
DAI1_PIN02
DAI1_PIN03
DAI1_PIN04
DAI1_PIN05
DAI1_PIN06
DAI1_PIN07
DAI1_PIN08
DAI1_PIN09
DAI1_PIN10
DAI1_PIN11
DAI1_PIN12
DAI1_PIN13
DAI1_PIN14
DAI1_PIN15
DAI1_PIN16
DAI1_PIN17
DAI1_PIN18
InOut
InOut
InOut
InOut
InOut
InOut
InOut
InOut
InOut
InOut
InOut
InOut
InOut
InOut
InOut
InOut
InOut
InOut
InOut
InOut
InOut
InOut
Programmable
None VDD_EXT Desc: DAI0 Pin 17
pull-up/pull-down1
Notes: See note2
None VDD_EXT Desc: DAI0 Pin 18
Notes: See note2
Programmable
pull-up/pull-down1
Programmable
None VDD_EXT Desc: DAI0 Pin 19
Notes: See note2
pull-up/pull-down1
Programmable
None VDD_EXT Desc: DAI0 Pin 20
Notes: See note2
pull-up/pull-down1
Programmable
None VDD_EXT Desc: DAI1 Pin 1
Notes: See note2
pull-up/pull-down1
Programmable
None VDD_EXT Desc: DAI1 Pin 2
Notes: See note2
pull-up/pull-down1
Programmable
None VDD_EXT Desc: DAI1 Pin 3
Notes: See note2
pull-up/pull-down1
Programmable
None VDD_EXT Desc: DAI1 Pin 4
Notes: See note2
pull-up/pull-down1
Programmable
None VDD_EXT Desc: DAI1 Pin 5
Notes: See note2
pull-up/pull-down1
Programmable
None VDD_EXT Desc: DAI1 Pin 6
Notes: See note2
pull-up/pull-down1
Programmable
None VDD_EXT Desc: DAI1 Pin 7
Notes: See note2
pull-up/pull-down1
Programmable
None VDD_EXT Desc: DAI1 Pin 8
Notes: See note2
pull-up/pull-down1
Programmable
None VDD_EXT Desc: DAI1 Pin 9
Notes: See note2
pull-up/pull-down1
Programmable
None VDD_EXT Desc: DAI1 Pin 10
Notes: See note2
pull-up/pull-down1
Programmable
None VDD_EXT Desc: DAI1 Pin 11
Notes: See note2
pull-up/pull-down1
Programmable
None VDD_EXT Desc: DAI1 Pin 12
Notes: See note2
pull-up/pull-down1
Programmable
None VDD_EXT Desc: DAI1 Pin 13
Notes: See note2
pull-up/pull-down1
Programmable
None VDD_EXT Desc: DAI1 Pin 14
Notes: See note2
pull-up/pull-down1
Programmable
None VDD_EXT Desc: DAI1 Pin 15
Notes: See note2
pull-up/pull-down1
Programmable
None VDD_EXT Desc: DAI1 Pin 16
Notes: See note2
pull-up/pull-down1
Programmable
None VDD_EXT Desc: DAI1 Pin 17
Notes: See note2
pull-up/pull-down1
Programmable
None VDD_EXT Desc: DAI1 Pin 18
Notes: See note2
pull-up/pull-down1
Rev. PrD
|
Page 53 of 143
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May 2021
ADSP-21591/21593/21594/ADSP-SC591/SC592/SC594 Preliminary Technical Data
Table 25. ADSP-2159x/ADSP-SC59x Designer Quick Reference (Continued)
Driver Internal
Reset
Reset Power
Signal Name
Type
Type Termination
Termination Drive Domain
Description and Notes
DAI1_PIN19
InOut
A
A
Programmable
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None VDD_EXT Desc: DAI1 Pin 19
pull-up/pull-down1
Notes: See note2
DAI1_PIN20
DMC0_A00
DMC0_A01
DMC0_A02
DMC0_A03
DMC0_A04
DMC0_A05
DMC0_A06
DMC0_A07
DMC0_A08
DMC0_A09
DMC0_A10
DMC0_A11
DMC0_A12
DMC0_A13
DMC0_A14
DMC0_A15
DMC0_BA0
DMC0_BA1
DMC0_BA2
DMC0_CAS
DMC0_CK
InOut
Programmable
None VDD_EXT Desc: DAI1 Pin 20
pull-up/pull-down1
Notes: See note2
VDD_DMC Desc: DMC0 Address 0
Notes: No notes
Output B
Output B
Output B
Output B
Output B
Output B
Output B
Output B
Output B
Output B
Output B
Output B
Output B
Output B
Output B
Output B
Output B
Output B
Output B
Output B
Output C
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
VDD_DMC Desc: DMC0 Address 1
Notes: No notes
VDD_DMC Desc: DMC0 Address 2
Notes: No notes
VDD_DMC Desc: DMC0 Address 3
Notes: No notes
VDD_DMC Desc: DMC0 Address 4
Notes: No notes
VDD_DMC Desc: DMC0 Address 5
Notes: No notes
VDD_DMC Desc: DMC0 Address 6
Notes: No notes
VDD_DMC Desc: DMC0 Address 7
Notes: No notes
VDD_DMC Desc: DMC0 Address 8
Notes: No notes
VDD_DMC Desc: DMC0 Address 9
Notes: No notes
VDD_DMC Desc: DMC0 Address 10
Notes: No notes
VDD_DMC Desc: DMC0 Address 11
Notes: No notes
VDD_DMC Desc: DMC0 Address 12
Notes: No notes
VDD_DMC Desc: DMC0 Address 13
Notes: No notes
VDD_DMC Desc: DMC0 Address 14
Notes: No notes
VDD_DMC Desc: DMC0 Address 15
Notes: No notes
VDD_DMC Desc: DMC0 Bank Address Input 0
Notes: No notes
VDD_DMC Desc: DMC0 Bank Address Input 1
Notes: No notes
VDD_DMC Desc: DMC0 Bank Address Input 2
Notes: No notes
VDD_DMC Desc: DMC0 Column Address Strobe
Notes: No notes
VDD_DMC Desc: DMC0 Clock
Notes: No notes
Rev. PrD
|
Page 54 of 143
|
May 2021
Preliminary Technical Data ADSP-21591/21593/21594/ADSP-SC591/SC592/SC594
Table 25. ADSP-2159x/ADSP-SC59x Designer Quick Reference (Continued)
Driver Internal
Reset
Reset Power
Signal Name
Type
Type Termination
Termination Drive Domain
Description and Notes
DMC0_CKE
Output B
Output C
Output B
None
None
None
None
None
None
None
L
VDD_DMC Desc: DMC0 Clock Enable
Notes: No notes
DMC0_CK
H
L
VDD_DMC Desc: DMC0 Clock (Complement)
Notes: No notes
DMC0_CS0
DMC0_DQ00
VDD_DMC Desc: DMC0 Chip Select 0
Notes: No notes
InOut
InOut
InOut
InOut
InOut
InOut
InOut
InOut
InOut
InOut
InOut
InOut
InOut
InOut
InOut
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
Internal logic
ensures that input
signal does not float
None VDD_DMC Desc: DMC0 Data 0
Notes: No notes
DMC0_DQ01
DMC0_DQ02
DMC0_DQ03
DMC0_DQ04
DMC0_DQ05
DMC0_DQ06
DMC0_DQ07
DMC0_DQ08
DMC0_DQ09
DMC0_DQ10
DMC0_DQ11
DMC0_DQ12
DMC0_DQ13
DMC0_DQ14
Internal logic
ensures that input
signal does not float
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None VDD_DMC Desc: DMC0 Data 1
Notes: No notes
Internal logic
ensures that input
signal does not float
None VDD_DMC Desc: DMC0 Data 2
Notes: No notes
Internal logic
ensures that input
signal does not float
None VDD_DMC Desc: DMC0 Data 3
Notes: No notes
Internal logic
ensures that input
signal does not float
None VDD_DMC Desc: DMC0 Data 4
Notes: No notes
Internal logic
ensures that input
signal does not float
None VDD_DMC Desc: DMC0 Data 5
Notes: No notes
Internal logic
ensures that input
signal does not float
None VDD_DMC Desc: DMC0 Data 6
Notes: No notes
Internal logic
ensures that input
signal does not float
None VDD_DMC Desc: DMC0 Data 7
Notes: No notes
Internal logic
ensures that input
signal does not float
None VDD_DMC Desc: DMC0 Data 8
Notes: No notes
Internal logic
ensures that input
signal does not float
None VDD_DMC Desc: DMC0 Data 9
Notes: No notes
Internal logic
ensures that input
signal does not float
None VDD_DMC Desc: DMC0 Data 10
Notes: No notes
Internal logic
ensures that input
signal does not float
None VDD_DMC Desc: DMC0 Data 11
Notes: No notes
Internal logic
ensures that input
signal does not float
None VDD_DMC Desc: DMC0 Data 12
Notes: No notes
Internal logic
ensures that input
signal does not float
None VDD_DMC Desc: DMC0 Data 13
Notes: No notes
Internal logic
ensures that input
signal does not float
None VDD_DMC Desc: DMC0 Data 14
Notes: No notes
Rev. PrD
|
Page 55 of 143
|
May 2021
ADSP-21591/21593/21594/ADSP-SC591/SC592/SC594 Preliminary Technical Data
Table 25. ADSP-2159x/ADSP-SC59x Designer Quick Reference (Continued)
Driver Internal
Reset
Reset Power
Signal Name
Type
Type Termination
Termination Drive Domain
Description and Notes
DMC0_DQ15
InOut
B
Internal logic
ensures that input
signal does not float
None
None VDD_DMC Desc: DMC0 Data 15
Notes: No notes
DMC0_LDM
DMC0_LDQS
Output B
None
None
None
L
VDD_DMC Desc: DMC0 Data Mask for Lower Byte
Notes: No notes
InOut
InOut
C
C
Internal logic
ensures that input
signal does not float
None VDD_DMC Desc: DMC0 Data Strobe for Lower Byte
Notes: No notes
DMC0_LDQS
Internal logic
None
None VDD_DMC Desc: DMC0 Data Strobe for Lower Byte
ensures that input
signal does not float
(Complement)
Notes: No notes
DMC0_ODT
DMC0_RAS
DMC0_RESET
DMC0_RZQ
Output B
Output B
Output B
None
None
None
None
None
None
None
None
L
L
L
VDD_DMC Desc: DMC0 On-Die Termination
Notes: No notes
VDD_DMC Desc: DMC0 Row Address Strobe
Notes: No notes
VDD_DMC Desc: DMC0 Reset
Notes: No notes
a
B
None VDD_DMC Desc: DMC0 External Calibration Resistor
Connection
Notes: 34 Ω external pull-down must be
added
DMC0_UDM
DMC0_UDQS
Output B
None
None
None
L
VDD_DMC Desc: DMC0 Data Mask for Upper Byte
Notes: No notes
InOut
InOut
C
C
Internal logic
ensures that input
signal does not float
None VDD_DMC Desc: DMC0 Data Strobe for Upper Byte
Notes: No notes
DMC0_UDQS
Internal logic
None
None VDD_DMC Desc: DMC0 Data Strobe for Upper Byte
ensures that input
signal does not float
(complement)
Notes: No notes
DMC0_VREF0
DMC0_VREF1
DMC0_WE
a
a
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None VDD_DMC Desc: DMC0 Voltage Reference
Notes: No notes
None VDD_DMC Desc: DMC0 Voltage Reference
Notes: No notes
Output B
g
L
VDD_DMC Desc: DMC0 Write Enable
Notes: No notes
GND
None
Desc: Ground
Notes: No notes
HADC0_VIN0
HADC0_VIN1
HADC0_VIN2
HADC0_VIN3
HADC0_VIN4
HADC0_VIN5
a
a
a
a
a
a
NA
None VDD_ANA Desc: HADC0 Analog Input 0
Notes: Connect to GND if not used
NA
NA
NA
NA
NA
None VDD_ANA Desc: HADC0 Analog Input 1
Notes: Connect to GND if not used
None VDD_ANA Desc: HADC0 Analog Input 2
Notes: Connect to GND if not used
None VDD_ANA Desc: HADC0 Analog Input 3
Notes: Connect to GND if not used
None VDD_ANA Desc: HADC0 Analog Input 4
Notes: Connect to GND if not used
None VDD_ANA Desc: HADC0 Analog Input 5
Notes: Connect to GND if not used
Rev. PrD
|
Page 56 of 143
|
May 2021
Preliminary Technical Data ADSP-21591/21593/21594/ADSP-SC591/SC592/SC594
Table 25. ADSP-2159x/ADSP-SC59x Designer Quick Reference (Continued)
Driver Internal
Reset
Reset Power
Signal Name
Type
Type Termination
Termination Drive Domain
Description and Notes
HADC0_VIN6
a
NA
NA
NA
None
None
None
None
None
None
None VDD_ANA Desc: HADC0 Analog Input 6
Notes: Connect to GND if not used
HADC0_VIN7
a
s
None VDD_ANA Desc: HADC0 Analog Input 7
Notes: Connect to GND if not used
HADC0_VREFN
None VDD_ANA Desc: HADC0 Ground Reference for ADC
Notes: Connect to GND if HADC and TMU are
not used
HADC0_VREFP
s
NA
None
None
None VDD_ANA Desc: HADC0 External Reference for ADC
Notes: Connect to VDD_REF if HADC and
TMU are not used
JTG_TCK
JTG_TDI
JTG_TDO
Input
Input
Pull-up
Pull-up
None
Pull-up
Pull-up
None VDD_EXT Desc: JTAG Clock
Notes: No notes
None VDD_EXT Desc: JTAG Serial Data In
Notes: No notes
Output A
High-Z when None VDD_EXT Desc: JTAG Serial Data Out
JTG_TRST is
Notes: No notes
low, not
affected by
SYS_HWRST
JTG_TMS
InOut
Input
A
Pull-up
Pull-up
Pull-down
None
None VDD_EXT Desc: JTAG Mode Select
Notes: No notes
JTG_TRST
MLB0_CLKN
Pull-down
None VDD_EXT Desc: JTAG Reset
Notes: No notes
Input N/A
Input N/A
Internal logic
ensures that input
signal does not float
None VDD_REF Desc: MLB0 Differential Clock (–)
Notes: No notes
MLB0_CLKP
MLB0_DATN
MLB0_DATP
MLB0_SIGN
MLB0_SIGP
PA_00
Internal logic
ensures that input
signal does not float
None
None
None
None
None
None
None
None
None VDD_REF Desc: MLB0 Differential Clock (+)
Notes: No notes
InOut
InOut
InOut
InOut
InOut
InOut
InOut
I
Internal logic
ensures that input
signal does not float
None VDD_REF Desc: MLB0 Differential Data (–)
Notes: No notes
I
Internal logic
ensures that input
signal does not float
None VDD_REF Desc: MLB0 Differential Data (+)
Notes: No notes
I
Internal logic
ensures that input
signal does not float
None VDD_REF Desc: MLB0 Differential Signal (–)
Notes: No notes
I
Internal logic
ensures that input
signal does not float
None VDD_REF Desc: MLB0 Differential Signal (+)
Notes: No notes
A
A
A
Programmable
None VDD_EXT Desc: PORTA Position 0 | OSPI0 MISO | SPI2
pull-up/pull-down1
MISO
Notes: See note2
PA_01
Programmable
None VDD_EXT Desc: PORTA Position1 | OSPI0 MOSI | SPI2
pull-up/pull-down1
MOSI
Notes: See note2
PA_02
Programmable
None VDD_EXT Desc: PORTA Position 2 | OSPI0 D2 | SPI2 D2 |
TWI3 Clock | TIMER0 Timer Alternate Clock 3
Notes: See note2
pull-up/pull-down1
Rev. PrD
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May 2021
ADSP-21591/21593/21594/ADSP-SC591/SC592/SC594 Preliminary Technical Data
Table 25. ADSP-2159x/ADSP-SC59x Designer Quick Reference (Continued)
Driver Internal
Reset
Reset Power
Signal Name
Type
Type Termination
Termination Drive Domain
Description and Notes
PA_03
InOut
A
A
A
Programmable
None
None
None
None VDD_EXT Desc: PORTA Position 3 | OSPI0 D3 | SPI2 D3 |
pull-up/pull-down1
TWI3 Data
Notes: See note2
PA_04
PA_05
InOut
InOut
Programmable
None VDD_EXT Desc: PORTA Position 4 | OSPI0 Clock | SPI2
pull-up/pull-down1
Clock
Notes: See note2
Programmable
None VDD_EXT Desc: PORTA Position 5 | OSPI0 Slave Select
Output 1 | SPI2 Slave Select Output 1 | SPI2
Slave Select
pull-up/pull-down1
Notes: See note2
PA_06
InOut
A
Programmable
None
None VDD_EXT Desc: PORTA Position 6 | OSPI0 D4 | SPI0
pull-up/pull-down1
Clock | UART0 TX | TIMER0 Timer Alternate
Clock 1
Notes: See note2
PA_07
PA_08
PA_09
InOut
InOut
InOut
A
A
A
Programmable
None
None
None
None VDD_EXT Desc:PORTAPosition7|OSPI0D5|SPI0MISO
| UART0 RX | TIMER0 Timer Alternate Input 0
Notes: See note2
pull-up/pull-down1
Programmable
None VDD_EXT Desc:PORTAPosition8|OSPI0D6|SPI0MOSI
| UART0 RTS | TIMER0 Timer Alternate Clock 2
Notes: See note2
pull-up/pull-down1
Programmable
None VDD_EXT Desc:PORTAPosition9|OSPI0D7|SPI0Slave
pull-up/pull-down1
Select Output 1 | UART0 CTS | SPI0 Slave
Select
Notes: See note2
PA_10
PA_11
InOut
InOut
A
A
Programmable
None
None
None VDD_EXT Desc:PORTA Position 10|SPI1Clock | TIMER0
Timer 0 | TWI0 Clock
pull-up/pull-down1
Notes: See note2
Programmable
None VDD_EXT Desc: PORTA Position 11 | HADC0 End of
Conversion | SPI1 MISO | TWI0 Data | TIMER0
Timer Alternate Input 4
pull-up/pull-down1
Notes: See note2
PA_12
PA_13
InOut
InOut
A
A
Programmable
None
None
None VDD_EXT Desc: PORTA Position 12 | SPI1 MOSI |
SHARC1 Core Flag 0 | TIMER0 Timer 1
Notes: See note2
pull-up/pull-down1
Programmable
None VDD_EXT Desc: PORTA Position 13 | SPI1 Slave Select
Output 1 | SHARC1 Core Flag 1 | TIMER0 Timer
2 | SPI1 Slave Select
pull-up/pull-down1
Notes: See note2
PA_14
InOut
A
Programmable
None
None VDD_EXT Desc: PORTA Position 14 | SPI1 D2 | TWI2
pull-up/pull-down1
Clock | UART1 RX | TIMER0 Alternate Clock
Input 1
Notes: See note2
PA_15
PB_00
InOut
InOut
A
A
Programmable
None
None
None VDD_EXT Desc:PORTAPosition15| SPI1 D3| TWI2 Data
pull-up/pull-down1
| UART1 TX
Notes: See note2
Programmable
None VDD_EXT Desc: PORTB Position 0 | MLB0 Data | TWI1
pull-up/pull-down1
Clock | UART1 RTS | TIMER0 Alternate Clock
Input 3
Notes: See note2
Rev. PrD
|
Page 58 of 143
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May 2021
Preliminary Technical Data ADSP-21591/21593/21594/ADSP-SC591/SC592/SC594
Table 25. ADSP-2159x/ADSP-SC59x Designer Quick Reference (Continued)
Driver Internal
Reset
Reset Power
Signal Name
Type
Type Termination
Termination Drive Domain
Description and Notes
PB_01
InOut
A
Programmable
None
None
None VDD_EXT Desc: PORTB Position 1 | MLB0 Signal | TWI1
Data | UART1 CTS | TIMER0 Timer Clock
Notes: See note2
pull-up/pull-down1
PB_02
PB_03
PB_04
PB_05
InOut
InOut
InOut
InOut
A
Programmable
None VDD_EXT Desc: PORTB Position 2 | LP1 Acknowledge |
MLB0 Clock | SHARC1 Core Flag 3 | TIMER0
Timer Alternate Clock 4
pull-up/pull-down1
Notes: See note2
A
A
A
Programmable
None
None
None
None VDD_EXT Desc: PORTB Position 3 | SPI2 Slave Select
Output 2 | SHARC1 Core Flag 2 | TIMER0 Timer
3 | CNT0 Count Up and Direction
pull-up/pull-down1
Notes: See note2
Programmable
None VDD_EXT Desc: PORTB Position 4 | LP0 Acknowledge |
pull-up/pull-down1
SPI1 Ready | TIMER0 Timer 4 | CNT0 Zero
Marker
Notes: See note2
Programmable
None VDD_EXT Desc: PORTB Position 5 | SPI0 Slave Select
Output 2 |SPI2 Ready| TIMER0 Timer 5| CNT0
Count Down and Gate
pull-up/pull-down1
Notes: See note2
PB_06
PB_07
PB_08
InOut
InOut
InOut
A
A
A
Programmable
None
None
None
None VDD_EXT Desc: PORTB Position 6 | LP0 Clock | SPI1
Slave Select Output 5 | TRACE0 Trace Clock
Notes: See note2
pull-up/pull-down1
Programmable
None VDD_EXT Desc: PORTB Position 7 | LP0 D0 | SPI2 Slave
Select Output 5 | TRACE0 Trace Data 00
Notes: See note2
pull-up/pull-down1
Programmable
None VDD_EXT Desc: PORTB Position 8 | LP0 D1 | SPI1 Slave
Select Output 7 | TIMER0 Timer 6 | TRACE0
Trace Data 01
pull-up/pull-down1
Notes: See note2
PB_09
InOut
A
Programmable
None
None VDD_EXT Desc: PORTB Position 9 | LP0 D2 | SPI2 Slave
Select Output 7 | TIMER0 Timer 7 | TRACE0
Trace Data 02
pull-up/pull-down1
Notes: See note2
PB_10
PB_11
PB_12
PB_13
PB_14
InOut
InOut
InOut
InOut
InOut
A
A
A
A
A
Programmable
None
None
None
None
None
None VDD_EXT Desc: PORTB Position 10 | LP0 D3 | SPI1 Slave
Select Output 2 | TRACE0 Trace Data 03
Notes: See note2
pull-up/pull-down1
Programmable
None VDD_EXT Desc:PORTBPosition11|LP0D4|SPI0Ready
| UART2 RX | TIMER0 Alternate Clock Input 2
Notes: See note2
pull-up/pull-down1
Programmable
None VDD_EXT Desc: PORTB Position 12 | LP0 D5 | SPI2 Slave
Select Output 3 | UART2 TX
pull-up/pull-down1
Notes: See note2
Programmable
None VDD_EXT Desc:PORTBPosition 13| LP0 D6 |OSPI0DQS
| SPI1 Slave Select Output 3 | UART2 RTS
Notes: See note2
pull-up/pull-down1
Programmable
None VDD_EXT Desc: PORTB Position 14 | LP0 D7 | SPI0 Slave
Select Output 3 | UART2 CTS
pull-up/pull-down1
Notes: See note2
Rev. PrD
|
Page 59 of 143
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May 2021
ADSP-21591/21593/21594/ADSP-SC591/SC592/SC594 Preliminary Technical Data
Table 25. ADSP-2159x/ADSP-SC59x Designer Quick Reference (Continued)
Driver Internal
Reset
Reset Power
Signal Name
Type
Type Termination
Termination Drive Domain
Description and Notes
PB_15
InOut
A
Programmable
None
None
None VDD_EXT Desc: PORTB Position 15 | LP1 D0 | SPI0 Slave
pull-up/pull-down1
Select Output 4
Notes: See note2
PC_00
PC_01
PC_02
PC_03
InOut
InOut
InOut
InOut
A
Programmable
None VDD_EXT Desc: PORTC Position 0 | LP1 D1 | SPI1 Slave
Select Output 4 | TRACE0 Trace Data 04 |
TWI4 Clock
pull-up/pull-down1
Notes: See note2
A
A
A
Programmable
None
None
None
None VDD_EXT Desc: PORTC Position 1 | LP1 D2 | SPI2 Slave
Select Output 4 | TRACE0 Trace Data 05 |
TWI4 Data
pull-up/pull-down1
Notes: See note2
Programmable
None VDD_EXT Desc: PORTC Position 2 | LP1 D3 | SPI1 Slave
Select Output 6 | TRACE0 Trace Data 06 |
TWI5 Clock
pull-up/pull-down1
Notes: See note2
Programmable
None VDD_EXT Desc: PORTC Position 3 | LP1 D4 | SPI2 Slave
Select Output 6 | TRACE0 Trace Data 07 |
TWI5 Data
pull-up/pull-down1
Notes: See note2
PC_04
PC_05
InOut
InOut
A
A
Programmable
None
None
None VDD_EXT Desc: PORTC Position 4 | LP1 D5 | OSPI0 Slave
pull-up/pull-down1
Select Output 2
Notes: See note2
Programmable
None VDD_EXT Desc: PORTC Position 5 | LP1 D6 | OSPI0 Slave
Select Output 3 | TIMER0 Timer 8
pull-up/pull-down1
Notes: See note2
PC_06
PC_07
InOut
InOut
A
A
Programmable
None
None
None VDD_EXT Desc: PORTC Position 6 | LP1 D7 | SPI1 Ready
Notes: See note2
pull-up/pull-down1
Programmable
None VDD_EXT Desc: PORTC Position 7 | LP1 Clock | OSPI0
Slave Select Output 4 | System Fault | TIMER0
Timer 9
pull-up/pull-down1
Notes: Defaults to GPIO on HPC package.
Defaults to SYS_FAULT on LPC package, so
external pull-down required to keep signal
in deasserted state.
PC_08
InOut
A
Programmable
None
None VDD_EXT Desc: PORTC Position 8 | EPPI0 D16 | OSPI0
pull-up/pull-down1
Clock
Notes: See note2
PC_09
PC_10
InOut
InOut
A
A
Programmable
None
None
None VDD_EXT Desc:PORTCPosition 9|EPPI0D17|OSPI0D3
Notes: See note2
pull-up/pull-down1
Programmable
None VDD_EXT Desc: PORTC Position 10 | EPPI0 D18 | OSPI0
pull-up/pull-down1
D2
Notes: See note2
PC_11
PC_12
InOut
InOut
A
A
Programmable
None
None
None VDD_EXT Desc: PORTC Position 11 | EPPI0 D19 | OSPI0
pull-up/pull-down1
MOSI
Notes: See note2
Programmable
None VDD_EXT Desc: PORTC Position 12 | EPPI0 D20 | OSPI0
pull-up/pull-down1
MISO
Notes: See note2
Rev. PrD
|
Page 60 of 143
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May 2021
Preliminary Technical Data ADSP-21591/21593/21594/ADSP-SC591/SC592/SC594
Table 25. ADSP-2159x/ADSP-SC59x Designer Quick Reference (Continued)
Driver Internal
Reset
Reset Power
Signal Name
Type
Type Termination
Termination Drive Domain
Description and Notes
PC_13
InOut
A
A
A
Programmable
None
None
None
None VDD_EXT Desc: PORTC Position 13 | EPPI0 D21 | OSPI0
pull-up/pull-down1
D7
Notes: See note2
PC_14
PC_15
InOut
InOut
Programmable
None VDD_EXT Desc: PORTC Position 14 | EPPI0 D22 | OSPI0
pull-up/pull-down1
D6
Notes: See note2
Programmable
None VDD_EXT Desc: PORTC Position 15 | EPPI0 D23 | OSPI0
pull-up/pull-down1
D5
Notes: See note2
PD_00
PD_01
InOut
InOut
A
A
Programmable
None
None
None VDD_EXT Desc: PORTD Position 0 | OSPI0 D4
Notes: See note2
pull-up/pull-down1
Programmable
None VDD_EXT Desc: PORTD Position 1 | EPPI0 D06 | OSPI0
Slave Select Output 1
pull-up/pull-down1
Notes: See note2
PD_02
PD_03
InOut
InOut
A
A
Programmable
None
None
None VDD_EXT Desc: PORTD Position 2 | EMAC0 Carrier
Sense | SHARC2 Core Flag 10 | UART1 RTS
Notes: See note2
pull-up/pull-down1
Programmable
None VDD_EXT Desc: PORTD Position 3 | LP0 Acknowl-
edgment | SHARC1 Core Flag 11 | UART1 CTS
| EMAC0 PTP Aux Input 2
pull-up/pull-down1
Notes: See note2
PD_04
InOut
A
Programmable
None
None VDD_EXT Desc: PORTD Position 4 | EPPI0 D07 | OSPI0
pull-up/pull-down1
DQS | UART1 RX | TIMER0 Alternate Clock
Input 1
Notes: See note2
PD_05
PD_06
PD_07
PD_08
InOut
InOut
InOut
InOut
A
A
A
A
Programmable
None
None
None
None
None VDD_EXT Desc: PORTD Position 5 | EPPI0 D08 | UART1
TX | EMAC0 PTP Aux Input 1
pull-up/pull-down1
Notes: See note2
Programmable
None VDD_EXT Desc: PORTD Position 6 | EMAC0 Receive
pull-up/pull-down1
Error | UART0 CTS
Notes: See note2
Programmable
None VDD_EXT Desc: PORTD Position 7 | EMAC0 Collision
Detect | UART0 RTS
pull-up/pull-down1
Notes: See note2
Programmable
None VDD_EXT Desc: PORTD Position 8 | UART0 RX | TIMER0
Alternate Clock Input 0
pull-up/pull-down1
Notes: See note2
PD_09
PD_10
InOut
InOut
A
A
Programmable
None
None
None VDD_EXT Desc: PORTD Position 9 | UART0 TX
Notes: See note2
pull-up/pull-down1
Programmable
None VDD_EXT Desc: PORTD Position 10 | EPPI0 D09 | UART2
RX | TIMER0 Alternate Clock Input 2
pull-up/pull-down1
Notes: See note2
PD_11
PD_12
InOut
InOut
A
A
Programmable
None
None
None VDD_EXT Desc: PORTD Position 11 | EPPI0 D10 | UART2
pull-up/pull-down1
TX
Notes: See note2
Programmable
None VDD_EXT Desc:PORTDPosition12|EPPI0D11|TIMER0
pull-up/pull-down1
Timer 6 | UART2 RTS
Notes: See note2
Rev. PrD
|
Page 61 of 143
|
May 2021
ADSP-21591/21593/21594/ADSP-SC591/SC592/SC594 Preliminary Technical Data
Table 25. ADSP-2159x/ADSP-SC59x Designer Quick Reference (Continued)
Driver Internal
Reset
Reset Power
Signal Name
Type
Type Termination
Termination Drive Domain
Description and Notes
PD_13
InOut
A
Programmable
None
None
None VDD_EXT Desc:PORTDPosition13|EPPI0D12|TIMER0
Timer 7 | UART2 CTS
pull-up/pull-down1
Notes: See note2
PD_14
InOut
A
Programmable
None VDD_EXT Desc: PORTD Position 14 | EPPI0 D13 | LP1
Acknowledgment | SHARC2 Core Flag 9 |
TWI4 Clock
pull-up/pull-down1
Notes: See note2
PD_15
PE_00
PE_01
InOut
InOut
InOut
A
A
A
Programmable
None
None
None
None VDD_EXT Desc:PORTDPosition15|EPPI0D14|TIMER0
Timer 15 | TWI4 Data
pull-up/pull-down1
Notes: See note2
Programmable
None VDD_EXT Desc: PORTE Position 0 | EPPI0 D15 | SPI3
Slave Select Output 3 | TWI5 Clock
Notes: See note2
pull-up/pull-down1
Programmable
None VDD_EXT Desc: PORTE Position 1 | EPPI0 Frame Sync 1
| SPI3 Slave Select Output 4 | TWI5 Data |
TIMER0 Timer Alternate Clock 15
pull-up/pull-down1
Notes: See note2
PE_02
PE_03
InOut
InOut
A
A
Programmable
None
None
None VDD_EXT Desc: PORTE Position 2 | EPPI0 Frame Sync 2
| HADC0 MUX0 | SPI1 Slave Select Output 4 |
TWI0 Clock
pull-up/pull-down1
Notes: See note2
Programmable
None VDD_EXT Desc: PORTE Position 3 | EPPI0 Frame Sync 3
| HADC0 MUX2 | SPI2 Slave Select Output 3 |
TWI0 Data | TIMER0 Timer Alternate Clock 4
Notes: See note2
pull-up/pull-down1
PE_04
PE_05
PE_06
PE_07
PE_08
PE_09
PE_10
PE_11
InOut
InOut
InOut
InOut
InOut
InOut
InOut
InOut
A
A
A
A
A
A
A
A
Programmable
None
None
None
None
None
None
None
None
None VDD_EXT Desc: PORTE Position 4 | EPPI0 Clock | HADC0
pull-up/pull-down1
MUX1 | TWI2 Clock
Notes: See note2
Programmable
None VDD_EXT Desc: PORTE Position 5 | EPPI0 D00 | TWI2
pull-up/pull-down1
Data
Notes: See note2
Programmable
None VDD_EXT Desc: PORTE Position 6 | EPPI0 D01 | SHARC1
Core Flag 2 | TIMER0 Timer 8
pull-up/pull-down1
Notes: See note2
Programmable
None VDD_EXT Desc: PORTE Position 7 | EPPI0 D02 | SPI1
Ready | SHARC1 Core Flag 3 | TIMER0 Timer 9
Notes: See note2
pull-up/pull-down1
Programmable
None VDD_EXT Desc: PORTE Position 8 | EPPI0 D03 | TIMER0
pull-up/pull-down1
Timer 0
Notes: See note2
Programmable
None VDD_EXT Desc: PORTE Position 9 | EPPI0 D04 | TIMER0
Timer 1 | EMAC0 PTP Aux Input 3
pull-up/pull-down1
Notes: See note2
Programmable
None VDD_EXT Desc: PORTE Position 10 | EPPI0 D05 | SPI0
Slave Select Output 4 | TIMER0 Timer 2
Notes: See note2
pull-up/pull-down1
Programmable
None VDD_EXT Desc: PORTE Position 11 | EMAC1 Reference
Clock | SHARC2 Core Flag 7
pull-up/pull-down1
Notes: See note2
Rev. PrD
|
Page 62 of 143
|
May 2021
Preliminary Technical Data ADSP-21591/21593/21594/ADSP-SC591/SC592/SC594
Table 25. ADSP-2159x/ADSP-SC59x Designer Quick Reference (Continued)
Driver Internal
Reset
Reset Power
Signal Name
Type
Type Termination
Termination Drive Domain
Description and Notes
PE_12
InOut
A
A
A
A
A
A
Programmable
None
None
None
None
None
None
None VDD_EXT Desc: PORTE Position 12 | EMAC1 Transmit
Enable | SHARC1 Core Flag 8
pull-up/pull-down1
Notes: See note2
PE_13
PE_14
PE_15
PF_00
PF_01
InOut
InOut
InOut
InOut
InOut
Programmable
None VDD_EXT Desc: PORTE Position 13 | EMAC1 Transmit
Data D0 | SHARC2 Core Flag 13
pull-up/pull-down1
Notes: See note2
Programmable
None VDD_EXT Desc: PORTE Position 14 | EMAC1 Transmit
Data D1 | SPI2 Slave Select Output 7
Notes: See note2
pull-up/pull-down1
Programmable
None VDD_EXT Desc: PORTE Position 15 | EMAC1 Receive
Data D0 | SPI0 Slave Select Output 6
Notes: See note2
pull-up/pull-down1
Programmable
None VDD_EXT Desc:PORTFPosition0|EMAC1ReceiveData
D1 | SPI0 Slave Select Output 7 | SPI3 Ready
Notes: See note2
pull-up/pull-down1
Programmable
None VDD_EXT Desc: PORTF Position 1 | EMAC1 Serial
Management Bidirectional Data | SHARC1
Core Flag 7
pull-up/pull-down1
Notes: See note2
PF_02
PF_03
InOut
InOut
A
A
Programmable
None
None
None VDD_EXT Desc: PORTF Position 2 | EMAC1 Serial
Management Clock | SHARC1 Core Flag 6
Notes: See note2
pull-up/pull-down1
Programmable
None VDD_EXT Desc:PORTFPosition3|EMAC1CarrierSense
| SHARC1 Core Flag 10 | USBC0 USBC Stop
Output Control
pull-up/pull-down1
Notes: See note2
PF_04
PF_05
PF_06
InOut
InOut
InOut
A
A
A
Programmable
None
None
None
None VDD_EXT Desc: PORTF Position 4 | USBC0 USBC Data 7
| TIMER0 Timer Alternate Clock 13
pull-up/pull-down1
Notes: See note2
Programmable
None VDD_EXT Desc: PORTF Position 5 | MLB0 Clock Output
| USBC0 USBC Data 6 | TIMER0 Timer Clock
Notes: See note2
pull-up/pull-down1
Programmable
None VDD_EXT Desc: PORTF Position 6 | SPI1 Slave Select
pull-up/pull-down1
Output 7 | SHARC2 Core Flag 2 | USBC0 USBC
Data 5
Notes: See note2
PF_07
PF_08
InOut
InOut
A
A
Programmable
None
None
None VDD_EXT Desc: PORTF Position 7 | SPI3 Slave Select
pull-up/pull-down1
Output 2 | SHARC2 Core Flag 3 | USBC0 USBC
Data 4
Notes: See note2
Programmable
None VDD_EXT Desc: PORTF Position 8 | SPI3 Slave Select
Output 6 | SHARC2 Core Flag 8 | TIMER0 Timer
11 | USBC0 USBC Next Data Control
pull-up/pull-down1
Notes: See note2
PF_09
PF_10
InOut
InOut
A
A
Programmable
None
None
None VDD_EXT Desc: PORTF Position 9 | SHARC1 Core Flag 9
| USBC0 USBC Data Direction Control
Notes: See note2
pull-up/pull-down1
Programmable
None VDD_EXT Desc: PORTF Position 10 | SHARC2 Core Flag
4 | USBC0 USBC Data 3
pull-up/pull-down1
Notes: See note
Rev. PrD
|
Page 63 of 143
|
May 2021
ADSP-21591/21593/21594/ADSP-SC591/SC592/SC594 Preliminary Technical Data
Table 25. ADSP-2159x/ADSP-SC59x Designer Quick Reference (Continued)
Driver Internal
Reset
Reset Power
Signal Name
Type
Type Termination
Termination Drive Domain
Description and Notes
PF_11
InOut
A
A
A
A
A
A
A
Programmable
None
None
None
None
None
None
None
None VDD_EXT Desc: PORTF Position 11 | SHARC2 Core Flag
5 | USBC0 USBC Data 2
pull-up/pull-down1
Notes: See note2
PF_12
PF_13
PF_14
PF_15
PG_00
PG_01
InOut
InOut
InOut
InOut
InOut
InOut
Programmable
None VDD_EXT Desc: PORTF Position 12 | SHARC1 Core Flag
13 | USBC0 USBC Data 1
pull-up/pull-down1
Notes: See note2
Programmable
None VDD_EXT Desc: PORTF Position 13 | SHARC1 Core Flag
12 | USBC0 USBC Data 0
pull-up/pull-down1
Notes: See note2
Programmable
None VDD_EXT Desc: PORTF Position 14 | SHARC2 Core Flag
12 | USBC0 USBC Clock Signal
pull-up/pull-down1
Notes: See note2
Programmable
None VDD_EXT Desc: PORTF Position 15 | CANFD0 Receive |
TIMER0 Alternate Clock Input 4
pull-up/pull-down1
Notes: See note2
Programmable
None VDD_EXT Desc: PORTG Position 0 | CANFD0 Transmit |
TIMER0 Alternate Clock 10
pull-up/pull-down1
Notes: See note2
Programmable
None VDD_EXT Desc: PORTG Position 1 | CANFD1 Receive |
SPI2SlaveSelectOutput6|TIMER0Alternate
Clock Input 11
pull-up/pull-down1
Notes: See note2
PG_02
InOut
A
Programmable
None
None VDD_EXT Desc: PORTG Position 2 | CANFD1 Transmit |
SPI0 Slave Select Output 5
pull-up/pull-down1
Notes: See note2
PG_03
PG_04
InOut
InOut
A
A
Programmable
None
None
None VDD_EXT Desc: PORTG Position 3 | UART3 TX
Notes: See note2
pull-up/pull-down1
Programmable
None VDD_EXT Desc: PORTG Position 4 | UART3 RX | TIMER0
Alternate Clock Input 3
pull-up/pull-down1
Notes: See note2
PG_05
InOut
A
Programmable
None
None VDD_EXT Desc: PORTG Position 5 | SPI3 Clock | TIMER0
pull-up/pull-down1
Alternate Clock 11
Notes: See note2
PG_06
PG_07
InOut
InOut
A
A
Programmable
None
None
None VDD_EXT Desc: PORTG Position 6 | SPI3 MISO
Notes: See note2
pull-up/pull-down1
Programmable
None VDD_EXT Desc: PORTG Position 7 | SPI3 MOSI | TIMER0
pull-up/pull-down1
Alternate Clock 12
Notes: See note2
PG_08
PG_09
InOut
InOut
A
A
Programmable
None
None
None VDD_EXT Desc: PORTG Position 7 | SPI3 Slave Select
Output 1 | SPI3 Slave Select Input
pull-up/pull-down1
Notes: See note2
Programmable
None VDD_EXT Desc: PORTG Position 9 | SPI1 Slave Select
Output 6 | SHARC1 Core Flag14 | UART3 RTS
| TIMER0 Alternate Clock 1
pull-up/pull-down1
Notes: See note2
PG_10
InOut
A
Programmable
None
None VDD_EXT Desc: PORTG Position 10 | SHARC2 Core
pull-up/pull-down1
Flag14 | UART3 CTS | TIMER0 Alternate Clock
3
Notes: See note2
Rev. PrD
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Preliminary Technical Data ADSP-21591/21593/21594/ADSP-SC591/SC592/SC594
Table 25. ADSP-2159x/ADSP-SC59x Designer Quick Reference (Continued)
Driver Internal
Reset
Reset Power
Signal Name
Type
Type Termination
Termination Drive Domain
Description and Notes
PG_11
InOut
A
Programmable
None
None
None VDD_EXT Desc: PORTG Position 11 | SHARC2 Core Flag
pull-up/pull-down1
15
Notes: See note2
PG_12
PG_13
PG_14
InOut
InOut
InOut
A
Programmable
None VDD_EXT Desc: PORTG Position 12 | OSPI0 Slave Select
Output 3 | SPI2 Slave Select Output 4 |
SHARC2 Core Flag 11 | TIMER0 Timer 3
Notes: See note2
pull-up/pull-down1
A
A
Programmable
None
None
None VDD_EXT Desc: PORTG Position 13 | OSPI0 Slave Select
pull-up/pull-down1
Output 4 | SHARC1 CoreFlag 0|SHARC2 Core
Flag 6
Notes: See note2
Programmable
None VDD_EXT Desc: PORTG Position 14 | SPI0 Slave Select
Output 2 | TIMER0 Timer 10 | TIMER0
Alternate Clock Input 10
pull-up/pull-down1
Notes: See note2
PG_15
PH_00
InOut
InOut
A
A
Programmable
None
None
None VDD_EXT Desc: PORTG Position 15 | SPI2 Ready | SPI3
Slave Select Output 5 | TIMER0 Timer 11
Notes: See note2
pull-up/pull-down1
Programmable
None VDD_EXT Desc: PORTH Position 0 | SPI3 Slave Select
Output 7 | TIMER0 Timer 12 | TIMER0
Alternate Clock Input 12
pull-up/pull-down1
Notes: See note2
PH_01
PH_02
InOut
InOut
A
A
Programmable
None
None
None VDD_EXT Desc: PORTH Position 1 | SPI0 Ready | TIMER0
Timer 13 | TIMER0 Alternate Clock Input 13
Notes: See note2
pull-up/pull-down1
Programmable
None VDD_EXT Desc: PORTH Position 2 | SPI2 Slave Select
pull-up/pull-down1
Output 2 | SHARC1 Core Flag 1 | TIMER0 Timer
14
Notes: See note2
PH_03
PH_04
InOut
InOut
A
A
Programmable
None
None
None VDD_EXT Desc: PORTH Position 3 | EMAC0 Serial
Management Clock | TRACE0 Trace D08
Notes: See note2
pull-up/pull-down1
Programmable
None VDD_EXT Desc: PORTH Position 4 | EMAC0 Serial
Management Bidirectional Data | TRACE0
Trace D09
pull-up/pull-down1
Notes: See note2
PH_05
PH_06
PH_07
PH_08
InOut
InOut
InOut
InOut
A
A
A
A
Programmable
None
None
None
None
None VDD_EXT Desc: PORTH Position 5 | EMAC0 Receive
Data D0 | TRACE0 Trace D10
pull-up/pull-down1
Notes: See note2
Programmable
None VDD_EXT Desc: PORTH Position 6 | EMAC0 Receive
Data D1 | TRACE0 Trace D11
pull-up/pull-down1
Notes: See note2
Programmable
None VDD_EXT Desc: PORTH Position 7 | EMAC0 Receive
Reference Clock | TRACE0 Trace D12
Notes: See note2
pull-up/pull-down1
Programmable
None VDD_EXT Desc: PORTH Position 8 | EMAC0 Receive
Data Valid | TRACE0 Trace D13
pull-up/pull-down1
Notes: See note2
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ADSP-21591/21593/21594/ADSP-SC591/SC592/SC594 Preliminary Technical Data
Table 25. ADSP-2159x/ADSP-SC59x Designer Quick Reference (Continued)
Driver Internal
Reset
Reset Power
Signal Name
Type
Type Termination
Termination Drive Domain
Description and Notes
PH_09
InOut
A
A
A
A
A
A
A
A
A
A
A
Programmable
None
None
None
None
None
None
None
None
None
None
None
None VDD_EXT Desc: PORTH Position 9 | EMAC0 Transmit
Data D0 | TRACE0 Trace D14
pull-up/pull-down1
Notes: See note2
PH_10
PH_11
PH_12
PH_13
PH_14
PH_15
PI_00
InOut
InOut
InOut
InOut
InOut
InOut
InOut
InOut
InOut
InOut
Programmable
None VDD_EXT Desc: PORTH Position 10 | EMAC0 Transmit
Data D1 | TRACE0 Trace D15
pull-up/pull-down1
Notes: See note2
Programmable
None VDD_EXT Desc: PORTH Position 11 | EMAC0 Receive
pull-up/pull-down1
Data D2
Notes: See note2
Programmable
None VDD_EXT Desc: PORTH Position 12 | EMAC0 Receive
pull-up/pull-down1
Data D3
Notes: See note2
Programmable
None VDD_EXT Desc: PORTH Position 13 | EMAC0 Transmit
pull-up/pull-down1
Enable
Notes: See note2
Programmable
None VDD_EXT Desc: PORTH Position 14 | EMAC0 Transmit
pull-up/pull-down1
Clock
Notes: See note2
Programmable
None VDD_EXT Desc: PORTH Position 15 | EMAC0 Transmit
pull-up/pull-down1
Data D2
Notes: See note2
Programmable
None VDD_EXT Desc: PORTI Position 0 | EMAC0 Transmit
pull-up/pull-down1
Data D3
Notes: See note2
PI_01
Programmable
None VDD_EXT Desc: PORTI Position 1 | EMAC0 PTP Clock
Input 0 | SHARC2 Core Flag 0 | TWI3 Clock
Notes: See note2
pull-up/pull-down1
PI_02
Programmable
None VDD_EXT Desc: PORTI Position 2 | EMAC0 PTP Aux
Input 0 | SHARC2 Core Flag 1 | TWI3 Data
Notes: See note2
pull-up/pull-down1
PI_03
Programmable
None VDD_EXT Desc: PORTI Position 3 | EMAC0 Pulse Per
pull-up/pull-down1
Second Output | SHARC1 Core Flag 4 | TWI1
Clock
Notes: See note2
PI_04
PI_05
InOut
InOut
A
A
Programmable
None
None
None VDD_EXT Desc: PORTI Position 4 | EMAC0 Pulse Per
pull-up/pull-down1
Second Output | SHARC1 Core Flag 5 | TWI1
Data
Notes: See note2
Programmable
None VDD_EXT Desc: PORTI Position 5 | EMAC0 Pulse Per
Second Output | OSPI0 Slave Select Output
2 | SHARC1 Core Flag 15 | TIMER0 Alternate
Clock 2
pull-up/pull-down1
Notes: See note2
PI_06
InOut
A
Programmable
None
None VDD_EXT Desc: PORTI Position 6 | EMAC0 Pulse Per
Second Output | TIMER0 Alternate Clock 14
Notes: See note2
pull-up/pull-down1
SYS_BMODE0
SYS_BMODE1
Input NA
Input NA
None
None
None
None
None VDD_EXT Desc: Boot Mode Control 0
Notes: Cannot be left unconnected
None VDD_EXT Desc: Boot Mode Control 1
Notes: Cannot be left unconnected
Rev. PrD
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ADSP-21591/21593/21594/ADSP-SC591/SC592/SC594
Preliminary Technical Data
Table 25. ADSP-2159x/ADSP-SC59x Designer Quick Reference (Continued)
Driver Internal
Reset
Reset Power
Signal Name
Type
Type Termination
Termination Drive Domain
Description and Notes
SYS_BMODE2
Input NA
None
None
None
None
None
None
None
None
None
None
None VDD_EXT Desc: Boot Mode Control 2
Notes: Cannot be left unconnected
SYS_CLKIN0
SYS_CLKIN1
SYS_CLKOUT
SYS_FAULT
a
a
NA
NA
None VDD_REF Desc: Clock/Crystal Input
Notes: Cannot be left unconnected
None VDD_REF Desc: Clock/Crystal Input
Notes: Cannot be left unconnected
Output A
L
VDD_EXT Desc: Processor Clock Output
Notes: No notes
InOut
InOut
A
A
None VDD_EXT Desc: Active-High Fault Output
Notes: External pull-down required to keep
signal in deasserted state
SYS_FAULT
None
None
None VDD_EXT Desc: Active-Low Fault Output
Notes: External pull-up required to keep
signal in deasserted state
SYS_HWRST
SYS_RESOUT
SYS_XTAL0
Input NA
Output A
None
None
None
None
None
None
None VDD_EXT Desc: Processor Hardware Reset Control
Notes: Cannot be left unconnected
L
VDD_EXT Desc: Reset Output
Notes: No notes
a
a
NA
None VDD_REF Desc: Crystal Output
Notes: Leave unconnected if an oscillator
provides SYS_CLKIN0
SYS_XTAL1
None
None
None VDD_REF Desc: Crystal Output
Notes: Leave unconnected if an oscillator
provides SYS_CLKIN1
VDD_ANA
VDD_DMC
VDD_EXT
s
s
s
s
s
s
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
Desc: Analog VDD
Notes: No notes
Desc: DMC VDD
Notes: No notes
Desc: External Voltage Domain
Notes: No notes
VDD_INT
Desc: Internal Voltage Domain
Notes: No notes
VDD_PLL
Desc: PLL VDD
Notes: No notes
VDD_REF
Desc: External Voltage Domain
Notes: No notes
1 Disabled by default.
2 When present, the internal pull-up/pull-down design holds the internal path from the pins at the expected logic levels. To pull up or pull down the external pads to the expected
logic levels, use external resistors.
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ADSP-21591/21593/21594/ADSP-SC591/SC592/SC594
PRELIMINARY SPECIFICATIONS
Preliminary Technical Data
Specifications are subject to change without notice. For information about product specifications, contact your Analog Devices, Inc.,
representative.
PRELIMINARY OPERATING CONDITIONS
Parameter
Conditions
Min
Nominal
Max
Unit
VDD_INT
VDD_EXT
VDD_ANA
Internal (Core) Supply Voltage
External (I/O) Supply Voltage
Analog Power Supply Voltage
DDR3L Controller Supply Voltage
DDR3 Controller Supply Voltage
External (I/O) Reference Supply Voltage
DDR3 Reference Voltage
600 MHz ≤ CCLK ≤ 1 GHz 0.95
1.00
3.30
1.80
1.350
1.500
1.80
1.05
3.47
1.89
1.418
1.575
1.89
V
V
V
V
V
V
V
V
V
V
V
V
V
V
3.13
1.71
1
VDD_DMC
1.283
1.425
1.71
2
VDD_REF
3
VDDR_VREF
0.49 × VDD_DMC
0.50 × VDD_DMC 0.51 × VDD_DMC
+1.89
4
VDELTA_EXT_REF (VDD_EXT – VDD_REF) and (VDD_EXT – VDD_ANA
)
–1.89
5
VHADC_REF
HADC Reference Voltage
HADC Input Voltage
1.71
1.80
VDD_ANA
VHADC0_VINx
0
VHADC_REF + 0.09
6
VIH
High Level Input Voltage
High Level Clock Input Voltage
Low Level Input Voltage
Low Level Clock Input Voltage
Low Level Input Voltage
Low Level Input Voltage
High Level Input Voltage
High Level Input Voltage
VDD_EXT = 3.47 V
VDD_EXT = 3.13 V
2.0
2
VIHCLKIN
0.65 × VDD_REF
VDD_REF
6
VIL
0.8
2
VILCLKIN
–0.30
+0.35 × VDD_REF
7
VIL_DDR3L
VDD_DMC = 1.283 V
VDD_DMC = 1.425 V
VDD_DMC = 1.418 V
VDD_DMC = 1.575 V
VDDR_VREF – 0.175 V
7
VIL_DDR3
VDDR_VREF – 0.175 V
7
VIH_DDR3L
VDDR_VREF + 0.175
VDDR_VREF + 0.175
V
V
7
VIH_DDR3
CONSUMER GRADE
TJ Junction Temperature
400-Ball BGA_ED
INDUSTRIAL GRADE
TJ Junction Temperature
400-Ball BGA_ED
AUTOMOTIVE GRADE8
TJ Junction Temperature
400-Ball BGA_ED
0
110
°C
–40
–40
+125
+125
°C
°C
1 Applies to DDR3L/DDR3 signals.
2 Applies to SYS_CLKIN0 pin.
3 Applies to DMC0_VREF0 and DMC0_VREF1 pins.
4 See Figure 9.
5 VHADC_VREF must always be less than VDD_ANA
.
6 Parameter value applies to all input and bidirectional pins except the DMC pins.
7 This parameter applies to all DMC0 pins.
8 Automotive application use profile only. Not supported for nonautomotive use. Contact Analog Devices for more information.
Rev. PrD
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ADSP-21591/21593/21594/ADSP-SC591/SC592/SC594
Preliminary Technical Data
Preliminary Clock Related Operating Conditions
Table 26 describes the core clock, system clock, and peripheral clock timing requirements. The data presented in the table applies to all
speed grades except where noted.
Table 26. Preliminary Clock Operating Conditions
Parameter
fCCLK
Conditions
Min
600
300
30
Typ
Max
1000
500
Unit
MHz
MHz
MHz
Core Clock (CCLK) Frequency
SYSCLK Frequency1
fCCLK = 2 × fSYSCLK
fSYSCLK
fSCLK0
SCLK0 Frequency
fSYSCLK = N × fSCLK0
125
where N = 2 or 4 or 6
fSCLK1
fDCLK
SCLK1 Frequency
DDR3 Clock (DCLK) Frequency2
fSYSCLK ≥ fSCLK1
250
800
MHz
MHz
All combinations are supported 300
except for:
[fCCLK > 800 MHz and Tj < 0°C and
fCCLK:fDCLK = 2:1]
fOCLK
Output Clock (OCLK) Frequency3
125
MHz
%
fSYS_CLKOUTJ SYS_CLKOUT Period Jitter4, 5
fLCLKTPROG Programmed Link Port Transmit Clock
fLCLKREXT
External Link Port Receive Clock6, 7
2
125
125
62.5
MHz
MHz
MHz
fLCLKREXT ≤ fOCLK_0
fSPTCLKPROG Programmed SPT Clock When Transmitting Data
and Frame Sync
fSPTCLKPROG Programmed SPT Clock When Receiving Data or
Frame Sync
31.25
62.5
MHz
MHz
MHz
fSPTCLKEXT
External SPT Clock When Receiving Data and
Frame Sync6, 7
fSPTCLKEXT ≤ fSCLK0
fSPTCLKEXT ≤ fSCLK0
fSPTCLKEXT
External SPT Clock Transmitting Data or
Frame Sync6, 7
31.25
fSPICLKPROG Programmed SPI Clock When Transmitting Data
fSPICLKPROG Programmed SPI Clock When Receiving Data
fSPICLKPROG Programmed SPI Clock When Transmitting Data
fSPICLKPROG Programmed SPI Clock When Receiving Data
fSPICLK:fSCLK0 ratio = 1:1
fSPICLK:fSCLK0 ratio = 1:1
fSPICLK:fSCLK0 ratio = 1:2
fSPICLK:fSCLK0 ratio = 1:2
fSPICLKEXT ≤ fCDU_CLKO0
fSPICLKEXT ≤ fCDU_CLKO0
fTMRCLKEXT ≤ fSCLK0 / 4
75
MHz
MHz
MHz
MHz
MHz
MHz
MHz
75
62.5
62.5
62.5
45
fSPICLKEXT
fSPICLKEXT
fTMRCLKEXT
External SPI Clock When Receiving Data6, 7
External SPI Clock When Transmitting Data6, 7
External Timer Clock (TMx_CLK)
31.25
1 When using MLB, there is a requirement that the fSYSCLK value must be a minimum of 100 MHz for 3-pin mode and for all supported speeds.
2 To ensure proper operation of the DDR3/3L, all the DDR3/3L guidelines must be strictly followed. SeeADSP-2159x Board Design Guidelines for Dynamic Memory Controller
(EE-TBD).
3 fOCLK must not exceed fSCLK0 when selected as SYS_CLKOUT.
4 SYS_CLKOUT jitter is dependent on the application system design including pin switching activity, board layout, and the jitter characteristics of the SYS_CLKIN source. Due
to the dependency on these factors, the measured jitter may be higher or lower than this typical specification for each end application.
5 The value in the Typ field is the percentage of the SYS_CLKOUT period.
6 The maximum achievable frequency for any peripheral in external clock mode is dependent on being able to meet the setup and hold times in the ac timing specifications
section for that peripheral.
7 The peripheral external clock frequency must also be less than or equal to the frequency that clocks the peripheral.
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ADSP-21591/21593/21594/ADSP-SC591/SC592/SC594
Preliminary Technical Data
Table 27. Preliminary Phase-Locked Loop (PLL) Operating Conditions
Parameter
Min
Max
Unit
fPLLCLK
PLL Clock Frequency
1.20
2.00
GHz
CCLK
CSEL
SYSCLK
SCLK0
SYSSEL
S0SEL
PLLCLK
PLL
SYS_CLKIN
S1SEL
DCLK
DSEL
OSEL
SCLK1
S1SELEX
OUTCLK
S1SELEXEN
REFER TO THE ADSP-2159x/ADSP-SC591/592/594 SHARC+ PROCESSOR HARDWARE REFERENCE
FOR INFORMATION ABOUT ALLOWED DIVIDER VALUES AND PROGRAMMING MODELS.
Figure 7. Clock Relationships and Divider Values
Rev. PrD
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ADSP-21591/21593/21594/ADSP-SC591/SC592/SC594
Preliminary Technical Data
PRELIMINARY ELECTRICAL CHARACTERISTICS
Parameter
Conditions
Min
Typ
Max
Unit
VOH
High Level Output Voltage
Low Level Output Voltage
VDD_EXT = minimum,
2.4
V
(IOH = –2.0 mA, DS1)1, (IOH = –4.0 mA, DS2)2
VOL
VDD_EXT = minimum,
0.4
V
(IOL = 2.0 mA, DS1)1, (IOL = 4.0 mA, DS2)2
3
VOH_XTAL
High Level Output Voltage
Low Level Output Voltage
VDD_REF = minimum, IOH = –1.0 mA
VDD_REF = minimum, IOL = 1.0 mA
1.26
V
V
V
3
VOL_XTAL
0.45
0.32
4
VOH_DDR3L High Level Output Voltage for VDD_DDR = minimum, IOH = –1.0 mA
0.963
DDR3L Drive Strength =100 Ω
4
VOL_DDR3L
Low Level Output Voltage for VDD_DDR = minimum, IOL = 1.0 mA
DDR3L Drive Strength =100 Ω
V
V
V
5
VOH_DDR3
High Level Output Voltage for VDD_DDR = minimum, IOH = –1.0 mA
DDR3 Drive Strength = 100 Ω
1.105
5
VOL_DDR3
Low Level Output Voltage for VDD_DDR = minimum, IOL = 1.0 mA
DDR3 Drive Strength = 100 Ω
0.32
6
IIH
High Level Input Current
Low Level Input Current
VDD_EXT = maximum, VIN = VDD_EXT maximum
VDD_EXT = maximum, VIN = 0 V
10
μA
μA
μA
6
IIL
10
7
IIL_PU
Low Level Input Current
Pull-Up
VDD_EXT = maximum, VIN = 0 V
200
8
IIH_PD
High Level Input Current
Pull-Down
VDD_EXT = maximum, VIN = VDD_EXT maximum
200
10
μA
μA
9
IOZH
Three-State Leakage Current VDD_EXT/VDD_DDR = maximum,
VIN = VDD_EXT/VDD_DDR maximum
9
IOZL
Three-State Leakage Current VDD_EXT/VDD_DDR = maximum, VIN = 0 V
10
5
μA
pF
10
CIN
Input Capacitance
TJ = 25°C
IDD_IDLE
VDD_INT Current in Idle
fCCLK = 1000 MHz
ASFSHARC = 0.35
TBD
mA
f
SYSCLK = 500 MHz
fSCLK0 = 125 MHz
SCLK1 = 250 MHz
f
(Other clocks are disabled)
No peripheral or DMA activity
TJ = 25°C
VDD_INT = 1.0 V
IDD_TYP
VDD_INT Current
fCCLK = 1000 MHz
ASFSHARC = 1.0
TBD
mA
f
SYSCLK = 500 MHz
fSCLK0 = 125 MHz
SCLK1 = 250 MHz
f
(Other clocks are disabled)
DMA data rate = 456 MB/s
TJ = 25°C
VDD_INT = 1.0 V
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ADSP-21591/21593/21594/ADSP-SC591/SC592/SC594
Preliminary Technical Data
Parameter
Conditions
Min
Typ
Max
Unit
IDD_IDLE
VDD_INT Current in Idle
fCCLK = 800 MHz
ASFSHARC = 0.35
TBD
mA
f
SYSCLK = 400 MHz
fSCLK0 = 100 MHz
SCLK1 = 228.6 MHz
f
(Other clocks are disabled)
No peripheral or DMA activity
TJ = 25°C
VDD_INT = 1.0 V
IDD_TYP
IDD_IDLE
IDD_TYP
VDD_INT Current
fCCLK = 800 MHz
ASFSHARC = 1.0
TBD
TBD
TBD
mA
mA
mA
f
SYSCLK = 400 MHz
fSCLK0 = 100 MHz
SCLK1 = 228.6 MHz
f
(Other clocks are disabled)
DMA data rate = 456 MB/s
TJ = 25°C
VDD_INT = 1.0 V
VDD_INT Current in Idle
fCCLK = 600 MHz
ASFSHARC = 0.35
f
SYSCLK = 300 MHz
fSCLK0 = 75 MHz
SCLK1 = 240 MHz
f
(Other clocks are disabled)
No peripheral or DMA activity
TJ = 25°C
VDD_INT = 1.0 V
VDD_INT Current
fCCLK = 600 MHz
ASFSHARC = 1.0
f
SYSCLK = 300 MHz
fSCLK0 = 75 MHz
SCLK1 = 240 MHz
f
(Other clocks are disabled)
DMA data rate = 456 MB/s
TJ = 25°C
VDD_INT = 1.0 V
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ADSP-21591/21593/21594/ADSP-SC591/SC592/SC594
Preliminary Technical Data
Parameter
Conditions
Min
Typ
Max
Unit
IDD_IDLE
VDD_INT Current in Idle
fCCLK = 400 MHz
ASFSHARC = 0.35
TBD
mA
f
SYSCLK = 200 MHz
fSCLK0 = 100 MHz
SCLK1 = 250 MHz
f
(Other clocks are disabled)
No peripheral or DMA activity
TJ = 25°C
VDD_INT = 1.0 V
IDD_TYP
VDD_INT Current
fCCLK = 400 MHz
ASFSHARC = 1.0
TBD
mA
f
SYSCLK = 200 MHz
fSCLK0 = 100 MHz
SCLK1 = 250 MHz
f
(Other clocks are disabled)
DMA data rate = 456 MB/s
TJ = 25°C
VDD_INT = 1.0 V
11
IDD_INT
VDD_INT Current
fCCLK 0 MHz
IDD_INT_TOT
mA
fSCLK0/1 0 MHz
See equation in
the Total
Internal Power
Dissipation
section.
1 Applies to all output and bidirectional pins operating at less than or equal to 62.5 MHz, except DMC and SYS_XTAL0.
2 Applies to all output and bidirectional pins operating above 62.5 MHz and less than or equal to 125 MHz, except DMC.
3 Applies to SYS_XTAL0 pin.
4 Applies to all DMC output and bidirectional signals in DDR3L mode.
5 Applies to all DMC output and bidirectional signals in DDR3 mode.
6 Applies to input pins: SYS_BMODE2-0, SYS_CLKIN, and SYS_HWRST.
7 Applies to input pins with internal pull-ups: JTG_TDI, JTG_TMS, and JTG_TCK.
8 Applies to JTAG_TRST signal.
9 Applies to signals: PA15 to PA0, PB15 to PB0, PC7 to PC0, DAI0_PINx, DAI1_PINx, DMC0_DQx, DMC0_LDQS, DMC0_UDQS, DMC0_LDQS, DMC0_UDQS,
SYS_FAULT, and JTG_TDO.
10Applies to all signal pins.
11See Estimating Power for ADSP-2159x/SC59x SHARC+ Processors (EE-TBD) for further information.
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ADSP-21591/21593/21594/ADSP-SC591/SC592/SC594 Preliminary Technical Data
Application Dependent Current
Total Internal Power Dissipation
Total power dissipation has two components:
• Static, including leakage current
The application dependent currents include the dynamic cur-
rent in the core clock domain of the SHARC+ core, as well as
the dynamic current in the accelerator block.
• Dynamic, due to transistor switching characteristics for
each clock domain
Dynamic current consumed by the core is subject to an activity
scaling factor (ASF) that represents application code running on
the processor core (see Table 29). The ASF is combined with the
CCLK frequency and VDD_INT dependent dynamic current data
in Table 30 to calculate this portion of the total dynamic power
dissipation component.
Many operating conditions can also affect power dissipation,
including temperature, voltage, operating frequency, and pro-
cessor activity. The following equation describes the internal
current consumption.
I
DD_INT_TOT = IDD_INT_STATIC + IDD_INT_CCLK_SHARC_DYN
DD_INT_DCLK_DYN + IDD_INT_SYSCLK_DYN
+
I
DD_INT_CCLK_SHARC_DYN = Table 30 × ASFSHARC
I
+
+
Table 29. Activity Scaling Factors for the SHARC+® Core
(ASFSHARC
I
I
DD_INT_SCLK0_DYN + IDD_INT_SCLK1_DYN
DD_INT_OCLK_DYN + IDD_INT_ACCL_DYN
+
)
IDD_INT_DMA_DR_DYN
IDD_INT Power Vector
IDD-LS
ASF
TBD
TBD
TBD
TBD
TBD
TBD
TBD
where IDD_INT_STATIC is the sole contributor to the static power
dissipation component and is specified as a function of voltage
(VDD_INT) and junction temperature (TJ) in Table 28.
IDD-IDLE
IDD-NOP
Table 28. Static Current—IDD_INT_STATIC (mA)
IDD-TYP_3070
IDD-TYP_5050
IDD-TYP_7030
IDD-PEAK_100
Voltage (VDD_INT
1.00 V
TBD
)
TJ (°C)
–45
0.95 V
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
1.05 V
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
–40
TBD
–20
TBD
Table 30. Dynamic Current for SHARC+®Core
(mA, with ASF = 1.00)
–10
TBD
0
TBD
Voltage (VDD_INT
)
+10
+25
+40
+55
+70
+85
+100
+105
+115
+125
TBD
fCCLK (MHz)
0.95 V
1.00 V 1.05 V
TBD
400
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
450
500
550
600
650
700
750
800
850
900
950
1000
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
The other eight addends in the IDD_INT_TOT equation comprise
the dynamic power dissipation component and fall into four
broad categories: application dependent currents, clock cur-
rents, currents from high speed peripheral operation, and data
transmission currents.
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Preliminary Technical Data ADSP-21591/21593/21594/ADSP-SC591/SC592/SC594
Clock Current
HADC DC Accuracy
The dynamic clock currents provide the total power dissipated
by all transistors switching in the clock paths. The power dissi-
pated by each clock domain is dependent on voltage (VDD_INT),
operating frequency, and a unique scaling factor.
Table 32. HADC DC Accuracy for BGA_ED1
Parameter
Typ
Unit2
Bits
Bits
Bits
LSB
LSB
LSB
LSB
LSB
LSB
Resolution
TBD
IDD_INT_SYSCLK_DYN (mA) = 0.626 × fSYSCLK (MHz) ×
VDD_INT (V)
No Missing Codes (NMC) – Unrestricted
TBD
No Missing Codes (NMC) – Pin Restrictions3 TBD
I
I
DD_INT_SCLK0_DYN (mA) = 0.23 × fSCLK0 (MHz) × VDD_INT (V)
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
Offset Error
TBD
TBD
TBD
TBD
TBD
TBD
DD_INT_SCLK1_DYN (mA) = 0.018 × fSCLK1 (MHz) ×
V
DD_INT (V)
I
I
DD_INT_DCLK_DYN (mA) = 0.125 × fDCLK (MHz) × VDD_INT (V)
DD_INT_OCLK_DYN (mA) = 0.048 × fOCLK (MHz) × VDD_INT (V)
Offset Error Matching
Gain Error
Gain Error Matching
Data Transmission Current
1 See the Preliminary Operating Conditions section for the HADC0_VINx
specification.
The data transmission current represents the power dissipated
when moving data throughout the system via DMA. This cur-
rent is proportional to the data rate. Refer to the power
calculator available with Estimating Power for ADSP-
2159x/SC59x SHARC+ Processors (EE-TBD) to estimate
2 LSB = HADC0_VREFP ÷ 512.
3 Pin restrictions required: pins DAI18, DAI19, and DAI20 must be programmed
to inputs and a static (non-switching) signal applied to the pins.
I
DD_INT_DMA_DR_DYN based on the bandwidth of the data
HADC Timing Specifications
transfer.
Table 33. HADC Timing Specifications
HADC
Parameter
Typ
Max
Unit
μs
HADC Electrical Characteristics
Conversion Time1
Throughput Range
TWAKEUP
TBD
TBD
TBD
MSPS
Table 31. HADC Electrical Characteristics
μs
Parameter
Conditions
Typ Unit
1 Refer to the ADSP-2159x/ADSP-SC591/592/594 SHARC+ Processor Hardware
Reference for additional information about TSAMPLE
IDD_HADC_IDLE
Current consumption on
VDD_HADC
TBD mA
.
HADC is powered on, but not
converting
IDD_HADC_ACTIVE
Current consumption on
VDD_HADC during a conversion
TBD mA
TBD μA
IDD_HADC_POWERDOWN Current consumption on
VDD_HADC
Analog circuitry of the HADC is
powered down
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ADSP-21591/21593/21594/ADSP-SC591/SC592/SC594 Preliminary Technical Data
Table 37. Maximum Duty Cycle for Input Transient Voltage
for VDD_INT and VDD_EXT
TMU
TMU Characteristics
VDD_INT (V)1
1.120
VDD_EXT (V)1
Maximum Duty Cycle2
Table 34. TMU Characteristics
5%
1.103
10%
20%
30%
50%
75%
100%
Parameter
Resolution
Accuracy
Typ
TBD
TBD
Unit
°C
1.086
1.077
°C
1.065
Table 35. TMU Gain and Offset
1.056
1.050
3.470
Junction Temperature Range TMU_GAIN
TBD
TMU_OFFSET
1 The individual values cannot be combined for analysis of a single instance of
overshoot or undershoot. The worst case observed value must fall within one of
the voltages specified and the total duration of the overshoot or undershoot
(exceeding the 100% case) must be less than or equal to the corresponding duty
cycle.
Contact Analog Devices, Inc.
ABSOLUTE MAXIMUM RATINGS
Stresses at or above those listed in Table 36 may cause perma-
nent damage to the product. This is a stress rating only;
functional operation of the product at these or any other condi-
tions above those indicated in the operational section of this
specification is not implied. Operation beyond the maximum
operating conditions for extended periods may affect product
reliability.
2 Duty cycle refers to the percentage of time the signal exceeds the value for the
100% case. This is equivalent to the measured duration of a single instance of
overshoot or undershoot as a percentage of the period of occurrence.
Table 38. Maximum Duty Cycle for Input Transient Voltage
3.3 V VIN Max (V)1 1.8 V VIN Max (V)1 Maximum Duty Cycle2
3.47
1.89
100%
1 The individual values cannot be combined for analysis of a single instance of
overshoot or undershoot. The worst case observed value must fall within one of
the voltages specified and the total duration of the overshoot or undershoot
(exceeding the 100% case) must be less than or equal to the corresponding duty
cycle.
Table 36. Absolute Maximum Ratings
Parameter
Rating
Internal (Core) Supply Voltage
–0.3 V to +1.05 V
2 Duty cycle refers to the percentage of time the signal exceeds the value for the
100% case. This is equivalent to the measured duration of a single instance of
overshoot or undershoot as a percentage of the period of occurrence.
(VDD_INT
External (I/O) Supply Voltage
(VDD_EXT
External (I/O) Reference Supply
Voltage (VDD_REF
)
–0.3 V to +3.47 V
–0.3 V to +1.89 V
–1.89 V to +1.89 V
–0.3 V to +1.60 V
–0.3 V to +1.89 V
)
ESD CAUTION
)
(VDD_EXT – VDD_REF) and
(VDD_EXT – VDD_ANA) (VDELTA_EXT_REF
)
ESD (electrostatic discharge) sensitive device.
Charged devices and circuit boards can discharge
without detection. Although this product features
patented or proprietary protection circuitry, damage
may occur on devices subjected to high energy ESD.
Therefore, proper ESD precautions should be taken to
avoid performance degradation or loss of functionality.
DDR3 Controller Supply Voltage
(VDD_DMC
)
Analog Supply Voltage (VDD_ANA
)
HADC Reference Voltage (VHADC_REF) –0.3 V to +1.89 V
DDR3 Input Voltage1
–0.3 V to +1.60 V
Digital Input Voltage1, 2
TWI Input Voltage1, 3
–0.3 V to +3.47 V
–0.3 V to +3.47 V
Output Voltage Swing
Analog Input Voltage4
IOH/IOL Current per Signal2
Storage Temperature Range
–0.3 V to VDD_EXT +0.5 V
–0.2 V to VDD_ANA +0.09 V
6 mA (maximum)
–65C to +150C
Junction Temperature While Biased 125C
1 Applies only when the related power supply (VDD_DMC or VDD_EXT) is within
specification. When the power supply is below specification, the range is the
voltage being applied to that power domain 0.2 V.
2 Applies to 100% transient duty cycle.
3 Applies to TWI_SCL and TWI_SDA.
4 Applies only when VDD_ANA is within specifications and ≤ 1.8 V. When VDD_ANA
is within specifications and > 1.8 V, the maximum rating is 1.89 V. When
V
DD_ANA is below specifications, the range is VDD_ANA 0.09 V.
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ADSP-21591/21593/21594/ADSP-SC591/SC592/SC594
Preliminary Technical Data
TIMING SPECIFICATIONS
Power-Up Reset Timing
Table 39 and Figure 8 show the relationship between power supply startup and processor reset timing, as relating to the clock generation
unit (CGU) and the reset control unit (RCU).
In Figure 8, the VDD_SUPPLIES are VDD_INT, VDD_EXT, VDD_DMC, VDD_REF, and VDD_ANA. The VDELTA_EXT_REF specification must be met at
all times, including during power-up reset and when powering down the device (Figure 9).
Table 39. Power-Up Reset Timing
All specifications are based on simulation data and are subject to change without notice.
Parameter
Min
Max
Unit
Timing Requirement
tRST_IN_PWR
SYS_HWRST Deasserted after VDD_SUPPLIES (VDD_INT, VDD_EXT, VDD_DMC, VDD_REF
,
11 × tCKIN
ns
VDD_ANA) and SYS_CLKIN0 are Stable and Within Specification
SYS_HWRST
tRST_IN_PWR
SYS_CLKIN0
V
DD_SUPPLIES
Figure 8. Power-Up Reset Timing
V
DD_EXT
V
DD_EXT
ޤ
V AND VDD_EXT
ޤ
V DD_REF
MUST NOT EXCEED V
DD_ANA
AT ANY TIME.
DELTA_EXT_REF
V
DD_REF,
V
DD_ANA
0V
POWER-UP
OPERATIONAL
POWER-DOWN
Figure 9. Power-Up and Power-Down Voltage Delta Requirement
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ADSP-21591/21593/21594/ADSP-SC591/SC592/SC594
Preliminary Technical Data
Clock and Reset Timing
Table 40 and Figure 10 describe clock and reset operations related to the CGU and RCU. Per the CCLK, SYSCLK, SCLKx, DCLK, and
OCLK timing specifications in Table 26 (Clock Operating Conditions), combinations of SYS_CLKIN0 and clock multipliers must not
select clock rates in excess of the maximum instruction rate of the processor.
Table 40. Clock and Reset Timing
All specifications are based on simulation data and are subject to change without notice.
Parameter
Min
Max
Unit
Timing Requirements
fCKIN
SYS_CLKIN0 Frequency (Crystal)1, 2
SYS_CLKIN0 Frequency (External SYS_CLKIN0)1, 2
SYS_CLKIN0 Low Pulse1
SYS_CLKIN0 High Pulse1
RESET Asserted Pulse Width Low3
20
30
30
MHz
MHz
ns
20
tCKINL
tCKINH
tWRST
16.67
16.67
11 × tCKIN
ns
ns
1 Applies to PLL bypass mode and PLL nonbypass mode.
2 The tCKIN period (see Figure 10) equals 1/fCKIN
.
3 Applies after power-up sequence is complete. See Table 39 and Figure 8 for power-up reset timing.
fCKIN
SYS_CLKIN0
tCKINL
tCKINH
tWRST
SYS_HWRST
Figure 10. Clock and Reset Timing
Dynamic Memory Controller (DMC)—Clock, Control, Write and Read Cycle Timing
The DMC clock, control, write and read timings comply with the JEDEC standards. To ensure proper operation of the DDR3/3L, all
DDR3/3L guidelines must be strictly followed. See ADSP-2159x Board Design Guidelines for Dynamic Memory Controller (EE-TBD).
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ADSP-21591/21593/21594/ADSP-SC591/SC592/SC594
Preliminary Technical Data
Link Ports (LPs)
In LP receive mode, the LP clock is supplied externally and is called fLCLKREXT, therefore the period can be represented by
1
tLCLKREXT
=
---------------
fLCLKREXT
In LP transmit mode, the programmed LP clock (fLCLKTPROG) frequency in megahertz is set by the following equation where VALUE is a
field in the LP_DIV register that can be set from 1 to 255:
fOCLK_0
VALUE 2
fLCLKTPROG
=
---------------------
In the case where VALUE = 0, fLCLKTPROG = fOCLK_0. For all settings of VALUE, the following equation is true:
1
tLCLKTPROG
=
------------------
fLCLKTPROG
Calculation of the link receiver data setup and hold relative to the link clock is required to determine the maximum allowable skew that
can be introduced in the transmission path length difference between LPx_Dx and LPx_CLK. Setup skew is the maximum delay that can
be introduced in LPx_Dx relative to LPx_CLK (setup skew = tLCLKTWH minimum – tDLDCH – tSLDCL). Hold skew is the maximum delay
that can be introduced in LPx_CLK relative to LPx_Dx (hold skew = tLCLKTWL minimum – tHLDCH – tHLDCL). See Table 42 for LP transmit
timing.
Table 41. LPs—Receive1
All specifications are based on simulation data and are subject to change without notice.
Parameter
Min
Max
Unit
Timing Requirements
fLCLKREXT
tSLDCL
LPx_CLK Frequency
TBD
MHz
ns
Data Setup Before LPx_CLK Low
Data Hold After LPx_CLK Low
LPx_CLK Period2
LPx_CLK Width Low2
LPx_CLK Width High2
TBD
tHLDCL
TBD
ns
tLCLKEW
tLCLKRWL
tLCLKRWH
tLCLKREXT – TBD
0.5 × tLCLKREXT
0.5 × tLCLKREXT
ns
ns
ns
Switching Characteristic
tDLALC
LPx_ACK Low Delay After LPx_CLK Low3
1.5 × tOCLK_0 + TBD
2.5 × tOCLK_0 + TBD
ns
1 Specifications apply to LP0 and LP1.
2 This specification indicates the minimum instantaneous width or period that can be tolerated due to duty cycle variation or jitter on the external LPx_CLK. For the external
LPx_CLK ideal maximum frequency, see the fLCLKRTEXT specification in Table 26.
3 LPx_ACK goes low with tDLALC relative to rise of LPx_CLK after first byte, but does not go low if the link buffer of the receiver is not about to fill.
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ADSP-21591/21593/21594/ADSP-SC591/SC592/SC594
Preliminary Technical Data
tLCLKEW
tLCLKRWH
tLCLKRWL
LPx_CLK
tHLDCL
tSLDCL
IN
LPx_D7–0
tDLALC
LPx_ACK (OUT)
Figure 11. LPs—Receive
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ADSP-21591/21593/21594/ADSP-SC591/SC592/SC594
Preliminary Technical Data
Table 42. LPs—Transmit1
All specifications are based on simulation data and are subject to change without notice.
Parameter
Timing Requirements
tSLACH
Min
Max
Unit
LPx_ACK Setup Before LPx_CLK Low
LPx_ACK Hold After LPx_CLK Low
TBD × tOCLK_0 + TBD
TBD
ns
ns
tHLACH
Switching Characteristics
tDLDCH
tHLDCH
tLCLKTWL
Data Delay After LPx_CLK High
TBD
ns
ns
ns
ns
ns
Data Hold After LPx_CLK High
LPx_CLK Width Low
TBD
2
TBD × tLCLKTPROG
TBD× tLCLKTPROG
N × tLCLKTPROG – TBD
tOCLK_0 + TBD
TBD × tLCLKTPROG
TBD × tLCLKTPROG
2
tLCLKTWH
LPx_CLK Width High
2
tLCLKTW
LPx_CLK Period
tDLACLK
LPx_CLK Low Delay After LPx_ACK High
TBD × tOCLK_0 + TBD × tLPCLK + TBD ns
1 Specifications apply to LP0 and LP1.
2 See Table 26 for details on the minimum period that can be programmed for fLCLKTPROG
.
LAST BYTE
FIRST BYTE
1
tLCLKTWH tLCLKTWL
TRANSMITTED
TRANSMITTED
LPx_CLK
tDLDCH
tHLDCH
LPx_Dx
(DATA)
OUT
tSLACH
tHLACH
tDLACLK
LPx_ACK (IN)
NOTES
The t
and tHLACH specifications apply only to the LPx_CLK falling edge. If these specifications are met,
LPx_CSLLACKH extends and the dotted LPx_CLK falling edge does not occur as shown. The position of the
dotted falling edge can be calculated using the tLCLKTWH specification. tLCLKTWH Min must be used for tSLACH
and tLCLKTWH Max for tHLACH
.
Figure 12. LPs—Transmit
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ADSP-21591/21593/21594/ADSP-SC591/SC592/SC594
Preliminary Technical Data
Serial Ports (SPORTs)
To determine whether a device is compatible with the SPORT at clock speed n, the following specifications must be confirmed: frame sync
delay and frame sync setup and hold; data delay and data setup and hold; and serial clock (SPTx_CLK) width. In Figure 13, either the ris-
ing edge or the falling edge of SPTx_A/BCLK (external or internal) can be used as the active sampling edge.
When externally generated, the SPORT clock is called fSPTCLKEXT
:
1
tSPTCLKEXT
=
-----------------------
fSPTCLKEXT
When internally generated, the programmed SPORT clock (fSPTCLKPROG) frequency in megahertz is set by the following equation:
fSCLK0
CLKDIV + 1
fSPTCLKPROG
=
------------------------
1
tSPTCLKPROG
=
---------------------------
fSPTCLKPROG
where CLKDIV is a field in the SPORT_DIV register that can be set from 0 to 65,535.
Table 43. SPORTs—External Clock1
All specifications are based on simulation data and are subject to change without notice.
Parameter
Min
Max
Unit
Timing Requirements
tSFSE
Frame Sync Setup Before SPTx_CLK
TBD
ns
(Externally Generated Frame Sync in Either Transmit or Receive
Mode)2
tHFSE
Frame Sync Hold After SPTx_CLK
TBD
ns
(Externally Generated Frame Sync in Either Transmit or Receive
Mode)2
tSDRE
Receive Data Setup Before Receive SPTx_CLK2
Receive Data Hold After SPTx_CLK2
SPTx_CLK Width3
TBD
ns
ns
ns
ns
tHDRE
TBD
tSPTCLKW
tSPTCLK
0.5 × tSPTCLKEXT – TBD
tSPTCLKEXT – TBD
SPTx_CLK Period3
Switching Characteristics
tDFSE
Frame Sync Delay After SPTx_CLK
TBD
TBD
ns
ns
(Internally Generated Frame Sync in Either Transmit or Receive
Mode)4
tHOFSE
Frame Sync Hold After SPTx_CLK
TBD
TBD
(Internally Generated Frame Sync in Either Transmit or Receive
Mode)4
tDDTE
tHDTE
Transmit Data Delay After Transmit SPTx_CLK4
Transmit Data Hold After Transmit SPTx_CLK4
ns
ns
1 Specifications apply to all four SPORTs.
2 Referenced to sample edge.
3 This specification indicates the minimum instantaneous width or period that can be tolerated due to duty cycle variation or jitter on the ideal maximum external SPTx_CLK.
For the external SPTx_CLK ideal maximum frequency, see the fSPTCLKEXT specification in Table 26.
4 Referenced to drive edge.
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Preliminary Technical Data
Table 44. SPORTs—Internal Clock1
All specifications are based on simulation data and are subject to change without notice.
Parameter
Timing Requirements
tSFSI
Min
Max
Unit
Frame Sync Setup Before SPTx_CLK
(Externally Generated Frame Sync in Either Transmit or
Receive Mode)2
TBD
ns
ns
tHFSI
Frame Sync Hold After SPTx_CLK
(Externally Generated Frame Sync in Either Transmit or
Receive Mode)2
TBD
tSDRI
tHDRI
Switching Characteristics
Receive Data Setup Before SPTx_CLK2
Receive Data Hold After SPTx_CLK2
TBD
TBD
ns
ns
tDFSI
Frame Sync Delay After SPTx_CLK (Internally Generated
TBD
TBD
ns
ns
Frame Sync in Transmit or Receive Mode)3
tHOFSI
Frame Sync Hold After SPTx_CLK (Internally Generated
Frame Sync in Transmit or Receive Mode)3
Transmit Data Delay After SPTx_CLK3
Transmit Data Hold After SPTx_CLK3
SPTx_CLK Width4
TBD
tDDTI
ns
ns
ns
ns
tHDTI
TBD
tSPTCLKIW
tSPTCLKW
0.5 × tSPTCLKPROG – TBD
tSPTCLKPROG – TBD
SPTx_CLK Period4
1 Specifications apply to all four SPORTs.
2 Referenced to the sample edge.
3 Referenced to drive edge.
4 See Table 26 for details on the minimum period that can be programmed for fSPTCLKPROG
.
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Preliminary Technical Data
DATA RECEIVE—INTERNAL CLOCK
DATA RECEIVE—EXTERNAL CLOCK
DRIVE EDGE
SAMPLE EDGE
DRIVE EDGE
SAMPLE EDGE
tSPTCLKIW
tSPTCLKW
SPTx_A/BCLK
(SPORT CLOCK)
SPTx_A/BCLK
(SPORT CLOCK)
tDFSI
tDFSE
tHOFSI
tSFSI
tHFSI
tHOFSE
tSFSE
tHFSE
SPTx_A/BFS
(FRAME SYNC)
SPTx_A/BFS
(FRAME SYNC)
tSDRI
tHDRI
tSDRE
tHDRE
SPTx_A/BDx
(DATA CHANNEL A/B)
SPTx_A/BDx
(DATA CHANNEL A/B)
DATA TRANSMIT—INTERNAL CLOCK
DRIVE EDGE SAMPLE EDGE
DATA TRANSMIT—EXTERNAL CLOCK
DRIVE EDGE SAMPLE EDGE
tSPTCLKIW
tSPTCLKW
SPTx_A/BCLK
(SPORT CLOCK)
SPTx_A/BCLK
(SPORT CLOCK)
tDFSI
tDFSE
tHOFSI
tSFSI
tHFSI
tHOFSE
tSFSE
tHFSE
SPTx_A/BFS
(FRAME SYNC)
SPTx_A/BFS
(FRAME SYNC)
tDDTI
tDDTE
tHDTI
tHDTE
SPTx_A/BDx
(DATA CHANNEL A/B)
SPTx_A/BDx
(DATA CHANNEL A/B)
Figure 13. SPORTs
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Preliminary Technical Data
Table 45. SPORTs—Enable and Three-State1
All specifications are based on simulation data and are subject to change without notice.
Parameter
Min
TBD
TBD
Max
Unit
Switching Characteristics
tDDTEN
tDDTTE
tDDTIN
tDDTTI
Data Enable From External Transmit SPTx_CLK2
ns
ns
ns
ns
Data Disable From External Transmit SPTx_CLK2
Data Enable From Internal Transmit SPTx_CLK2
Data Disable From Internal Transmit SPTx_CLK2
TBD
TBD
1 Specifications apply to all four SPORTs.
2 Referenced to drive edge.
DRIVE EDGE
DRIVE EDGE
SPTx_CLK
(SPORT CLOCK EXTERNAL)
tDDTEN
tDDTTE
SPTx_A/BDx
(DATA CHANNEL A/B)
DRIVE EDGE
DRIVE EDGE
SPTx_CLK
(SPORT CLOCK INTERNAL)
tDDTIN
tDDTTI
SPTx_A/BDx
(DATA CHANNEL A/B)
Figure 14. SPORTs—Enable and Three-State
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The SPTx_TDV output signal becomes active in SPORT multichannel mode. During transmit slots (enabled with active channel selection
registers) the SPTx_TDV is asserted for communication with external devices.
Table 46. SPORTs—Transmit Data Valid (TDV)1
All specifications are based on simulation data and are subject to change without notice.
Parameter
Min
TBD
TBD
Max
Unit
Switching Characteristics
tDRDVEN
tDFDVEN
tDRDVIN
tDFDVIN
Data Valid Enable Delay From Drive Edge of External Clock2
ns
ns
ns
ns
Data Valid Disable Delay From Drive Edge of External Clock2
Data Valid Enable Delay From Drive Edge of Internal Clock2
Data Valid Disable Delay From Drive Edge of Internal Clock2
TBD
TBD
1 Specifications apply to all four SPORTs.
2 Referenced to drive edge.
DRIVE EDGE
DRIVE EDGE
SPTx_CLK
(SPORT EXTERNAL CLOCK)
tDRDVEN
tDFDVEN
SPTx_A/BTDV
DRIVE EDGE
DRIVE EDGE
SPTx_CLK
(SPORT INTERNAL CLOCK)
tDRDVIN
tDFDVIN
SPTx_A/BTDV
Figure 15. SPORTs—Transmit Data Valid Internal and External Clock
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Table 47. SPORTs—External Late Frame Sync1
All specifications are based on simulation data and are subject to change without notice.
Parameter
Min
Max
Unit
Switching Characteristics
tDDTLFSE
DataDelayFromLateExternalTransmitFrameSyncorExternalReceiveFrame
Sync with SPORT_MCTL_A/B bits MCE = 1, MFD = 02
Data Enable for SPORT_MCTL_A/B bits MCE = 1, MFD = 02
TBD
ns
ns
tDDTENFS
TBD
1 Specifications apply to all four SPORTs.
2 The tDDTLFSE and tDDTENFS parameters apply to left justified as well as standard serial mode and MCE = 1, MFD = 0.
DRIVE
SAMPLE
DRIVE
SPTx_A/BCLK
(SPORT CLOCK)
tHFSE/I
tSFSE/I
SPTx_A/BFS
(FRAME SYNC)
tDDTE/I
tDDTENFS
tHDTE/I
SPTx_A/BDx
(DATA CHANNEL A/B)
1ST BIT
2ND BIT
tDDTLFSE
Figure 16. External Late Frame Sync
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Asynchronous Sample Rate Converter (ASRC)—Serial Input Port
The ASRC input signals are routed from the DAI0_PINx pins using the SRU. Therefore, the timing specifications provided in Table 48 are
valid at the DAI0_PINx pins.
Table 48. ASRC, Serial Input Port
All specifications are based on simulation data and are subject to change without notice.
Parameter
Min
Max
Unit
Timing Requirements
1
tSRCSFS
Frame Sync Setup Before Serial Clock Rising Edge
TBD
ns
ns
ns
ns
ns
ns
1
tSRCHFS
Frame Sync Hold After Serial Clock Rising Edge
Data Setup Before Serial Clock Rising Edge
Data Hold After Serial Clock Rising Edge
Clock Width
TBD
1
tSRCSD
TBD
1
tSRCHD
tSRCCLKW
tSRCCLK
TBD
tSCLK0 – TBD
2 × tSCLK0
Clock Period
1
The serial clock, data, and frame sync signals can originate from any of the DAI pins. The serial clock and frame sync signals can also originate via PCG or SPORTs. The
input of the PCG can be either CLKIN or any of the DAI pins.
SAMPLE EDGE
tSRCCLK
DAI0_PIN20–1
(SCLK0)
tSRCCLKW
tSRCSFS
tSRCHFS
DAI0_PIN20–1
(FS)
tSRCSD
tSRCHD
DAI0_PIN20–1
(SDATA)
Figure 17. ASRC Serial Input Port Timing
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Asynchronous Sample Rate Converter (ASRC)—Serial Output Port
For the serial output port, the frame sync is an input and it must meet setup and hold times with regard to SCLK0 on the output port. The
serial data output has a hold time and delay specification with regard to the serial clock. In TDM mode, the ASRC drives at the rising edge
and samples at the falling edge of the serial clock. In all other modes, the serial clock rising edge is the sampling edge, and the falling edge
is the driving edge.
Table 49. ASRC, Serial Output Port
All specifications are based on simulation data and are subject to change without notice.
Parameter
Min
Max
Unit
Timing Requirements
1
tSRCSFS
Frame Sync Setup Before Serial Clock Rising Edge
TBD
ns
ns
ns
ns
1
tSRCHFS
tSRCCLKW
tSRCCLK
Frame Sync Hold After Serial Clock Rising Edge
TBD
Clock Width
Clock Period
tSCLK0 – TBD
2 × tSCLK0
Switching Characteristics
1
tSRCTDD
Transmit Data Delay After Serial Clock Falling Edge
Transmit Data Hold After Serial Clock Falling Edge
TBD
ns
ns
1
tSRCTDH
TBD
1 The serial clock, data, and frame sync signals can originate from any of the DAI pins. The serial clock and frame sync signals can also originate via PCG or SPORTs. The input
of the PCG can be either CLKIN, SCLK0, or any of the DAI pins.
SAMPLE EDGE
tSRCCLK
DAI0_PIN20–1
(SCLK0)
tSRCCLKW
tSRCSFS
tSRCHFS
DAI0_PIN20–1
(FS)
tSRCTDD
tSRCTDH
DAI0_PIN20–1
(SDATA)
Figure 18. ASRC Serial Output Port Timing
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SPI Port—Master Timing
SPI0, SPI1, and SPI2
Table 50 and Figure 19 describe the SPI port master operations.
When internally generated, the programmed SPI clock (fSPICLKPROG) frequency in megahertz is set by the following equation:
fCDU_CLKO0
BAUD + 1
fSPICLKPROG
=
---------------------
1
tSPICLKPROG
=
--------------------------
fSPICLKPROG
where BAUD is a field in the SPIx_CLK register that can be set from 0 to 65,535.
Note that
• In dual-mode data transmit, the SPIx_MISO signal is also an output.
• In quad-mode data transmit, the SPIx_MISO, SPIx_D2, and SPIx_D3 signals are also outputs.
• In dual-mode data receive, the SPIx_MOSI signal is also an input.
• In quad-mode data receive, the SPIx_MOSI, SPIx_D2, and SPIx_D3 signals are also inputs.
• Quad mode is supported by SPI1 and SPI2.
• CPHA is a configuration bit in the SPI_CTL register.
Table 50. SPI Port—Master Timing1
All specifications are based on simulation data and are subject to change without notice.
Parameter
Timing Requirements
tSSPIDM
Min
Max
Unit
Data Input Valid to SPIx_CLK Edge (Data Input Setup)
SPIx_CLK Sampling Edge to Data Input Invalid
TBD
TBD
ns
ns
tHSPIDM
Switching Characteristics
tSDSCIM
SPIx_SEL Low to First SPI_CLK Edge for CPHA = 12
SPIx_SEL Low to First SPI_CLK Edge for CPHA = 02
SPIx_CLK High Period3
SPIx_CLK Low Period3
SPIx_CLK Period3
Last SPIx_CLK Edge to SPIx_SEL High for CPHA = 12
Last SPIx_CLK Edge to SPIx_SEL High for CPHA = 02
Sequential Transfer Delay2, 4
tSPICLKPROG – TBD
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1.5 × tSPICLKPROG –TBD
0.5 × tSPICLKPROG – TBD
0.5 × tSPICLKPROG – TBD
tSPICLKPROG – TBD
tSPICHM
tSPICLM
tSPICLK
tHDSM
1.5 × tSPICLKPROG – TBD
tSPICLKPROG – TBD
tSPITDM
tSPICLKPROG – TBD
tDDSPIDM
tHDSPIDM
SPIx_CLK Edge to Data Out Valid (Data Out Delay)
SPIx_CLK Edge to Data Out Invalid (Data Out Hold)
TBD
TBD
1 All specifications apply to SPI0, SPI1, and SPI2.
2 Specification assumes the LEADX and LAGX bits in the SPI_DLY register are 1.
3 See Table 26 for details on the minimum period that can be programmed for tSPICLKPROG
4 Applies to sequential mode with STOP ≥ 1.
.
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SPIx_SEL
(OUTPUT)
tSDSCIM
tSPICLM
tSPICHM
tSPICLK
tHDSM
tSPITDM
SPIx_CLK
(OUTPUT)
tHDSPIDM
tDDSPIDM
DATA OUTPUTS
(SPIx_MOSI)
tSSPIDM
CPHA = 1
tHSPIDM
DATA INPUTS
(SPIx_MISO)
tHDSPIDM
tDDSPIDM
DATA OUTPUTS
(SPIx_MOSI)
tSSPIDM
tHSPIDM
CPHA = 0
DATA INPUTS
(SPIx_MISO)
Figure 19. SPI Port—Master Timing
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SPI Port—Slave Timing
SPI0, SPI1, and SPI2
Table 51 and Figure 20 describe SPI port slave operations. Note that
• In dual-mode data transmit, the SPIx_MOSI signal is also an output.
• In quad-mode data transmit, the SPIx_MOSI, SPIx_D2, and SPIx_D3 signals are also outputs.
• In dual-mode data receive, the SPIx_MISO signal is also an input.
• In quad-mode data receive, the SPIx_MISO, SPIx_D2, and SPIx_D3 signals are also inputs.
• In SPI slave mode, the SPI clock is supplied externally and is called fSPICLKEXT
:
1
tSPICLKEXT
=
----------------------
fSPICLKEXT
• Quad mode is supported by SPI1 and SPI2.
• CPHA is a configuration bit in the SPI_CTL register.
Table 51. SPI Port—Slave Timing1
All specifications are based on simulation data and are subject to change without notice.
Parameter
Min
Max
Unit
Timing Requirements
tSPICHS
tSPICLS
tSPICLK
tHDS
SPIx_CLK High Period2
SPIx_CLK Low Period2
SPIx_CLK Period2
0.5 × tSPICLKEXT – TBD
0.5 × tSPICLKEXT – TBD
tSPICLKEXT – TBD
TBD
ns
ns
ns
ns
ns
ns
ns
ns
Last SPIx_CLK Edge to SPIx_SS Not Asserted
Sequential Transfer Delay
tSPITDS
tSDSCI
tSSPID
tHSPID
tSPICLKEXT – TBD
TBD
SPIx_SS Assertion to First SPIx_CLK Edge
Data Input Valid to SPIx_CLK Edge (Data Input Setup)
SPIx_CLK Sampling Edge to Data Input Invalid
TBD
TBD
Switching Characteristics
tDSOE
SPIx_SS Assertion to Data Out Active
TBD
TBD
TBD
TBD
TBD
ns
ns
ns
ns
tDSDHI
tDDSPID
tHDSPID
SPIx_SS Deassertion to Data High Impedance
SPIx_CLK Edge to Data Out Valid (Data Out Delay)
SPIx_CLK Edge to Data Out Invalid (Data Out Hold)
TBD
1 All specifications apply to SPI0, SPI1, and SPI2.
2 This specification indicates the minimum instantaneous width or period that can be tolerated due to duty cycle variation or jitter on the external SPIx_CLK. For the external
SPIx_CLK ideal maximum frequency, see the fSPICLKTEXT specification in Table 26.
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SPIx_SS
(INPUT)
tSDSCI
tSPICLS
tSPICHS
tSPICLK
tHDS
tSPITDS
SPIx_CLK
(INPUT)
tDSOE
tDDSPID
tHDSPID
tDDSPID
tDSDHI
DATA OUTPUTS
(SPIx_MISO)
CPHA = 1
tSSPID
tHSPID
DATA INPUTS
(SPIx_MOSI)
tDSOE
tHDSPID
tDDSPID
tDSDHI
DATA OUTPUTS
(SPIx_MISO)
tHSPID
CPHA = 0
tSSPID
DATA INPUTS
(SPIx_MOSI)
Figure 20. SPI Port—Slave Timing
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SPI Port—SPIx_RDY Slave Timing
SPIx_RDY provides flow control. CPOL, CPHA, and FCCH are configuration bits in the SPIx_CTL register.
Table 52. SPI Port—SPIx_RDY Slave Timing1
All specifications are based on simulation data and are subject to change without notice.
Parameter
Conditions Min
Max
Unit
Switching Characteristic
tDSPISCKRDYS SPIx_RDY Deassertion From Last Valid Input SPIx_CLK Edge FCCH = 0
3 × tCDU_CLKO0
4 × tCDU_CLKO0
4 × tCDU_CLKO0 + TBD
5 × tCDU_CLKO0 + TBD
ns
ns
FCCH = 1
1 All specifications apply to all three SPIs.
tDSPISCKRDYS
SPIx_CLK
(CPOL = 0)
CPHA = 0
SPIx_CLK
(CPOL = 1)
SPIx_CLK
(CPOL = 0)
CPHA = 1
SPIx_CLK
(CPOL = 1)
SPIx_RDY (O)
Figure 21. SPIx_RDY Deassertion from Valid Input SPIx_CLK Edge in Slave Mode
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SPI Port—Open Drain Mode (ODM) Timing
In Figure 22 and Figure 23, the outputs can be SPIx_MOSI, SPIx_MISO, SPIx_D2, and/or SPIx_D3, depending on the mode of operation.
CPOL and CPHA are configuration bits in the SPI_CTL register.
Table 53. SPI Port—ODM Master Mode Timing1
All specifications are based on simulation data and are subject to change without notice.
Parameter
Min
Max
Unit
Switching Characteristics
tHDSPIODMM
tDDSPIODMM
SPIx_CLK Edge to High Impedance From Data Out Valid
SPIx_CLK Edge to Data Out Valid From High Impedance
TBD
ns
ns
TBD
1 All specifications apply to all three SPIs.
tHDSPIODMM
tHDSPIODMM
SPIx_CLK
(CPOL = 0)
SPIx_CLK
(CPOL = 1)
OUTPUT
(CPHA = 1)
OUTPUT
(CPHA = 0)
tDDSPIODMM
tDDSPIODMM
Figure 22. ODM Master Mode
Table 54. SPI Port—ODM Slave Mode1
All specifications are based on simulation data and are subject to change without notice.
Parameter
Min
Max
Unit
Timing Requirements
tHDSPIODMS
tDDSPIODMS
SPIx_CLK Edge to High Impedance From Data Out Valid
SPIx_CLK Edge to Data Out Valid From High Impedance
TBD
ns
ns
TBD
1 All specifications apply to all three SPIs.
tHDSPIODMS
tHDSPIODMS
SPIx_CLK
(CPOL = 0)
SPIx_CLK
(CPOL = 1)
OUTPUT
(CPHA = 1)
OUTPUT
(CPHA = 0)
tDDSPIODMS
tDDSPIODMS
Figure 23. ODM Slave Mode
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SPI Port—SPIx_RDY Master Timing
SPIx_RDY is used to provide flow control. CPOL and CPHA are configuration bits in the SPIx_CTL register, whereas LEADX, LAGX,
and STOP are configuration bits in the SPIx_DLY register.
Table 55. SPI Port—SPIx_RDY Master Timing1
All specifications are based on simulation data and are subject to change without notice.
Parameter
Conditions
Min
Max
Unit
Timing Requirement
tSRDYSCKM
Setup Time for SPIx_RDY
Deassertion Before Last Valid
Data SPIx_CLK Edge
(TBD × BAUD2) × tCDU_CLKO0
TBD
+
ns
Switching Characteristic
3
tDRDYSCKM Assertion of SPIx_RDY to First
BAUD = 0, CPHA = 0 TBD × tCDU_CLKO0
TBD × tCDU_CLKO0 + TBD
TBD × tCDU_CLKO0 + TBD
ns
ns
SPIx_CLK Edge of Next Transfer
BAUD = 0, CPHA = 1 TBD × tCDU_CLKO0
BAUD > 0, CPHA = 0 (TBD × BAUD2) × tCDU_CLKO0
BAUD > 0, CPHA = 1 (TBD × BAUD2) × tCDU_CLKO0
(TBD × BAUD2) × tCDU_CLKO0 +TBD ns
(TBD × BAUD2) × tCDU_CLKO0 + TBD ns
1 All specifications apply to all three SPIs.
2 BAUD value is set using the SPIx_CLK.BAUD bits. BAUD value = SPIx_CLK.BAUD bits + 1.
3 Specification assumes the LEADX, LAGX, and STOP bits in the SPI_DLY register are zero.
tSRDYSCKM
SPIx_RDY
SPIx_CLK
(CPOL = 0)
SPIx_CLK
(CPOL = 1)
Figure 24. SPIx_RDY Setup Before SPIx_CLK
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tDRDYSCKM
SPIx_RDY
SPIx_CLK
(CPOL = 0)
CPHA = 0
SPIx_CLK
(CPOL = 1)
SPIx_CLK
(CPOL = 0)
CPHA = 1
SPIx_CLK
(CPOL = 1)
Figure 25. SPIx_CLK Switching Diagram after SPIx_RDY Assertion
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OSPI Port—Master Timing
OSPI0
Table 56 and Figure 26 describe the OSPI port master operations. Slave mode is not supported for OSPI.
When internally generated, the programmed SPI clock (fSPICLKPROG) frequency in megahertz is set by the following equation:
f
SYSCLK
f
=
----------------------
SPICLKPROG
PRG_MBD
1
t
=
--------------------------------------
SPICLKPROG
f
SPICLKPROG
where PRG_MBD is the master mode baud rate divisor.
Note that
• In dual-mode data transmit, the OSPI0_MISO signal is also an output.
• In quad-mode data transmit, the OSPI0_MISO, OSPI0_D2, and OSPI0_D3 signals are also outputs.
• In octal-mode data transmit, the OSPI0_MISO, OSPI0_D2, OSPI0_D3, OSPI0_D4, OSPI0_D5, OSPI0_D6, and OSPI0_D7 signals
are also outputs.
• In dual-mode data receive, the OSPI0_MOSI signal is also an input.
• In quad-mode data receive, the OSPI0_MOSI, OSPI0_D2, and OSPI0_D3 signals are also inputs.
• In octal-mode data receive, the OSPI0_MISO, OSPI0_D2, OSPI0_D3, OSPI0_D4, OSPI0_D5, OSPI0_D6, and OSPI0_D7 signals are
also outputs.
• CPHA is a configuration bit in the OSPI0_CTL register.
Table 56. OSPI0 Port—Master Timing1
All specifications are based on simulation data and are subject to change without notice.
Parameter
Min
Max
Unit
Timing Requirements
tSSPIDM Data Input Valid to OSPI0_CLK Sampling Edge
(Data Input Setup) 2
tSYSCLK + TBD
TBD
ns
ns
tHSPIDM OSPI0_CLK Sampling Edge to Data Input Invalid
(Data Input Hold)2
Switching Characteristics
tSDSCIM OSPI0_SEL Low to First OSPI0_CLK Edge3
TBD × tSPICLKPROG + PRG_CSSOT ×
ns
t
SYSCLK – TBD
tSPICHM OSPI0_CLK High Period4
tSPICLM OSPI0_CLK Low Period4
tSPICLK OSPI0_CLK Period4
TBD × tSPICLKPROG – TBD
TBD × tSPICLKPROG – TBD
tSPICLKPROG – TBD
ns
ns
ns
ns
ns
tHDSM
Last OSPI0_CLK Edge to OSPI0_SEL High for Mode = 05 PRG_CSEOT × tSYSCLK TBD
Last OSPI0_CLK Edge to OSPI0_SEL High for Mode = 35, 6 PRG_CSEOT × tSYSCLK + TBD ×
SPICLKPROG – TBD
t
tDDSPIDM OSPI0_CLK Edge to Data Out Valid to Driving Edge
(Data Out Delay)7
(PRG_WRHLD + TBD) × tSYSCLK ns
+TBD
tHDSPIDM OSPI0_CLK Edge to Data Out Invalid to Driving Edge
(Data Out Hold)7
PRG_WRHLD × tSYSCLK – TBD
ns
1 All specifications apply to OSPI0 only.
2
tSSPIDM and tHSPIDM specifications are valid only for default OSPI0_RDC settings.
3 PRG_CSSOT = chip select start of transfer (defined in OSPI0_DLY[7:0]).
4 See Table 26 for details on the minimum period that can be programmed for tSPICLKPROG
5 PRG_CSEOT = chip select end of transfer (defined in OSPI0_DLY[15:8]).
6 Mode = clock phase and clock polarity bits (defined inOSPI0_CTL[2:1]).
.
7 PRG_WRHLD = transmit delay to improve output hold (defined in OSPI0_RDC[19:16]).
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OSPI0_SEL
(OUTPUT)
tSDSCIM
tSPICLM
tSPICHM
tSPICLK
tHDSM
OSPI0_CLK
(OUTPUT)
tHDSPIDM
tDDSPIDM
DATA OUTPUTS
(OSPI0_MOSI)
tSSPIDM
CPHA = 1
tHSPIDM
DATA INPUTS
(OSPI0_MISO)
tHDSPIDM
tDDSPIDM
DATA OUTPUTS
(OSPI0_MOSI)
tSSPIDM
tHSPIDM
CPHA = 0
DATA INPUTS
(OSPI0_MISO)
Figure 26. OSPI Port—Master Timing
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Preliminary Technical Data
Precision Clock Generator (PCG) (Direct Pin Routing)
This timing is only valid when the SRU is configured such that the precision clock generator (PCG) takes inputs directly from the DAI
pins (via pin buffers) and sends outputs directly to the DAI pins. For the other cases, where the PCG inputs and outputs are not directly
routed to/from DAI pins (via pin buffers), there is no timing data available. All timing parameters and switching characteristics apply to
external DAI pins (DAI0_PINx).
Table 57. PCG (Direct Pin Routing)
All specifications are based on simulation data and are subject to change without notice.
Parameter
Min
Max
Unit
Timing Requirements
tPCGIP
tSTRIG
Input Clock Period
tSCLK0 × TBD
ns
ns
PCG Trigger Setup Before Falling Edge of PCG Input TBD
Clock
tHTRIG
PCG Trigger Hold After Falling Edge of PCG Input
Clock
TBD
ns
Switching Characteristics
tDPCGIO
PCGOutputClockandFrameSyncActiveEdgeDelay TBD
After PCG Input Clock
TBD
ns
ns
tDTRIGCLK
PCG Output Clock Delay After PCG Trigger
PCG Frame Sync Delay After PCG Trigger
Output Clock Period
TBD + (TBD × tPCGIP
)
TBD + (TBD × tPCGIP)
1
tDTRIGFS
TBD + ((TBD + D – PH) × tPCGIP) TBD + ((TBD + D – PH) × tPCGIP) ns
2 × tPCGIP – TBD ns
2
tPCGOW
1 D = FSxDIV, PH = FSxPHASE. For more information, see the ADSP-2159x/ADSP-SC591/592/594 SHARC+ Processor Hardware Reference.
2 Normal mode of operation.
tSTRIG
tHTRIG
DAI0_PIN20–1
PCG_TRIGx_I
DAI0_PIN20–1
PCG_EXTx_I
(CLKIN)
tDPCGIO
tPCGIP
DAI0_PIN20–1
PCG_CLKx_O
tDTRIGCLK
tPCGOW
tDPCGIO
DAI0_PIN20–1
PCG_FSx_O
tDTRIGFS
Figure 27. PCG (Direct Pin Routing)
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General-Purpose IO Port Timing
Table 58 and Figure 28 describe I/O timing, related to the general-purpose ports (PORT).
Table 58. General-Purpose Port Timing
All specifications are based on simulation data and are subject to change without notice.
Parameter
Min
Max
Unit
Timing Requirement
tWFI
General-Purpose Port Pin Input Pulse Width
2 × tSCLK0 – TBD
ns
tWFI
GPIO INPUT
Figure 28. General-Purpose Port Timing
General-Purpose I/O Timer Cycle Timing
Table 59, Table 60, and Figure 29 describe timer expired operations related to the general-purpose timer (TIMER0). The width value is the
timer period assigned in the TMx_TMRn_WIDTH register and can range from 1 to 232 – 1. When externally generated, the TMx_CLK
clock is called fTMRCLKEXT
:
1
tTMRCLKEXT
=
------------------------
fTMRCLKEXT
Table 59. Timer Cycle Timing—Internal Mode
All specifications are based on simulation data and are subject to change without notice.
Parameter
Min
Max
Unit
Timing Requirements
tWL
Timer Pulse Width Input Low (Measured In SCLK0 Cycles)1 2 × tSCLK0
Timer Pulse Width Input High (Measured In SCLK0 Cycles)1 2 × tSCLK0
ns
ns
tWH
Switching Characteristic
tHTO
Timer Pulse Width Output (Measured In SCLK0 Cycles)2
tSCLK0 × WIDTH – TBD
tSCLK0 × WIDTH + TBD
ns
1 The minimum pulse width applies for timer signals in width capture and external clock modes.
2 WIDTH refers to the value in the TMRx_WIDTH register (it can vary from 2 to 232 – 1).
Table 60. Timer Cycle Timing—External Mode
All specifications are based on simulation data and are subject to change without notice.
Parameter
Min
Max
Unit
Timing Requirements
tWL
Timer Pulse Width Input Low (Measured In EXT_CLK Cycles)1 2 × tEXT_CLK
Timer Pulse Width Input High (Measured In EXT_CLK Cycles)1 2 × tEXT_CLK
ns
ns
ns
tWH
tEXT_CLK
Timer External Clock Period2
tTMRCLKEXT (TBD)
Switching Characteristic
tHTO
Timer Pulse Width Output (Measured In EXT_CLK Cycles)3
tEXT_CLK × WIDTH – TBD tEXT_CLK × WIDTH + TBD ns
1 The minimum pulse width applies for timer signals in width capture and external clock modes.
2 This specification indicates the minimum instantaneous width or period that can be tolerated due to duty cycle variation or jitter on the external TMR_CLK. For the external
TMR_CLK maximum frequency, see the fTMRCLKEXT specification in Table 26.
3 WIDTH refers to the value in the TMRx_WIDTH register (it can vary from 1 to 232 – 1).
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TMR OUTPUT
tHTO
TMR INPUT
tWH, tWL
Figure 29. Timer Cycle Timing
DAIx Pin to DAIx Pin Direct Routing (DAI0 Block and DAI1 Block)
Table 61 and Figure 30 describe I/O timing related to the digital audio interface (DAI) for direct pin connections only (for example,
DAIx_PB01_I to DAIx_PB02_O).
Table 61. DAI Pin to DAI Pin Routing
All specifications are based on simulation data and are subject to change without notice.
Parameter
Min
Max
Unit
Switching Characteristic
tDPIO
Delay DAI Pin Input Valid to DAI Output Valid
TBD
TBD
ns
DAIx_PINn
DAIx_PINm
tDPIO
Figure 30. DAI Pin to DAI Pin Direct Routing
Up/Down Counter/Rotary Encoder Timing
Table 62 and Figure 31 describe timing related to the general-purpose counter (CNT).
Table 62. Up/Down Counter/Rotary Encoder Timing
All specifications are based on simulation data and are subject to change without notice.
Parameter
Min
Max
Unit
Timing Requirement
tWCOUNT
Up/Down Counter/Rotary Encoder Input Pulse Width
2 × tSCLK0
ns
CNT0_UD
CNT0_DG
CNT0_ZM
tWCOUNT
Figure 31. Up/Down Counter/Rotary Encoder Timing
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Preliminary Technical Data
Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing
The UART ports receive and transmit operations are described in the ADSP-2159x/ADSP-SC591/592/594 SHARC+ Processor Hardware
Reference.
Controller Area Network FD (CANFD) Interface
The CANFD interface timing is described in the ADSP-2159x/ADSP-SC591/592/594 SHARC+ Processor Hardware Reference.
Universal Serial Bus (USB)
Table 63 describes the universal serial bus (USB) clock timing. Refer to the USB 2.0 Specification for timing and dc specifications for USB
pins (including output characteristics for driver types E, F, and G listed in the ADSP-2159x/ADSP-SC59x Designer Quick Reference).
Table 63. USB Clock Timing1
All specifications are based on simulation data and are subject to change without notice.
Parameter
Timing Requirements
fUSBS
Min
Max
Unit
USB_CLKIN Frequency
TBD
TBD
TBD
TBD
MHz
ppm
fsUSB
USB_CLKIN Clock Frequency Stability
1 This specification is supported by USB0.
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Preliminary Technical Data
10/100 EMAC Timing (ETH0 and ETH1)
Table 64 through Table 66 and Figure 32 through Figure 34 describe the RMII EMAC operations.
Table 64. 10/100 EMAC Timing—RMII Receive Signal1
All specifications are based on simulation data and are subject to change without notice.
Parameter2
Min
Max
Unit
Timing Requirements
tREFCLKF
tREFCLKW
tREFCLKIS
tREFCLKIH
ETHx_REFCLK Frequency (fSCLK0 = SCLK0 Frequency)
TBD + TBD%
MHz
ETHx_REFCLK Width (tREFCLKF = ETHx_REFCLK Period)
tREFCLKF × TBD% tREFCLKF × TBD% ns
Rx Input Valid to RMII ETHx_REFCLK Rising Edge (Data Input Setup)
RMII ETHx_REFCLK Rising Edge to Rx Input Invalid (Data Input Hold)
TBD
TBD
ns
ns
1 These specifications apply to ETH0 and ETH1.
2 RMII inputs synchronous to RMII ETHx_REFCLK are ETHx_RXD1–0, RMII ETHx_CRS, and ERxER.
tREFCLKF
ETHx_REFCLK
tREFCLKW
tREFCLKW
ETHx_RXD1–0
ETHx_CRS
tREFCLKIS tREFCLKIH
Figure 32. 10/100 EMAC Controller Timing—RMII Receive Signal
Table 65. 10/100 EMAC Timing—RMII Transmit Signal1
All specifications are based on simulation data and are subject to change without notice.
Parameter2
Min
Max
Unit
Switching Characteristics
tREFCLKOV
tREFCLKOH
RMII ETHx_REFCLK Rising Edge to Transmit Output Valid (Data Out Valid)
RMII ETHx_REFCLK Rising Edge to Transmit Output Invalid (Data Out Hold) TBD
TBD
ns
ns
1 These specifications apply to ETH0 and ETH1.
2 RMII outputs synchronous to RMII ETHx_REFCLK are ETHx_TXD1 and TXD0.
tREFCLKF
ETHx_REFCLK
tREFCLKOH
ETHx_TXD1–0
ETHx_TXEN
tREFCLKOV
Figure 33. 10/100 EMAC Controller Timing—RMII Transmit Signal
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Table 66. EMAC Timing— Station Management1
All specifications are based on simulation data and are subject to change without notice.
Parameter2
Min
Max
Unit
Timing Requirements
tMDIOS
tMDCIH
Switching Characteristics
tMDCOV ETHx_MDC Falling Edge to ETHx_MDIO Output Valid
tMDCOH ETHx_MDC Falling Edge to ETHx_MDIO Output Invalid (Hold)
ETHx_MDIO Input Valid to ETHx_MDC Rising Edge (Setup)
TBD
TBD
ns
ns
ETHx_MDC Rising Edge to ETHx_MDIO Input Invalid (Hold)
tSCLK0 + TBD
ns
ns
tSCLK0 –TBD
1 These specifications apply to ETH0 and ETH1.
2 ETHx_MDC/ETHx_MDIO is a 2-wire serial bidirectional port for controlling one or more external PHYs. ETHx_MDC is an output clock with a minimum period that is
programmable as a multiple of the system clock SCLK0. ETHx_MDIO is a bidirectional data line.
ETHx_MDC
(OUTPUT)
tMDCOH
ETHx_MDIO
(OUTPUT)
tMDCOV
ETHx_MDIO
(INPUT)
tMDIOS
tMDCIH
Figure 34. Ethernet MAC Controller Timing— Station Management
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10/100/1000 EMAC Timing (ETH0 Only)
Table 67 and Figure 35 describe the RGMII EMAC timing.
Table 67. 10/100/1000 EMAC Timing—RGMII Receive and Transmit Signals 1
All specifications are based on simulation data and are subject to change without notice.
Parameter
Min
Max
Unit
Timing Requirements
tSETUPR
Data to Clock Input Setup at Receiver
TBD
TBD
TBD
TBD
ns
ns
ns
ns
tHOLDR
Data to Clock Input Hold at Receiver
RGMII Receive Clock Period
tGREFCLKF
tGREFCLKW
RGMII Receive Clock Pulse Width
Switching Characteristics
tSKEWT Data to Clock Output Skew at Transmitter
tCYC
TBD
TBD
ns
ns
ns
Clock Cycle Duration
TBD
TBD
tDUTY_G
Duty Cycle for RGMII Minimum
tGREFCLKF × TBD%
tGREFCLKF × TBD%
1 This specification is supported by ETH0 only (10/100/1000 EMAC controller).
ETH_TXCLK
(AT TRANSMITTER)
t
SKEWT
t
t
t
DUTY_G
DUTY_G
CYC
ETH_TXD3–0
ETH_TXCTL_TXEN
ETH_RXCLK_REFCLK
(AT RECEIVER)
t
t
t
t
GREFCLKW
GREFCLKW
GREFCLKF
SETUPR
t
HOLDR
ETH_RXD3–0
ETH_RXCTL_CRS
Figure 35. Gigabit EMAC Controller Timing—RGMII
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Preliminary Technical Data
Enhanced Parallel Peripheral Interface (EPPI) Timing
Table 68 and Table 69 and Figure 36 through Figure 44 describe enhanced parallel peripheral interface (EPPI) timing operations. In
Figure 36 through Figure 44, POLC[1:0] represents the setting of the EPPI_CTL register, which sets the sampling/driving edges of the
EPPI clock.
When internally generated, the programmed PPI clock (fPCLKPROG) frequency in megahertz is set by the following equation where
VALUE is a field in the EPPI_CLKDIV register that can be set from 0 to 65535:
fSCLK0
fPCLKPROG
=
=
--V---A--L--U---E---+----1--
1
tPCLKPROG
----------------
fPCLKPROG
When externally generated, the EPPI_CLK is called fPCLKEXT
:
1
tPCLKEXT
=
-------------
fPCLKEXT
Table 68. Enhanced Parallel Peripheral Interface (EPPI)—Internal Clock
Parameter
Min
Max
Unit
Timing Requirements
tSFSPI
External FS Setup Before EPPI_CLK
External FS Hold After EPPI_CLK
Receive Data Setup Before EPPI_CLK
Receive Data Hold After EPPI_CLK
TBD
TBD
TBD
TBD
ns
ns
ns
ns
ns
tHFSPI
tSDRPI
tHDRPI
tSFS3GI
External FS3 Input Setup Before EPPI_CLK Fall Edge in Clock TBD
Gating Mode
tHFS3GI
External FS3 Input Hold Before EPPI_CLK Fall Edge in Clock
Gating Mode
TBD
ns
Switching Characteristics
tPCLKW
EPPI_CLK Width1
tPCLK
0.5 × tPCLKPROG – TBD
tPCLKPROG – TBD
ns
ns
ns
ns
ns
ns
EPPI_CLK Period1
tDFSPI
tHOFSPI
tDDTPI
tHDTPI
Internal FS Delay After EPPI_CLK
Internal FS Hold After EPPI_CLK
Transmit Data Delay After EPPI_CLK
Transmit Data Hold After EPPI_CLK
TBD
TBD
TBD
TBD
1 See Table 26 for details on the minimum period that can be programmed for tPCLKPROG
.
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FRAME SYNC
DRIVEN
DATA
SAMPLED
POLC[1:0] = 10
EPPI_CLK
POLC[1:0] = 01
tDFSPI
tPCLKW
tHOFSPI
tPCLK
EPPI_FS1/2
tSDRPI
tHDRPI
EPPI_D00-23
Figure 36. EPPI Internal Clock GP Receive Mode with Internal Frame Sync Timing
FRAME SYNC
DRIVEN
DATA
DRIVEN
DATA
DRIVEN
tPCLK
POLC[1:0] = 11
EPPI_CLK
POLC[1:0] = 00
tDFSPI
tPCLKW
tHOFSPI
EPPI_FS1/2
tHDTPI
tDDTPI
EPPI_D00-23
Figure 37. EPPI Internal Clock GP Transmit Mode with Internal Frame Sync Timing
DATA SAMPLED /
DATA SAMPLED /
FRAME SYNC SAMPLED
FRAME SYNC SAMPLED
POLC[1:0] = 11
EPPI_CLK
POLC[1:0] = 00
tPCLKW
tSFSPI
tHFSPI
tPCLK
PPI_FS1/2
tSDRPI
tHDRPI
PPI_D00-23
Figure 38. EPPI Internal Clock GP Receive Mode with External Frame Sync Timing
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DATA DRIVEN /
FRAME SYNC SAMPLED
POLC[1:0] = 11
PPI_CLK
POLC[1:0] = 00
tSFSPI
tHFSPI
tPCLKW
tPCLK
PPI_FS1/2
tDDTPI
tHDTPI
PPI_D00-23
Figure 39. EPPI Internal Clock GP Transmit Mode with External Frame Sync Timing
EPPI_CLK
EPPI_FS3
tHFS3GI
tSFS3GI
Figure 40. Clock Gating Mode with Internal Clock and External Frame Sync Timing
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Table 69. Enhanced Parallel Peripheral Interface (EPPI)—External Clock
Parameter
Min
Max
Unit
Timing Requirements
tPCLKW
tPCLK
EPPI_CLK Width1
EPPI_CLK Period1
0.5 × tPCLKEXT – TBD
ns
ns
ns
ns
ns
ns
tPCLKEXT – TBD
TBD
tSFSPE
tHFSPE
tSDRPE
tHDRPE
External FS Setup Before EPPI_CLK
External FS Hold After EPPI_CLK
Receive Data Setup Before EPPI_CLK
Receive Data Hold After EPPI_CLK
TBD
TBD
TBD
Switching Characteristics
tDFSPE
tHOFSPE
tDDTPE
tHDTPE
Internal FS Delay After EPPI_CLK
TBD
TBD
ns
ns
ns
ns
Internal FS Hold After EPPI_CLK
Transmit Data Delay After EPPI_CLK
Transmit Data Hold After EPPI_CLK
TBD
TBD
1 This specification indicates the minimum instantaneous width or period that can be tolerated due to duty cycle variation or jitter on the external EPPI_CLK. For the external
EPPI_CLK ideal maximum frequency, see the fPCLKEXT specification in Table 26.
FRAME SYNC
DRIVEN
DATA
SAMPLED
POLC[1:0] = 10
EPPI_CLK
POLC[1:0] = 01
tDFSPE
tPCLKW
tHOFSPE
tPCLK
EPPI_FS1/2
tSDRPE
tHDRPE
EPPI_D00-23
Figure 41. EPPI External Clock GP Receive Mode with Internal Frame Sync Timing
FRAME SYNC
DRIVEN
DATA
DRIVEN
DATA
DRIVEN
tPCLK
POLC[1:0] = 11
EPPI_CLK
POLC[1:0] = 00
tDFSPE
tPCLKW
tHOFSPE
EPPI_FS1/2
tDDTPE
tHDTPE
EPPI_D00-23
Figure 42. EPPI External Clock GP Transmit Mode with Internal Frame Sync Timing
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DATA SAMPLED /
FRAME SYNC SAMPLED
DATA SAMPLED /
FRAME SYNC SAMPLED
POLC[1:0] = 11
EPPI_CLK
POLC[1:0] = 00
tPCLKW
tSFSPE
tHFSPE
tPCLK
EPPI_FS1/2
tSDRPE
tHDRPE
EPPI_D00-23
Figure 43. EPPI External Clock GP Receive Mode with External Frame Sync Timing
DATA DRIVEN /
FRAME SYNC SAMPLED
POLC[1:0] = 11
EPPI_CLK
POLC[1:0] = 00
tSFSPE
tHFSPE
tPCLKW
tPCLK
EPPI_FS1/2
tDDTPE
tHDTPE
EPPI_D00-23
Figure 44. EPPI External Clock GP Transmit Mode with External Frame Sync Timing
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Preliminary Technical Data
Sony/Philips Digital Interface (S/PDIF) Transmitter
Serial data input to the S/PDIF transmitter can be formatted as left justified, I2S, or right justified with word widths of 16, 18, 20, or 24 bits.
The following sections provide timing for the transmitter.
S/PDIF Transmitter Serial Input Waveforms
Table 70 and Figure 45 show the right justified mode. Frame sync is high for the left channel and low for the right channel. Data is valid on
the rising edge of the serial clock. The MSB is delayed the minimum in 24-bit output mode or the maximum in 16-bit output mode from a
frame sync transition, so that when there are 64 serial clock periods per frame sync period, the LSB of the data is right justified to the next
frame sync transition.
Table 70. S/PDIF Transmitter Right Justified Mode
All specifications are based on simulation data and are subject to change without notice.
Parameter
Timing Requirement
tRJD
Conditions
Nominal
Unit
Frame Sync to MSB Delay in Right Justified Mode
16-bit word mode
18-bit word mode
20-bit word mode
24-bit word mode
TBD
TBD
TBD
TBD
SCLK0
SCLK0
SCLK0
SCLK0
LEFT/RIGHT CHANNEL
DAI_P20–1
FS
DAI_P20–1
SCLK0
tRJD
DAI_P20–1
SDATA
LSB
MSB
MSB–1 MSB–2
LSB+2 LSB+1
LSB
Figure 45. Right Justified Mode
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Table 71 and Figure 46 show the default I2S justified mode. The frame sync is low for the left channel and high for the right channel. Data
is valid on the rising edge of the serial clock. The MSB is left justified to the frame sync transition but with a delay.
Table 71. S/PDIF Transmitter I2S Mode
All specifications are based on simulation data and are subject to change without notice.
Parameter
Timing Requirement
tI2SD
Nominal
Unit
Frame Sync to MSB Delay in I2S Mode
TBD
SCLK0
LEFT/RIGHT CHANNEL
DAI_P20–1
(FS)
DAI_P20–1
(SCLK0)
tI2SD
DAI_P20–1
(SDATA)
MSB
MSB–1 MSB–2
LSB+2 LSB+1
LSB
Figure 46. I2S Justified Mode
Table 72 and Figure 47 show the left justified mode. The frame sync is high for the left channel and low for the right channel. Data is valid
on the rising edge of the serial clock. The MSB is left justified to the frame sync transition with no delay.
Table 72. S/PDIF Transmitter Left Justified Mode
All specifications are based on simulation data and are subject to change without notice.
Parameter
Timing Requirement
tLJD
Nominal
Unit
Frame Sync to MSB Delay in Left Justified Mode
TBD
SCLK0
DAI_P20–1
(FS)
LEFT/RIGHT CHANNEL
DAI_P20–1
(SCLK0)
tLJD
DAI_P20–1
(SDATA)
MSB
MSB–1 MSB–2
LSB+2 LSB+1
LSB
Figure 47. Left Justified Mode
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Preliminary Technical Data
S/PDIF Transmitter Input Data Timing
The timing requirements for the S/PDIF transmitter are given in Table 73. Input signals are routed to the DAI0_PINx pins using the SRU.
Therefore, the timing specifications provided below are valid at the DAI0_PINx pins.
Table 73. S/PDIF Transmitter Input Data Timing
All specifications are based on simulation data and are subject to change without notice.
Parameter
Min
Max
Unit
Timing Requirements
1
tSISFS
Frame Sync Setup Before Serial Clock Rising Edge
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
ns
ns
ns
ns
ns
ns
ns
ns
1
tSIHFS
Frame Sync Hold After Serial Clock Rising Edge
Data Setup Before Serial Clock Rising Edge
Data Hold After Serial Clock Rising Edge
Transmit Clock Width
1
tSISD
1
tSIHD
tSITXCLKW
tSITXCLK
tSISCLKW
tSISCLK
Transmit Clock Period
Clock Width
Clock Period
1 The serial clock, data, and frame sync signals can come from any of the DAI pins. The serial clock and frame sync signals can also come via PCG or SPORTs. The input of the
PCG can be either CLKIN or any of the DAI pins.
SAMPLE EDGE
tSITXCLKW
tSITXCLK
DAI0_PIN20–1
(TxCLK)
tSISCLK
tSISCLKW
DAI0_PIN20–1
(SCLK0)
tSISFS
tSIHFS
DAI0_PIN20–1
(FS)
tSISD
tSIHD
DAI0_PIN20–1
(SDATA)
Figure 48. S/PDIF Transmitter Input Timing
Oversampling Clock (TxCLK) Switching Characteristics
The S/PDIF transmitter requires an oversampling clock input. This high frequency clock (TxCLK) input is divided down to generate the
internal biphase clock.
Table 74. Oversampling Clock (TxCLK) Switching Characteristics
All specifications are based on simulation data and are subject to change without notice.
Parameter
Max
Unit
Switching Characteristics
fTXCLK_384
fTXCLK_256
fFS
Frequency for TxCLK = 384 × Frame Sync
Oversampling ratio × frame sync ≤ 1/tSITXCLK
MHz
MHz
kHz
Frequency for TxCLK = 256 × Frame Sync
Frame Rate (FS)
TBD
TBD
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S/PDIF Receiver
The following section describes timing as it relates to the S/PDIF receiver.
Internal Digital PLL Mode
In the internal digital PLL mode, the internal digital PLL generates the 512 × FS clock.
Table 75. S/PDIF Receiver Internal Digital PLL Mode Timing
All specifications are based on simulation data and are subject to change without notice.
Parameter
Min
Max
TBD
TBD
Unit
Switching Characteristics
tDFSI
Frame Sync Delay After Serial Clock
Frame Sync Hold After Serial Clock
Transmit Data Delay After Serial Clock
Transmit Data Hold After Serial Clock
ns
ns
ns
ns
tHOFSI
tDDTI
tHDTI
TBD
TBD
DRIVE EDGE
SAMPLE EDGE
DAI0_PIN20–1
(SCLK0)
tDFSI
tHOFSI
DAI0_PIN20–1
(FS)
tDDTI
tHDTI
DAI0_PIN20–1
(DATA CHANNEL A/B)
Figure 49. S/PDIF Receiver Internal Digital PLL Mode Timing
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Preliminary Technical Data
MediaLB (MLB)
All the numbers shown in Table 76 are applicable for all MLB speed modes (1024 FS, 512 FS, and 256 FS) for the 3-pin protocol, unless
otherwise specified. Refer to the Media Local Bus Specification Version 4.2 for more details.
Table 76. 3-Pin MLB Interface Specifications
All specifications are based on simulation data and are subject to change without notice.
Parameter
Min
Typ
Max
Unit
tMLBCLK
MLB Clock Period
1024 FS
TBD
TBD
TBD
ns
ns
ns
512 FS
256 FS
tMCKL
MLBCLK Low Time
1024 FS
TBD
TBD
TBD
ns
ns
ns
512 FS
256 FS
tMCKH
MLBCLK High Time
1024 FS
TBD
TBD
TBD
ns
ns
ns
512 FS
256 FS
tMCKR
MLBCLK Rise Time (VIL to VIH)
1024 FS
TBD
TBD
ns
ns
512 FS/256 FS
tMCKF
MLBCLK Fall Time (VIH to VIL)
1024 FS
TBD
TBD
ns
ns
512 FS/256 FS
1
tMPWV
MLBCLK Pulse Width Variation
1024 FS
TBD
TBD
nspp
nspp
512 FS/256
tDSMCF
tDHMCF
tMCFDZ
tMCDRV
DAT/SIG Input Setup Time
TBD
TBD
TBD
ns
ns
ns
ns
DAT/SIG Input Hold Time
DAT/SIG Output Time to Three-State
DAT/SIG Output Data Delay From MLBCLK Rising Edge
TBD
TBD
2
tMDZH
Bus Hold Time
1024 FS
512 FS/256
TBD
TBD
ns
ns
CMLB
DAT/SIG Pin Load
1024 FS
TBD
TBD
pf
pf
512 FS/256
1 Pulse width variation is measured at 1.25 V by triggering on one edge of MLBCLK and measuring the spread on the other edge, measured in nanoseconds peak-to-peak.
2 Board designs must ensure the high impedance bus does not leave the logic state of the final driven bit for this time period. Therefore, coupling must be minimized while
meeting the maximum capacitive load listed.
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MLB_SIG/
MLB_DAT
(Rx, Input)
VALID
tDHMCF
tDSMCF
tMCKH
tMCKL
MLB_CLK
tMCKR
tMCKF
tMLBCLK
tMCFDZ
tMCDRV
tMDZH
MLB_SIG/
MLB_DAT
(Tx, Output)
VALID
Figure 50. MLB Timing (3-Pin Interface)
The ac timing specifications of the 6-pin MLB interface is detailed in Table 77. Refer to the Media Local Bus Specification version 4.2 for
more details.
Table 77. 6-Pin MLB Interface Specifications
Parameter
Conditions
Min
Typ
Max
Unit
tMT
Differential Transition Time at the Input Pin (See Figure 51)
20% to 80% VIN+/VIN–
80% to 20% VIN+/VIN–
TBD
ns
fMCKE MLBCP/N External Clock Operating Frequency (See Figure 52)1
2048 × FS at 44.0 kHz TBD
2048 × FS at 50.0 kHz
MHz
MHz
MHz
MHz
ns
TBD
fMCKR Recovered Clock Operating Frequency (Internal, Not Observable
at Pins, Only for Timing References) (See Figure 52)
2048 × FS at 44.0 kHz TBD
2048 × FS at 50.0 kHz
TBD
TBD
tDELAY Transmitter MLBSP/N (MLBDP/N) Output Valid From Transition of
MLBCP/N (Low to High) (See Figure 53)
fMCKR = 2048 × FS
TBD
TBD
TBD
TBD
TBD
tPHZ
tPLZ
tSU
Disable Turnaround Time From Transition of MLBCP/N (Low to High) fMCKR = 2048 × FS
(See Figure 54)
TBD
TBD
ns
ns
ns
ns
Enable Turnaround Time From Transition of MLBCP/N (Low to High) fMCKR = 2048 × FS
(See Figure 54)
MLBSP/N (MLBDP/N) Valid to Transition of MLBCP/N (Low to High)
(See Figure 53)
fMCKR = 2048 × FS
tHD
MLBSP/N (MLBDP/N) Hold From Transition of MLBCP/N (Low to High)
(See Figure 53)2
1 fMCKE (maximum) and fMCKR (maximum) include maximum cycle to cycle system jitter (tJITTER) of 600 ps for a bit error rate of 10E-9.
2 Receivers must latch MLBSP/N (MLBDP/N) data within tHD (minimum) of the rising edge of MLBCP/N.
Rev. PrD
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ADSP-21591/21593/21594/ADSP-SC591/SC592/SC594
Preliminary Technical Data
tMT
tMT
MLBCP/N
MLBDP/N
MLBSP/N
80%
20%
Figure 51. MLB 6-Pin Transition Time
MLBCP/N
1/f
MCKE
RECOVERED
CLOCK (1:1)
T
1:1
RECOVERED
CLOCK (2:1)
T
T
2:1
2:1
NOTE: T
T
= 1/f
1:1
MCKE
= 1/(2 × f
)
2:1
MCKE
Figure 52. MLB 6-Pin Clock Definitions
Rev. PrD
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ADSP-21591/21593/21594/ADSP-SC591/SC592/SC594
Preliminary Technical Data
1/f
MCKE
MLBCP/N
RECOVERED
CLOCK
1/f
MCKR
tDELAY
tDELAY
MLBSP/N
MLBDP/N
(TRANSMIT)
tSU
tSU
MLBSP/N
MLBDP/N
(RECEIVE)
VALID
tHD
VALID
tHD
1/f
MCKE
MLBCP/N
1/f
MCKR
RECOVERED
CLOCK
tDELAY
tDELAY
MLBSP/N
MLBDP/N
(TRANSMIT)
tSU
VALID
tHD
MLBSP/N
MLBDP/N
(RECEIVE)
VALID
tHD
Figure 53. MLB 6-Pin Delay, Setup, and Hold Times
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ADSP-21591/21593/21594/ADSP-SC591/SC592/SC594
Preliminary Technical Data
MLBCP/N
RECOVERED
CLOCK (1:1)
tPHZ
MLBDP/N
MLNSP/N
tPLZ
MLBCP/N
RECOVERED
CLOCK (2:1)
tPHZ
MLBDP/N
MLNSP/N
tPLZ
Figure 54. MLB 6-Pin Disable and Enable Turnaround Times
Rev. PrD
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ADSP-21591/21593/21594/ADSP-SC591/SC592/SC594
Preliminary Technical Data
Program Trace Macrocell (PTM) Timing
Table 78 and Figure 55 provide I/O timing related to the PTM.
Table 78. TRACE0 Timing
All specifications are based on simulation data and are subject to change without notice.
Parameter
Min
Max
Unit
Switching Characteristics
tDTRD
tHTRD
tPTRCK
TRACE0 Data Delay From Trace Clock Maximum
0.5 × tSCLK0 + TBD ns
TRACE0 Data Hold From Trace Clock Minimum
TRACE0 Clock Period Minimum
0.5 × tSCLK0 – TBD
2 × tSCLK0 – TBD
ns
ns
t
PTRCK
TRACE0_CLK
t
t
HTRD
t
HTRD
TRACE0_DX
D0
D1
t
DTRD
DTRD
Figure 55. Trace Timing
Rev. PrD
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ADSP-21591/21593/21594/ADSP-SC591/SC592/SC594
Preliminary Technical Data
Debug Interface (JTAG Emulation Port) Timing
Table 79 and Figure 56 provide I/O timing related to the debug interface (JTAG emulator port).
Table 79. JTAG Emulation Port Timing
All specifications are based on simulation data and are subject to change without notice.
Parameter
Min
Max
Unit
Timing Requirements
tTCK
JTG_TCK Period
TBD
TBD
TBD
TBD
TBD
TBD
ns
ns
ns
ns
ns
TCK
tSTAP
JTG_TDI, JTG_TMS Setup Before JTG_TCK High
JTG_TDI, JTG_TMS Hold After JTG_TCK High
System Inputs Setup Before JTG_TCK High1
System Inputs Hold After JTG_TCK High1
JTG_TRST Pulse Width (Measured in JTG_TCK Cycles)2
tHTAP
tSSYS
tHSYS
tTRSTW
Switching Characteristics
tDTDO
tDSYS
JTG_TDO Delay From JTG_TCK Low
System Outputs Delay After JTG_TCK Low3
TBD
TBD
ns
ns
1 System Inputs = DAI0_PIN20-19, DAI0_PIN12-1, DAI1_PIN20-19, DAI1_PIN12-1, DMC0_A15-0, DMC0_DQ15-0, DMC0_RESET, PA_15-0, PB_15-0, PC_7-0,
SYS_BMODE2-0, SYS_FAULT.
2 50 MHz maximum.
3 System Outputs = DMC0_A15-0, DMC0_BA2-0, DMC0_CAS, DMC0_CK, DMC0_CKE, DMC0_CS0, DMC0_DQ15-0, DMC0_LDM, DMC0_LDQS, DMC0_ODT,
DMC0_RAS, DMC0_RESET, DMC0_UDM, DMC0_UDQS, DMC0_WE, PA_15-0, PB_15-0, PC_7-0, SYS_CLKOUT, SYS_FAULT, SYS_RESOUT.
tTCK
JTG_TCK
tSTAP
tHTAP
JTG_TMS
JTG_TDI
tDTDO
JTG_TDO
tSSYS
tHSYS
SYSTEM
INPUTS
tDSYS
SYSTEM
OUTPUTS
Figure 56. JTAG Port Timing
Rev. PrD
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Preliminary Technical Data ADSP-21591/21593/21594/ADSP-SC591/SC592/SC594
OUTPUT DRIVE CURRENTS
20
Figure 57 through Figure 62 show typical current voltage char-
V
V
V
= 1.575V AT –40°C
= 1.500V AT +25°C
= 1.425V AT +125°C
18
16
14
12
10
8
DD
DD
DD
acteristics for the output drivers of the ADSP-2159x/ADSP-
SC591/592/594 processors. The curves represent the current
drive capability of the output drivers as a function of output
voltage.
TBD
50
V
V
V
= 3.47V AT –40°C
= 3.30V AT +25°C
= 3.13V AT +125°C
DD
DD
DD
40
30
6
4
20
2
10
0
0
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
TBD
SOURCE VOLTAGE (V)
–10
–20
–30
–40
–50
Figure 59. Driver Type B and Driver Type C (DDR3 Drive Strength 100 Ω)
0
V
V
V
= 1.575V AT –40°C
= 1.500V AT +25°C
= 1.425V AT +125°C
DD
DD
DD
–2
–4
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
SOURCE VOLTAGE (V)
Figure 57. Driver Type A Current for All GPIO and DAI Pins Except for
CLKOUT, OSPI/SPI Clocks, and LP Clocks (3.3 V VDD_EXT
–6
)
–8
TBD
50
40
–10
–12
–14
–16
V
V
V
= 3.47V AT –40°C
= 3.30V AT +25°C
= 3.13V AT +125°C
DD
DD
DD
30
20
10
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
0
TBD
SOURCE VOLTAGE (V)
–10
–20
–30
–40
–50
Figure 60. Driver Type B and Driver Type C (DDR3 Drive Strength 100 Ω)
18
16
14
12
10
8
V
V
V
= 1.418V AT –40°C
= 1.350V AT +25°C
= 1.285V AT +125°C
DD
DD
DD
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
SOURCE VOLTAGE (V)
Figure 58. Driver Type A Current for CLKOUT, OSPI/SPI Clocks,
and LP Clocks (3.3 V VDD_EXT
TBD
)
6
4
2
0
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
SOURCE VOLTAGE (V)
Figure 61. Driver Type B and Driver Type C (DDR3L Drive Strength100 Ω)
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ADSP-21591/21593/21594/ADSP-SC591/SC592/SC594 Preliminary Technical Data
0
REFERENCE
SIGNAL
V
V
V
= 1.418V AT –40°C
= 1.350V AT +25°C
= 1.285V AT +125°C
DD
DD
DD
–2
–4
tDIS
tENA
–6
–8
TBD
–10
–12
–14
OUTPUT STOPS DRIVING
OUTPUT STARTS DRIVING
HIGH IMPEDANCE STATE
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
Figure 64. Output Enable/Disable
SOURCE VOLTAGE (V)
Figure 62. Driver Type B and Driver Type C (DDR3L Drive Strength 100 Ω)
Output Disable Time Measurement
Output pins are considered disabled when they stop driving,
enter a high impedance state, and start to decay from the output
high or low voltage. The output disable time, tDIS, is the interval
from when a reference signal reaches a high or low voltage level
to the point when the output stops driving, as shown on the left
side of Figure 64).
TEST CONDITIONS
All timing parameters appearing in this data sheet were mea-
sured under the conditions described in this section. Figure 63
shows the measurement point for ac measurements (except out-
put enable/disable). The measurement point, VMEAS, is
V
DD_EXT/2 for VDD_EXT (nominal) = 3.3 V.
Capacitive Loading
Output delays and holds are based on standard capacitive loads
of an average of 6 pF on all pins (see Figure 65). VLOAD is equal
to VDD_EXT/2. Figure 66 through Figure 69 show how output
rise time varies with capacitance. The delay and hold specifica-
tions given must be derated by a factor derived from these
figures. The graphs in Figure 66 through Figure 69 cannot be
linear outside the ranges shown.
INPUT
OR
OUTPUT
V
V
MEAS
MEAS
Figure 63. Voltage Reference Levels for AC Measurements
(Except Output Enable/Disable)
TESTER PIN ELECTRONICS
Output Enable Time Measurement
50:
V
LOAD
T1
Output pins are considered enabled when they make a transi-
tion from a high impedance state to the point when they start
driving.
DUT
OUTPUT
45:
70:
ZO = 50:ꢀ(impedance)
TD = 4.04 r 1.18 ns
The output enable time, tENA, is the interval from the point
when a reference signal reaches a high or low voltage level to the
point when the output starts driving, as shown on the right side
of Figure 64. If multiple pins are enabled, the measurement
value is that of the first pin to start driving.
50:
0.5pF
4pF
2pF
400:
NOTES:
THE WORST-CASE TRANSMISSION LINE DELAY IS SHOWN AND CAN BE USED
FOR THE OUTPUT TIMING ANALYSIS TO REFLECT THE TRANSMISSION LINE
EFFECT AND MUST BE CONSIDERED.THE TRANSMISSION LINE (TD) IS FOR
LOAD ONLY AND DOES NOT AFFECT THE DATA SHEET TIMING SPECIFICATIONS.
ANALOG DEVICES RECOMMENDS USING THE IBIS MODEL TIMING FOR A GIVEN
SYSTEM REQUIREMENT. IF NECESSARY,THE SYSTEM CAN INCORPORATE
EXTERNAL DRIVERS TO COMPENSATE FOR ANY TIMING DIFFERENCES.
Figure 65. Equivalent Device Loading for AC Measurements
(Includes All Fixtures)
Rev. PrD
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Preliminary Technical Data ADSP-21591/21593/21594/ADSP-SC591/SC592/SC594
6
5
4
3
2
1
0
0
tRISE = 3.3V AT +25°C
tFALL = 3.3V AT +25°C
tRISE = 3.135V AT +125°C
tFALL = 3.135V AT +125°C
tRISE = 3.465V AT –40°C
tFALL = 3.465V AT –40°C
V
V
V
= 1.418V AT –40°C
= 1.350V AT +25°C
= 1.285V AT +125°C
DD
DD
DD
–2
–4
–6
TBD
–8
TBD
–10
–12
–14
0
5
10
15
20
25
30
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
LOAD CAPACITANCE (pF)
SOURCE VOLTAGE (V)
Figure 66. Driver Type A Rise and Fall Times (10% to 90%) vs. Load Capaci-
tance for All GPIO/CLKOUT Pins Operating Between
62.5 MHz and 125 MHz
Figure 69. Driver Type B and Driver Type C Rise and Fall Times
(10% to 90%) vs. Load Capacitance for DDR3L at 100 Ω
ENVIRONMENTAL CONDITIONS
8
The ADSP-2159x/ADSP-SC59x processors are rated for perfor-
mance over the temperature range specified in the Preliminary
Operating Conditions section.
tRISE = 3.3V AT +25°C
tFALL = 3.3V AT +25°C
7
tRISE = 3.135V AT +125°C
tFALL = 3.135V AT +125°C
6
5
4
3
2
1
0
tRISE = 3.465V AT –40°C
tFALL = 3.465V AT –40°C
The JESD51 package thermal characteristics in this section are
provided for package comparison and estimation purposes only.
They are not intended for accurate system temperature calcula-
tion. System thermal simulation is required for accurate
temperature analysis that accounts for all specific 3D system
design features, including, but not limited to other heat sources,
use of heat-sinks, and the system enclosure. Thermal models are
available under the Tools and Simulations tab of the product
page.
TBD
In Table 80, airflow measurements comply with JEDEC stan-
dards JESD51-2 and JESD51-6, and the junction-to-board
measurement complies with JESD51-8. Test board design com-
plies with JEDEC standards JESD51-7 (for leaded surface
mount packages). The junction-to-case measurement complies
with MIL- STD-883 (Method 1012.1). All measurements use a
2S2P JEDEC test board.
0
5
10
15
20
25
30
LOAD CAPACITANCE (pF)
Figure 67. Driver Type A Rise and Fall Times (10% to 90%) vs. Load Capaci-
tance for All GPIO/DAI Pins Operating at Less Than 62.5 MHz
1.2
tRISE = 1.5V AT +25°C
tFALL = 1.5V AT +25°C
To estimate the junction temperature of a single device while on
a JEDEC 2S2P PCB, use:
tRISE = 1.425V AT +125°C
1.0
tFALL = 1.425V AT +125°C
tRISE = 1.575V AT –40°C
tFALL = 1.575V AT –40°C
0.8
TJ = TCASE + (JT × PD)
where:
0.6
TJ is the junction temperature (°C).
T
CASE is the case temperature (°C) measured at the top center of
TBD
0.4
the package.
JT is the typical value (junction-to-top of package characteri-
0.2
0
zation parameter) from Table 80.
PD is the power dissipation (see the Total Internal Power Dissi-
pation section for the method to calculate PD).
0
1
2
3
4
5
6
LOAD CAPACITANCE (pF)
Figure 68. Driver Type B and Driver Type C Typical Rise and Fall Times
(10% to 90%) vs. Load Capacitance for DDR3 at 100 Ω
Rev. PrD
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ADSP-21591/21593/21594/ADSP-SC591/SC592/SC594 Preliminary Technical Data
Values of JA are provided for package comparison and PCB
design considerations. JA can be used for a first-order approxi-
mation of TJ by the equation:
TJ = TA + (JA × PD)
where TA is the ambient temperature (°C).
Values of JC are provided for package comparison and PCB
design considerations when an external heat sink is required.
Note that the thermal characteristics values provided in
Table 80 are modeled values.
Table 80. Thermal Characteristics for 400 HPC and LPC
BGA_ED
Parameter Conditions
Typical Unit
JA
JA
JA
JC
JT
JT
JT
0 linear m/s air flow
TBD
TBD
TBD
TBD
TBD
TBD
TBD
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
1 linear m/s air flow
2 linear m/s air flow
0 linear m/s air flow
1 linear m/s air flow
2 linear m/s air flow
Rev. PrD
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Preliminary Technical Data ADSP-21591/21593/21594/ADSP-SC591/SC592/SC594
ADSP-SC59x 400-BALL HIGH PERIPHERAL COUNT (HPC) BGA BALL ASSIGNMENTS
The ADSP-SC59x 400-Ball HPC BGA Ball Assignments
(Numerical by Ball Number) table lists the package by ball
number.
The ADSP-SC59x 400-Ball HPC BGA Ball Assignments (Alpha-
betical by Pin Name) table lists the package by pin name.
ADSP-SC59x 400-BALL HPC BGA BALL ASSIGNMENTS (NUMERICAL BY BALL NUMBER)
Ball No.
A01
A02
A03
A04
A05
A06
A07
A08
A09
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
B01
B02
B03
B04
B05
B06
B07
B08
B09
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
C01
Pin Name
GND
Ball No.
C02
C03
C04
C05
C06
C07
C08
C09
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
D01
D02
D03
D04
D05
D06
D07
D08
D09
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
E01
Pin Name
PG_14
Ball No.
E03
E04
E05
E06
E07
E08
E09
E10
E11
E12
E13
E14
E15
E16
E17
E18
E19
E20
F01
F02
F03
F04
F05
F06
F07
F08
F09
F10
F11
F12
F13
F14
F15
F16
F17
F18
F19
F20
G01
G02
G03
Pin Name
PI_03
Ball No.
G04
G05
G06
G07
G08
G09
G10
G11
G12
G13
G14
G15
G16
G17
G18
G19
G20
H01
H02
H03
H04
H05
H06
H07
H08
H09
H10
H11
H12
H13
H14
H15
H16
H17
H18
H19
H20
J01
Pin Name
PH_15
PG_12
GND
PH_00
PH_02
JTG_TDO
PB_05
GND
VDD_INT
GND
JTG_TDI
JTG_TRST
DMC0_DQ01
DMC0_DQ05
DMC0_DQ04
DMC0_DQ11
DMC0_A14
DMC0_A10
DMC0_A15
DMC0_A09
DMC0_A04
DMC0_A00
DMC0_CS0
DMC0_CAS
GND
PB_04
DMC0_DQ00
DMC0_LDQS
DMC0_LDQS
DMC0_DQ08
DMC0_UDQS
DMC0_UDQS
DMC0_VREF0
DMC0_DQ12
DMC0_A13
DMC0_A08
DMC0_A03
DMC0_A01
DMC0_CK
DMC0_CK
PB_00
SYS_RESOUT
DMC0_LDM
GND
GND
GND
GND
VDD_DMC
VDD_DMC
VDD_DMC
GND
GND
VDD_INT
VDD_INT
VDD_INT
GND
DMC0_A02
DMC0_BA2
GND
SYS_FAULT
PF_06
PB_01
PE_15
PF_10
PE_11
PF_03
DAI1_PIN18
GND
PF_14
PF_02
PF_09
PH_08
PH_05
GND
PI_01
PH_04
PH_09
PG_13
PI_04
PH_11
PH_14
GND
PG_15
PI_02
PI_06
PG_11
GND
PH_01
VDD_INT
VDD_EXT
VDD_INT
VDD_EXT
VDD_INT
VDD_EXT
VDD_INT
VDD_EXT
VDD_EXT
VDD_INT
PF_12
JTG_TCK
PB_03
GND
JTG_TMS
SYS_HWRST
DMC0_DQ03
DMC0_DQ09
DMC0_DQ13
DMC0_RESET
DMC0_WE
DMC0_UDM
DMC0_BA0
DMC0_BA1
DMC0_A05
DMC0_RAS
GND
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
GND
DMC0_DQ02
DMC0_DQ07
DMC0_DQ06
DMC0_DQ10
DMC0_DQ15
DMC0_A12
DMC0_DQ14
DMC0_A11
DMC0_A06
DMC0_A07
DMC0_RZQ
DMC0_CKE
DMC0_ODT
GND
PB_02
PF_04
PF_11
PE_12
PF_01
DAI1_PIN17
DAI1_PIN14
SYS_CLKIN0
SYS_CLKOUT
PH_12
SYS_FAULT
PF_08
PF_00
PE_10
PF_07
GND
J02
PF_13
SYS_XTAL1
SYS_CLKIN1
SYS_BMODE1
PH_10
J03
PI_05
E02
J04
PH_13
Rev. PrD
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ADSP-21591/21593/21594/ADSP-SC591/SC592/SC594
Preliminary Technical Data
Ball No.
J05
J06
J07
J08
J09
J10
J11
J12
J13
J14
J15
J16
J17
J18
J19
J20
K01
K02
K03
K04
K05
K06
K07
K08
K09
K10
K11
K12
K13
K14
K15
K16
K17
K18
K19
K20
L01
L02
L03
L04
L05
L06
L07
L08
L09
L10
L11
L12
Pin Name
PI_00
Ball No.
L13
Pin Name
GND
Ball No.
P01
P02
P03
P04
P05
P06
P07
P08
P09
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
P20
R01
R02
R03
R04
R05
R06
R07
R08
R09
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
T01
T02
T03
T04
T05
T06
T07
T08
Pin Name
GND
Ball No.
T09
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
U01
U02
U03
U04
U05
U06
U07
U08
U09
U10
U11
U12
U13
U14
U15
U16
U17
U18
U19
U20
V01
V02
V03
V04
V05
V06
V07
V08
V09
V10
V11
V12
V13
V14
V15
V16
Pin Name
PA_15
GND
L14
GND
PA_08
PF_15
GND
L15
GND
PC_12
PG_06
GND
L16
DAI1_PIN01
DAI1_PIN04
DAI1_PIN05
HADC0_VIN3
HADC0_VIN1
GND
PD_02
PG_10
GND
L17
PD_09
DAI0_PIN09
VDD_INT
VDD_INT
GND
GND
L18
VDD_INT
GND
GND
L19
GND
L20
GND
GND
M01
M02
M03
M04
M05
M06
M07
M08
M09
M10
M11
M12
M13
M14
M15
M16
M17
M18
M19
M20
N01
N02
N03
N04
N05
N06
N07
N08
N09
N10
N11
N12
N13
N14
N15
N16
N17
N18
N19
N20
GND
PC_07
GND
PA_05
VDD_REF
VDD_REF
VDD_REF
GND
DAI0_PIN16
DAI1_PIN12
DAI1_PIN19
PC_10
GND
PA_06
PF_05
PC_08
PE_13
PA_10
DAI1_PIN16
DAI1_PIN13
DAI1_PIN02
GND
VDD_INT
VDD_EXT
VDD_PLL
VDD_PLL
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_EXT
VDD_INT
DAI1_PIN10
DAI1_PIN09
DAI1_PIN06
HADC0_VIN6
GND
GND
PD_00
VDD_INT
PC_05
PD_06
GND
DAI0_PIN15
DAI1_PIN08
HADC0_VIN4
HADC0_VIN5
SYS_XTAL0
PC_09
PB_10
PA_00
PB_11
PH_03
VDD_INT
PA_12
PH_06
PH_07
PE_01
VDD_INT
VDD_EXT
VDD_PLL
VDD_PLL
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_EXT
VDD_INT
PE_14
PE_06
PD_01
PG_00
PD_10
PG_07
PD_08
DAI0_PIN01
DAI0_PIN10
VDD_INT
PC_03
GND
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
GND
SYS_BMODE2
PA_07
GND
PC_04
PA_09
DAI0_PIN18
DAI1_PIN20
PC_14
PC_11
DAI1_PIN15
DAI1_PIN03
HADC0_VIN2
HADC0_VIN0
SYS_BMODE0
PA_02
PC_15
VDD_INT
VDD_EXT
GND
PD_04
GND
PC_06
PB_06
GND
DAI0_PIN14
DAI0_PIN17
HADC0_VREFP
VDD_ANA
GND
PB_12
GND
PA_14
PA_01
GND
PA_11
PA_04
GND
PE_02
PA_03
GND
PE_08
GND
VDD_EXT
VDD_INT
DAI0_PIN13
DAI1_PIN11
DAI1_PIN07
HADC0_VIN7
HADC0_VREFN
PC_13
PE_05
GND
PD_03
PG_02
GND
PD_07
PG_09
GND
GND
PG_04
GND
VDD_INT
VDD_INT
GND
DAI0_PIN08
DAI0_PIN05
DAI0_PIN11
GND
GND
Rev. PrD
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Preliminary Technical Data ADSP-21591/21593/21594/ADSP-SC591/SC592/SC594
Ball No.
V17
V18
V19
V20
W01
W02
W03
W04
W05
W06
W07
W08
W09
W10
W11
W12
W13
W14
W15
W16
W17
W18
W19
W20
Y01
Pin Name
PC_02
GND
PC_01
PB_15
PD_05
GND
PD_11
PD_12
PB_13
PD_14
PE_00
PE_03
PE_04
PE_09
PG_01
PE_07
DAI0_PIN04
PG_05
DAI0_PIN02
DAI0_PIN07
PB_14
DAI0_PIN20
GND
PC_00
GND
Y02
PB_08
Y03
PB_07
Y04
PB_09
Y05
PA_13
Y06
PD_15
Y07
PD_13
Y08
MLB0_CLKN
MLB0_CLKP
MLB0_DATN
MLB0_DATP
MLB0_SIGN
MLB0_SIGP
PG_03
Y09
Y10
Y11
Y12
Y13
Y14
Y15
PG_08
Y16
DAI0_PIN03
DAI0_PIN06
DAI0_PIN12
DAI0_PIN19
GND
Y17
Y18
Y19
Y20
Rev. PrD
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ADSP-21591/21593/21594/ADSP-SC591/SC592/SC594
Preliminary Technical Data
ADSP-SC59x 400-BALL HPC BGA BALL ASSIGNMENTS (ALPHABETICAL BY PIN NAME)
Pin Name
Ball No.
U13
W15
Y16
W13
V15
Y17
W16
V14
T13
U14
V16
Y18
N16
R17
P17
T18
R18
U19
Y19
W18
L16
Pin Name
Ball No.
B14
B15
A14
C13
C11
B13
B11
A13
C10
C12
D13
D14
E15
C17
A17
A18
B17
C16
A05
C06
B06
D07
C08
C07
B08
B07
A08
D08
B09
C09
A12
D09
B12
B10
E08
A06
A07
B18
D16
D10
B16
D12
A09
A10
A11
D11
Pin Name
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Ball No.
A01
A20
B02
B19
C03
C18
D04
D17
E05
E09
E13
E16
F06
F15
G01
G07
G08
G09
G10
G11
G15
H01
J06
Pin Name
GND
Ball No.
N09
N10
N11
N12
N13
P01
P07
P08
P09
P13
P14
R06
R15
T01
T05
T08
T16
U04
U17
V03
V18
W02
W19
Y01
Y20
K20
L20
K19
L19
P19
P20
M19
N19
N20
R19
B04
A04
A03
B05
C05
Y08
Y09
Y10
Y11
Y12
Y13
DAI0_PIN01
DAI0_PIN02
DAI0_PIN03
DAI0_PIN04
DAI0_PIN05
DAI0_PIN06
DAI0_PIN07
DAI0_PIN08
DAI0_PIN09
DAI0_PIN10
DAI0_PIN11
DAI0_PIN12
DAI0_PIN13
DAI0_PIN14
DAI0_PIN15
DAI0_PIN16
DAI0_PIN17
DAI0_PIN18
DAI0_PIN19
DAI0_PIN20
DAI1_PIN01
DAI1_PIN02
DAI1_PIN03
DAI1_PIN04
DAI1_PIN05
DAI1_PIN06
DAI1_PIN07
DAI1_PIN08
DAI1_PIN09
DAI1_PIN10
DAI1_PIN11
DAI1_PIN12
DAI1_PIN13
DAI1_PIN14
DAI1_PIN15
DAI1_PIN16
DAI1_PIN17
DAI1_PIN18
DAI1_PIN19
DAI1_PIN20
DMC0_A00
DMC0_A01
DMC0_A02
DMC0_A03
DMC0_A04
DMC0_A05
DMC0_A06
DMC0_A07
DMC0_A08
DMC0_A09
DMC0_A10
DMC0_A11
DMC0_A12
DMC0_A13
DMC0_A14
DMC0_A15
DMC0_BA0
DMC0_BA1
DMC0_BA2
DMC0_CAS
DMC0_CK
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
DMC0_CK
GND
DMC0_CKE
DMC0_CS0
DMC0_DQ00
DMC0_DQ01
DMC0_DQ02
DMC0_DQ03
DMC0_DQ04
DMC0_DQ05
DMC0_DQ06
DMC0_DQ07
DMC0_DQ08
DMC0_DQ09
DMC0_DQ10
DMC0_DQ11
DMC0_DQ12
DMC0_DQ13
DMC0_DQ14
DMC0_DQ15
DMC0_LDM
DMC0_LDQS
DMC0_LDQS
DMC0_ODT
DMC0_RAS
DMC0_RESET
DMC0_RZQ
DMC0_UDM
DMC0_UDQS
DMC0_UDQS
DMC0_VREF0
DMC0_WE
GND
GND
GND
GND
GND
J20
GND
K18
L17
GND
J07
GND
L18
J08
GND
M18
N18
P18
M17
M16
N17
T19
J19
J09
HADC0_VIN0
HADC0_VIN1
HADC0_VIN2
HADC0_VIN3
HADC0_VIN4
HADC0_VIN5
HADC0_VIN6
HADC0_VIN7
HADC0_VREFN
HADC0_VREFP
JTG_TCK
JTG_TDI
JTG_TDO
JTG_TMS
JTG_TRST
MLB0_CLKN
MLB0_CLKP
MLB0_DATN
MLB0_DATP
MLB0_SIGN
MLB0_SIGP
J10
J11
J12
J13
J14
J15
K01
L06
L07
L08
L09
L10
L11
L12
L13
L14
L15
M01
M20
N08
H20
K17
J18
H19
G20
T20
U20
C15
A16
E14
A15
C14
D15
Rev. PrD
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Preliminary Technical Data ADSP-21591/21593/21594/ADSP-SC591/SC592/SC594
Pin Name
PA_00
PA_01
PA_02
PA_03
PA_04
PA_05
PA_06
PA_07
PA_08
PA_09
PA_10
PA_11
PA_12
PA_13
PA_14
PA_15
PB_00
PB_01
PB_02
PB_03
PB_04
PB_05
PB_06
PB_07
PB_08
PB_09
PB_10
PB_11
PB_12
PB_13
PB_14
PB_15
PC_00
PC_01
PC_02
PC_03
PC_04
PC_05
PC_06
PC_07
PC_08
PC_09
PC_10
PC_11
PC_12
PC_13
PC_14
PC_15
Ball No.
K02
L03
Pin Name
PD_00
PD_01
PD_02
PD_03
PD_04
PD_05
PD_06
PD_07
PD_08
PD_09
PD_10
PD_11
PD_12
PD_13
PD_14
PD_15
PE_00
PE_01
PE_02
PE_03
PE_04
PE_05
PE_06
PE_07
PE_08
PE_09
PE_10
PE_11
PE_12
PE_13
PE_14
PE_15
PF_00
PF_01
PF_02
PF_03
PF_04
PF_05
PF_06
PF_07
PF_08
PF_09
PF_10
PF_11
PF_12
PF_13
PF_14
PF_15
Ball No.
U02
R03
P04
T03
V02
W01
U03
T04
R05
P05
R04
W03
W04
Y07
W06
Y06
W07
U09
V08
W08
W09
V10
U10
W12
V09
W10
F20
Pin Name
PG_00
Ball No.
U11
W11
V11
Y14
V13
W14
T11
U12
Y15
V12
T12
B03
A02
B01
C02
D03
E04
F05
G05
K03
F02
H02
K04
K05
F01
H03
G03
F03
J03
Pin Name
SYS_RESOUT
SYS_XTAL0
SYS_XTAL1
VDD_ANA
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
Ball No.
E07
PG_01
R01
E01
R20
E10
E11
E12
F07
L02
PG_02
L05
PG_03
L04
PG_04
M02
M03
N02
P02
N03
M05
V07
U08
Y05
V06
T09
A19
E17
F16
D05
E06
C04
V04
Y03
Y02
Y04
U05
U06
V05
W05
W17
V20
W20
V19
V17
U16
U18
P16
R16
T17
M04
R02
U01
N04
P03
T02
V01
N05
PG_05
PG_06
PG_07
PG_08
F08
PG_09
F09
PG_10
F10
PG_11
F11
PG_12
F12
PG_13
F13
PG_14
F14
PG_15
H07
H09
H11
H13
H14
K07
K14
M07
M14
N07
N14
G06
G12
G13
G14
H06
H08
H10
H12
H15
K06
K10
K11
K12
K13
K15
M06
M10
M11
M12
M13
M15
N06
PH_00
PH_01
PH_02
PH_03
PH_04
PH_05
PH_06
PH_07
PH_08
PH_09
PH_10
G19
H18
J17
PH_11
PH_12
PH_13
J04
K16
G18
F19
PH_14
H04
G04
J05
PH_15
PI_00
F18
PI_01
D01
F04
E03
D02
C01
H05
L01
G02
N01
J01
E20
PI_02
E19
PI_03
H17
J16
PI_04
PI_05
G17
D20
D19
C20
E18
PI_06
SYS_BMODE0
SYS_BMODE1
SYS_BMODE2
SYS_CLKIN0
SYS_CLKIN1
SYS_CLKOUT
SYS_FAULT
SYS_FAULT
SYS_HWRST
F17
E02
J02
H16
B20
C19
T10
D18
G16
D06
Rev. PrD
|
Page 131 of 143
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May 2021
ADSP-21591/21593/21594/ADSP-SC591/SC592/SC594
Preliminary Technical Data
Pin Name
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_PLL
VDD_PLL
VDD_PLL
VDD_PLL
VDD_REF
VDD_REF
VDD_REF
Ball No.
N15
P06
P15
R07
R08
R09
R10
R11
R12
R13
R14
T06
T07
T14
T15
U07
U15
K08
K09
M08
M09
P10
P11
P12
Rev. PrD
|
Page 132 of 143
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May 2021
ADSP-21591/21593/21594/ADSP-SC591/SC592/SC594
Preliminary Technical Data
CONFIGURATION OF THE ADSP-SC59x 400-BALL HIGH PERIPHERAL COUNT (HPC) BGA
Figure 70 shows an overview of signal placement on the ADSP-SC59x 400-ball HPC BGA.
TOP VIEW
A1 BALL
CORNER
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20
A
B
C
D
E
F
G
H
J
K
L
P
P
P
P
GND
I/O SIGNALS
V
M
N
P
R
T
DD_EXT
V
DD_INT
V
DD_DMC
A
V
DD_REF
A
P
V
DD_ANA
U
V
W
Y
V
DD_PLL
A1 BALL
CORNER
20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
A
B
C
D
E
F
G
H
J
P
P
P
K
L
P
M
N
P
R
T
A
U
V
W
Y
BOTTOM VIEW
Figure 70. 400-Ball HPC BGA Configuration
Rev. PrD
|
Page 133 of 143
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May 2021
ADSP-21591/21593/21594/ADSP-SC591/SC592/SC594
Preliminary Technical Data
ADSP-2159x 400-BALL LOW PERIPHERAL COUNT (LPC) BGA BALL ASSIGNMENTS
The ADSP-2159x 400-Ball LPC BGA Ball Assignments (Numer-
ical by Ball Number) table lists the package by ball number.
The ADSP-2159x 400-Ball LPC BGA Ball Assignments (Alpha-
betical by Pin Name) table lists the package by pin name.
ADSP-2159x 400-BALL LPC BGA BALL ASSIGNMENTS (NUMERICAL BY BALL NUMBER)
Ball No.
A01
A02
A03
A04
A05
A06
A07
A08
A09
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
B01
B02
B03
B04
B05
B06
B07
B08
B09
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
C01
Pin Name
GND
Ball No.
C02
C03
C04
C05
C06
C07
C08
C09
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
D01
D02
D03
D04
D05
D06
D07
D08
D09
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
E01
Pin Name
DMC0_DQ08
GND
Ball No.
E03
E04
E05
E06
E07
E08
E09
E10
E11
E12
E13
E14
E15
E16
E17
E18
E19
E20
F01
F02
F03
F04
F05
F06
F07
F08
F09
F10
F11
F12
F13
F14
F15
F16
F17
F18
F19
F20
G01
G02
G03
Pin Name
GND
Ball No.
G04
G05
G06
G07
G08
G09
G10
G11
G12
G13
G14
G15
G16
G17
G18
G19
G20
H01
H02
H03
H04
H05
H06
H07
H08
H09
H10
H11
H12
H13
H14
H15
H16
H17
H18
H19
H20
J01
Pin Name
VDD_INT
VDD_INT
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_REF
VDD_REF
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_INT
VDD_INT
GND
DMC0_DQ11
DMC0_DQ10
DMC0_UDQS
DMC0_DQ15
DMC0_UDM
PB_00
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
GND
GND
GND
GND
PB_03
PB_05
SYS_BMODE2
SYS_HWRST
JTG_TRST
PB_01
SYS_RESOUT
JTG_TDO
JTG_TMS
JTG_TDI
GND
SYS_FAULT
DMC0_WE
DMC0_A14
DMC0_A13
DMC0_A10
DMC0_A08
DMC0_BA1
DMC0_A07
DMC0_A04
GND
GND
GND
GND
DMC0_RZQ
DMC0_VREF1
DMC0_DQ03
GND
GND
DMC0_BA2
DMC0_CAS
DMC0_LDQS
DMC0_LDQS
GND
DMC0_A03
DMC0_A02
DMC0_DQ07
GND
GND
GND
VDD_INT
VDD_INT
VDD_DMC
VDD_DMC
GND
GND
DMC0_DQ09
GND
VDD_INT
VDD_INT
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_INT
VDD_INT
GND
DMC0_DQ12
DMC0_UDQS
DMC0_DQ14
DMC0_DQ13
PB_04
GND
GND
GND
GND
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
GND
GND
PB_02
GND
SYS_BMODE1
SYS_BMODE0
JTG_TCK
GND
GND
VDD_DMC
VDD_DMC
VDD_INT
VDD_INT
GND
DMC0_RESET
DMC0_A15
DMC0_A12
DMC0_A11
DMC0_A09
DMC0_BA0
DMC0_A06
GND
GND
GND
GND
GND
GND
DMC0_ODT
DMC0_CKE
DMC0_DQ01
DMC0_DQ00
GND
GND
DMC0_RAS
DMC0_CS0
DMC0_DQ04
DMC0_DQ02
GND
DMC0_A00
DMC0_A01
DMC0_DQ05
DMC0_DQ06
J02
DMC0_A05
DMC0_LDM
J03
E02
J04
DMC0_VREF0
Rev. PrD
|
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Preliminary Technical Data ADSP-21591/21593/21594/ADSP-SC591/SC592/SC594
Ball No.
J05
J06
J07
J08
J09
J10
J11
J12
J13
J14
J15
J16
J17
J18
J19
J20
K01
K02
K03
K04
K05
K06
K07
K08
K09
K10
K11
K12
K13
K14
K15
K16
K17
K18
K19
K20
L01
L02
L03
L04
L05
L06
L07
L08
L09
L10
L11
L12
Pin Name
VDD_INT
VDD_DMC
VDD_DMC
GND
Ball No.
L13
Pin Name
GND
Ball No.
P01
P02
P03
P04
P05
P06
P07
P08
P09
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
P20
R01
R02
R03
R04
R05
R06
R07
R08
R09
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
T01
T02
T03
T04
T05
T06
T07
T08
Pin Name
GND
Ball No.
T09
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
U01
U02
U03
U04
U05
U06
U07
U08
U09
U10
U11
U12
U13
U14
U15
U16
U17
U18
U19
U20
V01
V02
V03
V04
V05
V06
V07
V08
V09
V10
V11
V12
V13
V14
V15
V16
Pin Name
VDD_REF
VDD_REF
VDD_REF
VDD_REF
VDD_REF
VDD_REF
VDD_REF
VDD_EXT
GND
L14
VDD_INT
VDD_INT
GND
PA_02
L15
PA_01
L16
VDD_EXT
VDD_REF
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_REF
VDD_EXT
GND
GND
L17
GND
GND
L18
HADC0_VREFN
VDD_ANA
HADC0_VREFP
GND
GND
L19
GND
L20
GND
M01
M02
M03
M04
M05
M06
M07
M08
M09
M10
M11
M12
M13
M14
M15
M16
M17
M18
M19
M20
N01
N02
N03
N04
N05
N06
N07
N08
N09
N10
N11
N12
N13
N14
N15
N16
N17
N18
N19
N20
VDD_INT
VDD_INT
VDD_INT
VDD_INT
GND
GND
DAI1_PIN09
DAI1_PIN06
DAI1_PIN04
GND
SYS_CLKOUT
VDD_EXT
VDD_INT
VDD_INT
VDD_PLL
GND
PA_10
DMC0_CK
DMC0_CK
GND
PA_08
GND
GND
GND
GND
GND
DAI1_PIN02
GND
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
GND
GND
GND
VDD_EXT
VDD_INT
VDD_PLL
VDD_DMC
GND
GND
GND
GND
PA_04
VDD_INT
VDD_REF
VDD_EXT
GND
GND
PA_03
VDD_EXT
VDD_REF
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_REF
VDD_EXT
GND
GND
GND
GND
GND
HADC0_VIN2
HADC0_VIN3
SYS_CLKIN0
GND
GND
GND
GND
VDD_INT
VDD_INT
VDD_INT
GND
DAI1_PIN10
DAI1_PIN07
DAI1_PIN05
PA_07
PA_00
VDD_EXT
VDD_REF
VDD_INT
VDD_INT
GND
GND
PA_09
GND
GND
GND
GND
SYS_XTAL0
GND
GND
PB_06
GND
DAI1_PIN03
DAI1_PIN08
DAI1_PIN01
GND
PB_09
GND
GND
PB_12
VDD_EXT
VDD_INT
VDD_PLL
VDD_PLL
GND
GND
PA_11
GND
DAI0_PIN02
DAI0_PIN06
DAI0_PIN09
DAI0_PIN20
PC_00
VDD_INT
VDD_REF
VDD_EXT
GND
PA_05
PA_06
GND
GND
VDD_EXT
VDD_REF
VDD_REF
VDD_REF
GND
GND
PC_05
GND
HADC0_VIN0
HADC0_VIN1
GND
GND
GND
Rev. PrD
|
Page 135 of 143
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May 2021
ADSP-21591/21593/21594/ADSP-SC591/SC592/SC594
Preliminary Technical Data
Ball No.
V17
V18
V19
V20
W01
W02
W03
W04
W05
W06
W07
W08
W09
W10
W11
W12
W13
W14
W15
W16
W17
W18
W19
W20
Y01
Pin Name
DAI1_PIN19
GND
DAI1_PIN11
DAI1_PIN12
GND
GND
PB_08
PB_07
PB_13
PA_12
PA_14
PA_15
DAI0_PIN03
DAI0_PIN05
DAI0_PIN08
DAI0_PIN12
DAI0_PIN19
PB_15
PC_01
PC_03
PC_06
DAI1_PIN20
GND
GND
GND
Y02
GND
Y03
PB_10
Y04
PB_11
Y05
GND
Y06
PA_13
Y07
GND
Y08
DAI0_PIN01
DAI0_PIN04
DAI0_PIN07
DAI0_PIN10
DAI0_PIN11
GND
Y09
Y10
Y11
Y12
Y13
Y14
PB_14
Y15
PC_02
Y16
GND
Y17
PC_04
Y18
PC_07
Y19
GND
Y20
GND
Rev. PrD
|
Page 136 of 143
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May 2021
Preliminary Technical Data ADSP-21591/21593/21594/ADSP-SC591/SC592/SC594
ADSP-2159x 400-BALL LPC BGA BALL ASSIGNMENTS (ALPHABETICAL BY PIN NAME)
Pin Name
Ball No.
Y08
V09
W09
Y09
W10
V10
Y10
W11
V11
Y11
Y12
W12
W13
V12
R20
P18
R18
T20
U20
T19
U19
R19
T18
U18
V19
V20
V17
W18
D19
D20
C20
C19
A19
B20
B18
A18
A16
B16
A15
B15
B14
A14
A13
B13
B17
A17
Pin Name
DMC0_BA2
DMC0_CAS
DMC0_CK
DMC0_CK
DMC0_CKE
DMC0_CS0
DMC0_DQ00
DMC0_DQ01
DMC0_DQ02
DMC0_DQ03
DMC0_DQ04
DMC0_DQ05
DMC0_DQ06
DMC0_DQ07
DMC0_DQ08
DMC0_DQ09
DMC0_DQ10
DMC0_DQ11
DMC0_DQ12
DMC0_DQ13
DMC0_DQ14
DMC0_DQ15
DMC0_LDM
DMC0_LDQS
DMC0_LDQS
DMC0_ODT
DMC0_RAS
DMC0_RESET
DMC0_RZQ
DMC0_UDM
DMC0_UDQS
DMC0_UDQS
DMC0_VREF0
DMC0_VREF1
DMC0_WE
GND
Ball No.
E19
E20
J19
Pin Name
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Ball No.
C16
C17
C18
D02
D04
D05
D06
D07
D12
D13
D14
D15
D16
D17
D18
E03
E18
F03
F18
G03
G18
H02
H03
H08
H09
H10
H11
H12
H13
H18
J03
Pin Name
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Ball No.
K13
K17
K18
K19
K20
L02
DAI0_PIN01
DAI0_PIN02
DAI0_PIN03
DAI0_PIN04
DAI0_PIN05
DAI0_PIN06
DAI0_PIN07
DAI0_PIN08
DAI0_PIN09
DAI0_PIN10
DAI0_PIN11
DAI0_PIN12
DAI0_PIN19
DAI0_PIN20
DAI1_PIN01
DAI1_PIN02
DAI1_PIN03
DAI1_PIN04
DAI1_PIN05
DAI1_PIN06
DAI1_PIN07
DAI1_PIN08
DAI1_PIN09
DAI1_PIN10
DAI1_PIN11
DAI1_PIN12
DAI1_PIN19
DAI1_PIN20
DMC0_A00
DMC0_A01
DMC0_A02
DMC0_A03
DMC0_A04
DMC0_A05
DMC0_A06
DMC0_A07
DMC0_A08
DMC0_A09
DMC0_A10
DMC0_A11
DMC0_A12
DMC0_A13
DMC0_A14
DMC0_A15
DMC0_BA0
DMC0_BA1
J20
H20
F20
J02
L03
J01
L08
G02
H01
G01
E01
E02
D01
C02
D03
A03
A02
B03
B06
B05
A05
C01
F01
F02
H19
F19
B12
G19
A06
A04
B04
J04
L09
L10
L11
L12
L13
L16
L17
M01
M02
M08
M09
M10
M11
M12
M13
M17
M18
N02
N08
N09
N10
N11
N12
N13
N17
N18
P01
P17
P19
P20
R02
R17
T01
T04
T17
U01
U04
U05
J08
J09
G20
A12
A01
A20
B01
B02
B19
C03
C04
C05
C06
C14
C15
J10
J11
J12
GND
J13
GND
J18
GND
K01
K02
K03
K08
K09
K10
K11
K12
GND
GND
GND
GND
GND
GND
GND
Rev. PrD
|
Page 137 of 143
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May 2021
ADSP-21591/21593/21594/ADSP-SC591/SC592/SC594
Preliminary Technical Data
Pin Name
GND
Ball No.
U16
U17
V03
V04
V15
V16
V18
W01
W02
W19
W20
Y01
Y02
Y05
Y07
Y13
Y16
Y19
Y20
N19
N20
M19
M20
L18
Pin Name
PB_02
Ball No.
B08
C07
B07
C08
V05
W04
W03
V06
Y03
Y04
V07
W05
Y14
W14
V13
W15
Y15
W16
Y17
V14
W17
Y18
B10
B09
A08
N01
M03
A11
A09
C10
L01
Pin Name
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
Ball No.
G14
G15
H06
H07
H14
H15
J06
Pin Name
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
Ball No.
E17
F04
F05
F16
F17
G04
G05
G16
G17
H04
H05
H16
H17
J05
GND
PB_03
GND
PB_04
GND
PB_05
GND
PB_06
GND
PB_07
GND
PB_08
GND
PB_09
J07
GND
PB_10
K07
D08
D09
D10
D11
K04
L04
M04
M16
N04
N16
P04
P16
R04
R16
T05
T16
U06
U07
U08
U09
U10
U11
U12
U13
U14
U15
E04
E05
E06
E07
E08
E09
E10
E11
E12
E13
E14
E15
E16
GND
PB_11
GND
PB_12
GND
PB_13
GND
PB_14
GND
PB_15
GND
PC_00
J14
GND
PC_01
J15
GND
PC_02
J16
GND
PC_03
J17
GND
PC_04
K05
K14
K15
K16
L05
L14
L15
M05
M06
M14
N06
N07
N14
P06
P07
P08
P09
P10
P11
P12
P13
P14
R06
R07
R08
R09
R10
R11
R12
R13
HADC0_VIN0
HADC0_VIN1
HADC0_VIN2
HADC0_VIN3
HADC0_VREFN
HADC0_VREFP
JTG_TCK
JTG_TDI
JTG_TDO
JTG_TMS
JTG_TRST
PA_00
PC_05
PC_06
PC_07
SYS_BMODE0
SYS_BMODE1
SYS_BMODE2
SYS_CLKIN0
SYS_CLKOUT
SYS_FAULT
SYS_HWRST
SYS_RESOUT
SYS_XTAL0
VDD_ANA
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
L20
B11
C13
C11
C12
A10
N03
P03
P02
R03
R01
T02
PA_01
L19
PA_02
F06
F07
F08
F09
F10
F11
F12
F13
F14
F15
G06
G07
G08
G09
G12
G13
PA_03
PA_04
PA_05
PA_06
T03
PA_07
V01
U03
V02
U02
V08
W06
Y06
W07
W08
A07
C09
PA_08
PA_09
PA_10
PA_11
PA_12
PA_13
PA_14
PA_15
PB_00
PB_01
Rev. PrD
|
Page 138 of 143
|
May 2021
Preliminary Technical Data ADSP-21591/21593/21594/ADSP-SC591/SC592/SC594
Pin Name
VDD_INT
VDD_PLL
VDD_PLL
VDD_PLL
VDD_PLL
VDD_REF
VDD_REF
VDD_REF
VDD_REF
VDD_REF
VDD_REF
VDD_REF
VDD_REF
VDD_REF
VDD_REF
VDD_REF
VDD_REF
VDD_REF
VDD_REF
VDD_REF
VDD_REF
VDD_REF
VDD_REF
VDD_REF
Ball No.
R14
K06
L06
L07
M07
G10
G11
M15
N05
N15
P05
P15
R05
R15
T06
T07
T08
T09
T10
T11
T12
T13
T14
T15
Rev. PrD
|
Page 139 of 143
|
May 2021
ADSP-21591/21593/21594/ADSP-SC591/SC592/SC594
Preliminary Technical Data
CONFIGURATION OF THE ADSP-2159x 400-BALL LOW PERIPHERAL COUNT (LPC) BGA
Figure 71 shows an overview of signal placement on the ADSP-2159x 400-ball LPC BGA.
TOP VIEW
A1 BALL
CORNER
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20
A
B
C
D
E
F
G
H
J
P
P
K
L
GND
A
P
P
I/O SIGNALS
V
M
N
P
R
T
DD_EXT
V
DD_INT
V
DD_DMC
V
DD_REF
A
P
V
DD_ANA
U
V
W
Y
V
DD_PLL
A1 BALL
CORNER
20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
A
B
C
D
E
F
G
H
J
P
P
K
L
A
P
P
M
N
P
R
T
U
V
W
Y
BOTTOM VIEW
Figure 71. 400-Ball LPC BGA Configuration
Rev. PrD
|
Page 140 of 143
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May 2021
ADSP-21591/21593/21594/ADSP-SC591/SC592/SC594
Preliminary Technical Data
OUTLINE DIMENSIONS
Dimensions for the 17 mm × 17 mm, ADSP-2159x/ADSP-SC59x 400-ball BGA_ED package in Figure 72 are shown in millimeters.
17.10
17.00 SQ
16.90
A1 BALL
A1 BALL
CORNER
CORNER
0.90
20 18 16 14 12 10
19 17 15 13 11
8
6
4
2
3
1
9
7
5
REF
A
B
C
D
E
F
G
H
J
15.20 REF
SQ
K
L
M
N
P
R
T
U
V
W
Y
0.80
BSC
TOP VIEW
BOTTOM VIEW
DETAIL A
SIDE VIEW
1.75
1.65
1.55
1.396
1.306
1.216
0.95 REF
DETAIL A
SEATING
PLANE
0.390
0.343
0.290
0.50
Ø 0.45
0.40
COPLANARITY
0.12
Figure 72. 400-Ball Ball Grid Array, Thermally Enhanced [BGA_ED]
(BP-400-2)
Dimensions shown in millimeters
SURFACE-MOUNT DESIGN
Table 81 is provided as an aid to PCB design. For industry-standard design recommendations, refer to IPC-7351, Generic Requirements for
Surface-Mount Design and Land Pattern Standard.
Table 81. BGA Data for Use with Surface-Mount Design
Package
Package Ball Attach Type
Package Solder Mask Opening
Package Ball Pad Size
BP-400-2
Solder Mask Defined
0.4 mm Diameter
0.5 mm Diameter
Rev. PrD
|
Page 141 of 143
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May 2021
ADSP-21591/21593/21594/ADSP-SC591/SC592/SC594 Preliminary Technical Data
PLANNED AUTOMOTIVE PRODUCTION PRODUCTS
Processor
Instruction
Rate (Max)
Arm
Arm
L2 SRAM Cores Cores
–40°C to +125°C 1 MB
Instruction
Temperature
SHARC+ Package
Description
Package
Option
Model1, 2
Rate (Max)3 Range4
ADSP-21591WCBPZ8
ADSP-21591WCBPZ8RL
ADSP-21593WCBPZ8
ADSP-21593WCBPZ8RL
ADSP-21593WCBPZ10
800 MHz
800 MHz
800 MHz
800 MHz
1000 MHz
N/A
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
1
1
2
2
2
2
400-Ball BGA_ED BP-400-2
400-Ball BGA_ED BP-400-2
400-Ball BGA_ED BP-400-2
400-Ball BGA_ED BP-400-2
400-Ball BGA_ED BP-400-2
400-Ball BGA_ED BP-400-2
400-Ball BGA_ED BP-400-2
400-Ball BGA_ED BP-400-2
400-Ball BGA_ED BP-400-2
400-Ball BGA_ED BP-400-2
400-Ball BGA_ED BP-400-2
400-Ball BGA_ED BP-400-2
400-Ball BGA_ED BP-400-2
400-Ball BGA_ED BP-400-2
400-Ball BGA_ED BP-400-2
400-Ball BGA_ED BP-400-2
N/A
–40°C to +125°C 1 MB
–40°C to +125°C 2 MB
–40°C to +125°C 2 MB
–40°C to +125°C 2 MB
–40°C to +125°C 2 MB
–40°C to +125°C 2 MB
–40°C to +125°C 2 MB
–40°C to +125°C 2 MB
–40°C to +125°C 2 MB
–40°C to +125°C 2 MB
–40°C to +125°C 2 MB
–40°C to +125°C 2 MB
–40°C to +125°C 2 MB
–40°C to +125°C 2 MB
–40°C to +125°C 2 MB
N/A
N/A
N/A
ADSP21593WCBPZ10RL 1000 MHz
N/A
ADSP-21594WCBPZ8
ADSP-21594WCBPZ8RL
ADSP-21594WCBPZ10
800 MHz
800 MHz
1000 MHz
N/A
N/A
N/A
ADSP21594WCBPZ10RL 1000 MHz
ADSP-SC592WCBPZ10 1000 MHz
ADSPSC592WCBPZ10RL 1000 MHz
ADSP-SC594WCBPZ8 800 MHz
ADSP-SC594WCBPZ8RL 800 MHz
ADSP-SC594WCBPZ10 1000 MHz
N/A
1000 MHz
1000 MHz
800 MHz
800 MHz
1000 MHz
1000 MHz
ADSPSC594WCBPZ10RL 1000 MHz
1 Z =RoHS compliant part.
2 RL = Supplied on Tape and Reel.
3 N/A means not applicable.
4 Referenced temperature is junction temperature. See Preliminary Operating Conditions for junction temperature (TJ) specification.
PLANNED PRODUCTION PRODUCTS
Processor
Instruction
Rate (Max)
Arm
Arm
L2 SRAM Cores
Instruction
Temperature
SHARC+ Package
Package
Option
Model1
Rate (Max)2 Range3
Cores
Description
ADSP-21591KBPZ8
ADSP-21593KBPZ8
ADSP-21593KBPZ10
ADSP-21594KBPZ8
ADSP-21594KBPZ10
ADSP-SC592KBPZ10
ADSP-SC594KBPZ8
ADSP-SC594KBPZ10
800 MHz
800 MHz
1000 MHz
800 MHz
1000 MHz
1000 MHz
800 MHz
1000 MHz
N/A
0°C to 110°C
1 MB
2 MB
2 MB
2 MB
2 MB
2 MB
2 MB
2 MB
0
0
0
0
0
1
1
1
2
2
2
2
2
1
2
2
400-Ball BGA_ED BP-400-2
400-Ball BGA_ED BP-400-2
400-Ball BGA_ED BP-400-2
400-Ball BGA_ED BP-400-2
400-Ball BGA_ED BP-400-2
400-Ball BGA_ED BP-400-2
400-Ball BGA_ED BP-400-2
400-Ball BGA_ED BP-400-2
N/A
0°C to 110°C
0°C to 110°C
0°C to 110°C
0°C to 110°C
0°C to 110°C
0°C to 110°C
0°C to 110°C
N/A
N/A
N/A
1000 MHz
800 MHz
1000 MHz
1 Z =RoHS compliant part.
2 N/A means not applicable.
3 Referenced temperature is junction temperature. See Preliminary Operating Conditions for junction temperature (TJ) specification.
Rev. PrD
|
Page 142 of 143
| May 2021
Preliminary Technical Data ADSP-21591/21593/21594/ADSP-SC591/SC592/SC594
PRE RELEASE PRODUCTS
Processor
Instruction
Rate (Max)
Arm
Arm
L2 SRAM Cores
Instruction
Temperature
SHARC+ Package
Package
Option
Model1
Rate (Max)2 Range3, 4
Cores
Description
ADSP-21593-BPZENG
ADSP-SC594-BPZENG
1000 MHz
1000 MHz
N/A
TBD
TBD
2 MB
2 MB
0
1
2
2
400-Ball BGA_ED BP-400-2
400-Ball BGA_ED BP-400-2
1000 MHz
1 Z =RoHS compliant part.
2 N/A means not applicable.
3 Referenced temperature is junction temperature.
4 These are pre production parts. See ENG-Grade agreement for details.
©2021 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
PR26463-5/21(PrD)
Rev. PrD
|
Page 143 of 143
| May 2021
相关型号:
ADSP-TS101SAB1-000
64-BIT, 250 MHz, OTHER DSP, PBGA625, 27 X 27 MM, PLASTIC, MS-034, BGA-625
ROCHESTER
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