ADT7411_06 [ADI]
SPI®-/I2C®-Compatible, 10-Bit Digital Temperature Sensor and 8-Channel ADC; SPI®- / I2C®兼容， 10位数字温度传感器和8通道ADC
| 型号： | ADT7411_06 |
| 厂家： | 
ADI |
| 描述： | SPI®-/I2C®-Compatible, 10-Bit Digital Temperature Sensor and 8-Channel ADC |
| 文件： | 总36页 (文件大小：1315K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SPI®-/I2C®-Compatible, 10-Bit Digital
Temperature Sensor and 8-Channel ADC
ADT7411
PIN CONFIGURATION
FEATURES
10-bit temperature-to-digital converter
10-bit 8-channel ADC
DC input bandwidth
Input range: 0 V to 2.25 V and 0 V to VDD
Temperature range: −40°C to +120°C
Temperature sensor accuracy of 0.5°C
Supply range: 2.7 V to 5.5 V
Power-down current : <10 μA
Internal 2.25 VREF option
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
AIN6
AIN5
NC
AIN7
AIN8
ADT7411
AIN4
TOP VIEW
CS
SCL/SCLK
SDA/DIN
DOUT/ADD
INT/INT
AIN3
(Not to Scale)
GND
V
DD
D+/AIN1
D–/AIN2
NC = NO CONNECT
Double-buffered input logic
I2C, SPI, QSPI™, MICROWIRE™, and DSP compatible
Figure 1.
4-wire serial interface
SMBus packet error checking (PEC) compatible
16-lead QSOP
APPLICATIONS
Portable battery-powered instruments
PCs
Smart battery chargers
Telecommunications systems electronic test equipment
Domestic appliances
Process controls
GENERAL DESCRIPTION
The ADT74111 combines a 10-bit temperature-to-digital
converter and a 10-bit 8-channel ADC in a 16-lead QSOP. This
includes a band gap temperature sensor and a 10-bit ADC to
monitor and digitize the temperature reading to a resolution of
0.25°C. The ADT7411 operates from a single 2.7 V to 5.5 V
supply. The input voltage on the ADC channels has a range of
0 V to 2.25 V and the input bandwidth is dc. The reference for
the ADC channels is derived internally. The ADT7411 provides
two serial interface options: a 4-wire serial interface compatible
with SPI, QSPI, MICROWIRE, and DSP interface standards,
and a 2-wire SMBus/I2C interface. It features a standby mode
that is controlled via the serial interface.
The ADT7411’s wide supply voltage range, low supply current,
and SPI-/I2C-compatible interface make it ideal for a variety of
applications, including PCs, office equipment, and domestic
appliances.
1 Protected by U.S. Patent Numbers: 6,169,442; 5,867,012; 5,764174.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2006 Analog Devices, Inc. All rights reserved.
ADT7411
TABLE OF CONTENTS
Features .............................................................................................. 1
Theory of Operation ...................................................................... 13
Power-Up Calibration................................................................ 13
Conversion Speed....................................................................... 13
Functional Description.................................................................. 14
Analog Inputs ............................................................................. 14
Functional Description—Measurement.................................. 15
ADT7411 Registers .................................................................... 19
Serial Interface............................................................................ 29
Outline Dimensions....................................................................... 35
Ordering Guide .......................................................................... 35
Applications....................................................................................... 1
Pin Configuration............................................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Functional Block Diagram .............................................................. 6
Absolute Maximum Ratings............................................................ 7
ESD Caution.................................................................................. 7
Pin Configuration and Functional Descriptions.......................... 8
Terminology ...................................................................................... 9
Typical Performance Characteristics ........................................... 10
REVISION HISTORY
12/06–Rev. A to Rev. B
3/04–Rev. 0 to Rev. A
Updated Format..................................................................Universal
Changes to Features.......................................................................... 1
Changes to Table 1............................................................................ 3
Changes to Table 2............................................................................ 7
Changes to Theory of Operation Section.................................... 13
Changes to Figure 20...................................................................... 14
Changes to Table 7.......................................................................... 20
Changes to Table 16 Title............................................................... 22
Changes to Internal THIGH Limit Register (Read/Write)
Format Updated..................................................................Universal
Change to Equation........................................................................ 17
8/03–Revision 0: Initial Version
[Address = 25h] Section ................................................................ 25
Changes to Internal TLOW Limit Register (Read/Write)
[Address = 26h] Section ................................................................ 26
Changes to External THIGH/AIN1 VHIGH Limit Register
(Read/Write) [Address = 27h] Section ........................................ 26
Changes to External TLOW/AIN1 VLOW Limit Register
(Read/Write) [Address = 28h] Section ........................................ 26
Changes to Serial Interface Selection Section............................. 29
Changes to SPI Serial Interface Section....................................... 30
Changes to Read Operation Section ............................................ 32
Changes to Ordering Guide .......................................................... 35
Rev. B | Page 2 of 36
ADT7411
SPECIFICATIONS
VDD = 2.7 V to 5.5 V, GND = 0 V, unless otherwise noted. Temperature ranges are −40°C to +120°C.
Table 1.
Parameter1
Min
Typ
Max
Unit
Conditions/Comments
ADC DC ACCURACY
Resolution
Total Unadjusted Error (TUE)
Maximum VDD = 5 V.
10
3
Bits
2
% of FSR VDD = 2.7 V to 5.5 V.
2
% of FSR VDD = 3.3 V ( 10%).
Offset Error
Gain Error
0.5
2
% of FSR
% of FSR
Hz
ADC BANDWIDTH
ANALOG INPUTS
Input Voltage Range
DC
0
0
2.25
VDD
1
V
V
μA
pF
MΩ
AIN1 to AIN8. C4 = 0 in Control Configuration 3.
AIN1 to AIN8. C4 = 1 in Control Configuration 3.
DC Leakage Current
Input Capacitance
Input Resistance
5
10
20
THERMAL CHARACTERISTICS
Internal Temperature Sensor
Accuracy @ VDD = 3.3 V 10%
Internal reference used. Averaging on.
1.5
3
5
3
5
°C
°C
°C
°C
°C
Bits
°C
TA = 85°C.
TA = 0°C to 85°C.
TA = −40°C to +120°C.
TA = 0°C to 85°C.
TA = −40°C to +120°C.
Equivalent to 0.25°C.
Drift over 10 years if part is operated at 55°C.
External transistor = 2N3906.
TA = 85°C.
0.5
2
2
Accuracy @ VDD = 5 V 5%
3
Resolution
Long-Term Drift
External Temperature Sensor
Accuracy @ VDD = 3.3 V 10%
10
0.25
1.5
3
°C
°C
TA = 0°C to 85°C.
5
3
°C
°C
TA = −40°C to +120°C.
TA = 0°C to 85°C.
Accuracy @ VDD = 5 V 5%
2
3
5
10
°C
TA = −40°C to +120°C.
Equivalent to 0.25°C.
High level.
Resolution
Bits
μA
μA
Output Source Current
180
11
Low level.
CONVERSION TIMES
Slow ADC
Single-channel mode.
VDD/AIN
11.4
712
ms
μs
Averaging (16 samples) on.
Averaging off.
Internal Temperature
External Temperature
11.4
712
24.22
1.51
ms
μs
ms
ms
Averaging (16 samples) on.
Averaging off.
Averaging (16 samples) on.
Averaging off.
Fast ADC
VDD/AIN
712
μs
μs
ms
μs
ms
μs
Averaging (16 samples) on.
Averaging off.
Averaging (16 samples) on.
Averaging off.
Averaging (16 samples) on.
Averaging off.
44.5
2.14
134
14.25
890
Internal Temperature
External Temperature
Rev. B | Page 3 of 36
ADT7411
Parameter1
ROUND ROBIN UPDATE RATE2
Min
Typ
Max
Unit
Conditions/Comments
Time to complete one measurement cycle
through all channels.
Slow ADC @ 25°C
Averaging On
Averaging Off
Averaging On
Averaging Off
125.4
17.1
140.36
12.11
ms
ms
ms
ms
AIN1 and AIN2 are selected on Pin 7 and Pin 8.
AIN1 and AIN2 are selected on Pin 7 and Pin 8.
D+ and D– are selected on Pin 7 and Pin 8.
D+ and D− are selected on Pin 7 and Pin 8.
Fast ADC @ 25°C
Averaging On
Averaging Off
Averaging On
Averaging Off
9.26
ms
μs
ms
ms
AIN1 and AIN2 are selected on Pin 7 and Pin 8.
AIN1 and AIN2 are selected on Pin 7 and Pin 8.
D+ and D− are selected on Pin 7 and Pin 8.
D+ and D− are selected on Pin 7 and Pin 8.
578.96
24.62
3.25
ON-CHIP REFERENCE3
Reference Voltage
Temperature Coefficient
DIGITAL INPUTS1, 3
Input Current
VIL, Input Low Voltage
VIH, Input High Voltage
Pin Capacitance
SCL, SDA Glitch Rejection
2.2662 2.28
80
2.2938
V
ppm/°C
1
0.8
μA
V
V
pF
ns
VIN = 0 V to VDD.
1.89
3
10
50
All digital inputs.
Input filtering suppresses noise spikes of less
than 50 ns.
DIGITAL OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
Output High Current, IOH
Output Capacitance, COUT
INT/INT Output Saturation Voltage
2.4
V
V
mA
pF
V
ISOURCE = ISINK = 200 μA.
IOL = 3 mA.
VOH = 5 V.
0.4
1
50
0.8
I
OUT = 4 mA.
I2C TIMING CHARACTERISTICS4, 5
Serial Clock Period, t1
Data In Setup Time to SCL High, t2
Data Out Stable after SCL Low, t3
SDA Low Setup Time to SCL Low
(Start Condition), t4
2.5
50
0
μs
ns
ns
ns
Fast-mode I2C. See Figure 2.
See Figure 2.
See Figure 2.
50
SDA High Hold Time after SCL High
(Stop Condition), t5
50
ns
See Figure 2.
SDA and SCL Fall Time, t6
SDA and SCL Rise Time, t7
300
3006
ns
ns
See Figure 2.
See Figure 2.
SPI TIMING CHARACTERISTICS1, 3, 7
CS to SCLK Setup Time, t1
0
ns
ns
ns
ns
ns
ns
ns
ns
See Figure 3.
See Figure 3.
See Figure 3.
See Figure 3.
See Figure 3.
See Figure 3.
See Figure 3.
See Figure 3.
SCLK High Pulse Width, t2
SCLK Low Pulse Width, t3
Data Access Time after SCLK Falling Edge, t4
Data Setup Time Prior to SCLK Rising Edge, t5 20
Data Hold Time after SCLK Rising Edge, t6
CS to SCLK Hold Time, t7
50
50
7
35
40
0
0
CS to DOUT High Impedance, t8
Rev. B | Page 4 of 36
ADT7411
Parameter1
Min
Typ
Max
Unit
Conditions/Comments
POWER REQUIREMENTS
VDD
VDD Settling Time
IDD (Normal Mode)8
2.7
5.5
50
3
V
ms
mA
mA
μA
μA
mW
μW
VDD settles to within 10% of its final voltage level.
VDD = 3.3 V, VIH = VDD and VIL = GND.
VDD = 5 V, VIH = VDD and VIL = GND.
VDD = 3.3 V, VIH = VDD and VIL = GND.
VDD = 5 V, VIH = VDD and VIL = GND.
VDD = 3.3 V. Using normal mode.
2.2
3
IDD (Power-Down Mode)
Power Dissipation
10
10
10
33
VDD = 3.3 V. Using shutdown mode.
1 See the Terminology section.
2 Round robin is the continuous sequential measurement of the following channels: VDD, internal temperature, external temperature (AIN1, AIN2), AIN3, AIN4, AIN5,
AIN6, AIN7, and AIN8.
3 Guaranteed by design and characterization, not production tested.
4 The SDA and SCL timing is measured with the input filters turned on so as to meet the fast-mode I2C specification. Switching off the input filters improves the transfer
rate but has a negative effect on the EMC behavior of the part.
5 Guaranteed by design. Not tested in production.
6 The interface is also capable of handling the I2C standard mode rise time specification of 1000 ns.
7 All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD), and timed from a voltage level of 1.6 V.
8 IDD specification is valid for full-scale analog input voltages. Interface inactive. ADC active. Load currents excluded.
t1
SCL
t5
t2
t4
SDA
DATA IN
t3
SDA
DATA OUT
t6
t7
Figure 2. I2C Bus Timing Diagram
CS
t1
t2
t7
SCLK
DIN
t3
t5
D2
t6
D7
X
D6
X
D5
X
D4
D3
X
D1
D0
X
X
X
X
X
X
X
X
X
t8
D0
t4
DOUT
X
X
X
D7
D6
D5
D4
D3
D2
D1
Figure 3. SPI Bus Timing Diagram
200µA
I
OL
TO
OUTPUT
PIN
1.6V
C
L
50pF
200µA
I
OH
Figure 4. Load Circuit for Access Time and Bus Relinquish Time
Rev. B | Page 5 of 36
ADT7411
FUNCTIONAL BLOCK DIAGRAM
ADT7411
INTERNAL
ON-CHIP
TEMPERATURE
SENSOR
TEMPERATURE
ADDRESS POINTER
REGISTER
VALUE REGISTER
T
LIMIT
HIGH
REGISTERS
EXTERNAL
TEMPERATURE
VALUE REGISTER
T
LIMIT
LOW
REGISTERS
7
8
D+/AIN1
D–/AIN2
AIN3
V
LIMIT
LIMIT
COMPARATOR
DD
REGISTERS
AIN
HIGH
REGISTERS
LIMIT
A-TO-D
CONVERTER
9
14
2
AIN
LIMIT
AIN4
LOW
REGISTERS
ANALOG
MUX
V
DD
AIN5
VALUE REGISTER
CONTROL CONFIG. 1
REGISTER
1
AIN6
AIN1
VALUE REGISTER
CONTROL CONFIG. 2
REGISTER
16
15
AIN7
AIN2
VALUE REGISTER
CONTROL CONFIG. 3
REGISTER
AIN8
AIN3
10
INT/INT
STATUS
REGISTERS
INTERRUPT MASK
REGISTERS
VALUE REGISTER
AIN4
VALUE REGISTER
V
DD
SENSOR
AIN5
VALUE REGISTER
SPI/SMBus INTERFACE
AIN6
VALUE REGISTER
AIN7
VALUE REGISTER
AIN8
VALUE REGISTER
6
5
4
13
12
11
V
GND
CS
SCL/SCLK
SDA/DIN
DOUT/ADD
DD
Figure 5.
Rev. B | Page 6 of 36
ADT7411
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
Table 3. I2C Address Selection
ADD Pin
Rating
I2C Address
VDD to GND
−0.3 V to +7 V
Low
Float
High
1001 000
1001 010
1001 011
Analog Input Voltage to GND
Digital Input Voltage to GND
Operating Temperature Range
Storage Temperature Range
Junction Temperature
16-Lead QSOP
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
−40°C to +120°C
−65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
150°C
(TJmax − TA)/θJA
Power Dissipation1
Thermal Impedance2
θJA Junction-to-Ambient
θJC Junction-to-Case
IR Reflow Soldering
105.44°C/W
38.8°C/W
Peak Temperature
Time at Peak Temperature
Ramp-Up Rate
220°C (0°C/5°C)
10 sec to 20 sec
2°C/sec to 3°C/sec
−6°C/sec
ESD CAUTION
Ramp-Down Rate
IR Reflow Soldering (Pb-Free Package)
Peak Temperature
260°C (+0°C)
Time at Peak Temperature
Ramp-Up Rate
Ramp-Down Rate
20 sec to 40 sec
3°C/sec maximum
−6°C/sec maximum
8 minutes maximum
Time 25°C to Peak Temperature
1 Values relate to package being used on a 4-layer board.
2 Junction-to-case resistance is applicable to components featuring a
preferential flow direction, for example, components mounted on a heat
sink. Junction-to-ambient resistance is more useful for air-cooled PCB-
mounted components.
Rev. B | Page 7 of 36
ADT7411
PIN CONFIGURATION AND FUNCTIONAL DESCRIPTIONS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
AIN6
AIN5
NC
AIN7
AIN8
ADT7411
AIN4
TOP VIEW
CS
SCL/SCLK
SDA/DIN
DOUT/ADD
INT/INT
AIN3
(Not to Scale)
GND
V
DD
D+/AIN1
D–/AIN2
NC = NO CONNECT
Figure 6. Pin Configuration
Table 4. Pin Function Descriptions
Pin
No. Mnemonic Description
1
2
3
4
AIN6
AIN5
NC
Analog Input. Single-ended analog input channel. Input range is 0 V to 2.25 V or 0 V to VDD
Analog Input. Single-ended analog input channel. Input range is 0 V to 2.25 V or 0 V to VDD
No Connection.
SPI—Active Low Control Input. This is the frame synchronization signal for the input data. When CS goes low, it
enables the input register and data is transferred in on the rising edges and out on the falling edges of the subsequent
serial clocks. It is recommended that this pin be tied high to VDD when operating the serial interface in I2C mode.
.
.
CS
5
6
7
GND
VDD
D+/AIN1
Ground Reference Point for All Circuitry on the Part. Analog and digital ground.
Positive Supply Voltage, 2.7 V to 5.5 V. The supply should be decoupled to ground.
Positive Connection to External Temperature Sensor/Analog Input. Single-ended analog input channel.
Input range is 0 V to 2.25 V or 0 V to 5 V.
8
D−/AIN2
Negative Connection to External Temperature Sensor/Analog Input. Single-ended analog input channel.
Input range is 0 V to 2.25 V or 0 V to 5 V.
9
AIN3
Analog Input. Single-ended analog input channel. Input range is 0 V to 2.25 V or 0 V to VDD.
10
INT/INT
Overlimit Interrupt. The output polarity of this pin can be set to give an active low or active high interrupt when
temperature, VDD, or AIN limits are exceeded. Default is active low. Open-drain output needs a pull-up resistor.
11
DOUT/ADD DOUT—SPI Serial Data Output. Logic output. Data is clocked out of any register at this pin. Data is clocked out on the
falling edge of SCLK. Open-drain output needs a pull-up resistor.
ADD—I2C Serial Bus Address Selection Pin. Logic input. A low on this pin gives the Address 1001 000, while leaving it
floating gives the Address 1001 010 and setting it high gives the Address 1001 011. The I2C address set up by the
ADD pin is not latched by the device until after this address has been sent twice. On the eighth SCL cycle of the
second valid communication, the serial bus address is latched in. Any subsequent changes on this pin have no
effect on the I2C serial bus address.
12
13
SDA/DIN
SCL/SCLK
SDA—I2C Serial Data Input. I2C serial data to be loaded into the part’s registers is provided on this input. An open-
drain configuration needs a pull-up resistor.
DIN—SPI Serial Data Input. Serial data to be loaded into the part’s registers is provided on this input. Data is
clocked into a register on the rising edge of SCLK. An open-drain configuration needs a pull-up resistor.
Serial Clock Input. This is the clock input for the serial port. The serial clock is used to clock data out of any register
of the ADT7411 and to clock data into any register that can be written to. An open-drain configuration needs a pull-
up resistor.
14
15
16
AIN4
AIN8
AIN7
Analog Input. Single-ended analog input channel. Input range is 0 V to 2.25 V or 0 V to VDD
Analog Input. Single-ended analog input channel. Input range is 0 V to 2.25 V or 0 V to VDD
Analog Input. Single-ended analog input channel. Input range is 0 V to 2.25 V or 0 V to VDD
.
.
.
Rev. B | Page 8 of 36
ADT7411
TERMINOLOGY
Relative Accuracy
Long-Term Temperature Drift
Relative accuracy or integral nonlinearity (INL) is a measure of
the maximum deviation, in LSBs, from a straight line passing
through the endpoints of the ADC transfer function. A typical
INL vs. code plot can be seen in Figure 10.
This is a measure of the change in temperature error with the
passage of time. It is expressed in degrees Celsius. The concept
of long-term stability has been used for many years to describe
by what amount an IC’s parameter would shift during its
lifetime. This is a concept that has been typically applied to both
voltage references and monolithic temperature sensors.
Unfortunately, ICs cannot be evaluated at room temperature
(25°C) for 10 years or so to determine this shift. As a result,
manufacturers typically perform accelerated lifetime testing of
ICs by operating ICs at elevated temperatures (between 125°C
and 150°C) over a shorter period (typically between 500 hours
and 1,000 hours). Because of this operation, the lifetime of an
IC is significantly accelerated due to the increase in rates of
reaction within the semiconductor material.
Total Unadjusted Error (TUE)
Total unadjusted error is a comprehensive specification that
includes the sum of the relative accuracy error, gain error, and
offset error under a specified set of conditions.
Offset Error
This is a measure of the offset error of the ADC. It can be
negative or positive. It is expressed in mV.
Gain Error
This is a measure of the span error of the ADC. It is the
deviation in slope of the actual ADC transfer characteristic
from the ideal expressed as a percentage of the full-scale range.
DC Power Supply Rejection Ratio (PSRR)
The power supply rejection ratio (PSRR) is defined as the ratio
of the power in the ADC output at full-scale frequency f to the
power of a 100 mV sine wave applied to the VDD supply of
frequency fs.
Offset Error Drift
This is a measure of the change in offset error with changes in
temperature. It is expressed in ppm of full-scale range/°C.
PSRR (dB) = 10 log(Pf/Pfs)
Gain Error Drift
This is a measure of the change in gain error with changes in
temperature. It is expressed in ppm of full-scale range/°C.
where:
Pf is the power at frequency f in ADC output.
Pfs is the power at frequency fs coupled into the VDD supply.
Round Robin
This term describes the ADT7411 cycling through the available
measurement channels in sequence, taking a measurement on
each channel.
Rev. B | Page 9 of 36
ADT7411
TYPICAL PERFORMANCE CHARACTERISTICS
2.00
1.0
0.8
ADC OFF
1.95
1.90
1.85
1.80
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
1.75
2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5
0
200
400
600
800
1000
V
(V)
ADC CODE
CC
Figure 7. Supply Current vs. Supply Voltage at 25°C
Figure 10. ADC INL with Ref = VDD (3.3 V)
0
–10
–20
–30
–40
–50
–60
1.5
1.0
0.5
0
±100mV RIPPLE ON V
CC
EXTERNAL TEMPERATURE @ 5V
INTERNAL TEMPERATURE @ 3.3V
V
V
= 2.25V
= 3.3V
REF
DD
TEMPERATURE = 25°C
–0.5
–1.0
EXTERNAL TEMPERATURE @ 3.3V
INTERNAL TEMPERATURE @ 5V
–30
0
40
85
120
1
10
100
TEMPERATURE (°C)
FREQUENCY (kHz)
Figure 11. Temperature Error at 3.3 V and 5 V
Figure 8. PSRR vs. Supply Ripple Frequency
3
2
7
6
5
4
3
2
1
0
V
= 3.3V
DD
OFFSET ERROR
1
0
–1
–2
–3
–4
GAIN ERROR
–40
–20
0
20
40
60
80
100
120
2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5
(V)
TEMPERATURE (°C)
V
CC
Figure 12. ADC Offset Error and Gain Error vs. Temperature
Figure 9. Power-Down Current vs. Supply Voltage at 25°C
Rev. B | Page 10 of 36
ADT7411
15
10
0
–10
–20
–30
–40
–50
–60
V
= 3.3V
DD
V
= 3.3V
DD
TEMPERATURE = 25°C
5
D+ TO GND
0
–5
D+ TO V
CC
–10
–15
–20
–25
0
10
20
30
40
50
60
70
80
90 100
0
5
10
15
20
25
30
35
40
45
50
PCB LEAKAGE RESISTANCE (MΩ)
CAPACITANCE (nF)
Figure 13. External Temperature Error vs. PCB Leakage Resistance
Figure 16. External Temperature Error vs. Capacitance Between D+ and D−
10
70
V
= 3.3V
V
= 3.3V
DD
DD
COMMON-MODE
VOLTAGE = 100mV
DIFFERENTIAL-MODE
VOLTAGE = 100mV
8
6
60
50
40
30
20
10
0
4
2
0
–2
–4
–6
–10
1
100
200
300
400
500
600
1
100
200
300
400
500
600
NOISE FREQUENCY (MHz)
NOISE FREQUENCY (Hz)
Figure 14. External Temperature Error vs.
Common-Mode Noise Frequency
Figure 17. External Temperature Error vs. Differential Mode Noise Frequency
3
0.6
V
= 3.3V
DD
OFFSET ERROR
2
1
0
0.4
0.2
0
–0.2
–0.4
–0.6
–1
–2
–3
±250mV
GAIN ERROR
1
100
200
300
400
500
600
2.7
3.1
3.5
3.9
4.3
(V)
4.7
5.1
5.5
NOISE FREQUENCY (Hz)
V
DD
Figure 15. ADC Offset Error and Gain Error vs. VDD
Figure 18. Internal Temperature Error vs. Power Supply Noise Frequency
Rev. B | Page 11 of 36
ADT7411
140
120
100
80
EXTERNAL TEMPERATURE
INTERNAL TEMPERATURE
60
40
TEMPERATURE OF
ENVIRONMENT
CHANGED HERE
20
0
0
10
20
30
40
50
60
TIME (s)
Figure 19. Temperature Sensor Response to Thermal Shock
Rev. B | Page 12 of 36
ADT7411
THEORY OF OPERATION
After the power-up calibration routine, the ADT7411 goes into
idle mode. In this mode, the device is not performing any
measurements and is fully powered up.
The dual serial interface defaults to the I2C protocol on power-
up. To select and lock in the SPI protocol, follow the selection
process as described in the Serial Interface Selection section.
The I2C protocol cannot be locked in, while the SPI protocol on
selection is automatically locked in. The interface can only be
switched back to I2C when the device is powered off and on.
To begin monitoring, write to the Control Configuration 1
register (Address 18h) and set Bit C0 = 1. The ADT7411 goes
into its power-up default measurement mode, which is round
robin. The device performs measurements in the following
channel sequence:
When using I2C, the pin should be tied to either VDD or GND.
CS
There are a number of different operating modes on the
ADT7411 devices and all of them can be controlled by the
configuration registers. These features consist of enabling and
1. VDD channel
2. Internal temperature sensor channel
disabling interrupts, polarity of the INT/
pin, enabling and
INT
3. External temperature sensor channel (or AIN1 and AIN2 if
external diode is not set up)
disabling the averaging on the measurement channels, SMBus
timeout, and software reset.
4. AIN3
5. AIN4
6. AIN5
7. AIN6
8. AIN7
9. AIN8
POWER-UP CALIBRATION
It is recommended that no communication to the part is initiated
until approximately 5 ms after VDD has settled to within 10% of its
final value. It is generally accepted that most systems take a
maximum of 50 ms to power up. Power-up time is directly
related to the amount of decoupling on the voltage supply line.
During the 5 ms after VDD has settled, the part is performing a
calibration routine; any communication to the device interrupts
this routine and can cause erroneous temperature measurements.
If it is not possible to have VDD at its nominal value by the time
50 ms elapses or that communication to the device starts prior
to VDD settling, then it is recommended that a measurement be
taken on the VDD channel before a temperature measurement
is taken. The VDD measurement is used to calibrate out any
temperature measurement error due to different supply
voltage values.
Once it finishes taking measurements on the AIN8 channel, the
device immediately loops back to start taking measurements on
the VDD channel and repeats the same cycle as before. This loop
continues until the monitoring is stopped by resetting Bit C0 of
the Control Configuration 1 register to 0. It is also possible to
continue monitoring as well as switching to single-channel
mode by writing to the Control Configuration 2 register
(Address 19h) and setting Bit C4 = 1. Further explanations of
the single-channel and round robin measurement modes are
given in the Single-Channel Measurement and Round Robin
Measurement sections. All measurement channels have
averaging enabled on them at power-up. Averaging forces the
device to take an average of 16 readings before giving a final
measured result. To disable averaging and consequently
decrease the conversion time by a factor of 16, set C5 = 1 in
the Control Configuration 2 register.
CONVERSION SPEED
The internal oscillator circuit used by the ADC has the
capability to output two different clock frequencies. This means
that the ADC is capable of running at two different speeds when
doing a conversion on a measurement channel. Therefore, the
time taken to perform a conversion on a channel can be reduced
by setting C0 of the Control Configuration 3 register
(Address 1Ah). This increases the ADC clock speed from
1.4 Hz to 22 kHz. At the higher clock speed, the analog filters
on the D+ and D− input pins (external temperature sensor) are
switched off. This is why the power-up default setting is to have
the ADC working at the slow speed. The typical times for fast
and slow ADC speeds are given in Table 1.
There are eight single-ended analog input channels on the
ADT7411: AIN1 to AIN8. AIN1 and AIN2 are multiplexed with
the external temperature sensors D+ and D− terminals. Bits C1
and C2 of the Control Configuration 1 register (Address 18h)
are used to select between AIN1/2 and the external temperature
sensor. The input range on the analog input channels is
dependent on whether the ADC reference used is the internal
V
REF or VDD. To meet linearity specifications, it is recommended
The ADT7411 powers up with averaging on. This means every
channel is measured 16 times and internally averaged to reduce
noise. The conversion time can also be reduced by turning the
averaging off. This is done by setting Bit C5 of the Control
Configuration 2 register (Address 19h) to a 1.
that the maximum VDD value is 5 V. Bit C4 of the Control
Configuration 3 register is used to select between the internal
reference and VDD as the analog inputs’ ADC reference.
Rev. B | Page 13 of 36
ADT7411
FUNCTIONAL DESCRIPTION
ANALOG INPUTS
INT V
V
DD
REF
REF
CAP DAC
Single-Ended Inputs
SAMPLING
CAPACITOR
A
AIN
The ADT7411 offers eight single-ended analog input channels.
The analog input range is from 0 V to 2.25 V or 0 V to VDD. To
maintain the linearity specification, it is recommended that the
maximum VDD value be set at 5 V. Selection between the two
input ranges is done by Bit C4 of the Control Configuration 3
register (Address 1Ah). Setting this bit to 0 sets up the analog
input ADC reference to be sourced from the internal voltage
reference of 2.25 V. Setting the bit to 1 sets up the ADC
SW1
B
ACQUISITION
PHASE
SW2
CONTROL
LOGIC
REF/2
COMPARATOR
Figure 21. ADC Acquisition Phase
When the ADC eventually goes into conversion phase (see
Figure 22) SW2 opens and SW1 moves to Position B, causing
the comparator to become unbalanced. The control logic and
the DAC are used to add and subtract fixed amounts of charge
from the sampling capacitor to bring the comparator back into
a balanced condition. When the comparator is rebalanced, the
conversion is complete. The control logic generates the ADC
output code. Figure 24 shows the ADC transfer function for
single-ended analog inputs.
reference to be sourced from VDD
.
The ADC resolution is 10 bits and is mostly suitable for dc
input signals or very slowly varying ac signals. Bit C1 and
Bit C2 of the Control Configuration 1 register (Address 18h) are
used to set up Pin 7 and Pin 8 as AIN1 and AIN2. Figure 20
shows the overall view of the 8-channel analog input path.
AIN1
M
U
L
T
I
P
L
E
X
E
R
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
INT V
REF
V
DD
TO ADC
VALUE
REGISTER
10-BIT
ADC
REF
CAP DAC
SAMPLING
CAPACITOR
A
AIN
SW1
B
CONVERSION
PHASE
Figure 20. Octal Analog Input Path
SW2
CONTROL
LOGIC
Converter Operation
REF/2
The analog input channels use a successive approximation ADC
based around a capacitor DAC. Figure 21 and Figure 22 show
simplified schematics of the ADC. Figure 21 shows the ADC
during acquisition phase. SW2 is closed and SW1 is in Position A.
The comparator is held in a balanced condition and the
sampling capacitor acquires the signal on AIN.
COMPARATOR
Figure 22. ADC Conversion Phase
V
DD
I
N × I
I
BIAS
OPTIONAL CAPACITOR, UP TO
3nF MAX. CAN BE ADDED TO
IMPROVE HIGH FREQUENCY
NOISE REJECTION IN NOISY
ENVIRONMENTS
V
OUT+
D+
REMOTE
TO ADC
C1
D–
SENSING
TRANSISTOR
(2N3906)
BIAS
DIODE
V
OUT–
LOW-PASS
FILTER
fC = 65kHz
Figure 23. Signal Conditioning for External Diode Temperature Sensor
Rev. B | Page 14 of 36
ADT7411
V
DD
ADC Transfer Function
I
N × I
I
BIAS
The output coding of the ADT7411 analog inputs is straight
binary. The designed code transitions occur midway between
successive integer LSB values (that is, 1/2 LSB, 3/2 LSB). The
LSB is VDD/1024 or Int VREF/1024, Int VREF = 2.25 V. The ideal
transfer characteristic is shown in Figure 24.
V
OUT+
TO ADC
BIAS
DIODE
INTERNAL
SENSE
TRANSISTOR
V
OUT–
111...111
111...110
Figure 25. Top Level Structure of Internal Temperature Sensor
111...000
011...111
100Ω
AIN
1LSB = INT V
/1024
REF
1LSB = V /1024
DD
4pF
000...010
000...001
000...000
Figure 26. Equivalent Analog Input ESD Circuit
0V 1/2 LSB
+V
– 1LSB
REF
ANALOG INPUT
AIN Interrupts
Figure 24. Transfer Function
The measured results from the AIN inputs are compared with
the AIN VHIGH (greater than comparison) and VLOW (less than or
equal to comparison) limits. An interrupt occurs if the AIN
inputs exceed or equal the limit registers. These voltage limits
are stored in on-chip registers. Note that the limit registers are
eight bits long while the AIN conversion result is 10 bits long.
If the voltage limits are not masked out, any out-of-limit
comparisons generate flags that are stored in the Interrupt
Status 1 register (Address 00h) and one or more out-of-limit
To work out the voltage on any analog input channel, the
following method is used.
1 LSB = Reference (V)/1024
Convert the value read back from the AIN value register into
decimal.
AIN Voltage = AIN Value (d) × LSB Size
where d is the decimal.
results will cause the INT/
output to pull either high or
INT
low, depending on the output polarity setting. It is good design
practice to mask out interrupts for channels that are of no
concern to the application. Figure 27 shows the interrupt
structure for the ADT7411. It shows a block diagram
representation of how the various measurement channels
Example:
Internal reference used. Therefore, VREF = 2.25 V.
AIN Value = 512d
affect the INT/
pin.
INT
1 LSB Size = 2.25 V/1024 = 2.197 × 10−3
AIN Voltage = 512 × 2.197 × 10−3
= 1.125 V
FUNCTIONAL DESCRIPTION—MEASUREMENT
Temperature Sensor
The ADT7411 contains an ADC with special input signal
conditioning to enable operation with external and on-chip
diode temperature sensors. When the ADT7411 is operating in
single-channel mode, the ADC continually processes the
measurement taken on one channel only. This channel is
preselected by Bit C0 to Bit C3 in the Control Configuration 2
register (Address 19h). When in round robin mode, the analog
input multiplexer sequentially selects the VDD input channel,
on-chip temperature sensor to measure its internal temperature,
the external temperature sensor, or an AIN channel, and then
the rest of the AIN channels. These signals are digitized by the
ADC and the results stored in the various value registers.
Analog Input ESD Protection
Figure 26 shows the input structure that provides ESD protec-
tion on any of the analog input pins. The diode provides the
main ESD protection for the analog inputs. Care must be taken
that the analog input signal never drops below the GND rail by
more than 200 mV. If this happens, the diode becomes forward
biased and starts conducting current into the substrate. The
4 pF capacitor is the typical pin capacitance and the resistor is a
lumped component made up of the on resistance of the
multiplexer switch.
Rev. B | Page 15 of 36
ADT7411
The measured results from the temperature sensors are
compared with the internal and external THIGH and TLOW
limits. These temperature limits are stored in on-chip registers.
If the temperature limits are not masked out, any out-of-limit
comparisons generate flags that are stored in Interrupt Status 1
reading by the I2C or SPI interface. The user has the option
of disabling the averaging by setting Bit 5 in the Control
Configuration 2 register (Address 19h). The ADT7411
defaults on power-up with the averaging enabled.
The second method is applicable when the part is in round
robin measurement mode. The part measures both the internal
and external temperature sensors as it cycles through all possible
measurement channels. The two temperature channels are
measured each time the part runs a round robin sequence.
In round robin mode, the part is continuously measuring all
channels.
INT
register. One or more out-of-limit results causes the INT/
output to pull either high or low, depending on the output
polarity setting.
Theoretically, the temperature measuring circuit can measure
temperatures from –128°C to +127°C with a resolution of
0.25°C. However, temperatures outside TA are outside the
guaranteed operating temperature range of the device.
Temperature measurement from –128°C to +127°C is
possible using an external sensor.
Temperature measurement is also initiated after every read
or write to the part when the part is in either single-channel
measurement mode or round robin measurement mode. Once
serial communication has started, any conversion in progress
is stopped and the ADC is reset. Conversion starts again
immediately after the serial communication has finished.
The temperature measurement proceeds normally as
previously described.
Temperature measurement is initiated by three methods. The
first method is applicable when the part is in single-channel
measurement mode. The temperature is measured 16 times and
internally averaged to reduce noise. In single-channel mode, the
part is continuously monitoring the selected channel, that is, as
soon as one measurement is taken, another one is started on the
same channel. The total time to measure a temperature channel
with the ADC operating at slow speed is typically 11.4 ms
(712 μs × 16) for the internal temperature sensor and 24.22 ms
(1.51 ms × 16) for the external temperature sensor. The new
temperature value is stored in two 8-bit registers and ready for
S/W RESET
INTERNAL
TEMP
INTERRUPT
STATUS
REGISTER 1
(TEMP AND
AIN1 TO AIN4)
EXTERNAL
TEMP
V
DD
WATCHDOG
LIMIT
COMPARISONS
INTERRUPT
INT/INT
(LATCHED OUTPUT)
MASK
REGISTERS
INTERRUPT
STATUS
DIODE
FAULT
REGISTER 2
(V AND
DD
AIN5 TO AIN8)
AIN1 TO AIN4
AIN5 TO AIN8
INT/INT
ENABLE BIT
READ RESET
CONTROL
CONFIGURATION
REGISTER 1
Figure 27. ADT7411 Interrupt Structure
Rev. B | Page 16 of 36
ADT7411
VDD Monitoring
On-Chip Reference
The ADT7411 also has the capability of monitoring its own
power supply. The part measures the voltage on its VDD pin to a
resolution of 10 bits. The resulting value is stored in two 8-bit
registers, with the 2 LSBs stored in register Address 03h and the
8 MSBs stored in register Address 06h. This allows the user to
have the option of just doing a 1-byte read if 10-bit resolution is
not important. The measured result is compared with the VHIGH
and VLOW limits. If the VDD interrupt is not masked out then any
out-of-limit comparison generates a flag in the Interrupt Status 2
register, and one or more out-of-limit results causes the
The ADT7411 has an on-chip 1.125 V band gap reference that
is gained up by a switched capacitor amplifier to give an output
of 2.25 V. The amplifier is powered up for the duration of the
device monitoring phase and is powered down once monitoring
is disabled. This saves on current consumption. The internal
reference is used as the reference for the ADC.
Round Robin Measurement
Upon power-up, the ADT7411 goes into round robin mode but
monitoring is disabled. Setting Bit C0 of the Configuration 1
register to 1 enables conversions. It sequences through all
available channels, taking a measurement from each in the
following order: VDD, internal temperature sensor, external
temperature sensor/(AIN1 and AIN2), AIN3, AIN4, AIN5,
AIN6, AIN7, and AIN8. Pin 7 and Pin 8 can be configured as
either external temperature sensor pins or standalone analog
input pins. Once conversion is completed on the AIN8 channel,
the device loops around for another measurement cycle.
This method of taking a measurement on all the channels in
one cycle is called round robin. Setting Bit 4 of the Control
Configuration 2 register (Address 19h) disables the round robin
mode and in turn sets up the single-channel mode. The single-
channel mode is where only one channel, for example, the
internal temperature sensor, is measured in each conversion cycle.
INT
INT/
output to pull either high or low, depending on the
output polarity setting.
Measuring the voltage on the VDD pin is regarded as monitoring
a channel along with the internal, external, and AIN channels.
The user can select the VDD channel for single-channel
measurement by setting Bit C4 = 1 and by setting Bit C0 to
Bit C2 to all 0s in the Control Configuration 2 register.
When measuring the VDD value, the reference for the ADC is
sourced from the internal reference. Table 5 shows the data
format. As the maximum VDD voltage measurable is 7 V,
internal scaling is performed on the VDD voltage to match the
2.25 V internal reference value. The following is an example of
how the transfer function works.
The time taken to monitor all channels will normally not be of
interest, as the most recently measured value can be read at any
time. For applications where the round robin time is important,
typical times at 25°C are given in Table 1.
ADC Reference = 2.25 V
1 LSB = ADC Reference/210 = 2.25/1024 = 2.197 mV
Scale Factor = Full Scale VCC/ADC Reference = 7/2.25 = 3.11
Conversion Result = VDD/(Scale Factor × LSB Size)
= 5/(3.11 × 2.197 mV)
Single-Channel Measurement
Setting Bit C4 of the Control Configuration 2 register enables
the single-channel mode and allows the ADT7411 to focus on
one channel only. A channel is selected by writing to Bit C0 to
Bit C3 in the Control Configuration 2 register. For example,
to select the VDD channel for monitoring, write to the Control
Configuration 2 register and set C4 to 1 (if not done so already),
then write all 0s to Bit C0 to Bit C3. All subsequent conversions
are done on the VDD channel only. To change the channel selection
to the internal temperature channel, write to the Control
Configuration 2 register and set C0 = 1. When measuring in
single-channel mode, conversions on the channel selected occur
directly after each other. Any communication to the ADT7411
stops the conversions, but they are restarted once the read or
write operation is completed.
= 2DBh
Table 5. VDD Data Format, VREF = 2.25 V
Digital Output
VDD Value (V)
Binary
Hex
16E
18B
1B7
200
249
292
2DB
324
36D
3B6
3FF
2.5
2.7
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
7.0
01 0110 1110
01 1000 1011
01 1011 0111
10 0000 0000
10 0100 1001
10 1001 0010
10 1101 1011
11 0010 0100
11 0110 1101
11 1011 0110
11 1111 1111
Rev. B | Page 17 of 36
ADT7411
Temperature Measurement Method
environment, C1 is provided as a noise filter. See the Layout
Considerations section for more information on C1.
Internal Temperature Measurement
The ADT7411 contains an on-chip, band gap temperature
sensor whose output is digitized by the on-chip ADC. The
temperature data is stored in the internal temperature value
register. As both positive and negative temperatures can be
measured, the temperature data is stored in twos complement
format, as shown in Table 6. The thermal characteristics of the
measurement sensor could change and therefore an offset is
added to the measured value to enable the transfer function to
match the thermal characteristics. This offset is added before
the temperature data is stored. The offset value used is stored in
the internal temperature offset register.
To measure ꢀVBE, the sensor is switched between operating
currents of I, and N × I. The resulting waveform is passed
through a low-pass filter to remove noise, then to a chopper-
stabilized amplifier that performs the functions of amplification
and rectification of the waveform to produce a dc voltage
proportional to ꢀVBE. This voltage is measured by the ADC
to give a temperature output in 10-bit twos complement
format. To further reduce the effects of noise, digital filtering is
performed by averaging the results of 16 measurement cycles.
Layout Considerations
Digital boards can be electrically noisy environments, and care
must be taken to protect the analog inputs from noise, particularly
when measuring the very small voltages from a remote diode
sensor. The following precautions should be taken:
External Temperature Measurement
The ADT7411 can measure the temperature of one external
diode sensor or diode-connected transistor.
1. Place the ADT7411 as close as possible to the remote
sensing diode. Provided that the worst noise sources, such
as clock generators, data/address buses, and CRTs, are
avoided, this distance can be 4 inches to 8 inches.
The forward voltage of a diode or diode-connected transistor,
operated at a constant current, exhibits a negative temperature
coefficient of about −2 mV/°C. Unfortunately, the absolute
value of VBE varies from device to device, and individual
calibration is required to null this out, so the technique is
unsuitable for mass production.
2. Route the D+ and D− tracks close together, in parallel,
with grounded guard tracks on each side. Provide a ground
plane under the tracks if possible.
The technique used in the ADT7411 is to measure the change
in VBE when the device is operated at two different currents.
3. Use wide tracks to minimize inductance and reduce noise
pickup. A 10 mil track minimum width and spacing is
recommended (see Figure 28).
This is given by
ΔVBE = KT/q × In (N)
where:
GND
10 MIL
10 MIL
K is Boltzmann’s constant.
q is the charge on the carrier.
T is the absolute temperature in Kelvin.
N is the ratio of the two currents.
D+
D–
10 MIL
10 MIL
10 MIL
10 MIL
Figure 23 shows the input signal conditioning used to measure
the output of an external temperature sensor. This figure shows
the external sensor as a substrate transistor, provided for
temperature monitoring on some microprocessors, but it
could equally well be a discrete transistor.
GND
10 MIL
Figure 28. Arrangement of Signal Tracks
4. Try to minimize the number of copper/solder joints, which
can cause thermocouple effects. Where copper/solder
joints are used, make sure that they are in both the D+ and
D− path and at the same temperature.
If a discrete transistor is used, the collector is not grounded and
should be linked to the base. If a PNP transistor is used, the
base is connected to the D− input and the emitter to the D+
input. If an NPN transistor is used, the emitter is connected to
the D− input and the base to the D+ input. A 2N3906 is
recommended as the external transistor.
Thermocouple effects should not be a major problem as
1°C corresponds to about 240 μV, and thermocouple
voltages are about 3 μV/°C of temperature difference.
Unless there are two thermocouples with a big temperature
differential between them, thermocouple voltages should
be much less than 200 mV.
To prevent ground noise from interfering with the
measurement, the more negative terminal of the sensor is not
referenced to ground but is biased above ground by an internal
diode at the D− input. As the sensor is operating in a noisy
Rev. B | Page 18 of 36
ADT7411
5. Place 0.1 μF bypass and 2200 pF input filter capacitors
close to the ADT7411.
Interrupts
The measured results from the internal temperature sensor,
external temperature sensor, VDD pin, and AIN inputs are
compared with their THIGH/VHIGH (greater than comparison)
and TLOW/VLOW (less than or equal to comparison) limits. An
interrupt occurs if the measurement exceeds or equals the limit
registers. These limits are stored in on-chip registers. Note that
the limit registers are eight bits long while the conversion results
are 10 bits long. If the limits are not masked out, then any out-
of-limit comparisons generate flags that are stored in the
Interrupt Status 1 register (Address 00h) and the Interrupt
Status 2 register (Address 01h). One or more out-of limit results
6. If the distance to the remote sensor is more than 8 inches,
the use of twisted-pair cable is recommended. This works
up to about 6 feet to 12 feet.
7. For long distances (up to 100 feet) use shielded twisted-
pair cable, such as Belden #8451 microphone cable.
Connect the twisted pair to D+ and D− and the shield to
GND close to the ADT7411. Leave the remote end of the
shield unconnected to avoid ground loops.
Because the measurement technique uses switched current
sources, excessive cable and/or filter capacitance can affect the
measurement. When using long cables, the filter capacitor can
be reduced or removed.
INT
causes the INT/
output to pull either high or low depending
on the output polarity setting. It is good design practice to mask
out interrupts for channels that are of no concern to the
application.
Cable resistance can also introduce errors. A series resistance of
1 Ω introduces about 0.5°C error.
Figure 27 shows the interrupt structure for the ADT7411.
It gives a block diagram representation of how the various
INT
measurement channels affect the INT/
pin.
Temperature Value Format
One LSB of the ADC corresponds to 0.25°C. The ADC can
theoretically measure a temperature span of 255°C. The internal
temperature sensor is guaranteed to a low value limit of −40°C.
It is possible to measure the full temperature span using the
external temperature sensor. The temperature data format is
shown in Table 6.
ADT7411 REGISTERS
The ADT7411 contains registers that are used to store the
results of external and internal temperature measurements, VDD
value measurements, analog input measurements, high and low
temperature limits, supply voltage and analog input limits,
configure multipurpose pins, and generally control the device.
See Table 7 for a detailed description of these registers.
The result of the internal or external temperature measurements is
stored as twos complement format in the temperature value
registers and is compared with limits programmed into the
internal or external high and low registers.
The register map is divided into registers of 8 bits. Each register
has its own individual address but some consist of data that is
linked with other registers. These registers hold the 10-bit
conversion results of measurements taken on the temperature,
Table 6. Temperature Data Format (Internal and External
Temperature)
VDD, and AIN channels. For example, the MSBs of the VDD
Temperature (°C)
Digital Output
11 0110 0000
11 1001 1100
11 1101 1000
11 1111 1111
00 0000 0000
00 0000 0001
00 0010 1000
00 0110 0100
00 1100 1000
01 0010 1100
01 1001 0000
01 1010 0100
01 1111 0100
measurement are stored in Register Address 06h while the two
LSBs are stored in Register Address 03h. The link involved
between these types of registers is that when the LSB register is
read first, the MSB registers associated with that LSB register
are locked out to prevent any updates. To unlock these MSB
registers the user has only to read any one of them, which has
the effect of unlocking all previously locked out MSB registers.
Therefore, for the example given above, if Register 03h is read
first, MSB Register 06h and Register 07h would be locked out to
prevent any updates to them. If Register 06h is read this register,
then Register 07h would be subsequently unlocked.
−40
−25
−10
−0.25
0
+0.25
+10
+25
+50
+75
+100
+105
+125
FIRST READ
COMMAND
LSB
REGISTER
OUTPUT
DATA
Temperature Conversion Formula:
LOCK ASSOCIATED
MSB REGISTERS
Positive Temperature = ADC Code/4
Negative Temperature = (ADC Code1 − 512)/4
Figure 29. Phase 1 of 10-Bit Read
1 DB9 is removed from the ADC Code.
Rev. B | Page 19 of 36
ADT7411
SECOND READ
COMMAND
MSB
REGISTER
OUTPUT
DATA
Power-
on
Default
RD/WR
Address Name
2Eh
2Fh
30h
31h
32h
33h
34h
35h
36h
37h
38h
39h-4Ch
4Dh
4Eh
4Fh
50h-7Eh
7F
AIN3 VLOW Limit
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
UNLOCK ASSOCIATED
MSB REGISTERS
AIN4 VHIGH Limit
AIN4 VLOW Limit
AIN5 VHIGH Limit
AIN5 VLOW Limit
AIN6 VHIGH Limit
AIN6 VLOW Limit
AIN7 VHIGH Limit
AIN7 VLOW Limit
AIN8 VHIGH Limit
AIN8 VLOW Limit
Reserved
Figure 30. Phase 2 of 10-Bit Read
If an MSB register is read first, its corresponding LSB register is
not locked out, thus leaving the user with the option of just
reading back 8 bits (MSB) of a 10-bit conversion result. Reading
an MSB register first does not lock out other MSB registers, and
likewise reading an LSB register first does not lock out other
LSB registers.
Table 7. ADT7411 Registers
Power-
on
Default
RD/WR
Address Name
Device ID
02h
41h
xxh
00h
00h
00h
Manufacturer’s ID
Silicon Revision
Reserved
00h
01h
02h
03h
Interrupt Status 1
Interrupt Status 2
00h
00h
Reserved
SPI Lock Status
Internal Temperature and VDD LSBs
External Temperature and AIN1 to AIN 4 LSBs 00h
00h
80hn-FFh Reserved
04h
05h
06h
07h
08h
AIN5 to AIN8 LSBs
VDD MSBs
Internal Temperature MSBs
External Temperature MSBs/AIN1 MSBs
AIN2 MSBs
AIN3 MSBs
AIN4 MSBs
AIN5 MSBs
AIN6 MSBs
00h
xxh
00h
00h
00h
00h
00h
00h
00h
00h
00h
Interrupt Status 1 Register (Read-Only) [Address = 00h]
This 8-bit read-only register reflects the status of some of the
INT
interrupts that can cause the INT/
pin to go active. This
register is reset by a read operation provided that any out-of-
limit event is corrected. It is also reset by a software reset.
09h
0Ah
0Bh
0Ch
0Dh
0Eh
Table 8. Interrupt Status 1 Register
D7
01
D6
01
D5
01
D4
01
D3
01
D2
01
D1
01
D0
01
AIN7 MSBs
AIN8 MSBs
1 Default settings at power-up.
0Fh
10h-17h
18h
19h
1Ah
1Bh-1Ch
1Dh
1Eh
1Fh
20h
21h
Reserved
Control Configuration 1
Control Configuration 2
Control Configuration 3
Reserved
Interrupt Mask 1
Interrupt Mask 2
Internal Temperature Offset
External Temperature Offset
Reserved
08h
00h
00h
00h
00h
00h
00h
22h
Reserved
23h
24h
25h
26h
27h
28h
29h-2Ah
2Bh
2Ch
2Dh
VDD VHIGH Limit
VDD VLOW Limit
C7h
62h
64h
C9h
FFh
00h
Internal THIGH Limit
Internal TLOW Limit
External THIGH/AIN1 VHIGH Limits
External TLOW/AIN1 VLOW Limits
Reserved
AIN2 VHIGH Limit
AIN2 VLOW Limit
AIN3 VHIGH Limit
FFh
00h
FFh
Rev. B | Page 20 of 36
ADT7411
Table 9.
Bit Function
Internal Temperature Value/VDD Value Register LSBs
(Read-Only) [Address = 03h]
D0 1 when internal temperature value exceeds THIGH limit.
Any internal temperature reading greater than the set
limit causes an out-of-limit event.
This internal temperature value and VDD value register is an
8-bit read-only register. It stores the two LSBs of the 10-bit
temperature reading from the internal temperature sensor and
also the two LSBs of the 10-bit supply voltage reading.
D1 1 when internal temperature value exceeds TLOW limit.
Any internal temperature reading less than or equal to
the set limit causes an out-of-limit event.
Table 12. Internal Temperature/VDD LSBs
D2 This status bit is linked to the configuration of Pin 7 and
Pin 8. If configured for external temperature sensor, this bit
is 1 when external temperature value exceeds THIGH limit.
The default value for this limit register is –1°C, so any external
temperature reading greater than the limit set causes an
out-of-limit event. If configured for AIN1 and AIN2, this bit is
1 when the AIN1 input voltage exceeds VHIGH or VLOW limits.
D7
D6
D5
D4
D3
V1
01
D2
LSB
01
D1
T1
01
D0
LSB
01
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
1 Default settings at power-up.
Table 13.
Bit
D0
D1
D2
D3
Function
D3 1 when external temperature value exceeds TLOW limit.
The default value for this limit register is 0°C, so any
external temperature reading less than or equal to the
limit set causes an out-of-limit event.
LSB of Internal Temperature Value
B1 of Internal Temperature Value
LSB of VDD Value
B1 of VDD Value
D4 1 indicates a fault (open or short) for the external temp sensor.
D5 1 when AIN2 voltage is greater than corresponding VHIGH
limit. 1 when AIN2 voltage is less than or equal to
corresponding VLOW limit.
External Temperature Value and AIN1 to AIN4 Register
LSBs (Read-Only) [Address = 04h]
This is an 8-bit read-only register. Bit D2 to Bit D7 store the two
LSBs of the analog inputs AIN2 to AIN4. Bit D0 and Bit D1 are
used to store the two LSBs of either the external temperature
value or AIN1 input value. The type of input for D0 and D1 is
selected by Bit 1 and Bit 2 of the Control Configuration 1 register.
D6 1 when AIN3 voltage is greater than corresponding VHIGH
limit. 1 when AIN3 voltage is less than or equal to
corresponding VLOW limit.
D7 1 when AIN4 voltage is greater than corresponding VHIGH
limit. 1 when AIN4 voltage is less than or equal to
corresponding VLOW limit.
Table 14. External Temperature and AIN1to AIN4 LSBs
Interrupt Status 2 Register (Read-Only) [Address = 01h]
D7
A4
01
D6
D5
A3
01
D4
D3
A2
01
D2
D1
T/A
01
D0
This 8-bit read-only register reflects the status of the VDD and
A4LSB
01
A3LSB
01
A2LSB
01
T/ALSB
01
INT
AIN5 to AIN8 interrupts that can cause the INT/
pin to go
active. This register is reset by a read operation provided that any
out-of-limit event is corrected. It is also reset by a software reset.
1 Default settings at power-up.
Table 15.
Table 10. Interrupt Status 2 Register
Bit
D0
D1
D2
D3
D4
D5
D6
D7
Function
D7
D6
D5
D4
01
D3
01
D2
01
D1
01
D0
01
LSB of External Temperature Value or AIN1 Value
Bit 1 of External Temperature Value or AIN1 Value
LSB of AIN2 Value
Bit 1 of AIN2 Value
LSB of AIN3 Value
Bit 1 of AIN3 Value
LSB of AIN4 Value
Bit 1 of AIN4 Value
N/A
N/A
N/A
1 Default settings at power-up.
Table 11.
Bit
Function
D0
1 when AIN5 voltage is greater than the corresponding
VHIGH limit. 1 when AIN5 voltage is less than or equal to
the corresponding VLOW limit.
D1
D2
D3
D4
1 when AIN6 voltage is greater than the corresponding
VHIGH limit. 1 when AIN6 voltage is less than or equal to
the corresponding VLOW limit.
1 when AIN7 voltage is greater than the corresponding
VHIGH limit. 1 when AIN7 voltage is less than or equal to
the corresponding VLOW limit.
1 when AIN8 voltage is greater than the corresponding
VHIGH limit. 1 when AIN8 voltage is less than or equal to
the corresponding VLOW limit.
1 when VDD value is greater than the corresponding
VHIGH limit. 1 when VDD is less than or equal to the
corresponding VLOW limit.
D5:D7 Reserved
Rev. B | Page 21 of 36
ADT7411
AIN5 to AIN8 Registers LSBs (Read-Only) [Address = 05h]
AIN2 Register MSBs (Read) [Address = 09h]
This is an 8-bit read-only register. Bit D0 to Bit D7 store the two
LSBs of the analog inputs AIN5 to AIN8. The MSBs are stored
in Register 0Ch to Register 0Fh.
This 8-bit read register contains the eight MSBs of the AIN2
analog input voltage word. The value in this register is
combined with Bit D2 and Bit D3 of the external temperature
value and AIN1 to AIN4 register LSBs, Address 04h, to give the
full 10-bit conversion result of the analog value on the AIN2 pin.
Table 16. AIN5 to AIN8 LSBs
D7 D6
D5 D4
D3 D2
D1 D0
Table 21. AIN2 MSBs
A8
01
A8LSB
01
A7
01
A7LSB
01
A6
01
A6LSB
01
A5
01
A5LSB
01
D7
MSB
01
D6
A8
01
D5
A7
01
D4
A6
01
D3
A5
01
D2
A4
01
D1
A3
01
D0
A2
01
1 Default settings at power-up.
Table 17.
1 Default settings at power-up.
Bit
D0
D1
D2
D3
D4
D5
D6
D7
Function
LSB of AIN5 Value
Bit 1 of AIN5 Value
LSB of AIN6 Value
Bit 1 of AIN6 Value
LSB of AIN7 Value
Bit 1 of AIN7 Value
LSB of AIN8 Value
Bit 1 of AIN8 Value
AIN3 Register MSBs (Read) [Address = 0Ah]
This 8-bit read register contains the eight MSBs of the AIN3
analog input voltage word. The value in this register is
combined with Bit D4 and Bit D5 of the external temperature
value and AIN1 to AIN4 register LSBs, Address 04h, to give the
full 10-bit conversion result of the analog value on the AIN3 pin.
Table 22. AIN3 MSBs
D7
MSB
01
D6
A8
01
D5
A7
01
D4
A6
01
D3
A5
01
D2
A4
01
D1
A3
01
D0
A2
01
VDD Value Register MSBs (Read-Only) [Address = 06h]
This 8-bit read-only register stores the supply voltage value. The
eight MSBs of the 10-bit value are stored in this register.
1 Default settings at power-up.
Table 18. VDD Value MSBs
AIN4 Register MSBs (Read) [Address = 0Bh]
D7
V9
x1
D6
V8
x1
D5
V7
x1
D4
V6
x1
D3
V5
x1
D2
V4
x1
D1
V3
x1
D0
V2
x1
This 8-bit read register contains the eight MSBs of the AIN4
analog input voltage word. The value in this register is combined
with Bit D6 and Bit D7 of the external temperature value and
AIN1 to AIN4 register LSBs, Address 04h, to give the full 10-bit
conversion result of the analog value on the AIN4 pin.
1 Loaded with VDD value after power-up.
Internal Temperature Value Register MSBs (Read-Only)
[Address = 07h]
Table 23. AIN4 MSBs
This 8-bit read-only register stores the internal temperature
value from the internal temperature sensor in twos complement
format. This register stores the eight MSBs of the 10-bit value.
D7
MSB
01
D6
A8
01
D5
A7
01
D4
A6
01
D3
A5
01
D2
A4
01
D1
A3
01
D0
A2
01
1 Default settings at power-up.
Table 19. Internal Temperature Value MSBs
D7
T9
01
D6
T8
01
D5
T7
01
D4
T6
01
D3
T5
01
D2
T4
01
D1
T3
01
D0
T2
01
AIN5 Register MSBs (Read) [Address = 0Ch]
This 8-bit read register contains the eight MSBs of the AIN5
analog input voltage word. The value in this register is combined
with Bit D0 and Bit D1 of the AIN5 to AIN8 register LSBs,
Address 05h, to give the full 10-bit conversion result of the
analog value on the AIN5 pin.
1 Default settings at power-up.
External Temperature Value or AIN1 Register MSBs
(Read-Only) [Address = 08h]
This 8-bit read-only register stores, if selected, the external
Table 24. AIN5 MSBs
temperature value or the analog input AIN1 value. Selection is
done in Control Configuration 1 register. The external temperature
value is stored in twos complement format. The eight MSBs of
the 10-bit value are stored in this register.
D7
MSB
01
D6
A8
01
D5
A7
01
D4
A6
01
D3
A5
01
D2
A4
01
D1
A3
01
D0
A2
01
1 Default settings at power-up.
Table 20. External Temperature Value/Analog Inputs MSBs
D7
T/A9
01
D6
T/A8
01
D5
T/A7
01
D4
T/A6
01
D3
T/A5
01
D2
T/A4
01
D1
T/A3
01
D0
T/A2
01
1 Default settings at power-up.
Rev. B | Page 22 of 36
ADT7411
AIN6 Register MSBs (Read) [Address = 0Dh]
Table 29.
Bit
Function
This 8-bit read register contains the eight MSBs of the AIN6
analog input voltage word. The value in this register is combined
with Bit D2 and Bit D3 of the AIN5 to AIN8 register LSBs,
Address 05h, to give the full 10-bit conversion result of the
analog value on the AIN6 pin.
C0
This bit enables/disables conversions in round robin
and single-channel mode. ADT7411 powers up in round
robin mode, but monitoring is not initiated until this bit
is set. Default = 0.
0 = Stop monitoring.
1 = Start monitoring.
Table 25. AIN6 MSBs
D7
MSB
01
D6
A8
01
D5
A7
01
D4
A6
01
D3
A5
01
D2
A4
01
D1
A3
01
D0
A2
01
C2:C1 Selects between the two different analog inputs on
Pin 7 and Pin 8. The ADT7411 powers up with AIN1 and
AIN2 selected.
00: AIN1 and AIN2 selected.
01: Undefined.
1 Default settings at power-up.
AIN7 Register MSBs (Read) [Address = 0Eh]
10: External TDM selected.
11: Undefined.
This 8-bit read register contains the eight MSBs of the AIN7
analog input voltage word. The value in this register is combined
with Bit D4 and Bit D5 of the AIN5 to AIN8 register LSBs,
Address 05h, to give the full 10-bit conversion result of the
analog value on the AIN7 pin.
C3
C4
C5
Reserved. Write 1 only to this bit.
Reserved. Write 0 only.
0: Enable INT/INT output.
1: Disable INT/INT output.
C6
PD
Configures INT/INT output polarity.
0: Active low.
1: Active high.
Table 26. AIN7 MSBs
D7
MSB
01
D6
A8
01
D5
A7
01
D4
A6
01
D3
A5
01
D2
A4
01
D1
A3
01
D0
A2
01
Power-Down Bit. Setting this bit to 1 puts the ADT7411
into standby mode. In this mode, the analog circuitry
is fully powered down, but the serial interface is still
operational. To power up the part again, write 0 to this bit.
1 Default settings at power-up.
AIN8 Register MSBs (Read) [Address = 0Fh]
This 8-bit read register contains the eight MSBs of the AIN8
analog input voltage word. The value in this register is
combined with Bit D6 and Bit D7 of the AIN5 to AIN8 register
LSBs, Address 05h, to give the full 10-bit conversion result of
the analog value on the AIN8 pin.
Control Configuration 2 Register (Read/Write)
[Address = 19h]
This configuration register is an 8-bit read/write register that is
used to set up some of the operating modes of the ADT7411.
Table 30. Control Configuration 2
Table 27. AIN8 MSBs
D7
C7
01
D6
C6
01
D5
C5
01
D4
C4
01
D3
C3
01
D2
C2
01
D1
C1
01
D0
C0
01
D7
MSB
01
D6
A8
01
D5
A7
01
D4
A6
01
D3
A5
01
D2
A4
01
D1
A3
01
D0
A2
01
1 Default settings at power-up.
1 Default settings at power-up.
Control Configuration 1 Register (Read/Write)
[Address = 18h]
This configuration register is an 8-bit read/write register that is
used to set up some of the operating modes of the ADT7411.
Table 28. Control Configuration 1
D7
PD
01
D6
C6
01
D5
C5
01
D4
C4
01
D3
C3
11
D2
C2
01
D1
C1
01
D0
C0
01
1 Default settings at power-up.
Rev. B | Page 23 of 36
ADT7411
Table 31.
Table 33.
Bit
Function
Bit
Function
C3:C0 In single-channel mode, these bits select between VDD
,
C0
Selects between fast and normal ADC conversion speeds.
0 = ADC clock at 1.4 kHz.
1 = ADC clock at 22.5 kHz. D+ and D− analog filters
are disabled.
the internal temperature sensor, external temperature
sensor/AIN1, AIN2 to AIN8 for conversion. The default is VDD
0000 = VDD
.
.
0001 = Internal Temperature Sensor.
C1:C2 Reserved. Only write 0s.
0010 = External Temperature Sensor/AIN1. (Bit C1 and
Bit C2 of Control Configuration 1 affect this selection.)
0011 = AIN2.
0100 = AIN3.
0101 = AIN4.
C3
C4
Reserved. Write only 1 to this bit.
Selects the ADC reference to be either Internal VREF or
DD for analog inputs.
0 = Int VREF
1 = VDD
V
0110 = AIN5.
0111 = AIN6.
C5:C7 Reserved. Only write 0s.
1000 = AIN7.
1001 = AIN8.
1010 to 1111 = Reserved.
Interrupt Mask 1 Register (Read/Write) [Address = 1Dh]
This mask register is an 8-bit read/write register that can be
INT
used to mask out any interrupts that can cause the INT/
to go active.
pin
C4
C5
Selects between single-channel and round robin
conversion cycle. Default is round robin.
0 = Round robin.
1 = Single-channel.
Table 34. Interrupt Mask 1
D7
D7
01
D6
D6
01
D5
D5
01
D4
D4
01
D3
D3
01
D2
D2
01
D1
D1
01
D0
Default condition is to average every measurement on
all channels 16 times. This bit disables this averaging.
Channels affected are temperature, analog inputs, and VDD
D0
01
.
1 Default settings at power-up.
0 = Enable averaging.
Table 35.
1 = Disable averaging.
Bit Function
C6
SMBus timeout on the serial clock puts a 25 ms limit on
the pulse width of the clock, ensuring that a fault on the
master SCL does not lock up the SDA line.
0 = Disable SMBus timeout.
1 = Enable SMBus timeout.
D0 0 = Enable internal THIGH interrupt
1 = Disable internal THIGH interrupt
D1 0 = Enable internal TLOW interrupt
1 = Disable internal TLOW interrupt
C7
Software Reset. Setting this bit to a 1 causes a software
reset. All registers reset to their default settings.
D2 0 = Enable external THIGH interrupt or AIN1 interrupt
1 = Disable external THIGH interrupt or AIN1 interrupt
D3 0 = Enable external TLOW interrupt
1 = Disable external TLOW interrupt
Control Configuration 3 Register (Read/Write)
[Address = 1Ah]
D4 0 = Enable external temperature fault interrupt
1 = Disable external temperature fault interrupt
D5 0 = Enable AIN2 interrupt
This configuration register is an 8-bit read/write register that is
used to set up some of the operating modes of the ADT7411.
Table 32. Control Configuration 3
1 = Disable AIN2 interrupt
D7
C7
01
D6
C6
01
D5
C5
01
D4
C4
01
D3
C3
11
D2
C2
01
D1
C1
01
D0
C0
01
D6 0 = Enable AIN3 interrupt
1 = Disable AIN3 interrupt
D7 0 = Enable AIN4 interrupt
1 Default settings at power-up.
1 = Disable AIN4 interrupt
Rev. B | Page 24 of 36
ADT7411
Interrupt Mask 2 Register (Read/Write) [Address = 1Eh]
if the thermal characteristics change. Because it is an 8-bit
register, the temperature resolution is 1°C.
This mask register is an 8-bit read/write register that can be
INT
used to mask out any interrupts that can cause the INT/
to go active.
pin
Table 39. External Temperature Offset
D7
D7
01
D6
D6
01
D5
D5
01
D4
D4
01
D3
D3
01
D2
D2
01
D1
D1
01
D0
D0
01
Table 36. Interrupt Mask 2
D7
D7
01
D6
D6
01
D5
D5
01
D4
D4
01
D3
D3
01
D2
D2
01
D1
D1
01
D0
1 Default settings at power-up.
D0
01
VDD VHIGH Limit Register (Read/Write) [Address = 23h]
1 Default settings at power-up.
This limit register is an 8-bit read/write register that stores the
VDD upper limit that causes an interrupt and activates the
Table 37.
Bit
Function
INT
INT/
output (if enabled). For this to happen, the measured
D0
0 = Enable AIN5 interrupt
1 = Disable AIN5 interrupt
0 = Enable AIN6 interrupt
1 = Disable AIN6 interrupt
0 = Enable AIN7 interrupt
1 = Disable AIN7 interrupt
0 = Enable AIN8 interrupt
1 = Disable AIN8 interrupt
0 = Enable VDD interrupts
1 = Disable VDD interrupts
Reserved. Only write 0s
V
DD value has to be greater than the value in this register. The
default value is 5.46 V.
D1
Table 40. VDD VHIGH Limit
D7
D7
11
D6
D6
11
D5
D5
01
D4
D4
01
D3
D3
01
D2
D2
11
D1
D1
11
D0
D0
11
D2
D3
1 Default settings at power-up.
D4
VDD VLOW Limit Register (Read/Write) [Address = 24h]
This limit register is an 8-bit read/write register that stores the
VDD lower limit that causes an interrupt and activates the INT/
D5:D7
INT
output (if enabled). For this to happen, the measured VDD
Internal Temperature Offset Register (Read/Write)
[Address = 1Fh]
value has to be less than or equal to the value in this register.
The default value is 2.7 V.
This register contains the offset value for the internal
temperature channel. A twos complement number can be
Table 41. VDD VLOW Limit
D7
D7
01
D6
D6
11
D5
D5
11
D4
D4
01
D3
D3
01
D2
D2
01
D1
D1
11
D0
D0
01
written to this register, which is then added to the measured
result before it is stored or compared to limits. In this way, a
sort of one-point calibration can be done whereby the whole
transfer function of the channel can be moved up or down.
From a software point of view, this may be a very simple
method to vary the characteristics of the measurement channel
if the thermal characteristics change. Because it is an 8-bit
register, the temperature resolution is 1°C.
1 Default settings at power-up.
Internal THIGH Limit Register (Read/Write) [Address = 25h]
This limit register is an 8-bit read/write register that stores the
twos complement of the internal temperature upper limit that
causes an interrupt and activates the INT/
For this to happen, the measured internal temperature value has
to be greater than the value in this register. Because it is an 8-bit
register, the temperature resolution is 1°C. The default value
is 100°C.
INT
output (if enabled).
Table 38. Internal Temperature Offset
D7
D7
01
D6
D6
01
D5
D5
01
D4
D4
01
D3
D3
01
D2
D2
01
D1
D1
01
D0
D0
01
1 Default settings at power-up.
Positive Temperature = Limit Register Code (d)
External Temperature Offset Register (Read/Write)
[Address = 20h]
Negative Temperature = Limit Register Code (d) − 256
Table 42. Internal THIGH Limit
This register contains the offset value for the external
temperature channel. A twos complement number can be
D7
D7
01
D6
D6
11
D5
D5
11
D4
D4
01
D3
D3
01
D2
D2
11
D1
D1
01
D0
D0
01
written to this register, which is then added to the measured
result before it is stored or compared to limits. In this way, a
sort of one-point calibration can be done whereby the whole
transfer function of the channel can be moved up or down.
From a software point of view, this may be a very simple
method to vary the characteristics of the measurement channel
1 Default settings at power-up.
Rev. B | Page 25 of 36
ADT7411
Internal TLOW Limit Register (Read/Write) [Address = 26h]
External TLOW/AIN1 VLOW Limit Register (Read/Write)
[Address = 28h]
This limit register is an 8-bit read/write register that stores the
twos complement of the internal temperature lower limit that
If Pin 7 and Pin 8 are configured for the external temperature
sensor, this limit register is an 8-bit read/write register that
stores the twos complement of the external temperature lower
INT
causes an interrupt and activates the INT/
output (if enabled).
For this to happen, the measured internal temperature value has
to be more negative than or equal to the value in this register.
Because it is an 8-bit register, the temperature resolution is 1°C.
The default value is −55°C.
INT
limit that causes an interrupt and activates the INT/
output
(if enabled). For this to happen, the measured external temperature
value has to be more negative than or equal to the value in this
register. Because it is an 8-bit register, the temperature
resolution is 1°C. The default value is 0°C.
Positive Temperature = Limit Register Code (d)
Negative Temperature = Limit Register Code (d) − 256
Positive Temperature = Limit Register Code (d)
Negative Temperature = Limit Register Code (d) − 256
Table 43. Internal TLOW Limit
D7
D7
11
D6
D6
11
D5
D5
01
D4
D4
01
D3
D3
11
D2
D2
01
D1
D1
01
D0
D0
11
If Pin 7 and Pin 8 are configured for AIN1 and AIN2 single-
ended inputs, this limit register is an 8-bit read/write register
that stores the AIN1 input lower limit that causes an interrupt
1 Default settings at power-up.
INT
and activates the INT/
output (if enabled). For this to
happen, the measured AIN1 value has to be less than or equal
to the value in this register. Because it is an 8-bit register, the
resolution is four times less than the resolution of the 10-bit
ADC. Because the power-up default settings for Pin 7 and Pin 8
are AIN1 and AIN2 single-ended inputs, the default value for
this limit register is 0 V.
External THIGH/AIN1 VHIGH Limit Register (Read/Write)
[Address = 27h]
If Pin 7 and Pin 8 are configured for the external temperature
sensor, this limit register is an 8-bit read/write register that
stores the twos complement of the external temperature upper
INT
limit that causes an interrupt and activates the INT/
output
Table 45. AIN1 VLOW Limit
(if enabled). For this to happen, the measured external
temperature value has to be greater than the value in this
register. Because it is an 8-bit register, the temperature
resolution is 1°C. The default value is −1°C.
D7
D7
01
D6
D6
01
D5
D5
01
D4
D4
01
D3
D3
01
D2
D2
01
D1
D1
01
D0
D0
01
1 Default settings at power-up.
Positive Temperature = Limit Register Code (d)
Negative Temperature = Limit Register Code (d) − 256
AIN2 VHIGH Limit Register (Read/Write) [Address = 2Bh]
This limit register is an 8-bit read/write register that stores the
AIN2 input upper limit that causes an interrupt and activates
If Pin 7 and Pin 8 are configured for AIN1 and AIN2 single-
ended inputs, this limit register is an 8-bit read/write register
that stores the AIN1 input upper limit that causes an interrupt
INT
the INT/
output (if enabled). For this to happen, the
measured AIN2 value has to be greater than the value in this
register. Because it is an 8-bit register, the resolution is four
times less than the resolution of the 10-bit ADC. The default
value is full-scale voltage.
INT
and activates the INT/
output (if enabled). For this to
happen, the measured AIN1 value has to be greater than the
value in this register. Because it is an 8-bit register, the
resolution is four times less than the resolution of the 10-bit
ADC. Because the power-up default settings for Pin 7 and Pin 8
are AIN1 and AIN2 single-ended inputs, the default value for
this limit register is full-scale voltage.
Table 46. AIN2 VHIGH Limit
D7
D7
11
D6
D6
11
D5
D5
11
D4
D4
11
D3
D3
11
D2
D2
11
D1
D1
11
D0
D0
11
Table 44. AIN1 VHIGH Limit
1 Default settings at power-up.
D7
D7
11
D6
D6
11
D5
D5
11
D4
D4
11
D3
D3
11
D2
D2
11
D1
D1
11
D0
D0
11
1 Default settings at power-up.
Rev. B | Page 26 of 36
ADT7411
AIN2 VLOW Limit Register (Read/Write) [Address = 2Ch]
Table 50. AIN4 VHIGH Limit
D7
D7
11
D6
D6
11
D5
D5
11
D4
D4
11
D3
D3
11
D2
D2
11
D1
D1
11
D0
D0
11
This limit register is an 8-bit read/write register that stores the
AIN2 input lower limit that causes an interrupt and activates
INT
the INT/
output (if enabled). For this to happen, the
1 Default settings at power-up.
measured AIN2 value has to be less than or equal to the value in
this register. Because it is an 8-bit register, the resolution is four
times less than the resolution of the 10-bit ADC. The default
value is 0 V.
AIN4 VLOW Limit Register (Read/Write) [Address = 30h]
This limit register is an 8-bit read/write register that stores the
AIN4 input lower limit that causes an interrupt and activates
the INT/
AIN4 value has to be less than or equal to the value in this
register. Because it is an 8-bit register, the resolution is four
times less than the resolution of the 10-bit ADC. The default
value is 0 V.
Table 47. AIN2 VLOW Limit
INT
output (if enabled). For this to happen, the measured
D7
D7
01
D6
D6
01
D5
D5
01
D4
D4
01
D3
D3
01
D2
D2
01
D1
D1
01
D0
D0
01
1 Default settings at power-up.
AIN3 VHIGH Limit Register (Read/Write) [Address = 2Dh]
Table 51. AIN4 VLOW Limit
D7
D7
01
D6
D6
01
D5
D5
01
D4
D4
01
D3
D3
01
D2
D2
01
D1
D1
01
D0
D0
01
This limit register is an 8-bit read/write register that stores the
AIN3 input upper limit that causes an interrupt and activates
INT
the INT/
output (if enabled). For this to happen, the
1 Default settings at power-up.
measured AIN3 value has to be greater than the value in this
register. Because it is an 8-bit register, the resolution is four
times less than the resolution of the 10-bit ADC. The default
value is full-scale voltage.
AIN5 VHIGH Limit Register (Read/Write) [Address = 31h]
This limit register is an 8-bit read/write register that stores the
AIN5 input upper limit that causes an interrupt and activates
the INT/
measured AIN5 value has to be greater than the value in this
register. Because it is an 8-bit register, the resolution is four
times less than the resolution of the 10-bit ADC. The default
value is full-scale voltage.
Table 48. AIN3 VHIGH Limit
INT
output (if enabled). For this to happen, the
D7
D7
11
D6
D6
11
D5
D5
11
D4
D4
11
D3
D3
11
D2
D2
11
D1
D1
11
D0
D0
11
1 Default settings at power-up.
AIN3 VLOW Limit Register (Read/Write) [Address = 2Eh]
Table 52. AIN5 VHIGH Limit
D7
D7
11
D6
D6
11
D5
D5
11
D4
D4
11
D3
D3
11
D2
D2
11
D1
D1
11
D0
D0
11
This limit register is an 8-bit read/write register that stores the
AIN3 input lower limit that causes an interrupt and activates
INT
the INT/
output (if enabled). For this to happen, the
1 Default settings at power-up.
measured AIN3 value has to be less than or equal to the value in
this register. Because it is an 8-bit register, the resolution is four
times less than the resolution of the 10-bit ADC. The default
value is 0 V.
AIN5 VLOW Limit Register (Read/Write) [Address = 32h]
This limit register is an 8-bit read/write register that stores the
AIN5 input lower limit that causes an interrupt and activates
the INT/
measured AIN5 value has to be less than or equal to the value in
this register. Because it is an 8-bit register, the resolution is four
times less than the resolution of the 10-bit ADC. The default
value is 0 V.
Table 49. AIN3 VLOW Limit
INT
output (if enabled). For this to happen, the
D7
D7
01
D6
D6
01
D5
D5
01
D4
D4
01
D3
D3
01
D2
D2
01
D1
D1
01
D0
D0
01
1 Default settings at power-up.
AIN4 VHIGH Limit Register (Read/Write) [Address = 2Fh]
Table 53. AIN5 VLOW Limit
D7
D7
01
D6
D6
01
D5
D5
01
D4
D4
01
D3
D3
01
D2
D2
01
D1
D1
01
D0
D0
01
This limit register is an 8-bit read/write register that stores the
AIN4 input upper limit that causes an interrupt and activates
INT
the INT/
output (if enabled). For this to happen, the
1 Default settings at power-up.
measured AIN4 value has to be greater than the value in this
register. Because it is an 8-bit register, the resolution is four
times less than the resolution of the 10-bit ADC. The default
value is full-scale voltage.
Rev. B | Page 27 of 36
ADT7411
AIN6 VHIGH Limit Register (Read/Write) [Address = 33h]
Table 57. AIN7 VLOW Limit
D7
D7
01
D6
D6
01
D5
D5
01
D4
D4
01
D3
D3
01
D2
D2
01
D1
D1
01
D0
D0
01
This limit register is an 8-bit read/write register that stores the
AIN3 input upper limit that causes an interrupt and activates
INT
the INT/
output (if enabled). For this to happen, the
1 Default settings at power-up.
measured AIN6 value has to be greater than the value in this
register. Because it is an 8-bit register, the resolution is four
times less than the resolution of the 10-bit ADC. The default
value is full-scale voltage.
AIN8 VHIGH Limit Register (Read/Write) [Address = 37h]
This limit register is an 8-bit read/write register that stores the
AIN8 input upper limit that causes an interrupt and activates
the INT/
measured AIN8 value has to be greater than the value in this
register. As it is an 8-bit register, the resolution is four times less
than the resolution of the 10-bit ADC. The default value is full-
scale voltage.
Table 54. AIN6 VHIGH Limit
INT
output (if enabled). For this to happen, the
D7
D7
11
D6
D6
11
D5
D5
11
D4
D4
11
D3
D3
11
D2
D2
11
D1
D1
11
D0
D0
11
1 Default settings at power-up.
AIN6 VLOW Limit Register (Read/Write) [Address = 34h]
Table 58. AIN8 VHIGH Limit
D7
D7
11
D6
D6
11
D5
D5
11
D4
D4
11
D3
D3
11
D2
D2
11
D1
D1
11
D0
D0
11
This limit register is an 8-bit read/write register that stores the
AIN6 input lower limit that causes an interrupt and activates
INT
the INT/
output (if enabled). For this to happen, the
1 Default settings at power-up.
measured AIN6 value has to be less than or equal to the value in
this register. Because it is an 8-bit register, the resolution is four
times less than the resolution of the 10-bit ADC. The default
value is 0 V.
AIN8 VLOW Limit Register (Read/Write) [Address = 38h]
This limit register is an 8-bit read/write register that stores the
AIN8 input lower limit that causes an interrupt and activates
the INT/
measured AIN8 value has to be less than or equal to the value in
this register. Because it is an 8-bit register, the resolution is four
times less than the resolution of the 10-bit ADC. The default
value is 0 V.
Table 55. AIN6 VLOW Limit
INT
output (if enabled). For this to happen, the
D7
D7
01
D6
D6
01
D5
D5
01
D4
D4
01
D3
D3
01
D2
D2
01
D1
D1
01
D0
D0
01
1 Default settings at power-up.
AIN7 VHIGH Limit Register (Read/Write) [Address = 35h]
Table 59. AIN8 VLOW Limit
D7
D7
01
D6
D6
01
D5
D5
01
D4
D4
01
D3
D3
01
D2
D2
01
D1
D1
01
D0
D0
01
This limit register is an 8-bit read/write register that stores the
AIN7 input upper limit that causes an interrupt and activates
INT
the INT/
output (if enabled). For this to happen, the
1 Default settings at power-up.
measured AIN7 value has to be greater than the value in this
register. Because it is an 8-bit register, the resolution is four
times less than the resolution of the 10-bit ADC. The default
value is full-scale voltage.
Device ID Register (Read-Only) [Address = 4Dh]
This 8-bit read-only register gives a unique identification
number for this part. ADT7411 = 02h.
Table 56. AIN7 VHIGH Limit
Manufacturer’s ID Register (Read-Only) [Address = 4Eh]
D7
D7
11
D6
D6
11
D5
D5
11
D4
D4
11
D3
D3
11
D2
D2
11
D1
D1
11
D0
D0
11
This register contains the manufacturer’s identification number.
Analog Devices, Inc. is 41h.
1 Default settings at power-up.
Silicon Revision Register (Read-Only) [Address = 4Fh]
AIN7 VLOW Limit Register (Read/Write) [Address = 36h]
This register is divided into the four LSBs representing the
stepping and the four MSBs representing the version. The
stepping contains the manufacturer’s code for minor revisions
or steppings to the silicon. The version is the ADT7411 version
number, 0100b (4h).
This limit register is an 8-bit read/write register that stores the
AIN7 input lower limit that causes an interrupt and activates
INT
the INT/
output (if enabled). For this to happen, the
measured AIN7 value has to be less than or equal to the value in
this register. Because it is an 8-bit register, the resolution is four
times less than the resolution of the 10-bit ADC. The default
value is 0 V.
Rev. B | Page 28 of 36
ADT7411
SPI Lock Status Register (Read-Only) [Address = 7Fh]
LOCK AND
SELECT SPI
ADT7411
Bit D0 (LSB) of this read-only register indicates whether the SPI
interface is locked or not. Writing to this register causes the
device to malfunction.
CS
V
DD
SPI FRAMING
EDGE
Default value is 00h.
820Ω 820Ω 820Ω
0 = I2C interface.
DIN
SCLK
DOUT
1 = SPI interface selected and locked.
SERIAL INTERFACE
There are two serial interfaces that can be used on this part: I2C
and SPI. The device powers up with the serial interface in I2C
mode, but it is not locked into this mode. To stay in I2C mode, it
Figure 32. Typical SPI Interface Connection
The following sections describe in detail how to use the I2C and
SPI protocols associated with the ADT7411.
CS
is recommended that the user tie the
line to either VCC or
GND. It is not possible to lock the I2C mode, but it is possible to
select and lock the SPI mode.
I2C Serial Interface
Like all I2C compatible devices, the ADT7411 has a 7-bit serial
address. The four MSBs of this address for the ADT7411 are set
to 1001. The three LSBs are set by Pin 11, ADD. The ADD pin
can be configured three ways to give three different address
options: low, floating, and high. Setting the ADD pin low gives a
serial bus address of 1001 000, leaving it floating gives the
Address 1001 010, and setting it high gives the Address 1001
011. The recommended pull-up resistor value is 10 kΩ.
To select and lock the interface into the SPI mode, a number of
CS
pulses must be sent down the
(Pin 4) line. The following
section describes how this is done.
Once the SPI communication protocol is locked in, it cannot be
unlocked while the device is still powered up. Bit D0 of the SPI
Lock Status register (Address 7Fh) is set to 1 when a successful
SPI interface lock is accomplished. To reset the serial interface,
the user must power down the part and power up again. A
software reset does not reset the serial interface.
There is an enable/disable bit for the SMBus timeout. When this
is enabled, the SMBus times out after 25 ms of no activity. To
enable it, set Bit 6 of the Control Configuration 2 register. The
power-up default is with the SMBus timeout disabled.
Serial Interface Selection
2
CS
The
line controls the selection between I C and SPI.
The ADT7411 supports SMBus packet error checking (PEC)
and its use is optional. It is triggered by supplying the extra
clocks for the PEC byte. The PEC is calculated using CRC-8.
The frame clock sequence (FCS) conforms to CRC-8 by the
polynomial
Figure 33 shows the selection process necessary to lock the SPI
interface mode.
To communicate to the ADT7411 using the SPI protocol, send
CS
three pulses down the
line, as shown in Figure 33. On the
C (x) = x8 + x2 + x1 +1
third rising edge (marked as C in Figure 33), the part selects
and locks the SPI interface. Communication to the device is
now limited to the SPI protocol.
Consult the SMBus specification for more information.
The serial bus protocol operates as follows:
CS
As per most SPI standards, the
line must be low during
every SPI communication to the ADT7411, and high at all other
times. Typical examples of how to connect the dual interface as
I2C or SPI are shown in Figure 31 and Figure 32.
1. The master initiates a data transfer by establishing a start
condition, defined as a high-to-low transition on the serial
data line SDA while the serial clock line SCL remains high.
This indicates that an address/data stream follows. All slave
peripherals connected to the serial bus respond to the start
condition and shift in the next eight bits, consisting of a
V
V
DD
DD
ADT7411
10kΩ
10kΩ
CS
7-bit address (MSB first) plus an R/ bit, which
W
SDA
SCL
determines the direction of the data transfer, that is,
whether data is written to or read from the slave device.
2
I C ADDRESS = 1001 000
ADD
Figure 31. Typical I2C Interface Connection
Rev. B | Page 29 of 36
ADT7411
The peripheral whose address corresponds to the
Writing to the ADT7411
transmitted address responds by pulling the data line low
during the low period before the ninth clock pulse, known
as the acknowledge bit. All other devices on the bus now
remain idle while the selected device waits for data to be
Depending on the register being written to, there are two
different writes for the ADT7411. It is not possible to do a block
write to this part, that is, no I2C auto-increment.
read from or written to it. If the R/ bit is 0, the master
writes to the slave device. If the R/ bit is 1, the master
W
W
Writing to the Address Pointer Register for a Subsequent
Read
reads from the slave device.
To read data from a particular register, the address pointer
register must contain the address of that register. If it does not,
the correct address must be written to the address pointer
register by performing a single-byte write operation, as shown
in Figure 34. The write operation consists of the serial bus
address followed by the address pointer byte. No data is written
to any of the data registers. A read operation is then performed
to read the register.
2. Data is sent over the serial bus in sequences of nine clock
pulses: eight bits of data followed by an acknowledge bit
from the receiver of data. Transitions on the data line must
occur during the low period of the clock signal and remain
stable during the high period because a low-to-high
transition when the clock is high can be interpreted as a
stop signal.
Writing Data to a Register
3. When all data bytes are read or written, stop conditions are
established. In write mode, the master pulls the data line
high during the 10th clock pulse to assert a stop condition.
In read mode, the master device pulls the data line high
during the low period before the ninth clock pulse. This is
known as No Acknowledge. The master then takes the data
line low during the low period before the 10th clock pulse,
and then high during the 10th clock pulse to assert a stop
condition.
All registers are 8-bit registers so only one byte of data can be
written to each register. Writing a single byte of data to one of
these read/write registers consists of the serial bus address, the
data register address written to the address pointer register,
followed by the data byte written to the selected data register
(see Figure 35). To write to a different register, another START
or repeated START is required. If more than one byte of data is
sent in one communication operation, the addressed register is
repeatedly loaded until the last data byte is sent.
Any number of bytes of data can be transferred over the
serial bus in one operation, but it is not possible to mix
read and write in one operation. This is because the type of
operation is determined at the beginning and cannot
subsequently be changed without starting a new operation.
Reading Data from the ADT7411
Reading data from the ADT7411 is done in a one-byte
operation. Reading back the contents of a register is shown in
Figure 36. The register address was previously set up by a
single-byte write operation to the Address Pointer register. To
read from another register, write to the Address Pointer register
again to set up the relevant register address. Therefore, block
reads are not possible, that is, no I2C auto-increment.
The I2C address set up by the ADD pin is not latched by
the device until after this address is sent twice. On the
eighth SCL cycle of the second valid communication, the
serial bus address is latched in. This is the SCL cycle
directly after the device has seen its own I2C serial bus
address. Any subsequent changes on this pin will have no
effect on the I2C serial bus address.
SPI Serial Interface
The SPI serial interface of the ADT7411 consists of four wires:
CS
CS
, SCLK, DIN, and DOUT. The
when more than one device is connected to the serial clock and
CS
is used to select the device
data lines. The
is also used to distinguish between any two
separate serial communications (see Figure 41 for a graphical
explanation). The SCLK is used to clock data in and out of the
part. The DIN line is used to write to the registers, and the
DOUT line is used to read data back from the registers. The
recommended pull-up resistor value is between 500 Ω and
820 Ω. Strong pull-ups are needed when serial clock speeds that
are close to the maximum limit are used or when the SPI
interface lines are experiencing large capacitive loading. Larger
resistor values can be used for pull-up resistors when the serial
clock speed is reduced.
Rev. B | Page 30 of 36
ADT7411
30ns MIN
A
A
B
B
C
CS
(START HIGH)
SPI LOCKED ON
THIRD RISING EDGE
SPI FRAMING
EDGE
30ns MIN
C
CS
(START LOW)
SPI LOCKED ON
THIRD RISING EDGE
SPI FRAMING
EDGE
Figure 33. Serial Interface—Selecting and Locking SPI Protocol
1
9
1
9
SCL
SDA
1
0
0
1
A2
A1
A0
R/W
P7
P6
P5
P4
P3
P2
P1
P0
ACK. BY
ADT7411
START BY
MASTER
ACK. BY
ADT7411
STOP BY
MASTER
FRAME 1
SERIAL BUS ADDRESS BYTE
FRAME 2
ADDRESS POINTER REGISTER BYTE
Figure 34. I2C—Writing to the Address Pointer Register to Select a Register for a Subsequent Read Operation
1
1
9
1
9
SCL
SDA
0
0
1
A2
A1
A0
P7
P6
P5
P4
P3
P2
P1
P0
R/W
START BY
MASTER
ACK. BY
ADT7411
ACK. BY
ADT7411
FRAME 1
SERIAL BUS ADDRESS BYTE
FRAME 2
ADDRESS POINTER REGISTER BYTE
1
9
SCL (CONTINUED)
SDA (CONTINUED)
D7
D6
D5
D4
D3
D2
D1
D0
ACK. BY STOP BY
ADT7411 MASTER
FRAME 3
DATA BYTE
Figure 35. I2C—Writing to the Address Pointer Register Followed by a Single Byte of Data to the Selected Register
1
1
9
1
9
SCL
SDA
0
0
1
A2
A1
A0 R/W
D7
D6
D5
D4
D3
D2
D1
D0
ACK. BY
ADT7411
START BY
MASTER
NO ACK. BY STOP BY
MASTER MASTER
FRAME 1
SERIAL BUS ADDRESS BYTE
FRAME 2
SINGLE DATA BYTE FROM ADT7411
Figure 36. I2C—Reading a Single Byte of Data from a Selected Register
Rev. B | Page 31 of 36
ADT7411
The part operates in a slave mode and requires an externally
applied serial clock to the SCLK input. The serial interface is
designed to allow the part to be interfaced to systems that
provide a serial clock that is synchronized to the serial data.
Multiple data reads are possible in SPI interface mode as the
address pointer register is auto-incremental. The address
pointer register auto-increments from 00h to 3Fh and loops
back to start over again at 00h when it reaches 3Fh.
INT
SMBus/SPI INT/
There are two types of serial operation: a read and a write.
Command words are used to distinguish between a read and a
write operation. These command words are given in Table 60.
Address auto-incrementing is possible in SPI mode.
INT
The ADT7411 INT/
output is an interrupt line for devices
that want to trade their ability to master for an extra pin. The
ADT7411 is a slave-only device and uses the SMBus/SPI
Table 60. SPI Command Words
INT
INT/
to signal the host device that it wants to talk. The
Write
Read
INT
SMBus/SPI INT/
limit indicator.
on the ADT7411 is used as an over/under
90h (1001 0000)
91h (1001 0001)
INT
The INT/
pin has an open-drain configuration that allows the
Write Operation
outputs of several devices to be wired-AND together when the
INT
Figure 37 shows the timing diagram for a write operation to the
ADT7411. Data is clocked into the registers on the rising edge
of SCLK. When the
INT/
register to set the active polarity of the INT/
INT
pin is active low. Use C6 of the Control Configuration 1
INT
output. The
CS
line is high, the DIN and DOUT lines
CS
power-up default is active low. The INT/
output can be
are in three-state mode. Only when the
goes from a high to a
disabled or enabled by setting C5 of the Control Configuration 1
register to 1 or 0, respectively.
low does the part accept any data on the DIN line. In SPI mode,
the address pointer register is capable of auto-incrementing to
the next register in the register map without having to load the
address pointer register each time. In Figure 37, the register
address portion of the diagram gives the first register that is
written to. Subsequent data bytes are written into sequential
writable registers. Therefore, after each data byte is written into
a register, the address pointer register auto-increments its value
to the next available register. The address pointer register auto-
increments from 00h to 3Fh and then loops back to start over
again at 00h.
INT
The INT/
output becomes active when either the internal
temperature value, the external temperature value, VDD value, or
any of the AIN input values exceed the values in their
corresponding THIGH/VHIGH or TLOW/VLOW registers. The
INT
INT/
output goes inactive again when a conversion result is
the measured value back within the trip limits and when the
status register associated with the out-of-limit event is read. The
two interrupt status registers show which event caused the
INT
INT/
pin to go active.
Read Operation
INT
The INT/
output requires an external pull-up resistor. This
Figure 38 to Figure 40 show the timing diagrams of correct read
operations. To read back from a register, first write to the
address pointer register with the address to be read from. This
operation is shown in Figure 38. Figure 39 shows the procedure
for reading back a single byte of data. The read command is first
sent to the part during the first eight clock cycles. As the read
command is being sent, irrelevant data is output onto the
DOUT line. During the following eight clock cycles the data
contained in the register selected by the address pointer register
is output onto the DOUT line. Data is output onto the DOUT
line on the falling edge of SCLK. Figure 40 shows the procedure
when reading data from two sequential registers.
can be connected to a voltage different from VDD, provided the
INT
exceeded. The value of the pull-up resistor depends on the
application but should be large enough to avoid excessive sink
maximum voltage rating of the INT/
output pin is not
INT
currents at the INT/
output, which can heat the chip and
affect the temperature reading.
SMBus Alert Response
INT
The INT/
when the SMBus/I2C interface is selected. It is an open-drain
INT
pin behaves the same way as an SMBus alert pin
output and requires a pull-up to VDD. Several INT/
can be wire-AND together so that the common line goes low if
INT
outputs
one or more of the INT/
outputs goes low. The polarity of
pin must be set for active low for a number of
outputs to be wire-AND together.
INT
the INT/
Rev. B | Page 32 of 36
ADT7411
CS
1
8
1
8
SCLK
DIN
D2
D1
D6
D5
D1
D7
D0
D7
START
D4
D3
D2
D0
D6
D5
D4
D3
WRITE COMMAND
REGISTER ADDRESS
CS (CONTINUED)
1
8
SCLK (CONTINUED)
D7
D6
D4
D3
D1
D5
D2
D0
DIN (CONTINUED)
STOP
DATA BYTE
Figure 37. SPI—Writing to the Address Pointer Register Followed by a Single Byte of Data to the Selected Register
CS
1
8
1
8
SCLK
DIN
D2
D6
D7
D1
D7
D5
D4
D3
D2
D1
D0
D6
D5
D4
D3
D0
STOP
START
WRITE COMMAND
REGISTER ADDRESS
Figure 38. SPI—Writing to the Address Pointer Register to Select a Register for Subsequent Read Operation
CS
1
8
1
8
SCLK
X
X
D6
X
X
DIN
D7
D5
X
D4
X
D3
X
D1
X
D0
X
X
X
D2
X
X
X
X
D0
X
D7
D6
D5
D4
D3
D2
D1
DOUT
STOP
START
READ COMMAND
DATA BYTE 1
Figure 39. SPI—Reading a Single Byte of Data from a Selected Register
Rev. B | Page 33 of 36
ADT7411
CS
1
8
1
8
SCLK
DIN
X
X
D6
X
X
D7
D5
X
D4
X
D3
X
D2
X
D1
X
D0
X
X
X
X
X
DOUT
X
D7
D6
D5
D4
D3
D2
D1
D0
X
START
READ COMMAND
DATA BYTE 1
CS (CONTINUED)
1
8
SCLK (CONTINUED)
DIN (CONTINUED)
X
X
X
X
X
X
X
X
DOUT (CONTINUED)
D6
D5
D4
D3
D1
D0
D7
D2
STOP
DATA BYTE 2
Figure 40. SPI—Reading Two Bytes of Data from Two Sequential Registers
CS
SPI
READ OPERATION
WRITE OPERATION
CS
Figure 41. SPI—Correct Use of During SPI Communications
INT
SMBALERT
INT
output is low responds to the
The INT/
Slave devices on the SMBus can normally not signal to the
SMBALERT
output can operate as an
function.
3. The device whose INT/
alert response address and the master reads its device
address. As the device address is seven bits long, an LSB of
1 is added. The address of the device is now known and it
can be interrogated in the usual way.
master that they want to talk, but the
allows them to do so.
the SMBus general call address.
function
is used in conjunction with
SMBALERT
INT
4. If more than one device’s INT/
output is low, the one
INT
One or more INT/
SMBALERT
SMBALERT
outputs can be connected to a common
with the lowest device address has priority, in accordance
with normal SMBus specifications.
line connected to the master. When the
line is pulled low by one of the devices, the
procedure shown in Figure 42 occurs.
5. Once the ADT7411 responds to the alert response address,
MASTER
RECEIVES
SMBALERT
INT
it resets its INT/
output, provided that the condition
that caused the out-of-limit event no longer exists and the
status register associated with the out-of-limit event is read.
ALERT RESPONSE
NO
ACK
START
RD ACK DEVICE ADDRESS
STOP
ADDRESS
SMBALERT
If the
line remains low, the master sends the
MASTER SENDS
ARA AND READ
COMMAND
ARA again. It continues to do this until all devices whose
DEVICE SENDS
ITS ADDRESS
SMBALERT
outputs were low have responded.
INT
SMBALERT
ARA
Figure 42. INT/
Responds to
MASTER
MASTER
NACK
MASTER
ACK
DEVICE ACK
RECEIVES
SMBALERT
SMBALERT
1.
is pulled low.
ALERT RESPONSE
DEVICE
ADDRESS
NO
START
RD ACK
ACK
PEC
STOP
ADDRESS
ACK
2. Master initiates a read operation and sends the alert
response address (ARA = 0001 100). This is a general call
address that must not be used as a specific device address.
MASTER SENDS
ARA AND READ
COMMAND
DEVICE SENDS DEVICE SENDS
ITS ADDRESS ITS PEC DATA
INT
SMBALERT
ARA with Packet Error Checking
Figure 43. INT/
Responds to
Rev. B | Page 34 of 36
ADT7411
OUTLINE DIMENSIONS
0.197
0.193
0.189
16
1
9
8
0.158
0.154
0.150
0.244
0.236
0.228
PIN 1
0.069
0.053
0.065
0.049
8°
0°
0.010
0.004
0.025
BSC
0.012
0.008
0.050
0.016
SEATING
PLANE
0.010
0.006
COPLANARITY
0.004
COMPLIANT TO JEDEC STANDARDS MO-137-AB
Figure 44. 16-Lead Shrink Small Outline Package [QSOP]
(RQ-16)
Dimensions shown in inches
ORDERING GUIDE
Model
ADT7411ARQ
ADT7411ARQ-REEL
ADT7411ARQ-REEL7
ADT7411ARQZ1
ADT7411ARQZ-REEL1
ADT7411ARQZ-REEL71
EVAL-ADT7411EBZ1
Temperature Range
Package Description
16-Lead QSOP
16-Lead QSOP
16-Lead QSOP
16-Lead QSOP
16-Lead QSOP
16-Lead QSOP
Evaluation Board
Package Option
RQ-16
RQ-16
RQ-16
RQ-16
Ordering Quantity
−40°C to +120°C
−40°C to +120°C
−40°C to +120°C
−40°C to +120°C
−40°C to +120°C
−40°C to +120°C
N/A
2,500
1,000
N/A
2,500
1,000
RQ-16
RQ-16
1 Z = Pb-free part.
Rev. B | Page 35 of 36
ADT7411
NOTES
Purchase of licensed I2C components of Analog Devices, Inc. or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C
Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C02882-0-12/06(B)
Rev. B | Page 36 of 36
相关型号：
©2020 ICPDF网 联系我们和版权申明