ADUC7019 [ADI]
Precision Analog Microcontroller 12-bit Analog I/O, ARM7TDMI MCU; 精密模拟微控制器12位模拟I / O ， ARM7TDMI MCU
| 型号： | ADUC7019 |
| 厂家： | 
ADI |
| 描述： | Precision Analog Microcontroller 12-bit Analog I/O, ARM7TDMI MCU |
| 文件： | 总92页 (文件大小：978K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Precision Analog Microcontroller 12-bit
Analog I/O, ARM7TDMI® MCU
ADuC7019/20/21/22/24/25/26/27
On-chip peripherals
FEATURES
Analog I/O
Multichannel, 12-bit, 1 MSPS ADC
Up to 16 ADC channels1
Fully differential and single-ended modes
0 to VREF analog input range
12-bit voltage output DACs
Up to 4 DAC outputs available1
On-chip voltage reference
On-chip temperature sensor ( 3°C)
Voltage comparator
UART, 2 × I2C® and SPI® serial I/O
Up to 40-pin GPIO port1
4 × general-purpose timers
Wake-up and watchdog timers (WDT)
Power supply monitor
Three-phase, 16-bit PWM generator1
Programmable logic array (PLA)
External memory interface, up to 512 kB1
Power
Specified for 3 V operation
Active mode: 11 mA @ 5 MHz; 40 mA @ 41.78 MHz
Packages and temperature range
From 40-lead 6 mm × 6 mm LFCSP to 80-lead LQFP1
Fully specified for –40°C to +125°C operation
Tools
Microcontroller
ARM7TDMI core, 16-bit/32-bit RISC architecture
JTAG port supports code download and debug
Clocking options
Trimmed on-chip oscillator ( 3ꢀ)
External watch crystal
External clock source up to 44 MHz
41.78 MHz PLL with programmable divider
Memory
Low-cost QuickStart™ development system
Full third-party support
APPLICATIONS
Industrial control and automation systems
Smart sensors, precision instrumentation
Base station systems, optical networking
62 kB flash/EE memory, 8 kB SRAM
In-circuit download, JTAG-based debug
Software triggered in-circuit reprogrammability
FUNCTIONAL BLOCK DIAGRAM
ADC0
12-BIT
DAC
DAC0
DAC1
DAC2
DAC3
1MSPS
MUX
12-BIT ADC
12-BIT
DAC
ADC11
TEMP
SENSOR
ADuC7026
12-BIT
DAC
CMP0
CMP1
BANDGAP
REF
12-BIT
DAC
CMP
OUT
V
REF
PWM0
PWM0
PWM1
PWM1
PWM2
PWM2
H
L
H
L
H
L
THREE-
PHASE
PWM
OSC
XCLKI
ARM7TDMI-BASED MCU WITH
ADDITIONAL PERIPHERALS
AND PLL
XCLKO
2k × 32 SRAM
31k × 16 FLASH/EEPROM
PSM
PLA
GPIO
JTAG
4 GENERAL
PURPOSE TIMERS
SERIAL I/O
RST
POR
EXT. MEMORY
INTERFACE
2
UART, SPI, I C
Figure 1.
1 Depending on part model. See Ordering Guide for more information.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice.
No license is granted by implication or otherwise under any patent or patent rights of Analog
Devices.Trademarks and registered trademarks are theproperty of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2006 Analog Devices, Inc. All rights reserved.
ADuC7019/20/21/22/24/25/26/27
TABLE OF CONTENTS
Features .............................................................................................. 1
Transfer Function....................................................................... 37
Typical Operation....................................................................... 38
MMRs Interface.......................................................................... 38
Converter Operation.................................................................. 40
Driving the Analog Inputs ........................................................ 42
Calibration................................................................................... 42
Temperature Sensor ................................................................... 42
Band Gap Reference................................................................... 42
Nonvolatile Flash/EE Memory ..................................................... 43
Programming.............................................................................. 43
Security ........................................................................................ 44
Flash/EE Control Interface ....................................................... 44
Execution Time from SRAM and Flash/EE............................ 46
Reset and Remap........................................................................ 46
Other Analog Peripherals.............................................................. 48
DAC.............................................................................................. 48
Power Supply Monitor............................................................... 49
Comparator................................................................................. 50
Oscillator and PLL—Power Control........................................ 51
Digital Peripherals.......................................................................... 53
Three-Phase PWM..................................................................... 53
General-Purpose Input/Output................................................ 60
Serial Port Mux........................................................................... 62
UART Serial Interface................................................................ 62
Serial Peripheral Interface......................................................... 65
I2C Compatible Interfaces ......................................................... 67
Programmable Logic Array (PLA)........................................... 71
Processor Reference Peripherals................................................... 74
Interrupt System......................................................................... 74
Timers.......................................................................................... 75
External Memory Interfacing ................................................... 79
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 3
General Description......................................................................... 4
Detailed Block Diagram .............................................................. 5
Specifications..................................................................................... 6
Timing Specifications .................................................................. 9
Absolute Maximum Ratings.......................................................... 16
ESD Caution................................................................................ 16
Pin Configurations and Function Descriptions ......................... 17
ADuC7019/ADuC7020/ADuC7021/ADuC7022 .................. 17
ADuC7024/ADuC7025 ............................................................. 20
ADuC7026/ADuC7027 ............................................................. 23
Typical Performance Characteristics ........................................... 27
Terminology .................................................................................... 30
ADC Specifications .................................................................... 30
DAC Specifications..................................................................... 30
Overview of the ARM7TDMI Core............................................. 31
Thumb Mode (T)........................................................................ 31
Long Multiply (M)...................................................................... 31
EmbeddedICE (I) ....................................................................... 31
Exceptions ................................................................................... 31
ARM Registers ............................................................................ 31
Interrupt Latency........................................................................ 32
Memory Organization ................................................................... 33
Memory Access........................................................................... 33
Flash/EE Memory....................................................................... 33
SRAM........................................................................................... 33
Memory Mapped Registers ....................................................... 33
ADC Circuit Overview.................................................................. 37
Rev. A | Page 2 of 92
ADuC7019/20/21/22/24/25/26/27
Hardware Design Considerations.................................................83
Power Supplies.............................................................................83
Grounding and Board Layout Recommendations .................84
Clock Oscillator...........................................................................84
Power-on Reset Operation.........................................................85
Typical System Configuration...................................................85
Development Tools .........................................................................86
PC-Based Tools ...........................................................................86
In-Circuit Serial Downloader ...................................................86
Outline Dimensions........................................................................87
Ordering Guide ...........................................................................89
REVISION HISTORY
1/06—Rev. 0 to Rev. A
Changes to Table 1 ............................................................................6
Added the Flash/EE Memory Reliability Section .......................43
Changes to Table 30 ........................................................................52
Changes to Serial Peripheral Interface .........................................66
Changes to Ordering Guide...........................................................90
10/05—Revision 0: Initial Version
Rev. A | Page 3 of 92
ADuC7019/20/21/22/24/25/26/27
GENERAL DESCRIPTION
The ADuC7019/7020/7021/7022/7024/7025/7026/7027 are fully
integrated, 1 MSPS, 12-bit data acquisition systems incorporat-
ing high performance multichannel ADCs, 16-bit/32-bit MCUs
and Flash/EE memory on a single chip.
The devices operate from an on-chip oscillator and a PLL
generating an internal high frequency clock of 41.78 MHz. This
clock is routed through a programmable clock divider from
which the MCU core clock operating frequency is generated.
The microcontroller core is an ARM7TDMI, 16-bit/32-bit RISC
machine, which offers up to 41 MIPS peak performance. Eight
kilobytes of SRAM and 62 kilobytes of nonvolatile Flash/EE
memory are provided on-chip. The ARM7TDMI core views all
memory and registers as a single linear array.
The ADC consists of up to 12 single-ended inputs. An
additional four inputs are available but are multiplexed
with the four DAC output pins. The four DAC outputs are
only available on certain models (ADuC7020, and ADuC7026).
However, in many cases where the DAC outputs are not present,
these pins can still be used as additional ADC inputs, giving a
maximum of 16 ADC input channels. The ADC can operate in
single-ended or differential input modes. The ADC input
voltage is 0 to VREF. Low-drift bandgap reference, temperature
sensor, and voltage comparator complete the ADC peripheral
set.
On-chip factory firmware supports in-circuit serial download
via the UART or I2C serial interface ports, while nonintrusive
emulation is also supported via the JTAG interface. These
features are incorporated into a low-cost QuickStart™
Development System supporting this MicroConverter® family.
The parts operate from 2.7 V to 3.6 V and are specified over an
industrial temperature range of −40°C to +125°C. When operating
at 41.78 MHz, the power dissipation is typically 120 mW. The
ADuC7019/7020/7021/7022/7024/7025/7026/7027 are available in
a variety of memory models and packages.
Depending on the part model, up to four buffered voltage
output DACs are available on-chip. The DAC output range is
programmable to one of three voltage ranges.
Rev. A | Page 4 of 92
ADuC7019/20/21/22/24/25/26/27
DETAILED BLOCK DIAGRAM
8
72 71 67 73 74
53 26 25 54
28 27 37
75 70 69
12-BIT
ADuC7026*
10
11
VOLTAGE
BUF
BUF
BUF
BUF
DAC0*/ADC12
DAC1*/ADC13
77
ADC0
ADC1 78
79
OUTPUTDAC
12-BIT SAR
ADC 1MSPS
ADC
ADC2/CMP0
ADC3/CMP1 80
12-BIT
VOLTAGE
OUTPUTDAC
CONTROL
1
2
3
4
5
6
7
ADC4
ADC5
ADC6
ADC7
ADC8
ADC9
ADC10
DAC
CONTROL
12-BIT
VOLTAGE
OUTPUTDAC
12 DAC2*/ADC14
MUX
12-BIT
VOLTAGE
OUTPUTDAC
13
DAC3*/ADC15
ADC11 76
TEMP
29 P3.0/AD0/PWM0 /PLAI[8]
H
SENSOR
9
ADCNEG
62KBYTES FLASH/EE
(31k × 16 BITS)
30 P3.1/AD1/PWM0 /PLAI[9]
L
31
32
P3.2/AD2/PWM1 /PLAI[10]
H
THREE-
PHASE
PWM
ARM7TDMI
P3.3/AD3/PWM1 /PLAI[11]
L
8192 BYTES USER RAM
/IRQ
(2k × 32 BITS)
MUX
38 P3.4/AD4/PWM2 /PLAI[12]
H
CMP
OUT
WAKEUP/
RTC TIMER
MCU
CORE
DAC
39 P3.5/AD5/PWM2 /PLAI[13]
L
BM/P0.0/CMP
/PLAI[7]/MS2 20
OUT
46
47
P3.6/AD6/PWM
P3.7/AD7/PWM
/PLAI[14]
/PLAI[15]
TRIP
POWER SUPPLY
MONITOR
DOWNLOADER
SYNC
68
V
V
REF
REF
OSC
BAND GAP
REFERENCE
44
XCLKO
PROG. CLOCK
DIVIDER
PLL
45 XCLKI
43
P0.7/ECLK/XCLK/SPM8/PLAO[4]
2
SPI/I C SERIAL
INTERFACE
UART
SERIAL PORT
P4.6/AD14/PLAO[14] 18
P4.7/AD15/PLAO[15] 19
PROG. LOGIC
ARRAY
40 IRQ0/P0.4/PWM
/PLAO[1]/MS1
/PLAO[2]/MS0
TRIP
INTERRUPT
CONTROLLER
POR
21
41
IRQ1/P0.5/ADC
BUSY
SERIAL PORT MULTIPLEXER
55 56 63 64 65 66 62 61 60 59 58 57 52 51
42
14 15 23 22 34
49 50 17 33 35 36 48 24 16
*SEE SELECTION TABLE FOR
FEATURE AVAILABILITY ON
DIFFERENT MODELS.
Figure 2.
Rev. A | Page 5 of 92
ADuC7019/20/21/22/24/25/26/27
SPECIFICATIONS
AVDD = IOVDD = 2.7 V to 3.6 V, VREF = 2.5 V internal reference, fCORE = 41.78 MHz, TA = 40°C to 125°C, unless otherwise noted.
Table 1.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
ADC CHANNEL SPECIFICATIONS
ADC Power-Up Time
DC Accuracy1, 2
Eight acquisition clocks and fADC/2
5
μs
Resolution
Integral Nonlinearity
12
Bits
LSB
LSB
LSB
LSB
LSB
0.6
1.0
0.5
+0.7/−0.6
1
1.5
2.5 V internal reference
1.0 V external reference
2.5 V internal reference
1.0 V external reference
ADC input is a dc voltage
Differential Nonlinearity3, 4
+1/−0.9
DC Code Distribution
ENDPOINT ERRORS5
Offset Error
Offset Error Match
Gain Error
1
1
2
1
2
5
LSB
LSB
LSB
LSB
Gain Error Match
DYNAMIC PERFORMANCE
Signal-to-Noise Ratio (SNR)
Total Harmonic Distortion (THD)
Peak Harmonic or Spurious Noise
Channel-to-Channel Crosstalk
ANALOG INPUT
fIN = 10 kHz sine wave, fSAMPLE = 1 MSPS
Includes distortion and noise components
69
dB
dB
dB
dB
−78
−75
−80
Measured on adjacent channels
Input Voltage Ranges
Differential Mode
6
VCM
V
VREF/2
0 to VREF
6
Single-Ended Mode
Leakage Current
Input Capacitance
V
ꢀA
pF
1
20
During ADC acquisition
ON-CHIP VOLTAGE REFERENCE
Output Voltage
0.47 ꢀF from VREF to AGND
2.5
V
Accuracy
5
mV
ppm/°C
dB
TA = 25°C
TA = 25°C
Reference Temperature Coefficient
Power Supply Rejection Ratio
Output Impedance
Internal VREF Power-On Time
EXTERNAL REFERENCE INPUT7
Input Voltage Range
Input Impedance
40
75
70
1
Ω
ms
0.625
AVDD
V
kΩ
65
DAC CHANNEL SPECIFICATIONS
DC ACCURACY8
RL = 5 kΩ, CL = 100 pF
Resolution
Relative Accuracy
Differential Nonlinearity
Offset Error
Gain Error9
12
2
Bits
LSB
LSB
mV
%
1
15
1
Guaranteed monotonic
2.5 V internal reference
Gain Error Mismatch
0.1
%
% of full scale on DAC0
Rev. A | Page 6 of 92
ADuC7019/20/21/22/24/25/26/27
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
ANALOG OUTPUTS
Output Voltage Range_0
0 to
V
DACREF range: DACGND to DACVDD
DACREF
Output Voltage Range_1
Output Voltage Range_2
0 to 2.5
0 to
V
V
DACVDD
Output Impedance
2
Ω
DAC AC CHARACTERISTICS
Voltage Output Settling Time
Digital to Analog Glitch Energy
COMPARATOR
10
20
ꢀs
nV-sec
1 LSB change at major carry
Input Offset Voltage
Input Bias Current
Input Voltage Range
Input Capacitance
Hysteresis4, 6
15
1
mV
ꢀA
V
pF
mV
AGND
2
AVDD − 1.2
15
7
3
Hysteresis can be turned on or off via the
CMPHYST bit in the CMPCON register
100 mV overdrive and configured with
CMPRES = 11
Response Time
ꢀs
TEMPERATURE SENSOR
Voltage Output at 25°C
Voltage TC
780
−1.3
3
mV
mV/°C
°C
Accuracy
POWER SUPPLY MONITOR (PSM)
IOVDD Trip Point Selection
2.79
3.07
2.5
V
V
%
V
Two selectable trip points
Power Supply Trip Point Accuracy
POWER-ON RESET
GLITCH IMMUNITY ON RESET PIN3
WATCHDOG TIMER (WDT)
Timeout Period
Of the selected nominal trip point voltage
2.36
50
ꢀs
0
512
sec
FLASH/EE MEMORY
Endurance10
Data Retention11
10,000
20
cycles
years
TJ = 85°C
DIGITAL INPUTS
Logic 1 Input Current
Logic 0 Input Current
All digital inputs excluding XCLKI and XCLKO
VIH = VDD or VIH = 5 V
VIL = 0 V; except TDI on
0.2
−40
1
−60
ꢀA
ꢀA
ADuC7019/20/21/22/24/25
−80
10
−120
0.8
ꢀA
pF
VIL = 0 V; TDI, on ADuC7019/20/21/22/24/25
Input Capacitance
LOGIC INPUTS3
VINL, Input Low Voltage
VINH, Input High Voltage
LOGIC OUTPUTS
VOH, Output High Voltage
VOL, Output Low Voltage12
CRYSTAL INPUTS XCLKI and XCLKO
Logic Inputs, XCLKI Only
VINL, Input Low Voltage
VINH, Input High Voltage
XCLKI Input Capacitance
XCLKO Output Capacitance
All logic inputs excluding XCLKI and XCLKO
V
V
2.0
2.4
All digital outputs excluding XCLKI and XCLKO
ISOURCE = 1.6 mA
ISINK = 1.6 mA
V
V
0.4
1.1
1.7
20
V
V
pF
pF
20
Rev. A | Page 7 of 92
ADuC7019/20/21/22/24/25/26/27
Parameter
Min
Typ
Max
Unit
kHz
%
Test Conditions/Comments
INTERNAL OSCILLATOR
32.768
3
MCU CLOCK RATE
From 32 kHz Internal Oscillator
From 32 kHz External Crystal
Using an External Clock
326
41.78
kHz
CD = 7
CD = 0
TA = 85°C
TA = 125°C
Core clock = 41.78 MHz
MHz
MHz
MHz
0.05
0.05
44
41.78
START-UP TIME
At Power-On
From Pause/Nap Mode
130
24
ms
ns
CD = 0
CD = 7
3.06
1.58
1.7
ꢀs
ms
ms
From Sleep Mode
From Stop Mode
PROGRAMMABLE LOGIC ARRAY (PLA)
Pin Propagation Delay
Element Propagation Delay
12
2.5
ns
ns
From input pin to output pin
13, 14
POWER REQUIREMENTS
Power Supply Voltage Range
AVDD − AGND and IOVDD − IOGND
Analog Power Supply Currents
AVDD Current
2.7
3.6
25
V
200
400
3
ꢀA
ꢀA
ꢀA
ADC in idle mode; all parts except ADuC7019
ADC in idle mode; ADuC7019 only
DACVDD Current15
Digital Power Supply Current
IOVDD Current in Normal Mode
Code executing from Flash/EE
CD = 7
CD = 3
CD = 0 (41.78 MHz clock)
CD = 0 (41.78 MHz clock)
TA = 85°C
7
10
15
45
30
400
1000
mA
mA
mA
mA
ꢀA
11
40
25
250
600
IOVDD Current in Pause Mode
IOVDD Current in Sleep Mode
ꢀA
TA = 125°C
Additional Power Supply Currents
ADC
2
0.7
700
mA
mA
ꢀA
@ 1 MSPS
@ 62.5 kSPS
per DAC
DAC
1 All ADC channel specifications are guaranteed during normal MicroConverter core operation.
2 Apply to all ADC input channels.
3 Measured using the factory set default values in ADCOF and ADCGN.
4 Not production tested but supported by design and/or characterization data on production release.
5 Measured using the factory set default values in ADCOF and ADCGN using an external AD845 op amp as an input buffer stage as shown in Figure 47. Based on
external ADC system components, the user may need to execute a system calibration to remove external endpoint errors and achieve these specifications (see the
Calibration section).
6 The input signal can be centered on any dc common-mode voltage (VCM) as long as this value is within the ADC voltage input range specified.
7 When using an external reference input pin, the internal reference must be disabled by setting the LSB in the REFCON memory mapped register to 0.
8 DAC linearity is calculated using a reduced code range of 100 to 3995.
9 DAC gain error is calculated using a reduced code range of 100 to internal 2.5 V VREF
.
10 Endurance is qualified as per JEDEC Standard 22 method A117 and measured at −40°C, +25°C, +85°C, and +125°C.
11 Retention lifetime equivalent at junction temperature (TJ) = 85°C as per JEDEC Standard 22 method A117. Retention lifetime derates with junction temperature.
12 Test carried out with a maximum of eight I/O set to a low output level.
13 Power supply current consumption is measured in normal, pause, and sleep modes under the following conditions: Normal Mode: 3.6 V supply, Pause Mode: 3.6 V
supply, Sleep Mode: 3.6 V supply.
14 IOVDD power supply current decreases typically by 2 mA during a flash/EE erase cycle.
15 On the ADuC7019/20/21/22, this current must be added to AVDD current.
Rev. A | Page 8 of 92
ADuC7019/20/21/22/24/25/26/27
TIMING SPECIFICATIONS
Table 2. External Memory Write Cycle
Parameter
Min
Typ
Max
Unit
CLK
UCLK
TMS_AFTER_CLKH
TADDR_AFTER_CLKH
TAE_H_AFTER_MS
TAE
THOLD_ADDR_AFTER_AE_L
THOLD_ADDR_BEFORE_WR_L
TWR_L_AFTER_AE_L
TDATA_AFTER_WR_L
TWR
TWR_H_AFTER_CLKH
THOLD_DATA_AFTER_WR_H
TBEN_AFTER_AE_L
TRELEASE_MS_AFTER_WR_H
0
4
4
8
ns
ns
½ CLK
(XMxPAR[14:12] + 1) x CLK
½ CLK + (!XMxPAR[10]) x CLK
(!XMxPAR[8]) x CLK
½ CLK + (!XMxPAR[10] + !XMxPAR[8]) x CLK
8
0
12
4
ns
ns
(XMxPAR[7:4] + 1) x CLK
(!XMxPAR[8]) x CLK
½ CLK
(!XMxPAR[8] + 1) x CLK
CLK
CLK
T
MS_AFTER_CLKH
MS
AE
T
WR_L_AFTER_AE_L
T
AE_H_AFTER_MS
T
WR
T
RELEASE_MS_AFTER_WR_H
T
AE
T
WR_H_AFTER_CLKH
WR
RD
T
HOLD_DATA_AFTER_WR_H
T
HOLD_ADDR_AFTER_AE_L
T
HOLD_ADDR_BEFORE_WR_L
T
T
ADDR_AFTER_CLKH
DATA_AFTER_WR_L
5678
A/D[15:0]
FFFF
9ABC
9ABE
1234
T
BEN_AFTER_AE_L
BEN0
BEN1
A16
Figure 3. External Memory Write Cycle
Rev. A | Page 9 of 92
ADuC7019/20/21/22/24/25/26/27
Table 3. External Memory Read Cycle
Parameter
CLK
Min
Typ
Max
Unit
UCLK
TMS_AFTER_CLKH
TADDR_AFTER_ CLKH
TAE_H_AFTER_MS
TAE
THOLD_ADDR_AFTER_AE_L
TRD_L_AFTER_AE_L
TDATA_AFTER_RD_L
TRD
4
4
8
16
ns
ns
½ CLK
(XMxPAR[14:12] + 1) x CLK
½ CLK + (!XMxPAR[10]) x CLK
½ CLK + (!XMxPAR[10] + !XMxPAR[9]) x CLK
8
0
12
4
ns
ns
(XMxPAR[3:0] + 1) x CLK
TRD_H_AFTER_CLKH
THOLD_DATA_AFTER_RD_H
TRELEASE_MS_AFTER_RD_H
(!XMxPAR[9]) x CLK
CLK
CLK
ECLK
GP0
T
MS_AFTER_CLKH
T
AE_H_AFTER_MS
T
RELEASE_MS_AFTER_RD_H
T
T
RD_H_AFTER_CLKH
AE
T
RD_L_AFTER_AE_L
AE
WR
T
RD
RD
T
HOLD_DATA_AFTER_RD_H
T
DATA_AFTER_RD_L
T
ADDR_AFTER_CLKH
234B
T
HOLD_ADDR_AFTER_AE_L
A/D[15:0]
FFFF
CDEF
D14A
234A
89AB
BEN1
BEN0
A16
Figure 4. External Memory Read Cycle
Rev. A | Page 10 of 92
ADuC7019/20/21/22/24/25/26/27
Table 4. I2C Timing in Fast Mode (400 kHz)
Slave
Parameter
Description
Min
200
100
300
100
50
100
100
1.3
Max
Master Typ
1360
1140
251350
740
400
Unit
ns
ns
ns
ns
ns
ns
ns
μs
ns
ns
ns
tL
tH
SCLOCK low pulse width1
SCLOCK high pulse width1
Start condition hold time
Data setup time
Data hold time
Setup time for repeated start
Stop condition setup time
Bus-free time between a stop condition and a start condition
Rise time for both CLOCK and SDATA
Fall time for both CLOCK and SDATA
Pulse width of spike suppressed
tSHD
tDSU
tDHD
tRSU
tPSU
tBUF
tR
12.51350
400
100
60
300
100
50
200
20
tF
tSUP
1 tHCLK depends on the clock divider or CD bits in PLLCON MMR. tHCLK = tUCLK/2CD
.
tBUF
tSUP
tR
MSB
tF
SDATA (I/O)
MSB
LSB
ACK
tDSU
tDSU
tDHD
tDHD
tPSU
tR
tSHD
tRSU
tH
1
2–7
8
9
1
SCLK (I)
tL
tSUP
PS
S(R)
tF
STOP
START
REPEATED
START
CONDITION CONDITION
Figure 5. I2C Compatible Interface Timing
Rev. A | Page 11 of 92
ADuC7019/20/21/22/24/25/26/27
Table 5. SPI Master Mode Timing (PHASE Mode = 1)
Parameter
Description
Min
Typ
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
tSL
tSH
SCLOCK low pulse width1
SCLOCK high pulse width1
Data output valid after SCLOCK edge
Data input setup time before SCLOCK edge2
Data input hold time after SCLOCK edge2
Data output fall time
(SPIDIV + 1) × tHCLK
(SPIDIV + 1) × tHCLK
tDAV
tDSU
tDHD
tDF
tDR
tSR
25
1 × tUCLK
2 × tUCLK
5
5
5
5
12.5
12.5
12.5
12.5
Data output rise time
SCLOCK rise time
SCLOCK fall time
tSF
ns
1 tHCLK depends on the clock divider or CD bits in PLLCON MMR. tHCLK = tUCLK/2CD
.
2 tUCLK = 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider.
SCLOCK
(POLARITY = 0)
tSH
tSL
tSR
tSF
SCLOCK
(POLARITY = 1)
tDAV
tDF
tDR
MOSI
MISO
MSB
BITS 6–1
LSB
MSB IN
tDSU
BITS 6–1
LSB IN
tDHD
Figure 6. SPI Master Mode Timing (PHASE Mode = 1)
Rev. A | Page 12 of 92
ADuC7019/20/21/22/24/25/26/27
Table 6. SPI Master Mode Timing (PHASE Mode = 0)
Parameter
Description
Min
Typ
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSL
tSH
SCLOCK low pulse width1
SCLOCK high pulse width1
Data output valid after SCLOCK edge
Data output setup before SCLOCK edge
Data input setup time before SCLOCK edge2
Data input hold time after SCLOCK edge2
Data output fall time
(SPIDIV + 1) × tHCLK
(SPIDIV + 1) × tHCLK
tDAV
tDOSU
tDSU
tDHD
tDF
tDR
tSR
tSF
25
75
1 × tUCLK
2 × tUCLK
5
5
5
5
12.5
12.5
12.5
12.5
Data output rise time
SCLOCK rise time
SCLOCK fall time
1 tHCLK depends on the clock divider or CD bits in PLLCON MMR. tHCLK = tUCLK/2CD
.
2 tUCLK = 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider.
SCLOCK
(POLARITY = 0)
tSH
tSL
tSR
tSF
SCLOCK
(POLARITY = 1)
tDAV
tDOSU
tDF
tDR
MOSI
MISO
MSB
BITS 6–1
LSB
MSB IN
tDSU
BITS 6–1
LSB IN
tDHD
Figure 7. SPI Master Mode Timing (PHASE Mode = 0)
Rev. A | Page 13 of 92
ADuC7019/20/21/22/24/25/26/27
Table 7. SPI Slave Mode Timing (PHASE Mode = 1)
Parameter
Description
CS to SCLOCK edge1
Min
Typ
Max
Unit
tCS
2 × tHCLK
2 × tUCLK
+
ns
tSL
tSH
SCLOCK low pulse width2
SCLOCK high pulse width2
Data output valid after SCLOCK edge
Data input setup time before SCLOCK edge1
Data input hold time after SCLOCK edge1
Data output fall time
Data output rise time
SCLOCK rise time
SCLOCK fall time
CS high after SCLOCK edge
(SPIDIV + 1) × tHCLK
(SPIDIV + 1) × tHCLK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tDAV
tDSU
tDHD
tDF
tDR
tSR
25
1 × tUCLK
2 × tUCLK
5
5
5
5
12.5
12.5
12.5
12.5
tSF
tSFS
0
1 tUCLK = 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider.
2 tHCLK depends on the clock divider or CD bits in PLLCON MMR. tHCLK = tUCLK/2CD
.
CS
tSFS
tCS
SCLOCK
(POLARITY = 0)
tSH
tSL
tSR
tSF
SCLOCK
(POLARITY = 1)
tDAV
tDF
tDR
MISO
MOSI
MSB
BITS 6–1
LSB
MSB IN
BITS 6–1
LSB IN
tDSU
tDHD
Figure 8. SPI Slave Mode Timing (PHASE Mode = 1)
Rev. A | Page 14 of 92
ADuC7019/20/21/22/24/25/26/27
Table 8. SPI Slave Mode Timing (PHASE Mode = 0)
Parameter
Description
Min
Typ
Max
Unit
tCS
CS to SCLOCK edge1
2 × tHCLK
2 × tUCLK
+
ns
tSL
tSH
tDAV
tDSU
tDHD
tDF
tDR
tSR
tSF
tDOCS
tSFS
SCLOCK low pulse width2
(SPIDIV + 1) × tHCLK
(SPIDIV + 1) × tHCLK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCLOCK high pulse width2
Data output valid after SCLOCK edge
Data input setup time before SCLOCK edge1
Data input hold time after SCLOCK edge1
Data output fall time
25
1 × tUCLK
2 × tUCLK
5
5
5
5
12.5
12.5
12.5
12.5
25
Data output rise time
SCLOCK rise time
SCLOCK fall time
Data output valid after CS edge
CS high after SCLOCK edge
0
1 tUCLK = 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider.
2 tHCLK depends on the clock divider or CD bits in PLLCON MMR. tHCLK = tUCLK/2CD
.
CS
tCS
tSFS
SCLOCK
(POLARITY = 0)
tSH
tSL
tSF
tSR
SCLOCK
(POLARITY = 1)
tDAV
tDOCS
tDF
tDR
MISO
MOSI
MSB
BITS 6–1
LSB
MSB IN
tDSU
BITS 6–1
LSB IN
tDHD
Figure 9. SPI Slave Mode Timing (PHASE Mode = 0)
Rev. A | Page 15 of 92
ADuC7019/20/21/22/24/25/26/27
ABSOLUTE MAXIMUM RATINGS
AGND = REFGND = DACGND = GNDREF
TA = 25°C, unless otherwise noted.
;
Table 9.
Parameter
AVDD to IOVDD
AGND to DGND
IOVDD to IOGND, AVDD to AGND
Digital Input Voltage to IOGND
Digital Output Voltage to IOGND
VREF to AGND
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rating
−0.3 V to +0.3 V
−0.3 V to +0.3 V
−0.3 V to +6 V
−0.3 V to +5.3 V
−0.3 V to IOVDD + 0.3 V
−0.3 V to AVDD + 0.3 V
−0.3 V to AVDD + 0.3 V
−0.3 V to AVDD + 0.3 V
Analog Inputs to AGND
Only one absolute maximum rating can be applied at any one
time.
Analog Outputs to AGND
Operating Temperature Range
Industrial
Storage Temperature Range
Junction Temperature
–40°C to +125°C
–65°C to +150°C
150°C
26°C/W
θJA Thermal Impedance (40-pin CSP)
θJA Thermal Impedance (64-pin CSP)
θJA Thermal Impedance (64-pin LQFP)
θJA Thermal Impedance (80-pin LQFP)
Peak Solder Reflow Temperature
SnPb Assemblies (10 sec to 30 sec)
24°C/W
47°C/W
38°C/W
240°C
Pb-Free Assemblies (20 sec to 40 sec) 260°C
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. A | Page 16 of 92
ADuC7019/20/21/22/24/25/26/27
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
ADuC7019/ADuC7020/ADuC7021/ADuC7022
ADC3/CMP1
ADC4
GNDREF
DAC0/ADC12
DAC1/ADC13
DAC2/ADC14
DAC3/ADC15
TMS
1
2
3
4
5
6
7
8
9
30 P1.3/SPM3/PLAI[3]
ADC4
ADC5
ADC6
1
2
3
4
5
6
7
8
9
30 P1.3/SPM3/PLAI[3]
PIN 1
INDICATOR
PIN 1
INDICATOR
29 P1.4/SPM4/PLAI[4]/IRQ2
28 P1.5/SPM5/PLAI[5]/IRQ3
27 P1.6/SPM6/PLAI[6]
29 P1.4/SPM4/PLAI[4]/IRQ2
28 P1.5/SPM5/PLAI[5]/IRQ3
27 P1.6/SPM6/PLAI[6]
ADC7
ADuC7019/
26 P1.7/SPM7/PLAO[0]
25 XCLKI
GNDREF
DAC0/ADC12
DAC1/ADC13
TMS
26 P1.7/SPM7/PLAO[0]
25 XCLKI
ADuC7020
ADuC7021
TOP VIEW
(Not to Scale)
TOP VIEW
24 XCLKO
24 XCLKO
(Not to Scale)
23 P0.7/ECLK/XCLK/SPM8/PLAO[4]
22 P2.0/SPM9/PLAO[5]/CONVSTART
21 IRQ1/P0.5/ADCBUSY/PLAO[2]
23 P0.7/ECLK/XCLK/SPM8/PLAO[4]
22 P2.0/SPM9/PLAO[5]/CONVSTART
21 IRQ1/P0.5/ADCBUSY/PLAO[2]
TDI
TDI
BM/P0.0/CMPOUT/PLAI[7] 10
BM/P0.0/CMPOUT/PLAI[7] 10
Figure 10. ADuC7019/ADuC7020 40-Lead LFCSP_VQ Pin Configuration
Figure 11. ADuC702140-Lead LFCSP_VQ Pin Configuration
ADC5
1
2
3
4
5
6
7
8
9
30 P1.2/SPM2/PLAI[2]
29 P1.3/SPM3/PLAI[3]
28 P1.4/SPM4/PLAI[4]/IRQ2
27 P1.5/SPM5/PLAI[5]/IRQ3
26 P1.6/SPM6/PLAI[6]
25 P1.7/SPM7/PLAO[0]
24 XCLKI
PIN 1
INDICATOR
ADC6
ADC7
ADC8
ADC9
ADuC7022
GNDREF
TMS
TDI
TOP VIEW
(Not to Scale)
23 XCLKO
BM/P0.0/CMPOUT/PLAI[7]
P0.6/T1/MRST/PLAO[3] 10
22 P0.7/ECLK/XCLK/SPM8/PLAO[4]
21 P2.0/SPM9/PLAO[5]/CONVSTART
Figure 12. ADuC7022 40-Lead LFCSP_VQ Pin Configuration
Rev. A | Page 17 of 92
ADuC7019/20/21/22/24/25/26/27
Table 10. Pin Function Descriptions (ADuC7019/ADuC7020/ADuC7021/ADuC7022)
Pin No.
7019/7020 7021 7022 Mnemonic
Description
38
39
40
1
37
38
39
40
36
37
38
39
ADC0
ADC1
ADC2/CMP0
ADC3/CMP1
Single-Ended or Differential Analog Input 0.
Single-Ended or Differential Analog Input 1.
Single-Ended or Differential Analog Input 2/Comparator Positive Input.
Single-Ended or Differential Analog Input 3 (Buffered Input on
ADuC7019)/Comparator Negative Input.
2
‒
‒
‒
‒
‒
3
1
2
40
1
ADC4
ADC5
Single-Ended or Differential Analog Input 4.
Single-Ended or Differential Analog Input 5.
3
4
2
3
4
5
6
ADC6
ADC7
ADC8
ADC9
GNDREF
Single-Ended or Differential Analog Input 6.
Single-Ended or Differential Analog Input 7.
Single-Ended or Differential Analog Input 8.
Single-Ended or Differential Analog Input 9.
‒
‒
5
Ground Voltage Reference for the ADC. For optimal performance, the
analog power supply should be separated from IOGND and DGND.
4
5
6
7
6
7
‒
‒
DAC0/ADC12
DAC1/ADC13
DAC2/ADC14
DAC3/ADC15
DAC0 Voltage Output/Single-Ended or Differential Analog Input 12.
DAC1 Voltage Output/Single-Ended or Differential Analog Input 13.
DAC2 Voltage Output/Single-Ended or Differential Analog Input 14.
‒
‒
‒
‒
DAC3 Voltage Output on ADuC7020. On the ADuC7019, a 10 nF capacitor
needs to be connected between this pin and AGND/Single-Ended or
Differential Analog Input 15.
8
9
10
8
9
10
7
8
9
TMS
TDI
Test Mode Select, JTAG Test Port Input. Debug and download access.
Test Data In, JTAG Test Port Input. Debug and download access.
Multifunction I/O Pin.
BM/P0.0/CMPOUT/PLAI[7]
Boot Mode (BM). The ADuC7019/20/21/22 enter serial download mode if
BM is low at reset and execute code if BM is pulled high at reset through a
1 kΩ resistor. General-Purpose Input and Output Port 0.0/Voltage
Comparator Output/Programmable Logic Array Input Element 7.
11
11
10
P0.6/T1/MRST/PLAO[3]
Multifunction Pin, Driven Low After Reset. General-Purpose Output Port
0.6/Timer1 Input/Power-On Reset Output/Programmable Logic Array
Output Element 3.
12
13
14
15
16
12
13
14
15
16
11
12
13
14
15
TCK
TDO
IOGND
IOVDD
LVDD
Test Clock, JTAG Test Port Input. Debug and download access.
Test Data Out, JTAG Test Port Output. Debug and download access.
Ground for GPIO. Typically connected to DGND.
3.3 V Supply for GPIO and Input of the On-Chip Voltage Regulator.
2.6 V Output of the On-Chip Voltage Regulator. This output must be
connected to a 0.47 ꢀf capacitor to DGND only.
17
18
17
18
16
17
DGND
P0.3/TRST/ADCBUSY
Ground for Core Logic.
General-Purpose Input and Output Port 0.3/Test Reset, JTAG Test Port
Input/ ADCBUSY Signal Output.
19
20
19
20
18
19
RST
Reset Input, Active Low.
IRQ0/P0.4/PWMTRIP/PLAO[1]
Multifunction I/O Pin. External Interrupt Request 0, Active High/General-
Purpose Input and Output Port 0.4/PWM Trip External
Input/Programmable Logic Array Output Element 1.
21
22
23
24
21
22
23
24
20
21
22
23
IRQ1/P0.5/ADCBUSY/PLAO[2]
Multifunction I/O Pin. External Interrupt Request 1, Active High/General-
Purpose Input andOutput Port 0.5/ADCBUSY Signa l Output/Programmable
Logic Array Output Element 2.
Serial Port Multiplexed. General-Purpose Input and Output Port 2.0/UART/
Programmable Logic Array Output Element 5/Start Conversion Input Signal
for ADC.
P2.0/SPM9/PLAO[5]/CONVSTART
P0.7/ECLK/XCLK/SPM8/PLAO[4] Serial Port Multiplexed. General-Purpose Input and Output Port
0.7/Output for External Clock Signal/Input to the Internal Clock Generator
Circuits/UART/ Programmable Logic Array Output Element 4.
XCLKO
Output from the Crystal Oscillator Inverter.
Rev. A | Page 18 of 92
ADuC7019/20/21/22/24/25/26/27
Pin No.
7019/7020 7021 7022 Mnemonic
Description
25
26
27
28
25
26
27
28
24
25
26
27
XCLKI
Input to the Crystal Oscillator Inverter and Input to the Internal Clock
Generator Circuits.
Serial Port Multiplexed. General-Purpose Input and Output Port 1.7/UART,
SPI/Programmable Logic Array Output Element 0.
Serial Port Multiplexed. General-Purpose Input and Output Port 1.6/UART,
SPI/Programmable Logic Array Input Element 6.
Serial Port Multiplexed. General-Purpose Input and Output Port 1.5/UART,
SPI/Programmable Logic Array Input Element 5/External Interrupt
Request 3, Active High.
P1.7/SPM7/PLAO[0]
P1.6/SPM6/PLAI[6]
P1.5/SPM5/PLAI[5]/IRQ3
29
29
28
P1.4/SPM4/PLAI[4]/IRQ2
Serial Port Multiplexed. General-Purpose Input and Output Port 1.4/UART,
SPI/Programmable Logic Array Input Element 4/External Interrupt
Request 2, Active High.
30
31
32
33
34
35
30
31
32
33
29
30
31
32
P1.3/SPM3/PLAI[3]
P1.2/SPM2/PLAI[2]
P1.1/SPM1/PLAI[1]
P1.0/T1/SPM0/PLAI[0]
P4.2/PLAO[10]
Serial Port Multiplexed. General-Purpose Input and Output Port 1.3/UART,
I2C1/Programmable Logic Array Input Element 3.
Serial Port Multiplexed. General-Purpose Input and Output Port 1.2/UART,
I2C1/Programmable Logic Array Input Element 2.
Serial Port Multiplexed. General-Purpose Input and Output Port 1.1/UART,
I2C0/Programmable Logic Array Input Element 1.
Serial Port Multiplexed. General-Purpose Input and Output Port 1.0/
Timer1 Input/UART, I2C0/Programmable Logic Array Input Element 0.
General-Purpose Input and Output Port 4.2/Programmable Logic Array
Output Element 10.
2.5 V Internal Voltage Reference. Must be connected to a 0.47 ꢀF capacitor
when using the internal reference.
‒
‒
34
33
VREF
36
37
35
36
34
35
AGND
AVDD
Analog Ground. Ground reference point for the analog circuitry.
3.3 V Analog Power.
Rev. A | Page 19 of 92
ADuC7019/20/21/22/24/25/26/27
ADuC7024/ADuC7025
ADC4
ADC5
ADC6
ADC7
ADC8
ADC9
1
2
3
4
5
6
7
8
9
48 P1.2/SPM2/PLAI[2]
47 P1.3/SPM3/PLAI[3]
46 P1.4/SPM4/PLAI[4]/IRQ2
45 P1.5/SPM5/PLAI[5]/IRQ3
44 P4.1/PLAO[9]
PIN 1
INDICATOR
ADuC7024/
43 P4.0/PLAO[8]
GND
42 IOV
REF
DD
ADuC7025
ADCNEG
DAC0/ADC12
DAC1/ADC13 10
TMS 11
TDI 12
P4.6/PLAO[14] 13
P4.7/PLAO[15] 14
41 IOGND
40 P1.6/SPM6/PLAI[6]
39 P1.7/SPM7/PLAO[0]
TOP VIEW
(Not to Scale)
38 P3.7/PWM
37 P3.6/PWM
36 XCLKI
/PLAI[15]
/PLAI[14]
SYNC
TRIP
35 XCLKO
BM/P0.0/CMP /PLAI[7] 15
OUT
34 P0.7/ECLK/XCLK/SPM8/PLAO[4]
P0.6/T1/MRST/PLAO[3] 16
33 P2.0/SPM9/PLAO[5]/CONV
START
Figure 13. ADuC7024/ADuC7025 64-Lead LFCSP_VQ Pin Configuration
ADC4
ADC5
ADC6
ADC7
ADC8
ADC9
1
2
3
4
5
6
7
8
9
48 P1.2/SPM2/PLAI[2]
47 P1.3/SPM3/PLAI[3]
46 P1.4/SPM4/PLAI[4]/IRQ2
45 P1.5/SPM5/PLAI[5]/IRQ3
44 P4.1/PLAO[9]
PIN 1
INDICATOR
ADuC7024/
43 P4.0/PLAO[8]
GND
42 IOV
REF
DD
ADuC7025
ADCNEG
DAC0/ADC12
DAC1/ADC13 10
TMS 11
TDI 12
P4.6/PLAO[14] 13
P4.7/PLAO[15] 14
41 IOGND
40 P1.6/SPM6/PLAI[6]
39 P1.7/SPM7/PLAO[0]
TOP VIEW
(Not to Scale)
38 P3.7/PWM
37 P3.6/PWM
36 XCLKI
/PLAI[15]
/PLAI[14]
SYNC
TRIP
35 XCLKO
BM/P0.0/CMP /PLAI[7] 15
OUT
34 P0.7/ECLK/XCLK/SPM8/PLAO[4]
P0.6/T1/MRST/PLAO[3] 16
33 P2.0/SPM9/PLAO[5]/CONV
START
Figure 14. ADuC7024/ADuC7025 64-Lead LQFP Pin Configuration
Rev. A | Page 20 of 92
ADuC7019/20/21/22/24/25/26/27
Table 11. Pin Function Descriptions (ADuC7024/ADuC7025 64-Lead CSP and ADuC7024/ADuC7025 64-Lead LQFP)
Pin No. Mnemonic
Description
1
2
3
4
5
6
7
ADC4
ADC5
ADC6
ADC7
ADC8
ADC9
GNDREF
Single-Ended or Differential Analog Input 4.
Single-Ended or Differential Analog Input 5.
Single-Ended or Differential Analog Input 6.
Single-Ended or Differential Analog Input 7.
Single-Ended or Differential Analog Input 8.
Single-Ended or Differential Analog Input 9.
Ground Voltage Reference for the ADC. For optimal performance, the analog power supply
should be separated from IOGND and DGND.
8
ADCNEG
Bias Point or Negative Analog Input of the ADC in Pseudo Differential Mode. Must be connected
to the ground of the signal to convert. This bias point must be between 0 V and 1 V.
9
DAC0/ADC12
DAC1/ADC13
DAC0 Voltage Output/Single-Ended or Differential Analog Input 12. DAC outputs are not
present on the ADuC7025.
DAC1 Voltage Output/Single-Ended or Differential Analog Input 13. DAC outputs are not
present on the ADuC7025.
10
11
12
13
14
15
TMS
TDI
JTAG Test Port Input, Test Mode Select. Debug and download access.
JTAG Test Port Input, Test Data In. Debug and download access
General-Purpose Input and Output Port 4.6/Programmable Logic Array Output Element 14.
General-Purpose Input and Output Port 4.7/Programmable Logic Array Output Element 15.
Multifunction I/O Pin. Boot mode. The ADuC7024/ADuC7025 enter download mode if BM is low at
reset and executes code if BM is pulled high at reset through a 1 kΩ resistor/General-Purpose Input
and Output Port 0.0/Voltage Comparator Output/Programmable Logic Array Input Element 7.
P4.6/PLAO[14]
P4.7/PLAO[15]
BM/P0.0/CMPOUT/PLAI[7]
16
P0.6/T1/MRST/PLAO[3]
Multifunction Pin, Driven Low After Reset. General-Purpose Output Port 0.6/Timer1
Input/Power-On Reset Output/Programmable Logic Array Output Element 3.
17
18
19
20
21
TCK
TDO
IOGND
IOVDD
LVDD
JTAG Test Port Input, Test Clock. Debug and download access.
JTAG Test Port Output, Test Data Out. Debug and download access.
Ground for GPIO. Typically connected to DGND.
3.3 V Supply for GPIO and Input of the On-Chip Voltage Regulator.
2.6 V Output of the On-Chip Voltage Regulator. This output must be connected to a 0.47 ꢀF
capacitor to DGND only.
22
23
DGND
P3.0/PWM0H/PLAI[8]
Ground for Core Logic.
General-Purpose Input and Output Port 3.0/PWM Phase 0 High-Side Output/Programmable
Logic Array Input Element 8.
24
25
26
27
P3.1/PWM0L/PLAI[9]
P3.2/PWM1H/PLAI[10]
P3.3/PWM1L/PLAI[11]
P0.3/TRST/ADCBUSY
General-Purpose Input and Output Port 3.1/PWM Phase 0 Low-Side Output/Programmable
Logic Array Input Element 9.
General-Purpose Input and Output Port 3.2/PWM Phase 1 High-Side Output/Programmable
Logic Array Input Element 10.
General-Purpose Input and Output Port 3.3/PWM Phase 1 Low-Side Output/Programmable
Logic Array Input Element 11.
General-Purpose Input and Output Port 0.3/JTAG Test Port Input, Test Reset/ADCBUSY Signal
Output.
28
29
RST
Reset Input, Active Low.
P3.4/PWM2H/PLAI[12]
General-Purpose Input and Output Port 3.4/PWM Phase 2 High-Side Output/Programmable
Logic Array Input 12.
30
31
32
33
34
P3.5/PWM2L/PLAI[13]
General-Purpose Input and Output Port 3.5/PWM Phase 2 Low-Side Output/Programmable
Logic Array Input Element 13.
Multifunction I/O Pin. External Interrupt Request 0, Active High/General-Purpose Input and
Output Port 0.4/PWM Trip External Input/Programmable Logic Array Output Element 1.
Multifunction I/O Pin. External Interrupt Request 1, Active High/General-Purpose Input and
Output Port 0.5/ADCBUSY Signal Output/Programmable Logic Array Output Element 2.
Serial Port Multiplexed. General-Purpose Input and Output Port 2.0/UART/Programmable Logic
Array Output Element 5/Start Conversion Input Signal for ADC.
IRQ0/P0.4/PWMTRIP/PLAO[1]
IRQ1/P0.5/ADCBUSY/PLAO[2]
P2.0/SPM9/PLAO[5]/CONVSTART
P0.7/ECLK/XCLK/SPM8/PLAO[4]
Serial Port Multiplexed. General-Purpose Input and Output Port 0.7/Output for External Clock
Signal/Input to the Internal Clock Generator Circuits/UART/Programmable Logic Array Output
Element 4.
35
XCLKO
Output from the Crystal Oscillator Inverter.
Rev. A | Page 21 of 92
ADuC7019/20/21/22/24/25/26/27
Pin No. Mnemonic
Description
36
37
XCLKI
P3.6/PWMTRIP/PLAI[14]
Input to the Crystal Oscillator Inverter and Input to the Internal Clock Generator Circuits.
General-Purpose Input and Output Port 3.6/PWM Safety Cut Off/Programmable Logic Array
Input Element 14.
38
39
40
P3.7/PWMSYNC/PLAI[15]
P1.7/SPM7/PLAO[0]
P1.6/SPM6/PLAI[6]
General-Purpose Input and Output Port 3.7/PWM Synchronization Input Output/Programmable
Logic Array Input Element 15.
Serial Port Multiplexed. General-Purpose Input and Output Port 1.7/UART, SPI/Programmable
Logic Array Output Element 0.
Serial Port Multiplexed. General-Purpose Input and Output Port 1.6/UART, SPI/Programmable
Logic Array Input Element 6.
41
42
43
44
45
IOGND
IOVDD
P4.0/PLAO[8]
P4.1/PLAO[9]
P1.5/SPM5/PLAI[5]/IRQ3
Ground for GPIO. Typically connected to DGND.
3.3 V Supply for GPIO and Input of the On-Chip Voltage Regulator.
General-Purpose Input and Output Port 4.0/Programmable Logic Array Output Element 8.
General-Purpose Input and Output Port 4.1/Programmable Logic Array Output Element 9.
Serial Port Multiplexed. General-Purpose Input and Output Port 1.5/UART, SPI/Programmable
Logic Array Input Element 5/External Interrupt Request 3, Active High.
46
47
48
49
50
P1.4/SPM4/PLAI[4]/IRQ2
P1.3/SPM3/PLAI[3]
P1.2/SPM2/PLAI[2]
P1.1/SPM1/PLAI[1]
P1.0/T1/SPM0/PLAI[0]
Serial Port Multiplexed. General-Purpose Input and Output Port 1.4/UART, SPI/Programmable
Logic Array Input Element 4/External Interrupt Request 2, Active High.
Serial Port Multiplexed. General-Purpose Input and Output Port 1.3/UART, I2C1/Programmable
Logic Array Input Element 3.
Serial Port Multiplexed. General-Purpose Input and Output Port 1.2/UART, I2C1/Programmable
Logic Array Input Element 2.
Serial Port Multiplexed. General-Purpose Input and Output Port 1.1/UART, I2C0/Programmable
Logic Array Input Element 1.
Serial Port Multiplexed. General-Purpose Input and Output Port 1.0/Timer1 Input/UART,
I2C0/Programmable Logic Array Input Element 0.
51
52
53
54
55
P4.2/PLAO[10]
P4.3/PLAO[11]
P4.4/PLAO[12]
P4.5/PLAO[13]
VREF
General-Purpose Input and Output Port 4.2/Programmable Logic Array Output Element 10.
General-Purpose Input and Output Port 4.3/Programmable Logic Array Output Element 11.
General-Purpose Input and Output Port 4.4/Programmable Logic Array Output Element 12.
General-Purpose Input and Output Port 4.5/Programmable Logic Array Output Element 13.
2.5 V Internal Voltage Reference. Must be connected to a 0.47 ꢀF capacitor when using the
internal reference.
56
57
58
59
60
61
62
63
64
DACREF
DACGND
AGND
AVDD
DACVDD
ADC0
ADC1
ADC2/CMP0
ADC3/CMP1
External Voltage Reference for the DACs. Range: DACGND to DACVDD.
Ground for the DAC. Typically connected to AGND.
Analog Ground. Ground reference point for the analog circuitry.
3.3 V Analog Power.
3.3 V Power Supply for the DACs. Typically connected to AVDD.
Single-Ended or Differential Analog Input 0.
Single-Ended or Differential Analog Input 1.
Single-Ended or Differential Analog Input 2/Comparator Positive Input.
Single-Ended or Differential Analog Input 3/Comparator Negative Input.
Rev. A | Page 22 of 92
ADuC7019/20/21/22/24/25/26/27
ADuC7026/ADuC7027
ADC4
ADC5
ADC6
ADC7
ADC8
ADC9
ADC10
1
2
3
4
5
6
7
8
9
60 P1.2/SPM2/PLAI[2]
59 P1.3/SPM3/PLAI[3]
58 P1.4/SPM4/PLAI[4]/IRQ2
57 P1.5/SPM5/PLAI[5]/IRQ3
56 P4.1/AD9/PLAO[9]
55 P4.0/AD8/PLAO[8]
PIN 1
INDICATOR
54 IOV
53 IOGND
DD
GND
REF
ADuC7026/
ADuC7027
ADCNEG
52 P1.6/SPM6/PLAI[6]
51 P1.7/SPM7/PLAO[0]
DAC0/ADC12 10
DAC1/ADC13 11
DAC2/ADC14 12
DAC3/ADC15 13
TMS 14
50 P2.2/RS/PWM0 /PLAO[7]
L
TOP VIEW
49 P2.1/WS/PWM0 /PLAO[6]
(Not to Scale)
H
48 P2.7/PWM1 /MS3
L
47 P3.7/AD7/PWM
46 P3.6/AD6/PWM
45 XCLKI
/PLAI[15]
SYNC
/PLAI[14]
TDI 15
TRIP
P0.1/PWM2 /BLE 16
H
P2.3/AE 17
P4.6/AD14/PLAO[14] 18
P4.7/AD15/PLAO[15] 19
44 XCLKO
43 P0.7/ECLK/XCLK/SPM8/PLAO[4]
42 P2.0/SPM9/PLAO[5]/CONV
START
/PLAO[2]/MS0
BM/P0.0/CMP
/PLAI[7]/MS2 20
41 IRQ1/P0.5/ADC
OUT
BUSY
Figure 15. ADuC7026/ADuC7027 80-Lead LQFP Pin Configuration
Table 12. Pin Function Descriptions (ADuC7026/ADuC7027)
Pin No. Mnemonic
Description
1
2
3
4
5
6
7
8
ADC4
ADC5
ADC6
ADC7
ADC8
ADC9
ADC10
GNDREF
Single-Ended or Differential Analog Input 4.
Single-Ended or Differential Analog Input 5.
Single-Ended or Differential Analog Input 6.
Single-Ended or Differential Analog Input 7.
Single-Ended or Differential Analog Input 8.
Single-Ended or Differential Analog Input 9.
Single-Ended or Differential Analog Input 10.
Ground Voltage Reference for the ADC. For optimal performance, the analog power supply
should be separated from IOGND and DGND.
9
ADCNEG
Bias Point or Negative Analog Input of the ADC in Pseudo Differential Mode. Must be connected
to the ground of the signal to convert. This bias point must be between 0 V and 1 V.
10
11
12
13
DAC0/ADC12
DAC1/ADC13
DAC2/ADC14
DAC3/ADC15
DAC0 Voltage Output/Single-Ended or Differential Analog Input 12. DAC outputs are not
present on the ADuC7027.
DAC1 Voltage Output/Single-Ended or Differential Analog Input 13. DAC outputs are not
present on the ADuC7027.
DAC2 Voltage Output/Single-Ended or Differential Analog Input 14. DAC outputs are not
present on the ADuC7027.
DAC3 Voltage Output/Single-Ended or Differential Analog Input 15. DAC outputs are not
present on the ADuC7027.
Rev. A | Page 23 of 92
ADuC7019/20/21/22/24/25/26/27
Pin No. Mnemonic
Description
14
15
16
TMS
TDI
P0.1/PWM2H/BLE
JTAG Test Port Input, Test Mode Select. Debug and download access.
JTAG Test Port Input, Test Data In. Debug and download access.
General-Purpose Input and Output Port 0.1/PWM Phase 2 High-Side Output/External Memory
Byte Low Enable.
17
18
P2.3/AE
P4.6/AD14/PLAO[14]
General-Purpose Input and Output Port 2.3/External Memory Access Enable.
General-Purpose Input and Output Port 4.6/External Memory Interface/Programmable Logic
Array Output Element 14.
19
20
P4.7/AD15/PLAO[15]
General-Purpose Input and Output Port 4.7/External Memory Interface/Programmable Logic
Array Output Element 15.
Multifunction I/O Pin. Boot Mode. The ADuC7026/ADuC7027 enter UART download mode if
BM is low at reset and execute code if BM is pulled high at reset through a 1 kΩ resistor/
General-Purpose Input and Output Port 0.0/Voltage Comparator Output/Programmable Logic
Array Input Element 7/External Memory Select 2.
BM/P0.0/CMPOUT/PLAI[7]/MS2
21
P0.6/T1/MRST/PLAO[3]/AE
Multifunction Pin, Driven Low After Reset. General-Purpose Output Port 0.6/Timer1
Input/Power-On Reset Output/Programmable Logic Array Output Element 3.
22
23
24
TCK
TDO
P0.2/ PWM2L/BHE
JTAG Test Port Input, Test Clock. Debug and download access.
JTAG Test Port Output, Test Data Out. Debug and download access.
General-Purpose Input and Output Port 0.2/PWM Phase 2 Low-Side Output/External Memory
Byte High Enable.
25
26
27
IOGND
IOVDD
LVDD
Ground for GPIO. Typically connected to DGND.
3.3 V Supply for GPIO and Input of the On-Chip Voltage Regulator.
2.6 V Output of the On-Chip Voltage Regulator. This output must be connected to a 0.47 ꢀF
capacitor to DGND only.
28
29
DGND
Ground for Core Logic.
P3.0/AD0/PWM0H/PLAI[8]
General-Purpose Input and Output Port 3.0/External Memory Interface/PWM Phase 0 High-
Side Output/Programmable Logic Array Input Element 8.
30
31
32
33
34
35
36
P3.1/AD1/PWM0L/PLAI[9]
P3.2/AD2/PWM1H/PLAI[10]
P3.3/AD3/PWM1L/PLAI[11]
P2.4/PWM0H/MS0
General-Purpose Input and Output Port 3.1/External Memory Interface/PWM Phase 0 Low-
Side Output/Programmable Logic Array Input Element 9.
General-Purpose Input and Output Port 3.2/External Memory Interface/PWM Phase 1 High-
Side Output/Programmable Logic Array Input Element 10.
General-Purpose Input and Output Port 3.3/External Memory Interface/PWM Phase 1 Low-
Side Output/Programmable Logic Array Input Element 11.
General-Purpose Input and Output Port 2.4/PWM Phase 0 High-Side Output/External Memory
Select 0.
General-Purpose Input and Output Port 0.3/JTAG Test Port Input, Test Reset/ADCBUSY Signal
Output.
General-Purpose Input and Output Port 2.5/PWM Phase 0 Low-Side Output/External Memory
Select 1.
General-Purpose Input and Output Port 2.6/PWM Phase 1 High-Side Output/External Memory
Select 2.
P0.3/TRST/A16/ADCBUSY
P2.5/PWM0L/MS1
P2.6/PWM1H/MS2
37
38
RST
Reset Input, Active Low.
P3.4/AD4/PWM2H/PLAI[12]
General-Purpose Input and Output Port 3.4/External Memory Interface/PWM Phase 2 High-
Side Output/Programmable Logic Array Input 12.
39
40
P3.5/AD5/PWM2L/PLAI[13]
General-Purpose Input and Output Port 3.5/External Memory Interface/PWM Phase 2 Low-
Side Output/Programmable Logic Array Input Element 13.
IRQ0/P0.4/PWMTRIP/PLAO[1]/MS1 Multifunction I/O Pin. External Interrupt Request 0, Active High/General-Purpose Input and
Output Port 0.4/PWM Trip External Input/Programmable Logic Array Output Element
1/External Memory Select 1.
41
42
IRQ1/P0.5/ADCBUSY/PLAO[2]/MS0 Multifunction I/O Pin. External Interrupt Request 1, Active High/General-Purpose Input and
Output Port 0.5/ADCBUSY Signal Output/Programmable Logic Array Output Element 2/External
Memory Select 0.
P2.0/SPM9/PLAO[5]/CONVSTART
Serial Port Multiplexed. General-Purpose Input and Output Port 2.0/UART/Programmable Logic
Array Output Element 5/Start Conversion Input Signal for ADC.
Rev. A | Page 24 of 92
ADuC7019/20/21/22/24/25/26/27
Pin No. Mnemonic
Description
43
P0.7/ECLK/XCLK/SPM8/ PLAO[4]
Serial Port Multiplexed. General-Purpose Input and Output Port 0.7/Output for External Clock
Signal/Input to the Internal Clock Generator Circuits/UART/Programmable Logic Array Output
Element 4.
44
45
46
XCLKO
XCLKI
Output from the Crystal Oscillator Inverter.
Input to the Crystal Oscillator Inverter and Input to the Internal Clock Generator Circuits.
General-Purpose Input and Output Port 3.6/External Memory Interface/PWM Safety Cut
Off/Programmable Logic Array Input Element 14.
P3.6/AD6/PWMTRIP/PLAI[14]
47
48
49
50
51
52
P3.7/AD7/PWMSYNC/PLAI[15]
P2.7/PWM1L/MS3
General-Purpose Input and Output Port 3.7/External Memory Interface/PWM
Synchronization/Programmable Logic Array Input Element 15.
General-Purpose Input and Output Port 2.7/PWM Phase 1 Low-Side Output/External Memory
Select 3.
General-Purpose Input and Output Port 2.1/External Memory Write Strobe/PWM Phase 0
High-Side Output/Programmable Logic Array Output Element 6.
General-Purpose Input and Output Port 2.2/External Memory Read Strobe/PWM Phase 0 Low-
Side Output/Programmable Logic Array Output Element 7.
Serial Port Multiplexed. General-Purpose Input and Output Port 1.7/UART, SPI/Programmable
Logic Array Output Element 0.
Serial Port Multiplexed. General-Purpose Input and Output Port 1.6/UART, SPI/Programmable
Logic Array Input Element 6.
P2.1/WS/PWM0H/PLAO[6]
P2.2/RS/PWM0L/PLAO[7]
P1.7/SPM7/PLAO[0]
P1.6/SPM6/PLAI[6]
53
54
55
IOGND
IOVDD
P4.0/AD8/PLAO[8]
Ground for GPIO. Typically connected to DGND.
3.3 V Supply for GPIO and Input of the On-Chip Voltage Regulator.
General-Purpose Input and Output Port 4.0/External Memory Interface/Programmable Logic
Array Output Element 8.
56
57
58
59
60
61
62
63
64
65
66
P4.1/AD9/PLAO[9]
General-Purpose Input and Output Port 4.1/External Memory Interface/Programmable Logic
Array Output Element 9.
Serial Port Multiplexed. General-Purpose Input and Output Port 1.5/UART, SPI/Programmable
Logic Array Input Element 5/External Interrupt Request 3, Active High.
Serial Port Multiplexed. General-Purpose Input and Output Port 1.4/UART, SPI/Programmable
Logic Array Input Element 4/External Interrupt Request 2, Active High.
Serial Port Multiplexed. General-Purpose Input and Output Port 1.3/UART, I2C1/Programmable
Logic Array Input Element 3.
Serial Port Multiplexed. General-Purpose Input and Output Port 1.2/UART, I2C1/Programmable
Logic Array Input Element 2.
Serial Port Multiplexed. General-Purpose Input and Output Port 1.1/UART, I2C0/Programmable
Logic Array Input Element 1.
Serial Port Multiplexed. General-Purpose Input and Output Port 1.0/Timer1 Input/UART,
I2C0/Programmable Logic Array Input Element 0.
General-Purpose Input and Output Port 4.2/External Memory Interface/Programmable Logic
Array Output Element 10.
P1.5/SPM5/PLAI[5]/IRQ3
P1.4/SPM4/PLAI[4]/IRQ2
P1.3/SPM3/PLAI[3]
P1.2/SPM2/PLAI[2]
P1.1/SPM1/PLAI[1]
P1.0/T1/SPM0/PLAI[0]
P4.2/AD10/PLAO[10]
P4.3/AD11/PLAO[11]
P4.4/AD12/PLAO[12]
P4.5/AD13/PLAO[13]
General-Purpose Input and Output Port 4.3/External Memory Interface/Programmable Logic
Array Output Element 11.
General-Purpose Input and Output Port 4.4/External Memory Interface/Programmable Logic
Array Output Element 12.
General-Purpose Input and Output Port 4.5/External Memory Interface/Programmable Logic
Array Output Element 13.
67
68
REFGND
VREF
Ground for the Reference. Typically connected to AGND.
2.5 V Internal Voltage Reference. Must be connected to a 0.47 ꢀF capacitor when using the
internal reference.
69
70
71, 72
73, 74
DACREF
DACGND
AGND
AVDD
External Voltage Reference for the DACs. Range: DACGND to DACVDD.
Ground for the DAC. Typically connected to AGND.
Analog Ground. Ground reference point for the analog circuitry.
3.3 V Analog Power.
Rev. A | Page 25 of 92
ADuC7019/20/21/22/24/25/26/27
Pin No. Mnemonic
Description
75
76
77
78
79
80
DACVDD
ADC11
ADC0
ADC1
ADC2/CMP0
ADC3/CMP1
3.3 V Power Supply for the DACs. Typically connected to AVDD.
Single-Ended or Differential Analog Input 11.
Single-Ended or Differential Analog Input 0.
Single-Ended or Differential Analog Input 1.
Single-Ended or Differential Analog Input 2/Comparator Positive Input.
Single-Ended or Differential Analog Input 3/Comparator Negative Input.
Rev. A | Page 26 of 92
ADuC7019/20/21/22/24/25/26/27
TYPICAL PERFORMANCE CHARACTERISTICS
1.0
1.0
0.8
fS = 774kSPS
fS = 774kSPS
0.8
0.6
0.4
0.6
0.4
0.2
0.2
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.2
–0.4
–0.6
–0.8
–1.0
0
1000
2000
3000
4000
0
1000
2000
3000
4000
ADC CODES
ADC CODES
Figure 16. Typical INL Error, fS = 774 kSPS
Figure 19. Typical DNL Error, fS = 774 kSPS
1.0
0.8
1.0
0.8
fS = 1MSPS
fS = 1MSPS
0.6
0.6
0.4
0.4
0.2
0.2
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.2
–0.4
–0.6
–0.8
–1.0
0
1000
2000
3000
4000
0
1000
2000
3000
4000
ADC CODES
ADC CODES
Figure 17. Typical INL Error, fS = 1 MSPS
Figure 20. Typical DNL Error, fS = 1 MSPS
1.0
0
–0.1
0
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
–0.7
–0.8
–0.9
–1.0
–0.2
–0.3
–0.5
–0.6
–0.7
–0.8
–0.9
–1.0
WCN
WCP
WCP
WCN
1.0
1.5
2.0
2.5
3.0
1.0
1.5
2.0
2.5
3.0
EXTERNAL REFERENCE (V)
EXTERNAL REFERENCE (V)
Figure 18. Typical Worst Case INL Error vs. VREF, fS = 774 kSPS
Figure 21. Typical Worst Case DNL Error vs. VREF, fS = 774 kSPS
Rev. A | Page 27 of 92
ADuC7019/20/21/22/24/25/26/27
9000
8000
7000
6000
5000
4000
3000
2000
1000
0
75
70
65
60
55
50
45
40
–76
–78
–80
–82
–84
–86
–88
SNR
THD
1161
1162
BIN
1163
1.0
1.5
2.0
2.5
3.0
EXTERNAL REFERENCE (V)
Figure 22. Code Histogram Plot, fs = 774 kSPS, VIN = 0.7 V
Figure 25. Typical Dynamic Performance vs. VREF
0
1500
1450
1400
1350
1300
1250
1200
1150
1100
1050
1000
fS = 774kSPS,
SNR = 69.3dB,
THD = –80.8dB,
PHSN = –83.4dB
–20
–40
–60
–80
–100
–120
–140
–160
0
100
200
–50
0
50
100
150
FREQUENCY (kHz)
TEMPERATURE (°C)
Figure 23. Dynamic Performance, fS = 774 kSPS
Figure 26. On-Chip Temperature Sensor Voltage Output vs. Temperature
20
0
39.8
39.7
39.6
39.5
39.4
39.3
39.2
39.1
39.0
38.9
fS = 1MSPS,
SNR = 70.4dB,
THD = –77.2dB,
PHSN = –78.9dB
–20
–40
–60
–80
–100
–120
–140
–160
0
50
100
150
200
–40
0
25
85
125
FREQUENCY (kHz)
TEMPERATURE (°C)
Figure 24. Dynamic Performance, fS = 1 MSPS
Figure 27. Current Consumption vs. Temperature @ CD = 0
Rev. A | Page 28 of 92
ADuC7019/20/21/22/24/25/26/27
12.05
12.00
11.95
11.90
11.85
11.80
11.75
11.70
11.65
11.60
11.55
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
–40
0
25
85
125
–40
0
25
85
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 28. Current Consumption vs. Temperature @ CD = 3
Figure 30. Current Consumption vs. Temperature in Sleep Mode
7.85
37.4
7.80
7.75
7.70
7.65
7.60
7.55
7.50
7.45
7.40
37.2
37.0
36.8
36.6
36.4
36.2
–40
0
25
85
125
62.25
125.00
250.00
500.00
1000.00
TEMPERATURE (°C)
SAMPLING FREQUENCY (kSPS)
Figure 29. Current Consumption vs. Temperature @ CD = 7
Figure 31. Current Consumption vs. ADC Speed
Rev. A | Page 29 of 92
ADuC7019/20/21/22/24/25/26/27
TERMINOLOGY
The theoretical signal to (noise + distortion) ratio for an ideal
N-bit converter with a sine wave input is given by
ADC SPECIFICATIONS
Integral Nonlinearity
The maximum deviation of any code from a straight line
passing through the endpoints of the ADC transfer function.
The endpoints of the transfer function are zero scale, a point
½ LSB below the first code transition and full scale, a point
½ LSB above the last code transition.
Signal to (Noise + Distortion) = (6.02 N + 1.76) dB
Thus, for a 12-bit converter, this is 74 dB.
Total Harmonic Distortion
The ratio of the rms sum of the harmonics to the fundamental.
Differential Nonlinearity
The difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
DAC SPECIFICATIONS
Relative Accuracy
Otherwise known as endpoint linearity, relative accuracy is a
measure of the maximum deviation from a straight line passing
through the endpoints of the DAC transfer function. It is
measured after adjusting for zero error and full-scale error.
Offset Error
The deviation of the first code transition (0000 . . . 000) to
(0000 . . . 001) from the ideal, that is, +½ LSB.
Gain Error
Voltage Output Settling Time
The deviation of the last code transition from the ideal AIN
voltage (full scale − 1.5 LSB) after the offset error has been
adjusted out.
The amount of time it takes for the output to settle to within a
1 LSB level for a full-scale input change.
Signal to (Noise + Distortion) Ratio
The measured ratio of signal to (noise + distortion) at the
output of the ADC. The signal is the rms amplitude of the
fundamental. Noise is the rms sum of all nonfundamental
signals up to half the sampling frequency (fS/2), excluding dc.
The ratio is dependent upon the number of quantization levels
in the digitization process; the more levels, the smaller the
quantization noise.
Rev. A | Page 30 of 92
ADuC7019/20/21/22/24/25/26/27
OVERVIEW OF THE ARM7TDMI CORE
The ARM7® core is a 32-bit reduced instruction set computer
(RISC). It uses a single 32-bit bus for instruction and data. The
length of the data can be 8 bits, 16 bits, or 32 bits. The length of
the instruction word is 32 bits.
When a breakpoint or watchpoint is encountered, the
processor halts and enters debug state. Once in a debug
state, the processor registers can be inspected as well as the
Flash/EE, the SRAM, and the memory mapped registers.
The ARM7TDMI is an ARM7 core with four additional
features:
EXCEPTIONS
ARM supports five types of exceptions and a privileged
processing mode for each type. The five types of exceptions are:
•
•
•
•
T support for the thumb (16 bit) instruction set
D support for debug
M support for long multiplications
I includes the embeddedICE module to support embedded
system debugging
•
•
Normal interrupt or IRQ. This is provided to service
general-purpose interrupt handling of internal and
external events.
Fast interrupt or FIQ. This is provided to service data
transfer or communication channel with low latency. FIQ
has priority over IRQ.
THUMB MODE (T)
An ARM instruction is 32 bits long. The ARM7TDMI processor
supports a second instruction set that has been compressed
into 16 bits, called the thumb instruction set. Faster execution
from 16-bit memory and greater code density can usually be
achieved by using the thumb instruction set instead of the ARM
instruction set, which makes the ARM7TDMI core particularly
suitable for embedded applications.
•
•
•
Memory abort.
Attempted execution of an undefined instruction.
Software interrupt instruction (SWI). This can be used to
make a call to an operating system.
However, the thumb mode has two limitations:
Typically, the programmer defines interrupt as IRQ, but for
higher priority interrupt, that is, faster response time, the
programmer can define interrupt as FIQ.
•
•
Thumb code usually uses more instructions for the same
job. As a result, ARM code is usually best for maximizing
the performance of the time-critical code.
ARM REGISTERS
ARM7TDMI has a total of 37 registers: 31 general-purpose
registers and six status registers. Each operating mode has
dedicated banked registers.
The thumb instruction set does not include some of the
instructions needed for exception handling, which
automatically switches the core to ARM code for exception
handling.
When writing user-level programs, 15 general-purpose 32-bit
registers (R0 to R14), the program counter (R15) and the
current program status register (CPSR) are usable. The
remaining registers are only used for system-level programming
and for exception handling.
See the ARM7TDMI user guide for details on the core
architecture, the programming model, and both the ARM and
ARM thumb instruction sets.
LONG MULTIPLY (M)
When an exception occurs, some of the standard registers are
replaced with registers specific to the exception mode. All
exception modes have replacement banked registers for the stack
pointer (R13) and the link register (R14) as represented in
Figure 32. The fast interrupt mode has more registers (R8 to R12) for
fast interrupt processing. This means the interrupt processing can
begin without the need to save or restore these registers, and thus
save critical time in the interrupt handling process.
The ARM7TDMI instruction set includes four extra instruc-
tions that perform 32-bit by 32-bit multiplication with 64-bit
result, and 32-bit by 32-bit multiplication-accumulation (MAC)
with 64-bit result. These results are achieved in fewer cycles
than required on a standard ARM7 core.
EMBEDDEDICE (I)
EmbeddedICE provides integrated on-chip support for the core.
The EmbeddedICE module contains the breakpoint and
watchpoint registers that allow code to be halted for debugging
purposes. These registers are controlled through the JTAG test port.
Rev. A | Page 31 of 92
ADuC7019/20/21/22/24/25/26/27
R0
R1
USABLE IN USER MODE
INTERRUPT LATENCY
SYSTEM MODES ONLY
R2
The worst case latency for a fast interrupt request (FIQ) consists
of the following:
R3
R4
R5
•
The longest time the request can take to pass through
the synchronizer
R6
R7
R8_FIQ
R9_FIQ
R8
R9
•
The time for the longest instruction to complete
(the longest instruction is an LDM) that loads all
the registers including the PC
R10_FIQ
R11_FIQ
R12_FIQ
R13_FIQ
R14_FIQ
R10
R11
R12
R13
R14
R15 (PC)
R13_UND
R13_IRQ
R13_ABT
R14_ABT
R14_UND
R14_IRQ
R13_SVC
R14_SVC
•
•
The time for the data abort entry
The time for FIQ entry
SPSR_UND
SPSR_IRQ
SPSR_ABT
SPSR_SVC
CPSR
SPSR_FIQ
At the end of this time, the ARM7TDMI executes the instruc-
tion at 0x1C (FIQ interrupt vector address). The maximum
total time is 50 processor cycles, which is just under 1.2 μs in a
system using a continuous 41.78 MHz processor clock.
FIQ
SVC
ABORT
MODE
IRQ
UNDEFINED
MODE
USER MODE
MODE
MODE
MODE
Figure 32. Register Organization
More information relative to the programmer’s model and the
ARM7TDMI core architecture can be found in the following
documents from ARM:
The maximum interrupt request (IRQ) latency calculation is
similar, but must allow for the fact that FIQ has higher priority
and could delay entry into the IRQ handling routine for an
arbitrary length of time. This time can be reduced to 42 cycles
if the LDM command is not used. Some compilers have an
option to compile without using this command. Another
option is to run the part in thumb mode, where the time
is reduced to 22 cycles.
•
•
DDI0029G, ARM7TDMI Technical Reference Manual
DDI0100E, ARM Architecture Reference Manual
The minimum latency for FIQ or IRQ interrupts is a total of
five cycles, which consist of the shortest time the request can
take through the synchronizer, plus the time to enter the
exception mode.
Note that the ARM7TDMI always runs in ARM (32-bit) mode
when in privileged modes, for example, when executing
interrupt service routines.
Rev. A | Page 32 of 92
ADuC7019/20/21/22/24/25/26/27
MEMORY ORGANIZATION
The ADuC7019/7020/7021/7022/7024/7025/7026/7027
incorporate two separate blocks of memory: 8 kB of SRAM and
64 kB of on-chip Flash/EE memory. Sixty-two kilobytes of on-
chip Flash/EE memory is available to the user, and the
remaining 2 kB are reserved for the factory configured boot
page. These two blocks are mapped as shown in Figure 33.
FLASH/EE MEMORY
The total 64 kB of Flash/EE memory is organized as 32 k ×
16 bits (31 k × 16 bits is user space and 1 k × 16 bits is reserved
for the on-chip kernel). The page size of this Flash/EE memory
is 512 bytes.
Sixty-two kilobytes of Flash/EE memory are available to the
user as code and nonvolatile data memory. There is no
distinction between data and program as ARM code shares the
same space. The real width of the Flash/EE memory is 16 bits,
which means that in ARM mode (32-bit instruction), two
accesses to the Flash/EE are necessary for each instruction
fetch. It is therefore recommended to use thumb mode when
executing from Flash/EE memory for optimum access speed.
The maximum access speed for the Flash/EE memory is
41.78 MHz in thumb mode and 20.89 MHz in full ARM mode.
More details about Flash/EE access time are outlined later in the
Execution Time from SRAM and Flash/EE section of this data
sheet.
0xFFFFFFFF
MMRs
0xFFFF0000
RESERVED
0x40000FFFF
EXTERNAL MEMORY REGION 3
0x40000000
RESERVED
0x30000FFFF
EXTERNAL MEMORY REGION 2
0x30000000
RESERVED
0x20000FFFF
EXTERNAL MEMORY REGION 1
0x20000000
RESERVED
0x10000FFFF
EXTERNAL MEMORY REGION 0
0x10000000
RESERVED
0x0008FFFF
SRAM
FLASH/EE
0x00080000
Eight kilobytes of SRAM are available to the user, organized as
2 k × 32 bits, that is, two words. ARM code can run directly
from SRAM at 41.78 MHz, given that the SRAM array is
configured as a 32-bit wide memory array. More details about
SRAM access time are outlined later in the Execution Time
from SRAM and Flash/EE section of this datasheet.
RESERVED
0x00011FFF
SRAM
0x00010000
0x0000FFFF REMAPPABLE MEMORY SPACE
0x00000000
(FLASH/EE OR SRAM)
Figure 33. Physical Memory Map
Note that by default, after a reset, the Flash/EE memory is
mirrored at address 0×00000000. It is possible to remap the
SRAM at address 0×00000000 by clearing Bit 0 of the REMAP
MMR. This remap function is described in more detail in the
Flash/EE Memory section.
MEMORY MAPPED REGISTERS
The memory mapped register (MMR) space is mapped into the
upper two pages of the memory array, and accessed by indirect
addressing through the ARM7 banked registers.
The MMR space provides an interface between the CPU and
all on-chip peripherals. All registers, except the core registers,
reside in the MMR area. All shaded locations shown in
Figure 35 are unoccupied or reserved locations, and should
not be accessed by user software. Table 13 shows the full MMR
memory map.
MEMORY ACCESS
The ARM7 core sees memory as a linear array of 232 byte
location where the different blocks of memory are mapped as
outlined in Figure 33.
The ADuC7019/7020/7021/7022/7024/7025/7026/7027
memory organizations are configured in little endian format,
which means that the least significant byte is located in the
lowest byte address, and the most significant byte is in the
highest byte address.
The access time for reading from or writing to an MMR
depends on the advanced microcontroller bus architecture
(AMBA) bus used to access the peripheral. The processor has
two AMBA busses: advanced high performance bus (AHB)
used for system modules, and advanced peripheral bus (APB)
used for lower performance peripheral. Access to the AHB is
one cycle, and access to the APB is two cycles. All peripherals
on the ADuC7019/7020/7021/7022/7024/7025/7026/7027 are
on the APB except the Flash/EE memory, the GPIOs, and the
PWM.
BIT 31
BIT 0
BYTE 3 BYTE 2 BYTE 1 BYTE 0
.
.
.
.
.
.
.
.
.
.
.
.
0xFFFFFFFF
B
7
3
A
6
2
9
5
1
8
4
0
0x00000004
0x00000000
32 BITS
Figure 34. Little Endian Format
Rev. A | Page 33 of 92
ADuC7019/20/21/22/24/25/26/27
0xFFFFFFFF
Table 13. Complete MMR List
0xFFFFFC3C
Access
Byte Type
Default
Value
PWM
0xFFFFFC00
Address Name
Page
IRQ address base = 0xFFFF0000
0xFFFFF820
FLASH CONTROL
INTERFACE
0x0000
0x0004
0x0008
0x000C
0x0010
0x0100
0x0104
0x0108
0x010C
IRQSTA
IRQSIG1
IRQEN
IRQCLR
SWICFG
FIQSTA
FIQSIG1
FIQEN
4
4
4
4
4
4
4
4
4
R
R
R/W
W
W
R
R
R/W
W
0x00000000
0x00XXX000 74
0x00000000
0x00000000
0x00000000
0x00000000
0x00XXX000 75
0x00000000
0x00000000
74
0xFFFFF800
0xFFFFF46C
74
74
75
74
GPIO
0xFFFFF400
0xFFFF0B54
PLA
0xFFFF0B00
0xFFFF0A14
SPI
0xFFFF0A00
75
75
FIQCLR
1 Depends on the level on the external interrupt pins (P0.4, P0.5, P1.4, and P1.5).
0xFFFF0948
2
I C1
0xFFFF0900
0xFFFF0848
System control address base = 0xFFFF0200
REMAP1
RSTSTA
RSTCLR
1
1
1
R/W
R/W
W
0x00
0x01
0x00
47
47
47
2
0x0220
0x0230
0x0234
I C0
0xFFFF0800
0xFFFF0730
UART
1 Depends on model.
0xFFFF0700
0xFFFF0620
Timer address base = 0xFFFF0300
DAC
0xFFFF0600
0x0300
0x0304
0x0308
0x030C
0x0320
0x0324
0x0328
0x032C
0x0330
0x0340
0x0344
0x0348
0x034C
0x0360
0x0364
0x0368
0x036C
T0LD
2
2
2
1
4
4
2
1
4
4
4
2
1
2
2
2
1
R/W
R
R/W
W
R/W
R
R/W
W
R/W
R/W
R
R/W
W
R/W
R
R/W
W
0x0000
0xFFFF
0x0000
0xFF
0x00000000
0xFFFFFFFF
0x0000
76
76
76
76
76
76
76
77
77
77
77
78
78
78
78
78
79
0xFFFF0538
T0VAL
T0CON
T0CLRI
T1LD
T1VAL
T1CON
T1CLRI
T1CAP
T2LD
T2VAL
T2CON
T2CLRI
T3LD
T3VAL
T3CON
T3CLRI
ADC
0xFFFF0500
0xFFFF0490
BAND GAP
REFERENCE
0xFFFF048C
0xFFFF0448
POWER SUPPLY
MONITOR
0xFF
0xFFFF0440
0x00000000
0x00000000
0xFFFFFFFF
0x0000
0xFF
0x0000
0xFFFF
0x0000
0x00
0xFFFF0420
PLL AND
OSCILLATOR CONTROL
0xFFFF0404
0xFFFF0370
WATCHDOG
TIMER
0xFFFF0360
0xFFFF0350
WAKE UP
TIMER
0xFFFF0340
0xFFFF0334
GENERAL PURPOSE
TIMER
0xFFFF0320
0xFFFF0310
TIMER 0
PLL base address = 0xFFFF0400
0x0404
0x0408
0x040C
0x0410
0x0414
0x0418
POWKEY1
POWCON
POWKEY2
PLLKEY1
PLLCON
2
2
2
2
1
2
W
R/W
W
W
R/W
W
0x0000
0x0003
0x0000
0x0000
0x21
52
52
52
52
52
52
0xFFFF0300
0xFFFF0238
REMAP AND
SYSTEM CONTROL
0xFFFF0220
0xFFFF0110
INTERRUPT
CONTROLLER
0xFFFF0000
PLLKEY2
0x0000
Figure 35. Memory Mapped Registers
PSM address base = 0xFFFF0440
0x0440
0x0444
PSMCON
CMPCON
2
2
R/W
R/W
0x0008
0x0000
49
50
Reference address base = 0xFFFF0480
0x048C REFCON R/W
1
0x00
42
Rev. A | Page 34 of 92
ADuC7019/20/21/22/24/25/26/27
Access
Byte Type
Default
Value
Access
Byte Type
Default
Value
Address Name
Page
Address Name
Page
ADC address base = 0xFFFF0500
I2C0 base address = 0xFFFF0800
0x0500
0x0504
0x0508
0x050C
0x0510
0x0514
0x0530
0x0534
ADCCON
ADCCP
2
1
1
1
4
1
2
2
R/W
R/W
R/W
R
0x0600
0x00
0x01
0x00
0x00000000
0x00
39
39
40
40
40
40
40
40
0x0800
0x0804
0x0808
0x080C
0x0810
0x0814
0x0818
0x081C
0x0824
0x0828
0x082C
0x0830
0x0838
0x083C
0x0840
0x0844
0x0848
0x084C
I2C0MSTA
I2C0SSTA
I2C0SRX
I2C0STX
I2C0MRX
I2C0MTX
I2C0CNT
I2C0ADR
I2C0BYTE
I2C0ALT
I2C0CFG
I2C0DIV
I2C0ID0
1
1
1
1
1
1
1
1
1
1
1
2
1
1
1
1
1
2
R
R
R
W
R
W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
0x00
0x01
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x1F1F
0x00
0x00
0x00
0x00
0x01
0x0000
68
68
69
69
69
69
69
69
69
69
70
70
70
70
70
70
70
71
ADCCN
ADCSTA
ADCDAT
ADCRST
ADCGN
ADCOF
R
R/W
R/W
R/W
0x0200
0x0200
DAC address base = 0xFFFF0600
0x0600
0x0604
0x0608
0x060C
0x0610
0x0614
0x0618
0x061C
DAC0CON
DAC0DAT
DAC1CON
DAC1DAT
DAC2CON
DAC2DAT
DAC3CON
DAC3DAT
1
4
1
4
1
4
1
4
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0x00
0x00000000
0x00
0x00000000
0x00
0x00000000
0x00
48
48
48
48
48
48
48
48
I2C0ID1
I2C0ID2
I2C0ID3
I2C0CCNT
I2C0FSTA
0x00000000
I2C1 base address = 0xFFFF0900
UART base address = 0xFFFF0700
0x0900
0x0904
0x0908
0x090C
0x0910
0x0914
0x0918
0x091C
0x0924
0x0928
0x092C
0x0930
0x0938
0x093C
0x0940
0x0944
0x0948
0x094C
I2C1MSTA
I2C1SSTA
I2C1SRX
I2C1STX
I2C1MRX
I2C1MTX
I2C1CNT
I2C1ADR
I2C1BYTE
I2C1ALT
I2C1CFG
I2C1DIV
I2C1ID0
1
1
1
1
1
1
1
1
1
1
1
2
1
1
1
1
1
2
R
R
R
W
R
W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
0x00
0x01
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x1F1F
0x00
0x00
0x00
0x00
0x01
0x0000
68
68
69
69
69
69
69
69
69
69
69
70
70
70
70
70
70
70
0x0700
COMTX
COMRX
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
R/W
R
R/W
R/W
R/W
R
R/W
R/W
R
0x00
0x00
0x00
0x00
0x00
0x01
0x00
0x00
0x60
0x00
0x00
0x04
0x01
0xAA
0x0000
63
63
63
63
63
63
63
64
64
64
64
65
65
65
64
COMDIV0
COMIEN0
COMDIV1
COMIID0
COMCON0
COMCON1
COMSTA0
COMSTA1
COMSCR
COMIEN1
COMIID1
COMADR
COMDIV2
0x0704
0x0708
0x070C
0x0710
0x0714
0x0718
0x071C
0x0720
0x0724
0x0728
0x072C
R
R/W
R/W
R
R/W
R/W
I2C1ID1
I2C1ID2
I2C1ID3
I2C1CCNT
I2C1FSTA
SPI base address = 0xFFFF0A00
0x0A00
0x0A04
0x0A08
0x0A0C
0x0A10
SPISTA
SPIRX
SPITX
SPIDIV
SPICON
1
1
1
1
2
R
R
W
R/W
R/W
0x00
0x00
0x00
0x1B
0x0000
66
66
66
66
66
Rev. A | Page 35 of 92
ADuC7019/20/21/22/24/25/26/27
Access
Byte Type
Default
Value
Access
Byte Type
Default
Value
Address Name
Page
Address Name
Page
PLA base address = 0xFFFF0B00
GPIO base address = 0xFFFFF400
0x0B00
0x0B04
0x0B08
0x0B0C
0x0B10
0x0B14
0x0B18
0x0B1C
0x0B20
0x0B24
0x0B28
0x0B2C
0x0B30
0x0B34
0x0B38
0x0B3C
0x0B40
0x0B44
0x0B48
0x0B4C
0x0B50
0x0B54
PLAELM0
PLAELM1
PLAELM2
PLAELM3
PLAELM4
PLAELM5
PLAELM6
PLAELM7
PLAELM8
PLAELM9
PLAELM10
PLAELM11
PLAELM12
PLAELM13
PLAELM14
PLAELM15
PLACLK
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1
4
4
4
4
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x00
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
72
73
73
73
73
73
0xF400
0xF404
0xF408
0xF40C
0xF410
0xF420
0xF424
0xF428
0xF42C
0xF430
0xF434
0xF438
0xF43C
0xF440
0xF444
0xF448
0xF450
0xF454
0xF458
0xF45C
0xF460
0xF464
0xF468
GP0CON
GP1CON
GP2CON
GP3CON
GP4CON
GP0DAT
GP0SET
GP0CLR
GP0PAR
GP1DAT
GP1SET
GP1CLR
GP1PAR
GP2DAT
GP2SET
GP2CLR
GP3DAT
GP3SET
GP3CLR
GP3PAR
GP4DAT
GP4SET
GP4CLR
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
R/W
R/W
R/W
R/W
R/W
R/W
W
W
W
R/W
W
W
W
R/W
W
W
R/W
W
W
W
R/W
W
W
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x000000XX 61
0x000000XX 61
0x000000XX 61
60
60
60
60
60
0x20000000
61
0x000000XX 61
0x000000XX 61
0x000000XX 61
0x00000000
61
0x000000XX 61
0x000000XX 61
0x000000XX 61
0x000000XX 61
0x000000XX 61
0x000000XX 61
PLAIRQ
PLAADC
PLADIN
PLADOUT
PLALCK
0x00000000
0x00000000
0x00000000
0x00000000
0x00
0x00222222
61
0x000000XX 61
0x000000XX 61
0x000000XX 61
W
External memory base address = 0xFFFFF000
Flash/EE base address = 0xFFFFF800
0xF000
0xF010
0xF014
0xF018
0xF01C
0xF020
0xF024
0xF028
0xF02C
XMCFG
1
1
1
1
1
2
2
2
2
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0x00
0x00
0x00
0x00
80
80
80
80
80
80
80
80
80
XM0CON
XM1CON
XM2CON
XM3CON
XM0PAR
XM1PAR
XM2PAR
XM3PAR
0xF800
0xF804
0xF808
0xF80C
0xF810
0xF818
0xF81C
0xF820
FEESTA
1
2
1
2
2
3
4
4
R
0x20
0x0000
0x07
0xXXXX
0x0000
0xFFFFFF
0x00000000
0xFFFFFFFF
45
45
45
45
45
45
45
45
FEEMOD
FEECON
FEEDAT
FEEADR
FEESIGN
FEEPRO
FEEHIDE
R/W
R/W
R/W
R/W
R
0x00
0x70FF
0x70FF
0x70FF
0x70FF
R/W
R/W
PWM base address = 0xFFFFFC00
0xFC00
0xFC04
0xFC08
0xFC0C
0xFC10
0xFC14
0xFC18
0xFC1C
0xFC20
0xFC24
PWMCON
PWMSTA
PWMDAT0
PWMDAT1
PWMCFG
PWMCH0
PWMCH1
PWMCH2
PWMEN
2
2
2
2
2
2
2
2
2
2
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
59
59
60
60
59
60
60
60
59
60
PWMDAT2
Rev. A | Page 36 of 92
ADuC7019/20/21/22/24/25/26/27
ADC CIRCUIT OVERVIEW
The analog-to-digital converter (ADC) incorporates a fast,
multichannel, 12-bit ADC. It can operate from 2.7 V to 3.6 V
supplies and is capable of providing a throughput of up to 1 MSPS
when the clock source is 41.78 MHz. This block provides the user
with a multichannel multiplexer, differential track-and-hold, on-
chip reference, and ADC.
TRANSFER FUNCTION
Pseudo Differential and Single-Ended Modes
In pseudo differential or single-ended modes, the input range is
0 V to VREF. The output coding is straight binary in pseudo
differential and single-ended modes with
1 LSB = FS/4096, or
The ADC consists of a 12-bit successive approximation
converter based around two capacitor DACs. Depending on the
input signal configuration, the ADC can operate in one of three
different modes:
2.5 V/4096 = 0.61 mV, or
610 μV when VREF = 2.5 V
The ideal code transitions occur midway between successive
integer LSB values (that is, 1/2 LSB, 3/2 LSB, 5/2 LSB, … ,
FS − 3/2 LSB). The ideal input/output transfer characteristic
is shown in Figure 37.
•
•
•
Fully differential mode, for small and balanced signals
Single-ended mode, for any single-ended signals
1111 1111 1111
1111 1111 1110
1111 1111 1101
Pseudo differential mode, for any single-ended signals,
taking advantage of the common-mode rejection offered
by the pseudo differential input
1111 1111 1100
FS
1LSB =
4096
The converter accepts an analog input range of 0 to VREF when
operating in single-ended mode or pseudo differential mode. In
fully differential mode, the input signal must be balanced
0000 0000 0011
0000 0000 0010
0000 0000 0001
0000 0000 0000
around a common-mode voltage VCM, in the range 0 V to AVDD
and with a maximum amplitude of 2 VREF (see Figure 36).
,
AV
DD
0V 1LSB
+FS – 1LSB
VOLTAGE INPUT
V
2V
CM
REF
Figure 37. ADC Transfer Function in Pseudo Differential Mode
or Single-Ended Mode
V
CM
2V
REF
V
Fully Differential Mode
2V
CM
REF
0
The amplitude of the differential signal is the difference
between the signals applied to the VIN+ and VIN– pins (that is,
Figure 36. Examples of Balanced Signals in Fully Differential Mode
V
IN+ – VIN–). The maximum amplitude of the differential signal
A high precision, low drift, and factory calibrated 2.5 V
reference is provided on-chip. An external reference can also be
connected as described later in the Band Gap Reference section.
is therefore –VREF to +VREF p-p (that is, 2 × VREF). This is
regardless of the common mode (CM). The common mode is
the average of the two signals, for example, (VIN+ + VIN–)/2, and
is therefore the voltage that the two inputs are centered on. This
results in the span of each input being CM ± VREF/2. This
voltage has to be set up externally and its range varies with VREF
(see the Driving the Analog Inputs section).
Single or continuous conversion modes can be initiated in the
software. An external
pin, an output generated from
CONVSTART
the on-chip PLA, or a Timer0 or Timer1 overflow can also be
used to generate a repetitive trigger for ADC conversions.
The output coding is twos complement in fully differential
mode with 1 LSB = 2 VREF/4096 or 2 × 2.5 V/4096 = 1.22 mV
when VREF = 2.5 V. The designed code transitions occur midway
between successive integer LSB values (that is, 1/2 LSB, 3/2 LSB,
5/2 LSB, … , FS – 3/2 LSB). The ideal input/output transfer
characteristic is shown in Figure 38.
A voltage output from an on-chip band gap reference
proportional to absolute temperature can also be routed
through the front-end ADC multiplexer, effectively an
additional ADC channel input. This facilitates an internal
temperature sensor channel, which measures die temperature to
an accuracy of ±3°C.
Rev. A | Page 37 of 92
ADuC7019/20/21/22/24/25/26/27
SIGN
BIT
ACQ
BIT TRIAL
WRITE
0
0
0
1111 1111 1110
1111 1111 1100
1111 1111 1010
2 × V
REF
4096
1LSB =
ADC CLOCK
0
0
1
0000 0000 0010
0000 0000 0000
1111 1111 1110
CONV
START
ADC
BUSY
1
1
1
0000 0000 0100
0000 0000 0010
0000 0000 0000
DATA
ADCDAT
–V
+ 1LSB
0LSB
+V
– 1LSB
REF
REF
ADCSTA = 0
ADCSTA = 1
ADC INTERRUPT
VOLTAGE INPUT (V + – V –)
IN IN
Figure 38. ADC Transfer Function in Differential Mode
Figure 40. ADC Timing
TYPICAL OPERATION
ADuC7019
Once configured via the ADC control and channel selection
registers, the ADC converts the analog input and provides a
12-bit result in the ADC data register.
The ADuC7019 is identical to the ADuC7020 except for one
buffered ADC channel, ADC3, and it has only three DACs. The
output buffer of the fourth DAC is internally connected to the
ADC3 channel as shown in Figure 41.
The top 4 bits are the sign bits. The 12-bit result is placed from
Bit 16 to Bit 27 as shown in Figure 39. Again, it should be noted
that in fully differential mode, the result is represented in twos
complement format, and in pseudo differential and single-
ended modes, the result is represented in straight binary format.
ADuC7019
1MSPS
12-BIT ADC
12-BIT
DAC
MUX
ADC3
DAC3
31
27
16 15
0
ADC15
SIGN BITS
12-BIT ADC RESULT
Figure 41. ADC3 Buffered Input
Figure 39. ADC Result Format
Note that the DAC3 output pin must be connected to a 10 nF
capacitor to AGND. This channel should be used to measure dc
voltages only. ADC calibration might be necessary on this
channel.
The same format is used in DAC×DAT, simplifying the software.
Current Consumption
The ADC in standby mode, that is, powered up but not converting,
typically consumes 640 μA. The internal reference adds 140 μA.
During conversion, the extra current is 0.3 μA multiplied by the
sampling frequency (in kHz). Figure 31 shows the current
consumption versus the sampling frequency of the ADC.
MMRS INTERFACE
The ADC is controlled and configured via the eight MMRs
described in this section.
ADCCON Register
Timing
Name
Address
Default Value
Access
Figure 40 gives details of the ADC timing. Users have control on
the ADC clock speed and on the number of acquisition clocks
in the ADCCON MMR. By default, the acquisition time is eight
clocks and the clock divider is two. The number of extra clocks
(such as bit trial or write) is set to 19, which gives a sampling
rate of 774 kSPS. For conversion on temperature sensor, the
ADC acquisition time is automatically set to 16 clocks and the
ADC clock divider is set to 32.
ADCCON
0xFFFF0500
0x0600
R/W
ADCCON is an ADC control register that allows the
programmer to enable the ADC peripheral, select the mode
of operation of the ADC (either in single-ended mode, pseudo
differential mode, or fully differential mode), and select the
conversion type. This MMR is described in Table 14.
Rev. A | Page 38 of 92
ADuC7019/20/21/22/24/25/26/27
Table 14. ADCCON MMR Bit Designations
ADCCP Register
Name
Address
Default Value
Access
Bit
Value Description
ADCCP
0xFFFF0504
0x00
R/W
15:13
12:10
Reserved.
ADC clock speed.
fADC/1. This divider is provided to obtain
1 MSPS ADC with an external clock <41.78 MHz.
fADC/2 (default value).
fADC/4.
fADC/8.
fADC/16.
fADC/32.
ADCCP is an ADC positive channel selection register. This
MMR is described in Table 15.
Table 15. ADCCP1 MMR Bit Designation
Bit
7:5
4:0
000
001
010
011
100
101
Value
Description
Reserved
Positive channel selection bits
ADC0
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
ADC1
ADC2
ADC3
ADC4
ADC5
ADC6
ADC7
ADC8
ADC9
ADC10
ADC11
DAC0/ADC12
DAC1/ADC13
DAC2/ADC14
DAC3/ADC15
9:8
7
ADC acquisition time.
2 clocks.
4 clocks.
8 clocks (default value).
16 clocks.
Enable start conversion.
Set by the user to start any type of conversion
command. Cleared by the user to disable a
start conversion (clearing this bit does not
stop the ADC when continuously converting).
Enable ADCBUSY.
Set by the user to enable the ADCBUSY pin.
Cleared by the user to disable the ADCBUSY pin.
ADC power control.
Set by the user to place the ADC in normal
mode (the ADC must be powered up for at least
5 μs before it converts correctly). Cleared by the
user to place the ADC in power-down mode.
Conversion mode.
Single-ended mode.
Differential mode.
Pseudo differential mode.
Reserved.
00
01
10
11
6
5
Temperature sensor
AGND (self-diagnostic feature)
Internal reference (self-diagnostic feature)
AVDD/2
4:3
2:0
00
01
10
11
Others Reserved
1 ADC and DAC channel availability depends on part model. See the Ordering
Guide for details.
Conversion type.
000
001
010
011
Enable CONVSTART pin as a conversion input.
Enable Timer1 as a conversion input.
Enable Timer0 as a conversion input.
Single software conversion; sets to 000 after
conversion (Bit 7 of ADCCON MMR should be
cleared after starting a single software
conversion to avoid further conversions
triggered by the CONVSTART pin).
100
101
Continuous software conversion.
PLA conversion.
Other Reserved.
Rev. A | Page 39 of 92
ADuC7019/20/21/22/24/25/26/27
ADCRST resets the digital interface of the ADC. Writing any
value to this register resets all the ADC registers to their default
value.
ADCCN Register
Name
Address
Default Value
Access
ADCCN
0xFFFF0508
0x01
R/W
ADCCN is an ADC negative channel selection register. This
MMR is described in Table 16.
ADCGN Register
Name
Address
Default Value
Access
ADCGN
0xFFFF0530
0x0200
R/W
Table 16. ADCCN MMR Bit Designation
Bit
7:5
4:0
Value
Description
ADCGN is a 10-bit gain calibration register.
Reserved
Negative channel selection bits
ADC0
ADC1
ADC2
ADC3
ADC4
ADC5
ADC6
ADC7
ADC8
ADC9
ADC10
ADC11
DAC0/ADC12
DAC1/ADC13
ADCOF Register
Name
Address
Default Value
Access
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
ADCOF
0xFFFF0534
0x0200
R/W
ADCOF is a 10-bit offset calibration register.
CONVERTER OPERATION
The ADC incorporates a successive approximation (SAR)
architecture involving a charge-sampled input stage. This
architecture can operate in three different modes: differential,
pseudo differential, and single-ended.
Differential Mode
The ADuC7019/7020/7021/7022/7024/7025/7026/7027 each
contain a successive approximation ADC based on two
capacitive DACs. Figure 42 and Figure 43 show simplified
schematics of the ADC in acquisition and conversion phase,
respectively. The ADC is comprised of control logic, a SAR, and
two capacitive DACs. In Figure 42 (the acquisition phase), SW3
is closed and SW1 and SW2 are in Position A. The comparator
is held in a balanced condition, and the sampling capacitor
arrays acquire the differential signal on the input.
DAC2/ADC14
DAC3/ADC15
Internal reference (self-diagnostic feature)
Others Reserved
ADCSTA Register
Name
Address
Default Value
Access
CAPACITIVE
DAC
ADCSTA
0xFFFF050C
0x00
R
COMPARATOR
C
C
B
A
S
S
CHANNEL+
CHANNEL–
ADCSTA is an ADC status register that indicates when an ADC
conversion result is ready. The ADCSTA register contains only
one bit, ADCReady (Bit 0), representing the status of the ADC.
This bit is set at the end of an ADC conversion, generating an
ADC interrupt. It is cleared automatically by reading the
ADCDAT MMR. When the ADC is performing a conversion,
the status of the ADC can be read externally via the ADCBUSY
pin. This pin is high during a conversion. When the conversion
is finished, ADCBUSY goes back low. This information can be
available on P0.5 (see the General-Purpose Input/Output
section) if enabled in the ADCCON register.
AIN0
SW1
SW2
CONTROL
LOGIC
MUX
SW3
A
B
AIN11
V
REF
CAPACITIVE
DAC
Figure 42. ADC Acquisition Phase
When the ADC starts a conversion, as shown in Figure 43, SW3
opens, and then SW1 and SW2 move to Position B. This causes
the comparator to become unbalanced. Both inputs are discon-
nected once the conversion begins. The control logic and the
charge redistribution DACs are used to add and subtract fixed
amounts of charge from the sampling capacitor arrays to bring
the comparator back into a balanced condition. When the
comparator is rebalanced, the conversion is complete. The
control logic generates the ADC’s output code. The output
impedances of the sources driving the VIN+ and VIN– pins must
be matched; otherwise, the two inputs have different settling
times, resulting in errors.
ADCDAT Register
Name
ADCDAT
Address
Default Value
Access
0xFFFF0510
0x00000000
R
ADCDAT is an ADC data result register. Hold the 12-bit ADC
result as shown in Figure 39.
ADCRST Register
Name
Address
Default Value
Access
ADCRST
0xFFFF0514
0x00
R/W
Rev. A | Page 40 of 92
ADuC7019/20/21/22/24/25/26/27
The capacitors, C1, in Figure 46 are typically 4 pF and can be
primarily attributed to pin capacitance. The resistors are
lumped components made up of the ON resistance of the
switches. The value of these resistors is typically about 100 Ω.
The capacitors, C2, are the ADC’s sampling capacitors and
typically have a capacitance of 16 pF.
CAPACITIVE
DAC
COMPARATOR
C
C
B
A
S
S
CHANNEL+
CHANNEL–
AIN0
SW1
SW2
CONTROL
LOGIC
MUX
SW3
A
B
AIN11
AV
DD
V
REF
CAPACITIVE
DAC
D
C2
R1
Figure 43. ADC Conversion Phase
C1
D
Pseudo Differential Mode
In pseudo differential mode, Channel− is linked to the VIN− pin
of the ADuC7019/7020/7021/7022/7024/7025/7026/7027. SW2
switches between A (Channel−) and B (VREF). VIN− pin must be
connected to ground or a low voltage. The input signal on VIN+
can then vary from VIN− to VREF + VIN−. Note that VIN− must be
AV
DD
D
D
C2
R1
C1
chosen so that VREF + VIN− do not exceed AVDD
.
CAPACITIVE
DAC
Figure 46. Equivalent Analog Input Circuit Conversion Phase:
Switches Open; Track Phase: Switches Closed
COMPARATOR
C
C
B
A
S
S
CHANNEL+
AIN0
For ac applications, removing high frequency components
from the analog input signal is recommended by using an RC
low-pass filter on the relevant analog input pins. In applications
where harmonic distortion and signal-to-noise ratio are critical,
the analog input should be driven from a low impedance
source. Large source impedances significantly affect the ac
performance of the ADC. This can necessitate the use of an
input buffer amplifier. The choice of the op amp is a function of
the particular application. Figure 47 and Figure 48 give an
example of ADC front end.
SW1
SW2
CONTROL
LOGIC
MUX
SW3
A
B
AIN11
VIN–
V
REF
CAPACITIVE
DAC
CHANNEL–
Figure 44. ADC in Pseudo Differential Mode
Single-Ended Mode
In single-ended mode, SW2 is always connected internally to
ground. The VIN− pin can be floating. The input signal range on
VIN+ is 0 V to VREF.
ADuC702x
CAPACITIVE
DAC
10Ω
ADC0
0.01μF
COMPARATOR
C
C
B
A
S
S
CHANNEL+
AIN0
SW1
CONTROL
LOGIC
Figure 47. Buffering Single-Ended/Pseudo Differential Input
MUX
SW3
CHANNEL–
AIN11
ADuC702x
ADC0
CAPACITIVE
DAC
V
REF
ADC1
Figure 45. ADC in Single-Ended Mode
Analog Input Structure
Figure 48. Buffering Differential Inputs
Figure 46 shows the equivalent circuit of the analog input structure
of the ADC. The four diodes provide ESD protection for the analog
inputs. Care must be taken to ensure that the analog input
signals never exceed the supply rails by more than 300 mV; this
would cause these diodes to become forward biased and start
conducting into the substrate. These diodes can conduct up to
10 mA without causing irreversible damage to the part.
When no amplifier is used to drive the analog input, the source
impedance should be limited to values lower than 1 kΩ. The
maximum source impedance depends on the amount of total
harmonic distortion (THD) that can be tolerated. The THD
increases as the source impedance increases and the
performance degrades.
Rev. A | Page 41 of 92
ADuC7019/20/21/22/24/25/26/27
DRIVING THE ANALOG INPUTS
TEMPERATURE SENSOR
Internal or external reference can be used for the ADC. In
differential mode of operation, there are restrictions on
common-mode input signal (VCM), which is dependent on the
reference value and supply voltage used to ensure that the signal
remains within the supply rails. Table 17 gives some calculated
The ADuC7019/7020/7021/7022/7024/7025/7026/7027 provide
voltage output from on-chip band gap references proportional
to absolute temperature. This voltage output can also be routed
through the front-end ADC multiplexer (effectively an
additional ADC channel input) facilitating an internal
temperature sensor channel, measuring die temperature to an
accuracy of ±3°C.
VCM min and VCM max for some conditions.
Table 17. VCM Ranges
AVDD VREF
VCM Min VCM Max Signal Peak-to-Peak
BAND GAP REFERENCE
3.3 V 2.5 V
1.25 V
2.05 V
2.276 V
2.55 V
1.75 V
1.976 V
2.25 V
2.5 V
Each ADuC7019/7020/7021/7022/7024/7025/7026/7027
provides an on-chip band gap reference of 2.5 V, which can be
used for the ADC and DAC. This internal reference also
appears on the VREF pin. When using the internal reference, a
0.47 μF capacitor must be connected from the external VREF pin
to AGND to ensure stability and fast response during ADC
conversions. This reference can also be connected to an external
pin (VREF) and used as a reference for other circuits in the
system. An external buffer is required because of the low drive
capability of the VREF output. A programmable option also
allows an external reference input on the VREF pin.
2.048 V 1.024 V
1.25 V
2.048 V
1.25 V
2.5 V
2.048 V
1.25 V
0.75 V
1.25 V
3.0 V 2.5 V
2.048 V 1.024 V
1.25 V
0.75 V
CALIBRATION
By default, the factory set values written to the ADC offset
(ADCOF) and gain coefficient registers (ADCGN) yield
optimum performance in terms of end-point errors and
linearity for standalone operation of the part. (See the
Specifications section.) If system calibration is required, it is
possible to modify the default offset and gain coefficients to
improve end-point errors, but note that any modification to the
factory set ADCOF and ADCGN values can degrade ADC
linearity performance.
REFCON Register
Name
Address
Default Value
Access
REFCON
0xFFFF048C
0x00
R/W
The band gap reference interface consists of an 8-bit MMR
REFCON described in Table 18.
For system offset error correction, the ADC channel input stage
must be tied to AGND. A continuous software ADC conversion
loop must be implemented by modifying the value in ADCOF
until the ADC result (ADCDAT) reads code 0 to 1. Offset error
correction is done digitally and has a resolution of 0.25 LSB and
Table 18. REFCON MMR Bit Designations
Bit
7:2
1
Description
Reserved.
Internal Reference Power-Down Enable. Set by user to
place the internal reference in power-down mode and
use as an external reference. Cleared by user to place
the internal reference in normal mode and use it for
ADC conversions.
a range of 3.125ꢀ of VREF
.
For system gain error correction, the ADC channel input stage
must be tied to VREF. A continuous software ADC conversion
loop must be implemented to modify the value in ADCOF until
the ADC result (ADCDAT) reads code 4094 to 4095. Similar to
the offset calibration, the gain calibration resolution is 0.25 LSB
0
Internal Reference Output Enable. Set by user to
connect the internal 2.5 V reference to the VREF pin. The
reference can be used for external component but
needs to be buffered. Cleared by user to disconnect
the reference from the VREF pin.
with a range of 3ꢀ of VREF
.
Rev. A | Page 42 of 92
ADuC7019/20/21/22/24/25/26/27
NONVOLATILE FLASH/EE MEMORY
The ADuC7019/7020/7021/7022/7024/7025/7026/7027
incorporate Flash/EE memory technology on-chip to provide
the user with nonvolatile, in-circuit reprogrammable memory
space.
Retention quantifies the ability of the Flash/EE memory to
retain its programmed data over time. Again, the parts is
qualified in accordance with the formal JEDEC Retention
Lifetime Specification (A117) at a specific junction temperature
(T
= 85°C). As part of this qualification procedure, the
J
Like EEPROM, flash memory can be programmed in-system at
a byte level, although it must first be erased. The erase is
performed in page blocks. As a result, flash memory is often
and more correctly referred to as Flash/EE memory.
Flash/EE memory is cycled to its specified endurance limit,
described previously, before data retention is characterized.
This means that the Flash/EE memory is guaranteed to retain
its data for its fully specified retention lifetime every time the
Flash/EE memory is reprogrammed. Also note that retention
lifetime, based on an activation energy of 0.6 eV, derates with T
as shown in Figure 49.
Overall, Flash/EE memory represents a step closer to the ideal
memory device that includes nonvolatility, in-circuit
programmability, high density, and low cost. Incorporated in
the ADuC7019/7020/7021/7022/7024/7025/7026/7027,
Flash/EE memory technology allows the user to update
program code space in-circuit, without the need to replace one
time programmable (OTP) devices at remote operating nodes.
J
600
450
300
150
0
Each ADuC7019/7020/7021/7022/7024/7025/7026/7027
contains a 64 kB array of Flash/EE memory. The lower 62 kB is
available to the user and the upper 2 kB contain permanently
embedded firmware, allowing in-circuit serial download. These
2 kB of embedded firmware also contain a power-on
configuration routine that downloads factory calibrated
coefficients to the various calibrated peripherals (such as ADC,
temperature sensor, and band gap references). This 2 kB
embedded firmware is hidden from user code.
30
40
55
70
85
100
125
135
150
JUNCTION TEMPERATURE (°C)
Figure 49. Flash/EE Memory Data Retention
Flash/EE Memory Reliability
The Flash/EE memory arrays on the parts is fully qualified for
two key Flash/EE memory characteristics: Flash/EE memory
cycling endurance and Flash/EE memory data retention.
PROGRAMMING
The 62 kB of Flash/EE memory can be programmed in-circuit,
using the serial download mode or the JTAG mode provided.
Endurance quantifies the ability of the Flash/EE memory to be
cycled through many program, read, and erase cycles. A single
endurance cycle is composed of four independent, sequential
events, defined as:
Serial Downloading (In-Circuit Programming)
The ADuC7019/7020/7021/7022/7024/7025/7026/7027
facilitate code download via the standard UART serial port or
via the I2C port. The parts enter serial download mode after a
reset or power cycle if the BM pin is pulled low through an
external 1 kΩ resistor. Once in serial download mode, the user
can download code to the full 62 kB of Flash/EE memory while
the device is in-circuit in its target application hardware. An
executable PC serial download is provided as part of the
development system for serial downloading via the UART. An
1. Initial page erase sequence.
2. Read/verify sequence a single Flash/EE.
3. Byte program sequence memory.
4. Second read/verify sequence endurance cycle.
application note is available at www.analog.com/microconverter
describing the protocol for serial downloading via the UART
and I2C.
In reliability qualification, every half word (16-bit wide)
location of the three pages (top, middle, and bottom) in the
Flash/EE memory is cycled 10,000 times from 0x0000 to
0xFFFF. As indicated in Table 1, the parts’ Flash/EE memory
endurance qualification is carried out in accordance with
JEDEC Retention Lifetime Specification A117 over the
industrial temperature range of --40°C to +25°C and +25°C to
+125°C. The results allow the specification of a minimum
endurance figure over supply temperature of 10,000 cycles.
JTAG Access
The JTAG protocol uses the on-chip JTAG interface to facilitate
code download and debug. An application note is available at
www.analog.com/microconverter describing the protocol via
JTAG.
Rev. A | Page 43 of 92
ADuC7019/20/21/22/24/25/26/27
It is possible to write to a single Flash/EE location address
twice. If a single address is written to more than twice, then the
data within the Flash/EE memory can be corrupted. That is, it is
possible to walk zeros only byte wise.
FLASH/EE CONTROL INTERFACE
Serial, parallel, and JTAG programming use the Flash/EE control
interface, which includes eight MMRs outlined in this section.
FEESTA Register
SECURITY
Name
Address
Default Value
Access
The 62 kB of Flash/EE memory available to the user can be read
and write protected.
FEESTA
0xFFFFF800
0x20
R
FEESTA is a read-only register that reflects the status of the
flash control interface as described in Table 19.
Bit 31 of the FEEPRO/FEEHIDE MMR (see Table 22) protects
the 62 kB from being read through JTAG and also in parallel
programming mode. The other 31 bits of this register protect
writing to the flash memory. Each bit protects four pages, that
is, 2 kB. Write protection is activated for all types of access.
Table 19. FEESTA MMR Bit Designations
Bit
15:6
5
Description
Reserved.
Burst Command Enable. Set when the command is a
burst command: 0x07, 0x08, or 0x09. Cleared when
another command.
Three Levels of Protection
•
Protection can be set and removed by writing directly into
FEEHIDE MMR. This protection does not remain after reset.
Protection can be set by writing into FEEPRO MMR. It
only takes effect after a save protection command (0×0C)
and a reset. The FEEPRO MMR is protected by a key to
avoid direct access. The key is saved once and must be
entered again to modify FEEPRO. A mass erase sets the
key back to 0×FFFF but also erases all the user code.
Flash can be permanently protected by using the FEEPRO
MMR and a particular value of key: 0×DEADDEAD.
Entering the key again to modify the FEEPRO register is
not allowed.
4
3
Reserved.
Flash Interrupt Status Bit. Set automatically when an
interrupt occurs, that is, when a command is complete
and the Flash/EE interrupt enable bit in the FEEMOD
register is set. Cleared when reading FEESTA register.
Flash/EE Controller Busy. Set automatically when the
controller is busy. Cleared automatically when the
controller is not busy.
Command Fail. Set automatically when a command
completes unsuccessfully. Cleared automatically when
reading FEESTA register.
Command Pass. Set by MicroConverter when a
command completes successfully. Cleared
automatically when reading FEESTA register.
•
2
1
0
•
Sequence to Write the Key
1. Write the bit in FEEPRO corresponding to the page to be
protected.
2. Enable key protection by setting Bit 6 of FEEMOD (Bit 5
must equal 0).
FEEMOD Register
Name
Address
Default Value
Access
FEEMOD
0xFFFFF804
0x0000
R/W
FEEMOD sets the operating mode of the flash control interface.
Table 20 shows FEEMOD MMR bit designations.
3. Write a 32-bit key in FEEADR, FEEDAT.
4. Run the write key command 0×0C in FEECON; wait for
the read to be successful by monitoring FEESTA.
Table 20. FEEMOD MMR Bit Designations
Bit
15:9
8
Description
5. Reset the part.
Reserved.
To remove or modify the protection, the same sequence is used
with a modified value of FEEPRO. If the key chosen is the value
0×DEAD, then the memory protection cannot be removed. Only a
mass erase unprotects the part, but it also erases all user code.
Reserved. This bit should always be set to 0.
7:5
Reserved. These bits should always be set to 0 except
when writing keys. See the Sequence to Write the Key
section.
4
Flash/EE Interrupt Enable. Set by user to enable the
Flash/EE interrupt. The interrupt occurs when a
command is complete. Cleared by user to disable
the Flash/EE interrupt.
Erase/Write Command Protection. Set by user to
enable the erase and write commands. Cleared to
protect the Flash against erase/write command.
The sequence to write the key is illustrated in the following
example (this protects writing Pages 4 to 7 of the Flash):
FEEPRO=0xFFFFFFFD;
FEEMOD=0x48;
//Protect pages 4 to 7
//Write key enable
//16 bit key value
//16 bit key value
// Write key command
3
FEEADR=0x1234;
FEEDAT=0x5678;
FEECON= 0x0C;
2:0
Reserved. These bits should always be set to 0.
The same sequence should be followed to protect the part
permanently with FEEADR = 0×DEAD and FEEDAT =
0×DEAD.
FEECON Register
Name
Address
Default Value
Access
FEECON
0xFFFFF808
0x07
R/W
Rev. A | Page 44 of 92
ADuC7019/20/21/22/24/25/26/27
FEECON is an 8-bit command register. The commands are
described in Table 21.
FEEDAT Register
Name
Address
Default Value
Access
FEEDAT
0xFFFFF80C
0xXXXX
R/W
Table 21. Command Codes in FEECON
Code Command
0x001 Null
0x011 Single Read
Description
FEEDAT is a 16-bit data register.
Idle State.
Load FEEDAT with the 16-bit data.
Indexed by FEEADR.
FEEADR Register
Name
Address
Default Value
Access
0x021 Single Write
0x031 Erase/Write
Write FEEDAT at the address pointed by
FEEADR. This operation takes 20 μs.
Erase the page indexed by FEEADR and
write FEEDAT at the location pointed by
FEEADR. This operation takes 20 ms.
FEEADR
0xFFFFF810
0x0000
R/W
FEEADR is another 16-bit address register.
FEESIGN Register
Name
Address
Default Value
Access
0x041 Single Verify Compare the contents of the location
pointed by FEEADR to the data in
FEESIGN
0xFFFFF818
0xFFFFFF
R
FEEDAT. The result of the comparison is
returned in FEESTA Bit 1.
Erase the page indexed by FEEADR.
Erase 62 kB of user space. The 2 kB of
kernel are protected. This operation
takes 2.48 seconds. To prevent accidental
execution, a command sequence is
required to execute this instruction. See
the Command Sequence for Executing a
Mass Erase section.
FEESIGN is a 24-bit code signature.
0x051 Single Erase
0x061 Mass Erase
FEEPRO Register
Name
Address
Default Value
Access
FEEPRO
0xFFFFF81C
0x00000000
R/W
FEEPRO MMR provides immediate protection. It does not
require any software keys, see Table 22.
FEEHIDE Register
Name
Address
Default Value
Access
0x07
0x08
0x09
Burst Read
Default Command. No write is allowed.
This operation takes two cycles.
Write can handle a maximum of 8 data of
FEEHIDE
0xFFFFF820
0xFFFFFFFF
R/W
Burst
Read/Write
FEEHIDE provides protection following subsequent reset of the
MMR. It requires a software key. See description in Table 22.
16 bits and takes a maximum of 8 x 20 μs.
Erase Burst
Read/Write
Automatically erases the page indexed by
the write; writes pages without running
an erase command. This command takes
20 ms to erase the page + 20 μs per data
to write.
Table 22. FEEPRO and FEEHIDE MMR Bit Designations
Bit
Description
31
Read Protection. Cleared by user to protect all code.
Set by user to allow reading the code.
0x0A Reserved
0x0B Signature
Reserved.
30:0
Write Protection for Pages 123 to 120, Pages 119 to 116,
and Pages 0 to 3. Cleared by user to protect the pages in
writing. Set by user to allow writing the pages.
Give a signature of the 64 kB of Flash/EE
in the 24-bit FEESIGN MMR. This
operation takes 32,778 clock cycles.
Command Sequence for Executing a Mass Erase
0x0C Protect
This command can run only once. The
value of FEEPRO is saved and removed
only with a mass erase (0x06) or the key.
Reserved.
Reserved.
FEEDAT=0x3CFF;
FEEADR = 0xFFC3;
FEEMOD= FEEMOD|0x8; //Erase key enable
0x0D Reserved
FEECON=0x06;
//Mass erase command
0x0E
0x0F
Reserved
Ping
No operation; interrupt generated.
1 The FEECON register always reads 0x07 immediately after execution of any
of these commands.
Rev. A | Page 45 of 92
ADuC7019/20/21/22/24/25/26/27
EXECUTION TIME FROM SRAM AND FLASH/EE
RESET AND REMAP
Execution from SRAM
The ARM exception vectors are all situated at the bottom of the
memory array, from address 0x00000000 to address
0x00000020 as shown in Figure 50.
Fetching instructions from SRAM takes one clock cycle as the
access time of the SRAM is 2 ns and a clock cycle is 22 ns
minimum. However, if the instruction involves reading or
writing data to memory, one extra cycle must be added if the
data is in SRAM (or three cycles if the data is in Flash/EE). One
cycle to execute the instruction, and two cycles to get the 32-bit
data from Flash/EE. A control flow instruction (a branch
instruction, for example) takes one cycle to fetch but also takes
two cycles to fill the pipeline with the new instructions.
0xFFFFFFFF
KERNEL
0x0008FFFF
0x00011FFF
FLASH/EE
INTERRUPT
SERVICE ROUTINES
0x00080000
0x00010000
Execution from Flash/EE
Because the Flash/EE width is 16 bits and access time for 16-bit
words is 22 ns, execution from Flash/EE cannot be done in
one cycle (as can be done from SRAM when CD Bit = 0). Also,
some dead times are needed before accessing data for any value
of CD bits.
SRAM
INTERRUPT
SERVICE ROUTINES
MIRROR SPACE
0x00000020
ARM EXCEPTION
In ARM mode, where instructions are 32 bits, two cycles are
needed to fetch any instruction when CD = 0. In thumb mode,
where instructions are 16 bits, one cycle is needed to fetch any
instruction.
VECTOR ADDRESSES 0x00000000 0x00000000
Figure 50. Remap for Exception Execution
By default, and after any reset, the Flash/EE is mirrored at the
bottom of the memory array. The remap function allows the
programmer to mirror the SRAM at the bottom of the memory
array, which facilitates execution of exception routines from SRAM
instead of from Flash/EE. This means exceptions are executed twice
as fast, being executed in 32-bit ARM mode, and the SRAM being
32-bit wide instead of 16-bit wide Flash/EE memory.
Timing is identical in both modes when executing instructions
that involve using the Flash/EE for data memory. If the
instruction to be executed is a control flow instruction, an extra
cycle is needed to decode the new address of the program
counter and then four cycles are needed to fill the pipeline. A
data-processing instruction involving only the core register
does not require any extra clock cycle. However, if it involves
data in Flash/EE, an extra clock cycle is needed to decode the
address of the data, and two cycles are needed to get the 32-bit
data from Flash/EE. An extra cycle must also be added before
fetching another instruction. Data transfer instructions are
more complex and are summarized in Table 23.
Remap Operation
When a reset occurs on the ADuC7019/7020/7021/7022/
7024/7025/7026/7027, execution starts automatically in factory
programmed internal configuration code. This kernel is hidden
and cannot be accessed by user code. If the ADuC7019/7020/
7021/7022/7024/7025/7026/7027 are in normal mode (BM pin
is high), then they execute the power-on configuration routine
of the kernel and then jump to the reset vector address,
0x00000000, to execute the user’s reset exception routine.
Table 23. Execution Cycles in ARM/Thumb Mode
Fetch
Instructions Cycles
Dead
Time
Dead
Time
Data Access
LD1
LDH
LDM/PUSH
STR1
2/1
2/1
2/1
2/1
2/1
2/1
1
1
N2
1
2
1
1
1
N1
1
Because the Flash/EE is mirrored at the bottom of the memory
array at reset, the reset interrupt routine must always be written
in Flash/EE.
2 x N2
2 x 20 μs
20 μs
2 x N x 20 μs1
STRH
1
N1
1
N1
The remap is done from Flash/EE by setting Bit 0 of the
REMAP register. Precaution must be taken to execute this
command from Flash/EE, above address 0x00080020, and not
from the bottom of the array as this is replaced by the SRAM.
STRM/POP
1 The SWAP instruction combines an LD and STR instruction with only one
fetch, giving a total of eight cycles plus 40 μs.
2 N is the number of data to load or store in the multiple load/store instruction
(1 <N ≤ 16).
This operation is reversible. The Flash/EE can be remapped at
address 0x00000000 by clearing Bit 0 of the REMAP MMR.
Precaution must again be taken to execute the remap function
from outside the mirrored area. Any type of reset remaps the
Flash/EE memory at the bottom of the array.
Rev. A | Page 46 of 92
ADuC7019/20/21/22/24/25/26/27
Reset Operation
RSTSTA Register
Name
Address
Default Value
Access
There are four kinds of reset: external, power-on, watchdog
expiation, and software force. The RSTSTA register indicates
the source of the last reset, and RSTCLR allows clearing the
RSTSTA register. These registers can be used during a reset
exception service routine to identify the source of the reset.
If RSTSTA is null, the reset is external.
RSTSTA
0xFFFF0230
0x01
R/W
Table 25. RSTSTA MMR Bit Designations
Bit
7:3
2
Description
Reserved.
Software Reset. Set by user to force a software reset.
Cleared by setting the corresponding bit in RSTCLR.
Watchdog Timeout. Set automatically when a
watchdog timeout occurs. Cleared by setting the
corresponding bit in RSTCLR.
Power-On Reset. Set automatically when a power-on
reset occurs. Cleared by setting the corresponding bit in
RSTCLR.
REMAP Register
Name
Address
Default Value
0xXX1
Access
1
0
REMAP
0xFFFF0220
R/W
1 Depends on model.
Table 24. REMAP MMR Bit Designations
Bit
Name
Description
4
Read-Only Bit. Indicates the size of the
Flash/EE memory available. If this bit is set,
only 32 kB of Flash/EE memory is available.
RSTCLR Register
Name
Address
Default Value
Access
3
Read-Only Bit. Indicates the size of the SRAM
memory available. If this bit is set, only 4 kB of
SRAM is available.
RSTCLR
0xFFFF0234
0x00
R/W
2:1
0
Reserved.
Remap Remap Bit. Set by user to remap the SRAM to
address 0x00000000. Cleared automatically
after reset to remap the Flash/EE memory to
address 0x00000000.
Rev. A | Page 47 of 92
ADuC7019/20/21/22/24/25/26/27
OTHER ANALOG PERIPHERALS
DACxDAT Registers
DAC
Name
Address
Default Value
0x00000000
0x00000000
0x00000000
0x00000000
Access
R/W
R/W
R/W
R/W
The ADuC7019/7020/7021/7022/7024/7025/7026/7027
incorporate two, three, or four 12-bit voltage output DACs on-
chip depending on the model. Each DAC has a rail-to-rail voltage
output buffer capable of driving 5 kΩ/100 pF.
DAC0DAT
DAC1DAT
DAC2DAT
DAC3DAT
0xFFFF0604
0xFFFF060C
0xFFFF0614
0xFFFF061C
Each DAC has three selectable ranges: 0 V to VREF (internal
band gap 2.5 V reference), 0 V to DACREF, and 0 V to AVDD
DACREF is equivalent to an external reference for the DAC.
.
Table 27. DAC0DAT MMR Bit Designations
Bit
Description
The signal range is 0 V to AVDD
.
31:28
27:16
15:0
Reserved
12-bit data for DAC0
Reserved
MMRs Interface
Each DAC is configurable independently through a control
register and a data register. These two registers are identical for
the four DACs. Only DAC0CON (see Table 26) and DAC0DAT
(see Table 27) are described in detail in this section.
Using the DACs
The on-chip DAC architecture consists of a resistor string DAC
followed by an output buffer amplifier, the functional
equivalent of which is shown in Figure 51.
DACxCON Registers
Name
Address
Default Value
0x00
0x00
0x00
0x00
Access
R/W
R/W
R/W
R/W
DAC0CON
DAC1CON
DAC2CON
DAC3CON
0xFFFF0600
0xFFFF0608
0xFFFF0610
0xFFFF0618
AV
OUTPUT
BUFFER
BYPASSED
FROM MCU
DD
REF
REF
V
DAC
R
R
R
DAC0
Table 26. DAC0CON MMR Bit Designations
Bit
Value Name
Description
6
Reserved.
5
DACCLK DAC Update Rate. Set by user to
update the DAC using Timer1.
Cleared by user to update the DAC
using HCLK (core clock).
R
R
4
DACCLR DAC Clear Bit. Set by user to enable
normal DAC operation. Cleared by
user to reset data register of the DAC
to zero.
Figure 51. DAC Structure
As illustrated in Figure 51, the reference source for each DAC is
user selectable in software. It can be either AVDD, VREF, or DACREF
In 0-to-AVDD mode, the DAC output transfer function spans
from 0 V to the voltage at the AVDD pin. In 0-to-DACREF mode,
the DAC output transfer function spans from 0 V to the voltage at
the DACREF pin. In 0-to-VREF mode, the DAC output transfer
3
2
1:0
Reserved. This bit should be left at 0.
Reserved. This bit should be left at 0.
DAC Range Bits.
Power-Down Mode. The DAC output
is in tri-state.
0 − DACREF Range.
0 − VREF (2.5 V) Range.
0 − AVDD Range.
.
00
01
10
11
function spans from 0 V to the internal 2.5 V reference, VREF
.
The DAC output buffer amplifier features a true rail-to-rail
output stage implementation. This means that, unloaded, each
output is capable of swinging to within less than 5 mV of both
AVDD and ground. Moreover, the DAC’s linearity specification
(when driving a 5 kꢁ resistive load to ground) is guaranteed
through the full transfer function except codes 0 to 100, and, in
0-to-AVDD mode only, codes 3995 to 4095.
Rev. A | Page 48 of 92
ADuC7019/20/21/22/24/25/26/27
Linearity degradation near ground and VDD is caused by
POWER SUPPLY MONITOR
saturation of the output amplifier, and a general representation
of its effects (neglecting offset and gain error) is illustrated in
Figure 52. The dotted line in Figure 52 indicates the ideal transfer
function, and the solid line represents what the transfer function
might look like with endpoint nonlinearities due to saturation of
the output amplifier. Note that Figure 52 represents a transfer
function in 0-to-AVDD mode only. In 0-to-VREF or 0-to-DACREF
modes (with VREF < AVDD or DACREF < AVDD), the lower non-
linearity is similar. However, the upper portion of the transfer
function follows the “ideal” line right to the end (VREF in this case,
not AVDD), showing no signs of endpoint linearity errors.
The power supply monitor regulates the IOVDD supply on the
ADuC7019/7020/7021/7022/7024/7025/7026/7027. It indicates
when the IOVDD supply pin drops below one of two supply trip
points. The monitor function is controlled via the PSMCON
register. If enabled in the IRQEN or FIQEN register, then the
monitor interrupts the core using the PSMI bit in the PSMCON
MMR. This bit is immediately cleared once CMP goes high.
This monitor function allows the user to save working registers
to avoid possible data loss due to the low supply or brown-out
conditions. It also ensures that normal code execution does not
resume until a safe supply level has been established.
AV
DD
PSMCON Register
AV – 100mV
DD
Name
Address
Default Value
Access
PSMCON
0xFFFF0440
0x0008
R/W
Table 28. PSMCON MMR Bit Descriptions
Bit Name Description
3
CMP
Comparator Bit. This is a read-only bit and
directly reflects the state of the comparator.
Read 1 indicates that the IOVDD supply is above
its selected trip point or the PSM is in power-
down mode. Read 0 indicates the IOVDD supply is
below its selected trip point. This bit should be
set before leaving the interrupt service routine.
100mV
0x00000000
0x0FFF0000
Figure 52. Endpoint Nonlinearities Due to Amplifier Saturation
2
1
TP
Trip Point Selection Bits. 0 = 2.79 V, 1 = 3.07 V.
PSMEN Power Supply Monitor Enable Bit. Set to 1 to
enable the power supply monitor circuit. Clear to
0 to disable the power supply monitor circuit.
The endpoint nonlinearities conceptually illustrated in
Figure 52 get worse as a function of output loading. Most of
the ADuC7019/7020/7021/7022/7024/7025/7026/7027’s data
sheet specifications assume a 5 kΩ resistive load to ground at
the DAC output. As the output is forced to source or sink more
current, the nonlinear regions at the top or bottom
0
PSMI
Power Supply Monitor Interrupt Bit. This bit is set
high by the MicroConverter once when CMP
goes low, indicating low I/O supply. The PSMI bit
can be used to interrupt the processor. Once
CMP returns high, the PSMI bit can be cleared by
writing a 1 to this location. A 0 write has no
effect. There is no timeout delay; PSMI can be
immediately cleared once CMP goes high.
(respectively) of Figure 52 become larger. With larger current
demands, this can significantly limit output voltage swing.
Rev. A | Page 49 of 92
ADuC7019/20/21/22/24/25/26/27
Table 29. CMPCON MMR Bit Descriptions
COMPARATOR
Bit
Value Name
Description
The ADuC7019/7020/7021/7022/7024/7025/7026/7027
integrate voltage comparators. The positive input is multiplexed
with ADC2 and the negative input has two options: ADC3 or
DAC0. The output of the comparator can be configured to
generate a system interrupt, can be routed directly to the
programmable logic array, can start an ADC conversion, or can
be on an external pin, CMPOUT, as shown in Figure 53.
15:11
10
Reserved.
CMPEN
Comparator Enable Bit. Set by user
to enable the comparator. Cleared
by user to disable the comparator.
Comparator Negative Input Select
Bits.
9:8
7:6
5
CMPIN
00
01
10
11
AVDD/2.
ADC3 input.
DAC0 output.
Reserved.
Comparator Output Configuration
Bits.
Reserved.
Reserved.
Output on CMPOUT
IRQ.
Comparator Output Logic State Bit.
When low, the comparator output is
high if the positive input (CMP0) is
above the negative input (CMP1).
When high, the comparator output
is high if the positive input is below
the negative input.
IRQ
ADC2/CMP0
MUX
CMPOC
ADC3/CMP1
MUX
DAC0
00
01
10
11
P0.0/CMP
OUT
.
Figure 53. Comparator
CMPOL
Hysteresis
Figure 54 shows how the input offset voltage and hysteresis
terms are defined. Input offset voltage (VOS) is the difference
between the center of the hysteresis range and the ground level.
This can either be positive or negative. The hysteresis voltage
(VH) is ½ the width of the hysteresis range.
4:3
CMPRES
00
Response Time.
5 μs response time typical for large
signals (2.5 V differential).
COMP
OUT
V
V
H
H
17 μs response time typical for small
signals (0.65 mV differential).
11
3 μs typical.
2
1
CMPHYST Comparator Hysteresis Bit. Set by
user to have a hysteresis of about
7.5 mV. Cleared by user to have no
hysteresis.
COMP0
V
OS
Figure 54. Comparator Hysteresis Transfer Function
Comparator Interface
CMPORI
Comparator Output Rising Edge
Interrupt. Set automatically when a
rising edge occurs on the moni-
tored voltage (CMP0). Cleared by
user by writing a 1 to this bit.
The comparator interface consists of a 16-bit MMR, CMPCON,
which is described in Table 29.
CMPCON Register
Name
CMPCON
0
CMPOFI
Comparator Output Falling Edge
Interrupt. Set automatically when a
falling edge occurs on the monitored
voltage (CMP0). Cleared by user.
Address
Default Value
Access
0xFFFF0444
0x0000
R/W
Rev. A | Page 50 of 92
ADuC7019/20/21/22/24/25/26/27
External Crystal Selection
OSCILLATOR AND PLL—POWER CONTROL
Clocking System
To switch to external crystal, clear the OSEL bit in the
PLLCON MMR (see Table 32). In noisy environments, noise
might couple to the external crystal pins and PLL could lose
lock momentarily. A PLL interrupt is provided in the interrupt
controller. The core clock is halted immediately and this
interrupt is only serviced once the lock has been restored.
Each ADuC7019/7020/7021/7022/7024/7025/7026/7027
integrates a 32.768 kHz ±3ꢀ oscillator, a clock divider, and a
PLL. The PLL locks onto a multiple (1275) of the internal
oscillator or an external 32.768 kHz crystal to provide a stable
41.78 MHz clock for the system referred to as UCLK. To allow
power saving, the core can operate at this frequency, or at
binary submultiples of it. The actual core operating frequency,
UCLK/2CD, is refered to as HCLK. The default core clock is the
PLL clock divided by 8 (CD = 3) or 5.22 MHz. The core clock
frequency can also come from an external clock on the ECLK
pin as described in Figure 55. The core clock can be outputted
on the ECLK pin when using an internal oscillator or external
crystal.
In case of crystal loss, the watchdog timer should be used.
During initialization, a test on the RSTSTA can determine
if the reset came from the watchdog timer.
External Clock Selection
To switch to an external clock on P0.7, configure P0.7 in
Mode 1 and MDCLK bits to 11. External clock can be up
to 44 MHz providing the tolerance is 1ꢀ.
Power Control System
XCLKO
XCLKI
WATCHDOG
TIMER
INT. 32kHz*
OSCILLATOR
CRYSTAL
OSCILLATOR
A choice of operating modes is available on the ADuC7019/
7020/7021/7022/7024/7025/7026/7027.
WAKEUP
TIMER
Table 30 describes what part is powered on in the different
modes and indicates the power-up time. Table 31 gives some
typical values of the total current consumption (analog + digital
supply currents) in the different modes depending on the clock
divider bits. The ADC is turned off. Note that these values also
include current consumption of the regulator and other parts
on the test board on which these values are measured.
AT POWER UP
OCLK 32.768kHz
41.78MHz
PLL
P0.7/XCLK
MDCLK
UCLK
ANALOG
PERIPHERALS
2
I C
CD
/2
CD
CORE
HCLK
*32.768kHz ±3%
P0.7/ECLK
Figure 55. Clocking System
The selection of the clock source is in the PLLCON register. By
default, the part uses the internal oscillator feeding the PLL.
Table 30. Operating Modes
Mode
Active
Pause
Nap
Sleep
Stop
Core
Peripherals
PLL
X
X
XTAL/T2/T3
IRQ0 to IRQ3
Start-up/Power-on Time
130 ms at CD = 0
24 ns at CD = 0; 3 ꢀs at CD = 7
24 ns at CD = 0; 3 ꢀs at CD = 7
1.58 ms
X
X
X
X
X
X
X
X
X
X
X
X
X
1.7 ms
Table 31. Typical Current Consumption at 25°C
PC[2-0]
Mode
Active
Pause
Nap
CD = 0
33.1
22.7
3.8
CD = 1
21.2
13.3
3.8
CD = 2
13.8
8.5
CD = 3
10
6.1
CD = 4
8.1
4.9
CD = 5
7.2
4.3
CD = 6
6.7
4
CD = 7
6.45
3.85
3.8
000
001
010
3.8
3.8
3.8
3.8
3.8
011
100
Sleep
Stop
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
Rev. A | Page 51 of 92
ADuC7019/20/21/22/24/25/26/27
Table 33. POWCON MMR Bit Designations
MMRs and Keys
Bit
Value
Name
Description
The operating mode, clocking mode, and programmable clock
divider are controlled via two MMRs, PLLCON (see Table 32)
and POWCON (see Table 33). PLLCON controls the operating
mode of the clock system, while POWCON controls the core
clock frequency and the power-down mode.
7
Reserved.
6:4
PC
Operating Modes.
Active Mode.
Pause Mode.
Nap.
Sleep Mode. IRQ0 to IRQ3 and
Timer2 can wake up the
000
001
010
011
To prevent accidental programming, a certain sequence (see
Table 34) has to be followed to write to the PLLCON and
POWCON registers.
ADuC7019/7020/7021/7022/7024/
7025/7026/7027.
100
Stop Mode. IRQ0 to IRQ3 can wake
up the ADuC7019/7020/7021/
7022/7024/7025/7026/7027.
Reserved.
Reserved.
PLLKEYx Registers
Name
Address
Default Value
0x0000
0x0000
Access
W
W
PLLKEY1
PLLKEY2
0xFFFF0410
0xFFFF0418
Others
3
2:0
CD
CPU Clock Divider Bits.
41.78 MHz.
20.89 MHz.
10.44 MHz.
5.22 MHz.
2.61 MHz.
1.31 MHz.
653 kHz.
326 kHz.
PLLCON Register
000
001
010
011
100
101
110
111
Name
Address
Default Value
Access
PLLCON
0xFFFF0414
0x21
R/W
POWKEYx Registers
Name
Address
Default Value
0x0000
0x0000
Access
W
W
POWKEY1
POWKEY2
0xFFFF0404
0xFFFF040C
Table 34. PLLCON and POWCON Write Sequence
POWCON Register
PLLCON
POWCON
Name
Address
Default Value
Access
PLLKEY1 = 0xAA
PLLCON = 0x01
PLLKEY2 = 0x55
POWKEY1 = 0x01
POWCON = User Value
POWKEY2 = 0xF4
POWCON
0xFFFF0408
0x0003
R/W
Table 32. PLLCON MMR Bit Designations
Bit Value Name
Description
7:6
Reserved.
5
OSEL
32 kHz PLL Input Selection. Set by
user to use the internal 32 kHz
oscillator. Set by default. Cleared by
user to use the external 32 kHz crystal.
4:2
1:0
Reserved.
MDCLK Clocking Modes.
Reserved.
00
01
10
11
PLL. Default configuration.
Reserved.
External Clock on P0.7 Pin.
Rev. A | Page 52 of 92
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DIGITAL PERIPHERALS
THREE-PHASE PWM
In double update mode, it is also possible to produce
asymmetrical PWM patterns that produce lower harmonic
distortion in three-phase PWM inverters. This technique
permits closed-loop controllers to change the average voltage
applied to the machine windings at a faster rate. As a result,
faster closed-loop bandwidths are achieved. The operating
mode of the PWM block is selected by a control bit in the
PWMCON register. In single update mode, a PWMSYNC pulse
is produced at the start of each PWM period. In double update
mode, an additional PWMSYNC pulse is produced at the
midpoint of each PWM period.
Each ADuC7019/7020/7021/7022/7024/7025/7026/7027
provides a flexible and programmable, three-phase pulse-width
modulation (PWM) waveform generator. It can be programmed
to generate the required switching patterns to drive a three-
phase voltage source inverter for ac induction motor control
(ACIM).
Note that only active high patterns can be produced.
The PWM generator produces three pairs of PWM signals on the
six PWM output pins (PWM0H, PWM0L, PWM1H, PWM1L,
PWM2H, and PWM2L). The six PWM output signals consist of
three high-side drive signals and three low-side drive signals.
The PWM block can also provide an internal synchronization
pulse on the PWMSYNC pin that is synchronized to the PWM
switching frequency. In single update mode, a pulse is produced
at the start of each PWM period. In double update mode, an
additional pulse is produced at the mid-point of each PWM
period. The width of the pulse is programmable through the
PWMDAT2 register. The PWM block can also accept an external
synchronization pulse on the PWMSYNC pin. The selection of
external synchronization or internal synchronization is in the
PWMCON register. The SYNC input timing can be synchronized
to the internal peripheral clock, which is selected in the
PWMCON register. If the external synchronization pulse from
the chip pin is asynchronous to the internal peripheral clock
(typical case), the external PWMSYNC is considered
The switching frequency and dead time of the generated PWM
patterns are programmable using the PWMDAT0 and
PWMDAT1 MMRs. In addition, three duty-cycle control
registers (PWMCH0, PWMCH1, and PWMCH2) directly
control the duty cycles of the three pairs of PWM signals.
Each of the six PWM output signals can be enabled or disabled by
separate output enable bits of the PWMEN register. In addition,
three control bits of the PWMEN register permit crossover of
the two signals of a PWM pair. In crossover mode, the PWM
signal destined for the high-side switch is diverted to the comple-
mentary low-side output. The signal destined for the low-side
switch is diverted to the corresponding high-side output signal.
asynchronous and should be synchronized. The synchronization
logic adds latency and jitter from the external pulse to the actual
PWM outputs. The size of the pulse on the PWMSYNC pin must be
greater than two core clock periods.
In many applications, there is a need to provide an isolation
barrier in the gate-drive circuits that turn on the power devices
of the inverter. In general, there are two common isolation
techniques, optical isolation using opto-couplers, and
transformer isolation using pulse transformers. The PWM
controller permits mixing of the output PWM signals with a
high frequency chopping signal to permit easy interface to such
pulse transformers. The features of this gate-drive chopping
mode can be controlled by the PWMCFG register. An 8-bit
value within the PWMCFG register directly controls the
chopping frequency. High frequency chopping can be
independently enabled for the high-side and low-side outputs
using separate control bits in the PWMCFG register.
The PWM signals produced by the ADuC7019/7020/7021/
7022/7024/7025/7026/7027 can be shut off via a dedicated
asynchronous PWM shutdown pin, PWMTRIP. When brought
low, PWMTRIP instantaneously places all six PWM outputs in the
off state (high). This hardware shutdown mechanism is
asynchronous so that the associated PWM disable circuitry does
not go through any clocked logic. This ensures correct PWM
shutdown even in the event of a core clock loss.
Status information about the PWM system is available to the
user in the PWMSTA register. In particular, the state of the
PWMTRIP pin is available, as well as a status bit that indicates
whether operation is in the first half or the second half of the
PWM period.
The PWM generator can operate in one of two distinct modes,
single update mode or double update mode. In single update
mode, the duty cycle values are programmable only once per
PWM period, so that the resulting PWM patterns are
symmetrical about the midpoint of the PWM period. In the
double update mode, a second updating of the PWM duty cycle
values is implemented at the midpoint of the PWM period.
Rev. A | Page 53 of 92
ADuC7019/20/21/22/24/25/26/27
•
The Output Control Unit. This block can redirect the
outputs of the three-phase timing unit for each channel to
either the high-side or low-side output. In addition, the
output control unit allows individual enabling/disabling of
each of the six PWM output signals.
40-Pin Package Devices
On the 40-pin package devices, the PWM outputs are not
directly accessible, as described in the General-Purpose
Input/Output section. One channel can be brought out on a
GPIO via the PLA as shown in this example:
•
•
The Gate Drive Unit. This block can generate the high
frequency chopping frequency and its subsequent mixing
with the PWM signals.
PWMCON = 0x1;
PWMDAT0 = 0x055F;
// enables PWM o/p
// PWM switching freq
// Configure Port Pins
GP4CON = 0x300;
GP3CON = 0x1;
// P4.2 as PLA output
The PWM Shutdown Controller. This block takes care of
the PWM shutdown via the PWMTRIP pin and generates the
correct reset signal for the timing unit.
// P3.0 configured as
// output of PWM0
//(internally)
The PWMSYNC pulse control unit generates the internal
synchronization pulse and also controls whether the external
PWMSYNC pin is used or not.
// PWM0 onto P4.2
PLAELM8 = 0x0035;
// P3.0 (PWM output)
// input of element 8
PLAELM10 = 0x0059; // PWM from element 8
The PWM controller is driven by the ADuC7019/7020/
7021/7022/7024/7025/7026/7027 core clock frequency and is
capable of generating two interrupts to the ARM core. One
interrupt is generated on the occurrence of a PWMSYNC pulse,
and the other is generated on the occurrence of any PWM
shutdown action.
Description of the PWM Block
A functional block diagram of the PWM controller is shown in
Figure 56. The generation of the six output PWM signals on
pins PWM0H to PWM2L is controlled by four important blocks:
•
The Three-Phase PWM Timing Unit. The core of the PWM
controller, it generates three pairs of complemented and dead-
time-adjusted, center-based PWM signals.
CONFIGURATION
REGISTERS
DUTY CYCLE
REGISTERS
PWMCON
PWMDAT0
PWMDAT1
PWMDAT2
PWMCH0
PWMCH1
PWMCH2
PWMEN
PWMCFG
PWM0
PWM0
PWM1
PWM1
PWM2
PWM2
H
L
H
L
H
L
THREE-PHASE
PWM TIMING
UNIT
OUTPUT
CONTROL
UNIT
GATE
DRIVE
UNIT
PWM
SHUTDOWN
CONTROLLER
CORE CLOCK
SYNC
PWM
PWM
SYNC
TO INTERRUPT
CONTROLLER
TRIP
Figure 56. Overview of the PWM Controller
Rev. A | Page 54 of 92
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The PWMDAT1 register is a 10-bit register with a maximum
value of 0x3FF (= 1023), which corresponds to a maximum
programmed dead time of
Three-Phase Timing Unit
PWM Switching Frequency (PWMDAT0 MMR)
The PWM switching frequency is controlled by the PWM
period register, PWMDAT0. The fundamental timing unit of
the PWM controller is
TD(max) = 1023 × 2 × tCORE = 1023 × 2 × 24 ×10–9 = 48.97 μs
for a core clock of 41.78 MHz
Obviously, the dead time can be programmed to be zero by
writing 0 to the PWMDAT1 register.
t
CORE = 1/fCORE
where fCORE is the core frequency of the MicroConverter.
PWM Operating Mode (PWMCON, PWMSTA MMRs)
Therefore, for a 41.78 MHz fCORE, the fundamental time
increment is 24 ns. The value written to the PWMDAT0
register is effectively the number of fCORE clock increments in ½
a PWM period. The required PWMDAT0 value is a function of
the desired PWM switching frequency (fPWN) and is given by
As previously discussed, the PWM controller of the
ADuC7019/7020/7021/7022/7024/7025/7026/7027 can operate
in two distinct modes, single update mode and double update
mode. The operating mode of the PWM controller is
determined by the state of Bit 2 of the PWMCON register.
If this bit is cleared, the PWM operates in the single update
mode. Setting Bit 2 places the PWM in the double update
mode. The default operating mode is single update mode.
PWMDAT0 = fCORE/(2 × fPWM
)
Therefore, the PWM switching period, TS, can be written as
TS = 2 × PWMDAT0 × tCORE
In single update mode, a single PWMSYNC pulse is produced
in each PWM period. The rising edge of this signal marks the
start of a new PWM cycle, and is used to latch new values from
the PWM configuration registers (PWMDAT0 and PWMDAT1)
and the PWM duty cycle registers (PWMCH0, PWMCH1, and
PWMCH2) into the three-phase timing unit. In addition, the
PWMEN register is latched into the output control unit on the
rising edge of the PWMSYNC pulse. In effect, this means that
the characteristics and resulting duty cycles of the PWM signals
can be updated only once per PWM period at the start of each
cycle. The result is symmetrical PWM patterns about the
midpoint of the switching period.
The largest value that can be written to the 16-bit PWMDAT0
MMR is 0×FFFF = 65535, which corresponds to a minimum
PWM switching frequency of
f
PWM(min) = 41.78 × 106/(2 × 65535) = 318.75 Hz
Note that a PWMDAT0 value of 0 and 1 are not defined and
should not be used.
PWM Switching Dead Time (PWMDAT1 MMR)
The second important parameter that must be set up in the initial
configuration of the PWM block is the switching dead time. This
is a short delay time introduced between turning off one PWM
signal (0H, for example) and turning on the complementary
signal (0L). This short time delay is introduced to permit the
power switch to be turned off (in this case, 0H) to completely
recover its blocking capability before the complementary switch is
turned on. This time delay prevents a potentially destructive
short-circuit condition from developing across the dc link
capacitor of a typical voltage source inverter.
In double update mode, there is an additional PWMSYNC
pulse produced at the midpoint of each PWM period. The
rising edge of this new PWMSYNC pulse is again used to latch
new values of the PWM configuration registers, duty cycle
registers, and the PWMEN register. As a result, it is possible to
alter both the characteristics (switching frequency and dead
time) as well as the output duty cycles at the midpoint of each
PWM cycle. Consequently, it is also possible to produce PWM
switching patterns that are no longer symmetrical about the
midpoint of the period (asymmetrical PWM patterns). In
double update mode, it may be necessary to know whether
operation at any point in time is in either the first half or the
second half of the PWM cycle. This information is provided by
Bit 0 of the PWMSTA register, which is cleared during
operation in the first half of each PWM period (between the
rising edge of the original PWMSYNC pulse and the rising edge
of the new PWMSYNC pulse introduced in double update
mode). Bit 0 of the PWMSTA register is set during operation
in the second half of each PWM period. This status bit allows
the user to make a determination of the particular half-cycle
during implementation of the PWMSYNC interrupt service
routine, if required.
The dead time is controlled by the 10-bit, read/write PWMDAT1
register. There is only one dead-time register that controls the
dead time inserted into all three pairs of PWM output signals.
The dead time, TD, is related to the value in the PWMDAT1
register by:
TD = PWMDAT1 × 2 × tCORE
Therefore, a PWMDAT1 value of 0x00A (= 10), introduces
a 426 ns delay between the turn-off on any PWM signal (0H,
for example) and the turn-on of its complementary signal (0L).
The amount of the dead time can therefore be programmed in
increments of 2tCORE (or 49 ns for a 41.78 MHz core clock).
Rev. A | Page 55 of 92
ADuC7019/20/21/22/24/25/26/27
The advantage of double update mode is that lower harmonic
voltages can be produced by the PWM process and faster
control bandwidths are possible. However, for a given PWM
switching frequency, the PWMSYNC pulses occur at twice the
rate in the double update mode. Because new duty cycle values
must be computed in each PWMSYNC interrupt service
routine, there is a larger computational burden on the ARM
core in double update mode.
Both switching edges are moved by an equal amount
(PWMDAT1 × tCORE) to preserve the symmetrical output
patterns.
Also shown is the PWMSYNC pulse and Bit 0 of the PWMSTA
register, which indicates whether operation is in the first or
second half cycle of the PWM period.
The resulting on-times of the PWM signals over the full PWM
period (two half periods) produced by the timing unit can be
written as follows:
PWM Duty Cycles (PWMCH0, PWMCH1,
PWMCH2 MMRs)
On the high side
The duty cycles of the six PWM output signals on Pin PWM0H
to Pin PWM2L are controlled by the three, 16-bit read/write
duty cycle registers, PWMCH0, PWMCH1, and PWMCH2.
The duty cycle registers are programmed in integer counts of
the fundamental time unit, tCORE. They define the desired on-
time of the high-side PWM signal produced by the three-phase
timing unit over half the PWM period. The switching signals
produced by the three-phase timing unit are also adjusted to
incorporate the programmed dead time value in the
T0HH = PWMDAT0 + 2(PWMCH0 − PWMDAT1) × tCORE
T
0HL = PWMDAT0 − 2(PWMCH0 − PWMDAT1) × tCORE
and the corresponding duty cycles (d)
0H = T0HH/TS = ½ + (PWMCH0 − PWMDAT1)/PWMDAT0
and on the low side
d
T
0LH = PWMDAT0 − 2(PWMCH0 + PWMDAT1) × tCORE
0LL = PWMDAT0 + 2(PWMCH0 + PWMDAT1) × tCORE
PWMDAT1 register. The three-phase timing unit produces
active low signals so that a low level corresponds to a command
to turn on the associated power device.
T
and the corresponding duty cycles (d)
OL = T0LH/TS = ½ − (PWMCH0 + PWMDAT1)/PWMDAT0
d
Figure 57 shows a typical pair of PWM outputs (in this case, 0H
and 0L) from the timing unit in single update mode. All
illustrated time values indicate the integer value in the
associated register and can be converted to time by simply
multiplying by the fundamental time increment, tCORE. Note that
the switching patterns are perfectly symmetrical about the
midpoint of the switching period in this mode because the same
values of PWMCH0, PWMDAT0, and PWMDAT1 are used to
define the signals in both half cycles of the period.
The minimum permissible T0H and T0L values are zero,
corresponding to a 0ꢀ duty cycle. In a similar fashion, the
maximum value is TS, corresponding to a 100ꢀ duty cycle.
Figure 58 shows the output signals from the timing unit for
operation in double update mode. It illustrates a general case
where the switching frequency, dead time, and duty cycle are all
changed in the second half of the PWM period. Of course, the
same value for any or all of these quantities can be used in both
halves of the PWM cycle. However, there is no guarantee that
symmetrical PWM signals are produced by the timing unit in
double update mode. Figure 58 also shows that the dead time
inserted into the PWM signals are done so in the same way as
demonstrated in single update mode.
Figure 57 also demonstrates how the programmed duty cycles
are adjusted to incorporate the desired dead time into the
resulting pair of PWM signals. Clearly, the dead time is incor-
porated by moving the switching instants of both PWM signals
(0H and 0L) away from the instant set by the PWMCH0 register.
–PWMDAT0 /2
2
–PWMDAT0/2
0
+PWMDAT0/2
0
–PWMDAT0/2
+PWMDAT0 /2
–PWMDAT0 /2
0
+PWMDAT0 /2
0
2
1
1
PWMCH0
PWMCH0
0H
PWMCH0
PWMCH0
1
2
0H
0L
2 × PWMDAT1
2 × PWMDAT1
2 × PWMDAT1
2 × PWMDAT1
2
1
0L
PWMDAT2+1
PWMSYNC
PWMSYNC
PWMDAT2 +1
PWMDAT2 +1
2
1
PWMSTA (0)
PWMSTA (0)
PWMDAT0
PWMDAT0
PWMDAT0
PWMDAT0
2
1
Figure 57. Typical PWM Outputs of Three-Phase Timing Unit
in Single Update Mode
Figure 58. Typical PWM Outputs of the Three-Phase Timing Unit
in Double Update Mode
Rev. A | Page 56 of 92
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In general, the on-times of the PWM signals in double update
mode can be defined as follows:
Output Control Unit
The operation of the output control unit is controlled by the
9-bit read/write PWMEN register. This register controls two
distinct features of the output control unit that are directly
useful in the control of electronic counter measures (ECM) or
binary decimal counter measures (BDCM). The PWMEN
register contains three crossover bits, one for each pair of PWM
outputs. Setting Bit 8 of the PWMEN register enables the
crossover mode for the 0H/0L pair of PWM signals, setting
Bit 7 enables crossover on the 1H/1L pair of PWM signals, and
setting Bit 6 enables crossover on the 2H/2L pair of PWM
signals. If crossover mode is enabled for any pair of PWM
signals, the high-side PWM signal from the timing unit (0H, for
example) is diverted to the associated low-side output of the
output control unit so that the signal ultimately appears at the
PWM0L pin. Of course, the corresponding low-side output of
the timing unit is also diverted to the complementary high-side
output of the output control unit so that the signal appears at
the PWM0H pin. Following a reset, the three crossover bits are
cleared and the crossover mode is disabled on all three pairs of
PWM signals. The PWMEN register also contains 6 bits (Bit 0
to Bit 5) that can be used to individually enable or disable each
of the six PWM outputs. If the associated bit of the PWMEN
register is set, the corresponding PWM output is disabled
regardless of corresponding value of the duty cycle register. This
PWM output signal remains in the off state as long as the
corresponding enable/disable bit of the PWMEN register is set.
The implementation of this output enable function is
On the high side
T0HH = (PWMDAT01/2 + PWMDAT02/2 + PWMCH01 +
PWMCH02 − PWMDAT11 − PWMDAT12) × tCORE
T0HL = (PWMDAT01/2 + PWMDAT02/2 − PWMCH01 −
PWMCH02 + PWMDAT11 + PWMDAT12) × tCORE
where the subscript 1 refers to the value of that register during
the first half cycle, and the subscript 2 refers to the value during
the second half cycle.
The corresponding duty cycles (d) are
d0H = T0HH/TS = (PWMDAT01/2 + PWMDAT02/2 +
PWMCH01 + PWMCH02 − PWMDAT11 − PWMDAT12)/
(PWMDAT01+ PWMDAT02)
On the low side
T0LH = (PWMDAT01/2 + PWMDAT02/2 + PWMCH01 +
PWMCH02 + PWMDAT11 + PWMDAT12) × tCORE
T0LL = (PWMDAT01/2 + PWMDAT02/2 − PWMCH01 −
PWMCH02 − PWMDAT11 − PWMDAT12) × tCORE
where the subscript 1 refers to the value of that register during
the first half cycle, and the subscript 2 refers to the value during
the second half cycle.
The corresponding duty cycles (d) are
d0L = T0LH/TS = (PWMDAT01/2 + PWMDAT02/2 +
PWMCH01 + PWMCH02 + PWMDAT11 +
PWMDAT12)/(PWMDAT01 + PWMDAT02)
implemented after the crossover function.
Following a reset, all six enable bits of the PWMEN register are
cleared, and all PWM outputs are enabled by default. In a
manner identical to the duty cycle registers, the PWMEN is
latched on the rising edge of the PWMSYNC signal. As a result,
changes to this register only become effective at the start of each
PWM cycle in single update mode. In double update mode, the
PWMEN register can also be updated at the midpoint of the
PWM cycle.
For the completely general case in double update mode
(see Figure 58), the switching period is given by
TS = (PWMDAT01 + PWMDAT02) × tCORE
Again, the values of T0H and T0L are constrained to lie between
zero and TS.
PWM signals similar to those illustrated in Figure 57 and
Figure 58 can be produced on the 1H, 1L, 2H, and 2L outputs by
programming the PWMCH1 and PWMCH2 registers in a manner
identical to that described for PWMCH0. The PWM controller
does not produce any PWM outputs until all of the PWMDAT0,
PWMCH0, PWMCH1, and PWMCH2 registers have been written
to at least once. Once these registers have been written, internal
counting of the timers in the three-phase timing unit is enabled.
In the control of an ECM, only two inverter legs are switched at
any time, and often the high-side device in one leg must be
switched on at the same time as the low-side driver in a second
leg. Therefore, by programming identical duty cycle values for
two PWM channels (for example, PWMCH0 = PWMCH1) and
setting Bit 7 of the PWMEN register to cross over the 1H/1L
pair of PWM signals, it is possible to turn on the high-side
switch of Phase A and the low-side switch of Phase B at the
same time. In the control of ECM, it is usual for the third
inverter leg (Phase C in this example) to be disabled for a
number of PWM cycles. This function is implemented by
disabling both the 2H and 2L PWM outputs by setting Bit 0
and Bit 1 of the PWMEN register.
Writing to the PWMDAT0 register starts the internal timing of the
main PWM timer. Provided that the PWMDAT0 register is written
to prior to the PWMCH0, PWMCH1, and PWMCH2 registers in
the initialization, the first PWMSYNC pulse and interrupt (if
enabled) appear 1.5 × tCORE × PWMDAT0 seconds after the initial
write to the PWMDAT0 register in single update mode. In double
update mode, the first PWMSYNC pulse appears after
PWMDAT0 × tCORE seconds.
Rev. A | Page 57 of 92
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This situation is illustrated in Figure 59, where it can be seen
that both the 0H and 1L signals are identical, because
The chopping frequency is therefore an integral subdivision of
the MicroConverter core frequency
PWMCH0 = PWMCH1 and the crossover bit for phase B is set.
f
CHOP = fCORE/(4 × (GDCLK + 1))
PWMCH0 = PWMCH0 =
PWMCH1 PWMCH1
The GDCLK value can range from 0 to 255, corresponding to
a programmable chopping frequency rate from 40.8 kHz to
10.44 MHz for a 41.78 MHz core frequency. The gate drive
features must be programmed before operation of the PWM
controller and are typically not changed during normal
operation of the PWM controller. Following a reset, all bits of
the PWMCFG register are cleared so that high frequency
chopping is disabled, by default.
0H
2 × PWMDAT1
2 × PWMDAT1
0L
1H
1L
2H
2L
PWMCH0
PWMCH0
0L
0H
2 × PWMDAT1
2 × PWMDAT1
PWMDAT0
PWMDAT0
Figure 59. Active LO PWM Signals Suitable for ECM Control,
PWMCH0 = PWMCH1, Crossover 1H/1L Pair and Disable
0L, 1H, 2H, and 2L Outputs in Single Update Mode.
4 × (GDCLK + 1) × tCORE
PWMDAT0
PWMDAT0
In addition, the other four signals (0L, 1H, 2H, and 2L) have
been disabled by setting the appropriate enable/disable bits of
the PWMEN register. In Figure 59, the appropriate value for
the PWMEN register is 0×00A7. In normal ECM operation,
each inverter leg is disabled for certain periods of time so that
the PWMEN register is changed based on the position of the
rotor shaft (motor commutation).
Figure 60. Typical PWM Signals with High Frequency Gate Chopping Enabled
on Both High-Side and Low-Side Switches
PWM Shut Down
In the event of external fault conditions, it is essential that the
PWM system be instantaneously shut down in a safe fashion. A
low level on the PWMTRIP pin provides an instantaneous,
asynchronous (independent of the MicroConverter core clock)
shutdown of the PWM controller. All six PWM outputs are
placed in the off state, that is, high state. In addition, the
PWMSYNC pulse is disabled. The PWMTRIP pin has an internal
pull-down resistor to disable the PWM if the pin becomes
disconnected. The state of the PWMTRIP pin can be read from
Bit 3 of the PWMSTA register.
Gate Drive Unit
The gate drive unit of the PWM controller adds features that
simplify the design of isolated gate-drive circuits for PWM
inverters. If a transformer-coupled, power device, gate-drive
amplifier is used, then the active PWM signal must be chopped at
a high frequency. The 10-bit read/write PWMCFG register
programs this high frequency chopping mode. The chopped
active PWM signals can be required for the high-side drivers
only, the low-side drivers only, or both the high-side and low-
side switches. Therefore, independent control of this mode for
both high-side and low-side switches is included with two
separate control bits in the PWMCFG register.
If a PWM shutdown command occurs, a PWMTRIP interrupt is
generated, and internal timing of the three-phase timing unit of
the PWM controller is stopped. Following a PWM shutdown, the
PWM can only be re-enabled (in a PWMTRIP interrupt service
routine, for example) by writing to all of the PWMDAT0,
PWMCH0, PWMCH1, and PWMCH2 registers. Provided that
the external fault is cleared and the PWMTRIP is returned to a
high level, the internal timing of the three-phase timing unit
resumes, and new duty-cycle values are latched on the next
PWMSYNC boundary.
Typical PWM output signals with high frequency chopping
enabled on both high-side and low-side signals are shown in
Figure 60. Chopping of the high-side PWM outputs (0H, 1H,
and 2H) is enabled by setting Bit 8 of the PWMCFG register.
Chopping of the low-side PWM outputs (0L, 1L, and 2L) is
enabled by setting Bit 9 of the PWMCFG register. The high
chopping frequency is controlled by the 8-bit word (GDCLK)
placed in Bit 0 to Bit 7 of the PWMCFG register. The period of
this high frequency carrier is
Note that the PWMTRIP interrupt is available in IRQ only,
and the PWMSYNC interrupt is available in FIQ only. Both
interrupts share the same bit in the interrupt controller.
Therefore, only one of the interrupts can be used at once.
See the Interrupt System section for further details.
TCHOP = (4 × (GDCLK + 1)) × tCORE
Rev. A | Page 58 of 92
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PWM MMRs Interface
PWMCFG Register
Name
PWMCFG
Address
0xFFFFFC10
Default Value
0x0000
Access
R/W
The PWM block is controlled via the MMRs described in this
section.
PWMCFG is a gate chopping register.
PWMCON Register
Name
Address
Default Value
Access
Table 37. PWMCFG MMR Bit Descriptions
PWMCON
0xFFFFFC00
0x0000
R/W
Bit
15:10
9
Name
Description
PWMCON is a control register that enables the PWM and
chooses the update rate.
Reserved.
CHOPLO
CHOPHI
GDCLK
Low-side gate chopping enable bit.
High-side gate chopping enable bit.
PWM gate chopping period (unsigned).
8
7:0
Table 35. PWMCON MMR Bit Descriptions
Bit
7:5
4
Name
Description
Reserved.
PWMEN Register
PWM_SYNCSEL
PWM_EXTSYNC
External Sync Select. Set to use external
sync. Cleared to use internal sync.
External Sync Select. Set to select
external synchronous sync signal.
Cleared for asynchronous sync signal.
Double Update Mode. Set to 1 by user
to enable double update mode.
Cleared to 0 by the user to enable
single update mode.
Name
Address
Default Value
0x0000
Access
R/W
PWMEN
0xFFFFFC20
3
2
PWMEN allows enabling channel outputs and crossover. See its
bit definitions in Table 38.
PWMDBL
Table 38. PWMEN MMR Bit Descriptions
Bit Name
Description
1
0
PWM_SYNC_EN
PWMEN
PWM Synchronization Enable. Set by
user to enable synchronization. Cleared
by user to disable synchronization.
PWM Enable Bit. Set to 1 by the user
to enable the PWM. Cleared to 0 by
the user to disable the PWM. Also
cleared automatically with PWMTRIP.
8
7
6
5
4
3
2
1
0
0H0L_XOVR Channel 0 Output Crossover Enable Bit. Set
to 1 by user to enable Channel 0 output
crossover. Cleared to 0 by user to disable
Channel 0 output crossover.
1H1L_XOVR Channel 1 Output Crossover Enable Bit. Set
to 1 by user to enable Channel 1 output
crossover. Cleared to 0 by user to disable
Channel 1 output crossover.
2H2L_XOVR Channel 2 Output Crossover Enable Bit. Set
to 1 by user to enable Channel 2 output
crossover. Cleared to 0 by user to disable
Channel 2 output crossover.
PWMSTA Register
Name
PWMSTA
Address
0xFFFFFC04
Default Value
Access
0x0000
R/W
0L_EN
0H_EN
1L_EN
1H_EN
2L_EN
2H_EN
0L Output Enable Bit. Set to 1 by user to
disable the 0L output of the PWM. Cleared
to 0 by user to enable the 0L output of the
PWM.
0H Output Enable Bit. Set to 1 by user to
disable the 0H output of the PWM. Cleared
to 0 by user to enable the 0H output of the
PWM.
1L Output Enable Bit. Set to 1 by user to
disable the 1L output of the PWM. Cleared
to 0 by user to enable the 1L output of the
PWM.
1H Output Enable Bit. Set to 1 by user to
disable the 1H output of the PWM. Cleared
to 0 by user to enable the 1H output of the
PWM.
2L Output Enable Bit. Set to 1 by user to
disable the 2L output of the PWM. Cleared
to 0 by user to enable the 2L output of the
PWM.
2H Output Enable Bit. Set to 1 by user to
disable the 2H output of the PWM. Cleared
to 0 by user to enable the 2H output of the
PWM.
PWMSTA reflects the status of the PWM.
Table 36. PWMSTA MMR Bit Descriptions
Bit
15:10
9
8
3
Name
Description
Reserved.
PWMSYNCINT PWM Sync Interrupt Bit.
PWMTRIPINT PWM Trip Interrupt Bit.
PWMTRIP
Raw Signal from the PWMTRIP Pin.
Reserved.
PWM Phase Bit. Set to 1 by the Micro-
Converter when the timer is counting
down (1st half). Cleared to 0 by the
MicroConverter when the timer is
counting up (2nd half).
2:1
0
PWMPHASE
Rev. A | Page 59 of 92
ADuC7019/20/21/22/24/25/26/27
PWMDAT0 Register
Table 39. GPIO Pin Function Descriptions
Name
Address
Default Value
Access
Configuration
PWMDAT0
0xFFFFFC08
0x0000
R/W
Port Pin
00
01
10
11
0
1
2
3
4
P0.0 GPIO
P0.1 GPIO
P0.2 GPIO
P0.3 GPIO
P0.4 GPIO/IRQ0
P0.5 GPIO/IRQ1
P0.6 GPIO/T1
P0.7 GPIO
P1.0 GPIO/T1
P1.1 GPIO
P1.2 GPIO
P1.3 GPIO
P1.4 GPIO/IRQ2
P1.5 GPIO/IRQ3
P1.6 GPIO
P1.7 GPIO
P2.0 GPIO
P2.1 GPIO
P2.2 GPIO
P2.3 GPIO
P2.4 GPIO
P2.5 GPIO
P2.6 GPIO
P2.7 GPIO
P3.0 GPIO
P3.1 GPIO
P3.2 GPIO
P3.3 GPIO
P3.4 GPIO
P3.5 GPIO
P3.6 GPIO
P3.7 GPIO
P4.0 GPIO
P4.1 GPIO
P4.2 GPIO
P4.3 GPIO
P4.4 GPIO
P4.5 GPIO
P4.6 GPIO
P4.7 GPIO
CMP
MS2
BLE
BHE
A16
MS1
MS0
AE
PLAI[7]
PWMDAT0 is an unsigned 16-bit register for switching period.
PWM2H
PWM2L
TRST
PWMTRIP
ADCBUSY
MRST
PWMDAT1 Register
Name
Address
Default Value
Access
ADCBUSY
PLAO[1]
PLAO[2]
PLAO[3]
PLAO[4]
PWMDAT1
0xFFFFFC0C
0x0000
R/W
PWMDAT1 is an unsigned 10-bit register for dead time.
ECLK/XCLK1 SIN
PWMCHx Registers
Name
Address
Default Value
0x0000
0x0000
Access
R/W
R/W
SIN
SOUT
RTS
CTS
RI
DCD
DSR
DTR
SCL0 PLAI[0]
SDA0 PLAI[1]
SCL1 PLAI[2]
SDA1 PLAI[3]
PWMCH0
PWMCH1
PWMCH2
0xFFFFFC14
0xFFFFFC18
0xFFFFFC1C
0x0000
R/W
CLK
PLAI[4]
PWMCH0, PWMCH1, and PWMCH2 are channel duty cycles
for the three phases.
MISO PLAI[5]
MOSI PLAI[6]
CSL
PWMDAT2 Register
PLAO[0]
Name
Address
Default Value
Access
2
CONVSTART
PWM0H
PWM0L
SOUT PLAO[5]
PWMDAT2
0xFFFFFC24
0x0000
R/W
WS
RS
AE
PLAO[6]
PLAO[7]
PWMDAT2 is an unsigned 10-bit register for PWM sync pulse
width.
PWM0H
PWM0L
PWM1H
PWM1L
PWM0H
PWM0L
PWM1H
PWM1L
PWM2H
PWM2L
PWMTRIP
PWMSYNC
MS0
MS1
MS2
MS3
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
GENERAL-PURPOSE INPUT/OUTPUT
The ADuC7019/7020/7021/7022/7024/7025/7026/7027 provide
40 general-purpose, bi-directional I/O (GPIO) pins. All I/O pins
are 5 V tolerant, which means that the GPIOs support an input
voltage of 5 V. In general, many of the GPIO pins have multiple
functions (see Table 39 for the pin function definitions). By
default, the GPIO pins are configured in GPIO mode.
PLAI[8]
PLAI[9]
PLAI[10]
PLAI[11]
PLAI[12]
PLAI[13]
PLAI[14]
PLAI[15]
PLAO[8]
PLAO[9]
All GPIO pins have an internal pull-up resistor (of about 100 kΩ)
and their drive capability is 1.6 mA. Note that a maximum of
20 GPIO can drive 1.6 mA at the same time. The following GPIO
have programmable pull up: P0.0, P0.4, P0.5, P0.6, P0.7, and the
8 GPIOs of P1.
AD10 PLAO[10]
AD11 PLAO[11]
AD12 PLAO[12]
AD13 PLAO[13]
AD14 PLAO[14]
AD15 PLAO[15]
The 40 GPIO are grouped in five ports, Port 0 to Port 4. Each
port is controlled by four or five MMRs, x representing the port
number.
Note that the kernel changes P0.6 from its default configuration
at reset (MRST) to GPIO mode. If MRST is used for external
circuitry, an external pull-up resistor should be used to ensure
that the level on P0.6 does not drop when the kernel switches
mode. For example, if MRST is required for power down, it can
be reconfigured in GP0CON MMR.
1 When configured in Mode 1, P0.7 is ECLK by default, or core clock output.
To configure it as a clock input, MDCLK bits in PLLCON must be set to 11.
2
CONVSTART
The
signal is active in all modes of P2.0.
GPxCON Registers
The input level of any GPIO can be read at any time in the
GPxDAT MMR, even when the pin is configured in a different
mode than GPIO. The PLA input are also always active.
Name
Address
Default Value
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
Access
R/W
R/W
R/W
R/W
GP0CON
GP1CON
GP2CON
GP3CON
GP4CON
0xFFFFF400
0xFFFFF404
0xFFFFF408
0xFFFFF40C
0xFFFFF410
R/W
Rev. A | Page 60 of 92
ADuC7019/20/21/22/24/25/26/27
GPxCON are the port x control registers, which select the
function of each pin of port x. as described in Table 40.
GPxDAT Registers
Name
Address
Default Value
0x000000XX
0x000000XX
0x000000XX
0x000000XX
0x000000XX
Access
R/W
R/W
R/W
R/W
GP0DAT
GP1DAT
GP2DAT
GP3DAT
GP4DAT
0xFFFFF420
0xFFFFF430
0xFFFFF440
0xFFFFF450
0xFFFFF460
Table 40. GPxCON MMR Bit Descriptions
Bit
Description
31:30
29:28
27:26
25:24
23:22
21:20
19:18
17:16
15:14
13:12
11:10
9:8
Reserved
Select Function of Px.7 Pin
Reserved
Select Function of Px.6 Pin
Reserved
Select Function of Px.5 Pin
Reserved
Select Function of Px.4 Pin
Reserved
Select Function of Px.3 Pin
Reserved
Select Function of Px.2 Pin
Reserved
R/W
GPxDAT are port x configuration and data registers. They
configure the direction of the GPIO pins of port x, set the
output value for the pins configured as output, and store the
input value of the pins configured as input.
Table 42. GPxDAT MMR Bit Descriptions
Bit
Description
31:24
Direction of the Data. Set to 1 by user to configure
the GPIO pin as an output. Cleared to 0 by user to
configure the GPIO pin as an input.
7:6
23:16
15:8
7:0
Port x Data Output.
Reflect the State of Port x Pins at Reset (read only).
Port x Data Input (read only).
5:4
3:2
Select Function of Px.1 Pin
Reserved
1:0
Select Function of Px.0 Pin
GPxSET Registers
GPxPAR Registers
Name
Address
Default Value
0x000000XX
0x000000XX
0x000000XX
0x000000XX
0x000000XX
Access
W
W
W
W
Name
Address
Default Value
0x20000000
0x00000000
0x00222222
Access
R/W
R/W
GP0SET
GP1SET
GP2SET
GP3SET
GP4SET
0xFFFFF424
0xFFFFF434
0xFFFFF444
0xFFFFF454
0xFFFFF464
GP0PAR
GP1PAR
GP3PAR
0xFFFFF42C
0xFFFFF43C
0xFFFFF45C
R/W
W
GPxPAR program the parameters for Port 0, Port 1, and Port 3.
Note that the GPxDAT MMR must always be written after
changing the GPxPAR MMR.
GPxSET are data set port x registers.
Table 43. GPxSET MMR Bit Descriptions
Table 41. GPxPAR MMR Bit Descriptions
Bit
Description
Bit
Description
31:24
23:16
Reserved.
31:29
28
27:25
24
23:21
20
19:17
16
15:13
12
11:9
8
7:5
4
Reserved
Pull-Up Disable Px.7
Reserved
Pull-Up Disable Px.6
Reserved
Pull-Up Disable Px.5
Reserved
Pull-Up Disable Px.4
Reserved
Pull-Up Disable Px.3
Reserved
Pull-Up Disable Px.2
Reserved
Pull-Up Disable Px.1
Reserved
Data Port x Set Bit. Set to 1 by user to set bit on port
x; also sets the corresponding bit in the GPxDAT
MMR. Cleared to 0 by user; does not affect the data out.
15:0
Reserved.
GPxCLR Registers
Name
Address
Default Value
0x000000XX
0x000000XX
0x000000XX
0x000000XX
0x000000XX
Access
W
W
W
W
GP0CLR
GP1CLR
GP2CLR
GP3CLR
GP4CLR
0xFFFFF428
0xFFFFF438
0xFFFFF448
0xFFFFF458
0xFFFFF468
W
GPxCLR are data clear port x registers.
Table 44. GPxCLR MMR Bit Descriptions
3:1
Bit
Description
0
Pull-Up Disable Px.0
31:24
23:16
Reserved.
Data Port x Clear Bit. Set to 1 by user to clear bit on
port x; also clears the corresponding bit in the
GPxDAT MMR. Cleared to 0 by user; does not affect
the data out.
15:0
Reserved.
Rev. A | Page 61 of 92
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Baud Rate Generation
SERIAL PORT MUX
There are two ways of generating the UART baud rate.
The serial port mux multiplexes the serial port peripherals
(an SPI, UART, and two I2Cs) and the programmable logic array
(PLA) to a set of ten GPIO pins. Each pin must be configured to
one of its specific I/O functions as described in Table 45.
1. Normal 450 UART Baud Rate Generation.
The baud rate is a divided version of the core clock using the
value in COMDIV0 and COMDIV1 MMRs (16-bit value, DL).
Table 45. SPM Configuration
GPIO
(00)
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P0.7
P2.0
UART
(01)
UART/I2C/SPI
(10)
PLA
(11)
41.78MHz
2CD × 16 × 2 × DL
Baud rate =
Pin
SPM0
SPM1
SPM2
SPM3
SPM4
SPM5
SPM6
SPM7
SPM8
SPM9
SIN
SOUT
RTS
CTS
RI
DCD
DSR
DTR
ECLK/XCLK
CONV
I2C0SCL
I2C0SDA
I2C1SCL
I2C1SDA
SPICLK
SPIMISO
SPIMOSI
SPICSL
PLAI[0]
PLAI[1]
PLAI[2]
PLAI[3]
PLAI[4]
PLAI[5]
PLAI[6]
PLAO[0]
PLAO[4]
PLAO[5]
Table 47 gives some common baud rate values.
Table 47. Baud Rate Using the Normal Baud Rate Generator
Baud Rate
9600
CD
0
DL
Actual Baud Rate
9600
ꢀ Error
88 h
44 h
0
0
19200
0
19200
115200
9600
0
3
3
3
0B h
11 h
8 h
118691
9600
3
0
SIN
SOUT
19200
115200
20400
163200
6.25
41.67
1 h
Table 45 also details the mode for each of the SPMUX GPIO
pins. This configuration has to be done via the GP0CON,
GP1CON, and GP2CON MMRs. By default these ten pins are
configured as GPIOs.
2. Using the Fractional Divider.
The fractional divider combined with the normal baud rate
generator produces a wider range of more accurate baud rates.
UART SERIAL INTERFACE
FBEN
CORE
CLOCK
/2
The UART peripheral is a full-duplex, universal, asynchronous
receiver/transmitter. It is fully compatible with the 16450 serial port
standard. The UART performs serial-to-parallel conversion on data
characters received from a peripheral device or modem, and
parallel-to-serial conversion on data characters received from the
CPU. The UART includes a fractional divider for baud rate
generation and has a network addressable mode. The UART
function is made available on the 10 pins of the ADuC7019/7020/
7021/7022/7024/7025/7026/7027 (see Table 46).
/16DL
UART
/(M+N/2048)
Figure 61. Baud Rate Generation Options
Calculation of the baud rate using fractional divider is as
follows:
41.78MHz
Baud Rate =
N
2048
2
CD ×16×DL×2×
(
M +
)
Table 46. UART Signal Description
41.78MHz
2048 Baud Rate × 2CD ×16 ×DL×2
N
M +
=
Pin
Signal
Description
SPM0 (Mode 1)
SPM1 (Mode 1)
SPM2 (Mode 1)
SPM3 (Mode 1)
SPM4 (Mode 1)
SPM5 (Mode 1)
SPM6 (Mode 1)
SPM7 (Mode 1)
SPM8 (Mode 2)
SPM9 (Mode 2)
SIN
SOUT
RTS
CTS
RI
DCD
DSR
DTR
SIN
Serial Receive Data
Serial Transmit Data
Request to Send
Clear to Send
Ring Indicator
Data Carrier Detect
Data Set Ready
Data Terminal Ready
Serial Receive Data
Serial Transmit Data
For example, generation of 19,200 baud with CD bits = 3
(Table 47 gives DL = 8 h),
41.78MHz
2048 19200×23 ×16×8×2
N
M +
=
N
2048
M +
=1.06
where:
M = 1
N = 0.06 × 2048 = 128
SOUT
The serial communication adopts an asynchronous protocol,
which supports various word lengths, stop bits, and parity
generation options selectable in the configuration register.
41.78MHz
Baud Rate =
128
2048
⎛
⎜
⎝
⎞
⎟
⎠
23 ×16×8× 2×
where:
Baud Rate = 19,200 bps
Rev. A | Page 62 of 92
ADuC7019/20/21/22/24/25/26/27
Error = 0ꢀ compared to 6.25ꢀ with the normal baud rate
generator.
COMDIV1 Register
Name
Address
Default Value
Access
COMDIV1
0xFFFF0704
0x00
R/W
UART Registers Definition
COMDIV1 is a divisor latch (high byte) register.
The UART interface consists on 12 registers: COMTX,
COMRX, COMDIV0, COMIEN0, COMDIV1, COMIIDO,
COMCON0, COMCON1, COMSTA0, COMSTA1, COMSCR,
and COMDIV2.
COMIID0 Register
Name
Address
Default Value
Access
COMIID0
0xFFFF0708
0x01
R
COMIID0 is the interrupt identification register.
COMTX Register
Name
Address
Default Value
Access
Table 49. COMIID0 MMR Bit Descriptions
Bit 2:1
COMTX
0xFFFF0700
0x00
R/W
Status Bit 0
Clearing
Operation
COMTX is an 8-bit transmit register.
Bits
NINT Priority Definition
COMRX Register
00
11
1
0
No interrupt
Receive line
status interrupt
Receive buffer
full interrupt
Transmit buffer Write data to
empty interrupt COMTX or read
COMIID0
Modem status
interrupt
Name
Address
Default Value
Access
1
2
3
Read COMSTA0
Read COMRX
COMRX
0xFFFF0700
0x00
R
10
01
0
0
COMRX is an 8-bit receive register.
COMDIV0 Register
Name
Address
Default Value
Access
COMDIV0
0xFFFF0700
0x00
R/W
00
0
4
Read COMSTA1
register
COMDIV0 is a low-byte divisor latch. COMTX, COMRX,
and COMDIV0 share the same address location. COMTX
and COMRX can be accessed when Bit 7 in COMCON0
register is cleared. COMDIV0 can be accessed when Bit 7
of COMCON0 is set.
COMCON0 Register
Name
Address
Default Value
Access
COMCON0
0xFFFF070C
0x00
R/W
COMIEN0 Register
COMCON0 is the line control register.
Name
Address
Default Value
Access
Table 50. COMCON0 MMR Bit Descriptions
COMIEN0
0xFFFF0704
0x00
R/W
Bit
Name
Description
COMIEN0 is the interrupt enable register.
7
DLAB
Divisor Latch Access. Set by user to enable
access to COMDIV0 and COMDIV1 registers.
Cleared by user to disable access to COMDIV0
and COMDIV1 and enable access to COMRX
and COMTX.
Set Break. Set by user to force SOUT to 0.
Cleared to operate in normal mode.
Stick Parity. Set by user to force parity to
defined values: 1 if EPS = 1 and PEN = 1,
0 if EPS = 0 and PEN = 1.
Even Parity Select Bit. Set for even parity.
Cleared for odd parity.
Parity Enable Bit. Set by user to transmit and
check the parity bit. Cleared by user for no
parity transmission or checking.
Stop Bit. Set by user to transmit 1.5 stop bits if the
word length is 5 bits or 2 stop bits if the word
length is 6 bits, 7 bits, or 8 bits. The receiver
checks the first stop bit only, regardless of the
number of stop bits selected. Cleared by user to
generate 1 stop bit in the transmitted data.
Word Length Select:
00 = 5 bits, 01 = 6 bits
10 = 7 bits, 11 = 8 bits
Table 48. COMIEN0 MMR Bit Descriptions
Bit
7:4
3
Name
Description
Reserved.
EDSSI
Modem Status Interrupt Enable Bit. Set by
user to enable generation of an interrupt if
any of COMSTA1[3:0] are set. Cleared by user.
6
5
BRK
SP
2
1
0
ELSI
Rx Status Interrupt Enable Bit. Set by user to
enable generation of an interrupt if any of
COMSTA0[3:0] are set. Cleared by user.
Enable Transmit Buffer Empty Interrupt. Set
by user to enable interrupt when buffer is
empty during a transmission. Cleared by user.
Enable Receive Buffer Full Interrupt. Set by
user to enable interrupt when buffer is full
during a reception. Cleared by user.
4
3
EPS
ETBEI
ERBFI
PEN
2
STOP
WLS
1:0
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COMCON1 Register
COMSTA1 Register
Name
Address
Default Value
Access
Name
Address
Default Value
Access
COMCON1
0xFFFF0710
0x00
R/W
COMSTA1
0xFFFF0718
0x00
R
COMCON1 is the modem control register.
COMSTA1 is a modem status register.
Table 51. COMCON1 MMR Bit Descriptions
Table 53. COMSTA1 MMR Bit Descriptions
Bit
7:5
4
Name
Description
Bit Name Description
Reserved.
7
6
5
4
3
DCD
RI
DSR
CTS
Data Carrier Eetect.
Ring Indicator.
Data Set Ready.
Clear To Send.
LOOPBACK
Loop Back. Set by user to enable loop
back mode. In loop back mode, the
SOUT is forced high. The modem signals
are also directly connected to the status
inputs (RTS to CTS, DTR to DSR, OUT1 to
RI, and OUT2 to DCD). Cleared by user to
be in normal mode.
Parity Enable Bit. Set by user to transmit
and check the parity bit. Cleared by user
for no parity transmission or checking.
Stop Bit. Set by user to transmit 1.5 stop
bits if the word length is 5 bits or 2 stop
bits if the word length is 6 bits, 7 bits, or
8 bits. The receiver checks the first stop
bit only, regardless of the number of
stop bits selected. Cleared by user to
generate 1 stop bit in the transmitted
data.
DDCD Delta DCD. Set automatically if DCD changed
state since COMSTA1 last read. Cleared automati-
cally by reading COMSTA1.
2
1
0
TERI
Trailing Edge RI. Set if NRI changed from 0 to 1
since COMSTA1 last read. Cleared automatically
by reading COMSTA1.
3
2
PEN
DDSR Delta DSR. Set automatically if DSR changed state
since COMSTA1 last read. Cleared automatically
by reading COMSTA1.
STOP
DCTS
Delta CTS. Set automatically if CTS changed state
since COMSTA1 last read. Cleared automatically
by reading COMSTA1.
COMSCR Register
1
0
RTS
DTR
Request To Send. Set by user to force the
RTS output to 0. Cleared by user to force
the RTS output to 1.
Data Terminal Ready. Set by user to force
the DTR output to 0. Cleared by user to
force the DTR output to 1.
Name
Address
Default Value
Access
COMSCR
0xFFFF071C
0x00
R/W
COMSCR is an 8-bit scratch register used for temporary
storage. It is also used in network addressable UART mode.
COMDIV2 Register
Name
Address
Default Value
Access
COMSTA0 Register
COMDIV2
0xFFFF072C
0x0000
R/W
Name
Address
Default Value
Access
COMSTA0
0xFFFF0714
0x60
R
COMDIV2 is a 16-bit fractional baud divide register.
COMSTA0 is the line status register.
Table 54. COMDIV2 MMR Bit Descriptions
Bit
Name
Description
Table 52. COMSTA0 MMR Bit Descriptions
Bit Name Description
15
FBEN
Fractional Baud Rate Generator Enable Bit.
Set by user to enable the fractional baud
rate generator. Cleared by user to generate
baud rate using the standard 450 UART
baud rate generator.
Reserved.
M if FBM = 0, M = 4.
7
6
Reserved.
TEMT
THRE
COMTX Empty Status Bit. Set automatically if
COMTX is empty. Cleared automatically when
writing to COMTX.
COMTX and COMRX Empty. Set automatically if
COMTX and COMRX are empty. Cleared automati-
cally when one of the register receives data.
14:13
12:11
10:0
5
FBM[1-0]
FBN[10-0] N.
4
3
2
1
0
BI
Break Error. Set when SIN is held low for more than
the maximum word length. Cleared automatically.
Framing Error. Set when invalid stop bit. Cleared
automatically.
Parity Error. Set when a parity error occurs.
Cleared automatically.
Overrun Error. Set automatically if data is over-
written before being read. Cleared automatically.
Data Ready. Set automatically when COMRX is
full. Cleared by reading COMRX.
FE
PE
OE
DR
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Network Addressable UART Mode
Table 56. COMIID1 MMR Bit Descriptions
Bit 3:1
Status
Bits
This mode connects the MicroConverter to a 256-node serial
network, either as a hardware single-master or via software in a
multimaster network. Bit 7 of COMIEN1 (ENAM bit) must be set
to enable UART in network addressable mode. Note that there is
no parity check in this mode; the parity bit is used for address.
Bit 0
Clearing
Operation
NINT Priority Definition
000
110
1
0
No interrupt
Matching
network address
Address
transmitted,
buffer empty
Receive line
status interrupt
Receive buffer
full interrupt
2
3
Read COMRX
101
0
Write data to
COMTX or
read COMIID0
Read
COMSTA0
Network Addressable UART Register Definitions
Four additional registers, COMSCR, COMIEN1, COMIID1, and
COMADR are only used in network addressable UART mode.
011
010
001
0
0
0
1
2
3
COMSCR is an 8-bit scratch register used for temporary
storage. In network address mode, the least significant bit of the
scratch register is the transmitted network address control bit.
If set to 1, the device is transmitting an address. If cleared to 0,
the device is transmitting data.
Read COMRX
Transmit buffer
Write data to
empty interrupt COMTX or
read COMIID0
000
0
4
Modem status
interrupt
Read COMSTA1
register
COMIEN1 Register
Name
Address
Default Value
Access
COMIEN1
0xFFFF0720
0x04
R/W
COMADR Register
COMIEN1 is an 8-bit network enable register.
Name
Address
Default Value
Access
COMADR
0xFFFF0728
0xAA
R/W
Table 55. COMIEN1 MMR Bit Descriptions
Bit
Name
Description
COMADR is an 8-bit, read/write network address register that
holds the address that the network addressable UART checks
for. Upon receiving this address, the device interrupts the
processor and/or sets the appropriate status bit in COMIID1.
7
ENAM
Network Address Mode Enable Bit. Set by user
to enable network address mode. Cleared by
user to disable network address mode.
9-Bit Transmit Enable Bit. Set by user to enable
9-bit transmit. ENAM must be set. Cleared by
user to disable 9-bit transmit.
9-Bit Receive Enable Bit. Set by user to enable
9-bit receive. ENAM must be set. Cleared by
user to disable 9-bit receive.
Network Interrupt Enable Bit.
Word Length. Set for 9-bit data. E9BT has to be
cleared. Cleared for 8-bit data.
Transmitter Pin Driver Enable Bit. Set by user to
enable SOUT pin as an output in slave mode or
multimaster mode. Cleared by user; SOUT is
three-state.
6
5
E9BT
E9BR
SERIAL PERIPHERAL INTERFACE
The ADuC7019/7020/7021/7022/7024/7025/7026/7027 integrate
a complete hardware serial peripheral interface (SPI) on-chip. SPI
is an industry standard, synchronous serial interface that allows
eight bits of data to be synchronously transmitted and simultane-
ously received, that is, full duplex up to a maximum bit rate of
3.48 Mb as shown in Table 57. The SPI interface is not
operational with core clock divider bits (CD bits) POWCON[2:0]
= 6 or 7 in master mode.
4
3
ENI
E9BD
2
ETD
The SPI port can be configured for master or slave operation
and typically consists of four pins: MISO, MOSI, SCL, and CS.
1
0
NABP
NAB
Network Address Bit. Interrupt polarity bit.
Network Address Bit. Set by user to transmit the
slave’s address. Cleared by user to transmit data.
MISO (Master In, Slave Out) Pin
The MISO pin is configured as an input line in master mode
and an output line in slave mode. The MISO line on the master
(data in) should be connected to the MISO line in the slave
device (data out). The data is transferred as byte wide (8-bit)
serial data, MSB first.
COMIID1 Register
Name
Address
Default Value
Access
COMIID1
0xFFFF0724
0x01
R
COMIID1 is an 8-bit network interrupt register. Bit 7 to Bit 4
are reserved (see Table 56).
MOSI (Master Out, Slave In) Pin
The MOSI pin is configured as an output line in master mode
and an input line in slave mode. The MOSI line on the master
(data out) should be connected to the MOSI line in the slave
device (data in). The data is transferred as byte wide (8-bit)
serial data, MSB first.
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SCL (Serial Clock) I/O Pin
SPISTA Register
Name
Address
Default Value
Access
The master serial clock (SCL) is used to synchronize the data
being transmitted and received through the MOSI SCL period.
Therefore, a byte is transmitted/received after eight SCL
periods. The SCL pin is configured as an output in master mode
and as an input in slave mode.
SPISTA
0xFFFF0A00
0x00
R/W
SPISTA is an 8-bit read-only status register. Only Bit 1 or Bit 4
of this register generates an interrupt. Bit 6 of the SPICON
register determines which bit generates the interrupt.
Table 58. SPISTA MMR Bit Descriptions
In master mode, polarity and phase of the clock are controlled
by the SPICON register, and the bit rate is defined in the
SPIDIV register as follows:
Bit
7:6
5
Description
Reserved.
SPIRX Data Register Overflow Status Bit. Set if SPIRX is
overflowing. Cleared by reading SPIRX register.
fUCLK
fserial clock
=
2×(1+ SPIDIV )
4
3
SPIRX Data Register IRQ. Set automatically if Bit 3 or Bit 5
is set. Cleared by reading SPIRX register.
SPIRX Data Register Full Status Bit. Set automatically if a
valid data is present in the SPIRX register. Cleared by
reading SPIRX register.
The maximum speed of the SPI clock is dependant on the clock
divider bits and is summarized in Table 57.
Table 57. SPI Speed vs. Clock Divider Bits in Master Mode
2
1
0
SPITX Data Register Underflow Status Bit. Set auto-
matically if SPITX is under flowing. Cleared by writing in
the SPITX register.
SPITX Data Register IRQ. Set automatically if Bit 0 is clear
or Bit 2 is set. Cleared by writing in the SPITX register or if
finished transmission disabling the SPI.
SPITX Data Register Empty Status Bit. Set by writing to
SPITX to send data. This bit is set during transmission of
data. Cleared when SPITX is empty.
CD Bits
0
1
2
3
4
5
SPIDIV in
hex
0x05
0x0B 0x17
0x2F
0x5F
0xBF
SPI speed 3.482 1.741 0.870
in MHz
0.435
0.218
0.109
In slave mode, the SPICON register must be configured with
the phase and polarity of the expected input clock. The slave
accepts data from an external master up to 10.4 Mb at CD = 0.
The formula to determine the maximum speed is as follow:
SPIRX Register
fHCLK
Name
Address
Default Value
Access
fserialclock
=
4
SPIRX
0xFFFF0A04
0x00
R
SPIRX is an 8-bit read-only receive register.
In both master and slave modes, data is transmitted on one edge
of the SCL signal and sampled on the other. Therefore, it is
important that the polarity and phase are configured the same
for the master and slave devices.
SPITX Register
Name
Address
Default Value
Access
SPITX
0xFFFF0A08
0x00
W
Chip Select (CS) Input Pin
SPITX is an 8-bit write-only transmit register.
CS
In SPI slave mode, a transfer is initiated by the assertion of
which is an active low input signal. The SPI port then transmits
and receives 8-bit data until the transfer is concluded by
,
SPIDIV Register
Name
Address
Default Value
Access
SPIDIV
0xFFFF0A0C
0x1B
R/W
CS
CS
deassertion of . In slave mode,
is always an input.
SPIDIV is an 8-bit serial clock divider register.
SPI Registers
SPICON Register
The following MMR registers are used to control the SPI
interface: SPISTA, SPIRX, SPITX, SPIDIV, and SPICON.
Name
Address
Default Value
Access
SPICON
0xFFFF0A10
0x0000
R/W
SPICON is a 16-bit control register.
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Table 59. SPICON MMR Bit Descriptions
Bit
Description
15:13
12
Reserved.
Continuous Transfer Enable. Set by user to enable continuous transfer. In master mode, the transfer continues until no valid data
is available in the TX register. CS is asserted and remains asserted for the duration of each 8-bit serial transfer until TX is empty.
Cleared by user to disable continuous transfer. Each transfer consists of a single 8-bit serial transfer. If valid data exists in the
SPITX register, then a new transfer is initiated after a stall period.
11
10
9
Loop Back Enable. Set by user to connect MISO to MOSI and test software. Cleared by user to be in normal mode.
Slave Output Enable. Set by user to enable the slave output. Cleared by user to disable slave output.
Slave Select Input Enable. Set by user in master mode to enable the output. Cleared by user to disable master output.
8
SPIRX Overflow Overwrite Enable. Set by user, the valid data in the RX register is overwritten by the new serial byte received.
Cleared by user, the new serial byte received is discarded.
7
6
SPITX Underflow Mode. Set by user to transmit 0. Cleared by user to transmit the previous data.
Transfer and Interrupt Mode. Set by user to initiate transfer with a write to the SPITX register. Interrupt only occurs when TX is
empty. Cleared by user to initiate transfer with a read of the SPIRX register. Interrupt only occurs when RX is full.
5
4
3
2
LSB First Transfer Enable Bit. Set by user, the LSB is transmitted first. Cleared by user, the MSB is transmitted first.
Reserved.
Serial Clock Polarity Mode Bit. Set by user, the serial clock idles high. Cleared by user, the serial clock idles low.
Serial Clock Phase Mode Bit. Set by user, the serial clock pulses at the beginning of each serial bit transfer. Cleared by user, the
serial clock pulses at the end of each serial bit transfer.
1
0
Master Mode Enable Bit. Set by user to enable master mode. Cleared by user to enable slave mode.
SPI Enable Bit. Set by user to enable the SPI. Cleared by user to disable the SPI.
I2C COMPATIBLE INTERFACES
Serial Clock Generation
The I2C master in the system generates the serial clock for a
transfer. The master channel can be configured to operate in
fast mode (400 kHz) or standard mode (100 kHz).
The ADuC7019/7020/7021/7022/7024/7025/7026/7027 support
two fully licensed I2C interfaces. The I2C interfaces are both
implemented as a full hardware master and slave interface. Because
the two I2C interfaces are identical, this data sheet describes only
I2C0 in detail. Note that the two masters and one of the slaves have
individual interrupts. See the Interrupt System section.
The bit rate is defined in the I2C0DIV MMR as follows:
fUCLK
fserialclock
=
(2 + DIVH) + (2 + DIVL)
The two pins used for data transfer, SDA and SCL, are
configured in a wired-AND format that allows arbitration in a
multimaster system.
where:
UCLK = clock before the clock divider.
f
The I2C bus peripheral’s address in the I2C bus system is
programmed by the user. This ID can be modified any time a
transfer is not in progress. The user can configure the interface
to respond to four slave addresses.
DIVH = the high period of the clock.
DIVL = the low period of the clock.
Thus, for 100 kHz operation,
DIVH = DIVL = 0×CF
The transfer sequence of an I2C system consists of a master
device initiating a transfer by generating a start condition while
the bus is idle. The master transmits the address of the slave
device and the direction of the data transfer in the initial
address transfer. If the master does not lose arbitration and the
slave acknowledges, then the data transfer is initiated. This
continues until the master issues a stop condition and the bus
becomes idle.
and for 400 kHz,
DIVH = DIVL = 0×32
The I2C×DIV register corresponds to DIVH:DIVL.
Slave Addresses
The registers I2C0ID0, I2C0ID1, I2C0ID2, and I2C0ID3
contain the device IDs. The device compares the four I2C0IDx
registers to the address byte. The seven most significant bits of
either ID register must be identical to that of the seven most
significant bits of the first address byte received to be correctly
addressed. The LSB of the ID registers, the transfer direction
bit, is ignored in the process of address recognition.
The I2C peripheral master and slave functionality are
independent and can be simultaneously active. A slave is
activated when a transfer has been initiated on the bus. If it is
not addressed, it remains inactive until another transfer is
initiated. This also allows a master device, which loses
arbitration, to respond as a slave in the same cycle.
Rev. A | Page 67 of 92
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I2C Registers
Table 61. I2C0SSTA MMR Bit Descriptions
The I2C peripheral interface consists of 18 MMRs, which are
discussed in this section.
Bit
Value Description
31:15
14
Reserved. These bits should be written as 0.
START Decode Bit. Set by hardware if the
device receives a valid START + matching
address. Cleared by an I2C STOP condition
or an I2C general call reset.
Repeated START Decode Bit. Set by hardware
if the device receives a valid repeated START +
matching address. Cleared by an I2C STOP
condition, a read of the I2CSSTA register,
or an I2C general call reset.
I2CxMSTA Registers
Name
Address
Default Value
0x00
0x00
Access
I2C0MSTA
I2C1MSTA
0xFFFF0800
0xFFFF0900
R
R
13
I2CxMSTA are status registers for the master channel.
Table 60. I2C0MSTA MMR Bit Descriptions
Bit Description
12:11
ID Decode Bits.
7
Master Transmit FIFO Flush. Set by user to flush the master
Tx FIFO. Cleared automatically once the master Tx FIFO is
flushed. This bit also flushes the slave receive FIFO.
00
01
10
11
Received Address Natched ID Register 0.
Received Address Matched ID Register 1.
Received Address Matched ID Register 2.
Received Address Matched ID Register 3.
6
5
4
Master Busy. Set automatically if the master is busy. Cleared
automatically.
10
Stop After Start and Matching Address
Arbitration Loss. Set in multimaster mode if another master
has the bus. Cleared when the bus becomes available.
No ACK. Set automatically if there is no acknowledge of the
address by the slave device. Cleared automatically by
reading the I2C0MSTA register.
Interrupt. Set by hardware if the slave device
receives an I2C STOP condition after a previous
I2C START condition and matching address.
Cleared by a read of the I2C0SSTA register.
9:8
General Call ID.
3
2
1
Master Receive IRQ. Set after receiving data. Cleared
automatically by reading the I2C0MRX register.
Master Transmit IRQ. Set at the end of a transmission.
Cleared automatically by writing to the I2C0MTX register.
Master Transmit FIFO Underflow. Set automatically if the
master transmit FIFO is underflowing. Cleared
00
01
10
11
No General Call.
General Call Reset and Program Address.
General Call Program Address.
General Call Matching Alternative ID.
7
General Call Interrupt. Set if the slave device
receives a general call of any type. Cleared by
setting Bit 8 of the I2CxCFG register. If it is a
general call reset, then all registers are at their
default values. If it is a hardware general call,
then the Rx FIFO holds the second byte of the
general call. This is similar to the I2C0ALT
register (unless it is a general call to reprogram
the device address). For more details, see I2C
bus specification, version 2.1, Jan. 2000.
Slave Busy. Set automatically if the slave is
busy. Cleared automatically.
No ACK. Set if master asking for data and no
data is available. Cleared automatically by
reading the I2C0SSTA register.
automatically by writing to the I2C0MTX register.
0
Master TX FIFO Empty. Set automatically if the master
transmit FIFO is empty. Cleared automatically by writing to
the I2C0MTX register.
I2CxSSTA Registers
Name
Address
Default Value
0x01
0x01
Access
I2C0SSTA
I2C1SSTA
0xFFFF0804
0xFFFF0904
R
R
6
5
I2CxSSTA are status registers for the slave channel.
4
3
2
1
Slave Receive FIFO Overflow. Set automatically
if the slave receive FIFO is overflowing. Cleared
automatically by reading the I2C0SSTA register.
Slave Receive IRQ. Set after receiving data.
Cleared automatically by reading the I2C0SRX
register or flushing the FIFO.
Slave Transmit IRQ. Set at the end of a trans-
mission. Cleared automatically by writing to
the I2C0STX register.
Slave Transmit FIFO Underflow. Set automatically
if the slave transmit FIFO is underflowing.
Cleared automatically by writing to the
I2C0SSTA MMR.
0
Slave Transmit FIFO Empty. Set automatically if
the slave transmit FIFO is empty. Cleared
automatically by writing to the I2C0STX register.
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I2CxSRX Registers
I2CxADR Registers
Name
Address
Default Value
0x00
0x00
Access
Name
Address
Default Value
0x00
Access
R/W
I2C0SRX
I2C1SRX
0xFFFF0808
0xFFFF0908
R
R
I2C0ADR
I2C1ADR
0xFFFF081C
0xFFFF091C
0x00
R/W
I2CxSRX are receive registers for the slave channel.
I2CxADR are master address byte registers. The I2CxADR
value is the device address that the master wants to
communicate with. It automatically transmits at the start of a
master transfer sequence if there is no valid data in the
I2CxMTX register when the master enable bit is set.
I2CxSTX Registers
Name
Address
Default Value
0x00
0x00
Access
W
W
I2C0STX
I2C1STX
0xFFFF080C
0xFFFF090C
I2CxBYTE Registers
I2CxSTX are transmit registers for the slave channel.
Name
Address
Default Value
0x00
0x00
Access
R/W
R/W
I2CxMRX Registers
I2C0BYTE
I2C1BYTE
0xFFFF0824
0xFFFF0924
Name
Address
Default Value
0x00
0x00
Access
I2C0MRX
I2C1MRX
0xFFFF0810
0xFFFF0910
R
R
I2CxBYTE are broadcast byte registers. Data written to these
register do not go through the TxFIFO. This data is transmitted
at the start of a transfer sequence before the address. Once the
byte has been transmitted and acknowledged, the I2C expects
another byte written in I2CxBYTE or an address written to the
address register.
I2CxMRX are receive registers for the master channel.
I2CxMTX Registers
Name
Address
Default Value
0x00
0x00
Access
W
W
I2C0MTX
I2C1MTX
0xFFFF0814
0xFFFF0914
I2CxALT Registers
Name
Address
Default Value
0x00
0x00
Access
R/W
R/W
I2CxMTXare transmit registers for the master channel.
I2C0ALT
I2C1ALT
0xFFFF0828
0xFFFF0928
I2CxCNT Registers
Name
Address
Default Value
0x00
0x00
Access
R/W
R/W
I2CxALT are hardware general call ID registers used in slave
mode.
I2C0CNT
I2C1CNT
0xFFFF0818
0xFFFF0918
I2CxCFG Registers
I2CxCNT are 3-bit master receive data count registers. If a
master read transfer sequence is initiated, then the I2CxCNT
registers denote the number of bytes (−1) to be read from the
slave device. By default, this counter is 0, which corresponds to
1 byte expected.
Name
Address
Default Value
0x00
0x00
Access
R/W
R/W
I2C0CFG
I2C1CFG
0xFFFF082C
0xFFFF092C
I2CxCFG are configuration registers.
Rev. A | Page 69 of 92
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Table 62. I2C0CFG MMR Bit Descriptions
Bit
31:5
14
Description
Reserved. These bits should be written by the user as 0.
Enable Stop Interrupt. Set by the user to generate an interrupt upon receiving a stop condition and after receiving a valid start
condition + matching address. Cleared by the user to disable the generation of an interrupt upon receiving a stop condition.
13
12
11
10
9
Reserved.
Reserved.
Enable Stretch SCL (Holds SCL Low). Set by the user to stretch the SCL line. Cleared by the user to disable stretching of the SCL line.
Reserved.
Slave Tx FIFO Request Interrupt Enable. Set by the user to disable the slave Tx FIFO request interrupt. Cleared by the user to
generate an interrupt request just after the negative edge of the clock for the R/W bit. This allows the user to input data into the
slave Tx FIFO if it is empty. At 400 ksps and the core clock running at 41.78 MHz, the user has 45 clock cycles to take appropriate
action, taking interrupt latency into account.
8
7
6
5
4
General Call Status Bit Clear. Set by the user to clear the general call status bits. Cleared automatically by hardware after the general
call status bits have been cleared.
Master Serial Clock Enable Bit. Set by user to enable generation of the serial clock in master mode. Cleared by user to disable serial
clock in master mode.
Loop Back Enable Bit. Set by user to internally connect the transition to the reception to test user software. Cleared by user to
operate in normal mode.
Start Back-Off Disable Bit. Set by user in multimaster mode. If losing arbitration, the master immediately tries to retransmit. Cleared
by user to enable start back-off. After losing arbitration, the master waits before trying to retransmit.
Hardware General Call Enable. When this bit and the general call enable bit are set, and have received a general call (address 0x00)
and a data byte, the device checks the contents of the I2C0ALT against the receive register. If they match, then the device has
received a hardware general call. This is used if a device needs urgent attention from a master device without knowing which
master it needs to turn to. This is a "to whom it may concern" call. The ADuC7019/7020/7021/7022/7024/7025/7026/7027 watch for
these addresses. The device that requires attention embeds its own address into the message. All masters listen and the master
that knows how to handle the device contacts its slave and acts appropriately. The LSB of the I2C0ALT register should always be
written to a 1, as per I2C January 2000 specification.
3
General Call Enable Bit. Set this bit to enable the slave device to ACK an I2C general call, address 0x00 (write). The device then
recognizes a data bit. If it receives a 0x06 as the data byte, “Reset and write programmable part of slave address by hardware,” then
the I2C interface resets as per the I2C January 2000 specification. This command can be used to reset an entire I2C system. The
general call interrupt status bit sets on any general call. It is up to the user to take correct action by setting up the I2C interface after
a reset. If it receives a 0x04 as the data byte, “Write programmable part of slave address by hardware,” then the general call interrupt
status bit sets on any general call. It is up to the user to take correct action by reprogramming the device address.
2
1
0
Reserved.
Master Enable Bit. Set by user to enable the master I2C channel. Cleared by user to disable the master I2C channel.
Slave Enable Bit. Set by user to enable the slave I2C channel. A slave transfer sequence is monitored for the device address in
I2C0ID0, I2C0ID1, I2C0ID2, and I2C0ID3. If the device address is recognized, the part participates in the slave transfer sequence.
Cleared by user to disable the slave I2C channel.
I2CxDIV Registers
I2CxID0, I2CxID1, I2CxID2, and I2CxID3 are slave address
device ID registers of I2Cx.
Name
Address
Default Value
0x1F1F
0x1F1F
Access
R/W
R/W
I2C0DIV
I2C1DIV
0xFFFF0830
0xFFFF0930
I2CxCCNT Registers
Name
Address
Default Value
0x01
0x01
Access
R/W
R/W
I2CxDIV are the clock divider registers.
I2C0CCNT
I2C1CCNT
0xFFFF0848
0xFFFF0948
I2CxIDx Registers
Name
Address
Default Value
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
I2CxCCNT are 8-bit start/stop generation counters. They hold
off SDA low for start and stop conditions.
I2C0ID0
I2C0ID1
I2C0ID2
I2C0ID3
I2C1ID0
I2C1ID1
I2C1ID2
I2C1ID3
0xFFFF0838
0xFFFF083C
0xFFFF0840
0xFFFF0844
0xFFFF0938
0xFFFF093C
0xFFFF0940
0xFFFF0944
I2CxFSTA Registers
Name
Address
Default Value
0x0000
0x0000
Access
I2C0FSTA
I2C1FSTA
0xFFFF084C
0xFFFF094C
R
R
I2CxFSTA are FIFO status registers.
Rev. A | Page 70 of 92
ADuC7019/20/21/22/24/25/26/27
Table 63. I2C0FSTA MMR Bit Descriptions
In total, 30 GPIO pins are available on each ADuC7019/7020/
7021/7022/7024/7025/7026/7027 for the PLA. These include 16
input pins and 14 output pins, which need to be configured in
the GPxCON register as PLA pins before using the PLA. Note
that the comparator output is also included as one of the 16
input pins.
Bit
15:0
9
Value
Description
Reserved.
Master Transmit FIFO Flush. Set by the user to
flush the master Tx FIFO. Cleared automatically
once the master Tx FIFO is flushed. This bit also
flushes the slave receive FIFO.
8
Slave Transmit FIFO Flush. Set by the user to
flush the slave Tx FIFO. Cleared automatically
once the slave Tx FIFO is flushed.
Master Rx FIFO Status Bits.
FIFO Empty.
Byte Written to FIFO.
1 Byte in FIFO.
FIFO Full.
Master Tx FIFO Status Bits.
FIFO Empty.
Byte Written to FIFO.
1 Byte in FIFO.
FIFO Full.
Slave Rx FIFO Status Bits.
FIFO Empty.
Byte Written to FIFO.
1 Byte in FIFO.
FIFO Full.
Slave Tx FIFO Status Bits.
FIFO Empty.
Byte Written to FIFO.
1 Byte in FIFO.
The PLA is configured via a set of user MMRs. The output(s) of
the PLA can be routed to the internal interrupt system, to the
signal of the ADC, to a MMR, or to any of the 16
CONVSTART
7:6
PLA output pins.
00
01
10
11
The two blocks can be interconnected as follows:
•
Output of Element 15 (Block 1) can be fed back to Input 0 of
Mux 0 of Element 0 (Block 0)
5:4
3:2
1:0
00
01
10
11
•
Output of Element 7 (Block 0) can be fed back to the Input 0
of Mux 0 of Element 8 (Block 1)
Table 64. Element Input/Output
PLA Block 0
PLA Block 1
Input
P3.0
Element Input
Output
P1.7
P0.4
P0.5
P0.6
P0.7
P2.0
P2.1
P2.2
Element
Output
P4.0
P4.1
P4.2
P4.3
P4.4
P4.5
P4.6
P4.7
00
01
10
11
0
1
2
3
4
5
6
7
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P0.0
8
9
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
10
11
12
13
14
15
00
01
10
11
FIFO Full.
PLA MMRs Interface
The PLA peripheral interface consists of the 22 MMRs
described in this section.
PROGRAMMABLE LOGIC ARRAY (PLA)
Every ADuC7019/7020/7021/7022/7024/7025/7026/7027
integrates a fully programmable logic array (PLA), which
consists of two independent but interconnected PLA blocks.
Each block consists of eight PLA elements, which gives each
part a total of 16 PLA elements.
PLAELMx Registers
Name
Address
Default Value
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
Access
PLAELM0
PLAELM1
PLAELM2
PLAELM3
PLAELM4
PLAELM5
PLAELM6
PLAELM7
PLAELM8
PLAELM9
PLAELM10
PLAELM11
PLAELM12
PLAELM13
PLAELM14
PLAELM15
0xFFFF0B00
0xFFFF0B04
0xFFFF0B08
0xFFFF0B0C
0xFFFF0B10
0xFFFF0B14
0xFFFF0B18
0xFFFF0B1C
0xFFFF0B20
0xFFFF0B24
0xFFFF0B28
0xFFFF0B2C
0xFFFF0B30
0xFFFF0B34
0xFFFF0B38
0xFFFF0B3C
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Each PLA element contains a two-input look-up table that can
be configured to generate any logic output function based on
two inputs and a flip-flop. This is represented in Figure 62.
0
4
A
2
LOOK-UP
TABLE
B
3
1
Figure 62. PLA Element
Rev. A | Page 71 of 92
ADuC7019/20/21/22/24/25/26/27
PLAELMx are Element 0 to Element 15 control registers. They
configure the input and output mux of each element, select the
function in the look-up table, and bypass/use the flip-flop. See
Table 65 and Table 67.
PLACLK Register
Name
Address
Default Value
Access
PLACLK
0xFFFF0B40
0x00
R/W
PLACLK is a clock selection for the flip-flops of Block 0 and
clock selection for the flip-flops of Block 1.
Table 65. PLAELMx MMR Bit Descriptions
Bit
Value Description
Table 66. PLACLK MMR Bit Descriptions
31:11
10:9
8:7
Reserved.
Mux (0) Control (see Table 67).
Mux (1) Control (see Table 67).
Mux (2) Control. Set by user to select the
output of mux (0). Cleared by user to select
the bit value from PLADIN.
Mux (3) Control. Set by user to select the
input pin of the particular element. Cleared
by user to select the output of mux (1).
Bit
Value
Description
7
Reserved
6:4
Block 1 Clock Source Selection
GPIO Clock on P0.5
GPIO Clock on P0.0
GPIO Clock on P0.7
HCLK
OCLK (32.768 kHz)
Timer1 Overflow
Reserved
6
000
001
010
011
100
101
Other
5
4:1
Look-Up Table Control.
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0.
NOR.
3
Reserved
B AND NOT A.
NOT A.
A AND NOT B.
NOT B.
EXOR.
NAND.
AND.
EXNOR.
B.
NOT A OR B.
A.
A OR NOT B.
OR.
2:0
Block 0 Clock Source Selection
GPIO Clock on P0.5
GPIO Clock on P0.0
GPIO Clock on P0.7
HCLK
OCLK (32.768 kHz)
Timer1 Overflow
Reserved
000
001
010
011
100
101
Other
1.
0
Mux (4) Control. Set by user to bypass the flip-
flop. Cleared by user to select the flip-flop
(cleared by default).
Table 67. Feedback Configuration
Bit
Value
PLAELM0
Element 15
Element 2
Element 4
Element 6
Element 1
Element 3
Element 5
Element 7
PLAELM1 to PLAELM7
Element 0
Element 2
Element 4
Element 6
Element 1
Element 3
Element 5
Element 7
PLAELM8
PLAELM9 to PLAELM15
10:9
00
01
10
11
00
01
10
11
Element 7
Element 10
Element 12
Element 14
Element 9
Element 11
Element 13
Element 15
Element 8
Element 10
Element 12
Element 14
Element 9
Element 11
Element 13
Element 15
8:7
Rev. A | Page 72 of 92
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PLAIRQ Register
PLADIN Register
Name
Address
Default Value
Access
Name
Address
Default Value
Access
PLAIRQ
0xFFFF0B44
0x00000000
R/W
PLADIN
0xFFFF0B4C
0x00000000
R/W
PLAIRQ enables IRQ0 and/or IRQ1 and selects the source of
the IRQ.
PLADIN is a data input MMR for PLA.
Table 70. PLADIN MMR Bit Descriptions
Table 68. PLAIRQ MMR Bit Descriptions
Bit
Description
Bit
Value
Description
31:16
15:0
Reserved
Input Bit to Element 15 to Element 0
15:13
12
Reserved.
PLA IRQ1 Enable Bit. Set by user to enable
IRQ1 output from PLA. Cleared by user to
disable IRQ1 output from PLA.
PLADOUT Register
Name
Address
Default Value
Access
11:8
PLA IRQ1 Source.
PLA Element 0.
PLA Element 1.
PLA Element 15.
Reserved.
PLA IRQ0 Enable Bit. Set by user to enable
IRQ0 output from PLA. Cleared by user to
disable IRQ0 output from PLA.
PLA IRQ0 Source.
PLA Element 0.
PLA Element 1.
PLA Element 15.
PLADOUT
0xFFFF0B50
0x00000000
R
0000
0001
1111
PLADOUT is a data output MMR for PLA. This register is
always updated.
7:5
4
Table 71. PLADOUT MMR Bit Descriptions
Bit
Description
31:16
15:0
Reserved
Output Bit from Element 15 to Element 0
3:0
0000
0001
1111
PLALCK Register
Name
PLALCK
Address
Default Value
Access
0xFFFF0B54
0x00
W
PLALCK is a PLA lock option. Bit 0 is written only once. When
set, it does not allow modifying any of the PLA MMR, except
PLADIN. A PLA tool is provided in the development system to
easily configure the PLA.
PLAADC Register
Name
Address
Default Value
Access
PLAADC
0xFFFF0B48
0x00000000
R/W
PLAADC is a PLA source from the ADC start conversion
signal.
Table 69. PLAADC MMR Bit Descriptions
Bit
31:5
4
Value Description
Reserved.
ADC Start Conversion Enable Bit. Set by user
to enable ADC start conversion from PLA.
Cleared by user to disable ADC start
conversion from PLA.
3:0
ADC Start Conversion Source.
PLA Element 0.
PLA Element 1.
0000
0001
1111
PLA Element 15.
Rev. A | Page 73 of 92
ADuC7019/20/21/22/24/25/26/27
PROCESSOR REFERENCE PERIPHERALS
IRQSTA Register
INTERRUPT SYSTEM
Name
Address
Default Value
Access
There are 23 interrupt sources on the ADuC7019/7020/
7021/7022/7024/7025/7026/7027 that are controlled by the
interrupt controller. Most interrupts are generated from the on-
chip peripherals, such as ADC and UART. Four additional
interrupt sources are generated from external interrupt request
pins, IRQ0, IRQ1, IRQ2, and IRQ3. The ARM7TDMI CPU core
only recognizes interrupts as one of two types, a normal
interrupt request IRQ or a fast interrupt request FIQ. All the
interrupts can be masked separately.
IRQSTA
0xFFFF0000
0x00000000
R
IRQSTA (read-only register) provides the current enabled IRQ
source status. When set to 1 that source should generate an
active IRQ request to the ARM7TDMI core. There is no priority
encoder or interrupt vector generation. This function is
implemented in software in a common interrupt handler
routine. All 32 bits are logically OR’ed to create the IRQ signal
to the ARM7TDMI core.
IRQSIG Register
The control and configuration of the interrupt system is
managed through nine interrupt-related registers, four
dedicated to IRQ, and four dedicated to FIQ. An additional
MMR is used to select the programmed interrupt source. The
bits in each IRQ and FIQ registers (except for Bit 23) represent
the same interrupt source as described in Table 72.
Name
Address
Default Value
Access
IRQSIG
0xFFFF0004
0x00XXX000
R
IRQSIG reflects the status of the different IRQ sources. If a
peripheral generates an IRQ signal, then the corresponding bit
in the IRQSIG is set; otherwise it is cleared. The IRQSIG bits are
cleared when the interrupt in the particular peripheral is
cleared. All IRQ sources can be masked in the IRQEN MMR.
IRQSIG is read-only.
Table 72. IRQ/FIQ MMRs Bit Description
Bit
Description
All Interrupts OR’ed
SWI
0
1
IRQEN Register
2
Timer0
Name
Address
Default Value
Access
3
Timer1
IRQEN
0xFFFF0008
0x00000000
R/W
4
5
6
7
Wake-Up Timer – Timer2
Watchdog Timer – Timer3
Flash Control
ADC Channel
PLL Lock
IRQEN provides the value of the current enable mask. When bit
is set to 1, the source request is enabled to create an IRQ
exception. When bit is set to 0, the source request is disabled or
masked, which does not create an IRQ exception.
8
9
I2C0 Slave
IRQCLR Register
10
11
12
13
14
15
16
17
18
19
20
21
22
23
I2C0 Master
I2C1 Master
SPI Slave
SPI Master
UART
External IRQ0
Comparator
PSM
External IRQ1
PLA IRQ0
Name
Address
Default Value
Access
IRQCLR
0xFFFF000C
0x00000000
W
IRQCLR (write-only register) clears the IRQEN register in
order to mask an interrupt source. Each bit set to 1 clears the
corresponding bit in the IRQEN register without affecting the
remaining bits. The pair of registers, IRQEN and IRQCLR,
independently manipulates the enable mask without requiring
an atomic read-modify-write.
FIQ
PLA IRQ1
The fast interrupt request (FIQ) is the exception signal to enter
the FIQ mode of the processor. It is provided to service data
transfer or communication channel tasks with low latency. The
FIQ interface is identical to the IRQ interface providing the
second-level interrupt (highest priority). Four 32-bit registers
are dedicated to FIQ: FIQSIG, FIQEN, FIQCLR, and FIQSTA.
External IRQ2
External IRQ3
PWM Trip (IRQ only)/ PWM Sync (FIQ only)
IRQ
The interrupt request (IRQ) is the exception signal to enter the
IRQ mode of the processor. It is used to service general-
purpose interrupt handling of internal and external events.
The four 32-bit registers dedicated to IRQ are: IRQSTA,
IRQSIG, IRQEN, and IRQCLR.
Rev. A | Page 74 of 92
ADuC7019/20/21/22/24/25/26/27
FIQSTA Register
TIMERS
Name
Address
Default Value
Access
The ADuC7019/7020/7021/7022/7024/7025/7026/7027 have
four general-purpose timer/counters:
FIQSTA
0xFFFF0100
0x00000000
R
•
•
•
•
Timer0
FIQSIG Register
Name
Address
Default Value
Access
Timer1
FIQSIG
0xFFFF0104
0x00XXX000
R
Timer2 or Wake-Up Timer
Timer3 or Watchdog Timer
FIQEN Register
Name
Address
Default Value
Access
FIQEN
0xFFFF0108
0x00000000
R/W
These four timers in their normal mode of operation can be
either free-running or periodic.
FIQCLR Register
Name
Address
Default Value
Access
In free-running mode, the counter decreases from the
maximum value until zero scale and starts again at the
minimum value. (It also increases from the minimum value
until full scale and starts again at the maximum value.)
FIQCLR
0xFFFF010C
0x00000000
W
Bit 31 to Bit 1 of FIQSTA are logically OR’ed to create the FIQ
signal to the core and Bit 0 of both the FIQ and IRQ registers
(FIQ source).
In periodic mode, the counter decrements/increments from the
value in the load register (T×LD MMR) until zero/full scale and
starts again at the value stored in the load register.
The logic for FIQEN and FIQCLR does not allow an interrupt
source to be enabled in both IRQ and FIQ masks. A bit set to 1
in FIQEN does, as a side effect, clear the same bit in IRQEN.
Also, a bit set to 1 in IRQEN does, as a side effect, clear the
same bit in FIQEN. An interrupt source can be disabled in both
IRQEN and FIQEN masks.
The timer interval is calculated as follow:
T × LD
× prescaler
Interval =
source clock
The value of a counter can be read at any time by accessing
its value register (T×VAL). Note that when a timer is being
clocked from a clock other than core clock, an incorrect value
could be read (due to asynchronous clock system). In this
configuration, T×VAL should always be read twice. If the two
readings are different, then it should be read a third time to
get the correct value.
Programmed Interrupts
Because the programmed interrupts are nonmaskable, they are
controlled by another register, SWICFG, which simultaneously
writes into the IRQSTA and IRQSIG registers, and/or the
FIQSTA and FIQSIG registers. The 32-bit register dedicated to
software interrupt is SWICFG described in Table 73. This MMR
allows the control of programmed source interrupt.
Timers are started by writing in the control register of the
corresponding timer (T×CON).
SWICFG Register
Name
Address
Default Value
Access
SWICFG
0xFFFF0010
0x00000000
W
In normal mode, an IRQ is generated each time the value of the
counter reaches zero when counting down. It is also generated
each time the counter value reaches full scale when counting
up. An IRQ can be cleared by writing any value to clear the
register of that particular timer (T×CLRI).
Table 73. SWICFG MMR Bit Descriptions
Bit
31:3
2
Description
Reserved.
Programmed Interrupt-FIQ. Setting/Clearing this bit
corresponds with setting/clearing Bit 1 of FIQSTA
and FIQSIG.
Programmed Interrupt-IRQ. Setting/Clearing this bit
corresponds with setting/clearing Bit 1 of IRQSTA
and IRQSIG.
When using an asynchronous clock-to-clock timer, the interrupt
in the timer block could take more time to clear than the time it
takes for the code in the interrupt routine to execute. Ensure that
the interrupt signal is cleared before leaving the interrupt service
routine. This can be done by checking the IRQSTA MMR.
1
0
Reserved.
Note that any interrupt signal must be active for at least the
equivalent of the interrupt latency time, to be detected by the
interrupt controller and to be detected by the user in the
IRQSTA/FIQSTA register.
Rev. A | Page 75 of 92
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Timer0 (RTOS Timer)
T0CLRI Register
Name
Address
Default Value
Access
Timer0 is a general-purpose, 16-bit timer (count-down) with a
programmable prescaler (see Figure 63). The prescaler source is
the core clock frequency (HCLK) and can be scaled by factors
of 1, 16, or 256.
T0CLRI
0xFFFF030C
0xFF
W
T0CLRI is an 8-bit register. Writing any value to this register
clears the interrupt.
16-BIT
LOAD
Timer1 (General-Purpose Timer)
Timer1 is a general-purpose, 32-bit timer (count down or count
up) with a programmable prescaler. The source can be the
32 kHz external crystal, the core clock frequency, or an external
GPIO, P1.0 or P0.6. This source can be scaled by a factor of 1,
16, 256, or 32768.
16-BIT
PRESCALER
/1, 16 OR 256
TIMER0 IRQ
DOWN
HCLK
COUNTER
ADC CONVERSION
TIMER0
VALUE
Figure 63. Timer0 Block Diagram
The counter can be formatted as a standard 32-bit value or as
Hours: Minutes: Seconds: Hundredths.
Timer0’s interface consists of four MMRS: T0LD, T0VAL,
T0CON, and T0CLRI.
Timer1 has a capture register (T1CAP), which can be triggered
by a selected IRQ source initial assertion. This feature can be
used to determine the assertion of an event more accurately
than the precision allowed by the RTOS timer when the IRQ is
serviced.
T0LD Register
Name
Address
Default Value
Access
T0LD
0xFFFF0300
0x0000
R/W
T0LD is a 16-bit load register.
Timer1 can be used to start ADC conversions as shown in the
block diagram in Figure 64.
T0VAL Register
Name
Address
Default Value
Access
32-BIT
LOAD
T0VAL
0xFFFF0304
0xFFFF
R
T0VAL is a 16-bit read-only register representing the current
state of the counter.
32kHz OSCILLATOR
PRESCALER
/1, 16, 256
OR 32768
32-BIT
UP/DOWN
COUNTER
HCLK
P0.6
P1.0
TIMER1 IRQ
ADC CONVERSION
T0CON Register
TIMER1
VALUE
Name
Address
Default Value
Access
T0CON
0xFFFF0308
0x0000
R/W
CAPTURE
IRQ[31:0]
T0CON is the configuration MMR described in Table 74.
Figure 64. Timer1 Block Diagram
Table 74. T0CON MMR Bit Descriptions
Timer1’s interface consists of five MMRS: T1LD, T1VAL,
T1CON, T1CLRI, and T1CAP.
Bit
31:8
7
Value Description
Reserved.
Timer0 Enable Bit. Set by user to enable Timer0.
T1LD Register
Cleared by user to disable Timer0 by default.
Name
Address
Default Value
Access
6
Timer0 Mode. Set by user to operate in
periodic mode. Cleared by user to operate in
free-running mode. Default mode.
T1LD
0xFFFF0320
0x00000000
R/W
T1LD is a 16-bit load register.
5:4
3:2
Reserved.
Prescale.
T1VAL Register
Name
Address
Default Value
Access
00
01
10
11
Core Clock/1. Default value.
Core Clock/16.
Core Clock/256.
Undefined. Equivalent to 00.
Reserved.
T1VAL
0xFFFF0324
0xFFFFFFFF
R
T1VAL is a 16-bit read-only register that represents the current
state of the counter.
1:0
T1CON Register
Name
Address
Default Value
Access
T1CON
0xFFFF0328
0x0000
R/W
T1CON is the configuration MMR described in Table 75.
Rev. A | Page 76 of 92
ADuC7019/20/21/22/24/25/26/27
Table 75. T1CON MMR Bit Descriptions
T1CAP Register
Bit
Value Description
Name
Address
Default Value
Access
31:18
17
Reserved.
T1CAP
0xFFFF0330
0x00000000
R
Event Select Bit. Set by user to enable time
capture of an event. Cleared by user to
disable time capture of an event
Event Select Range, 0 to 31. These events are
as described in Table 72. All events are offset
by two, that is, event 2 in Table 72 becomes
event zero for the purposes of Timer1.
Clock Select.
Core Clock (HCLK).
External 32.768 kHz Crystal.
P1.0 Raising Edge Triggered.
P0.6 Raising Edge Triggered.
Count Up. Set by user for Timer1 to count up.
Cleared by user for Timer1 to count down by
default.
Timer1 enable bit. Set by user to enable
Timer1. Cleared by user to disable Timer1 by
default.
Timer1 Mode. Set by user to operate in
periodic mode. Cleared by user to operate in
free-running mode. Default mode.
T1CAP is a 32-bit register. It holds the value contained in
T1VAL when a particular event occurred. This event must be
selected in T1CON.
16:12
11:9
Timer2 (Wake-Up Timer)
Timer2 is a 32-bit wake-up timer (count-down or count-up)
with a programmable prescaler. The source can be the 32 kHz
external crystal, the core clock frequency, or the internal 32 kHz
oscillator. The clock source can be scaled by a factor of 1, 16,
256, or 32,768. The wake-up timer continues to run when the
core clock is disabled.
000
001
010
011
8
7
6
The counter can be formatted as plain 32-bit value or as
Hours: Minutes: Seconds: Hundredths.
Timer2 can be used to start ADC conversions as shown in the
block diagram Figure 65.
32-BIT
LOAD
INTERNAL
OSCILLATOR
5:4
00
01
10
11
3:0
Format.
Binary.
Reserved.
PRESCALER
/1, 16, 256
OR 32768
32-BIT
UP/DOWN
COUNTER
EXTERNAL
CRYSTAL
TIMER2 IRQ
HCLK
Hr:Min:Sec:Hundredths (23 hours to 0 hour).
Hr:Min:Sec:Hundredths (255 hours to 0 hour).
Prescale:
TIMER2
VALUE
Figure 65. Timer2 Block Diagram
0000
0100
1000
1111
Source Clock/1.
Source Clock/16.
Source Clock/256.
Source Clock/32768.
Timer2 interface consists in four MMRS: T2LD, T2VAL,
T2CON, and T2CLRI.
T2LD Register
Name
Address
Default Value
Access
T2LD
0xFFFF0340
0x00000000
R/W
T1CLRI Register
Name
Address
Default Value
Access
T2LD is a 16-bit register load register.
T1CLRI
0xFFFF032C
0xFF
W
T2VAL Register
T1CLRI is an 8-bit register. Writing any value to this register
clears the Timer1 interrupt.
Name
Address
Default Value
Access
T2VAL
0xFFFF0344
0xFFFFFFFF
R
T2VAL is a 16-bit read-only register that represents the current
state of the counter.
Rev. A | Page 77 of 92
ADuC7019/20/21/22/24/25/26/27
16-BIT
LOAD
T2CON Register
Name
Address
Default Value
Access
WATCHDOG
RESET
16-BIT
UP/DOWN
COUNTER
T2CON
0xFFFF0348
0x0000
R/W
PRESCALER
/1, 16 OR 256
32.768kHz
TIMER3 IRQ
T2CON is the configuration MMR described in Table 76.
Table 76. T2CON MMR Bit Descriptions
TIMER3
VALUE
Bit
Value Description
Figure 66. Timer3 Block Diagram
31:11
10:9
Reserved.
Clock Source.
Watchdog Mode
00
01
10
11
External Crystal.
External Crystal.
Internal Oscillator.
Core Clock (41 MHz/2CD).
Watchdog mode is entered by setting Bit 5 in T3CON MMR.
Timer3 decreases from the value present in T3LD register until
zero. T3LD is used as timeout. The maximum timeout can be
512 seconds using the prescaler/256, and full-scale in T3LD.
Timer3 is clocked by the internal 32 kHz crystal when
operating in the watchdog mode. Note that to enter watchdog
mode successfully, Bit 5 in the T3CON MMR must be set after
writing to the T3LD MMR.
8
Count Up. Set by user for Timer2 to count up.
Cleared by user for Timer2 to count down by
default.
7
6
Timer2 Enable Bit. Set by user to enable Timer2.
Cleared by user to disable Timer2 by default.
Timer2 Mode. Set by user to operate in
periodic mode. Cleared by user to operate in
free-running mode. Default mode.
If the timer reaches 0, a reset or an interrupt occurs, depending
on Bit 1 in T3CON register. To avoid reset or interrupt, any value
must be written to T3ICLR before the expiration period. This
reloads the counter with T3LD and begins a new timeout period.
5:4
Format.
00
01
10
11
Binary.
Reserved.
As soonas watchdog mode is entered, T3LD and T3CON are
write-protected. These two registers cannot be modified until a
reset clears the watchdog enable bit, which causes Timer3 to
exit watchdog mode.
Hr:Min:Sec:Hundredths (23 hours to 0 hour).
Hr:Min:Sec:Hundredths (255 hours to 0 hour).
Prescale:
3:0
0000
0100
1000
1111
Source Clock/1 by Default.
Source Clock/16.
Source Clock/256 Expected for Format 2 and 3.
Source Clock/32768.
The Timer3 interface consists of four MMRS: T3LD, T3VAL,
T3CON, and T3CLRI.
T3LD Register
Name
Address
Default Value
Access
T2CLRI Register
T3LD
0xFFFF0360
0x0000
R/W
Name
Address
Default Value
Access
T3LD is a 16-bit register load register.
T2CLRI
0xFFFF034C
0xFF
W
T2CLRI is an 8-bit register. Writing any value to this register
clears the Timer2 interrupt.
T3VAL Register
Name
Address
Default Value
Access
T3VAL
0xFFFF0364
0xFFFF
R
Timer3 (Watchdog Time)
T3VAL is a 16-bit read-only register that represents the current
state of the counter.
Timer3 has two modes of operation, normal mode and
watchdog mode. The watchdog timer is used to recover from
an illegal software state. Once enabled, it requires periodic
servicing to prevent it from forcing a reset of the processor.
T3CON Register
Name
Address
Default Value
Access
T3CON
0xFFFF0368
0x0000
R/W
Normal Mode
T3CON is the configuration MMR described in Table 77.
Timer3 in normal mode is identical to Timer0, except for the
clock source and the count-up functionality. The clock source is
32 kHz from the PLL and can be scaled by a factor of 1, 16, or
256 (see Figure 66).
Rev. A | Page 78 of 92
ADuC7019/20/21/22/24/25/26/27
Table 77. T3CON MMR Bit Descriptions
The value 0×00 should not be used as an initial seed due to the
properties of the polynomial. The value 0×00 is always
guaranteed to force an immediate reset. The value of the LFSR
cannot be read; it must be tracked/generated in software.
Bit
31:9
8
Value
Description
Reserved.
Count Up. Set by user for Timer3 to count up.
Cleared by user for Timer3 to count down by
default.
Example of a sequence:
7
Timer3 Enable Bit. Set by user to enable
Timer3. Cleared by user to disable Timer3 by
default.
1. Enter initial seed, 0×AA, in T3ICLR before starting Timer3
in watchdog mode.
2. Enter 0×AA in T3ICLR; Timer3 is reloaded.
3. Enter 0×37 in T3ICLR; Timer3 is reloaded.
4. Enter 0×6E in T3ICLR; Timer3 is reloaded.
5. Enter 0×66. 0×DC was expected; the watchdog reset the chip.
6
Timer3 Mode. Set by user to operate in
periodic mode. Cleared by user to operate
in free-running mode. Default mode.
Watchdog Mode Enable Bit. Set by user to
enable watchdog mode. Cleared by user to
disable watchdog mode by default.
Secure Clear Bit. Set by user to use the secure
clear option. Cleared by user to disable the
secure clear option by default.
Prescale:
Source Clock/1 by Default.
Source Clock/16.
Source Clock/256.
Undefined. Equivalent to 00.
Watchdog IRQ Option Bit. Set by user to
produce an IRQ instead of a reset when
the watchdog reaches 0. Cleared by user to
disable the IRQ option.
5
EXTERNAL MEMORY INTERFACING
4
The ADuC7026 and ADuC7027 are the only models in their
series that feature an external memory interface The external
memory interface requires a larger number of pins. This is why
it is only available on larger pin count packages. The XMCFG
MMR must be set to 1 to use the external port.
3:2
00
01
10
11
Although 32-bit addresses are supported internally, only the
lower 16 bits of the address are on external pins.
1
0
The memory interface can address up to four 128 kB of
asynchronous memory (SRAM or/and EEPROM).
Reserved.
The pins required for interfacing to an external memory are
shown in Table 78.
T3CLRI Register
Table 78. External Memory Interfacing Pins
Name
Address
Default Value
Access
Pin
Function
T3CLRI
0xFFFF036C
0x00
W
AD[15:0]
A16
MS[3:0]
WR
Address/Data Bus
Extended Addressing for 8-Bit Memory Only
Memory Select Pins
Write Strobe
T3CLRI is an 8-bit register. Writing any value to this register
clears the Timer3 interrupt in normal mode or resets a new
timeout period in watchdog mode.
RS
Read Strobe
Secure Clear Bit (Watchdog Mode Only)
AE
BHE, BLE
Address Latch Enable
Byte Write Capability
The secure clear bit is provided for a higher level of protection.
When set, a specific sequential value must be written to T3ICLR
to avoid a watchdog reset. The value is a sequence generated by
the 8-bit linear feedback shift register (LFSR) polynomial = X8
+ X6 + X5 + X + 1 as shown in Figure 67.
There are four external memory regions available as described
in Table 79. Associated with each region are the pins MS[3:0].
These signals allow access to the particular region of external
memory. The size of each memory region can be 128 kB maxi-
mum, 64 k × 16 or 128 k × 8. To access 128 k with an 8-bit
memory, an extra address line (A16) is provided. (See the
example in Figure 68.) The four regions are configured
independently.
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
7
6
5
4
3
2
1
0
CLOCK
Figure 67. 8-Bit LFSR
Table 79. Memory Regions
Address Start
0x10000000
0x20000000
0x30000000
0x40000000
Address End
0x1000FFFF
0x2000FFFF
0x3000FFFF
0x4000FFFF
Contents
The initial value or seed is written to T3ICLR before entering
watchdog mode. After entering watchdog mode, a write to
T3ICLR must match this expected value. If it matches, the
LFSR is advanced to the next state when the counter reload
happens. If it fails to match the expected state, reset is
immediately generated, even if the count has not yet expired.
External Memory 0
External Memory 1
External Memory 2
External Memory 3
Each external memory region can be controlled through three
MMRs: XMCFG, XMxCON, and XMxPAR.
Rev. A | Page 79 of 92
ADuC7019/20/21/22/24/25/26/27
EPROM
64k × 16-BIT
ADuC7026/
XMxPAR Registers
ADuC7027
Name
Address
Default Value
0x70FF
0x70FF
0x70FF
0x70FF
Access
R/W
R/W
R/W
R/W
A16
XM0PAR
XM1PAR
XM2PAR
XM3PAR
0xFFFFF020
0xFFFFF024
0xFFFFF028
0xFFFFF02C
AD15:0
D0–D15
A0:15
LATCH
AE
MS0
MS1
CS
XMxPAR are registers that define the protocol used for
accessing the external memory for each memory region.
WS
RS
WE
OE
Table 81. XMxPAR MMR Bit Descriptions
Bit
Description
RAM
128k × 8-BIT
15
Enable Byte Write Strobe. This bit is only used for two, 8-
bit memory sharing the same memory region. Set by
the user to gate the A0 output with the WR output. This
allows byte write capability without using BHE and BLE
signals. Cleared by user to use BHE and BLE signals.
Number of wait states on the address latch enable
strobe.
D0–D7
A16
A0:15
CS
WE
OE
14:12
Figure 68. Interfacing to External EPROM/RAM
11
10
Reserved.
Extra Address Hold Time. Set by the user to disable extra
hold time. Cleared by the user to enable one clock cycle
of hold on the address in read and write.
XMCFG Register
Name
Address
Default Value
Access
XMCFG
0xFFFFF000
0x00
R/W
9
8
Extra bus transition time on read. Set by the user to disable
extra bus transition time. Cleared by the user to enable
one extra clock before and after the read strobe (RS).
Extra Bus Transition Time On Write. Set by the user to
disable extra bus transition time. Cleared by the user to
enable one extra clock before and after the write strobe
(WS).
Number of Write Wait States. Select the number of wait
states added to the length of the WS pulse. 0x0 is 1clock;
0xF is 16 clock cycles (default value).
Number of Read Wait States. Select the number of wait
states added to the length of the RS pulse. 0x0 is 1 clock;
0xF is 16 clock cycles (default value).
XMCFG is set to 1 to enable external memory access. This must
be set to 1 before any port pins function as external memory
access pins. The port pins must also be individually enabled via
the GPxCON MMR.
XMxCON Registers
Name
7:4
3:0
Address
Default Value
0x00
0x00
0x00
0x00
Access
R/W
R/W
R/W
R/W
XM0CON
XM1CON
XM2CON
XM3CON
0xFFFFF010
0xFFFFF014
0xFFFFF018
0xFFFFF01C
Figure 69, Figure 70, Figure 71, and Figure 72 show the timing
for a read cycle, a read cycle with address hold and bus turn
cycles, a write cycle with address and write hold cycles, and a
write cycle with wait sates, respectively.
XMxCON are the control registers for each memory region.
They allow the enabling/disabling of a memory region and
control the data bus width of the memory region.
Table 80. XMxCON MMR Bit Descriptions
Bit Description
1
Selects Between 8-Bit and 16-Bit Data Bus Width. Set by the
user to select a 16-bit data bus. Cleared by the user to
select an 8-bit data bus.
0
Enables Memory Region. Set by the user to enable memory
region. Cleared by the user to disable the memory region.
Rev. A | Page 80 of 92
ADuC7019/20/21/22/24/25/26/27
MCLK
AD16:0
MSx
ADDRESS
DATA
AE
RS
Figure 69. External Memory Read Cycle
MCLK
AD16:0
ADDRESS
DATA
EXTRA ADDRESS
HOLD TIME
(BIT-10)
MSx
AE
RS
BUS TURN OUT CYCLE
(BIT-9)
BUS TURN OUT CYCLE
(BIT-9)
Figure 70. External Memory Read Cycle with Address Hold and Bus Turn Cycles
Rev. A | Page 81 of 92
ADuC7019/20/21/22/24/25/26/27
MCLK
AD16:0
ADDRESS
DATA
EXTRA ADDRESS
HOLD TIME
(BIT-10)
MSx
AE
WS
WRITE HOLD ADDRESS
AND DATA CYCLES
(BIT-8)
WRITE HOLD ADDRESS
AND DATA CYCLES
(BIT-8)
Figure 71. External Memory Write Cycle with Address and Write Hold Cycles
MCLK
AD16:0
ADDRESS
DATA
MSx
AE
1 ADDRESS WAIT STATE
(BIT-14 TO BIT-12)
WS
1 WRITE STROBE WAIT STATE
(BIT-7 TO BIT-4)
Figure 72. External Memory Write Cycle with Wait States
Rev. A | Page 82 of 92
ADuC7019/20/21/22/24/25/26/27
HARDWARE DESIGN CONSIDERATIONS
Notice that in both Figure 73 and Figure 74, a large value
(10 μF) reservoir capacitor sits on IOVDD, and a separate 10 μF
capacitor sits on AVDD. In addition, local small-value (0.1 μF)
capacitors are located at each AVDD and IOVDD pin of the chip.
As per standard design practice, be sure to include all of these
capacitors and ensure the smaller capacitors are close to each
AVDD pin with trace lengths as short as possible. Connect the
ground terminal of each of these capacitors directly to the
underlying ground plane. Finally, note that the analog and
digital ground pins on the ADuC7019/7020/7021/7022/
7024/7025/7026/7027 must be referenced to the same system
ground reference point at all times.
POWER SUPPLIES
The ADuC7019/7020/7021/7022/7024/7025/7026/7027
operational power supply voltage range is 2.7 V to 3.6 V.
Separate analog and digital power supply pins (AVDD and
IOVDD, respectively) allow AVDD to be kept relatively free of
noisy digital signals often present on the system IOVDD line. In
this mode, the part can also operate with split supplies, that is,
using different voltage levels for each supply. For example, the
system can be designed to operate with an IOVDD voltage level
of 3.3 V while the AVDD level can be at 3 V, or vice versa. A
typical split supply configuration is shown in Figure 73.
DIGITAL
SUPPLY
ANALOG
SUPPLY
Linear Voltage Regulator
+
–
+
–
10
μF
10μF
Each ADuC7019/7020/7021/7022/7024/7025/7026/7027
requires a single 3.3 V supply, but the core logic requires a 2.6 V
supply. An on-chip linear regulator generates the 2.6 V from
IOVDD for the core logic. LVDD Pin 21 is the 2.6 V supply for the
core logic. An external compensation capacitor of 0.47 μF must
be connected between LVDD and DGND (as close as possible to
these pins) to act as a tank of charge as shown Figure 75.
ADuC7026
73
74
75
26
54
AV
DD
DD
IOV
DD
DACV
0.1
μF
0.1μF
8
GND
REF
70
71
67
DACGND
AGND
25
53
IOGND
REFGND
ADuC7026
Figure 73. External Dual Supply Connections
27
LV
DD
As an alternative to providing two separate power supplies, the
user can reduce noise on AVDD by placing a small series resistor
and/or ferrite bead between AVDD and IOVDD, and then
decouple AVDD separately to ground. An example of this
configuration is shown in Figure 74. With this configuration,
other analog circuitry (such as op amps, voltage reference, and
others) can be powered from the AVDD supply line as well.
0.47μF
28
DGND
Figure 75. Voltage Regulator Connections
BEAD
DIGITAL SUPPLY
1.6Ω
The LVDD pin should not be used for any other chip. It is also
recommended to use excellent power supply decoupling on
IOVDD to help improve line regulation performance of the on-
chip voltage regulator.
10μF
10μF
+
–
ADuC7026
73
26
54
AV
74
75
DD
DD
IOV
DD
DACV
0.1μF
0.1μF
8
GND
REF
DACGND 70
71
67
25
53
AGND
IOGND
REFGND
Figure 74. External Single Supply Connections
Rev. A | Page 83 of 92
ADuC7019/20/21/22/24/25/26/27
For example, do not power components on the analog side, as
seen in Figure 76b, with IOVDD because that would force return
currents from IOVDD to flow through AGND. Also, avoid digital
currents flowing under analog circuitry, which could occur if a
noisy digital chip is placed on the left half of the board shown in
Figure 76c. If possible, avoid large discontinuities in the ground
plane(s) (such as those formed by a long trace on the same
layer), because they force return signals to travel a longer path.
In addition, make all connections to the ground plane directly,
with little or no trace separating the pin from its via to ground.
GROUNDING AND BOARD LAYOUT
RECOMMENDATIONS
As with all high resolution data converters, special attention
must be paid to grounding and PC board layout of
ADuC7019/7020/7021/7022/7024/7025/7026/7027-based
designs in order to achieve optimum performance from the
ADCs and DAC.
Although the ADuC7019/7020/7021/7022/7024/7025/7026/7027
have separate pins for analog and digital ground (AGND and
IOGND), the user must not tie these to two separate ground
planes unless the two ground planes are connected very close to
the part. This is illustrated in the simplified example shown in
Figure 76a. In systems where digital and analog ground planes
are connected together somewhere else (at the system’s power
supply, for example), the planes cannot be reconnected near the
part, because a ground loop would result. In these cases, tie all the
ADuC7019/7020/7021/7022/7024/7025/7026/7027’s AGND and
IOGND pins to the analog ground plane, as illustrated in Figure
76b. In systems with only one ground plane, ensure that the
digital and analog components are physically separated onto
separate halves of the board so that digital return currents do not
flow near analog circuitry and vice versa. The ADuC7019/7020/
7021/7022/7024/7025/7026/7027 can then be placed between the
digital and analog sections, as illustrated in Figure 76c.
When connecting fast logic signals (rise/fall time < 5 ns) to any
of the ADuC7019/7020/7021/7022/7024/7025/7026/7027’s
digital inputs, add a series resistor to each relevant line to keep
rise and fall times longer than 5 ns at the ADuC7019/7020/
7021/7022/7024/7025/7026/7027 input pins. A value of 100 Ω
or 200 Ω is usually sufficient enough to prevent high speed
signals from coupling capacitively into the part and affecting
the accuracy of ADC conversions.
CLOCK OSCILLATOR
The clock source for the ADuC7019/7020/7021/7022/
7024/7025/7026/7027 can be generated by the internal PLL or
by an external clock input. To use the internal PLL, connect a
32.768 kHz parallel resonant crystal between XCLKI and
XCLKO, and connect a capacitor from each pin to ground as
shown Figure 77. This crystal allows the PLL to lock correctly to
give a frequency of 41.78 MHz. If no external crystal is present,
the internal oscillator is used to give a frequency of 41.78 MHz
±3ꢀ typically.
PLACE ANALOG
COMPONENTS HERE
PLACE DIGITAL
COMPONENTS HERE
a.
ADuC7026
AGND
DGND
XCLKI
45
12pF
32.768kHz
TO
INTERNAL
PLL
44
12pF
XCLKO
PLACE ANALOG
COMPONENTS
HERE
PLACE DIGITAL
COMPONENTS HERE
b.
Figure 77. External Parallel Resonant Crystal Connections
AGND
DGND
To use an external source clock input instead of the PLL (see
Figure 78), Bit 1 and Bit 0 of PLLCON must be modified.The
external clock uses P0.7 and XCLK.
ADuC7026
PLACE ANALOG
COMPONENTS HERE
PLACE DIGITAL
COMPONENTS HERE
XCLKO
c.
XCLKI
DGND
EXTERNAL
CLOCK
SOURCE
TO
FREQUENCY
DIVIDER
XCLK
Figure 76. System Grounding Schemes
Figure 78. Connecting an External Clock Source
In all of these scenarios, and in more complicated real-life
applications, pay particular attention to the flow of current from
the supplies and back to ground. Make sure the return paths for
all currents are as close as possible to the paths the currents
took to reach their destinations.
Using an external clock source, the ADuC7019/7020/7021/
7022/7024/7025/7026/7027’s specified operational clock speed
range is 50 kHz to 44 MHz ±1ꢀ to ensure correct operation of
the analog peripherals and Flash/EE.
Rev. A | Page 84 of 92
ADuC7019/20/21/22/24/25/26/27
3.3V
POWER-ON RESET OPERATION
IOV
LV
DD
An internal power-on reset (POR) is implemented on the
ADuC7019/7020/7021/7022/7024/7025/7026/7027. For LVDD
below 2.35 V typical, the internal POR holds the part in reset.
As LVDD rises above 2.35 V, an internal timer times out for
typically 128 ms before the part is released from reset. The user
must ensure that the power supply IOVDD has reached a stable
2.7 V minimum level by this time. Likewise, on power-down,
the internal POR holds the ADuC7019/7020/7021/7022/
7024/7025/7026/7027 in reset until LVDD has dropped below
2.35 V.
2.6V
2.35V TYP
2.35V TYP
DD
128ms TYP
POR
0.12ms TYP
MRST
Figure 79 illustrates the operation of the internal POR in detail.
Figure 79. ADuC7019/7020/7021/7022/7024/7025/7026/7027
Internal Power-on Reset Operation
TYPICAL SYSTEM CONFIGURATION
A typical ADuC7020 configuration is shown in Figure 80. It summarizes some of the hardware considerations discussed in the previous
sections. The bottom of the CSP package has an exposed pad that needs to be soldered to a metal plate on the board for mechanical
reasons. The metal plate of the board can be connected to ground.
+
10Ω
–
0.01μF
RS232 INTERFACE*
0.47μF
AV
DD
STANDARD D-TYPE
SERIAL COMMS
CONNECTOR TO
PC HOST
40 39 38 37 36 35 34 33 32 31
DV
DD
ADM3202
V
1
2
30
29
28
27
26
25
24
23
22
21
1
2
3
4
5
6
7
8
C1+
16
CC
1
2
3
4
5
6
7
8
9
V+
GND 15
T1OUT 14
R1IN 13
3
GND
REF
C1–
C2+
C2–
V–
4
DAC0
5
R1OUT 12
T1IN 11
ADuC7020
6
XCLKI
7
XCLKO
T2OUT
R2IN
T2IN 10
8
TMS
TDI
32.768kHz
R2OUT
9
9
10
P0.0
1kΩ
DV
DD
1kΩ
11 12 13 14 15 16 17 18 19 20
*EXTERNAL UART TRANSCEIVER INTEGRATED IN SYSTEM OR AS
PART OF AN EXTERNAL DONGLE AS DESCRIBED IN uC006.
DV
DD
0.47μF
DV
DD
DV
DD
AV
DD
1
2
3
4
5
6
DV
DD
ADP3333-3.3
OUT IN
TRST
TDI
1.5Ω
270Ω
GND SD
TMS
TCK
7
8
10μF
10μF
0.1μF
9
10
11
12
13
14
15
16
17
18
19
20
TDO
NOT CONNECTED IN THIS EXAMPLE
Figure 80. Typical System Configuration
Rev. A | Page 85 of 92
ADuC7019/20/21/22/24/25/26/27
DEVELOPMENT TOOLS
PC-BASED TOOLS
Software
•
Integrated development environment, incorporating
assembler, compiler, and nonintrusive JTAG-based
debugger
Four types of development systems are available for the
ADuC7019/7020/7021/7022/7024/7025/7026/7027 family:
•
The ADuC7026 QuickStart Plus is intended for new users
who want to have a comprehensive hardware development
environment. Since the ADuC7026 contains the superset of
functions available on the ADuC7019/7020/7021/
7022/7024/7025/7026/7027 family, it is suitable for users
who wish to develop on any of the parts in this family. All
of the parts are fully code compatible.
•
•
Serial downloader software
Example code
Miscellaneous
•
CD-ROM documentation
IN-CIRCUIT SERIAL DOWNLOADER
•
The ADuC7020, ADuC7024, and ADuC7026 QuickStart
are intended for users who already have an emulator.
The serial downloader is a Windows application that allows the
user to serially download an assembled program to the on-chip
program Flash/EE memory via the serial port on a standard PC.
These systems consist of the following PC-based (Windows®
compatible) hardware and software development tools:
The UART based serial downloader is included in all the
development systems and is usable with ADuC7019/7020/7021/
7022/7024/7025/7026/7027 that do not contain the “I” suffix in
the ordering guide.
Hardware
•
ADuC7019/7020/7021/7022/7024/7025/7026/7027
evaluation board
An I2C based serial downloader is also available at
www.analog.com. This software requires an USB to I2C
adaptor board available from http://www.fh-pforzheim.de/
stw-svs/texte/Dongle.html. The I2C based serial downloader
is only usable with the part models containing the “I” suffix
in the ordering guide.
•
•
Serial port programming cable
RDI compliant JTAG emulator (included in the
ADuC7026 QuickStart Plus only)
Rev. A | Page 86 of 92
ADuC7019/20/21/22/24/25/26/27
OUTLINE DIMENSIONS
6.00
BSC SQ
0.60 MAX
0.60 MAX
PIN 1
INDICATOR
31
40
1
30
PIN 1
INDICATOR
0.50
BSC
TOP
VIEW
4.25
4.10 SQ
3.95
5.75
BCS SQ
EXPOSED
PAD
(BOTTOM VIEW)
0.50
0.40
0.30
21
10
11
20
0.25 MIN
4.50
REF
12° MAX
0.80 MAX
0.65 TYP
0.05 MAX
0.02 NOM
1.00
0.85
0.80
0.30
0.23
0.18
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-2
Figure 81. 40-Lead Frame Chip Scale Package [LFCSP_VQ]
6 mm x 6 mm Body, Very Thin Quad
(CP-40)
Dimensions shown in millimeters
0.30
0.25
0.18
9.00
BSC SQ
0.60 MAX
0.60 MAX
PIN 1
INDICATOR
64
49
48
1
PIN 1
INDICATOR
*
4.85
4.70 SQ
4.55
8.75
BSC SQ
TOP
VIEW
0.45
33
32
16
17
0.40
0.35
7.50
REF
0.80 MAX
1.00
0.85
0.80
12° MAX
0.65 TYP
0.05 MAX
0.02 NOM
SEATING
PLANE
0.50 BSC
0.20 REF
*
COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4
EXCEPT FOR EXPOSED PAD DIMENSION
Figure 82. 64-Lead Frame Chip Scale Package [LFCSP_VQ]
9 mm x 9 mm Body, Very Thin Quad
(CP-64-1)
Dimensions shown in millimeters
Rev. A | Page 87 of 92
ADuC7019/20/21/22/24/25/26/27
0.75
0.60
0.45
12.00
BSC SQ
1.60
MAX
64
49
1
48
PIN 1
10.00
BSC SQ
TOP VIEW
(PINS DOWN)
1.45
0.20
1.40
0.09
1.35
7°
3.5°
0°
0.08 MAX
COPLANARITY
16
33
0.15
0.05
SEATING
PLANE
17
32
VIEW A
0.27
0.22
0.17
0.50
BSC
LEAD PITCH
VIEW A
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MS-026-BCD
Figure 83. 64-Lead Low Profile Quad Flat Package [LQFP]
(ST-64-2)
Dimensions shown in millimeters
14.00
BSC SQ
0.75
0.60
0.45
1.60
MAX
80
61
60
1
PIN
1
12.00
BSC SQ
TOP VIEW
(PINS DOWN)
1.45
1.40
1.35
0.20
0.09
7°
3.5°
0°
20
41
0.15
0.05
21
40
SEATING
PLANE
0.08 MAX
COPLANARITY
VIEW A
0.50
BSC
0.27
0.22
0.17
LEAD PITCH
VIEW A
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MS-026-BDD
Figure 84. 80-Lead Low Profile Quad Flat Package [LQFP]
(ST-80-1)
Dimensions shown in millimeters
Rev. A | Page 88 of 92
ADuC7019/20/21/22/24/25/26/27
ORDERING GUIDE
ADC
DAC
Channels
Temperature
FLASH/RAM GPIO Downloader Range
Package
Description
Package
Option
Ordering
Quantity
Model
Channels
ADuC7019BCPZ62I1
52
3
3
3
4
4
4
4
4
4
2
2
2
2
2
2
2
2
2
62 kB/8 kB
62 kB/8 kB
62 kB/8 kB
62 kB/8 kB
62 kB/8 kB
62 kB/8 kB
62 kB/8 kB
62 kB/8 kB
62 kB/8 kB
62 kB/8 kB
62 kB/8 kB
62 kB/8 kB
62 kB/8 kB
62 kB/8 kB
62 kB/8 kB
32 kB/4 kB
32 kB/4 kB
32 kB/4 kB
62 kB/8 kB
62 kB/8 kB
62 kB/8 kB
32 kB/4 kB
32 kB/4 kB
32 kB/4 kB
62 kB/8 kB
62 kB/8 kB
62 kB/8 kB
62 kB/8 kB
62 kB/8 kB
14
14
14
14
14
14
14
14
14
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
30
30
30
30
30
I2C
−40°C to
+125°C
40-Lead LFCSP_VQ
40-Lead LFCSP_VQ
40-Lead LFCSP_VQ
40-Lead LFCSP_VQ
40-Lead LFCSP_VQ
40-Lead LFCSP_VQ
40-Lead LFCSP_VQ
40-Lead LFCSP_VQ
40-Lead LFCSP_VQ
40-Lead LFCSP_VQ
40-Lead LFCSP_VQ
40-Lead LFCSP_VQ
40-Lead LFCSP_VQ
40-Lead LFCSP_VQ
40-Lead LFCSP_VQ
40-Lead LFCSP_VQ
40-Lead LFCSP_VQ
40-Lead LFCSP_VQ
40-Lead LFCSP_VQ
40-Lead LFCSP_VQ
40-Lead LFCSP_VQ
40-Lead LFCSP_VQ
40-Lead LFCSP_VQ
40-Lead LFCSP_VQ
64-Lead LFCSP_VQ
64-Lead LFCSP_VQ
64-Lead LFCSP_VQ
64-Lead LQFP
CP-40
CP-40
CP-40
CP-40
CP-40
CP-40
CP-40
CP-40
CP-40
CP-40
CP-40
CP-40
CP-40
CP-40
CP-40
CP-40
CP-40
CP-40
CP-40
CP-40
CP-40
CP-40
CP-40
CP-40
CP-64-1
CP-64-1
CP-64-1
ST-64-2
ST-64-2
ADuC7019BCPZ62I-RL1
52
I2C
−40°C to
+125°C
2,500
750
ADuC7019BCPZ62IRL71 52
I2C
−40°C to
+125°C
ADuC7020BCPZ621
5
UART
UART
UART
I2C
−40°C to
+125°C
ADuC7020BCPZ62-RL1
5
−40°C to
+125°C
2,500
750
ADuC7020BCPZ62-
RL71
ADuC7020BCPZ62I1
5
−40°C to
+125°C
5
−40°C to
+125°C
ADuC7020BCPZ62I-RL1
ADuC7020BCPZ62IRL71
5
I2C
−40°C to
+125°C
2,500
750
5
I2C
−40°C to
+125°C
ADuC7021BCPZ621
8
UART
UART
UART
I2C
−40°C to
+125°C
ADuC7021BCPZ62-RL1
8
−40°C to
+125°C
2,500
750
ADuC7021BCPZ62-
RL71
ADuC7021BCPZ62I1
8
−40°C to
+125°C
8
−40°C to
+125°C
ADuC7021BCPZ62I-RL1
ADuC7021BCPZ62IRL71
8
I2C
−40°C to
+125°C
2,500
750
8
I2C
−40°C to
+125°C
ADuC7021BCPZ321
8
UART
UART
UART
UART
UART
UART
UART
UART
UART
UART
UART
UART
UART
UART
−40°C to
+125°C
ADuC7021BCPZ32-RL1
8
−40°C to
+125°C
2,500
750
ADuC7021BCPZ32-
RL71
ADuC7022BCPZ621
8
−40°C to
+125°C
10
10
10
10
10
10
10
10
10
10
10
−40°C to
+125°C
ADuC7022BCPZ62-RL1
−40°C to
+125°C
2,500
750
ADuC7022BCPZ62-
RL71
ADuC7022BCPZ321
−40°C to
+125°C
−40°C to
+125°C
ADuC7022BCPZ32-RL1
−40°C to
+125°C
2,500
750
ADuC7022BCPZ32-
RL71
ADuC7024BCPZ621
−40°C to
+125°C
2
2
2
2
2
−40°C to
+125°C
ADuC7024BCPZ62-RL1
−40°C to
+125°C
2,500
750
ADuC7024BCPZ62-
RL71
ADuC7024BSTZ621
−40°C to
+125°C
−40°C to
+125°C
ADuC7024BSTZ62-RL1
−40°C to
+125°C
64-Lead LQFP
1,000
Rev. A | Page 89 of 92
ADuC7019/20/21/22/24/25/26/27
ADC
Channels
DAC
Channels
Temperature
FLASH/RAM GPIO Downloader Range
Package
Description
Package
Option
Ordering
Quantity
Model
ADuC7025BCPZ621
12
12
12
12
12
12
12
12
12
62 kB/8 kB
62 kB/8 kB
62 kB/8 kB
32 kB/4 kB
32 kB/4 kB
32 kB/4 kB
62 kB/8 kB
62 kB/8 kB
62 kB/8 kB
62 kB/8 kB
62 kB/8 kB
62 kB/8 kB
62 kB/8 kB
62 kB/8 kB
30
30
30
30
30
30
30
30
40
40
40
40
40
40
UART
UART
UART
UART
UART
UART
UART
UART
UART
UART
I2C
−40°C to
+125°C
64-Lead LFCSP_VQ
64-Lead LFCSP_VQ
64-Lead LFCSP_VQ
64-Lead LFCSP_VQ
64-Lead LFCSP_VQ
64-Lead LFCSP_VQ
64-Lead LQFP
CP-64-1
CP-64-1
CP-64-1
CP-64-1
CP-64-1
CP-64-1
ST-64-2
ST-64-2
ST-80-1
ST-80-1
ST-80-1
ST-80-1
ST-80-1
ST-80-1
ADuC7025BCPZ62-RL1
−40°C to
+125°C
2,500
750
ADuC7025BCPZ62-
RL71
ADuC7025BCPZ321
−40°C to
+125°C
−40°C to
+125°C
ADuC7025BCPZ32-RL1
−40°C to
+125°C
2,500
750
ADuC7025BCPZ32-
RL71
ADuC7025BSTZ621
−40°C to
+125°C
−40°C to
+125°C
ADuC7025BSTZ62-RL1
−40°C to
+125°C
64-Lead LQFP
1,000
1,000
1,000
1,000
ADuC7026BSTZ621, 3
4
4
4
4
−40°C to
+125°C
80-Lead LQFP
ADuC7026BSTZ62-RL1, 3 12
−40°C to
+125°C
80-Lead LQFP
ADuC7026BSTZ62I1, 3
12
12
16
16
−40°C to
+125°C
80-Lead LQFP
ADuC7026BSTZ62I-RL1,
I2C
−40°C to
+125°C
80-Lead LQFP
3
ADuC7027BSTZ621, 3
UART
UART
−40°C to
+125°C
80-Lead LQFP
ADuC7027BSTZ62-RL1, 3
−40°C to
+125°C
80-Lead LQFP
EVAL-ADuC7020MK
EVAL-ADuC7020QS
ADuC7020 MiniKit
ADuC7020
QuickStart
Development
System
EVAL-ADuC7024QS
EVAL-ADuC7026QS
EVAL-ADuC7026QSP
ADuC7024
QuickStart
Development
System
ADuC7026
QuickStart
Development
System
ADuC7026
QuickStart Plus
Development
System
1 Z = Pb-free part.
2 One of the ADC channels is internally buffered.
3 Includes external memory interface.
Rev. A | Page 90 of 92
ADuC7019/20/21/22/24/25/26/27
NOTES
Rev. A | Page 91 of 92
ADuC7019/20/21/22/24/25/26/27
NOTES
Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent
Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04955-0-1/06(A)
Rev. A | Page 92 of 92
相关型号：
ADUC7020BCPZ62-RL
IC 32-BIT, FLASH, 44 MHz, RISC MICROCONTROLLER, QCC40, 6 X 6 MM, ROHS COMPLIANT, MO-220VJJD-2, LFCSP-40, Microcontroller
ADI
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