ADUC7120BBCZ [ADI]
Precision Analog Microcontroller, 12-Bit Analog Input/Output, ARM7TDMI MCU;
| 型号： | ADUC7120BBCZ |
| 厂家： | 
ADI |
| 描述： | Precision Analog Microcontroller, 12-Bit Analog Input/Output, ARM7TDMI MCU 微控制器 |
| 文件： | 总102页 (文件大小：1594K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Precision Analog Microcontroller, 12-Bit
Analog Input/Output, ARM7TDMI MCU
ADuC7120/ADuC7121
Data Sheet
Memory
FEATURES
126 kB Flash/EE memory, 8 kB SRAM
In-circuit download, JTAG-based debug
Software triggered in-circuit reprogrammability
On-chip peripherals
UART, 2 × I2C and SPI serial I/O
32-pin GPIO port
4× general-purpose timers
Wake-up timers and WDT
Power supply monitor
Analog input/output
Multiple channel, 12-bit, 1 MSPS ADC
2 differential pairs with input PGA
General-purpose inputs (differential or single-ended)
ADuC7120: 11 channels
ADuC7121: 7 channels
Fully differential and single-ended modes
0 V to VREF analog input voltage range (single-ended mode)
5 low noise IDACs
250 mA, 200 mA, 45 mA, 80 mA, 20 mA
12-bit voltage output DACs
IDAC monitor
Temperature monitor
Vectored interrupt controller for FIQ and IRQ
8 priority levels for each interrupt type
Interrupt on edge or level external pin inputs
Power
ADuC7120: 12 channels
ADuC7121: 4 channels
4× 12-bit voltage output DACs
On-chip voltage reference
Specified for 3 V operation
Normal mode: 11 mA at 5.22 MHz, 30 mA at 41.78 MHz
Packages and temperature range
7 mm × 7 mm 108-ball CSP_BGA
Fully specified for –40°C to +105°C operation
Tools
On-chip temperature sensor
Microcontroller
ARM7TDMI core, 16-bit/32-bit RISC architecture
JTAG port supports code download and debug
Clocking options
Trimmed on-chip oscillator ( 3ꢀ)
External watch crystal
Low cost QuickStart development system
Full third party support
External clock source up to 41.78 MHz
41.78 MHz PLL with programmable divider
APPLICATIONS
Optical modules—tunable laser
FUNCTIONAL BLOCK DIAGRAM
AVDD 3.3V
AGND
IDAC0 IDAC1 IDAC2 IDAC3 IDAC4
DAC
DAC
BUF
BUF
DAC0
ADuC7120: 12 CHANNELS
ADuC7121: 4 CHANNELS
DAC11
PADC0N
PADC0P
PGA
ADuC7120/
ADuC7121
PLA
PADC1N
PADC1P
PGA
OSC
PLL
POR
PWM
1MSPS
12-BIT
SAR ADC
ADC0
ADC1
8kB SRAM
3× GP
WAKE-UP
TIMER
IOVDD
IOGND
(2k × 32-BIT)
TIMERS
LDO
126kB
FLASH
(63k ×
WDT
VIC
ARM7
TDMI
XTALI
XTALO
RST
ADC9
UART
16-BIT)
ADC10/AINCM
GPIO
CONTROL
2
TEMPERATURE
SENSOR
TDO
TDI
JTAG
SPI
I C × 2
TCK
TMS
TRST
INTERNAL
REFERENCE
BUF
V
_1.2
V
_2.5
REF
REF
P0.0 TO P0.7
P1.0 TO P1.7
P2.0 TO P2.7
P3.0 TO P3.7
Figure 1.
Rev. D
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Tel: 781.329.4700 ©2011–2017 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
ADuC7120/ADuC7121
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Other Analog Peripherals.............................................................. 46
DACs ............................................................................................ 46
Low Dropout (LDO) Regulator................................................ 49
Current Output DACs (IDAC)................................................. 50
IDAC MMRs............................................................................... 51
Oscillator and PLL—Power Control........................................ 52
Digital Peripherals.......................................................................... 55
Pulse-Width Modulator (PWM) Overview............................ 55
PWM Convert Start Control .................................................... 57
General-Purpose Input/Output.................................................... 58
UART Serial Interface.................................................................... 62
Baud Rate Generation................................................................ 62
UART Register Definition......................................................... 62
I2C Peripherals ................................................................................ 66
Serial Clock Generation ............................................................ 66
I2C Bus Addresses....................................................................... 66
I2C Registers................................................................................ 67
I2C Common Registers.............................................................. 74
Serial Peripheral Interface............................................................. 75
SPI Master In, Slave Out (MISO) Pin...................................... 75
SPI Master Out, Slave In (MOSI) Pin...................................... 75
Serial Clock Input/Output (SPICLK) Pin ............................... 75
SPI Chip Select Input Pin.......................................................... 75
Configuring External Pins for SPI Functionality................... 75
SPI Registers................................................................................ 75
Programmable Logic Array (PLA)............................................... 78
PLA MMRs Interface................................................................. 79
Interrupt System ............................................................................. 82
Normal Interrupt Request (IRQ) ............................................. 82
Fast Interrupt Request (FIQ) .................................................... 83
External Interrupts (IRQ0 to IRQ5) ........................................ 88
Timers .............................................................................................. 89
Hour: Minute: Second: 1/128 Format...................................... 89
Timer0—Lifetime Timer........................................................... 89
Timer1—General-Purpose Timer ........................................... 91
Timer2—Wake-Up Timer......................................................... 93
Timer3—Watchdog Timer........................................................ 94
Timer4—General-Purpose Timer ........................................... 97
Hardware Design Considerations ................................................ 99
Power Supplies............................................................................ 99
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 3
General Description......................................................................... 4
Specifications..................................................................................... 5
Timing Specifications ................................................................ 10
Absolute Maximum Ratings.......................................................... 15
Thermal Resistance .................................................................... 15
ESD Caution................................................................................ 15
Pin Configurations and Function Descriptions ......................... 16
Terminology .................................................................................... 24
ADC Specifications .................................................................... 24
DAC Specifications..................................................................... 24
Overview of the ARM7TDMI Core............................................. 25
Thumb (T) Mode........................................................................ 25
Long Multiply (M)...................................................................... 25
EmbeddedICE (I) ....................................................................... 25
Exceptions ................................................................................... 25
ARM Registers ............................................................................ 26
Interrupt Latency........................................................................ 26
Memory Organization ................................................................... 27
Memory Access........................................................................... 27
Flash/EE Memory....................................................................... 27
SRAM........................................................................................... 27
Memory Mapped Registers (MMR)......................................... 27
Complete MMR Listing............................................................. 28
ADC Circuit Overview .................................................................. 31
ADC Transfer Function............................................................. 31
Temperature Sensor ................................................................... 33
Converter Operation.................................................................. 36
Driving the Analog Inputs ........................................................ 37
Band Gap Reference................................................................... 38
Power Supply Monitor (PSM)................................................... 39
Nonvolatile Flash/EE Memory ..................................................... 40
Flash/EE Memory Overview..................................................... 40
Flash/EE Memory Security ....................................................... 41
Flash/EE Control Interface........................................................ 41
Execution Time from SRAM and Flash/EE............................ 44
Reset and Remap ........................................................................ 44
Rev. D | Page 2 of 102
Data Sheet
ADuC7120/ADuC7121
Grounding and Board Layout Recommendations .............. 100
Clock Oscillator........................................................................ 101
Outline Dimensions......................................................................102
Ordering Guide .........................................................................102
REVISION HISTORY
9/2017—Rev. C to Rev. D
Changes to Table 89 ........................................................................63
Changes to Table 96 ........................................................................67
Changes to Table 97 ........................................................................68
Added Hardware Design Consideration Section........................95
Added ADuC7120.............................................................. Universal
Changed –40°C to +95°C to –40°C to +105°C.......... Throughout
Changes to Features Section and Figure 1 .....................................1
Changes to General Description Section.......................................4
Changes to Specifications Section and Table 1..............................5
Added Figure 7 and Table 10; Renumbered Sequentially..........16
Changes to Table 11 ........................................................................20
Changes to Table 12 and Table 14.................................................28
Changes to Table 25 ........................................................................30
Changes to Table 32 to Table 35 ....................................................35
Change to Table 40..........................................................................36
Change to Flash/EE Memory Overview Section, Flash/EE
Memory Reliability Section, and Serial Downloading (In Circuit
Programming) Section ...................................................................40
Changes to FEE0STA Register Section and FEE1STA Register
Section ..............................................................................................42
Changes to Execution from Flash/EE Section and Table 50 .....44
Changes to DACs Section and Figure 29 .....................................46
Added Table 55 ................................................................................47
Changes to Table 56 ........................................................................47
Added Table 58 and Table 60.........................................................48
Changes to Table 59 ........................................................................48
Changes to External Clock Selection Section and Table 71 ......53
Changes to Table 80 ........................................................................57
Changes to Slave Mode Section.....................................................66
Changes Table 102 and I2C Slave Status Register Section..........71
Changes to Table 109 ......................................................................79
Changes to Table 126 ......................................................................87
Changes to IRQCLRE Register Section........................................88
Changes to Figure 42 and Figure 43 .............................................99
Changes to Figure 44 to Figure 48 ..............................................100
Changes to Figure 49 and Figure 50 ...........................................101
Changes to Ordering Guide.........................................................102
3/2013—Rev. A to Rev. B
Changes to Table 9 ..........................................................................19
Changes to Table 11 ........................................................................24
Changes to Reset Operation Section............................................40
Added RSTCFGKEY0 Register and RSTCFGKEY1 Register
Sections.............................................................................................40
Added Table 49 and Table 50; Renumbered Sequentially .........40
Changed IREF = 370.37 μA to IREF = 380 μA..................................44
Changes to Figure 32 ......................................................................44
Changes to Table 57 ........................................................................45
Changes to Table 64 ........................................................................46
3/2012—Rev. 0 to Rev. A
Changed IDAC2 Full-Scale Output to 45 mA ...........Throughout
Changed IDAC3 Full-Scale Output to 80 mA ...........Throughout
Added BUFFER VREF Out Parameter to Table 1,
Specifications Section.......................................................................6
Changes to IDAC3 and IDAC2, Full-Scale Output Parameter,
Table 1, Specifications Section.........................................................6
Changes to Flash/EE Memory Section.........................................35
Changes to PADC0x/PADC1x Pins Section ...............................28
Added New Figure 15, Renumbered Sequentially......................28
Changes to Temperature Sensor Section .....................................29
Changes to Current Output DACs (IDAC) Section...................43
Changes to Table 58 ........................................................................45
Change to External Interrupts (IRQ0 to IRQ5) Section
Heading ............................................................................................84
Added Hour:Minute:Second:1/128 Format Section...................86
Added New Table 122, Renumbered Sequentially......................86
Changes to Timer3 Control Register Section..............................91
Changes to Table 130......................................................................92
11/2014—Rev. B to Rev. C
Changes to Flash/EE Memory Section.........................................23
Changes to PADC0x/PADC1x Pins Section................................28
Changes to Flash/EE Memory Section and Serial Downloading
(In-Circuit Programming) Section...............................................35
Changes to Flash/EE Memory Security Section .........................36
Changes to Table 41, Table 42, and FEE0STA Default Value ....37
Changes to I2C Peripherals Section ..............................................62
1/2011—Revision 0: Initial Version
Rev. D | Page 3 of 102
ADuC7120/ADuC7121
Data Sheet
GENERAL DESCRIPTION
The ADuC7120/ADuC7121 are fully integrated, 12-bit, 1 MSPS,
data acquisition systems incorporating a high performance
multichannel ADC, 16-bit/32-bit microcontroller unit (MCU),
and Flash®/EE memory on a single chip.
The devices operate from an on-chip oscillator and a phase-
locked loop (PLL) generating an internal high frequency
clock of 41.78 MHz (UCLK). This clock is routed through a
programmable clock divider from which the MCU core clock
operating frequency is generated. The microcontroller core is
an ARM7TDMI®, 16-bit/32-bit reduced instruction set
computer (RISC) machine, which offers up to 41 MIPS peak
performance. 8 kB of SRAM and 126 kB of nonvolatile Flash/EE
memory are provided on chip. The ARM7TDMI core views all
memory and registers as a single linear array.
The analog-to-digital converter (ADC) consists of eleven
single-ended inputs for the ADuC7120 (seven single-ended
inputs for the ADuC7121) and two extra differential input
pairs. The two differential input pairs can be routed through a
programmable gain amplifier (PGA). The ADC can operate in
single-ended or differential input mode. The ADC input voltage
is 0 V to VREF. A low drift band gap reference, temperature sensor,
and voltage comparator complete the ADC peripheral set.
On-chip factory firmware supports in circuit serial download
via the I2C serial interface port; nonintrusive emulation is also
supported via the JTAG interface. These features are incorporated
into a low cost QuickStart development system supporting this
MicroConverter® family.
The ADuC7120/ADuC7121 provide five current output digital-
to-analog converters (DACs). The current sources (five current
DACs) feature low noise and low drift, high-side current output
at an 11-bit resolution. The five current digital-to-analog converters
(IDACs) are as follows: IDAC0 with 250 mA full-scale (FS)
output, IDAC1 with 200 mA FS output, IDAC2 with 45 mA FS
output, IDAC3 with 80 mA FS output, and IDAC4 with 20 mA
FS output.
The devices operate from 3.0 V to 3.6 V, and they are specified
over the −40°C to +105°C industrial temperature range. The
IDACs are powered from a separate input power supply, PVDD
.
When operating at 41.78 MHz, the power dissipation is typically
120 mW. The ADuC7120/ADuC7121 are available in a 108-ball
chip-scale package ball grid array [CSP_BGA].
The ADuC7120/ADuC7121 also contain up to 12 voltage output
DACs. The DAC output range is programmable to one of three
voltage ranges, which are listed in Table 42.
Rev. D | Page 4 of 102
Data Sheet
ADuC7120/ADuC7121
SPECIFICATIONS
AVDD = IOVDD = 3.0 V to 3.6 V, PVDD_IDACx = 1.5 V to 2.1 V, reference voltage (VREF) = 2.5 V internal reference, core frequency
(fCORE) = 41.78 MHz, ambient temperature (TA) = −40°C to +105°C, unless otherwise noted.
Table 1.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
ADC CHANNEL SPECIFICATIONS
Eight acquisition clocks and
ADC frequency (fADC)/2
ADC Power-Up Time
DC Accuracy1, 2
5
μs
Resolution
Integral Nonlinearity
12
Bits
LSB
LSB
0.ꢀ
0.ꢀ
2.2
2
−10°C to +95°C temperature range only
2.5 V internal reference, not production
tested for PADC0x and PADC1x channels
2.5 V internal reference, guaranteed monotonic
ADC input is a dc voltage
Differential Nonlinearity3, 4
DC Code Distribution
ENDPOINT ERRORS5
Offset Error
0.5
1
+1.4/−0.99
LSB
LSB
Internally unbuffered channels
All Channels Except IDACx
Channels
2
5
LSB
IDACx Channels Only
Offset Error Match
Gain Error
1
1
2
2
1
% of FS
LSB
LSB
LSB
LSB
5.3
5
−10°C to +95°C temperature range only
Gain Error Match
DYNAMIC PERFORMANCE
Input frequency (fIN) = 10 kHz sine wave,
sample frequency (fSAMPLE) = 1 MSPS,
internally unbuffered channels
Signal-to-Noise Ratio (SNR)
Total Harmonic Distortion (THD)
Peak Harmonic or Spurious Noise
Channel to Channel Crosstalk
ANALOG INPUT
ꢀ9
dB
dB
dB
dB
Includes distortion and noise components
−78
−75
−80
Measured on adjacent channels
Input Voltage Ranges
Differential Mode
ꢀ
VCM VREF/2
V
See Table 42
Single-Ended Mode
0 to VREF
AVDD − 1.5
1
V
V
μA
pF
pF
Buffer bypassed
Buffer enabled
0.15
Leakage Current
Input Capacitance
0.2
20
20
During ADC acquisition buffer bypassed
During ADC acquisition buffer enabled
PADC0x INPUT
28.3 kΩ resistor, PGA gain = 3, acquisition
time = 3.2 μs, pseudo differential mode
Full-Scale Input Range
Input Leakage at PADC0x4
Resolution
20
11
1000
2
μA
nA
Bits
0.15
0.1% accuracy, 5 ppm external resistor for
current to voltage
Gain Error4
1
50
ꢀ
ꢀ0
%
Gain Drift4
ppm/°C
nA
pA/°C
V
Offset4
3
30
PGA offset not included
Offset Drift4
PADC0x Compliant Range
0.1
AVDD − 1.2
Rev. D | Page 5 of 102
ADuC7120/ADuC7121
Data Sheet
Parameter
Min
10.6
11
Typ
Max
Unit
Test Conditions/Comments
PADC1x INPUT
53.5 kΩ resistor, PGA gain = 3
Full-Scale Input Range
Input Leakage at PADC1x4
Resolution
700
2
µA
nA
Bits
0.15
0.1% accuracy, 5 ppm external resistor for
current to voltage
Gain Error4
1
50
6
60
%
Gain Drift4
ppm/°C
nA
pA/°C
V
Offset4
3
30
PGA offset not included
Offset Drift4
PADC1x Compliant Range
ON-CHIP VOLTAGE REFERENCE
Output Voltage
0.1
AVDD − 1.2
0.47 µF from VREF to AGND
TA = 25°C
2.5
V
Accuracy7
5
30
mV
ppm/°C
dB
Ω
ms
Reference Temperature Coefficient4
Power Supply Rejection Ratio (PSRR)
Output Impedance
10
61
10
1
TA = 25°C
Internal VREF Power-On Time
BUFFER VREF OUTPUT
BUF_VREFx
80
mV
V
EXTERNAL REFERENCE INPUT
Input Voltage Range
IDAC CHANNEL SPECIFICATIONS
Voltage Compliance Range
IDAC0 Voltage Compliance Range
1.2
AVDD
0.4
−0.2
1.6
+1.68
V
V
Output voltage compliance
For IDAC0 channel only, linearity not
guaranteed below 0 V
REFERENCE CURRENT GENERATOR
Reference Current
0.38
mA
Using internal reference, 0.1%, 5 ppm,
3.16 kΩ external resistor
Temperature Coefficient
Short-Circuit Detection
Overheat Shutdown
RESOLUTION
25
1
135
11
ppm/°C Using internal reference
mA
°C
Junction temperature
Guaranteed monotonic
Bits
FULL-SCALE OUTPUT
IDAC4
IDAC3
20
80
mA
mA
PVDD_IDACx = 1.5 V to 2.1 V
PVDD_IDACx = 1.9 V to 2.1 V; when
PVDD_IDACx = 1.5 V to 1.9 V, the maximum
output current cannot exceed 57 mA
IDAC2
IDAC1
IDAC0
45
mA
mA
mA
PVDD_IDACx = 1.9 V to 2.1 V; when
PVDD_IDACx = 1.5 V to 1.9 V, the maximum
output current cannot exceed 35 mA
PVDD_IDACx = 1.9 V to 2.1 V; when
PVDD_IDACx = 1.5 V to 1.9 V, the maximum
output current cannot exceed 150 mA
PVDD_IDACx = 1.9 V to 2.1 V; when
PVDD_IDACx = 1.5 V to 1.9 V, the maximum
output current cannot exceed 195 mA
200
250
Integral Nonlinearity
Noise Current
Full-Scale Error
2
20
3
LSB
µA
%
11-bit mode
RMS value, bandwidth 20 Hz to 10 MHz
Output voltage (VOUT) = 1.6 V
Full-Scale Error Drift
50
ppm/°C Internal VREF, 5 ppm external resistor
Rev. D | Page 6 of 102
Data Sheet
ADuC7120/ADuC7121
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
Zero-Scale Error
IDAC4 Channel
IDAC± Channel
IDAC2 Channel
IDAC1 Channel
IDAC0 Channel
Pull-down switch off, VOUT = 0 V
VOUT = 0.4 V
VOUT = 0.4 V
VOUT = 0.4 V
VOUT = 0.4V
±±0
μA
μA
μA
μA
μA
+42/−70
+70/−110
±240
±2ꢀ0
Pull-down switch off, VOUT = 0.4 V,
output range 0.4 V to 1.6 V
+ꢀ80/−4±0
μA
Pull-down switch off, VOUT = 0.4 V,
output range −0.2 V to +1.6 V
Settling Time
Signal Bandwidth
LINE REGULATION
1
20
ms
kHz
To 0.1%
Measured with full-scale current load on
current DACs
IDAC4
IDAC±
IDAC2
IDAC1
IDAC0
10
22.ꢀ
40
100
7ꢀ0
μA/V
μA/V
μA/V
μA/V
μA/V
LOAD REGULATION
Measured with full-scale current load on
current DACs
IDAC4
IDAC±
IDAC2
IDAC1
IDAC0
10
22.ꢀ
40
100
7ꢀ0
μA/V
μA/V
μA/V
μA/V
μA/V
AC PSRR4
0.7ꢀ%
6%
% of
FS/V
% of
FS/V
10 kHz, percentage of each current DAC full-
scale current per volt
2.2ꢀ MHz, percentage of each current DAC
full-scale current per volt
PULL-DOWN
Negative Metal Oxide
Semiconductor (NMOS)
Speed4
100
mV
μs
Drain 40 mA
10
Triggered by programmable logic array
(PLA), draw the pin voltage to 10% of its
original value
VOLTAGE DAC (VDAC) CHANNEL
Load resistance (RL) = ꢀ kΩ,
load capacitance (CL) = 100 pF
Buffered
DC Accuracy9
Resolution
12
±2
±0.2
±2
9
±0.1ꢀ
0.1
10
Bits
LSB
LSB
mV
mV
%
Relative Accuracy
Differential Nonlinearity
Calculated Offset Error
Actual Offset Error
Gain Error10
Gain Error Mismatch
Settling Time
PSRR4
±1
Guaranteed monotonic
2.ꢀ V internal reference
Measured at Code 0 (zero scale)
±0.8
%
μs
% of full scale on DAC0
Buffered
DC
1 kHz
10 kHz
100 kHz
−ꢀ9
−ꢀ7
−47
−19
−61
dB
dB
dB
dB
DRIFT
Offset Drift4
20
10
10
μV/°C
μV/°C
μV/°C
−10°C to +9ꢀ°C temperature range only
Gain Error Drift4
Rev. D | Page 7 of 102
ADuC7120/ADuC7121
Data Sheet
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
SHORT-CIRCUIT CURRENT
ANALOG OUTPUTS
Output Range
20
mA
0.1
VREF/AVDD − 0.1
Buffer on
DAC AC CHARACTERISTICS
Slew Rate
Voltage Output Settling Time
Digital to Analog Glitch Energy
2.49
10
20
V/μs
μs
nV-sec
1 LSB change at major carry (where
maximum number of bits simultaneously
change in the DACxDAT register)
TEMPERATURE SENSOR11
Voltage Output at 25°C
Voltage Temperature Coefficient
Accuracy
After user calibration
707
−1.25
3
mV
mV/°C
°C
MCU in power-down or standby mode
before measurement
POWER SUPPLY MONITOR (PSM)
IOVDD Trip Point Selection
2.79
3.07
2.5
V
V
%
V
Two selectable trip points
Power Supply Trip Point Accuracy
POWER-ON RESET
WATCHDOG TIMER (WDT)
Timeout Period
Of the selected nominal trip point voltage
2.36
0
512
sec
FLASH/EE MEMORY
Endurance12
Data Retention13
DIGITAL INPUTS
Input Current
10,000
20
Cycles
Years
Junction temperature (TJ) = 85°C
All digital inputs excluding XTALI and XTALO
Logic 1
Logic 0
Input Capacitance
LOGIC INPUTS4
Input Low Voltage, VINL
0.2
−40
10
1
−60
μA
μA
pF
VINH = VDD
VINL = 0 V; except TDI
All logic inputs excluding XTALI
4
0.8
0.4
V
V
4
Input High Voltage, VINH
2.0
2.4
LOGIC OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
All digital outputs excluding XTALO
Source current (ISOURCE) = 1.6 mA
Sink current (ISINK) = 1.6 mA
V
V
14
CRYSTAL INPUTS (XTALI AND XTALO)
Logic Inputs, XTALI Only
VINL
1.1
V
VINH
1.7
V
XTALI Input Capacitance
XTALO Output Capacitance
INTERNAL OSCILLATOR
20
20
pF
pF
kHz
%
32.768
3
MCU CLOCK RATE
From 32 kHz Internal Oscillator
From 32 kHz External Crystal
Using an External Clock
START-UP TIME
326
41.78
kHz
MHz
MHz
Clock divider (CD) = 7
CD = 0
TA = 105°C
0.05
41.78
Core clock (HCLK) = 41.78 MHz
At Power-On
From Pause/Nap Mode
70
24
ms
ns
CD = 0
CD = 7
3.06
1.58
1.7
μs
ms
ms
From Sleep Mode
From Stop Mode
Rev. D | Page 8 of 102
Data Sheet
ADuC7120/ADuC7121
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
PROGRAMMABLE LOGIC ARRAY (PLA)
Pin Propagation Delay
Element Propagation Delay
POWER REQUIREMENTS15, 16
Power Supply Voltage Range
12
2.5
ns
ns
From input pin to output pin
AVDD to AGND and IOVDD to IOGND 3.0
Analog Power Supply Currents
AVDD Current
3.6
V
200
µA
ADC in idle mode
Digital Power Supply Current
IOVDD Current in Normal Mode
Code executing from Flash/EE
CD = 7
CD = 3 (5.22 MHz clock)
CD = 0 (41.78 MHz clock)
CD = 0 (41.78 MHz clock)
TA = 25°C
7
mA
mA
mA
mA
µA
11
30
25
100
40
IOVDD Current in Pause Mode4
IOVDD Current in Sleep Mode4
Additional Power Supply Currents
ADC
IDAC
DAC
2.7
21
250
mA
mA
µA
At 1 MSPS
All current DACs (IDACs) on
Per VDAC
ELECTROSTATIC DISCHARGE (ESD) TESTS
Human Body Model (HBM)
Field Induced Charged Devices
Model (FICDM)
2.5 V reference, TA = 25°C
4
0.5
kV
kV
1 All ADC channel specifications are guaranteed during normal MicroConverter core operation.
2 Apply to all ADC input channels.
3 Measured using the factory set default values in the ADC offset register (ADCOF) and gain coefficient register (ADCGN).
4 Not production tested but supported by design and/or characterization data on production release.
5 Measured using the factory set default values in ADCOF and ADCGN with an external AD845 op amp as an input buffer stage as shown in Figure 25. Based on external ADC
system components, the user may need to execute a system calibration to remove external endpoint errors and achieve these specifications (see the ADC Transfer
Function section).
6 The input signal can be centered on any dc common-mode voltage (VCM) provided that this value is within the ADC voltage input range specified.
7 VREF calibration and trimming are performed under the following conditions: the core is operating in normal mode (CD = 0), the ADC is on, the current DACs are on,
and all VDACs are on. VREF accuracy can vary under other operating conditions.
8 The PVDD_IDAC0 pad voltage must be at least 300 mV greater than the IDAC0 pad voltage. These voltages are measured via the PVDD0 and IDAC0 channels of the
ADC, which allows the IDAC0 pin to be pulled up to 1.7 V, provided the 300 mV differential voltage is maintained between the pads. This operation can require
supplying the PVDD_IDAC0 with a voltage greater than 2.0 V. The 2.1 V maximum PVDD_IDACx rating must not be exceeded.
9 To calculate DAC linearity, use a reduced code range of 100 to 3995.
10 To calculate DAC gain error, use a reduced code range of 100 to internal 2.5 V VREF
11 Die temperature.
.
12 Endurance is qualified per JEDEC Standard 22, Method A117 and measured at −40°C, +25°C, +85°C, and +125°C.
13 Retention lifetime equivalent at TJ = 85°C as per JEDEC Standard 22, Method A117. Retention lifetime derates with junction temperature.
14 Test carried out with a maximum of eight inputs/outputs set to a low output level.
15 Power supply current consumption is measured in normal, pause, and sleep modes under the following conditions: normal mode using a 3.6 V supply, pause mode
using a 3.6 V supply, and sleep mode using 3.6 V supply.
16 IOVDD power supply current increases typically by 2 mA during a Flash/EE erase cycle.
Rev. D | Page 9 of 102
ADuC7120/ADuC7121
Data Sheet
TIMING SPECIFICATIONS
Table 2. I2C Timing in Fast Mode (400 kHz)
Slave
Max
Master
Typ
Parameter
Description
Min
200
100
300
100
0
100
100
1.3
Unit
ns
ns
ns
ns
ns
ns
ns
μs
ns
ns
ns
tL
tH
SCLx low pulse width
SCLx high pulse width
Start condition hold time
Data setup time
Data hold time
Setup time for repeated start
Stop condition setup time
Bus free time between a stop condition and a start condition
Rise time for both SCLx and SDAx
Fall time for both SCLx and SDAx
Pulse width of spike suppressed
1360
1140
251,350
740
400
12.51350
400
tSHD
tDSU
tDHD
tRSU
tPSU
tBUF
tR
300
300
50
200
tF
tSUP
Table 3. I2C Timing in Standard Mode (100 kHz)
Slave
Max
Parameter
Description
Min
Unit
μs
ns
μs
ns
μs
μs
μs
μs
μs
ns
tL
tH
SCLx low pulse width
SCLx high pulse width
Start condition hold time
Data setup time
Data hold time
Setup time for repeated start
Stop condition setup time
Bus free time between a stop condition and a start condition
Rise time for both SCLx and SDAx
Fall time for both SCLx and SDAx
4.7
4.0
4.0
250
0
4.7
4.0
4.7
tSHD
tDSU
tDHD
tRSU
tPSU
tBUF
tR
3.45
1
300
tF
tBUF
tSUP
tR
SDAx
MSB
LSB
ACK
MSB
tF
tDSU
tDSU
tDHD
tDHD
tPSU
tR
tSHD
tRSU
tH
1
8
9
1
SCLx
2 TO 7
tL
tSUP
P
S
S(R)
tF
STOP
START
REPEATED
START
CONDITION CONDITION
Figure 2. I2C-Compatible Interface Timing
Rev. D | Page 10 of 102
Data Sheet
ADuC7120/ADuC7121
Table 4. SPI Master Mode Timing (Phase Mode = 1)
Parameter
Description
Min1
Typ1
Max
Unit
ns
tSL
tSH
SPICLK low pulse width
SPICLK high pulse width
Data output valid after SPICLK edge
Data input setup time before SPICLK edge
Data input hold time after SPICLK edge
Data output fall time
Data output rise time
SPICLK rise time
SPICLK fall time
(SPIDIV + 1) × tUCLK
(SPIDIV + 1) × tUCLK
ns
tDAV
tDSU
tDHD
tDF
tDR
tSR
25
ns
1 × tUCLK
2 × tUCLK
ns
ns
5
5
5
5
12.5
12.5
12.5
12.5
ns
ns
ns
ns
tSF
1 tUCLK = 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider.
SPICLK
(POLARITY = 0)
tSH
tSL
tSR
tSF
SPICLK
(POLARITY = 1)
tDAV
tDF
tDR
MOSI
MISO
MSB
BIT 6 TO BIT 1
LSB
MSB IN
BIT 6 TO BIT 1
LSB IN
tDSU
tDHD
Figure 3. SPI Master Mode Timing (Phase Mode = 1)
Rev. D | Page 11 of 102
ADuC7120/ADuC7121
Data Sheet
Table 5. SPI Master Mode Timing (Phase Mode = 0)
Parameter
Description
Min1
Typ1
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSL
tSH
SPICLK low pulse width
(SPIDIV + 1) × tUCLK
(SPIDIV + 1) × tUCLK
SPICLK high pulse width
Data output valid after SPICLK edge
Data output setup before SPICLK edge
Data input setup time before SPICLK edge
Data input hold time after SPICLK edge
Data output fall time
Data output rise time
SPICLK rise time
SPICLK fall time
tDAV
tDOSU
tDSU
tDHD
tDF
tDR
tSR
tSF
25
75
1 × tUCLK
2 × tUCLK
5
5
5
5
12.5
12.5
12.5
12.5
1 tUCLK = 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider.
SPICLK
(POLARITY = 0)
tSH
tSL
tSR
tSF
SPICLK
(POLARITY = 1)
tDAV
tDOSU
tDF
tDR
BIT 6 TO BIT 1
MOSI
MISO
MSB
LSB
MSB IN
tDSU
BIT 6 TO BIT 1
LSB IN
tDHD
Figure 4. SPI Master Mode Timing (Phase Mode = 0)
Rev. D | Page 12 of 102
Data Sheet
ADuC7120/ADuC7121
Table 6. SPI Slave Mode Timing (Phase Mode = 1)
Parameter
Description
Min1
Typ1
Max
Unit
tCS
CS to the SPICLK edge2
200
ns
tSL
tSH
SPICLK low pulse width
(SPIDIV + 1) × tUCLK
(SPIDIV + 1) × tUCLK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SPICLK high pulse width
Data output valid after SPICLK edge
Data input setup time before SPICLK edge
Data input hold time after SPICLK edge
Data output fall time
Data output rise time
SPICLK rise time
SPICLK fall time
CS high after SPICLK edge
tDAV
tDSU
tDHD
tDF
tDR
tSR
25
1 × tUCLK
2 × tUCLK
5
5
5
5
12.5
12.5
12.5
12.5
tSF
tSFS
0
1 tUCLK = 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider.
2 CS
CS
is the (SPI slave select input) function of the multifunction Pin F3.
CS
tSFS
tCS
SPICLK
(POLARITY = 0)
tSH
tSL
tSR
tSF
SPICLK
(POLARITY = 1)
tDAV
tDF
tDR
MISO
MOSI
MSB
BIT 6 TO BIT 1
LSB
MSB IN
BIT 6 TO BIT 1
LSB IN
tDSU
tDHD
Figure 5. SPI Slave Mode Timing (Phase Mode = 1)
Rev. D | Page 13 of 102
ADuC7120/ADuC7121
Data Sheet
Table 7. SPI Slave Mode Timing (Phase Mode = 0)
Parameter
Description
Min1
Typ1
Max
Unit
tCS
CS to SPICLK edge2
200
ns
tSL
tSH
tDAV
tDSU
tDHD
tDF
tDR
tSR
tSF
tDOCS
tSFS
SPICLK low pulse width
SPICLK high pulse width
Data output valid after SPICLK edge
Data input setup time before SPICLK edge
Data input hold time after SPICLK edge
Data output fall time
Data output rise time
SPICLK rise time
SPICLK fall time
Data output valid after CS edge
CS high after SPICLK edge
(SPIDIV + 1) × tUCLK
(SPIDIV + 1) × tUCLK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
25
1 × tUCLK
2 × tUCLK
5
5
5
5
12.5
12.5
12.5
12.5
25
0
1 tUCLK = 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider.
2 CS
CS
is the (SPI slave select input) function of the multifunction Pin F3.
CS
tCS
tSFS
SPICLK
(POLARITY = 0)
tSH
tSL
tSF
tSR
SPICLK
(POLARITY = 1)
tDAV
tDOCS
tDF
tDR
MISO
MOSI
MSB
BIT 6 TO BIT 1
LSB
MSB IN
BIT 6 TO BIT 1
LSB IN
tDSU
tDHD
Figure 6. SPI Slave Mode Timing (Phase Mode = 0)
Rev. D | Page 14 of 102
Data Sheet
ADuC7120/ADuC7121
ABSOLUTE MAXIMUM RATINGS
AGND = 0 V, TA = 25°C, unless otherwise noted.
THERMAL RESISTANCE
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environments. Careful attention to
PCB thermal design is required. θJA is the natural convection,
junction to ambient thermal resistance measured in a one cubic
foot sealed enclosure. θJC is the junction to case thermal
resistance.
Table 8.
Parameter
Rating
AVDD to IOVDD
AGND to DGND
−0.3 V to +0.3 V
−0.3 V to +0.3 V
−0.3 V to +6 V
−0.3 V to +5.3 V
−0.3 V to IOVDD + 0.3 V
−0.3 V to AVDD + 0.3 V
−0.3 V to AVDD + 0.3 V
−0.3 V to AVDD + 0.3 V
IOVDD to IOGND, AVDD to AGND
Digital Input Voltage to IOGND
Digital Output Voltage to IOGND
VREF_2.5 and VREF_1.2 to AGND
Analog Inputs to AGND
Analog Outputs to AGND
Table 9. Thermal Resistance
Package Type
CSP_BGA1
θJA
θJC
Unit
40
12
°C/W
1 Test Condition 1: Thermal impendance simulated values are based on
JEDEC 2S2P thermal test board with thermal vias. See JEDEC JESD-51.
Operating Temperature Range, Industrial −40°C to +105°C
Storage Temperature Range
Junction Temperature
−65°C to +150°C
150°C
Peak Solder Reflow Temperature
SnPb Assemblies (10 sec to 30 sec)
RoHS-Compliant Assemblies
(20 sec to 40 sec)
ESD CAUTION
240°C
260°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Only one absolute maximum rating can be applied at any one time.
Rev. D | Page 15 of 102
ADuC7120/ADuC7121
Data Sheet
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
9 10 11 12
A
B
C
D
E
F
A
B
C
D
E
F
ADuC7120
TOP VIEW
G
H
J
G
H
J
(Not to Scale)
K
K
L
L
M
M
1
2
3
4
5
6
7
8
9 10 11 12
Figure 7. ADuC7020 Pin Configuration
Table 10. ADuC7120 Pin Function Descriptions
Pin No. Mnemonic
Type1 Description
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
B1
IDAC1
AO
S
S
AO
AO
AI
IDAC1 Output. The output for this pin is 200 mA.
Power for IDAC1.
Power for IDAC1.
IDAC1 Output. The output for this pin is 200 mA.
IDAC3 Output. The output for this pin is 80 mA.
Damping Capacitor Pin for IDAC4.
PVDD_IDAC1
PVDD_IDAC1
IDAC1
IDAC3
CDAMP_IDAC4
PVDD_IDAC2
IDAC2
S
2.0 V Power for IDAC2.
AO
AO
S
S
AO
AI
IDAC2 Output. The output for this pin is 45 mA.
IDAC0 Output. The output for this pin is 250 mA.
Power for IDAC0.
Power for IDAC0.
IDAC0 Output. The output for this pin is 250 mA.
Damping Capacitor for IDAC1.
General-Purpose Input and Output (GPIO) Port 1.7 (P1.7).
Programmable Logic Array for Output Element 4 (PLAO[4]).
General-Purpose Input and Output Port 1.6 (P1.6).
Programmable Logic Array for Output Element 5 (PLAO[5]).
Damping Capacitor for IDAC3.
IDAC4 Output. The output for this pin is 20 mA.
Analog Ground.
Output of 2.5 V LDO Regulator for Internal IDACs. Connect a 470 nF capacitor to AGND
to this pin.
IDAC0
PVDD_IDAC0
PVDD_IDAC0
IDAC0
CDAMP_IDAC1
P1.7/PLAO[4]
B2
I/O
B3
P1.6/PLAO[5]
I/O
B4
B5
B6
B7
CDAMP_IDAC3
IDAC4
AGND
AI
AO
S
AVDD_IDAC
S
B8
B9
IREF
PGND
AI/O
S
Generates Reference Current for IDACs. Set by the external resistor, REXT
Power Ground.
.
B10
B11
B12
C1
PGND
S
AI/O
AI
Power Ground.
IDAC Test Purposes.
Damping Capacitor Pin for IDAC0.
General-Purpose Input and Output Port 2.6 (P2.6).
External Interrupt Request 3, Active High (IRQ3).
Programmable Logic Array for Input Element 15 (PLAI[15]).
IDAC_TST
CDAMP_IDAC0
P2.6/IRQ3/PLAI[15]
I/O
Rev. D | Page 16 of 102
Data Sheet
ADuC7120/ADuC7121
Pin No. Mnemonic
Type1 Description
C2
C3
C4
P1.0/SIN/SCL1/PLAI[7]
I/O
General-Purpose Input and Output Port 1.0 (P1.0).
Serial Input, Receive Data, UART (SIN).
I2C Interface Serial Clock for I2C1 (SCL1).
Programmable Logic Array for Input Element 7 (PLAI[7]).
General-Purpose Input and Output Port 0.2 (P0.2).
SPI Clock (SPICLK).
P0.2/SPICLK/ADCBUSY/PLAO[13] I/O
Status of the ADC (ADCBUSY).
Programmable Logic Array for Output Element 13 (PLAO[13]).
General-Purpose Input and Output Port 3.0 (P3.0).
Programmable Logic Array for Output Element 0 (PLAO[0]).
2.0 V Power for the IDAC3.
2.0 V Power for IDAC4.
Analog Supply (3.3 V).
P3.0/PLAO[0]
I/O
C5
C6
C7
C8
C9
PVDD_IDAC3
PVDD_IDAC4
AVDD
CDAMP_IDAC2
P2.7/PLAI[0]
S
S
S
AI
I/O
Damping Capacitor Pin for IDAC2.
General-Purpose Input and Output Port 2.7 (P2.7).
Programmable Logic Array for Input Element 0 (PLAI[0]).
General-Purpose Input and Output Port 1.2 (P1.2).
C10
P1.2/TDI/PLAO[15]
DI
JTAG Test Port Input, Test Data In (TDI). The TDI function of Pin C10 is for debug and
download access.
Programmable Logic Array for Output Element 15 (PLAO[15]).
General-Purpose Input and Output Port 3.1 (P3.1).
Programmable Logic Array for Output Element 1 (PLAO[1]).
Reset Input (Active Low).
C11
P3.1/PLAO[1]
I/O
C12
D1
RST
I
P3.2/IRQ4/PWM3/PLAO[2]
I/O
General-Purpose Input and Output Port 3.2 (P3.2).
External Interrupt Request 4, Active High (IRQ4).
Pulse-Width Modulator 3 Output (PWM3).
Programmable Logic Array for Output Element 2 (PLAO[2]).
General-Purpose Input and Output Port 1.1 (P1.1).
Serial Output, Transmit Data, UART (SOUT).
D2
D3
P1.1/SOUT/SDA1/PLAI[6]
P0.3/MISO/PLAO[12]/SYNC
I/O
I/O
I2C Interface Serial Data for I2C1 (SDA1).
Programmable Logic Array for Input Element 6 (PLAI[6]).
General-Purpose Input and Output Port 0.3 (P0.3).
SPI Master In Slave Out (MISO).
Programmable Logic Array for Output Element 12 (PLAO[12]).
Synchronous Reset (SYNC). Input to reset synchronously the PWM counters using an
external source.
D10
D11
P1.3/TDO/PLAO[14]
P0.0/SCL0/PLAI[5]
DO
I/O
General-Purpose Input and Output Port 1.3 (P1.3).
JTAG Test Port Output, Test Data Out (TDO). The TDO function of Pin D10 is for debug
and download access.
Programmable Logic Array for Output Element 14 (PLAO[14]).
General-Purpose Input and Output Port 0.0 (P0.0).
I2C Interface Serial Clock for I2C0 (SCL0).
Programmable Logic Array for Input Element 5 (PLAI[5]).
General-Purpose Input and Output Port 3.6 (P3.6).
Programmable Logic Array for Output Element 10 (PLAO[10]).
General-Purpose Input and Output Port 3.3 (P3.3).
External Interrupt Request 5, Active High (IRQ5).
Pulse-Width Modulator 4 Output (PWM4).
D12
E1
P3.6/PLAO[10]
I/O
I/O
P3.3/IRQ5/PWM4/PLAO[3]
Programmable Logic Array for Output Element 3 (PLAO[3]).
General-Purpose Input and Output Port 3.4 (P3.4).
Programmable Logic Array for Output Element 8 (PLAO[8]).
E2
P3.4/PLAO[8]
I/O
Rev. D | Page 17 of 102
ADuC7120/ADuC7121
Data Sheet
Pin No. Mnemonic
Type1 Description
E3
P0.4/MOSI/PLAI[11]/TRIP
I/O
General-Purpose Input and Output Port 0.4 (P0.4).
SPI Master Out Slave In (MOSI).
Programmable Logic Array for Input Element 11 (PLAI[11]).
PWM Trip Interrupt (TRIP). The TRIP function of Pin E3 is the input that allows the PWM
trip interrupt to be triggered.
E10
E11
TMS
DI
I/O
JTAG Test Port Input, Test Mode Select. Debug and download access.
General-Purpose Input and Output Port 0.1 (P0.1).
I2C Interface Serial Data for I2C0 (SDA0).
P0.1/SDA0/PLAI[4]
Programmable Logic Array for Input Element 4 (PLAI[4]).
General-Purpose Input and Output Port 3.7 (P3.7).
Boot Mode (BM).
E12
P3.7/BM/PLAO[11]
I/O
Programmable Logic Array for Output Element 11 (PLAO[11]).
Digital Ground.
General-Purpose Input and Output Port 3.5 (P3.5).
Programmable Logic Array for Output Element 9 (PLAO[9]).
General-Purpose Input and Output Port 0.5 (P0.5).
F1
F2
DGND
P3.5/PLAO[9]
S
I/O
F3
P0.5/CS/PLAI[10]/ADCCONVST
I/O
SPI Slave Select Input (CS).
Programmable Logic Array for Input Element 10 (PLAI[10]).
ADC Conversions (ADCCONVST). The ADCCONVST function of Pin F3 initiates the ADC
conversions using the PLA or the timer output.
F10
F11
TCK
DI
I/O
JTAG Test Port Input, Test Clock. Debug and download access.
General-Purpose Input and Output Port 2.0 (P2.0).
External Interrupt Request 0, Active High (IRQ0).
P2.0/IRQ0/PLAI[13]
Programmable Logic Array for Input Element 13 (PLAI[13]).
Digital Ground.
Output of 2.6 V On-Chip LDO Regulator. Connect a 470 nF capacitor to DGND to this pin.
Crystal Oscillator Inverter Output. If an external crystal is not used, this pin can remain
unconnected.
F12
G1
G2
DGND
DVDD
XTALO
S
S
DO
G3
P0.6/MRST/PLAI[2]
P0.7/TRST/PLAI[3]
P2.1/IRQ1/PLAI[12]
I/O
I/O
I/O
General-Purpose Input and Output Port 0.6 (P0.6).
Power On Reset Output (MRST).
Programmable Logic Array for Input Element 2 (PLAI[2]).
General-Purpose Input and Output Port 0.7 (P0.7).
JTAG Test Port Input, Test Reset (TRST). Debug and download access.
Programmable Logic Array for Input Element 3 (PLAI[3]).
General-Purpose Input and Output Port 2.1 (P2.1)
External Interrupt Request 1, Active High (IRQ1).
Programmable Logic Array for Input Element 12 (PLAI[12]).
Output of 2.6 V On-Chip LDO Regulator. Connect a 470 nF capacitor to DGND to this pin.
3.3 V GPIO Supply.
G10
G11
G12
H1
H2
DVDD
IOVDD
XTALI
S
S
DI
Crystal Oscillator Inverter Input and Internal Clock Generator Circuits Input. If an
external crystal is not used, connect this pin to the DGND system ground.
H3
P1.4/PWM1/ECLK/XCLK/PLAI[8] I/O
General-Purpose Input and Output Port 1.4 (P1.4).
Pulse-Width Modulator 1 Output (PWM1).
Base System Clock Output (ECLK).
Base System Clock Input (XCLK).
Programmable Logic Array for Input Element 8 (PLAI[8]).
General-Purpose Input and Output Port 2.4 (P2.4).
Pulse-Width Modulator 5 Output (PWM5).
Programmable Logic Array for Output Element 7 (PLAO[7]).
General-Purpose Input and Output Port 2.2 (P2.2).
Programmable Logic Array for Input Element 1 (PLAI[1]).
3.3 V GPIO Supply.
H10
P2.4/PWM5/PLAO[7]
I/O
H11
H12
P2.2/PLAI[1]
IOVDD
I/O
S
Rev. D | Page 18 of 102
Data Sheet
ADuC7120/ADuC7121
Pin No. Mnemonic
Type1 Description
J1
J2
J3
IOGND
DAC2
P1.5/PWM2/PLAI[9]
S
AO
I/O
3.3 V GPIO Ground.
12-Bit DAC2 Output.
General-Purpose Input and Output Port 1.5 (P1.5).
Pulse-Width Modulator 2 Output (PWM2).
Programmable Logic Array for Input Element 9 (PLAI[9]).
General-Purpose Input and Output Port 2.5 (P2.5).
Pulse-Width Modulator 6 Output (PWM6).
Programmable Logic Array for Output Element 6 (PLAO[6]).
General-Purpose Input and Output Port 2.3 (P2.3).
External Interrupt Request 2, Active High (IRQ2).
Programmable Logic Array for Input Element 14 (PLAI[14]).
3.3 V GPIO Ground.
J10
J11
P2.5/PWM6/PLAO[6]
P2.3/IRQ2/PLAI[14]
I/O
I/O
J12
K1
K2
K3
K4
K5
K6
K7
K8
IOGND
DAC0
DAC1
ADC4
ADC1
ADC0
BUF_VREF1
BUF_VREF2
ADC10/AINCM
S
AO
AO
AI
AI
AI
AO
AO
AI
12-Bit DAC0 Output.
12-Bit DAC1 Output.
Single-Ended or Differential Analog Input 4.
Single-Ended or Differential Analog Input 1.
Single-Ended or Differential Analog Input 0.
Buffered 2.5 V. The maximum load for BUF_VREF1 is 1.2 mA.
Buffered 2.5 V. The maximum load for BUF_VREF2 is 1.2 mA.
Single-Ended or Differential Analog Input 10 (ADC10).
Common Mode Analog Input (AINCM). The common-mode function of this pin is for
pseudo differential input.
K9
ADC9
DAC9
DAC10
DAC11
AVDD
DAC3
DAC5
ADC2
VREF_1.2
AI
Single-Ended or Differential Analog Input 9.
12-Bit DAC9 Output.
12-Bit DAC10 Output.
12-Bit DAC11 Output.
Analog Supply (3.3 V).
K10
K11
K12
L1
L2
L3
AO
AO
AO
S
AO
AO
AI
12-Bit DAC3 Output.
12-Bit DAC5 Output.
L4
L5
Single-Ended or Differential Analog Input 3.
1.2 V Reference Output and External 1.2 V Reference Input. Cannot be used to source
current externally.
AI/O
L6
L7
L8
L9
PADC0P
PADC1P
VREF_2.5
ADC8
DAC8
DAC7
AVDD
AGND
DAC4
ADC5
ADC2
PADC0N
AGND
AVDD
PADC1N
ADC7
ADC6
DAC6
AGND
AI
AI
AI/O
AI
AO
AO
S
PGA Channel 0 Positive.
PGA Channel 1 Positive.
2.5 V Reference Output and External 2.5 V Reference Input.
Single-Ended or Differential Analog Input 8.
12-Bit DAC8 Output.
12-Bit DAC7 Output.
Analog Supply (3.3 V).
Analog Ground.
12-Bit DAC4 Output.
Single-Ended or Differential Analog Input 5.
Single-Ended or Differential Analog Input 2.
PGA Channel 0 Negative.
Analog Ground.
Analog Supply (3.3 V).
L10
L11
L12
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
M12
S
AO
AI
AI
AI
S
S
AI
AI
AI
AO
S
PGA Channel 1 Negative.
Single-Ended or Differential Analog Input 7.
Single-Ended or Differential Analog Input 6.
12-Bit DAC6 Output.
Analog Ground.
1 AO is analog output, S is supply, AI is analog input, I/O is input/output, AI/O is analog input/output, DI is digital input, and DO is digital output.
Rev. D | Page 19 of 102
ADuC7120/ADuC7121
Data Sheet
1
2
3
4
5
6
7
8
9 10 11 12
A
B
C
D
E
F
A
B
C
D
E
F
ADuC7121
TOP VIEW
G
H
J
G
H
J
(Not to Scale)
K
K
L
L
M
M
1
2
3
4
5
6
7
8
9 10 11 12
Figure 8. ADuC7121 Pin Configuration
Table 11. ADuC7121 Pin Function Descriptions
Pin No. Mnemonic
Type1 Description
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
B1
IDAC1
AO
S
S
AO
AO
AI
IDAC1 Output. The output for this pin is 200 mA.
Power for IDAC1.
Power for IDAC1.
IDAC1 Output. The output for this pin is 200 mA.
IDAC3 Output. The output for this pin is 80 mA.
Damping Capacitor Pin for IDAC4.
PVDD_IDAC1
PVDD_IDAC1
IDAC1
IDAC3
CDAMP_IDAC4
PVDD_IDAC2
IDAC2
S
2.0 V Power for IDAC2.
AO
AO
S
S
AO
AI
IDAC2 Output. The output for this pin is 45 mA.
IDAC0 Output. The output for this pin is 250 mA.
Power for IDAC0.
Power for IDAC0.
IDAC0 Output. The output for this pin is 250 mA.
Damping Capacitor for IDAC1.
General-Purpose Input and Output Port 1.7 (P1.7).
Programmable Logic Array for Output Element 4 (PLAO[4]).
General-Purpose Input and Output Port 1.6 (P1.6).
Programmable Logic Array for Output Element 5 (PLAO[5]).
Damping Capacitor for IDAC3.
IDAC4 Output. The output for this pin is 20 mA.
Analog Ground.
Output of 2.5 V LDO regulator for internal IDACs. Connect a 470 nF capacitor to AGND
to this pin.
IDAC0
PVDD_IDAC0
PVDD_IDAC0
IDAC0
CDAMP_IDAC1
P1.7/PLAO[4]
B2
I/O
B3
P1.6/PLAO[5]
I/O
B4
B5
B6
B7
CDAMP_IDAC3
IDAC4
AGND
AI
AO
S
AVDD_IDAC
S
B8
B9
IREF
PGND
AI/O
S
Generates Reference Current for IDACs. Set by the external resistor, REXT
Power Ground.
.
B10
B11
B12
C1
PGND
S
AI/O
AI
Power Ground.
IDAC Test Purposes.
Damping Capacitor Pin for IDAC0.
General-Purpose Input and Output Port 2.6 (P2.6).
External Interrupt Request 3, Active High (IRQ3).
Programmable Logic Array for Input Element 15 (PLAI[15]).
General-Purpose Input and Output Port 1.0 (P1.0).
Serial Input, Receive Data, UART (SIN).
I2C Interface Serial Clock for I2C1 (SCL1).
Programmable Logic Array for Input Element 7 (PLAI[7]).
IDAC_TST
CDAMP_IDAC0
P2.6/IRQ3/PLAI[15]
I/O
C2
P1.0/SIN/SCL1/PLAI[7]
I/O
Rev. D | Page 20 of 102
Data Sheet
ADuC7120/ADuC7121
Pin No. Mnemonic
Type1 Description
P0.2/SPICLK/ADCBUSY/PLAO[13] I/O General-Purpose Input and Output Port 0.2 (P0.2).
C3
SPI Clock (SPICLK).
Status of the ADC (ADCBUSY).
Programmable Logic Array for Output Element 13 (PLAO[13]).
General-Purpose Input and Output Port 3.0 (P3.0).
Programmable Logic Array for Output Element 0 (PLAO[0]).
2.0 V Power for the IDAC3.
2.0 V Power for IDAC4.
Analog Supply (3.3 V).
C4
P3.0/PLAO[0]
I/O
C5
C6
C7
C8
C9
PVDD_IDAC3
PVDD_IDAC4
AVDD
CDAMP_IDAC2
P2.7/PLAI[0]
S
S
S
AI
I/O
Damping Capacitor Pin for IDAC2.
General-Purpose Input and Output Port 2.7 (P2.7).
Programmable Logic Array for Input Element 0 (PLAI[0]).
General-Purpose Input and Output Port 1.2 (P1.2).
C10
P1.2/TDI/PLAO[15]
DI
JTAG Test Port Input, Test Data In (TDI). The TDI function of Pin C10 is for debug and
download access.
Programmable Logic Array for Output Element 15 (PLAO[15]).
General-Purpose Input and Output Port 3.1 (P3.1).
Programmable Logic Array for Output Element 1 (PLAO[1]).
Reset Input (Active Low).
C11
P3.1/PLAO[1]
I/O
C12
D1
RST
I
P3.2/IRQ4/PWM3/PLAO[2]
I/O
General-Purpose Input and Output Port 3.2 (P3.2).
External Interrupt Request 4, Active High (IRQ4).
Pulse-Width Modulator 3 Output (PWM3).
Programmable Logic Array for Output Element 2 (PLAO[2]).
General-Purpose Input and Output Port 1.1 (P1.1).
Serial Output, Transmit Data, UART (SOUT).
D2
D3
P1.1/SOUT/SDA1/PLAI[6]
P0.3/MISO/PLAO[12]/SYNC
I/O
I/O
I2C Interface Serial Data for I2C1 (SDA1).
Programmable Logic Array for Input Element 6 (PLAI[6]).
General-Purpose Input and Output Port 0.3 (P0.3).
SPI Master In Slave Out (MISO).
Programmable Logic Array for Output Element 12 (PLAO[12]).
Synchronous Reset (SYNC). Input to reset synchronously the PWM counters using an
external source.
D10
D11
P1.3/TDO/PLAO[14]
P0.0/SCL0/PLAI[5]
DO
I/O
General-Purpose Input and Output Port 1.3 (P1.3).
JTAG Test Port Output, Test Data Out (TDO). The TDO function of Pin D10 is for debug
and download access.
Programmable Logic Array for Output Element 14 (PLAO[14]).
General-Purpose Input and Output Port 0.0 (P0.0).
I2C Interface Serial Clock for I2C0 (SCL0).
Programmable Logic Array for Input Element 5 (PLAI[5]).
General-Purpose Input and Output Port 3.6 (P3.6).
Programmable Logic Array for Output Element 10 (PLAO[10]).
General-Purpose Input and Output Port 3.3 (P3.3).
External Interrupt Request 5, Active High (IRQ5).
Pulse-Width Modulator 4 Output (PWM4).
D12
E1
P3.6/PLAO[10]
I/O
I/O
P3.3/IRQ5/PWM4/PLAO[3]
Programmable Logic Array for Output Element 3 (PLAO[3]).
General-Purpose Input and Output Port 3.4 (P3.4).
Programmable Logic Array for Output Element 8 (PLAO[8]).
General-Purpose Input and Output Port 0.4 (P0.4).
SPI Master Out Slave In (MOSI).
E2
E3
P3.4/PLAO[8]
I/O
I/O
P0.4/MOSI/PLAI[11]/TRIP
Programmable Logic Array for Input Element 11 (PLAI[11]).
PWM Trip Interrupt (TRIP). The TRIP function of Pin E3 is the input that allows the PWM
trip interrupt to be triggered.
E10
TMS
DI
JTAG Test Port Input, Test Mode Select. Debug and download access.
Rev. D | Page 21 of 102
ADuC7120/ADuC7121
Data Sheet
Pin No. Mnemonic
Type1 Description
E11
P0.1/SDA0/PLAI[4]
I/O
General-Purpose Input and Output Port 0.1 (P0.1).
I2C Interface Serial Data for I2C0 (SDA0).
Programmable Logic Array for Input Element 4 (PLAI[4]).
General-Purpose Input and Output Port 3.7 (P3.7).
Boot Mode (BM).
E12
P3.7/BM/PLAO[11]
I/O
Programmable Logic Array for Output Element 11 (PLAO[11]).
Digital Ground.
General-Purpose Input and Output Port 3.5 (P3.5).
Programmable Logic Array for Output Element 9 (PLAO[9]).
General-Purpose Input and Output Port 0.5 (P0.5).
F1
F2
DGND
P3.5/PLAO[9]
S
I/O
F3
P0.5/CS/PLAI[10]/ADCCONVST
I/O
SPI Slave Select Input (CS).
Programmable Logic Array for Input Element 10 (PLAI[10]).
ADC Conversions (ADCCONVST). The ADCCONVST function of Pin F3 initiates the ADC
conversions using the PLA or the timer output.
F10
F11
TCK
DI
I/O
JTAG Test Port Input, Test Clock. Debug and download access.
General-Purpose Input and Output Port 2.0 (P2.0).
P2.0/IRQ0/PLAI[13]
External Interrupt Request 0, Active High (IRQ0).
Programmable Logic Array for Input Element 13 (PLAI[13]).
Digital Ground.
Output of 2.6 V On-Chip LDO Regulator. Connect a 470 nF capacitor to DGND this pin.
Crystal Oscillator Inverter Output. If an external crystal is not being used, this pin can
remain unconnected.
F12
G1
G2
DGND
DVDD
XTALO
S
S
DO
G3
P0.6/MRST/PLAI[2]
P0.7/TRST/PLAI[3]
P2.1/IRQ1/PLAI[12]
I/O
I/O
I/O
General-Purpose Input and Output Port 0.6 (P0.6).
Power On Reset Output (MRST).
Programmable Logic Array for Input Element 2 (PLAI[2]).
General-Purpose Input and Output Port 0.7 (P0.7).
JTAG Test Port Input, Test Reset (TRST). Debug and download access.
Programmable Logic Array for Input Element 3 (PLAI[3]).
General-Purpose Input and Output Port 2.1 (P2.1)
External Interrupt Request 1, Active High (IRQ1).
Programmable Logic Array for Input Element 12 (PLAI[12]).
Output of 2.6 V On-Chip LDO Regulator. Connect a 470 nF capacitor to DGND to this pin.
3.3 V GPIO Supply.
G10
G11
G12
H1
H2
DVDD
IOVDD
XTALI
S
S
DI
Crystal Oscillator Inverter Input and Internal Clock Generator Circuits Input. If an
external crystal is not being used, connect this pin to the DGND system ground.
H3
P1.4/PWM1/ECLK/XCLK/PLAI[8] I/O
General-Purpose Input and Output Port 1.4 (P1.4).
Pulse-Width Modulator 1 Output (PWM1).
Base System Clock Output (ECLK).
Base System Clock Input (XCLK).
Programmable Logic Array for Input Element 8 (PLAI[8]).
General-Purpose Input and Output Port 2.4 (P2.4).
Pulse-Width Modulator 5 Output (PWM5).
Programmable Logic Array for Output Element 7 (PLAO[7]).
General-Purpose Input and Output Port 2.2 (P2.2).
Programmable Logic Array for Input Element 1 (PLAI[1]).
3.3 V GPIO Supply.
H10
H11
P2.4/PWM5/PLAO[7]
P2.2/PLAI[1]
I/O
I/O
H12
J1
IOVDD
IOGND
S
S
3.3 V GPIO Ground.
J2
J3
DNC
DNC
I/O
No Connect. Do not connect to this pin.
General-Purpose Input and Output Port 1.5 (P1.5).
Pulse-Width Modulator 2 Output (PWM2).
Programmable Logic Array for Input Element 9 (PLAI[9]).
P1.5/PWM2/PLAI[9]
Rev. D | Page 22 of 102
Data Sheet
ADuC7120/ADuC7121
Pin No. Mnemonic
Type1 Description
J10
P2.5/PWM6/PLAO[6]
I/O
General-Purpose Input and Output Port 2.5 (P2.5).
Pulse-Width Modulator 6 Output (PWM6).
Programmable Logic Array for Output Element 6 (PLAO[6]).
General-Purpose Input and Output Port 2.3 (P2.3).
External Interrupt Request 2, Active High (IRQ2).
Programmable Logic Array for Input Element 14 (PLAI[14]).
3.3 V GPIO Ground.
J11
P2.3/IRQ2/PLAI[14]
I/O
J12
L1
L2
L3
L4
L5
IOGND
AVDD
DNC
DNC
DNC
S
S
DNC
DNC
DNC
AI/O
Analog Supply (3.3 V).
Do Not Connect. Do not connect to this pin.
Do Not Connect. Do not connect to this pin.
Do Not Connect. Do not connect to this pin.
1.2 V Reference Output and External 1.2 V Reference Input. Cannot be used to source
current externally.
VREF_1.2
L6
L7
L8
L9
PADC0P
PADC1P
VREF_2.5
ADC8
DNC
DNC
AVDD
DAC0
DAC1
ADC4
DNC
DNC
BUF_VREF1
BUF_VREF2
ADC10/AINCM
AI
AI
PGA Channel 0 Positive.
PGA Channel 1 Positive.
AI/O
AI
DNC
DNC
S
AO
AO
AI
DNC
DNC
AO
AO
AI
2.5 V Reference Output and External 2.5 V Reference Input.
Single-Ended or Differential Analog Input 8.
Do Not Connect. Do not connect to this pin.
Do Not Connect. Do not connect to this pin.
Analog Supply (3.3 V).
L10
L11
L12
K1
K2
K3
K4
K5
K6
K7
K8
12-Bit DAC0 Output.
12-Bit DAC1 Output.
Single-Ended or Differential Analog Input 4.
Do Not Connect. Do not connect to this pin.
Do Not Connect. Do not connect to this pin.
Buffered 2.5 V. The maximum load for BUF_VREF1 is 1.2 mA.
Buffered 2.5 V. The maximum load for BUF_VREF2 is 1.2 mA.
Single-Ended or Differential Analog Input 10 (ADC10).
Common-Mode Analog Input (AINCM). The common-mode function of this pin is for
pseudo differential input.
K9
ADC9
DNC
DNC
DAC3
AGND
DNC
ADC5
DNC
PADC0N
AGND
AVDD
PADC1N
ADC7
ADC6
DAC2
AGND
AI
Single-Ended or Differential Analog Input 9.
Do Not Connect. Do not connect to this pin.
Do Not Connect. Do not connect to this pin.
12-Bit DAC3 Output.
K10
K11
K12
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
M12
DNC
DNC
AO
S
DNC
AI
DNC
AI
S
S
AI
AI
AI
Analog Ground.
Do Not Connect. Do not connect to this pin.
Single-Ended or Differential Analog Input 5.
Do Not Connect. Do not connect to this pin.
PGA Channel 0 Negative.
Analog Ground.
Analog Supply (3.3 V).
PGA Channel 1 Negative.
Single-Ended or Differential Analog Input 7.
Single-Ended or Differential Analog Input 6.
12-Bit DAC2 Output.
AO
S
Analog Ground.
1 AO is analog output, S is supply, AI is analog input, I/O is input/output, AI/O is analog input/output, DI is digital input, DO is digital output, and DNC is do not connect.
Rev. D | Page 23 of 102
ADuC7120/ADuC7121
Data Sheet
TERMINOLOGY
The ratio is dependent on the number of quantization levels in
the digitization process: the more levels there are, the smaller
the quantization noise becomes.
ADC SPECIFICATIONS
Integral Nonlinearity
Integral nonlinearity (INL) is the maximum deviation of any
code from a straight line passing through the endpoints of the
ADC transfer function. The endpoints of the transfer function
are zero scale, a point ½ LSB below the first code transition, and
full scale, a point ½ LSB above the last code transition.
The theoretical SINAD ratio for an ideal N-bit converter with a
sine wave input is given by
SINAD = (6.02 N + 1.76) dB
Therefore, for a 12-bit converter, this is 74 dB.
Differential Nonlinearity
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the rms sum of
the harmonics to the fundamental.
Differential nonlinearity (DNL) is the difference between the
measured and the ideal 1 LSB change between any two adjacent
codes in the ADC.
DAC SPECIFICATIONS
Offset Error
Relative Accuracy
Offset error is the deviation of the first code transition (0000 …
000) to (0000 … 001) from the ideal, that is, +½ LSB.
Otherwise known as endpoint linearity, relative accuracy is a
measure of the maximum deviation from a straight line passing
through the endpoints of the DAC transfer function. It is
measured after adjusting for zero error and full-scale error.
Gain Error
Gain error is the deviation of the last code transition from the
ideal analog input (AIN) voltage (full scale − 1.5 LSB) after the
offset error has been adjusted out.
Voltage Output Settling Time
Voltage output settling time is the amount of time it takes the
output to settle to within a one LSB level for a full-scale input
change.
Signal-to-Noise-and-Distortion Ratio
Signal-to-noise-and-distortion ratio (SINAD) is the measured
ratio of signal to noise and distortion at the output of the ADC.
The signal is the rms amplitude of the fundamental. Noise is the
rms sum of all nonfundamental signals up to half the sampling
frequency (fS/2), excluding dc.
Rev. D | Page 24 of 102
Data Sheet
ADuC7120/ADuC7121
OVERVIEW OF THE ARM7TDMI CORE
The ARM7™ core is a 32-bit reduced instruction set computer
(RISC). It uses a single 32-bit bus for instruction and data. The
length of the data can be 8 bits, 16 bits, or 32 bits. The length of
the instruction word is 32 bits.
LONG MULTIPLY (M)
The ARM7TDMI instruction set includes four extra
instructions that perform 32-bit by 32-bit multiplication with a
64-bit result, and 32-bit by 32-bit multiplication accumulation
(MAC) with a 64-bit result. These results are achieved in fewer
cycles than required on a standard ARM7 core.
The ARM7TDMI® is an ARM7 core with four additional
features, as follows:
•
•
•
•
T support for the thumb (16-bit) instruction set
D support for debug
M support for long multiplications
I includes the EmbeddedICE™ module to support
embedded system debugging
EmbeddedICE (I)
EmbeddedICE provides integrated on-chip support for the core.
The EmbeddedICE module contains the breakpoint and watch-
point registers that halts code for debugging purposes. These
registers are controlled through the JTAG test port.
When a breakpoint or watchpoint is encountered, the processor
halts and enters a debug state. When in a debug state, the
breakpoint and watchpoint registers can be inspected, as well
as the Flash/EE, static random access memory (SRAM), and
memory mapped registers.
THUMB (T) MODE
An ARM® instruction is 32 bits long. The ARM7TDMI processor
supports a second instruction set that has been compressed into
16 bits, the Thumb® instruction set. Faster execution from 16-bit
memory and greater code density can usually be achieved by
using the Thumb instruction set instead of the ARM instruction
set, which makes the ARM7TDMI core suitable for embedded
applications.
EXCEPTIONS
ARM supports five types of exceptions and a privileged
processing mode for each type. The five exception types include
the following:
However, the Thumb mode has the following two limitations:
•
Normal interrupt (IRQ) can service general-purpose
interrupt handling of internal and external events.
Fast interrupt (FIQ) can service data transfers or
communication channels with low latency.; FIQ has
priority over IRQ.
•
•
Thumb code typically requires more instructions for the
same job. As a result, ARM code is usually best for
maximizing the performance of time critical code.
The Thumb instruction set does not include some of the
instructions needed for exception handling, which
automatically switches the core to ARM code for exception
handling.
•
•
•
•
Memory abort.
Attempted execution of an undefined instruction.
Software interrupt instruction (SWI) can make a call to an
operating system.
See the ADuC7XXX Microconverter™ Get Started Guide for
details on the core architecture, the programming model, and
both the ARM and ARM Thumb instruction sets.
Typically, the programmer defines interrupt as IRQ, but for
higher priority interrupt, that is, faster response time, the
programmer can define interrupt as FIQ.
Rev. D | Page 25 of 102
ADuC7120/ADuC7121
Data Sheet
ARM REGISTERS
INTERRUPT LATENCY
ARM7TDMI has a total of 37 registers: 31 general-purpose
registers and 6 status registers. Each operating mode has
dedicated banked registers.
The worst case latency for a FIQ consists of the following:
•
The longest time the request can take to pass through the
synchronizer.
When writing user level programs, 15 general-purpose 32-bit
registers (R0 to R14), the program counter (R15), and the current
program status register (CPSR) are usable. The remaining
registers are used for system level programming and exception
handling only.
•
The time for the longest instruction to complete (the
longest instruction is a load multiple (LDM)) that loads all
the registers including the PC.
The time for the data abort entry.
The time for FIQ entry.
•
•
When an exception occurs, some of the standard registers are
replaced with registers specific to the exception mode. All
exception modes have replacement banked registers for the
stack pointer (R13) and the link register (R14) as represented
in Figure 9. The fast interrupt mode has more registers (R8 to
R12) for fast interrupt processing, which means that interrupt
processing can begin without the need to save or restore these
registers, thus saving critical time in the interrupt handling
process.
At the end of this time, the ARM7TDMI executes the instruction at
0x1C (FIQ interrupt vector address). The maximum total time
is 50 processor cycles, which is just under 1.2 µs in a system
using a continuous 41.78 MHz processor clock.
The maximum IRQ latency calculation is similar but must allow
the fact that FIQ has higher priority and can delay entry into
the IRQ handling routine for an arbitrary length of time. This
time can be reduced to 42 cycles if the LDM command is not
used. Some compilers have an option to compile without using this
command. Another option is to run the devices in thumb mode
wherein the time is reduced to 22 cycles.
R0
R1
USABLE IN USER MODE
SYSTEM MODES ONLY
R2
R3
The minimum latency for FIQ or IRQ interrupts is five cycles,
which consist of the shortest time the request can take through
the synchronizer plus the time to enter the exception mode.
R4
R5
R6
R7
R8_FIQ
R9_FIQ
R8
The ARM7TDMI always runs in ARM (32-bit) mode when in
privileged modes, for example, when executing interrupt
service routines.
R9
R10_FIQ
R11_FIQ
R12_FIQ
R13_FIQ
R14_FIQ
R10
R11
R12
R13
R14
R15 (PC)
R13_UND
R13_IRQ
R13_ABT
R14_ABT
R14_UND
R14_IRQ
R13_SVC
R14_SVC
SPSR_UND
SPSR_IRQ
SPSR_ABT
SPSR_SVC
CPSR
SPSR_FIQ
FIQ
MODE
SVC
MODE
ABORT
MODE
IRQ
MODE
UNDEFINED
MODE
USER MODE
Figure 9. Register Organization
More information relative to the model of the programmer and
the ARM7TDMI core architecture can be found in the following
materials from ARM, Ltd.:
•
•
ARM DDI 0029G, ARM7TDMI Technical Reference Manual
ARM DDI 0100, ARM Architecture Reference Manual
Rev. D | Page 26 of 102
Data Sheet
ADuC7120/ADuC7121
MEMORY ORGANIZATION
The ADuC7120/ADuC7121 incorporate three separate blocks
of memory: 8 kB of SRAM and two 64 kB of on-chip Flash/EE
memory. There are 126 kB of on-chip Flash/EE memory available
to the user, and the remaining 2 kB are reserved for the factory-
configured boot page. These two blocks are mapped as shown
in Figure 10.
FLASH/EE MEMORY
The 128 kB of Flash/EE are organized as two banks of 32k ×
16 bits. Block 0 starts at Address 0x90000 and finishes at
Address 0x9F700. In this block, 31k × 16 bits is user space and
1k × 16 bits are reserved for the factory configured boot page.
The page size of this Flash/EE memory is 512 bytes.
By default, after a reset, the Flash/EE memory is mirrored at
Address 0x00000000. It is possible to remap the SRAM at
Address 0x00000000 by clearing Bit 0 of the remap MMR. This
remap function is described in more detail in the Flash/EE
Memory section.
Block 1 starts at Address 0x80000 and finishes at Address 0x90000.
In this block, the 64 kB block is arranged in 32k × 16 bits, all of
which are available as user space.
The 126 kB of Flash/EE are available to the user as code and
nonvolatile data memory. There is no distinction between data
and program because ARM code shares the same space. The
real width of the Flash/EE memory is 16 bits, meaning that in
ARM mode (32-bit instruction), two accesses to the Flash/EE
are necessary for each instruction fetch. Therefore, it is
recommended that thumb mode be used when executing from
Flash/EE memory for optimum access speed. The maximum
access speed for the Flash/EE memory is 41.78 MHz in thumb
mode and 20.89 MHz in full ARM mode (see the Execution
Time from SRAM and Flash/EE section).
0xFFFFFFFF
MMRs
0xFFFF0000
RESERVED
0x0009F800
FLASH/EE
0x00080000
RESERVED
0x00041FFF
SRAM
0x00040000
RESERVED
0x0001FFFF
SRAM
The 8 kB of SRAM are available to the user, organized as 2k ×
32 bits, that is, 2k words. ARM code can run directly from
SRAM at 41.78 MHz, given that the SRAM array is configured
as a 32-bit wide memory array (see the Execution Time from
SRAM and Flash/EE section).
REMAPPABLE MEMORY SPACE
(FLASH/EE OR SRAM)
0x00000000
Figure 10. Physical Memory Map
MEMORY ACCESS
MEMORY MAPPED REGISTERS (MMR)
The ARM7 core sees memory as a linear array of 232 byte
locations where the different blocks of memory are mapped as
outlined in Figure 10.
The MMR space is mapped into the upper two pages of the
memory array and accessed by indirect addressing through the
ARM7 banked registers.
The ADuC7120/ADuC7121 memory organization is configured
in little endian format: the LSB is located in the lowest byte
address, and the MSB is located in the highest byte address.
The MMR space provides an interface between the central
processing unit (CPU) and all on-chip peripherals. All registers,
except the core registers, reside in the MMR area. All shaded
locations shown in Figure 12 are unoccupied or reserved
locations that must not be accessed by user software. Table 12
through Table 29 provide the complete MMR memory maps.
BIT 31
BIT 0
BYTE 3 BYTE 2 BYTE 1 BYTE 0
.
.
.
.
.
.
.
.
.
.
.
.
0xFFFFFFFF
B
7
3
A
6
2
9
5
1
8
4
0
The access time reading or writing an MMR depends on the
advanced microcontroller bus architecture (AMBA) bus used
to access the peripheral. The processor has two AMBA buses:
the advanced high performance bus (AHB) used for system
modules, and the advanced peripheral bus (APB) used for a lower
performance peripheral. Access to the AHB is one cycle, and
access to the APB is two cycles. All peripherals on the ADuC7120/
ADuC7121 are on the APB except the Flash/EE memory and
the GPIOs.
0x00000004
0x00000000
32 BITS
Figure 11. Little Endian Format
Rev. D | Page 27 of 102
ADuC7120/ADuC7121
Data Sheet
Address
0x0038
0x003C
0x0100
0x0104
0x0108
0x010C
0x011C
0x013C
Name
Byte
Access Type
Cycle
0xFFFF0746
IRQCLRE
IRQSTAN
FIQSTA
FIQSIG
1
1
4
4
4
4
4
1
W
R/W
R
R
R/W
W
1
1
1
1
1
1
1
1
IDAC
0xFFFF0700
0xFFFF05DF
DAC
0xFFFF0580
FIQEN
0xFFFF0524
ADC
0xFFFF0500
FIQCLR
FIQVEC
FIQSTAN
0xFFFFFFFF
R
R/W
0xFFFF04A8
0xFFFF0480
0xFFFF0FBC
0xFFFF0F80
BAND GAP
REFERENCE
PWM
Table 13. Remap and System Control Base Address =
0xFFFF0200
0xFFFF0448
0xFFFF0440
0xFFFF0EA8
0xFFFF0E80
POWER SUPPLY
MONITOR
FLASH CONTROL
INTERFACE 1
Address
0x0220
0x0230
0x0234
0x0248
0x024C
0x0250
Name
Byte
Access Type
Cycle
REMAP
RSTSTA
RSTCLR
RSTCFGKEY0
RSTCFG
1
1
1
1
1
1
R/W
R
W
W
R/W
W
1
1
1
1
1
1
0xFFFF0418
0xFFFF0400
0xFFFF0E28
0xFFFF0E00
PLL AND
OSCILLATOR
CONTROL
FLASH CONTROL
INTERFACE 0
0xFFFF0D78
0xFFFF0D00
0xFFFF0394
0xFFFF0380
GENERAL-PURPOSE
TIMER 4
GPIO
PLA
RSTCFGKEY1
0xFFFF0B54
0xFFFF0B00
0xFFFF0370
0xFFFF0360
WATCHDOG
TIMER
Table 14. Timer Base Address = 0xFFFF0300
Address
0x0300
0x0304
0x0308
0x030C
0x0310
0x0314
0x0320
0x0324
0x0328
0x032C
0x0330
0x0340
0x0344
0x0348
0x034C
0x0360
0x0364
0x0368
0x036C
0x0380
0x0384
0x0388
0x038C
0x0390
Name
Byte
Access Type
Cycle
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
0xFFFF0350
0xFFFF0340
0xFFFF0A14
0xFFFF0A00
WAKE-UP
TIMER
T0LD
2
2
4
4
1
2
4
4
4
1
4
4
4
4
1
2
2
2
1
4
4
4
1
4
R/W
R
R
R/W
W
R
R/W
R
R/W
W
R
R/W
R
R/W
W
R/W
SPI
T0VAL0
T0VAL1
T0CON
T0CLRI
T0CAP
T1LD
T1VAL
T1CON
T1CLRI
T1CAP
T2LD
T2VAL
T2CON
T2CLRI
T3LD
T3VAL
T3CON
T3CLRI
T4LD
0xFFFF0334
0xFFFF0320
0xFFFF0950
0xFFFF0900
GENERAL-PURPOSE
TIMER
2
I C1
0xFFFF0318
0xFFFF0300
0xFFFF08D0
0xFFFF0880
2
TIMER 0
I C0
0xFFFF082C
0xFFFF0800
0xFFFF0240
0xFFFF0200
REMAP AND
SYSTEM CONTROL
UART0
0xFFFF013C
0xFFFF0000
INTERRUPT
CONTROLLER
Figure 12. Memory Mapped Registers
COMPLETE MMR LISTING
The Access Type column corresponds to the access time reading
or writing an MMR, where R is read, W is write, and R/W is read/
write. It depends on the AMBA bus that accesses the peripheral.
The processor has two AMBA buses: AHB used for system
modules, and APB used for lower performance peripherals.
Table 12. IRQ Base Address = 0xFFFF0000
R
R/W one time only
W
R/W
R
R/W
W
T4VAL
T4CON
T4CLRI
T4CAP
Address
0x0000
0x0004
0x0008
0x000C
0x0010
0x0014
0x001C
0x0020
0x0024
0x0028
0x002C
0x0030
0x0034
Name
Byte
Access Type
Cycle
IRQSTA
IRQSIG
IRQEN
IRQCLR
SWICFG
IRQBASE
IRQVEC
IRQP0
IRQP1
IRQP2
IRQP3
IRQCONN
IRQCONE
4
4
4
4
4
4
4
4
4
4
4
1
R
R
R/W
W
W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
1
1
1
1
1
1
1
1
1
1
1
1
R
Table 15. PLL and Oscillator Control Base Address =
0xFFFF0400
Address
0x0404
0x0408
0x040C
0x0410
0x0414
0x0418
Name
Byte
Access Type
Cycle
POWKEY1
POWCON
POWKEY2
PLLKEY1
PLLCON
PLLKEY2
2
1
2
2
1
2
W
R/W
W
W
R/W
W
2
2
2
2
2
2
4
Rev. D | Page 28 of 102
Data Sheet
ADuC7120/ADuC7121
Table 16. PSM Base Address = 0xFFFF0440
Table 21. UART0 Base Address = 0xFFFF0800
Address
Name
Byte
Access Type
Cycle
Address
Name
Byte
Access Type
Cycle
0x0440
PSMCON
2
R/W
2
0x0800
COMTX
COMRX
1
1
1
1
1
1
1
1
1
2
W
R
2
2
2
2
2
2
2
2
2
2
Table 17. Band Gap Reference Base Address = 0xFFFF0480
Address
COMDIV0
COMIEN0
COMDIV1
COMIID0
COMCON0
COMCON1
COMSTA0
COMDIV2
R/W
R/W
R/W
R
R/W
R/W
R
Name
Byte
Access Type
Cycle
0x0804
0x0480
REFCON
1
R/W
2
0x0808
0x080C
0x0810
0x0814
0X082C
Table 18. ADC Base Address = 0xFFFF0500
Address
0x0500
0x0504
0x0508
0x050C
0x0510
0x0514
0x0518
0x051C
0x0520
Name
Byte
Access Type
Cycle
ADCCON
ADCCP
ADCCN
ADCSTA
ADCDAT
ADCRST
ADCGN
ADCOF
PGA_GN
4
1
1
1
4
1
2
2
2
R/W
R/W
R/W
R
R
W
R/W
R/W
R/W
2
2
2
2
2
2
2
2
2
R/W
Table 22. I2C0 Base Address = 0xFFFF0880
Address
0x0880
0x0884
0x0888
0x088C
0x0890
0x0894
0x0898
0x089C
0x08A0
0x08A4
0x08A8
0x08AC
0x08B0
0x08B4
0x08B8
0x08BC
0x08C0
0x08C4
0x08C8
0x08CC
Name
Byte
Access Type
R/W
R
R
W
Cycle
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
I2C0MCTL
I2C0MSTA
I2C0MRX
I2C0MTX
I2C0MCNT0
I2C0MCNT1
I2C0ADR0
I2C0ADR1
I2C0SBYTE
I2C0DIV
I2C0SCTL
I2C0SSTA
I2C0SRX
I2C0STX
I2C0ALT
I2C0ID0
2
2
1
2
2
1
1
1
1
2
2
2
1
1
1
1
R/W
R
Table 19. DAC Base Address = 0xFFFF0580
Address
0x0580
0x0584
0x0588
0x058C
0x05B0
0x05B4
0x05D8
0x05DC
Name
Byte
Access Type
Cycle
R/W
R/W
R/W
R/W
R/W
R
DAC0CON
DAC0DAT
DAC1CON
DAC1DAT
DAC2CON
DAC2DAT
DAC3CON
DAC3DAT
2
4
2
4
2
4
2
4
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
2
2
2
2
2
2
2
2
R
W
R/W
R/W
R/W
R/W
R/W
R/W
Table 20. IDAC Base Address = 0xFFFF0700
Address Name Byte Access Type Cycle
IDAC0CON
I2C0ID1
I2C0ID2
I2C0ID3
I2C0FSTA
1
1
1
1
2
2
2
2
0x0700
0x0704
0x0708
0x070C
0x0710
0x0714
0x0718
0x071C
0x0720
0x0724
0x0728
0x072C
0x0730
0x0734
0x0738
0x073C
0x0740
0x0744
2
4
1
2
4
1
2
4
1
2
4
1
2
4
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
IDAC0DAT
IDAC0BW
IDAC1CON
IDAC1DAT
IDAC1BW
IDAC2CON
IDAC2DAT
IDAC2BW
IDAC3CON
IDAC3DAT
IDAC3BW
IDAC4CON
IDAC4DAT
IDAC4BW
TSDCON
Table 23. I2C1 Base Address = 0xFFFF0900
Address
0x0900
0x0904
0x0908
0x090C
0x0910
0x0914
0x0918
0x091C
0x0920
0x0924
0x0928
0x092C
0x0930
0x0934
0x0938
0x093C
Name
Byte
Access Type
Cycle
I2C1MCTL
I2C1MSTA
I2C1MRX
I2C1MTX
I2C1MCNT0
I2C1MCNT1
I2C1ADR0
I2C1ADR1
I2C1SBYTE
I2C1DIV
I2C1SCTL
I2C1SSTA
I2C1SRX
I2C1STX
I2C1ALT
2
2
1
2
2
1
1
1
1
2
2
2
1
1
1
1
R/W
R
R
W
R/W
R
R/W
R/W
R/W
R/W
R/W
R
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
IDACSTA
IDAC0PULLDOWN
R
W
R/W
R/W
I2C1ID0
Rev. D | Page 29 of 102
ADuC7120/ADuC7121
Data Sheet
Address
0x0940
0x0944
0x0948
0x094C
Name
Byte
Access Type
R/W
R/W
R/W
R/W
Cycle
Address
0x0D44
0x0D48
0x0D4C
0x0D50
0x0D54
0x0D58
0x0D5C
Name
Byte Access Type
Cycle
I2C1ID1
I2C1ID2
I2C1ID3
I2C1FSTA
1
1
1
1
2
2
2
2
GP2SET
GP2CLR
GP2PAR
GP3DAT
GP3SET
GP3CLR
GP3PAR
1
1
4
4
1
1
4
W
W
R/W
R/W
W
1
1
1
1
1
1
1
Table 24. SPI Base Address = 0xFFFF0A00
W
R/W
Address
0x0A00
0x0A04
0x0A08
0x0A0C
0x0A10
Name
SPISTA
SPIRX
SPITX
SPIDIV
SPICON
Byte Access Type
Cycle
2
1
1
1
2
R
R
W
R/W
R/W
2
2
2
2
2
Table 27. Flash/EE Block 0 Base Address = 0xFFFF0E00
Address
0x0E00
0x0E04
0x0E08
0x0E0C
0x0E10
0x0E18
0x0E1C
0x0E20
Name
Byte Access Type
Cycle
FEE0STA
FEE0MOD
FEE0CON
FEE0DAT
FEE0ADR
FEE0SGN
FEE0PRO
FEE0HID
1
1
1
2
2
3
4
4
R
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R
Table 25. PLA Base Address = 0xFFFF0B00
Address
0x0B00
0x0B04
0x0B08
0x0B0C
0x0B10
0x0B14
0x0B18
0x0B1C
0x0B20
0x0B24
0x0B28
0x0B2C
0x0B30
0x0B34
0x0B38
0x0B3C
0x0B40
0x0B44
0x0B48
0x0B4C
0x0B50
0x0B54
Name
Byte Access Type
Cycle
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
PLAELM0
PLAELM1
PLAELM2
PLAELM3
PLAELM4
PLAELM5
PLAELM6
PLAELM7
PLAELM8
PLAELM9
PLAELM10
PLAELM11
PLAELM12
PLAELM13
PLAELM14
PLAELM15
PLACLK
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1
2
4
4
4
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
R/W
Table 28. Flash/EE Block 1 Base Address = 0xFFFF0E80
Address
0x0E80
0x0E84
0x0E88
0x0E8C
0x0E90
0x0E98
0x0E9C
0x0EA0
Name
Byte Access Type
Cycle
FEE1STA
FEE1MOD
FEE1CON
FEE1DAT
FEE1ADR
FEE1SGN
FEE1PRO
FEE1HID
1
1
1
2
2
3
4
4
R
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R
R/W
R/W
Table 29. PWM Base Address= 0xFFFF0F80
Address
0x0F80
0x0F84
0x0F88
0x0F8C
0x0F90
0x0F94
0x0F98
0x0F9C
0x0FA0
0x0FA4
0x0FA8
0x0FAC
0x0FB0
0x0FB4
0x0FB8
Name
Byte Access Type
Cycle
2
2
2
2
2
2
PWMCON1
PWM1COM1
PWM1COM2
PWM1COM3
PWM1LEN
PWM2COM1
PWM2COM2
PWM2COM3
PWM2LEN
PWM3COM1
PWM3COM2
PWM3COM3
PWM3LEN
PWMCON2
PWMICLR
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
PLAIRQ
PLAADC
PLADIN
PLADOUT
PLALCK
W
Table 26. GPIO Base Address = 0xFFFF0D00
Address
0x0D00
0x0D04
0x0D08
0x0D0C
0x0D20
0x0D24
0x0D28
0x0D2C
0x0D30
0x0D34
0x0D38
0x0D3C
0x0D40
Name
Byte Access Type
Cycle
GP0CON
GP1CON
GP2CON
GP3CON
GP0DAT
GP0SET
GP0CLR
GP0PAR
GP1DAT
GP1SET
GP1CLR
GP1PAR
GP2DAT
4
4
4
4
4
1
1
4
4
1
1
4
4
R/W
R/W
R/W
R/W
R/W
W
1
1
1
1
1
1
1
1
1
1
1
1
1
W
R/W
R/W
W
W
R/W
R/W
Rev. D | Page 30 of 102
Data Sheet
ADuC7120/ADuC7121
ADC CIRCUIT OVERVIEW
The ADC incorporates a fast, multichannel, 12-bit ADC. It can
operate from a 3.0 V to 3.6 V supply and is capable of providing a
throughput of up to 1 MSPS when the clock source is 41.78 MHz.
This block provides the user with a multichannel multiplexer, a
differential track-and-hold amplifier, an on-chip reference, and
an ADC.
The PADC0x and PADC1x inputs connect to a PGA and allow a
gain from 1 to 5 with 32 steps. The remaining channels can be
configured as single-ended or differential. A buffer is provided
before the ADC for measuring internal channels.
ADC TRANSFER FUNCTION
Pseudo Differential and Single-Ended Modes
The ADC consists of a 12-bit successive approximation converter
based around two capacitor DACs. Depending on the input
signal configuration, the ADC can operate in one of the
following three modes:
For both pseudo differential and single-ended modes, the input
range is 0 to VREF. In addition, the output coding is straight
binary in both pseudo differential and single-ended modes
with 1 LSB = FS/4096, 2.5 V/4096 = 0.61 mV, or 610 μV when
Fully differential mode for small and balanced signals.
Single-ended mode for any single-ended signals.
Pseudo differential mode for any single-ended signals,
taking advantage of the common-mode rejection offered
by the pseudo differential input.
VREF = 2.5 V.
The ideal code transitions occur midway between successive
integer LSB values (that is, 1/2 LSB, 3/2 LSBs, 5/2 LSBs, …,
FS − 3/2 LSBs). e ideal input/output transfer characteristics
are shown in Figure 14.
The converter accepts an analog input range of 0 V to VREF
when operating in single-ended mode or pseudo differential
mode. In fully differential mode, the input signal must be balanced
around a common-mode voltage (VCM) in the 0 V to AVDD range
and with a maximum amplitude of 2 × VREF (see Figure 13).
1111 1111 1111
1111 1111 1110
1111 1111 1101
1111 1111 1100
FS
1LSB =
4096
AV
DD
V
2 × V
CM
REF
0000 0000 0011
0000 0000 0010
0000 0000 0001
0000 0000 0000
V
CM
2 × V
REF
V
2 × V
CM
REF
0V 1LSB
+FS – 1LSB
0
VOLTAGE INPUT
Figure 13. Examples of Balanced Signals for Fully Differential Mode
Figure 14. ADC Transfer Function in Pseudo Differential Mode or
Single-Ended Mode
A high precision, low drift, and factory calibrated 2.5 V reference
is provided on chip. An external reference can also be connected
as described in the Band Gap Reference section.
Fully Differential Mode
The amplitude of the differential signal is the difference between
the signals applied to the VIN+ and VIN− inputs (that is, VIN+
−
Single or continuous conversion modes can be initiated in the
software. An external ADCCONVST pin, an output generated from
VIN−). Therefore, the maximum amplitude of the differential
signal is −VREF to +VREF p-p (2 × VREF), regardless of the CM.
CM is the average of the two signals (VIN+ + VIN−)/2 and is
therefore the voltage that the two inputs are centered on, which
the on-chip PLA, a Timer0, or a Timer1 overflow can also
generate a repetitive trigger for ADC conversions.
If the signal is not deasserted by the time the ADC conversion
completes, a second conversion begins automatically. A voltage
output from an on-chip, band gap reference proportional to
absolute temperature can also be routed through the front-end
ADC multiplexer, effectively creating an additional ADC channel
input. This action facilitates an internal temperature sensor
channel, measuring die temperature to an accuracy of 3ꢀC.
results in the span of each input being CM
VREF/2. This voltage
must be set up externally, and its range varies with VREF (see the
Driving the Analog Inputs section).
The output coding is twos complement in fully differential
mode with 1 LSB = 2 × VREF/4096 or 2 × 2.5 V/4096 = 1.22 mV
when VREF = 2.5 V
The ADuC7120/ADuC7121 are modified to differentiate their
ADC structure from other devices in the device family.
Rev. D | Page 31 of 102
ADuC7120/ADuC7121
Data Sheet
The output result is ±±± ꢀits; however, it shifts ꢀy one ꢀit to the
right, allowing the result in ADCDAT to ꢀe declared as a signed
integer when writing C code. The designed code transitions occur
midway ꢀetween successive integer LSB values (that is, ±/2 LSB,
3/2 LSBs, 5/2 LSBs, …, FS − 3/2 LSBs). The ideal input and
output transfer characteristics are shown in Figure ±5.
4. Set the ADC to pseudo differential mode in
Register ADCCON, Bits[4:3].
5. Start the conversion.
EXTERNAL
PADC0P
0.15V
BUFFER BYPASS
SWITCH
0.1%,
1nF
SIGN
BIT
ADCCON[15]
5ppm
VREF_EXT
VREF_INT
0
0
0
1111 1111 1110
1111 1111 1100
1111 1111 1010
PADC0N
2 × V
4096
REF
1LSB =
GAIN SET BY
PGA_GN[11:6]
PADC1P
0.15V
0
0
1
0000 0000 0001
0000 0000 0000
1111 1111 1110
SAR
ADC
0.1%,
1nF
5ppm
TO
MCU
PADC1N
BUFFER
BYPASS
SWITCH
GAIN SET BY
PGA_GN[5:0]
1
1
1
0000 0000 0100
0000 0000 0010
0000 0000 0000
ADCCON[14]
MISCELLANEOUS
OTHER
–V
+ 1LSB
0LSB
+V
– 1LSB
REF
REF
VOLTAGE INPUT (V + – V –)
IN
IN
Figure 15. ADC Transfer Function in Differential Mode
Figure 16. PADC0x/PADC1x ADC Input
PADC0x/PADC1x Pins
Other Input Channels
The PADC0x and PADC±x pins are differential input channels
to the ADC that each have a PGA on their front ends.
The ADuC7±20/ADuC7±2± contain seven extra ADC input
pins. These pins can also ꢀe configured as differential input
pairs, single-ended inputs, or pseudo differential inputs. The
ꢀuffer and ADC are configured independently from the input
channel selection. The input range of the ADC input ꢀuffer is
from 0.±5 V to AVDD − 0.±5 V; if the input signal range exceeds
this range, the input ꢀuffer must ꢀe ꢀypassed.
An external precision resistor converts the current to voltage and
the PGA and then amplifies this voltage signal with a gain up to
5 ꢀy 32 steps. The intention is to compensate the variation of
the detector diode responsivity and normalize optical power
read ꢀy the ADC. The external resistor is assumed to have 0.±%
accuracy and 5 ppm. A ± nF capacitor is shunted with the
resistor to suppress wideꢀand noise. Select the resistor value
so the full-scale voltage developed on the resistor is less than
AVDD − ±.2 V, or typically ±.8 V.
The ADuC7±20/ADuC7±2± provide two pins for each thermistor
input. The negative input removes the error of the ground
difference. When selecting the thermistor input, always ꢀypass
the negative side ꢀuffer to ensure that the amplifier is not saturated.
Configure the ADC to work in positive pseudo differential mode.
The PGA handles a ±0 mV minimum input. To minimize noise,
ꢀypass the ADC input ꢀuffer.
Besides these external inputs, the ADC can also select internal
inputs to monitor three power supplies: IOVDD, PVDD_IDAC0,
and PVDD_IDAC±. The voltage of the five IDAC outputs can
also ꢀe monitored ꢀy the ADC ꢀy selecting the required
channel in Register ADCCP. These internal signals are single-
ended and can select AGND/PGND/IOGND as the negative
input of the ADC via the ADCCN register.
PADC0N is driven ꢀy a ꢀuffer to 0.±5 V to keep the PGA from
saturation when the input current drops to zero (see Figure ±6).
Another ꢀuffer on the output of the mux can ꢀe disaꢀled ꢀy
setting Register ADCCON, Bit ±4 so that the PADCxN pin can
ꢀe connected to the ground plane, which is the same for the
PADCxP pin using Register ADCCON, Bit ±5. The ꢀuffer is
alongside the switch in Figure ±6.
When monitoring IDAC outputs or PVDD_IDAC0, PVDD_
IDAC±, or IOVDD_MON, enaꢀle the ꢀuffer to isolate
interference from ADC sampling.
Set the ADC in pseudo differential mode and assume that the
negative input is close to ground.
An on-chip diode can also ꢀe selected to provide chip temperature
monitoring. The ADC can also select VREF and AGND as inputs
for caliꢀration purposes.
All of the controls are independently set through register ꢀits
for giving maximum flexiꢀility to the user. Typically, users take
the following steps:
PGA and Input Buffer
±. Select PADCxP and PADCxN in the ADCCP and ADCCN
registers.
2. Optionally, ꢀypass the ADC input ꢀuffers in
Register ADCCON, Bits[±5:±4].
The PGA is a one stage, positive gain amplifier that can accept
input from 0.± V to AVDD − ±.2 V, and the output swing must ꢀe
at least 2.5 V. The gain of the PGA is from ± to 5 with 32 linear
3. Set the proper gain value for the PGA in PGA_GN.
Rev. D | Page 32 of 102
Data Sheet
ADuC7120/ADuC7121
steps. The PGA cannot be bypassed for the PADC0x and
PADC1x channels.
facilitating an internal temperature sensor channel that
measures die temperature.
The input level for PGA is limited to a maximum value of
AVDD − 1.2 V and minimum value of 0.1 V to ensure that the
amplifiers are not saturated. The input buffer is a rail-to-rail
buffer. It can accept signals from 0.15 to AVDD − 0.15 V. Both
the positive and negative input buffers can be bypassed indepen-
dently by setting Register ADCCON, Bits[15:14].
The internal temperature sensor is not designed for use as an
absolute ambient temperature calculator. It is intended for use
as an approximate indicator of the temperature of the
ADuC7120/ADuC7121 die. The typical temperature
coefficient is −1.25 mV/°C.
1250
Typical Operation
1200
1150
1100
1050
1000
Once configured via the ADC control and channel selection
registers, the ADC converts the analog input and provides a
12-bit result in the ADC data register.
The top four bits are the sign bits, and the 12-bit result is placed
from Bit 27 to Bit 16, as shown in Figure 17. In fully differential
mode, the result is represented in twos complement format, and
when in pseudo differential and single-ended modes, the result is
represented in straight binary format.
31
27
16 15
0
–20
0
20
40
60
80
100
TEMPERATURE (°C)
SIGN BITS
12-BIT ADC RESULT
Figure 19. ADC Output vs. Temperature
Figure 17. ADC Result Format
Timing
ADC MMR Interface
Figure 18 provides details of the ADC timing. Users control the
ADC clock speed and the number of acquisition clocks in the
ADCCON MMR. By default, the acquisition time is eight clocks
and the clock divider is two. The number of additional clocks
(such as bit trial or write) is set to 19, giving a sampling rate of
774 kSPS. For conversion on the temperature sensor, the ADC
acquisition time is automatically set to 16 clocks and the ADC
clock divider is set to 32. When using multiple channels, including
the temperature sensor, the timing settings revert back to the
user-defined settings after reading the temperature sensor channel.
The ADC is controlled and configured via a number of MMRs
(see Table 30) that are described in detail in this section.
Table 30. ADC MMRs
Name
Description
ADCCON ADC control register. ADCCON allows the programmer
to enable the ADC peripheral, to select the mode of
operation of the ADC (either single-ended, pseudo-
differential, or fully differential mode), and to select
the conversion type (see Table 31).
ADCCP
ADCCN
ADCSTA
ADC positive channel selection register.
ADC negative channel selection register.
ACQ
BIT TRIAL
WRITE
ADC status register. ADCSTA indicates when an ADC
conversion result is ready. The ADCSTA register contains
only one bit, ADCREADY (Bit 0), representing the
status of the ADC. This bit is set at the end of an ADC
conversion generating an ADC interrupt. It is cleared
automatically by reading the ADCDAT MMR. When
the ADC is performing a conversion, the status of the
ADC can be read externally via the ADCBUSY function
of Pin C3. This pin is high during a conversion. When
the conversion is finished, ADCBUSY returns to low.
This information can be available on P0.2 (see the
General-Purpose Input/Output section) if enabled in
the GP0CON register.
ADC CLOCK
CONV
START
ADC
BUSY
DATA
ADCDAT
ADCSTA = 0
ADCSTA = 1
ADC INTERRUPT
ADCDAT ADC data result register. ADCDAT holds the 12-bit
ADC result, as shown in Figure 17.
ADCRST
ADC reset register. ADCRST resets all of the ADC
registers to their default values.
Figure 18. ADC Timing
TEMPERATURE SENSOR
ADCGN
ADCOF
ADC gain calibration register for non-PGA channels.
ADC offset calibration register for all ADC channels.
The ADuC7120/ADuC7121 provide a voltage output from an
on-chip, band gap reference proportional to absolute temperature.
This voltage output can also be routed through the front-end
ADC multiplexer (effectively, an additional ADC channel input),
PGA_GN Gain of PGA_PADC0 and PGA_PADC1.
Rev. D | Page 33 of 102
ADuC7120/ADuC7121
Data Sheet
Table 31. ADCCON MMR Bit Designations (Address = 0xFFFF0500, Default Value = 0x00000A00)
Bit(s)
[31:16]
15
Setting
Description
Reserved
These bits are reserved.
Positive ADC buffer bypass.
0
1
Set to 0 by the user to enable the positive ADC buffer.
Set to 1 by the user to bypass the positive ADC buffer.
Negative ADC buffer bypass.
14
0
1
Set to 0 by the user to enable the negative ADC buffer.
Set to 1 by the user to bypass the negative ADC buffer.
ADC clock speed.
[13:11]
fADC = fCORE Conversion = 19 ADC Clocks + Acquisition Time
000 fADC divide by 1. This divider is provided to obtain a 1 MSPS ADC with an external clock of <41.78 MHz.
001 fADC divide by 2 (default value).
010 fADC divide by 4.
011 fADC divide by 8.
100 fADC divide by 16.
101 fADC divide by 32.
[10:8]
ADC acquisition time (number of ADC clocks).
000 2 clocks.
001 4 clocks.
010 8 clocks (default value).
011 16 clocks.
100 32 clocks.
101 64 clocks.
7
Enable conversion.
Set by the user to 1 to enable conversion mode.
Cleared by the user to 0 to disable conversion mode.
Reserved. The user sets this bit to 0.
ADC power control.
6
5
1
0
Set by the user to 1 to place the ADC in normal mode. The ADC must be powered up for at least 5 μs
before it converts correctly.
Cleared by the user to 0 to place the ADC in power-down mode.
Conversion mode.
[4:3]
[2:0]
00 Single-ended mode.
01 Differential mode.
10 Pseudo differential mode.
11 Reserved.
Conversion type.
000 Enable the ADCCONVST function on Pin F3 as a conversion input.
001 Enable Timer1 as a conversion input.
010 Enable Timer0 as a conversion input.
011 Single software conversion. Automatically sets to 000 after conversion.
100 Continuous software conversion.
101 PLA conversion.
110 PWM conversion.
Others
Reserved.
Rev. D | Page 34 of 102
Data Sheet
ADuC7120/ADuC7121
Table 32. ADuC7120 ADCCP1 MMR Bit Designations
Bit(s) Setting
Description
Bit(s) Setting
Description
10100 Reserved
[7:5]
[4:0]
Reserved Reserved
10101 Reserved
10110 VREF
Positive channel selection bits
10111 AGND
00000 PADC0P
Others Reserved
1 ADC channel availability depends on device model.
00001 PADC1P
00010 ADC0
00011 ADC1
00100 ADC2
00101 ADC3
00110 ADC4
00111 ADC5
01000 ADC6
01001 ADC7
Table 34. ADuC7120 ADCCN1 MMR Bit Designations
Bit(s) Setting
Description
[7:5]
[4:0]
Reserved Reserved
Negative channel selection bits
00000 PADC0N
00001 PADC1N
00010 ADC0
00011 ADC1
00100 ADC2
00101 ADC3
00110 ADC4
00111 ADC5
01000 ADC6
01001 ADC7
01010 ADC8
01011 ADC9
01100 ADC10/AINCM
01101 VREF
01010 ADC8
01011 ADC9
01100 ADC10/AINCM
01101 Temperature sensor
01110 DVDD_IDAC0
01111 DVDD_IDAC1
10000 DVDD_IDAC2
10001 DVDD_IDAC3
10010 DVDD_IDAC4
10011 IOVDD_MON
10100 PVDD_IDAC0
10101 PVDD_IDAC1
10110 VREF
01110 AGND
01111 PGND
10000 IOGND
10111 AGND
Others Reserved
1 ADC channel availability depends on device model.
Others
Reserved
1 ADC channel availability depends on device model.
Table 33. ADuC7121 ADCCP1 MMR Bit Designations
Table 35. ADuC7121 ADCCN1 MMR Bit Designations
Bit(s) Setting
Description
Bit(s) Setting
Description
[7:5]
[4:0]
Reserved Reserved
[7:5]
[4:0]
Reserved Reserved
Positive channel selection bits
00000 PADC0P
Negative channel selection bits
00001 PADC1P
00000 PADC0N
00010 Reserved
00011 Reserved
00100 Reserved
00101 Reserved
00110 ADC4
00001 PADC1N
00010 Reserved
00011 Reserved
00100 Reserved
00101 Reserved
00110 ADC4
00111 ADC5
01000 ADC6
00111 ADC5
01001 ADC7
01000 ADC6
01010 ADC8
01001 ADC7
01011 ADC9
01010 ADC8
01100 ADC10/AINCM
01101 Temperature sensor
01110 DVDD_IDAC0
01111 DVDD_IDAC1
10000 DVDD_IDAC2
10001 DVDD_IDAC3
10010 DVDD_IDAC4
10011 IOVDD_MON
01011 ADC9
01100 ADC10/AINCM
01101 VREF
01110 AGND
01111 PGND
10000 IOGND
Others
Reserved
1 ADC channel availability depends on device model.
Rev. D | Page 35 of 102
ADuC7120/ADuC7121
Data Sheet
Table 36. ADCSTA MMR Bit Designations
CAPACITIVE
DAC
Bit(s) Setting
Description
COMPARATOR
0
1
Indicates that an ADC conversion is complete. It
is set automatically after an ADC conversion
completes.
C
C
B
A
S
CHANNEL+
CHANNEL–
AIN0
SW1
SW2
CONTROL
LOGIC
MUX
SW3
S
0
0
Automatically cleared by reading the
ADCDAT MMR.
A
B
AIN11
V
REF
Table 37. ADCDAT MMR Bit Designations
CAPACITIVE
DAC
Bit(s)
Setting Description
[27:16]
Holds the ADC result (see Figure 17).
Figure 20. ADC Acquisition Phase
When the ADC starts a conversion (see Figure 21), SW3 opens,
and SW1 and SW2 move to Position B, causing the comparator
to become unbalanced. Both inputs are disconnected as soon as
the conversion begins. The control logic and the charge redistribu-
tion DACs add and subtract fixed amounts of charge from the
sampling capacitor arrays to return the comparator to a
balanced condition. When the comparator is rebalanced, the
conversion completes.
Table 38. ADCRST MMR Bit Designations
Bit(s) Setting
Description
0
1
Set to 1 by the user to reset all the ADC
registers to their default values.
Table 39. PGA_GN MMR Bit Designations1
Bit(s) Setting2 Description
[11:6] N/A
Gain of PGA for PADC0 = 1 + 4 ×
(PGA_PADC0_GN/32).
The control logic generates the ADC output code. The output
impedances of the sources driving the VIN+ input and the VIN−
input must match; otherwise, the two inputs have different
settling times, resulting in errors.
[5:0] N/A
Gain of PGA for PADC1 = 1 + 4 ×
(PGA_PADC1_GN/32).
1 PGA_PADC0_GN and PGA_PADC1_GN must be ≤ 32.
2 N/A means not applicable.
Table 40. ADCGN MMR Bit Designations
CAPACITIVE
DAC
Bit(s)
[11:10] N/A
[9:0] N/A
Setting1 Description
COMPARATOR
C
C
B
A
These bits are reserved.
S
CHANNEL+
CHANNEL–
AIN0
10-bit ADC gain calibration value for non-
PGA channels.
SW1
SW2
CONTROL
LOGIC
MUX
SW3
S
A
B
1 N/A means not applicable.
AIN11
V
Table 41. ADCOF MMR Bit Designations
REF
CAPACITIVE
DAC
Bit(s)
[15:10] N/A
[9:0] N/A
Setting1 Description
These bits are reserved.
Figure 21. ADC Conversion Phase
10-bit ADC offset calibration value.
Pseudo Differential Mode
1 N/A means not applicable.
In pseudo differential mode, Channel− is linked to the VIN− input
of the ADuC7120/ADuC7121, and SW2 switches between A
(Channel−) and B (VREF). The VIN− input must be connected to
ground or a low voltage. The input signal on VIN+ can then vary
from VIN− to VREF + VIN−. Choose VIN− so VREF + VIN− does not
exceed AVDD.
CONVERTER OPERATION
The ADC incorporates a successive approximation architecture
involving a charge sampled input stage. This architecture is
described for the three different modes of operation:
differential, pseudo differential, and single-ended.
Differential Mode
CAPACITIVE
DAC
The ADuC7120/ADuC7121 contain a successive approximation
ADC based on two capacitive DACs. Figure 20 and Figure 21
show simplified schematics of the ADC in acquisition and
conversion phase, respectively. The ADC comprises control logic,
an SAR, and two capacitive DACs. In Figure 20 (the acquisition
phase), SW3 is closed, and SW1 and SW2 are in Position A. The
comparator is held in a balanced condition, and the sampling
capacitor arrays acquire the differential signal on the input.
COMPARATOR
C
C
B
A
S
CHANNEL+
AIN0
SW1
SW2
CONTROL
LOGIC
MUX
SW3
S
A
B
AIN11
V
REF
CAPACITIVE
DAC
V
IN–
CHANNEL–
Figure 22. ADC in Pseudo Differential Mode
Rev. D | Page 36 of 102
Data Sheet
ADuC7120/ADuC7121
Single-Ended Mode
For ac applications, removing high frequency components from
the analog input signal is recommended with a resistor
In single-ended mode, SW2 is always connected internally to
ground. The VIN− input pin can be floating. The input signal
range on VIN+ is 0 V to VREF
capacitor (RC) low-pass filter on the relevant analog input pins. In
applications where harmonic distortion and SNR are critical,
drive the analog input from a low impedance source. Large source
impedances significantly affect the ac performance of the ADC
and can necessitate the use of an input buffer amplifier. The choice
of the op amp is a function of the particular application. Figure 25
and Figure 26 give an example of an ADC front end.
.
CAPACITIVE
DAC
COMPARATOR
C
C
B
S
CHANNEL+
AIN0
A
SW1
CONTROL
LOGIC
MUX
SW3
S
CHANNEL–
AIN11
ADuC7120/
ADuC7121
10Ω
CAPACITIVE
DAC
ADC0
0.01µF
Figure 23. ADC in Single-Ended Mode
Figure 25. Buffering Single-Ended/Pseudo Differential Input
Analog Input Structure
ADuC7120/
ADuC7121
ADC0
Figure 24 shows the equivalent circuit of the analog input structure
of the ADC. The four diodes provide ESD protection for the analog
inputs. Ensure that the analog input signals never exceed the
supply rails by more than 300 mV. Voltage in excess of 300 mV
causes these diodes to become forward biased and start
V
REF
ADC1
conducting into the substrate. These diodes can conduct up to
10 mA without causing irreversible damage to the device.
Figure 26. Buffering Differential Inputs
When no amplifier drives the analog input, limit the source
impedance to values lower than 1 kꢀ. The maximum source
impedance depends on the amount of THD that can be tolerated.
The THD increases as the source impedance increases and the
performance degrades.
The C1 capacitors in Figure 24 are typically 4 pF and can be
primarily attributed to pin capacitance. The resistors are lumped
components made up of the on resistance of the switches. The
value of these resistors is typically about 100 Ω. The C2 capacitors
are the ADC sampling capacitors and have a capacitance of
16 pF typical.
DRIVING THE ANALOG INPUTS
An internal or external reference can be used for the ADC.
In differential mode of operation, there are restrictions on the
VCM. These restrictions are dependent on the reference value and
supply voltage used to ensure the signal remains within the
supply rails. Table 42 lists calculated VCM minimum and VCM
maximum values.
AV
DD
D
C2
R1
C1
D
AV
DD
D
D
C2
R1
C1
Figure 24. Equivalent Analog Input Circuit Conversion Phase: Switches Open,
Track Phase: Switches Closed
Table 42. VCM Ranges
VCM (V)
AVDD (V)
VREF (V)
2.5
2.048
1.25
Min
Max
2.05
2.276
2.55
1.75
1.976
2.25
Signal Peak-to-Peak (V)
3.3
1.25
1.024
0.75
1.25
1.024
0.75
2.5
2.048
1.25
2.5
2.048
1.25
3.0
2.5
2.048
1.25
Rev. D | Page 37 of 102
ADuC7120/ADuC7121
Data Sheet
BUF_VREF2, and used as a reference for other circuits in the
system.
BAND GAP REFERENCE
The ADuC7120/ADuC7121 provide an on-chip, band gap
reference of 2.5 V that can be used for the ADC and the DAC.
This 2.5 V reference is generated from a 1.2 V reference.
The band gap reference also connects through buffers to the
BUF_VREF1 and the BUF_VREF2 pins. To dampen the noise,
connect a 0.1 μF minimum capacitor to these pins. The band
gap reference interface consists of an 8-bit REFCON MMR, as
described in Table 43.
This internal reference also appears on the VREF pins (VREF_2.5
and VREF_1.2). When using the internal reference, connect a
capacitor of 0.47 µF between each external VREF pin and AGND
to ensure stability and fast response during ADC conversions.
This reference can also be connected to the external pin,
Table 43. REFCON MMR Bit Designations (Address = 0xFFFF0480, Default Value = 0x01)
Bit(s) Description
[7:1]
2
Reserved.
BUF_VREF1/BUF_VREF2 are driven from the internal 2.5 V reference when set to 1.
Internal 2.5 V reference output enable.
1
Set by the user to connect the internal 2.5 V reference to the VREF_2.5 pin.
Cleared by the user to disconnect the reference from the VREF_2.5 pin. The VREF_2.5 pin must also be cleared to connect an external
reference source to it.
0
Internal 1.2 V reference output enable.
Set by the user to connect the internal 1.2 V reference to the VREF_1.2 pin.
Cleared by the user to disconnect the reference from the VREF_1.2 pin.
Rev. D | Page 38 of 102
Data Sheet
ADuC7120/ADuC7121
generated until CMP returns high. The user must ensure that
the code execution remains within the interrupt service routine
(ISR) until CMP returns high.
POWER SUPPLY MONITOR (PSM)
The PSM on the ADuC7120/ADuC7121 indicates when the
IOVDD supply pin drops below one of two supply trip points.
The monitor function is controlled via the PSMCON register. If
enabled in the IRQEN or FIQEN register, the monitor interrupts
the core using the PSMI bit in the PSMCON MMR. This bit
clears immediately after the CMP bit goes high. If the interrupt
generated is exited before CMP goes high (IOVDD supply
voltage is above the trip point), no further interrupts are
This monitor function allows the user to save working registers
to avoid possible data loss due to low supply or brownout
conditions. It also ensures that normal code execution does not
resume until a safe supply level is established.
The PSM does not operate correctly when using JTAG debug;
therefore, disable PSM while in JTAG debug mode.
Table 44. PSMCON MMR Bit Designations (Address = 0xFFFF0440, Default Value = 0x0008)
Bit(s) Name Description
[15:4] Reserved These bits are reserved.
3
2
1
0
CMP
Comparator bit. This is a read only bit that directly reflects the state of the comparator.
Read 1 indicates that the IOVDD supply is above its selected trip point or the PSM is in power-down mode.
Read 0 indicates the IOVDD supply is below its selected trip point. Set this bit before leaving the interrupt service routine.
TP
Trip point selection bit.
0 = 2.79 V.
1 = 3.07 V.
PSMEN
PSMI
Power supply monitor enable bit.
Set to 1 to enable the power supply monitor circuit.
Cleared to 0 to disable the power supply monitor circuit.
Power supply monitor interrupt bit. This bit is set high by the MicroConverter if the CMP bit is low, indicating low
input/output supply. The PSMI bit can interrupt the processor. When the CMP bit returns high, the PSMI bit can be
cleared by writing a 1 to this location. Writing a 0 to this location has no effect. There is no timeout delay. PSMI can be
cleared immediately after the CMP bit goes high.
Rev. D | Page 39 of 102
ADuC7120/ADuC7121
Data Sheet
NONVOLATILE FLASH/EE MEMORY
As indicated in the Specifications section, the Flash/EE memory
endurance qualification is carried out in accordance with
JEDEC Retention Lifetime Specification, Method A117 over the
industrial temperature range of −40°C to +105°C. The results
allow the specification of a minimum endurance figure over a
supply temperature of 10,000 cycles.
FLASH/EE MEMORY OVERVIEW
The ADuC7120/ADuC7121 incorporate Flash/EE memory
technology on chip to provide the user with nonvolatile,
in circuit reprogrammable memory space.
Similar to EEPROM, flash memory can be programmed in system
at a byte level, although it must first be erased. The erase is
performed in page blocks. As a result, flash memory is often
(and more correctly) referred to as Flash/EE memory.
Retention quantifies the ability of the Flash/EE memory to retain
its programmed data over time. The devices are qualified in
accordance with the formal JEDEC Retention Lifetime
Specification, Method A117 at a specific junction temperature
(TJ = 85°C). As part of this qualification procedure, the
Flash/EE memory is cycled to the specified endurance limit,
previously described, before data retention is characterized. The
Flash/EE memory is guaranteed to retain its data for its fully
specified retention lifetime every time the Flash/EE memory is
reprogrammed. Retention lifetime, based on activation energy
of 0.6 eV, derates with TJ, as shown in Figure 27.
Overall, Flash/EE memory represents the ideal memory device
that includes no volatility, in circuit programmability, high
density, and low cost. Incorporated in the ADuC7120/
ADuC7121, Flash/EE memory technology allows the user to
update program code space in circuit, without the need to
replace one time programmable (OTP) devices at remote
operating nodes.
The ADuC7120/ADuC7121 contain two 64 kB arrays of
Flash/EE memory. In Flash Block 0, the lower 62 kB is available
to the user, and the upper 2 kB of this Flash/EE memory array
program contain permanently embedded firmware, allowing
in circuit serial download. The 2 kB of embedded firmware also
contain a power-on configuration routine that downloads factory
calibrated coefficients to the various calibrated peripherals (band
gap references and so forth). This 2 kB embedded firmware is
hidden from the user code. It is not possible for the user to read,
write, or erase this page.
600
450
300
150
0
In Flash Block 1, all 64 kB of Flash/EE memory are available to
the user.
The 128 kB of Flash/EE memory can be programmed in circuit
using serial download mode or JTAG mode.
30
40
55
70
85
100
125
135
150
JUNCTION TEMPERATURE (°C)
Flash/EE Memory Reliability
Figure 27. Flash/EE Memory Data Retention
The Flash/EE memory arrays on the ADuC7120/ADuC7121 are
fully qualified for two key Flash/EE memory characteristics:
Flash/EE memory cycling endurance and Flash/EE memory
data retention.
Serial Downloading (In Circuit Programming)
The ADuC7120/ADuC7121 facilitate code download via the
2
BM
BM
I C serial port. If the
function of the P3.7/ /PLAO[11]
pin is pulled low through an external 1 kΩ resistor, the
ADuC7120/ADuC7121 enter serial download mode after a reset
or power cycle. In the Flash, if Address 0x0014 is 0xFFFFFFFF
Endurance quantifies the ability of the Flash/EE memory to
cycle through many program, read, and erase cycles. A single
endurance cycle is composed of four independent, sequential
events, defined as follows:
BM
and
is pulled low, the devices enter download mode; if this
address contains any other value, user code is executed. When
in serial download mode, the user can download code to the
full 128 kB of Flash/EE memory while the devices are in circuit
in their target application hardware. A PC serial download
executable and hardware dongle are provided as part of the
development system for serial downloads via the I2C port.
The I2C maximum allowed baud rate is 100 kHz for the I2C
downloader.
1. Initial page erase sequence
2. Read and verify sequence a single Flash/EE
3. Byte program sequence memory
4. Second read and verify sequence endurance cycle
In reliability qualification, every half word (16-bit wide) location
of the three pages (top, middle, and bottom) in the Flash/EE
memory is cycled 10,000 times from 0x0000 to 0xFFFF.
JTAG Access
The JTAG protocol uses the on-chip JTAG interface to facilitate
code download and debug.
Rev. D | Page 40 of 102
Data Sheet
ADuC7120/ADuC7121
FLASH/EE MEMORY SECURITY
FLASH/EE CONTROL INTERFACE
FEE0DAT Register
The 126 kB of Flash/EE memory available to the user can be
read and write protected. Bit 31 of the FEE0PRO and FEE0HID
MMRs protects it from read through by JTAG and I2C
FEE0DAT is a 16-bit data register.
Name:
FEE0DAT
programming mode. The other 31 bits of this register protect
writing to the Flash/EE memory; each bit protects four pages, that
is, 2 kB. Write protection is activated for all access types. FEE1PRO
and FEE1HID protect Flash Block 1. Bit 31 of the FEE1PRO and
FEE1HID MMRs protects the 64 kB of Block 1 from being read
through JTAG. Bit 30 protects writing to the top 8 pages of Block
1. The other 30 bits of this register protect writing to the Flash/EE
memory; each bit protects four pages, that is, 2 kB.
Address:
Default value:
Access:
0xFFFF0E0C
0xXXXX
Read and write
FEE0ADR Register
FEE0ADR is a 16-bit address register.
Three Levels of Protection
Name:
FEE0ADR
0xFFFF0E10
0x0000
Protection can be set and removed by writing directly into the
FEExHID MMRs. This protection does not remain after reset.
Address:
Default value:
Access:
Protection can be set by writing into the FEExPRO MMRs. It
takes effect only after a save protection command (0x0C) and
a reset. The FEExPRO MMRs are protected by a key to avoid
direct access. The key is saved one time only and must be
reentered to modify the FEExPRO. A mass erase sets the key
back to 0xFFFF but also erases all user code.
Read and write
FEE0SGN Register
FEE0SGN is a 24-bit code signature.
The Flash/EE memory can be permanently protected by using
the FEExPRO MMRs and a particular value of the 0xDEADDEAD
key. Entering the key again to modify the FEExPRO register is
not allowed.
Name:
FEE0SGN
0xFFFF0E18
0xFFFFFF
Read only
Address:
Default value:
Access:
Sequence to Write the Key to Protection Registers
1. Write the bit in the FEExPRO corresponding to the page to
be protected.
2. Enable key protection by setting Bit 6 of FEExMOD (Bit 5
must equal 0).
3. Write a 32-bit key in FEExADR and FEExDAT.
4. Run the write key command 0x0C in FEExCON; wait for
the read to be successful by monitoring FEExSTA.
5. Reset the device.
FEE0PRO Register
FEE0PRO provides protection following subsequent reset MMR.
It requires a software key (see Table 45).
Name:
FEE0PRO
Address:
Default value:
Access:
0xFFFF0E1C
0x00000000
Read and write
To remove or modify the protection, the same sequence is used
with a modified value of FEExPRO. If the key chosen is the value
0xDEAD, the memory protection cannot be removed. Only a mass
erase unprotects the device, but it also erases all user code.
The sequence to write the key is shown in the following example;
this protects writing Page 4 to Page 7 of the Flash/EE memory:
FEE0HID Register
FEE0HID provides immediate protection MMR. It does not
require any software keys (see Table 45).
FEE0PRO=0xFFFFFFFD; //Protect Page 4 to Page 7
FEE0MOD=0x48;
FEE0ADR=0x1234;
FEE0DAT=0x5678;
FEE0CON= 0x0C;
//Write key enable
//16-bit key value
//16-bit key value
//Write key command
Name:
FEE0HID
Address:
Default value:
Access:
0xFFFF0E20
0xFFFFFFFF
Read and write
Follow the same sequence to permanently protect the devices
with FEExADR = 0xDEAD and FEExDAT = 0xDEAD.
Rev. D | Page 41 of 102
ADuC7120/ADuC7121
Data Sheet
Table 45. FEE0PRO and FEE0HID MMR Bit Designations
FEE1HID Register
Bit(s) Description
FEE1HID provides immediate protection MMR. It does not
require any software keys (see Table 46).
31
Read protection.
Cleared by the user to protect Block 0.
Set by the user to allow reading Block 0.
Name:
FEEHID
[30:0] Write protection for Page 123 to Page 0. Each bit
protects a group of 4 pages.
Address:
Default value:
Access:
0xFFFF0EA0
0xFFFFFFFF
Read and write
Cleared by the user to protect the pages when writing
to flash, thus preventing an accidental write to specific
pages in Flash.
Set by the user to allow writing the pages.
Table 46. FEE1PRO and FEE1HID MMR Bit Designations
Command Sequence for Executing a Mass Erase
Bit(s) Description
31
Read protection.
FEE0DAT = 0x3CFF;
FEE0ADR = 0xFFC3;
FEE0MOD = FEE0MOD|0x8; //Erase key enable
FEE0CON = 0x06;
Cleared by the user to protect Block 1.
Set by the user to allow reading Block 1.
Write protection for Page 127 to Page 120.
//Mass erase command
30
FEE1DAT Register
Cleared by the user to protect the pages when writing
to flash, thus preventing an accidental write to specific
pages in flash.
FEE1DAT is a 16-bit data register.
Set by the user to allow writing the pages.
Name:
FEE1DAT
[29:0] Write protection for Page 119 to Page 0. Each bit
protects a group of 4 pages.
Address:
Default value:
Access:
0xFFFF0E8C
0xXXXX
Cleared by the user to protect the pages when writing
to flash, thus preventing an accidental write to specific
pages in flash.
Read and write
Set by the user to allow writing the pages.
FEE1ADR Register
FEE1ADR is a 16-bit address register.
FEE0STA Register
Name:
FEE0STA
0xFFFF0E00
0x0001
Name:
FEE1ADR
0xFFFF0E90
0x0000
Address:
Default value:
Access:
Address:
Default value:
Access:
Read only
Read and write
FEE1STA Register
Name:
FEE1STA
FEE1SGN Register
Address:
Default value:
Access:
0xFFFF0E80
0x0000
FEE1SGN is a 24-bit code signature.
Name:
FEE1SGN
0xFFFF0E98
0xFFFFFF
Read only
Address:
Default value:
Access:
Read only
Table 47. FEExSTA MMR Bit Designations
Bit(s) Description
[15:4] Reserved.
3
Flash/EE interrupt status bit.
FEE1PRO Register
Set automatically when an interrupt occurs, that is,
when a command is complete and the Flash/EE
interrupt enable bit in the FEExMOD register is set.
FEE1PRO provides protection following subsequent reset MMR.
It requires a software key (see Table 46).
Cleared when reading FEExSTA register.
Flash/EE controller busy.
Name:
FEE1PRO
2
Set automatically when the controller is busy.
Cleared automatically when the controller is not busy.
Address:
Default value:
Access:
0xFFFF0E9C
0x00000000
Read and write
Rev. D | Page 42 of 102
Data Sheet
ADuC7120/ADuC7121
Table 48. FEExMOD MMR Bit Designations
Bit(s) Description
Bit(s) Description
1
Command fail.
Set automatically when a command completes
unsuccessfully.
Cleared automatically when reading FEExSTA register.
Command complete.
[7:5]
Reserved. These bits are always set to 0 except when
writing keys. See the Sequence to Write the Key to
Protection Registers section for details.
4
Flash/EE interrupt enable.
0
Set by the user to enable the Flash/EE interrupt. The
interrupt occurs when a command is complete.
Cleared by the user to disable the Flash/EE interrupt.
Erase/write command protection.
Set by MicroConverter when a command is complete.
Cleared automatically when reading FEExSTA register.
FEE0MOD Register
3
Set by the user to enable the erase and write commands.
Name:
FEE0MOD
Cleared to protect the Flash/EE memory against
erase/write command.
Address:
Default value:
Access:
0xFFFF0E04
0x80
2
Reserved. The user must set this bit to 0.
[1:0]
Flash/EE wait states. Both Flash/EE blocks must have the
same wait state value for any change to take effect.
Read and write
FEE0CON Register
FEE1MOD Register
Name:
FEE0CON
Name:
FEE1MOD
Address:
Default value:
Access:
0xFFFF0E08
0x00
Address:
Default value:
Access:
0xFFFF0E84
0x80
Read and write
Read and write
FEE1CON Register
Name:
FEE1CON
Address:
Default value:
Access:
0xFFFF0E88
0x00
Read and write
Table 49. Command Codes in FEExCON
Code Command
0x001 Null
Description
Idle state.
0x011 Single read
0x021 Single write
0x031 Erase/write
Load FEExDAT with the 16-bit data indexed by FEExADR.
Write FEExDAT at the address pointed by FEExADR. This operation takes 50 µs.
Erase the page indexed by FEExADR and write FEExDAT at the location pointed by FEExADR. This operation takes 20 ms.
0x041 Single verify Compare the contents of the location pointed by FEExADR to the data in FEExDAT. The result of the comparison is
returned in FEExSTA Bit 1.
0x051 Single erase Erase the page indexed by FEExADR.
0x061 Mass erase
Erase user space. The 2 kB of kernel are protected in Block 0. This operation takes 2.48 sec. To prevent accidental
execution, a command sequence is required to execute this instruction.
0x07
0x08
0x09
0x0A
0x0B
0x0C
Reserved
Reserved
Reserved
Reserved
Signature
Protect
Reserved.
Reserved.
Reserved.
Reserved.
Gives a signature of the 64 kB of Flash/EE in the 24-bit FEExSIGN MMR. This operation takes 32,778 clock cycles.
This command can run only once. The value of FEExPRO is saved and can be removed only with a mass erase (0x06)
or with the key.
0x0D Reserved
Reserved.
0x0E
0x0F
Reserved
Ping
Reserved.
No operation, interrupt generated.
1 The FEExCON register always reads 0x07 immediately after execution of any of these commands.
Rev. D | Page 43 of 102
ADuC7120/ADuC7121
Data Sheet
EXECUTION TIME FROM SRAM AND FLASH/EE
RESET AND REMAP
This section describes SRAM and Flash/EE access times during
execution for applications where execution time is critical.
The ARM exception vectors are located at the bottom of the
memory array, from Address 0x00000000 to Address 0x00000020,
as shown in Figure 28.
Execution from SRAM
0xFFFFFFFF
Fetching instructions from SRAM take one clock cycle because
the access time of the SRAM is 2 ns, and a clock cycle is 22 ns
minimum. However, if the instruction involves reading or
writing data to memory, one extra cycle must be added if the
data is in SRAM (or three cycles if the data is in Flash/EE), one
cycle to execute the instruction, and two cycles to retrieve the
32-bit data from Flash/EE. A control flow instruction, such as a
branch instruction, takes one cycle to fetch, but it also takes two
cycles to fill the pipeline with the new instructions.
KERNEL
0x0008FFFF
0x00041FFF
FLASH/EE
INTERRUPT
SERVICE ROUTINES
0x00080000
0x00040000
Execution from Flash/EE
SRAM
INTERRUPT
SERVICE ROUTINES
Because the Flash/EE width is 16 bits and access time for 16-bit
words is 22 ns, execution from Flash/EE cannot be accomplished
in one cycle (as can be done from SRAM when the CD bit = 0). In
addition, some dead times are needed before accessing data for
any value of CD bits.
MIRROR SPACE
0x00000020
ARM EXCEPTION
VECTOR ADDRESSES 0x00000000 0x00000000
Figure 28. Remap for Exception Execution
In ARM mode, where instructions are 32 bits, two cycles are
needed to fetch any instruction when CD = 0. In thumb mode,
where instructions are 16 bits, one cycle is needed to fetch any
instruction.
By default and after any reset, the Flash/EE is mirrored at the
bottom of the memory array. The remap function allows the
programmer to mirror the SRAM at the bottom of the memory
array, facilitating execution of exception routines from SRAM
instead of from Flash/EE. This results in exceptions executing
twice as fast, with the exception executed in ARM mode (32
bits), and the SRAM being 32 bits wide instead of 16-bit wide
Flash/EE memory.
Timing is identical in both modes when executing instructions
that involve using the Flash/EE for data memory. If the instruction
executed is a control flow instruction, an extra cycle is needed
to decode the new address of the program counter and then four
cycles are needed to fill the pipeline. A data processing instruction
involving only core registers does not require any extra clock
cycles, but if it involves data in Flash/EE, one additional clock
cycle is needed to decode the address of the data, and two
additional cycles are needed to obtain the 32-bit data from
Flash/EE. An extra cycle must also be added before fetching
another instruction. Data transfer instructions are more
complex and are summarized in Table 50.
Remap Operation
When a reset occurs on the ADuC7120/ADuC7121, execution
starts automatically in factory programmed internal configuration
code. This kernel is hidden and cannot be accessed by user code.
BM
If the ADuC7120/ADuC7121 is in normal mode (the P3.7/
/
PLAO[11] pin is high), they execute the power-on configuration
routine of the kernel and then jump to the reset vector address,
0x00000000, to execute the reset exception routine of the user.
Because the Flash/EE is mirrored at the bottom of the memory
array at reset, the reset interrupt routine must always be written
in Flash/EE.
Table 50. Execution Cycles in ARM/Thumb Mode
Fetch
Cycles
Dead
Time
Dead
Time
Instructions1
LD
LDH
LDM/PUSH
STR
Data Access
2/1
2/1
2/1
2/1
2/1
2/1
1
1
N
1
1
N
2
1
1
1
N
1
1
N
The remap is performed from Flash/EE by setting Bit 0 of the
remap register. Take precautions to execute this command from
Flash/EE (above Address 0x00080020) and not from the bottom
of the array because the defined memory space is replaced by
the SRAM.
2 × N
2 × 20 μs
20 μs
STRH
STRM/POP
2 × N × 20 μs
1 LD is the load register, LDH is the load register half word, LDM/PUSH loads
multiple registers onto the stack and updates the stack pointer, STR is the
store register, STRH is the store register half word, and STRM/POP loads
multiple registers off the stack and updates the stack pointer.
This operation is reversible: the Flash/EE can be remapped at
Address 0x00000000 by clearing Bit 0 of the remap MMR. Take
precautions to execute the remap function from outside the
mirrored area. Any kind of reset remaps the Flash/EE memory
at the bottom of the array.
With 1 < N ≤ 16, N is the number of bytes of data to load or
store in the multiple load/store instruction. The SWAP instruction
combines an LD and STR instruction with only one fetch,
giving a total of eight cycles plus 40 μs.
Rev. D | Page 44 of 102
Data Sheet
ADuC7120/ADuC7121
Reset Operation
RSTCFGKEY0 Register
There are four types of reset: external reset, power-on reset,
watchdog expiration, and software force. The RSTSTA register
indicates the source of the last reset and the RSTCLR register
clears the RSTSTA register. These registers can be used during a
reset exception service routine to identify the source of the
reset. If RSTSTA is null, the reset is external. When clearing
RSTSTA, all bits currently set to 1 must be cleared. Otherwise, a
reset event occurs.
Name:
RSTCFGKEY0
Address:
Default value:
Access
0xFFFF0248
0xXX
Write only
RSTCFGKEY1 Register
Name:
RSTCFGKEY1
The RSTCFG register allows different peripherals to retain their
state after a watchdog or software reset.
Address:
Default value:
Access:
0xFFFF0250
0xXX
Table 51. Remap MMR Bit Designations (Address =
0xFFFF0220, Default Value = 0x00)
Write only
Bit Name
Remap Remap bit.
Set by the user to remap the SRAM to
Description
0
Table 53. RSTCFG Write Sequence
Name
Code
Address 0x00000000.
Cleared automatically after reset to remap the
Flash/EE memory to Address 0x00000000.
RSTCFGKEY0
RSTCFG
0x76
User value
0xB1
RSTCFGKEY1
Table 52. RSTSTA MMR Bit Designations (Address =
0xFFFF0230, Default Value = 0x0X)
Bit(s) Description
Table 54. RSTCFG MMR Bit Designations (Address =
0xFFFF024C, Default Value = 0x00)
Bit(s) Description
[7:3]
2
Reserved.
Software reset.
[7:4]
3
Reserved. Always set to 0.
Set by the user to force a software reset.
Cleared by setting the corresponding bit in RSTCLR.
Watchdog timeout.
Set automatically when a watchdog timeout occurs.
Cleared by setting the corresponding bit in RSTCLR.
Power-on reset.
This bit is set to 1 to configure the IDAC outputs to
retain their state after a watchdog or software reset.
1
0
This bit is cleared for the IDAC output pins and registers
to return to their default state.
2
This bit is set to 1 to configure the DAC outputs to retain
their state after a watchdog or software reset.
This bit is cleared for the DAC output pins and registers
to return to their default state.
Set automatically when a power-on reset occurs.
Cleared by setting the corresponding bit in RSTCLR.
1
0
Reserved. Always set to 0.
This bit is set to 1 to configure the GPIO pins to retain
their state after a watchdog or software reset.
This bit is cleared for the GPIO pins and registers to
return to their default state.
Rev. D | Page 45 of 102
ADuC7120/ADuC7121
Data Sheet
OTHER ANALOG PERIPHERALS
MMR Interfaces
DACs
Each DAC is independently configurable through a control
register and a data register. These two registers are identical for
the 12 DACs. Only DAC0CON and DAC0DAT are described in
detail in this section.
The ADuC7120/ADuC7121 incorporate up to 12 buffered, 12-bit
voltage output string DACs on chip. Each DAC has a rail-to-rail
voltage output buffer capable of driving 5 kΩ//100 pF
Each DAC has three selectable ranges: 0 V to VREF (internal
band gap 2.5 V reference), 0 V to AVDD, and 0 V to external
reference, EXT_REF (see the Pin Configurations and Function
Descriptions section, Table 49, and Figure 29). The signal range
is 0 V to AVDD. The DAC can also operate in interpolation
mode.
AV
AV
DD
DD
EXT_REF
EXT_REF
INTERNAL
REFERENCE
+
INTERNAL
REFERENCE
+
DAC_REFBUF
DAC_REFBUF
SW_A0
SW_A11
–
–
SW_B0
SW_B11
STRING
DAC
STRING
DAC
. . . . . .
SW_C0
SW_C11
SW_D0
SW_D11
DAC0
DAC11
DAC_BUF
DAC_BUF
. . . . . .
NOTES
1. SW_xx ARE INTERNAL SWITCHES.
Figure 29. DAC Configuration
SW_B
SW_C
12
STRING
DAC
INTERPOLATOR
DIV
UCLK
16/32
DAC
OUTPUT
DAC_BUF
12
16
HCLK
DATA
REGISTER
TIMER1
Figure 30. DAC User Functionality
Rev. D | Page 46 of 102
Data Sheet
ADuC7120/ADuC7121
Table 55. ADuC7120 DACxCON Registers (Default Value = 0x100, Read/Write Access)
Name
Address
DAC0CON
DAC1CON
DAC2CON
DAC3CON
DAC4CON
DAC5CON
DAC6CON
DAC7CON
DAC8CON
DAC9CON
DAC10CON
DAC11CON
0xFFFF0580
0xFFFF0588
0xFFFF0590
0xFFFF0598
0xFFFF05A0
0xFFFF05A8
0xFFFF05B0
0xFFFF05B8
0xFFFF05C0
0xFFFF05C8
0xFFFF05D0
0xFFFF05D8
Table 56. ADuC7121 DACxCON Registers (Default Value = 0x100, Read/Write Access)
Name
Address
DAC0CON
DAC1CON
DAC2CON
DAC3CON
0xFFFF0580
0xFFFF0588
0xFFFF05B0
0xFFFF05D8
Table 57. DAC0CON MMR Bit Designations
Bit(s) Setting Name
Description
[15:9]
0
1
0
0
Reserved.
8
7
6
DACPD
DAC power-down. Set by the user to set DAC output to tristate mode.
DACBUF_LP DAC buffer low power mode. Set by the user to place DAC buffer into a low power mode.
BYP
DAC bypass bit.
Set this bit to bypass the DAC buffer.
Cleared to buffer the DAC output.
DAC update rate.
Set by the user to update the DAC using Timer1.
Cleared by the user to update the DAC using HCLK (core clock).
DAC clear bit.
Set by the user to enable normal DAC operation.
Cleared by the user to reset data register of the DAC to 0.
Mode bit.
Set by the user to operate on DAC normal mode and turn off the interpolator clock source. Cleared by the
user to enable the interpolation mode.
5
4
3
0
0
DACCLK
DACCLR
Mode
0
0
2
Rate
Rate bit. Set by the user to enable the interpolation clock to HCLK/16. Cleared by the user to HCLK/32.
DAC range bits.
[1:0]
DACRNx
00
01
DAC range is from AGND to the internal reference.
External reference DAC range is from AGND to the external reference. See the REFCON MMR in Table 43
for details.
10
11
External reference DAC range is from AGND to the external reference. See the REFCON MMR in Table 43
for more details.
AVDD and AGND.
Rev. D | Page 47 of 102
ADuC7120/ADuC7121
Data Sheet
Table 58. ADuC7120 DACxDAT Registers (Default Value = 0x00000000, Read/Write Access)
Name
Address
DAC0DAT
DAC1DAT
DAC2DAT
DAC3DAT
DAC4DAT
DAC5DAT
DAC6DAT
DAC7DAT
DAC8DAT
DAC9DAT
DAC10DAT
DAC11DAT
0xFFFF0584
0xFFFF058C
0xFFFF0594
0xFFFF059C
0xFFFF05A4
0xFFFF05AC
0xFFFF05B4
0xFFFF05BC
0xFFFF05C4
0xFFFF05CC
0xFFFF05D4
0xFFFF05DC
Table 59. ADuC7121 DACxDAT Registers (Default Value = 0x00000000, Read/Write Access)
Name
Address
DAC0DAT
DAC1DAT
DAC2DAT
DAC3DAT
0xFFFF0584
0xFFFF058C
0xFFFF05B4
0xFFFF05DC
Table 60. DACxDAT MMR Bit Designations
Bits
Description
[31:28]
[27:16]
[15:12]
[11:0]
Reserved.
12-bit data for DACx.
Extra bits for interpolation mode.
Reserved.
Rev. D | Page 48 of 102
Data Sheet
ADuC7120/ADuC7121
Using the DACs
AVDD
The on-chip DAC architecture consists of a resistor string DAC
followed by an output buffer amplifier. The functional equivalent
is shown in Figure 31.
AVDD – 100mV
AVDD
V
REF
EXT_REF
R
R
R
DAC0
100mV
0x00000000
0x0FFF0000
Figure 32. Endpoint Nonlinearities due to Amplifier Saturation
The endpoint nonlinearities conceptually illustrated in Figure 32
worsen as a function of output loading. The ADuC7120/
ADuC7121 specifications assume a 5 kΩ resistive load to
ground at the DAC output. As the output is forced to source
or sink more current, the nonlinear regions at the top or
bottom, respectively, of Figure 32 become larger. Larger
current demands can significantly limit output voltage swing.
R
R
Figure 31. DAC Structure
As shown in Figure 31, the reference source for each DAC is
user selectable in software. It can be either AVDD, VREF, or
EXT_REF. In 0 V to AVDD mode, the DAC output transfer
function spans from 0 V to the voltage at the AVDD pin. In 0 V
to EXT_REF mode, the DAC output transfer function spans
from 0 V to the voltage at the VREF_2.5 pin. In 0 V to VREF mode,
the DAC output transfer function spans from 0 V to the internal
LOW DROPOUT (LDO) REGULATOR
The ADuC7120/ADuC7121 contain an integrated LDO
regulator that generates the core supply voltage (DVDD) of
approximately 2.6 V from the IOVDD supply. As the LDO is
driven from IOVDD, the IOVDD supply voltage must be
greater than 2.7 V.
2.5 V reference, VREF
.
An external compensation capacitor (CT) of 0.47 μF with low
equivalent series resistance (ESR) must be placed close to each
of the DVDD pins. This capacitor also acts as a storage tank of
charge, and supplies an instantaneous charge required by the
core, particularly at the positive edge of the core clock (HCLK).
The DAC output buffer amplifier features a true rail-to-rail
output stage implementation. When unloaded, each output is
capable of swinging to within less than 5 mV of both AVDD and
ground. Moreover, the linearity specification of the DAC (when
driving a 5 kΩ resistive load to ground) is guaranteed through the
full transfer function except for Code 0 to Code 100, and, in 0 V to
AVDD mode only, Code 3995 to Code 4095.
The DVDD voltage generated by the LDO is solely for providing
a supply for the ADuC7120/ADuC7121. Therefore, do not use
a DVDD pin as the power supply pin for any other chip. In
addition, the IOVDD has excellent power supply decoupling
to help improve line regulation performance of the LDO.
Linearity degradation near ground and AVDD is caused by
saturation of the output amplifier, and a general representation of
its effects (neglecting offset and gain error) is shown in Figure 32.
The dotted line in Figure 32 indicates the ideal transfer function,
and the solid line represents what the transfer function may
look like with endpoint nonlinearities due to saturation of the
output amplifier. Note that Figure 32 represents a transfer function
in 0 V to AVDD mode only. In 0 V to VREF or 0 V to EXT_REF
modes (with VREF < AVDD or EXT_REF < AVDD), the lower
nonlinearity is similar. However, the upper portion of the
transfer function follows the ideal line right to the end (VREF in this
case, not AVDD), showing no signs of endpoint linearity errors.
The DVDD pin has no reverse battery, current limit, or thermal
shutdown protection; therefore, it is essential that users of the
ADuC7120/ADuC7121 do not short this pin to ground at any
time during normal operation or during board manufacturing.
Rev. D | Page 49 of 102
ADuC7120/ADuC7121
Data Sheet
developed reference current into an on-board resistor of half the
expected size of the external resistor, a fault signal is generated
if the resistor is less than half the expected value (to an accuracy
of about 20%). The external resistor value is calculated by
CURRENT OUTPUT DACs (IDAC)
The ADuC7120/ADuC7121 provide five output current DACs.
The current sources (five current DACs) feature low noise and
low drift high-side current output with 11-bit resolution. The
five IDACs are as follows: IDAC0 with a 250 mA FS output,
IDAC1 with a 200 mA FS output, IDAC2 with a 45 mA FS
output, IDAC3 with an 80 mA FS output, and IDAC4 with a
20 mA FS output.
R
EXT = VREF/IREF
where:
REF = 380 ꢀA.
REF is the selected reference voltage for the voltage to current
I
V
(V to I) circuit.
The reference current of each IDAC is generated by a precision
internal band gap voltage reference and an external precision
resistor, and as such, the gain error of each IDAC is impacted by
the accuracy of the external resistor. Connect the resistor to the
IDAC and Output Stage Fault Protection
All five IDACs use the same architecture to generate high-side
current whereby only the section that generates the reference
current is shared. A low current is generated first using a current
mode DAC, which is then mirrored up to give the large output
current that is desired. A thermal shutdown circuit protects the
chip from overheating. The IDACs are guaranteed monotonic
to within 11 bits of resolution.
I
REF pin. The noise of each IDAC is limited by its damping
capacitor, CDAMP, which is selected to band limit noise as well as
meet the signal bandwidth. Connect CDAMP_IDACx to PVDD.
A negative metal oxide semiconductor (NMOS) switch is
provided to shut down the IDAC0 diode. The output current
switches off while this switch is on. When the switch is on, the
IDAC0 pin is able to withstand −0.5 V. At power-up or reset,
IDAC0 is powered down by default and its output is high
impedance. When enabled, the IDAC0 output current does
not overshoot.
The bandwidth limit is provided by a programmable internal
resistor and an external capacitor to filter high frequency noise.
This limit also generates a triangle wave from a square wave
input for the IDAC4 only.
The thermal shutdown circuit automatically shuts down all
of the output stages when the chip temperature exceeds a
certain threshold. The intention of the thermal shutdown is
only for protection in the case of a short on an IDAC output.
The overheating of the chip from other causes also triggers a
thermal shutdown but only the IDAC output stage automatically
shuts down. It triggers an interrupt and sets the TSHUT bit in
the IDACSTA register to indicate overheating of the chip.
To reduce the heat dissipation on chip, use a separate power
supply. An internal LDO provides a stable 2.5 V supply for all
low current internal IDACs.
Precision Current Generation and Fault Protection
The reference current is generated either from an on-chip
precision band gap voltage source or from an external voltage
reference by default, which is applied to an external precision
resistor. This resistor is connected to the IREF pin. The band gap
is factory trimmed to obtain a precise initial value and low
temperature drift. The external resistor is an assumed 0.1%
accuracy with 5 ppm drift, and a 0.1 μF external capacitor is
required to bypass high frequency noise.
In case the digital core malfunctions at a temperature lower than
the thermal shutdown trigger point, the circuit can still shut
down the IDAC, but use a watchdog reset to reset the chip. The
TSHUT bit retains its value after a software reset or a watchdog
reset. This bit can only be cleared by a power-on reset, a hardware
reset, or when 0 is written to the IDACSTA register.
A fault detection block is included to stop problems from occurring
if too small a reference resistor is detected. By sending the
PVDD
0.47µF
PVDD
AVDD_IDAC
C
DAMP
3.3V
2.5V
LDO
VOLTAGE
REFERENCE
BUF
BUF
I
OUT
I
REF
PULL_DOWN
R
EXT
PGND
Figure 33. IDAC Configuration
Rev. D | Page 50 of 102
Data Sheet
ADuC7120/ADuC7121
Table 63. TDSCON MMR Bit Designations
Bit(s) Name Setting Description
IDAC MMRS
Table 61. IDAC Control Registers (Read and Write Access)
Name
[7:3]
2
Reserved
The user sets these bits to 0.
The user must set this to 1.
Disable thermal trigger interrupt.
Address (Hex)
0xFFFF0700
0xFFFF070C
0xFFFF0718
0xFFFF0724
0xFFFF0730
0xFFFF073C
0xFFFF0744
Default Value
0x0010
0x0010
0x0010
0x0010
0x0010
0x00
Reserved
DISINT
IDAC0CON
IDAC1CON
IDAC2CON
IDAC3CON
IDAC4CON
TDSCON
1
0
0
Set by the user to 0 to generate
an interrupt if the temperature
passes the thermal shutdown
point.
0
DISSD
Set by the user to 0 to disable the
output current DACs when the
temperature passes a trip point.
IDAC0PULLDOWN
0x00
Table 62. IDACxCON MMR Bit Designations
Table 64. IDAC0PULLDOWN MMR Bit Designations
Bit(s) Name Setting Description
These bits are set to 0 by the
Bit(s) Name
Setting Description
[15:9]
These bits are reserved.
[7:6]
5
Reserved
[8:7]
SFHMODE
Bit shuffling is a method of
increasing the ac precision of
an IDAC. Do not use in
user.
Pulldown
0
IDAC0 pull-down.
applications where dc
performance is important.
00 Shuffle one increment at a
time.
01 Shuffle based on an internal
counter.
10 Shuffle based on the input
data.
11 Reserved.
Set to 1 by the user to pull
down the IDAC0 pin as well as
power down IDAC0.
Set to 0 by the user to disable
the pull-down.
4
PLA_PD_EN
PLA Source
0
PLA output trigger enable.
Set to 1 by the user to enable
the PLA output to trigger the
IDAC0 pull-down.
Set to 0 by the user to disable
this feature.
6
5
4
MSBSHFEN
LSBSHFEN
IDACPD
0
0
1
MSB shuffle enable.
Set by the user to 1 to enable
MSB shuffling.
Set by the user to 0 to disable
MSB shuffling.
3:0
PLA output source for PLA
output trigger enable.
Can select the output of any
element, 0 to 15, by
programming these bits with
the corresponding binary
value.
LSB shuffle enable.
Set by the user to 1 to enable
LSB shuffling.
Set by the user to 0 to disable
LSB shuffling.
Table 65. IDAC Data Registers (Default Value = 0x00000000,
Read and Write Access)
IDAC power-down bit.
Set by the user to 1 to power
down the IDAC. IDAC output is
high impedance.
Set by the user to 0 to power
up the IDAC.
Name
Address (Hex)
0xFFFF0704
0xFFFF0710
0xFFFF071C
0xFFFF0728
0xFFFF0734
IDAC0DAT
IDAC1DAT
IDAC2DAT
IDAC3DAT
IDAC4DAT
3
2
IDACCLK
IDACCLR
0
0
IDAC update rate.
Set by the user to update the
IDAC using Timer1.
Cleared by the user to update
the IDAC using HCLK (core
clock).
Table 66. IDACxDAT MMR Bit Designations
Bit(s) Name Setting Description
These bits are reserved.
[31:28] Reserved
[27:17] Data
IDAC clear bit.
Data from IDACx.
Set by the user to enable
normal IDAC operation.
[16:0]
Reserved
000 These bits are reserved.
Cleared by the user to reset
data register of the IDAC to 0.
1
0
Mode
0
0
Mode bit. This bit must always
be cleared.
Reserved
Set this bit to 0.
Rev. D | Page 51 of 102
ADuC7120/ADuC7121
Data Sheet
Table 67. IDAC Bandwidth Registers (Default Value = 0x00,
Read and Write Access)
OSCILLATOR AND PLL—POWER CONTROL
The ADuC7120/ADuC7121 integrate a 32.768 kHz oscillator, a
clock divider, and a phase-locked loop (PLL). The PLL locks
onto a multiple (1275) of the internal oscillator to provide a
stable 41.78 MHz clock for the system. The core can operate at
this frequency, or at binary submultiples of it, to allow power
saving. The default core clock is the PLL clock divided by 8
(CD = 3) or 5.2 MHz. The core clock frequency can be output on
the XCLK pin as described in Figure 34. When the XCLK pin
outputs the core clock, the output signal is not buffered and is
not suitable for use as a clock source to an external device
without an external buffer.
Name
Address
IDAC0BW
IDAC1BW
IDAC2BW
IDAC3BW
IDAC4BW
0xFFFF0708
0xFFFF0714
0xFFFF0720
0xFFFF072C
0xFFFF0738
Table 68. IDACxBW MMR Bit Designations
Bit(s) Name Setting Description
The user sets these bits to 0.
[7:4]
[3:0]
Reserved
BW
Bandwidth control bits. Defines
the 3 dB bandwidth of the
resistor capacitor (RC) low-pass
filter, assuming a 0.01 μF
capacitor on the CDAMP_IDACx
pins of the IDACx.
A power-down mode is available on the ADuC7120/ADuC7121.
The operating mode, clocking mode, and programmable clock
divider are controlled via two MMRs: PLLCON (see Table 73) and
POWCON (see Table 74). PLLCON controls the operating
mode of the clock system, and POWCON controls the core
clock frequency and the power-down mode.
000 100 kHz.
001 28.7 kHz.
010 15 kHz.
011 7.8 kHz.
100 4 kHz.
1
XTALO
XTALI
INT. 32kHz
OSCILLATOR
WATCHDOG
TIMER
CRYSTAL
OSCILLATOR
101 2.2 kHz.
110 1.2 kHz.
TIMERS
Others
Not defined.
AT POWER-UP
OCLK 32.768kHz
Table 69. IDAC Status Register (Default Value = 0x00, Read
and Write Access)
41.78MHz
PLL
P1.4/XCLK
MDCLK
Name
Address (Hex)
UCLK
ANALOG
PERIPHERALS
IDACSTA
0xFFFF0740
2
I C
Table 70. IDACSTA MMR Bit Designations
Bit(s) Name Setting Description
These bits are set to 0 by the user.
CD
/2
CD
CORE
HCLK
[7:2]
1
Reserved
TSHUT
0
Thermal shutdown error status
bit.
1
32.768kHz ±3%
P1.4/ECLK
Figure 34. Clocking System
Set to 1 by the core indicating a
thermal shutdown event.
Set to 0 by the core indicating
the IDACs are within operating
temperature.
External Crystal Selection
To switch to an external crystal, use the following procedure:
1. Enable the Timer2 interrupt and configure it for a timeout
period of >120 µs.
0
Reserved
Reserved.
2. Follow the write sequence to the PLLCON register, setting
the MDCLK bits to 01 and clearing the OSEL bit.
3. Force the device into nap mode by writing the correct write
sequence to the POWCON register.
4. When the device is interrupted from nap mode by the Timer2
interrupt source, the clock source switches to the external
clock.
In noisy environments, noise can couple to the external crystal
pins, and PLL can lose lock momentarily. A PLL interrupt is
provided in the interrupt controller. The core clock is immediately
halted, and this interrupt is serviced only when the lock is restored.
Rev. D | Page 52 of 102
Data Sheet
ADuC7120/ADuC7121
In case of crystal loss, use the watchdog timer. During initialization,
a test on the RSTSTA register can determine if the reset came
from the watchdog timer.
External Clock Selection
To switch to an external clock on P1.4 (of the P1.4/PWM1/
ECLK/XCLK/PLAI[8] pin), configure P1.4 using PLLCON
register. The external clock can be up to 41.78 MHz.
Example Source Code for External Crystal Selection
T2LD = 5;
Example Source Code for External Clock Selection
TCON = 0x480;
T2LD = 5;
TCON = 0x480;
while ((T2VAL == t2val_old) || (T2VAL > 3))
//ensures timer value loaded
while ((T2VAL == t2val_old) || (T2VAL > 3))
//ensures timer value loaded
IRQEN = 0x10;
//enable T2 interrupt
IRQEN = 0x10;
//enable T2 interrupt
PLLKEY1 = 0xAA;
PLLCON = 0x01;
PLLKEY2 = 0x55;
PLLKEY1 = 0xAA;
PLLCON = 0x03; //Select external clock
PLLKEY2 = 0x55;
POWKEY1 = 0x01;
POWKEY1 = 0x01;
POWCON = 0x27;
// set core into nap mode
POWCON = 0x27; // Set Core into Nap mode
POWKEY2 = 0xF4;
POWKEY2 = 0xF4;
Power Control System
These devices offer a choice of operating modes. Table 71
describes what part of the ADuC7120/ADuC7121 is powered
on in the different modes and indicates the power-up time.
Table 72 gives some typical values of the total current
consumption (analog + digital supply currents) in the different
modes, depending on the clock divider bits. The ADC is turned
off. These values also include current consumption of the
regulator and other parts on the test board on which these
values are measured.
Table 71. Operating Modes
Mode
Active
Pause
Nap
Sleep
Stop
Core
Peripherals
PLL
On
On
On
Off
Off
XTAL/Timer2/Timer3
External IRQ Start-Up/Power-On Time
On
On
On
Off
Off
Off
On
On
On
On
Off
On
On
On
On
On
66 ms at CD = 0
Off
Off
Off
Off
24 ns at CD = 0; 3.06 µs at CD = 7
24 ns at CD = 0; 3.06 µs at CD = 7
1.58 ms
1.7 ms
Table 72. Typical Current Consumption at 25°C
PC Bits,
Bits[2:0]
Mode
Active
Pause
Nap
Sleep
Stop
CD = 0
33.1
22.7
3.8
0.4
0.4
CD = 1
21.2
13.3
3.8
0.4
0.4
CD = 2
13.8
8.5
3.8
0.4
CD = 3
10
6.1
3.8
0.4
CD = 4
CD = 5
7.2
4.3
3.8
0.4
CD = 6
6.7
4
3.8
0.4
CD = 7
6.45
3.85
3.8
0.4
0.4
000
001
010
011
8.1
4.9
3.8
0.4
0.4
100
0.4
0.4
0.4
0.4
Rev. D | Page 53 of 102
ADuC7120/ADuC7121
Data Sheet
MMRs and Keys
POWKEYx Registers
To prevent accidental programming, a certain sequence must be
followed when writing in the PLLCON and POWCON registers
(see Table 75).
Name:
POWKEY1
Address:
Default value:
Access:
0xFFFF0404
0x0000
PLLKEYx Registers
Name:
PLLKEY1
0xFFFF0410
0x0000
Write only
Address:
Default value:
Access:
Name:
POWKEY2
0xFFFF040C
0x0000
Address:
Default value:
Access:
Write only
Name:
PLLKEY2
0xFFFF0418
0x0000
Write only
Address:
Default value:
Access:
POWCON Register
Name:
POWCON
Write only
Address:
Default value:
Access:
0xFFFF0408
0x0003
PLLCON Register
Name:
PLLCON
Read and write
Address:
Default value:
Access:
0xFFFF0414
0x21
Table 74. POWCON MMR Bit Designations
Bit(s) Name
Setting
Description
7
Reserved.
Read and write
[6:4]
PC
Operating modes.
000 Normal mode.
001 Pause mode.
010 Nap mode.
Table 73. PLLCON MMR Bit Designations
Bit(s) Name
Setting
Description
011 Sleep mode. IRQ0 to IRQ3 and
Timer2 can wake up the devices.
100 Stop mode.
[7:6]
Reserved.
5
OSEL
32 kHz PLL input selection.
Set by the user to use the internal
32 kHz oscillator.
Others
Reserved.
3
RSVD
CD
Reserved.
Set by default.
Cleared by the user to use the
external 32 kHz crystal.
[2:0]
CPU clock divider bits.
000 41.779200 MHz.
[4:2]
[1:0]
Reserved.
001 20.889600 MHz.
010 10.444800 MHz.
011 5.222400 MHz.
100 2.611200 MHz.
101 1.305600 MHz.
110 654.800 kHz.
111 326.400 kHz.
MDCLK
Clocking modes.
00 Reserved.
01 PLL. Default configuration.
10 Reserved.
11 External clock on the
P1.4/PWM1/ECLK/XCLK/PLAI[8]
pin.
Table 75. PLLCON and POWCON Write Sequence
PLLCON
POWCON
PLLKEY1 = 0xAA
PLLCON = 0x01
PLLKEY2 = 0x55
POWKEY1 = 0x01
POWCON = user value
POWKEY2 = 0xF4
Rev. D | Page 54 of 102
Data Sheet
ADuC7120/ADuC7121
DIGITAL PERIPHERALS
The PWM clock is selectable via the PWMCON1 register with
one of the following values: UCLK divide by 2, divide by 4,
divide by 8, divide by 16, divide by 32, divide by 64, divide by 128,
or divide by 256. The length of a PWM period is defined by
PWMxLEN.
PULSE-WIDTH MODULATOR (PWM) OVERVIEW
The ADuC7120/ADuC7121 integrate a 6-channel PWM interface.
The PWM outputs can drive an H-bridge or can be used as
standard PWM outputs. On power-up, the PWM outputs default
to H-bridge mode, which ensures that the motor is turned off
by default. In standard PWM mode, the outputs are arranged as
three pairs of PWM pins. Users have control over the period of
each pair of outputs and over the duty cycle of each individual
output.
The PWM waveforms are set by the count value of the 16-bit
timer and the compare registers contents as shown with the
PWM1 and PWM2 waveforms in Figure 35.
The low-side waveform, PWM2, goes high when the timer
count reaches PWM1LEN, and it goes low when the timer
count reaches the value held in PWM1COM3 or when the
high-side waveform PWM1 goes low.
In all modes, the PWMxCOMx MMRs control the point at
which the PWM outputs change state. An example of the first
pair of PWM outputs (PWM1 and PWM2) timing is shown in
Figure 35.
The high-side waveform, PWM1, goes high when the timer
count reaches the value held in PWM1COM1, and it goes low
when the timer count reaches the value held in PWM1COM2.
HIGH SIDE
(PWM1)
LOW SIDE
(PWM2)
PWM1COM3
PWM1COM2
PWM1COM1
PWM1LEN
Figure 35. Example of the First Pair of PWM Outputs (PWM1 and PWM2) Timing
Table 76. PWM MMRs
Name
Function
PWMCON1
PWM1COM1
PWM1COM2
PWM1COM3
PWM1LEN
PWM2COM1
PWM2COM2
PWM2COM3
PWM2LEN
PWM3COM1
PWM3COM2
PWM3COM3
PWM3LEN
PWMCON2
PWMICLR
PWM control
Compare Register 1 for PWM Output 1 and PWM Output 2
Compare Register 2 for PWM Output 1 and PWM Output 2
Compare Register 3 for PWM Output 1 and PWM Output 2
Frequency control for PWM Output 1 and PWM Output 2
Compare Register 1 for PWM Output 3 and PWM Output 4
Compare Register 2 for PWM Output 3 and PWM Output 4
Compare Register 3 for PWM Output 3 and PWM Output 4
Frequency control for PWM Output 3 and PWM Output 4
Compare Register 1 for PWM Output 5 and PWM Output 6
Compare Register 2 for PWM Output 5 and PWM Output 6
Compare Register 3 for PWM Output 5 and PWM Output 6
Frequency control for PWM Output 5 and PWM Output 6
PWM convert start control
PWM interrupt clear
Rev. D | Page 55 of 102
ADuC7120/ADuC7121
Data Sheet
Table 77. PWMCON1 MMR Bit Designations (Address = 0xFFFF0F80, Default Value = 0x0012)
Bit(s) Name
Description
15
14
Reserved
This bit is reserved.
Enables PWM synchronization.
SYNC
Set to 1 by the user so that all PWM counters are reset on the next clock edge after the detection of a high to low
transition on SYNC of the P0.3/MISO/PLAO[12]/SYNC pin.
Cleared by the user to ignore transitions on SYNC of the P0.3/MISO/PLAO[12]/SYNC pin.
Set to 1 by the user to invert PWM6.
Cleared by the user to use PWM6 in normal mode.
Set to 1 by the user to invert PWM4.
Cleared by the user to use PWM4 in normal mode.
Set to 1 by the user to invert PWM2.
Cleared by the user to use PWM2 in normal mode.
13
12
11
10
PWM6INV
PWM4NV
PWM2INV
PWMTRIP
Set to 1 by the user to enable PWM trip interrupt. When the PWMTRIP input is low, the PWMEN bit is cleared, and an
interrupt is generated.
Cleared by the user to disable the PWMTRIP interrupt.
9
ENA
If HOFF = 0 and HMODE = 1. If HOFF = 1 and HMODE = 1, see Table 78. If not in H-Bridge mode, this bit has no effect.
Set to 1 by the user to enable PWM outputs.
Cleared by the user to disable PWM outputs.
[8:6]
PWMCP[2:0] PWM clock prescaler bits. Sets the UCLK divider.
000 = UCLK divide by 2.
001 = UCLK divide by 4.
010 = UCLK divide by 8.
011 = UCLK divide by 16.
100 = UCLK divide by 32.
101 = UCLK divide by 64.
110 = UCLK divide by 128.
111 = UCLK divide by 256.
5
4
POINV
HOFF
Set to 1 by the user to invert all PWM outputs.
Cleared by the user to use PWM outputs as normal.
High-side off.
Set to 1 by the user to force PWM1 and PWM3 outputs high, which also forces PWM2 and PWM4 low.
Cleared by the user to use the PWM outputs as normal.
Load compare bit.
3
LCOMP
Set to 1 by the user to load the internal compare registers with the values in PWMxCOMx on the next transition of
the PWM timer from 0x00 to 0x01.
Cleared by the user to use the values previously stored in the internal compare registers.
Direction control.
Set to 1 by the user to enable PWM1 and PWM2 as the output signals while PWM3 and PWM4 are held low.
Cleared by the user to enable PWM3 and PWM4 as the output signals while PWM1 and PWM2 are held low.
Enables H-bridge mode.
Set to 1 by the user to enable H-Bridge mode and Bits[5:2] of PWMCON1.
Cleared by the user to operate the PWMs in standard mode.
Set to 1 by the user to enable all PWM outputs.
2
1
0
DIR
HMODE
PWMEN
Cleared by the user to disable all PWM outputs.
Rev. D | Page 56 of 102
Data Sheet
ADuC7120/ADuC7121
In H-bridge mode, HMODE = 1 and Table 77 determine the
PWM outputs, as listed in Table 78.
Table 80. PWMCON2 MMR Bit Designations (Address =
0xFFFF0FB4, Default Value = 0x00)
Bit
Name
Value Description
Table 78. PWM Output Selection
7
CSEN
Set to 1 by the user to enable the
PWM to generate a convert start
signal.
Cleared by the user to disable the
PWM convert start signal.
PWMCOM1 MMR
PWM Outputs
ENA HOFF POINV DIR PWM1 PWM2 PWMR3 PWM4
0
X1
1
1
1
1
0
1
0
0
0
0
X1
X1
0
0
1
X1
X1
0
1
0
1
1
0
HS1
HS1
1
1
0
0
1
1
1
0
LS1
0
1
LS1
HS1
0
1
HS1
[6:4] Reserved
This bit is reserved.
LS1
LS1
1
[3:0] CSD3 to
CSD0
Convert start delay. Delays the
convert start signal by a number of
clock pulses.
1
1
1 X is a don’t care bit, HS is high side, and LS is low side.
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
4 clock pulses.
8 clock pulses.
12 clock pulses.
16 clock pulses.
20 clock pulses.
24 clock pulses.
28 clock pulses.
32 clock pulses.
36 clock pulses.
40 clock pulses.
44 clock pulses.
48 clock pulses.
52 clock pulses.
56 clock pulses.
60 clock pulses.
64 clock pulses.
On power-up, PWMCON1 defaults to 0x12 (HOFF = 1 and
HMODE = 1). All GPIO pins associated with the PWM are
configured in PWM mode by default (see Table 79).
Table 79. Compare Register (Default Value = 0x0000, Access
Is Read/Write)
Name
Address
Default Value
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PWM1COM1
PWM1COM2
PWM1COM3
PWM2COM1
PWM2COM2
PWM2COM3
PWM3COM1
PWM3COM2
PWM3COM3
0xFFFF0F84
0xFFFF0F88
0xFFFF0F8C
0xFFFF0F94
0xFFFF0F98
0xFFFF0F9C
0xFFFF0FA4
0xFFFF0FA8
0xFFFF0FAC
When calculating the time from the convert start delay to the
start of an ADC conversion, take account of internal delays. The
following example shows the case for a delay of four clocks. One
additional clock is required to pass the convert start signal to
the ADC logic. When the ADC logic receives the convert start
signal, an ADC conversion begins on the next ADC clock edge
(see Figure 36).
The PWM trip interrupt can be cleared by writing any value to
the PWMICLR MMR. When using the PWM trip interrupt,
ensure that the PWM interrupt is cleared before exiting the ISR
to prevent generation of multiple interrupts.
PWM CONVERT START CONTROL
The PWM can generate an ADC convert start signal after
the active low-side signal goes high. Note that there is a
programmable delay between when the low-side signal goes
high and the convert start signal is generated, which is controlled
via the PWMCON2 MMR. If the delay selected is higher than
the width of the PWM pulse, the interrupt remains low.
UCLOCK
LOW SIDE
COUNT
PWM SIGNAL
TO CONVST
SIGNAL PASSED
TO ADC LOGIC
Figure 36. ADC Conversion
Rev. D | Page 57 of 102
ADuC7120/ADuC7121
Data Sheet
GENERAL-PURPOSE INPUT/OUTPUT
The ADuC7120/ADuC7121 provide 32 general-purpose,
bidirectional input/output (GPIO) pins. All input/output pins
are 5 V tolerant, meaning that the GPIOs support an input
voltage of 5 V. In general, many of the GPIO pins have multiple
functions (see Table 81). By default, the GPIO pins are configured
in GPIO mode.
Name:
GP2CON
Address:
Default value:
Access:
0xFFFF0D08
0x00000000
Read and write
All GPIO pins have an internal pull-up resistor (of about 100 kΩ)
and their drive capability is 1.6 mA. A maximum of 20 GPIOs
can drive 1.6 mA at the same time. The 32 GPIOs are grouped
into four ports: Port 0 to Port 3. Each port is controlled by four
or five MMRs, with x representing the port number.
Name:
GP3CON
Address:
Default value:
Access:
0xFFFF0D0C
0x00000000
Read and write
GPxCON Registers
Name:
GP0CON
Address:
Default value:
Access:
0xFFFF0D00
0x11000000
Read and write
The input level of any GPIO can be read at any time in the
GPxDAT MMR, even when the pin is configured in a mode
other than GPIO. The PLA input is always active.
When the ADuC7120/ADuC7121 enter power-saving mode,
the GPIO pins retain their state.
Name:
GP1CON
GPxCON is the Port x control register, and it selects the
function of each pin of Port x, as described in Table 81.
Address:
Default value:
Access:
0xFFFF0D04
0x00000000
Read and write
Table 81. GPIO Pin Function Designations
Configuration (See Table 82 for the GPxCON MMR Bit Designations)
Port
Pin
00
01
10
11
0
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
SCL0
SDA0
SPICLK
MISO
MOSI
CS
PLAI[5]
PLAI[4]
PLAO[13]
PLAO[12]
PLAI[11]
PLAI[10]
JTAG disabled
JTAG disabled ADCBUSY
SYNC (PWM)
TRIP (PWM)
ADCCONVST
P0.6
P0.7
GPIO
GPIO
MRST
TRST
PLAI[2]
PLAI[3]
1
P1.0
P1.1
P1.21
P1.31
P1.4
P1.5
P1.6
P1.7
GPIO
GPIO
TDI (JTAG)
TDO (JTAG)
GPIO
GPIO
GPIO
GPIO
SIN
SOUT
SCL1
SDA1
PLAI[7]
PLAI[6]
PLAO[15]
PLAO[14]
PLAI[8]
PLAI[9]
PLAO[5]
PLAO[4]
PWM1
PWM2
ECLK/XCLK
Rev. D | Page 58 of 102
Data Sheet
ADuC7120/ADuC7121
Configuration (See Table 82 for the GPxCON MMR Bit Designations)
Port
Pin
00
01
10
11
2
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
GPIO/IRQ0
GPIO/IRQ1
GPIO
GPIO/IRQ2
GPIO
GPIO
GPIO/IRQ3
GPIO
PLAI[13]
PLAI[12]
PLAI[1]
PLAI[14]
PLAO[7]
PLAO[6]
PLAI[15]
PLAI[0]
PWM5
PWM6
3
GPIO
GPIO
GPIO/IRQ4
GPIO/IRQ5
GPIO
GPIO
GPIO
GPIO/BM
PLAO[0]
PLAO[1]
PLAO[2]
PLAO[3]
PLAO[8]
PLAO[9]
PLAO[10]
PLAO[11]
PWM3
PWM4
1 Reconfiguring these pins disables JTAG mode. Erase to reenable JTAG access after changing default value.
Name:
GP1PAR
Table 82. GPxCON MMR Bit Designations
Bit(s) Description
Address:
Default value:
Access:
0xFFFF0D3C
0x00000000
Read and write
[31:30] Reserved
[29:28] Selects function of the Px.7 pin
[27:26] Reserved
[25:24] Selects function of the Px.6 pin
[23:22] Reserved
Name:
GP2PAR
[21:20] Selects function of the Px.5 pin
[19:18] Reserved
Address:
Default value:
Access:
0xFFFF0D4C
0x00000000
Read and write
[17:16] Selects function of the Px.4 pin
[15:14] Reserved
[13:12] Selects function of the Px.3 pin
[11:10] Reserved
[9:8]
[7:6]
[5:4]
[3:2]
[1:0]
Selects function of the Px.2 pin
Reserved
Name:
GP3PAR
Selects function of the Px.1 pin
Reserved
Address:
Default value:
Access:
0xFFFF0D5C
0x00222222
Read and write
Selects function of the Px.0 pin
GPxPAR Registers
The GPxPAR registers program the parameters for Port 0, Port 1,
Port 2, and Port 3. Note that the GPxDAT MMR must always be
written after changing the GPxPAR MMR.
Table 83. GPxPAR MMR Bit Designations
Bit(s)
[31:29]
28
Description
Reserved
Pull-up disable Px.7 pin
Set to 1 to enable the pull-up
Clear to 0 to disable the pull-up
Reserved
Name:
GP0PAR
Address:
Default value:
Access:
0xFFFF0D2C
0x20000000
Read and write
[27:25]
24
Pull-up disable Px.6 pin
Reserved
[23:21]
20
Pull-up disable Px.5 pin
Reserved
[19:17]
16
Pull-up disable Px.4 pin
Rev. D | Page 59 of 102
ADuC7120/ADuC7121
Data Sheet
GPxSET Registers
The GPxSET registers provide a data set for the Port x registers.
Bit(s)
[15:13]
12
Description
Reserved
Pull-up disable Px.3 pin
Reserved
Name:
GP0SET
[11:9]
8
Pull-up disable Px.2 pin
Reserved
Address:
Default value:
Access:
0xFFFF0D24
0x000000XX
Write only
[7:5]
4
Pull-up disable Px.1 pin
Reserved
[3:1]
0
Pull-up disable Px.0 pin
GPxDAT Register
Name:
GP1SET
GPxDAT is a Port x configuration and data register. It configures
the direction of the GPIO pins of Port x, sets the output value
for the pins configured as output, and receives and stores the
input value of the pins configured as inputs.
Address:
Default value:
Access:
0xFFFF0D34
0x000000XX
Write only
Name:
GP0DAT
Address:
Default value:
Access:
0xFFFF0D20
0x000000XX
Read and write
Name:
GP2SET
Address:
Default value:
Access:
0xFFFF0D44
0x000000XX
Write only
Name:
GP1DAT
Address:
Default value:
Access:
0xFFFF0D30
0x000000XX
Read and write
Name:
GP3SET
Address:
Default value:
Access:
0xFFFF0D54
0x000000XX
Write only
Name:
GP2DAT
Address:
Default value:
Access:
0xFFFF0D40
0x000000XX
Read and write
Table 85. GPxSET MMR Bit Designations
Bit(s)
Description
[31: 24]
[23:16]
Reserved.
Data Port x set bit.
Set to 1 by the user to set the bit on Port x; also sets
the corresponding bit in the GPxDAT MMR.
Name:
GP3DAT
Address:
Default value:
Access:
0xFFFF0D50
0x000000XX
Read and write
Cleared to 0 by user; does not affect the data out.
Reserved.
[15:0]
Table 84. GPxDAT MMR Bit Designations
Bit(s) Description
[31:24] Direction of the data.
Set to 1 by the user to configure the GPIO pin as an
output.
Cleared to 0 by the user to configure the GPIO pin as
an input.
[23:16] Port x data output.
[15:8]
[7:0]
Reflect the state of Port x pins at reset (read only).
Port x data input (read only).
Rev. D | Page 60 of 102
Data Sheet
ADuC7120/ADuC7121
GPxCLR Registers
Name:
GP3CLR
The GPxCLR registers are data clear for Port x registers.
Address:
Default value:
Access:
0xFFFF0D58
0x000000XX
Write only
Name:
GP0CLR
Address:
Default value:
Access:
0xFFFF0D28
0x000000XX
Write only
Table 86. GPxCLR MMR Bit Designations
Bit(s)
Description
[31:24]
[23:16]
Reserved.
Name:
GP1CLR
Data Port x clear bit.
Set to 1 by the user to clear bit on Port x; also clears
the corresponding bit in the GPxDAT MMR.
Cleared to 0 by user; does not affect the data output.
Reserved.
Address:
Default value:
Access:
0xFFFF0D38
0x000000XX
Write only
[15:0]
Name:
GP2CLR
Address:
Default value:
Access:
0xFFFF0D48
0x000000XX
Write only
GPxOCE Registers
Open collector functionality is available on the following GPIO pins: P1.7 and P1.6, Port 2 and Port 3.
Table 87. GPxOCE MMR Bit Designations
Bit(s)
[31:8]
7
Description
Reserved.
GPIO Px.7 open collector enable.
Set to 1 by the user to enable the open collector.
Set to 0 by the user to disable the open collector.
GPIO Px.6 open collector enable.
Set to 1 by the user to enable the open collector.
Set to 0 by the user to disable the open collector.
GPIO Px.5 open collector enable.
Set to 1 by the user to enable open collector.
Set to 0 by the user to disable the open collector.
GPIO Px.4 open collector enable.
Set to 1 by the user to enable open collector.
Set to 0 by the user to disable the open collector.
GPIO Px.3 open collector enable.
Set to 1 by the user to enable open collector.
Set to 0 by the user to disable the open collector.
GPIO Px.2 open collector enable.
Set to 1 by the user to enable open collector.
Set to 0 by the user to disable the open collector.
GPIO Px.1 open collector enable.
Set to 1 by the user to enable open collector.
Set to 0 by the user to disable the open collector.
GPIO Px.0 open collector enable.
6
5
4
3
2
1
0
Set to 1 by the user to enable open collector.
Set to 0 by the user to disable the open collector.
Rev. D | Page 61 of 102
ADuC7120/ADuC7121
Data Sheet
UART SERIAL INTERFACE
The ADuC7120/ADuC7121 feature a 16,450-compatible
universal asynchronous receiver transmitter (UART). The
UART is a full duplex, universal, asynchronous receiver/
transmitter. The UART performs serial to parallel conversion
on data characters received from a peripheral device, and
parallel to serial conversion on data characters received from
the ARM7TDMI. The UART features a fractional divider that
facilitates high accuracy baud rate generation. The UART
functionality is available on the P1.0/SIN/SCL1/PLAI[7] and
P1.1/SOUT/SDA1/PLAI[6] pins of the ADuC7120/ADuC7121.
For example, generation of 19,200 baud
41.78MHz
2048 19200×16×67×2
N
M +
M +
=
N
=1.015
2048
where:
M = 1.
N = 0.015 × 2048 = 30
41.78MHz
Baud Rate =
The serial communication adopts an asynchronous protocol
that supports various word length, stop bits, and parity
generation options selectable in the configuration register.
30
2048
16 × 67×2× 1+
where Baud Rate = 19,219 bps.
BAUD RATE GENERATION
UART REGISTER DEFINITION
The ADuC7120/ADuC7121 feature two methods of generating
the UART baud rate: normal 450 UART baud rate generation
and ADuC7120/ADuC7121 fractional divider.
The UART interface consists of the following 10 registers:
•
•
•
•
•
•
•
•
•
•
COMTX: 8-bit transmit register
COMRX: 8-bit receive register
Normal 450 UART Baud Rate Generation
COMDIV0: divisor latch (low byte)
COMDIV1: divisor latch (high byte)
COMCON0: Line Control Register 0
COMCON1: Line Control Register 1
COMSTA0: Line Status Register 0
COMIEN0: interrupt enable register
COMIID0: interrupt identification register
COMDIV2: 16-bit fractional baud divide register
The baud rate is a divided version of the core clock using the
value in COMDIV0 and COMDIV1 MMRs (16-bit value,
divisor latch (DL)). The standard baud rate generator formula is
Baud Rate = 41.78 MHz/(16 × 2 × DL)
(1)
Table 88 lists common baud rate values.
Table 88. Baud Rate Using the Standard Baud Rate Generator
Baud Rate (bps) DL
Actual Baud Rate (bps) Error (%)
COMTX, COMRX, and COMDIV0 share the same address
location. COMTX and COMRX can be accessed when Bit 7 in
the COMCON0 register is cleared. COMDIV0 can be accessed
when Bit 7 of COMCON0 is set.
9600
19,200
115,200
0x88 9600
0x44 19,200
0x0B 118,691
0%
0%
3%
Fractional Divider
UART TX Register
The fractional divider combined with the normal baud rate
generator allows the generating of a wider range of more
accurate baud rates.
Write to this 8-bit register to transmit data using the UART.
Name:
COMTX
FBEN
CORE
CLOCK
/2
Address:
Access:
0xFFFF0800
Write only
/16DL
UART
/(M + N/2048)
Figure 37. Baud Rate Generation Options
UART RX Register
Calculation of the baud rate using fractional divider is as
follows:
This 8-bit register is read from to receive data transmitted using
the UART.
41.78 MHz
(2)
Baud Rate =
Name:
COMRX
0xFFFF0800
0x00
N
2048
16 × DL ×2× M +
Address:
Default value:
Access:
41.78 MHz
2048 Baud Rate ×16 × DL×2
N
M +
=
Read only
Rev. D | Page 62 of 102
Data Sheet
ADuC7120/ADuC7121
UART Divisor Latch Register 0
UART Control Register 0
This 8-bit register contains the least significant byte of the
divisor latch that controls the baud rate at which the UART
operates.
This 8-bit register controls the operation of the UART in
conjunction with COMCON1.
Name:
COMCON0
0xFFFF080C
Name:
COMDIV0
0xFFFF0800
0x00
Address:
Address:
Default value:
Access:
Default value: 0x00
Access: Read and write
Read and write
UART Divisor Latch Register 1
This 8-bit register contains the most significant byte of the
divisor latch that controls the baud rate at which the UART
operates.
Name:
COMDIV1
0xFFFF0804
Address:
Default value: 0x00
Access:
Read and write
Table 89. COMCON0 MMR Bit Designations
Bit(s) Name Description
7
6
5
4
3
2
DLAB
BRK
SP
Divisor latch access.
Set by the user to enable access to COMDIV0 and COMDIV1 registers.
Cleared by the user to disable access to COMDIV0 and COMDIV1 and enable access to COMRX, COMTX, and COMIEN0.
Set break.
Set by the user to force the transmit pin (SOUT) to 0.
Cleared to operate in normal mode.
Stick parity. Set by the user to force parity to defined values.
1 if EPS = 1 and PEN = 1.
0 if EPS = 0 and PEN = 1.
EPS
Even parity select bit.
Set for even parity.
Cleared for odd parity.
PEN
STOP
Parity enable bit.
Set by the user to transmit and check the parity bit.
Cleared by the user for no parity transmission or checking.
Stop bit.
Set by the user to transmit 1.5 stop bits if the word length is five bits, or two stop bits if the word length is six, seven, or
eight bits. The receiver checks the first stop bit only, regardless of the number of stop bits selected.
Cleared by the user to generate one stop bit in the transmitted data.
[1:0]
WLS
Word length select.
00 = five bits.
01 = six bits.
10 = seven bits.
11 = eight bits.
Rev. D | Page 63 of 102
ADuC7120/ADuC7121
Data Sheet
UART Control Register 1
UART Status Register 0
This 8-bit register controls the operation of the UART in
conjunction with COMCON0.
This 8-bit read only register reflects the current status on the
UART.
Name:
COMCON1
0xFFFF0810
Name:
COMSTA0
Address:
Address:
0xFFFF0814
Default value: 0x00
Default value: 0x60
Access: Read only
Access:
Read and write
Table 90. COMCON1 MMR Bit Designations
Bit(s)
[7:5]
4
Name
Description
Reserved bits. Not used.
LOOPBACK
RTS
Loopback. Set by the user to enable loopback mode. In loopback mode, SOUT is forced high.
Reserved bits. Not used.
[3:2]
1
Request to send.
Set by the user to force the RTS output to 0.
Cleared by the user to force the RTS output to 1.
Data terminal ready.
0
DTR
Set by the user to force the DTR output to 0.
Cleared by the user to force the DTR output to 1.
Table 91. COMSTA0 MMR Bit Designations
Bit Name Description
7
6
Reserved.
TEMT
THRE
COMTX and shift register empty status bit.
Set automatically if COMTX and the shift register are empty. This bit indicates that the data has been transmitted, that is, no
more data is present in the shift register.
Cleared automatically when writing to COMTX.
COMTX empty status bit.
5
Set automatically if COMTX is empty. COMTX can be written as soon as this bit is set; the previous data may not have been
transmitted yet and can still be present in the shift register.
Cleared automatically when writing to COMTX.
4
3
2
1
0
BI
Break indicator.
Set when SIN of the P1.0/SIN/SCL1/PLAI[7] pin is held low for more than the maximum word length.
Cleared automatically.
FE
PE
OE
DR
Framing error.
Set when the stop bit is invalid.
Cleared automatically.
Parity error.
Set when a parity error occurs.
Cleared automatically.
Overrun error.
Set automatically if data are overwritten before being read.
Cleared automatically.
Data ready.
Set automatically when COMRX is full.
Cleared by reading COMRX.
Rev. D | Page 64 of 102
Data Sheet
ADuC7120/ADuC7121
UART Interrupt Enable Register 0
UART Fractional Divider Register
This 8-bit register enables and disables the individual UART
interrupt sources.
This 16-bit register controls the operation of the fractional
divider for the ADuC7120/ADuC7121.
Name:
COMIEN0
Name:
COMDIV2
Address:
0xFFFF0804
Address:
0xFFFF082C
Default value: 0x00
Default value: 0x0000
Access: Read and write
Access:
Read and write
UART Interrupt Identification Register 0
This 8-bit register reflects the source of the UART interrupt.
Name:
COMIID0
Address:
0xFFFF0808
Default value: 0x01
Access:
Read only
Table 92. COMIEN0 MMR Bit Designations
Bit(s) Name Description
[7:3]
2
Reserved. Not used.
Cleared by the user.
ELSI
Receive pin (SIN) status interrupt enable bit.
Set by the user to enable generation of an interrupt if any of the COMSTA0 register bits, Bits[3:1], are set.
Cleared by the user.
1
0
ETBEI
ERBFI
Enable transmit buffer empty interrupt.
Set by the user to enable an interrupt when the buffer is empty during a transmission, that is, when COMSTA, Bit 5 is set.
Cleared by the user.
Enable receive buffer full interrupt.
Set by the user to enable an interrupt when the buffer is full during a reception.
Cleared by the user.
Table 93. COMIID0 MMR Bit Designations
Status Bits, Bits[2:1]
Bit 0 NINT
Priority
Definition
Clearing Operation
00
11
10
01
00
1
0
0
0
0
No interrupt
1
2
3
4
Receive line status interrupt
Receive buffer full interrupt
Transmit buffer empty interrupt
Modem status interrupt
Read COMSTA0
Read COMRX
Write data to COMTX or read COMIID0
Read COMSTA1 register
Table 94. COMDIV2 MMR Bit Designations
Bit
Name
Description
15
FBEN
Fractional baud rate generator enable bit.
Set by the user to enable the fractional baud rate generator.
Cleared by the user to generate the baud rate using the standard 450 UART baud rate generator.
Reserved.
[14:13]
[12:11] FBM[1:0]
M. If FBM = 0, M = 4. See Equation 2 for the calculation of the baud rate using a fractional divider and Table 88 for
common baud rate values.
[10:0]
FBN[10:0] N. See Equation 2 for the calculation of the baud rate using a fractional divider and Table 88 for common baud rate values.
Rev. D | Page 65 of 102
ADuC7120/ADuC7121
Data Sheet
I2C PERIPHERALS
The ADuC7120/ADuC7121 incorporate two I2C peripherals
that can be configured as a fully I2C-compatible bus master device
or as a fully I2C-compatible bus slave device. Both peripherals
are identical.
Bit 4 of the GP0CON register must be set to 1 to enable I2C
mode. To configure the I2C1 pins (SCL1, SDA1), Bit 1 and Bit 5 of
the GP1CON register must be set to 1 to enable I2C mode, as
shown in the General-Purpose Input/Output section.
The pins used for data transfer, SDAx and SCLx, are configured
in a wired-AND format that allows arbitration in a multimaster
system. These pins require external pull-up resistors. Typical
pull-up values are between 4.7 kΩ and 10 kΩ.
The address of the I2C bus peripheral in the I2C bus system is
programmed by the user. This ID can be modified any time a
transfer is not in progress. The user can configure the interface
to respond to four slave addresses.
SERIAL CLOCK GENERATION
The I2C master in the system generates the serial clock for a
transfer. The master channel can be configured to operate in
fast mode (400 kHz) or standard mode (100 kHz). The bit rate
is defined in the I2CDIV MMR as follows:
f
SERIALCLOCK = fUCLK/((2 + DIVH) + (2 + DIVL))
where:
UCLK is the clock before the clock divider.
f
The transfer sequence of an I2C system consists of a master device
initiating a transfer by generating a start condition while the bus
is idle. The master transmits the slave device address and the
DIVH is the high period of the clock.
DIVL is the low period of the clock.
Thus, for 100 kHz operation, DIVH = DIVL = 0xCF, and for
400 kHz operation, DIVH = 0x28, and DIVL = 0x3C.
W
direction of the data transfer (R/ ) during the initial address
transfer. If the master does not lose arbitration and the slave
acknowledges, the data transfer initiates, which continues until
the master issues a stop condition, and the bus becomes idle.
The I2C peripheral can only be configured as a master or slave
at any given time. The same I2C channel cannot simultaneously
support master and slave modes. The I2C interface on the
ADuC7120/ADuC7121 includes the following features:
The I2CDIV register corresponds to DIVH and DIVL.
I2C BUS ADDRESSES
Slave Mode
In slave mode, the I2CxID0, I2CxID1, I2CxID2, and I2CxID3
registers contain the device IDs. The device compares the four
I2CxIDx registers to the address byte received from the bus
master. To be correctly addressed, the 7 MSBs of either ID
register must be identical to that of the 7 MSBs of the first
received address byte. The LSB of the ID registers (the transfer
direction bit) is ignored in the process of address recognition.
•
Support for repeated start conditions. In master mode, the
ADuC7120/ADuC7121 can be programmed to generate a
repeated start. In slave mode, the ADuC7120/ADuC7121
recognize repeated start conditions.
•
•
In master and slave modes, the devices recognize both
7-bit and 10-bit bus addresses.
The ADuC7120/ADuC7121 also support 10-bit addressing mode.
When Bit 1 of I2CxSCTL (ADR10EN bit) is set to 1, one 10-bit
address is supported in slave mode and is stored in the I2CxID0
and I2CxID1 registers. The 10-bit address is derived as follows:
In I2C master mode, the ADuC7120/ADuC7121 support
continuous reads from a single slave up to 512 bytes in a
single transfer sequence.
write
bit, and it is not part of the
•
I2CxID0, Bit 0 is the read/
I2C address.
•
•
Clock stretching can be enabled by other devices on the bus
without causing any issues with the ADuC7120/ADuC7121.
However, the ADuC7120/ADuC7121 cannot enable clock
stretching.
In slave mode, the devices can be programmed to return a
no acknowledge that allows the validation of the checksum
bytes at the end of I2C transfers.
Bus arbitration in master mode is supported.
Internal and external loopback modes are supported for
I2C hardware testing in loopback mode.
The transmit and receive circuits in both master and slave
mode contain 2-byte first in, first outs (FIFOs). Status bits
are available to the user to control these FIFOs.
•
•
•
I2CxID0, Bits[7:1] = Address Bits[6:0].
I2CxID1, Bits[2:0] = Address Bits[9:7].
I2CxID1, Bits[7:3] must be set to 11110b.
Master Mode
In master mode, the I2CxADR0 register is programmed with
the I2C address of the device. In 7-bit address mode,
I2CxADR0[7:1] are set to the device address. I2CxADR0[0] is
•
•
write
the read/
bit.
•
In 10-bit address mode, the 10-bit address is created as follows:
•
•
•
•
I2CxADR0, Bits[7:3] must be set to 11110b.
I2CxADR0, Bits[2:1] = Address Bits[9:8].
I2CxADR1, Bits[7:0] = Address Bits[7:0].
Configuring External Pins for I2C Functionality
The I2C pins of the ADuC7120/ADuC7121 are P0.0 and P0.1
for I2C0, and P1.0 and P1.1 for I2C1. P0.0 and P1.0 are the I2C
clock signals, and P0.1 and P1.1 are the I2C data signals. For
instance, to configure the I2C0 pins (SCL0, SDA0), Bit 0 and
write
I2CxADR0, Bit 0 is the read/
bit.
Rev. D | Page 66 of 102
Data Sheet
ADuC7120/ADuC7121
I2C REGISTERS
The I2C peripheral interfaces consists of a number of MMRs. These are described in the following section.
I2C Master Registers
I2C Master Control Register
This 16-bit MMR configures the I2C peripheral in master mode.
Name:
I2C0MCTL, I2C1MCTL
0xFFFF0880, 0xFFFF0900
0x0000, 0x0000
Address:
Default value:
Access:
Read/write
Table 95. I2CxMCTL MMR Bit Designations
Bit(s) Name
Description
[15:9]
Reserved. These bits are reserved; do not write to these bits.
I2C transmission complete interrupt enable bit.
Set this bit to enable an interrupt on detecting a stop condition on the I2C bus.
Clear this interrupt source.
8
7
6
5
4
I2CMCENI
I2CNACKENI I2C no acknowledge received interrupt enable bit.
Set this bit to enable interrupts when the I2C master receives a no acknowledge.
Clear this interrupt source.
I2CALENI
I2CMTENI
I2CMRENI
I2C arbitration lost interrupt enable bit.
Set this bit to enable interrupts when the I2C master has been unsuccessful in gaining control of the I2C bus.
Clear this interrupt source.
I2C transmit interrupt enable bit.
Set this bit to enable interrupts when the I2C master has transmitted a byte.
Clear this interrupt source.
I2C receive interrupt enable bit.
Set this bit to enable interrupts when the I2C master receives data.
Cleared by the user to disable interrupts when the I2C master is receiving data.
Reserved. A value of 0 should be written to this bit.
I2C internal loopback enable.
Set this bit to enable loopback test mode. In this mode, the SCL and SDA signals are connected internally to their
respective input signals.
Cleared by the user to disable loopback mode.
I2C master back off disable bit.
Set this bit to allow the device to compete for control of the bus even if another device is currently driving a start
condition.
3
2
I2CILEN
I2CBD
1
0
Clear this bit to back off until the I2C bus becomes free.
I2C master enable bit.
I2CMEN
Set by the user to enable I2C master mode.
Clear this bit to disable I2C master mode.
Rev. D | Page 67 of 102
ADuC7120/ADuC7121
Data Sheet
I2C Master Status Register
This 16-bit MMR is I2C status register in master mode.
Name:
I2C0MSTA, I2C1MSTA
0xFFFF0884, 0xFFFF0904
0x0000, 0x0000
Address:
Default value:
Access:
Read only
Table 96 I2CxMSTA MMR Bit Designations
Bit(s)
[15:11]
10
Name
Description
Reserved. These bits are reserved.
I2C bus busy status bit.
I2CBBUSY
This bit is set to 1 when a start condition is detected on the I2C bus.
This bit is cleared when a stop condition is detected on the I2C bus.
Master receiver (Rx) FIFO overflow.
This bit is set to 1 when a byte is written to the Rx FIFO when it is already full.
This bit is cleared in all other conditions.
I2C transmission complete status bit.
9
8
I2CMRxFO
I2CMTC
This bit is set to 1 when a transmission is complete between the master and the slave with which it was
communicating. If the I2CMCENI bit in I2CxMCTL is set, an interrupt is generated when the I2CMTC bit is set.
Clear this interrupt source.
7
I2CMNA
I2C master no acknowledge data bit.
This bit is set to 1 when a no acknowledge condition is received by the master in response to a data write transfer. If
the I2CNACKENI bit in I2CxMCTL is set, an interrupt is generated when the I2CMNA bit is set.
This bit is cleared in all other conditions.
6
5
I2CMBUSY I2C master busy status bit.
Set to 1 when the master is busy processing a transaction.
Cleared if the master is ready or if another master device has control of the bus.
I2C arbitration lost status bit.
I2CAL
This bit is set to 1 when the I2C master is unsuccessful in gaining control of the I2C bus. If the I2CALENI bit in
I2CxMCTL is set, an interrupt is generated when the I2CAL bit is set.
This bit is cleared in all other conditions.
I2C master no acknowledge address bit.
4
I2CMNA
This bit is set to 1 when a no acknowledge condition is received by the master in response to an address. If the
I2CNACKENI bit in I2CxMCTL is set, an interrupt is generated when the I2CMNA bit is set.
This bit is cleared in all other conditions.
3
2
I2CMRXQ
I2CMTXQ
I2C master receive request bit.
This bit is set to 1 when data enters the Rx FIFO. If the I2CMRENI in I2CxMCTL is set, an interrupt is generated.
This bit is cleared in all other conditions.
I2C master transmit request bit.
This bit goes high if the transmitter (Tx) FIFO is empty or only contains one byte and the master has transmitted an
address plus write. If the I2CMTENI bit in I2CxMCTL is set, an interrupt is generated when the I2CMTXQ bit is set.
This bit is cleared in all other conditions.
[1:0]
I2CMTFSTA I2C master Tx FIFO status bits.
00 = I2C master Tx FIFO empty.
01 = one byte in master Tx FIFO.
10 = one byte in master Tx FIFO.
11 = I2C master Tx FIFO full.
Rev. D | Page 68 of 102
Data Sheet
ADuC7120/ADuC7121
I2C Master Receive Registers
I2C Address 0 Registers
This 8-bit MMR is the I2C master receive register.
write
This 8-bit MMR holds the 7-bit slave address plus the read/
bit when the master begins communicating with a slave.
Name:
I2C0MRX, I2C1MRX
Name:
I2C0ADR0, I2C1ADR0
Address:
0xFFFF0888, 0xFFFF0908
Address:
0xFFFF0898, 0xFFFF0918
Default value: 0x00
Default value: 0x00
Access:
Read only
Access:
Read and write
I2C Master Transmit Registers
This 8-bit MMR is the I2C master transmit register.
Table 98. I2CxADR0 MMR in 7-Bit Address Mode
Bit(s) Name
Description
Name:
I2C0MTX, I2C1MTX
[7:1]
I2CADR These bits contain the 7-bit address of the
required slave device.
Address:
0xFFFF088C, 0xFFFF090C
0
W
write
Bit 0 is the read/
R/
bit.
When this bit = 1, a read sequence is requested.
When this bit = 0, a write sequence is requested.
Default value: 0x00
Access:
Write only
Table 99. I2CxADR0 MMR in 10-Bit Address Mode
I2C Master Read Count Registers
Bit(s) Name
Description
[7:3]
These bits must be set to [11110b] in 10-bit
address mode.
This 16-bit MMR holds the required number of bytes when the
master begins a read sequence from a slave device.
[2:1]
0
I2CMADR These bits contain ADDR, Bits[9:8] in 10-bit
addressing mode.
Name:
I2C0MCNT0, I2C1MCNT0
0xFFFF0890, 0xFFFF0910
W
write
bit.
R/
Read/
Address:
When this bit = 1, a read sequence is
requested.
When this bit = 0, a write sequence is
requested.
Default value: 0x0000
Access:
Read and write
I2C Address 1 Register
Table 97. I2CxMCNT0 MMR Bit Descriptions
This 8-bit MMR is used in 10-bit addressing mode only. This
register contains the least significant byte of the address.
Bit(s) Name
Description
[15:9]
Reserved.
8
I2CRECNT Set this bit if greater than 256 bytes are
required from the slave.
Name:
I2C0ADR1, I2C1ADR1
Address:
0xFFFF089C, 0xFFFF091C
Clear this bit when reading 256 bytes or less.
[7:0]
I2CRCNT
These 8 bits hold the number of bytes
required during a slave read sequence,
minus 1. If only a single byte is required, set
these bits to 0.
Default value: 0x00
Access:
Read and write
I2C Master Current Read Count Registers
Table 100. I2CxADR1 MMR in 10-Bit Address Mode
Bit(s) Name
Description
This 8-bit MMR holds the number of bytes received during a
read sequence with a slave device.
[7:0]
I2CLADR These bits contain ADDR, Bits[7:0] in 10-bit
addressing mode.
Name:
I2C0MCNT1, I2C1MCNT1
0xFFFF0894, 0xFFFF0914
Address:
Default value: 0x00
Access: Read only
Rev. D | Page 69 of 102
ADuC7120/ADuC7121
Data Sheet
I2C Slave Registers
I2C Slave Control Register
This 16-bit MMR configures the I2C peripheral in slave mode.
I2C Master Clock Control Register
This MMR controls the frequency of the I2C clock generated by
the master on to the SCLx pin.
Name:
I2C0DIV, I2C1DIV
Name:
I2C0SCTL, I2C1SCTL
Address:
0xFFFF08A4, 0xFFFF0924
Address:
0xFFFF08A8, 0xFFFF0928
Default value: 0x1F1F
Default value: 0x0000
Access: Read and write
Access:
Read and write
Table 101. I2CxDIV MMR
Bit(s) Name Description
[15:8] DIVH
These bits control the duration of the high
period of SCLx.
[7:0] DIVL
These bits control the duration of the low
period of SCLx.
Table 102. I2CxSCTL MMR Bit Designations
Bit(s)
[15:11]
10
Name
Description
Reserved bits.
I2CSTXENI
Slave transmit interrupt enable bit.
Set this bit to enable an interrupt after a slave transmits a byte.
Clear this interrupt source.
9
8
7
I2CSRXENI
I2CSSENI
Slave receive interrupt enable bit.
Set this bit to enable an interrupt after the slave receives data.
Clear this interrupt source.
I2C stop condition detected interrupt enable bit.
Set this bit to enable an interrupt on detecting a stop condition on the I2C bus.
Clear this interrupt source.
I2CNACKEN I2C no acknowledge enable bit.
Set this bit to no acknowledge the next byte in the transmission sequence.
Clear this bit to let the hardware control the acknowledge/no acknowledge sequence.
Reserved. A value of 0 should be written to this bit.
I2C early transmit interrupt enable bit.
Setting this bit enables a transmit request interrupt just after the positive edge of SCLx during the read bit transmission.
Clear this bit to enable a transmit request interrupt just after the negative edge of SCLx during the read bit transmission.
I2C general call status and ID clear bit.
Writing a 1 to this bit clears the general call status and ID bits in the I2CxSSTA register.
Clear this bit at all other times.
I2C hardware general call enable. Hardware general call enable. When this bit and Bit 2 are set, and having received
a general call (Address 0x00) and a data byte, the device checks the contents of the I2CxALT register against the
receive register. If the contents match, the device has received a hardware general call. This is used if a device needs
urgent attention from a master device without knowing which master it needs to turn to. This is a to whom it may
concern call. The ADuC7120/ADuC7121 watch for these addresses. The device that requires attention embeds its
own address into the message. All masters listen, and the one that can handle the device contacts its slave and acts
appropriately. The LSB of the I2CxALT register must always be written to 1, as per the I2C January 2000 Bus Specification.
6
5
I2CSETEN
I2CGCCLR
I2CHGCEN
4
3
Set this bit and I2CGCEN to enable hardware general call recognition in slave mode.
Clear to disable recognition of hardware general call commands.
Rev. D | Page 70 of 102
Data Sheet
ADuC7120/ADuC7121
Bit(s)
Name
Description
2
I2CGCEN
I2C general call enable. Set this bit to enable the slave device to acknowledge an I2C general call, Address 0x00
(write). The device then recognizes a data bit. If it receives a 0x06 (reset and write programmable part of the slave
address by hardware) as the data byte, the I2C interface resets as per the I2C January 2000 Bus Specification. This
command can reset an entire I2C system. If it receives a 0x04 (write programmable part of the slave address by
hardware) as the data byte, the general call interrupt status bit sets on any general call. The user must take
corrective action by reprogramming the device address.
Set this bit to allow the slave acknowledge I2C general call commands.
Clear to disable recognition of general call commands.
Set this bit to 1 to enable 10-bit addressing only.
I2C slave enable bit.
1
0
ADR10EN
I2CSEN
Set by the user to enable I2C slave mode.
Clear to disable I2C slave mode.
I2C Slave Status Registers
These 16-bit MMRs are the I2C status registers in slave mode.
Name:
I2C0SSTA, I2C1SSTA
0xFFFF08AC, 0xFFFF092C
0x0000, 0x0000
Address:
Default value:
Access:
Read only
Table 103. I2CxSSTA MMR Bit Designations
Bit(s)
Name
Description
15
Reserved bit.
14
I2CSTA
This bit is set to 1 if:
A start condition followed by a matching address is detected.
A start byte (0x01) is received.
General calls are enabled and a general call code of (0x00) is received.
This bit is cleared on receiving a stop condition.
This bit is set to 1 if a repeated start condition is detected.
This bit is cleared on receiving a stop condition. A read of the I2CxSSTA register also clears this bit.
I2C address matching register. These bits indicate which I2CxIDx register matches the received address.
00 = received address matches I2CxID0.
13
I2CREPS
[12:11] I2CID[1:0]
01 = received address matches I2CxID1.
10 = received address matches I2CxID2.
11 = received address matches I2CxID3.
10
I2CSS
I2C stop condition after start detected bit.
This bit is set to 1 when a stop condition is detected after a previous start and matching address. When the
I2CSSENI bit in the I2CxSCTL register is set, an interrupt is generated.
This bit is cleared by reading this register.
[9:8]
I2CGCID[1:0] I2C general call ID bits.
00 = no general call received.
01 = general call reset and program address.
10 = general program address.
11 = general call matching alternative ID.
Clear these bits by writing a 1 to the I2CGCCLR bit in the I2CxSCTL register. These bits are not cleared by a general
call reset command.
7
I2CGC
I2C general call status bit.
This bit is set to 1 if the slave receives a general call command of any type. If the command received was a reset
command, all registers return to their default state. If the command received was a hardware general call, the Rx
FIFO holds the second byte of the command and this can be compared with the I2CxALT register.
Clear this bit by writing a 1 to the I2CGCCLR bit in I2CxSCTL.
Rev. D | Page 71 of 102
ADuC7120/ADuC7121
Data Sheet
Bit(s)
Name
Description
I2C slave busy status bit.
6
I2CSBUSY
Set to 1 when the slave receives a start condition.
Cleared by hardware under the following conditions:
The received address does not match any of the I2CxIDx registers.
The slave device receives a stop condition.
A repeated start address does not match any of the I2CxIDx registers.
I2C slave no acknowledge data bit.
5
I2CSNA
This bit sets to 1 when the slave responds to a bus address with a no acknowledge. This bit is asserted under the
following conditions:
If no acknowledge was returned because there was no data in the Tx FIFO.
If the I2CNACKEN bit was set in the I2CxSCTL register.
This bit is cleared in all other conditions.
4
3
I2CSRxFO
I2CSRXQ
Slave Rx FIFO overflow.
This bit is set to 1 when a byte is written to the Rx FIFO when it is already full.
This bit is cleared in all other conditions.
I2C slave receive request bit.
This bit is set to 1 when the Rx FIFO of the slave is not empty. This bit causes an interrupt to occur if the I2CSRXENI
bit in I2CxSCTL is set.
The Rx FIFO must be read or flushed to clear this bit.
I2C slave transmit request bit.
2
I2CSTXQ
This bit is set to 1 when the slave receives a matching address followed by a read.
If the I2CSETEN bit in I2CxSCTL is = 0, this bit goes high just after the negative edge of SCLx during the read bit
transmission.
If the I2CSETEN bit in I2CxSCTL is = 1, this bit goes high just after the positive edge of SCLx during the read bit
transmission. This bit causes an interrupt to occur if the I2CSTXENI bit in I2CxSCTL is set.
This bit is cleared in all other conditions.
I2C slave FIFO underflow status bit.
This bit is high if the Tx FIFO is empty when a master requests data from the slave. This bit asserts at the rising
edge of SCLx during the read bit.
This bit clears in all other conditions.
I2C slave early transmit FIFO status bit.
1
0
I2CSTFE
I2CETSTA
If the I2CSETEN bit in I2CxSCTL is = 0, this bit goes high if the slave Tx FIFO is empty.
If the I2CSETEN bit in I2CxSCTL is = 1, this bit goes high just after the positive edge of SCLx during the write bit
transmission. This bit asserts once only for a transfer.
This bit is cleared after being read.
Rev. D | Page 72 of 102
Data Sheet
ADuC7120/ADuC7121
I2C Slave Receive Registers
This 8-bit MMR is the I2C slave receive register.
Name:
I2C0ID2
Address:
0xFFFF08C4
Name:
I2C0SRX, I2C1SRX
Default value: 0x00
Address:
0xFFFF08B0, 0xFFFF0930
Access:
Read and write
Default value: 0x00
Name:
I2C0ID3
Access:
Read only
I2C Slave Transmit Registers
Address:
0xFFFF08C8
This 8-bit MMR is the I2C slave transmit register.
Default value: 0x00
Name:
I2C0STX, I2C1STX
Access:
Read and write
Address:
0xFFFF08B4, 0xFFFF0934
Name:
I2C1ID0
Default value: 0x00
Address:
0xFFFF093C
Access:
Write only
Default value: 0x00
I2C Hardware General Call Recognition Registers
Access:
Read and write
This 8-bit MMR is used with hardware general calls when
I2CxSCTL Bit 3 is set to 1. This register is used in cases where a
master is unable to generate an address for a slave, and instead,
the slave must generate the address for the master.
Name:
I2C1ID1
Address:
0xFFFF0940
Name:
I2C0ALT, I2C1ALT
Default value: 0x00
Address:
0xFFFF08B8, 0xFFFF0938
Access:
Read and write
Default value: 0x00
Access:
Read and write
Name:
I2C1ID2
I2C Slave Device ID Registers
Address:
0xFFFF0944
I2C0IDx Registers
Default value: 0x00
These eight I2C0IDx 8-bit MMRs are programmed with I2C bus
IDs of the slave. See the I2C Bus Addresses section for further
details.
Access:
Read and write
Name:
I2C1ID3
Name:
I2C0ID0
Address:
0xFFFF0948
Address:
0xFFFF08BC
Default value: 0x00
Access: Read and write
Default value: 0x00
Access:
Read and write
Name:
I2C0ID1
Address:
0xFFFF08C0
Default value: 0x00
Access: Read and write
Rev. D | Page 73 of 102
ADuC7120/ADuC7121
Data Sheet
I2C COMMON REGISTERS
Table 104. I2CxFSTA MMR Bit Designations
I2C FIFO Status Registers
Bit(s)
[15:10]
9
Name
Description
Reserved bits.
These 16-bit MMRs contain the status of the Rx/Tx FIFOs in
both master and slave modes.
I2CFMTX
I2CFSTX
Set this bit to 1 to flush the master Tx FIFO.
Set this bit to 1 to flush the slave Tx FIFO.
8
[7:6]
I2CMRXSTA I2C master receive FIFO status bits.
Name:
I2C0FSTA
00 = FIFO empty.
01 = byte written to FIFO.
10 = one byte in FIFO.
Address:
0xFFFF08CC
Default value: 0x0000
11 = FIFO full.
I2CMTXSTA I2C master transmit FIFO status bits.
Access:
Read and write
[5:4]
[3:2]
[1:0]
00 = FIFO empty.
01 = byte written to FIFO.
10 = one byte in FIFO.
Name:
I2C1FSTA
11 = FIFO full.
Address:
0xFFFF094C
I2CSRXSTA
I2CSTXSTA
I2C slave receive FIFO status bits.
00 = FIFO empty.
01 = byte written to FIFO.
10 = one byte in FIFO.
11 = FIFO full.
Default value: 0x0000
Access: Read and write
I2C slave transmit FIFO status bits.
00 = FIFO empty.
01 = byte written to FIFO.
10 = one byte in FIFO.
11 = FIFO full.
Rev. D | Page 74 of 102
Data Sheet
ADuC7120/ADuC7121
SERIAL PERIPHERAL INTERFACE
The ADuC7120/ADuC7121 integrate a complete hardware
serial peripheral interface (SPI) on-chip. SPI is an industry
standard, synchronous serial interface that allows eight bits of
data to synchronously transmitt and simultaneously receive,
that is, full duplex up to a maximum bit rate of 20 Mbps.
In both master and slave modes, data is transmitted on one edge
of the SPICLK signal and sampled on the other. Therefore, it is
important that the polarity and phase are configured the same
for the master and slave devices.
SPI CHIP SELECT INPUT PIN
The SPI port can be configured for master or slave operation
and typically consists of four pins: P0.3/MISO/PLAO[12]/SYNC,
P0.4/MOSI/PLAI[11]/TRIP, P0.2/SPICLK/ADCBUSY/PLAO[13],
CS
In SPI slave mode, a transfer is initiated by the assertion of
CS CS
on the P0.5/ /PLAI[10]/ADCCONVST pin.
input signal. The SPI port then transmits and receives 8-bit data
CS
is an active low
CS
and P0.5/ /PLAI[10]/ADCCONVST
.
until the transfer is concluded by deassertion of . In slave mode,
CS
SPI MASTER IN, SLAVE OUT (MISO) PIN
is always an input.
MISO on the P0.3/MISO/PLAO[12]/SYNC pin is configured as
an input line in master mode and an output line in slave mode.
Connect the MISO line on the master (data in) to the MISO line
in the slave device (data out). The data is transferred as byte
wide (8-bit) serial data, MSB first.
CS
In SPI master mode,
is an active low output signal. It asserts
itself automatically at the beginning of a transfer and deasserts
itself upon completion.
CONFIGURING EXTERNAL PINS FOR SPI
FUNCTIONALITY
SPI MASTER OUT, SLAVE IN (MOSI) PIN
The SPI pins of the ADuC7120/ADuC7121 are P0.2 to P0.5.
MOSI on the P0.4/MOSI/PLAI[11]/TRIP pin is configured as
an output line in master mode and an input line in slave mode.
Connect the MOSI line on the master (data out) to the MOSI
line in the slave device (data in). The data is transferred as byte
wide (8-bit) serial data, MSB first.
CS
•
P0.5/ /PLAI[10]/ADCCONVST is the slave chip select pin. In
slave mode, this pin is an input and must be driven low by
the master. In master mode, this pin is an output and goes
low at the beginning of a transfer and high at the end of a
transfer.
P0.2/SPICLK/ADCBUSY/PLAO[13] is the SPICLK pin.
P0.3/MISO/PLAO[12]/SYNC is the master in, slave out pin.
P0.4/MOSI/PLAI[11]/TRIP is the master out, slave in pin.
SERIAL CLOCK INPUT/OUTPUT (SPICLK) PIN
•
•
•
The master serial clock (SPICLK) synchronizes the data
transmitted and received through the MOSI SPICLK period.
Therefore, a byte is transmitted/received after eight SPICLK
periods. The P0.2/SPICLK/ADCBUSY/PLAO[13] pin is configured
as an output in master mode and as an input in slave mode.
To configure P0.2 to P0.5 for SPI mode, see the General-
Purpose Input/Output section.
In master mode, the polarity and phase of the clock are controlled
by the SPICON register, and the bit rate is defined in the SPIDIV
register as follows:
SPI REGISTERS
The following MMR registers control the SPI interface: SPISTA,
SPIRX, SPITX, SPIDIV, and SPICON.
fSERIAL CLOCK = (fUCLK/(2 × (1 + SPIDIV))
SPI Status Register
The maximum speed of the SPI clock is independent on the
clock divider bits.
This 32-bit MMR contains the status of the SPI interface in both
master and slave modes.
In slave mode, the SPICON register must be configured with
the phase and polarity of the expected input clock. The slave
accepts data from an external master up to 10 Mbps.
Name:
SPISTA
Address:
0xFFFF0A00
Default value: 0x0000
Access: Read only
Table 105. SPISTA MMR Bit Designations
Bit(s)
[15:12]
11
Name
Description
Reserved bits.
SPIREX
SPI Rx FIFO excess bytes present. This bit is set when there are more bytes in the Rx FIFO than indicated in the
SPIMDE bits in SPICON.
This bit is cleared when the number of bytes in the FIFO is equal or less than the number in SPIMDE.
Rev. D | Page 75 of 102
ADuC7120/ADuC7121
Data Sheet
Bit(s)
Name
Description
[10:8]
SPIRXFSTA[2:0] SPI Rx FIFO status bits.
000 = Rx FIFO is empty.
001 = one valid byte in the FIFO.
010 = two valid bytes in the FIFO.
011 = three valid bytes in the FIFO.
100 = four valid bytes in the FIFO.
SPI Rx FIFO overflow status bit.
7
SPIFOF
Set when the Rx FIFO was already full when new data was loaded to the FIFO. This bit generates an interrupt
except when SPIRFLH is set in SPICON.
Cleared when the SPISTA register is read.
SPI Rx IRQ status bit.
Set when a receive interrupt occurs. This bit is set when SPITMDE in SPICON is cleared and the required number
of bytes have been received.
Cleared when the SPISTA register is read.
SPI Tx IRQ status bit.
Set when a transmit interrupt occurs. This bit is set when SPITMDE in SPICON is set and the required number of
bytes have been transmitted.
6
SPIRXIRQ
SPITXIRQ
SPITXUF
5
Cleared when the SPISTA register is read.
SPI Tx FIFO underflow.
4
This bit is set when a transmit is initiated without any valid data in the Tx FIFO. This bit generates an interrupt
except when SPITFLH is set in SPICON.
Cleared when the SPISTA register is read.
[3:1]
SPITXFSTA[2:0] SPI Tx FIFO status bits.
000 = Tx FIFO is empty.
001 = one valid byte in the FIFO.
010 = two valid bytes in the FIFO.
011 = three valid bytes in the FIFO.
100 = four valid bytes in the FIFO.
SPI interrupt status bit.
0
SPIISTA
Set to 1 when an SPI based interrupt occurs.
Cleared after reading SPISTA.
SPIRX Register
This 8-bit MMR is the SPI receive register.
SPIDIV Register
This 8-bit MMR is the SPI baud rate selection register.
Name:
SPIRX
Name:
SPIDIV
Address:
0xFFFF0A04
Address:
0xFFFF0A0C
Default value: 0x00
Default value: 0x00
Access:
Read only
Access:
Read and write
SPITX Register
SPI Control Register
This 8-bit MMR is the SPI transmit register.
This 16-bit MMR configures the SPI peripheral in both master
and slave modes.
Name:
SPITX
Name:
SPICON
Address:
0xFFFF0A08
Address:
0xFFFF0A10
Default value: 0x00
Access: Write only
Default value: 0x0000
Access: Read and write
Rev. D | Page 76 of 102
Data Sheet
ADuC7120/ADuC7121
Table 106. SPICON MMR Bit Designations
Bit(s)
Name
Description
[15:14] SPIMDE
SPI IRQ mode bits. These bits configure when the Tx/Rx interrupts occur in a transfer.
00 = Tx interrupt occurs when one byte has been transferred. Rx interrupt occurs when one or more bytes have been
received into the FIFO.
01 = Tx interrupt occurs when two bytes has been transferred. Rx interrupt occurs when two or more bytes have been
received into the FIFO.
10 = Tx interrupt occurs when three bytes has been transferred. Rx interrupt occurs when three or more bytes have
been received into the FIFO.
11 = Tx interrupt occurs when four bytes has been transferred. Rx interrupt occurs when the Rx FIFO is full, or four
bytes present.
13
12
11
SPITFLH
SPIRFLH
SPI Tx FIFO flush enable bit.
Set this bit to flush the Tx FIFO. This bit does not clear itself and must be toggled if a single flush is required. If this bit is
left high, either the last transmitted value or 0x00 is transmitted depending on the SPIZEN bit. Any writes to the Tx
FIFO are ignored while this bit is set.
Clear this bit to disable Tx FIFO flushing.
SPI Rx FIFO flush enable bit.
Set this bit to flush the Rx FIFO. This bit does not clear itself and must be toggled if a single flush is required. If this bit
is set, all incoming data is ignored, and no interrupts are generated. If this bit is set and SPITMDE = 0, a read of the Rx
FIFO initiates a transfer.
Clear this bit to disable Rx FIFO flushing.
SPICONT Continuous transfer enable.
Set by the user to enable continuous transfer. In master mode, the transfer continues until no valid data is available in
CS
the Tx register. The P0.5/ /PLAI[10]/ADCCONVST pin is asserted and remains asserted for the duration of each 8-bit serial
transfer until Tx is empty.
Cleared by the user to disable continuous transfer. Each transfer consists of a single 8-bit serial transfer. If valid data
exists in the SPITX register, a new transfer is initiated after a stall period of one serial clock cycle.
Loopback enable bit.
Set by the user to connect MISO to MOSI and test software.
Cleared by the user to be in normal mode.
10
9
8
7
6
5
4
3
2
1
0
SPILP
SPIOEN
SPIROW
SPIZEN
Slave MISO output enable bit.
Set this bit for normal operation of MISO.
Clear this bit to disable the output driver on the MISO pin. The MISO pin is open drain when this bit is clear.
SPIRX overflow overwrite enable.
Set by the user, the valid data in the Rx register is overwritten by the new serial byte that is received.
Cleared by the user, the new serial byte that is received is discarded.
SPI transmits zeros when Tx FIFO is empty.
Set this bit to transmit 0x00 when there is no valid data in the Tx FIFO.
Clear this bit to transmit the last transmitted value when there is no valid data in the Tx FIFO.
SPITMDE SPI transfer and interrupt mode.
Set by the user to initiate a transfer with a write to the SPITX register. Interrupt occurs only when Tx is empty.
Cleared by the user to initiate a transfer with a read of the SPIRX register. Interrupt occurs only when Rx is full.
LSB first transfer enable bit.
Set by the user, the LSB is transmitted first.
SPILF
Cleared by the user, the MSB is transmitted first.
SPIWOM SPI wired or mode enable bit.
Set to 1 to enable open-drain data output enable. External pull-ups are required on data output pins.
Clear for normal output levels.
Serial clock polarity mode bit.
SPICPO
SPICPH
SPIMEN
SPIEN
Set by the user, the serial clock idles high.
Cleared by the user, the serial clock idles low.
Serial clock phase mode bit.
Set by the user, the serial clock pulses at the beginning of each serial bit transfer.
Cleared by the user, the serial clock pulses at the end of each serial bit transfer.
Master mode enable bit.
Set by the user to enable master mode.
Cleared by the user to enable slave mode.
SPI enable bit.
Set by the user to enable the SPI.
Cleared by the user to disable the SPI.
Rev. D | Page 77 of 102
ADuC7120/ADuC7121
Data Sheet
PROGRAMMABLE LOGIC ARRAY (PLA)
The ADuC7120/ADuC7121 integrate a fully programmable logic
array (PLA) that consists of two independent but interconnected
PLA blocks. Each block consists of eight PLA elements, giving
each device 16 PLA elements.
In total, 32 GPIO pins are available on each ADuC7120/
ADuC7121 for the PLA. These include 16 input pins and 16 output
pins that must be configured in the GPxCON register as PLA pins
before using the PLA. The comparator output is also included as
one of the 16 input pins, and that the JTAG TDI and TDO pins
are included as PLA outputs. If using JTAG programming or
debugging, do not use the JTAG TDI and TDO pins as PLA
outputs.
Each PLA element contains a dual input lookup table that can
be configured to generate any logic output function based on
two inputs and a flip-flop, which is represented in Figure 38.
The PLA is configured via a set of user MMRs. The output(s)
of the PLA can be routed to the internal interrupt system, to
the ADCCONVST signal of the ADC, to an MMR, or to any of the
0
4
A
2
LOOKUP
TABLE
16 PLA output pins.
B
3
The two blocks can be interconnected as follows:
1
Output of Element 15 (Block 1) can be fed to Input 0 of
Mux 0 of Element 0 (Block 0).
Output of Element 7 (Block 0) can be fed to the Input 0 of
Mux 0 of Element 8 (Block 1).
Figure 38. PLA Element
Table 107. Element Input/Output
PLA Block 0
PLA Block 1
Element
Input
P2.7
P2.2
P0.6
P0.7
P0.1
P0.0
P1.1
P1.0
Output
P3.0
P3.1
P3.2
P3.3
P1.7
P1.6
P2.5
P2.4
Element
Input
P1.4
P1.5
P0.5
P0.4
P2.1
P2.0
P2.3
P2.6
Output
P3.4
P3.5
P3.6
P3.7
P0.3
P0.2
P1.3
P1.2
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Rev. D | Page 78 of 102
Data Sheet
ADuC7120/ADuC7121
Table 109. PLAELMx MMR Bit Descriptions
PLA MMRS INTERFACE
The PLA peripheral interface consists of the 21 MMRs
described in the following sections.
Bit(s)
[31:11]
[10:9]
[8:7]
6
Setting Description
Reserved.
Mux 0 control (see Table 110).
Mux 1 control (see Table 110).
Mux 2 control.
PLAELMx Registers
PLAELMx are Element 0 to Element 15 control registers. They
configure the input and output mux of each element, select the
function in the lookup table, and bypass and use the flip-flop.
See Table 109 and Table 112.
Set by the user to select the output of Mux 0.
Cleared by the user to select the bit value from
PLADIN.
5
Mux 3 control.
Set by the user to select the input pin of the
particular element.
Cleared by the user to select the output of
Mux 1.
Table 108. PLAELMx MMR Addresses (Default Value =
0x0000, Access Is Read/Write)
Name
Address
PLAELM0
PLAELM1
PLAELM2
PLAELM3
PLAELM4
PLAELM5
PLAELM6
PLAELM7
PLAELM8
PLAELM9
PLAELM10
PLAELM11
PLAELM12
PLAELM13
PLAELM14
PLAELM15
0xFFFF0B00
0xFFFF0B04
0xFFFF0B08
0xFFFF0B0C
0xFFFF0B10
0xFFFF0B14
0xFFFF0B18
0xFFFF0B1C
0xFFFF0B20
0xFFFF0B24
0xFFFF0B28
0xFFFF0B2C
0xFFFF0B30
0xFFFF0B34
0xFFFF0B38
0xFFFF0B3C
[4:1]
Look up table control.
0000 0.
0001 NOR.
0010 B AND NOT A.
0011 NOT A.
0100 A AND NOT B.
0101 NOT B.
0110 EXOR.
0111 NAND.
1000 AND.
1001 EXNOR.
1010 B.
1011 NOT A OR B.
1100 A.
1101 A OR NOT B.
1110 OR.
1111 1.
0
Mux 4 control.
Set by the user to bypass the flip-flop.
Cleared by the user to select the flip-flop
(cleared by default).
Table 110. Feedback Configuration for PLAELMx MMRs
Bit(s)
Setting
PLAELM0
00 Element 15
01 Element 2
10 Element 4
11 Element 6
00 Element 1
01 Element 3
10 Element 5
11 Element 7
PLAELM1 to PLAELM7
PLAELM8
Element 7
Element 10
Element 12
Element 14
Element 9
Element 11
Element 13
Element 15
PLAELM9 to PLAELM15
Element 8
Element 10
Element 12
Element 14
Element 9
Element 11
Element 13
Element 15
[10:9]
Element 0
Element 2
Element 4
Element 6
[8:7]
Element 1
Element 3
Element 5
Element 7
Rev. D | Page 79 of 102
ADuC7120/ADuC7121
Data Sheet
PLACLK Register
Bit(s)
Setting Description
PLA IRQ1 source.
[11:8]
PLACLK is the clock selection for the flip-flops of Block 0 and
Block 1. The maximum frequency when using the GPIO pins as
the clock input for the PLA blocks is 41.78 MHz.
0000 PLA Element 0.
0001 PLA Element 1.
1111 PLA Element 15.
Reserved.
Name:
PLACLK
[7:5]
4
PLA IRQ0 enable bit.
Set by the user to enable IRQ0 output from
the PLA.
Cleared by the user to disable IRQ0 output
from the PLA.
Address:
0xFFFF0B40
Default value: 0x00
Access:
Read and write
[3:0]
PLA IRQ0 source.
Table 111. PLACLK MMR Bit Descriptions
0000 PLA Element 0.
Bit(s) Setting Description
0001 PLA Element 1.
1111 PLA Element 15.
7
Reserved.
[6:4]
Block 1 clock source selection.
PLAADC Register
000
CS
GPIO clock on P0.5 of the P0.5/ /PLAI[10]/
ADCCONVST pin.
PLAADC is the PLA source for the ADC start conversion signal.
001 GPIO clock on P0.0 of the P0.0/SCL0/PLAI[5] pin.
010 GPIO clock on the P0.7 of the P0.7/TRST/PLAI[3]
pin.
Name:
PLAADC
Address:
0xFFFF0B48
011 HCLK (core clock).
100 OCLK (32.768 kHz external crystal).
101 Timer1 overflow.
Default value: 0x00000000
Access: Read and write
Other
Reserved.
3
Reserved.
Table 113. PLAADC MMR Bit Descriptions
[2:0]
Block 0 clock source selection.
Bit(s)
[31:5]
4
Setting Description
000
CS
/
GPIO clock on P0.5. on P0.5 of the P0.5/
PLAI[10]/ADCCONVST pin.
Reserved.
ADC start conversion enable bit.
001 GPIO clock on P0.0 of the P0.0/SCL0/PLAI[5] pin.
010 GPIO clock on P0.7 of the P0.7/TRST/PLAI[3] pin.
011 HCLK (core clock).
100 OCLK (32.768 kHz external crystal).
101 Timer1 overflow.
Set by the user to enable an ADC start
conversion from the PLA.
Cleared by the user to disable an ADC start
conversion from the PLA.
[3:0]
ADC start conversion source.
0000 PLA Element 0.
Other
Reserved.
0001 PLA Element 1.
1111 PLA Element 15.
PLAIRQ Register
PLAIRQ enables IRQ0 and/or IRQ1 and selects the source of
the normal interrupt request IRQ (IRQ).
PLADIN Register
PLADIN is a data input MMR for PLA.
Name:
PLAIRQ
Name:
PLADIN
Address:
0xFFFF0B44
Address:
0xFFFF0B4C
Default value: 0x0000
Default value: 0x00000000
Access: Read and write
Access:
Read and write
Table 112. PLAIRQ MMR Bit Descriptions
Bit(s)
[15:13]
12
Setting Description
Table 114. PLADIN MMR Bit Descriptions
Reserved.
Bit(s)
[31:16]
[15:0]
Description
PLA IRQ1 enable bit.
Set by the user to enable IRQ1 output from
the PLA.
Reserved.
Input bit from Element 15 to Element 0.
Cleared by the user to disable IRQ1 output
from the PLA.
Rev. D | Page 80 of 102
Data Sheet
ADuC7120/ADuC7121
PLADOUT Register
PLALCK Register
PLADOUT is a data output MMR for PLA. This register is
always updated.
PLALCK is a PLA lock option. Bit 0 is written only once. When
set, it does not allow modifying any of the PLA MMRs, except
PLADIN. A PLA tool is provided in the development system to
easily configure the PLA.
Name:
PLADOUT
Address:
0xFFFF0B50
Name:
PLALCK
Default value: 0x00000000
Access: Read only
Address:
0xFFFF0B54
Default value: 0x00
Access: Write only
Table 115. PLADOUT MMR Bit Descriptions
Bit(s)
[31:16]
[15:0]
Description
Reserved.
Output bit from Element 15 to Element 0.
Rev. D | Page 81 of 102
ADuC7120/ADuC7121
Data Sheet
INTERRUPT SYSTEM
There are 27 interrupt on the ADuC7120/ADuC7121 that are
controlled by the interrupt controller. All interrupts are generated
from the on-chip peripherals, except for the software interrupt
(SWI), which is programmable by the user. The ARM7TDMI
CPU core recognizes interrupts as one of only two types: a
normal interrupt request (IRQ) and a fast interrupt request
(FIQ). All the interrupts can be masked separately.
IRQCONN register to enable interrupt nesting. When the
full vectored interrupt controller is enabled, extra MMRs are
used.
Upon entering the ISR, immediately save the IRQSTA and the
FIQSTA registers to service all valid interrupt sources are
serviced.
NORMAL INTERRUPT REQUEST (IRQ)
The control and configuration of the interrupt system is managed
through a number of interrupt related registers. The bits in each
IRQ and FIQ register represent the same interrupt source as
described in Table 116.
The normal interrupt request (IRQ) is the exception signal
to enter the IRQ mode of the processor. It services general-
purpose interrupt handling of internal and external events.
All 32 bits are logically OR’ed to create a single IRQ signal to the
ARM7TDMI core. The four 32-bit registers dedicated to IRQ
follow.
The ADuC7120/ADuC7121 contain a vectored interrupt
controller (VIC) that supports nested interrupts up to eight
levels. The VIC also allows the programmer to assign priority
levels to all interrupt sources. Set the ENIRQN bit in the
Table 116. IRQ/FIQ MMRs Bit Designations
Bit
Description
All interrupts OR’ed (FIQ only)
Software interrupt
Timer0
Comments
0
1
2
3
4
5
6
7
This bit is set if any FIQ is active
User-programmable interrupt source
General-Purpose Timer0
General-Purpose Timer1
General-Purpose Timer2 or wake-up timer
General-Purpose Timer3 or watchdog timer
General-Purpose Timer4
IDAC fault IRQ
Timer1
Timer2 or wake-up timer
Timer3 or watchdog timer
Timer4
IDAC fault
8
PSM
Power supply monitor
9
Undefined
This bit is not used
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
Flash Control 0
Flash Control 1
ADC
UART
SPI
I2C0 master IRQ
I2C0 slave IRQ
I2C1 master IRQ
I2C1 slave IRQ
XIRQ0 (GPIO IRQ0 )
XIRQ1 (GPIO IRQ1)
XIRQ2 (GPIO IRQ2 )
XIRQ3 (GPIO IRQ3)
PWM
Flash controller for Block 0 interrupt
Flash controller for Block 1 interrupt
ADC interrupt source bit
UART interrupt source bit
SPI interrupt source bit
I2C Master Interrupt Source 0 bit
I2C Slave Interrupt Source 0 bit
I2C Master Interrupt Source 1 bit
I2C Slave Interrupt Source 1 bit
External Interrupt 0
External Interrupt 1
External Interrupt 2
External Interrupt 3
PWM trip interrupt source bit
External Interrupt 4
XIRQ4 (GPIO IRQ4 )
XIRQ5 (GPIO IRQ5)
PLA IRQ0
External Interrupt 5
PLA Block 0 IRQ bit
PLA Block 1 IRQ bit
PLA IRQ1
Rev. D | Page 82 of 102
Data Sheet
ADuC7120/ADuC7121
IRQSIG Register
IRQSTA Register
IRQSIG reflects the status of the different IRQ sources. If a
peripheral generates an IRQ signal, the corresponding bit in
the IRQSIG is set; otherwise, it is cleared. The IRQSIG bits clear
when the interrupt in the particular peripheral is cleared. All
IRQ sources can be masked in the IRQEN MMR. IRQSIG is a
read only register. Do not use this register in an interrupt service
routine for determining the source of an IRQ exception; use
only IRQSTA for this purpose.
IRQSTA is a read only register that provides the current enabled
IRQ source status (effectively a logic AND of the IRQSIG and
IRQEN bits). When set to 1, that source generates an active IRQ
request to the ARM7TDMI core. There is no priority encoder
or interrupt vector generation. This function is implemented in
software in a common interrupt handler routine.
Name:
IRQSTA
Address:
Default value:
Access:
0xFFFF0000
0x00000000
Read only
Name:
IRQSIG
Address:
0xFFFF0004
Default value: 0x00000000
Access:
Read only
FAST INTERRUPT REQUEST (FIQ)
The fast interrupt request (FIQ) is the exception signal to enter
the FIQ mode of the processor. It is provided to service data
transfer or communication channel tasks with low latency. The
FIQ interface is identical to the IRQ interface and provides the
second level interrupt (highest priority). Four 32-bit registers
are dedicated to FIQ: FIQSIG, FIQEN, FIQCLR, and FIQSTA.
IRQEN Register
IRQEN provides the value of the current enable mask. When
a bit is set to 1, the corresponding source request is enabled to
create an IRQ exception. When a bit is set to 0, the corresponding
source request is disabled or masked, which does not create an
IRQ exception. The IRQEN register cannot be used to disable
an interrupt.
Bit 31 to Bit 1 of FIQSTA are logically OR’ed to create the FIQ
signal to the core and to Bit 0 of both the FIQ and IRQ registers
(FIQ source).
Name:
IRQEN
The logic for FIQEN and FIQCLR does not allow an interrupt
source to be enabled in both IRQ and FIQ masks. A bit set to 1
in FIQEN clears, as a side effect, the same bit in IRQEN. Likewise,
a bit set to 1 in IRQEN clears, as a side effect, the same bit in
FIQEN. An interrupt source can be disabled in both IRQEN
and FIQEN masks.
Address:
Default value:
Access:
0xFFFF0008
0x00000000
Read and write
IRQCLR Register
FIQSIG Register
IRQCLR is a write only register that allows the IRQEN register
to clear or mask an interrupt source. Each bit that is set to 1
clears the corresponding bit in the IRQEN register without
affecting the remaining bits. A pair of registers, IRQEN and
IRQCLR, allows independent manipulation of the enable mask
without requiring an atomic read modify write.
FIQSIG reflects the status of the different FIQ sources. If a
peripheral generates an FIQ signal the corresponding bit in
the FIQSIG is set; otherwise, it is cleared. The FIQSIG bits are
cleared when the interrupt in the particular peripheral is
cleared. All FIQ sources can be masked in the FIQEN MMR.
FIQSIG is read only.
Use this register to disable an interrupt source only when:
•
The device is in the interrupt sources interrupt service
Name:
FIQSIG
routine.
Address:
0xFFFF0104
•
The peripheral is temporarily disabled by its own control
register.
Default value: 0x00000000
Access: Read only
Do not use the IRQCLR to disable an IRQ source if that IRQ
source has an interrupt pending or could have an interrupt
pending.
Name:
IRQCLR
Address:
0xFFFF000C
Default value: 0x00000000
Access: Write only
Rev. D | Page 83 of 102
ADuC7120/ADuC7121
Data Sheet
FIQEN Register
Programmed Interrupts
FIQEN provides the value of the current enable mask. When a
bit is set to 1, the corresponding source request is enabled to create
an FIQ exception. When a bit is set to 0, the corresponding
source request is disabled or masked, which does not create an
FIQ exception. The FIQEN register cannot be used to disable an
interrupt.
Because the programmed interrupts are not maskable, they are
controlled by another register (SWICFG) that writes into both
IRQSTA and IRQSIG registers and/or the FIQSTA and FIQSIG
registers at the same time.
SWICFG is the 32-bit register dedicated to software interrupt
(see Table 117). This MMR can control a programmed source
interrupt.
FIQEN Register
Name:
FIQEN
Table 117. SWICFG MMR Bit Designations
Bit(s)
[31:3]
2
Description
Address:
0xFFFF0108
Reserved.
Default value: 0x00000000
Programmed Interrupt FIQ. Setting or clearing this bit
corresponds to setting or clearing Bit 1 of FIQSTA and
FIQSIG.
Access:
Read and write
FIQCLR
1
Programmed Interrupt IRQ1. Setting or clearing this bit
corresponds to setting or clearing Bit 1 of IRQSTA and
IRQSIG.
FIQCLR is a write only register that allows the FIQEN register
to clear to mask an interrupt source. Each bit that is set to 1
clears the corresponding bit in the FIQEN register without
affecting the remaining bits. A pair of registers, FIQEN and
FIQCLR, allows independent manipulation of the enable mask
without requiring an atomic read modify write.
0
Reserved.
Any interrupt signal must be active for at least the minimum
interrupt latency time to be detected by the interrupt controller
and to be detected by the user in the IRQSTA register or the
FIQSTA register.
Use this register to disable an interrupt source only when:
PROGRAMMABLE PRIORITY
PER INTERRUPT (IRQP0/IRQP1/IRQP2)
•
The device is in the interrupt sources interrupt service
routine.
POINTER TO
FUNCTION
(IRQVEC)
IRQ_SOURCE
FIQ_SOURCE
•
The peripheral is temporarily disabled by its own control
register.
INTERNAL
ARBITER
LOGIC
Do not use this register to disable an FIQ source if that FIQ
source has an interrupt pending or a potential interrupt
pending.
INTERRUPT VECTOR
FIQCLR Register
Name:
FIQCLR
BIT 31 TO BIT 22 TO BIT 7 BIT 6 TO BIT 1 TO
BIT 23
UNUSED
(IRQBASE)
BIT 2
BIT 0
LSB
HIGHEST
PRIORITY
ACTIVE IRQ
Address:
0xFFFF010C
0x00000000
Write only
Default value:
Figure 39. Interrupt Structure (See Table 116)
Access:
FIQSTA
FIQSTA is a read only register that provides the current enabled
FIQ source status (effectively a logic AND of the FIQSIG and
FIQEN bits). When set to 1, that source generates an active FIQ
request to the ARM7TDMI core. There is no priority encoder
or interrupt vector generation. This function is implemented in
software in a common interrupt handler routine.
FIQSTA Register
Name:
FIQSTA
Address:
0xFFFF0100
Default value: 0x00000000
Access: Read only
Rev. D | Page 84 of 102
Data Sheet
ADuC7120/ADuC7121
Vectored Interrupt Controller (VIC)
Table 119. IRQVEC MMR Bit Designations
Initial
Value Description
The ADuC7120/ADuC7121 incorporate an enhanced interrupt
control system or vectored interrupt controller. The vectored
interrupt controller for IRQ interrupt sources is enabled by
setting Bit 0 of the IRQCONN register. Similarly, Bit 1 of
IRQCONN enables the vectored interrupt controller for the FIQ
interrupt sources. The vectored interrupt controller provides the
following enhancements to the standard IRQ/FIQ interrupts:
Bit(s)
Type
[31:23] Read only
0
0
0
Always read as 0.
[22:7]
[6:2]
Read and write
IRQBASE register value.
Read only
Highest priority source; a
value between 0 and 27
representing the possible
interrupt sources. For
example, if the highest
currently active IRQ is
Timer2, these bits are 00100.
•
Vectored interrupts allow a user to define separate
interrupt service routine addresses for every interrupt
source, which is achieved by using the IRQBASE and
IRQVEC registers.
IRQ/FIQ interrupts can be nested up to eight levels
depending on the priority settings. An FIQ still has a higher
priority than an IRQ. Therefore, if the VIC is enabled for both
the FIQ and IRQ, and prioritization is maximized, it is
possible to have 16 separate interrupt levels.
[1:0]
Reserved
0
Reserved bits.
Priority Registers
•
IRQP0 Register
Name:
IRQP0
Address:
0xFFFF0020
•
Programmable interrupt priorities that use the IRQP0
to IRQP3 registers interrupt source can be assigned an
interrupt priority level value between 0 and 7.
Default value: 0x00000000
Access: Read and write
VIC MMRs
Table 120. IRQP0 MMR Bit Designations
IRQBASE Register
Bit
Name
Description
The vector base register, IRQBASE, points to the memory start
address that stores 32 pointer addresses. These pointer addresses
are the addresses of the individual interrupt service routines.
31
Reserved
Reserved bit.
[30:28] IDAC_FAULT A priority level of 0 to 7 can be set for an
IDAC fault interrupt.
27
Reserved
Reserved bit.
Name:
IRQBASE
[26:24] T4PI
A priority level of 0 to 7 can be set for
Timer4.
Address:
0xFFFF0014
23
Reserved
Reserved bit.
Default value: 0x00000000
Access: Read and write
[22:20] T3PI
A priority level of 0 to 7 can be set for
Timer3.
19
Reserved
Reserved bit.
[18:16] T2PI
A priority level of 0 to 7 can be set for
Timer2.
Table 118. IRQBASE MMR Bit Designations
Bits Type Initial Value Description
[31:16] Read only
15
Reserved
Reserved bit.
Reserved
0
Always read as 0
[14:12] T1PI
A priority level of 0 to 7 can be set for
Timer1.
[15:0]
Read and write
Vector base address
11
Reserved
Reserved bit.
IRQVEC Register
[10:8]
T0PI
A priority level of 0 to 7 can be set for
Timer0.
The IRQ interrupt vector register, IRQVEC, points to a memory
address containing a pointer to the interrupt service routine of
the currently active IRQ. Read this register only when an IRQ
occurs and IRQ interrupt nesting has been enabled by setting
Bit 0 of the IRQCONN register.
7
Reserved
SWINTP
Reserved bit.
[6:4]
A priority level of 0 to 7 can be set for
the software interrupt source.
[3:0]
Reserved
Reserved bit.
Name:
IRQVEC
Address:
0xFFFF001C
Default value: 0x00000000
Access: Read and write
Rev. D | Page 85 of 102
ADuC7120/ADuC7121
Data Sheet
IRQP1 Register
Bit(s)
Name
Description
A priority level of 0 to 7 can be set for I2C1
master.
[6:4]
I2C1MPI
Name:
IRQP1
3
Reserved Reserved bit.
I2C0SPI
A priority level of 0 to 7 can be set for I2C0
slave.
Address:
0xFFFF0024
[2:0]
Default value: 0x00000000
Access: Read and write
IRQP3 Register
Name:
IRQP3
Table 121. IRQP1 MMR Bit Designations
Bit(s)
Name
Description
Address:
0xFFFF002C
31
Reserved Reserved bit.
Default value: 0x00000000
Access: Read and write
[30:28] I2C0MPI
A priority level of 0 to 7 can be set for I2C 0
master.
27
Reserved Reserved bit.
[26:24] SPIPI
A priority level of 0 to 7 can be set for SPI.
IRQP3 MMR Bit Designations
Bit(s) Name Description
[31:15] Reserved Reserved bit.
[14:12] PLA1PI A priority level of 0 to 7 can be set for PLA0.
Reserved Reserved bit.
PLA0PI A priority level of 0 to 7 can be set for PLA0.
Reserved Reserved bit.
23
Reserved Reserved bit.
[22:20] UARTPI
A priority level of 0 to 7 can be set for UART.
19
Reserved Reserved bit.
[18:16] ADCPI
A priority level of 0 to 7 can be set for the
ADC interrupt source.
11
[10:8]
7
15
Reserved Reserved bit.
[14:12] Flash1PI
A priority level of 0 to 7 can be set for the
Flash Block 1 controller interrupt source.
[6:4]
3
IRQ5PI
A priority level of 0 to 7 can be set for IRQ5.
Reserved Reserved bit.
11
Reserved Reserved bit.
[2:0]
IRQ4PI
A priority level of 0 to 7 can be set for IRQ4.
[10:8]
Flash0PI
A priority level of 0 to 7 can be set for the
Flash Block 0 controller interrupt source.
IRQCONN Register
[7:3]
[2:0]
Reserved Reserved bits.
PSMPI A priority level of 0 to 7 can be set for the
power supply monitor interrupt source.
The IRQCONN register is the IRQ and FIQ control register.
It contains two active bits. The first to enable nesting and
prioritization of IRQ interrupts the other to enable nesting
and prioritization of FIQ interrupts.
IRQP2 Register
Name:
IRQP2
If these bits are cleared, FIQs and IRQs can still be used, but it is
not possible to nest IRQs or FIQs, nor is it possible to set an
interrupt source priority level. In this default state, an FIQ does
have a higher priority than an IRQ.
Address:
0xFFFF0028
Default value: 0x00000000
Access: Read and write
Name:
IRQCONN
0xFFFF0030
Address:
Table 122. IRQP2 MMR Bit Designations
Bit(s)
Name
Description
Default value: 0x00000000
Access: Read and write
31
Reserved Reserved bit.
[30:28] PWMPI
A priority level of 0 to 7 can be set for PWM.
A priority level of 0 to 7 can be set for IRQ3.
A priority level of 0 to 7 can be set for IRQ2.
A priority level of 0 to 7 can be set for IRQ1.
A priority level of 0 to 7 can be set for IRQ0.
27
Reserved Reserved bit.
Table 123. IRQCONN MMR Bit Designations
Bit(s) Name Description
[26:24] IRQ3PI
23
Reserved Reserved bit.
[31:2] Reserved These bits are reserved and must not be
written to.
[22:20] IRQ2PI
19
Reserved Reserved bit.
1
ENFIQN
Setting this bit to 1 enables nesting of FIQ
interrupts. Clearing this bit means no
nesting or prioritization of FIQs is allowed.
[18:16] IRQ1PI
15
Reserved Reserved bit.
[14:12] IRQ0PI
0
ENIRQN
Setting this bit to 1 enables nesting of IRQ
interrupts. Clearing this bit means no
nesting or prioritization of IRQs is allowed.
11
Reserved Reserved bit.
[10:8]
I2C1SPI
A priority level of 0 to 7 can be set for I2C1
slave.
7
Reserved Reserved bit.
Rev. D | Page 86 of 102
Data Sheet
ADuC7120/ADuC7121
IRQSTAN Register
Table 125. FIQVEC MMR Bit Designations
Initial
Value Description
If IRQCONN, Bit 0 is asserted and IRQVEC is read, one of
these bits is asserted. The bit that asserts depends on the
priority of the IRQ. If the IRQ is of Priority 0, Bit 0 asserts; if the
IRQ is of Priority 1, Bit 1 asserts; and so forth. When a bit is set in
this register, all interrupts of that priority and lower are blocked.
Bit(s)
Type
[31:23] Read only
0
0
Always read as 0.
[22:7]
[6:2]
Read and
write
IRQBASE register value.
0
0
Highest priority source. This is a
value between 0 and 27
representing the possible
interrupt sources. For example, if
the highest currently active FIQ is
Timer2, these bits are 00100.
To clear a bit in this register, all bits of a higher priority must be
cleared first. It is only possible to clear one bit at a time. For
example, if this register is set to 0x09, writing 0xFF changes the
register to 0x08 and writing 0xFF a second time changes the
register to 0x00.
[1:0]
Reserved
Reserved bits.
Name:
IRQSTAN
FIQSTAN Register
Address:
0xFFFF003C
If IRQCONN, Bit 1 is asserted and FIQVEC is read, one of
these bits assert. The bit that asserts depends on the priority of
the FIQ. If the FIQ is of Priority 0, Bit 0 asserts; if the FIQ is of
Priority 1, Bit 1 asserts, and so on.
Default value: 0x00000000
Access: Read and write
When a bit is set in this register, all interrupts of that priority
and lower are blocked.
Table 124. IRQSTAN MMR Bit Designations
Bit(s) Name Description
To clear a bit in this register, all bits of a higher priority must be
cleared first. It is only possible to clear one bit at a time. For
example, if this register is set to 0x09, writing 0xFF changes the
register to 0x08 and writing 0xFF a second time changes the
register to 0x00.
[31:8] Reserved These bits are reserved and must not be
written to.
[7:0]
Setting this bit to 1 enables nesting of FIQ
interrupts.
Clearing this bit means no nesting or
prioritization of FIQs is allowed.
Name:
FIQSTAN
FIQVEC Register
Address:
0xFFFF013C
The FIQ interrupt vector register, FIQVEC, points to a memory
address containing a pointer to the interrupt service routine of
the currently active FIQ. Read this register only when an FIQ
occurs and FIQ interrupt nesting has been enabled by setting
Bit 1 of the IRQCONN register.
Default value: 0x00000000
Access: Read and write
Table 126. FIQSTAN MMR Bit Designations
Bit(s) Name Description
Name:
FIQVEC
Address:
Default value:
Access:
0xFFFF011C
0x00000000
Read only
[31:8] Reserved These bits are reserved and must not be
written to.
[7:0]
FIQ
Setting this bit to 1 enables nesting of FIQ
interrupts. Clearing this bit means no
nesting or prioritization of FIQs is allowed.
nesting
Rev. D | Page 87 of 102
ADuC7120/ADuC7121
Data Sheet
Table 127. IRQCLRE MMR Bit Designations
Bit(s) Name Description
EXTERNAL INTERRUPTS (IRQ0 TO IRQ5)
The ADuC7120/ADuC7121 provide up to six external interrupt
sources. These external interrupts can be individually configured as
level or rising/falling edge triggered.
[31:25] Reserved These bits are reserved and must not be
written to.
24
IRQ5CLRI A 1 must be written to this bit in the IRQ5
interrupt service routine to clear an edge
triggered IRQ5 interrupt.
To enable the external interrupt source, first set the appropriate
bit in the FIQEN or IRQEN register. To select the required edge or
level to trigger on, configure the IRQCONE register appropriately.
24
IRQ4CLRI A 1 must be written to this bit in the IRQ4
interrupt service routine to clear an edge
triggered IRQ4 interrupt.
To properly clear an edge based external IRQ interrupt, set the
appropriate bit in the IRQCLRE register.
23
22
Reserved This bit is reserved.
IRQCONE Register
IRQ3CLRI A 1 must be written to this bit in the IRQ3
interrupt service routine to clear an edge
triggered IRQ3 interrupt.
Name:
IRQCONE
21
IRQ2CLRI A 1 must be written to this bit in the IRQ2
interrupt service routine to clear an edge
triggered IRQ2 interrupt.
Address:
Default value:
Access:
0xFFFF0034
0x00000000
Read and write
20
IRQ1CLRI A 1 must be written to this bit in the IRQ1
interrupt service routine to clear an edge
triggered IRQ1 interrupt.
19
IRQ0CLRI A 1 must be written to this bit in the IRQO
interrupt service routine to clear an edge
triggered IRQ0 interrupt.
IRQCLRE Register
Name:
IRQCLRE
[18:0]
Reserved These bits are reserved and must not be
written to.
Address:
0xFFFF0038
Default value: 0x00000000
Access: Write only
Table 128. IRQCONE MMR Bit Designations
Bit(s)
Name
Setting
Description
[31:12]
[11:10]
Reserved
IRQ5SRC[1:0]
These bits are reserved and must not be written to.
11 External IRQ5 triggers on falling edge.
10 External IRQ5 triggers on rising edge.
01 External IRQ5 triggers on low level.
00 External IRQ5 triggers on high level.
11 External IRQ4 triggers on falling edge.
10 External IRQ4 triggers on rising edge.
01 External IRQ4 triggers on low level.
00 External IRQ4 triggers on high level.
11 External IRQ3 triggers on falling edge.
10 External IRQ3 triggers on rising edge.
01 External IRQ3 triggers on low level.
00 External IRQ3 triggers on high level.
11 External IRQ2 triggers on falling edge.
10 External IRQ2 triggers on rising edge.
01 External IRQ2 triggers on low level.
00 External IRQ2 triggers on high level.
11 External IRQ1 triggers on falling edge.
10 External IRQ1 triggers on rising edge.
01 External IRQ1 triggers on low level.
00 External IRQ1 triggers on high level.
11 External IRQ0 triggers on falling edge.
10 External IRQ0 triggers on rising edge.
01 External IRQ0 triggers on low level.
00 External IRQ0 triggers on high level.
[9:8]
[7:6]
[5:4]
[3:2]
[1:0]
IRQ4SRC[1:0]
IRQ3SRC[1:0]
IRQ2SRC[1:0]
IRQ1SRC[1:0]
IRQ0SRC[1:0]
Rev. D | Page 88 of 102
Data Sheet
ADuC7120/ADuC7121
TIMERS
The ADuC7120/ADuC7121 have five general-purpose timers
and/or counters.
This arrangement applies to TxLD and TxVAL when using the
hour:minute:second: hundredths format as set in TxCON,
Bits[5:4]. See Table 130 for additional details.
•
•
•
•
•
Timer0
Timer1
Timer2 or wake-up timer
Timer3 or watchdog timer
Timer4
Table 130. Hour: Minute: Second: Hundredths Format
Bit(s)
[31:24]
[23:22]
[21:16]
[15:14]
[13.8]
7
Value
Description
0 to 23 or 0 to 255
0
0 to 59
0
0 to 59
0
Hours
Reserved
Minutes
Reserved
Seconds
Reserved
1/128 second
The five timers in their normal mode of operation can be either
free running or periodic.
In free running mode, the counter decrements or increments
from the maximum or minimum value until zero scale or full
scale and starts again at the maximum or minimum value.
[6:0]
0 to 127
TIMER0—LIFETIME TIMER
In periodic mode, the counter decrements or increments from
the value in the load register (TxLD MMR) until zero scale or
full scale and starts again at the value stored in the load register.
Timer0 is a general-purpose, 48-bit count up, or a 16-bit count
up/down timer with a programmable prescaler. Timer0 is
clocked from the core clock, with a prescaler of 1, 16, 256, or
32,768 that gives a minimum resolution of 22 ns when the core
is operating at 41.78 MHz and has a prescaler of 1. Timer0 can
also be clocked from the undivided core clock, internal 32 kHz
oscillator or external 32 kHz crystal.
The value of a counter can be read at any time by accessing its
value register (TxVALx). Timers are started by writing in the
control register of the corresponding timer (TxCON).
In normal mode, an IRQ is generated each time the value of the
counter reaches zero if counting down or full scale if counting up.
An IRQ can be cleared by writing any value to the clear register
of the particular timer (TxCLRI).
In 48-bit mode, Timer0 counts up from zero. The current
counter value can be read from T0VAL0 and T0VAL1.
In 16-bit mode, Timer0 can count up or count down. A 16-bit
value can be written to T0LD that is loaded into the counter. The
current counter value can be read from T0VAL0. Timer0 has a
capture register (T0CAP) that can be triggered by a selected source
initial assertion of the IRQ. When triggered, the current timer value
is copied to T0CAP, and the timer keeps running. This feature can
determine the assertion of an event with more accuracy than by
servicing an interrupt alone.
Table 129. Event Selection (ES) Numbers
ES
Interrupt Number
Name
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
RTOS timer (Timer0)
GP Timer0 (Timer1)
Wake-up timer (Timer2)
Watchdog timer (Timer3)
GP Timer4 (Timer4)
IDAC fault IRQ
Power supply monitor
Undefined
Timer0 reloads the value from T0LD either when TIMER0
overflows or immediately when T0ICLR is written.
Flash Block 0
Flash Block 1
ADC
The Timer0 interface consists of six MMRs (see Table 131).
Table 131. Timer0 Interface MMRs
UART
SPI
Name
Description
T0LD
16-bit register that holds the 16-bit value that loads
into the counter. Available only in 16-bit mode.
I2C0 master
I2C0 slave
T0CAP
16-bit register that holds the 16-bit value captured by
an enabled IRQ event. Available only in 16-bit mode.
I2C1 master
I2C1 slave
T0VAL0/ TOVAL0 is a 16-bit register that holds the 16 LSBs.
T0VAL1
T0VAL1 is a 32-bit register that holds the 32 MSBs.
External IRQ0
T0VAL0 and T0VAL1 are read only. In 16-bit mode,
16-bit T0VAL0 is used. In 48-bit mode, both 16-bit
T0VAL0 and 32-bit T0VAL1 are used.
HOUR: MINUTE: SECOND: 1/128 FORMAT
To use the timer in hour:minute:second:hundredths format,
select the 32,768 kHz clock and a prescaler of 256. The
hundredths field does not represent milliseconds but 1/128
of a second (256/32,768). The bits representing the hour,
minute, and second are not consecutive in the registers.
T0ICLR
T0CON
8-bit register. Writing any value to this register clears
the interrupt. Available only in 16-bit mode.
Configuration MMR.
Rev. D | Page 89 of 102
ADuC7120/ADuC7121
Data Sheet
Timer0 Value Registers
Bit(s)
Setting Description
Clock select.
[10:9]
T0VAL0 and T0VAL1 are 16-bit and 32-bit registers that hold
the 16 LSBs and 32 MSBs, respectively. T0VAL0 and T0VAL1 are
read only registers. In 16-bit mode, 16-bit T0VAL0 is used. In
48-bit mode, both 16-bit T0VAL0 and 32-bit T0VAL1 are used.
00 Internal 32 kHz oscillator.
01 UCLK.
10 External 32 kHz crystal.
11 HCLK.
Name:
T0VAL0
8
Count up. Available in 16-bit mode only.
Set by the user for Timer0 to count up.
Cleared by the user for Timer0 to count
down (default).
Address:
0xFFFF0304
Default value: 0x0000
7
6
Timer0 enable bit.
Access:
Read only
Set by the user to enable Timer0.
Cleared by the user to disable Timer0 (default).
Timer0 mode.
Name:
T0VAL1
Set by the user to operate in periodic mode.
Cleared by the user to operate in free running
mode (default).
Address:
0xFFFF0308
Default value: 0x00000000
Access: Read only
5
4
Reserved.
Timer0 mode of operation.
16-bit operation (default).
48-bit operation.
Prescaler.
0
1
Timer0 Capture Register
[3:0]
This is a 16-bit register that holds the 16-bit value captured by
an enabled IRQ event; available in 16-bit mode only.
0000 Source clock divide by 1 (default).
0100 Source clock divide by 16.
1000 Source clock divide by 256.
1111 Source clock divide by 32,768.
Name:
T0CAP
Address:
0xFFFF0314
Timer0 Load Registers
Default value: 0x0000
T0LD is a 16-bit register that holds the 16-bit value that loads
into the counter; available only in 16-bit mode.
Access:
Read only
Name:
T0LD
Timer0 Control Register
Address:
0xFFFF0300
This 17-bit MMR configures the mode of operation of Timer0.
Default value: 0x00
Name:
T0CON
Access:
Read and write
Address:
0xFFFF030C
Default value: 0x00000000
Access: Read and write
Timer0 Clear Register
This 8-bit, write only MMR is written (with any value) by user
code to refresh (reload) Timer0.
Table 132. T0CON MMR Bit Designations
Name:
T0CLRI
Bit(s)
[31:18]
17
Setting Description
Address:
0xFFFF0310
Reserved.
Event select bit.
Default value: 0x00
Access: Write only
Set by the user to enable time capture of an
event.
Cleared by the user to disable time capture
of an event.
[16:12]
11
Event select range, 0 to 16. The events are
described in the Timers section.
Reserved.
Rev. D | Page 90 of 102
Data Sheet
ADuC7120/ADuC7121
Timer1 Clear Register
TIMER1—GENERAL-PURPOSE TIMER
This 8-bit, write only MMR is written (with any value) by user
code to refresh (reload) Timer1.
Timer1 is a 32-bit general-purpose timer, count down or count up,
with a programmable prescaler. The prescaler source can be
from the 32 kHz internal oscillator, the 32 kHz external crystal,
the core clock, or the undivided PLL clock output. This source
can be scaled by a factor of 1, 16,256, or 32,768, which gives a
minimum resolution of 22 ns when operating at CD zero.
The core operates at 41.78 MHz with a prescaler of 1.
Name:
T1CLRI
Address:
0xFFFF032C
Default value: 0x00
The counter can be formatted as a standard 32-bit value or as
hours: minutes: seconds: hundredths.
Access:
Write only
Timer1 Value Register
Timer1 has a capture register (T1CAP) that can be triggered by
a source initial assertion of a selected IRQ. When triggered, the
current timer value is copied to T1CAP, and the timer keeps
running. This feature can determine the assertion of an event
with increased accuracy. Timer1 interface consists of five
MMRs (see Table 133).
T1VAL is a 32-bit register that holds the current value of Timer1.
Name:
T1VAL
Address:
0xFFFF0324
Default value: 0x00000000
Access: Read only
If the devices are in low power mode and Timer1 is clocked
from the GPIO or low power oscillator source, Timer1
continues to operate.
Timer1 reloads the value from T1LD either when Timer1
overflows or immediately when T1ICLR is written.
Timer1 Capture Register
This is a 32-bit register that holds the 32-bit value captured by
an enabled IRQ event.
Table 133. Timer1 Interface Registers
Register Description
Name:
T1CAP
T1LD
32-bit register. Holds 32-bit unsigned integers. This
register is read only.
32-bit register. Holds 32-bit unsigned integers.
32-bit register. Holds 32-bit unsigned integers. This
register is read only.
Address:
0xFFFF0330
T1VAL
T1CAP
Default value: 0x0000
T1CLRI
T1CON
8-bit register. Writing any value to this register clears
the Timer1 interrupt.
Configuration MMR.
Access:
Read only
Timer1 Control Register
This 32-bit MMR configures the mode of operation of Timer1.
Timer1 Load Registers
Name:
T1CON
T1LD is a 32-bit register that holds the 32-bit value that loads
into the counter.
Address:
0xFFFF0328
Name:
T1LD
Default value: 0x00000000
Access: Read and write
Address:
0xFFFF0320
Default value: 0x00000000
Access: Read and write
Table 134. T1CON MMR Bit Designations
Bit(s)
[31:24]
23
Setting
Description
8-bit post scaler.
Enable write to post scaler.
Reserved.
[22:20]
19
Post scaler compare flag.
T1 interrupt generation selection flag.
Event select bit.
18
17
Set by the user to enable time capture of an event.
Cleared by the user to disable time capture of an event.
Rev. D | Page 91 of 102
ADuC7120/ADuC7121
Data Sheet
Bit(s)
[16:12]
[11:9]
Setting
Description
Event select range, 0 to 16. The events are as described in the introduction to the Timers section.
Clock select.
000 Internal 32 kHz oscillator (default).
001 Core clock.
010 UCLK.
011 P0.6. of the P0.6/MRST/PLAI[2] pin.
8
Count up.
Set by the user for Timer1 to count up.
Cleared by the user for Timer1 to count down (default).
Timer1 enable bit.
7
Set by the user to enable Timer1.
Cleared by the user to disable Timer1 (default).
Timer1 mode.
6
Set by the user to operate in periodic mode.
Cleared by the user to operate in free running mode (default).
Format.
[5:4]
00 Binary (default).
01 Reserved.
10 Hours: minutes: seconds: hundredths: 23 hours to 0 hour.
11 Hours: minutes: seconds: hundredths: 255 hours to 0 hour.
Prescaler.
[3:0]
0000 Source clock divide by 1 (default).
0100 Source clock divide by 16.
1000 Source clock divide by 256.
1111 Source clock divide by 32,768.
Rev. D | Page 92 of 102
Data Sheet
ADuC7120/ADuC7121
Timer2 Clear Register
TIMER2—WAKE-UP TIMER
This 8-bit write only MMR is written (with any value) by the
user code to refresh (reload) Timer2.
Timer2 is a 32-bit wake-up timer, count down or count up, with
a programmable prescaler. The prescaler is clocked directly from
one of four clock sources, the core clock (default selection), the
internal 32.768 kHz oscillator, the external 32.768 kHz watch
crystal, or the PLL undivided clock. The selected clock source
can be scaled by a factor of 1, 16, 256, or 32,768. The wake-up
timer continues to run when the core clock is disabled, which
gives a minimum resolution of 22 ns when the core operates at
41.78 MHz with a prescaler of 1. Enable the Timer2 interrupt
via IRQEN, Bit 4, to enable the capture of the current timer value.
Name:
T2CLRI
Address:
0xFFFF034C
Default value: 0x00
Access:
Write only
Timer2 Value Register
The counter can be formatted as a plain 32-bit value or as
hours: minutes: seconds: hundredths.
T2VAL is a 32-bit register that holds the current value of Timer2.
Name:
T2VAL
Timer2 reloads the value from T2LD either when Timer2
overflows or immediately when T2CLRI is written. The
Timer2 interface consists of four MMRs (see Table 135).
Address:
0xFFFF0344
Default value: 0x00000000
Access: Read only
Table 135. Timer2 Interface Registers
Register Description
T2LD
T2VAL
32-bit register. Holds 32-bit unsigned integers.
32-bit register. Holds 32-bit unsigned integers.
This register is read only.
Timer2 Control Register
This 32-bit MMR configures the mode of operation for Timer2.
T2CLRI
T2CON
8-bit register. Writing any value to this register clears
the Timer2 interrupt.
Configuration MMR.
Name:
T2CON
Address:
0xFFFF0348
Timer2 Load Registers
Default value: 0x00000000
Access: Read and write
T2LD is a 32-bit register that holds the 32-bit value that loads
into the counter.
Name:
T2LD
Address:
0xFFFF0340
Default value: 0x00000000
Access: Read and write
Table 136. T2CON MMR Bit Designations
Bit(s)
[31:11]
[10:9]
Setting Description
Reserved.
Clock source select.
00 Internal 32.768 kHz oscillator (default).
01 Core clock.
10 External 32.768kHz watch crystal.
11 UCLK.
8
7
6
Count up.
Set by the user for Timer2 to count up.
Cleared by the user for Timer2 to count down (default).
Timer2 enable bit.
Set by the user to enable Timer2.
Cleared by the user to disable Timer2 (default).
Timer2 mode.
Set by the user to operate in periodic mode.
Cleared by the user to operate in free running mode (default).
Rev. D | Page 93 of 102
ADuC7120/ADuC7121
Data Sheet
Bit(s)
Setting Description
[5:4]
Format.
00 Binary (default).
01 Reserved.
10 Hours: minutes: seconds: hundredths: 23 hours to 0 hour.
11 Hours: minutes: seconds: hundredths: 255 hours to 0 hour.
Prescaler.
[3:0]
0000 Source clock divide by 1 (default).
0100 Source clock divide by 16.
1000 Source clock divide by 256. Use this setting in conjunction with Timer2 Format 1, 0 and Format 1, 1.
1111 Source clock divide by 32,768.
power-on reset event resets the watchdog timer. After any
other reset event, the watchdog timer continues to count.
Configure the watchdog timer in the initial lines of user code
to avoid an infinite loop of watchdog resets.
TIMER3—WATCHDOG TIMER
Timer3 has two modes of operation: normal mode and watchdog
mode. The watchdog timer recovers the devices from illegal
software states. When enabled, the watchdog timer requires
periodic servicing to prevent it from forcing a reset of the
processor.
Timer3 automatically halts during JTAG debug access and only
recommences counting when JTAG has relinquished control of
the ARM7TDMI core. By default, Timer3 continues to count
during power-down, which can be disabled by setting Bit 0 in
T3CON. It is recommended to use the default value, that is, the
watchdog timer continues to count during power-down.
Timer3 reloads the value from T3LD either when Timer3
overflows or immediately when T3CLRI is written.
16-BIT LOAD
Timer3 Interface
WATCHDOG
16-BIT
Timer3 interface consists of four MMRS (see Table 137).
RESET
LOW POWER
32.768kHz
PRESCALER
1, 16, OR 256
UP/DOWN
COUNTER
TIMER3IRQ
Table 137. Timer3 Interface Registers
Register Description
TIMER3 VALUE
T3CON
T3LD
The configuration MMR.
6-bit register (Bit 0 to Bit15); holds 16-bit unsigned
integers.
Figure 40. Timer3 Block Diagram
Normal Mode
T3VAL
T3CLRI
6-bit register (Bit 0 to Bit 15); holds 16-bit unsigned
integers. This register is read only.
8-bit register. Writing any value to this register clears
the Timer3 interrupt in normal mode or resets a new
timeout period in watchdog mode.
Timer3 in normal mode is identical to Timer0 in 16-bit mode
of operation except for the clock source. The clock source is the
32.768 kHz oscillator and can be scaled by a factor of 1, 16, or
256. Timer3 also features a capture facility that allows capture
of the current timer value if Timer2 interrupt is enabled via
IRQEN, Bit 5.
Timer3 Load Register
This 16-bit MMR holds the Timer3 reload value.
Watchdog Mode
Name:
T3LD
Set T3CON, Bit 5 to enter watchdog mode. Timer3 decrements
from the timeout value present in the T3LD register until 0.
The maximum timeout is 512 seconds, using the maximum
prescaler divide by 256 and full scale in T3LD.
Address:
0xFFFF0360
Default value: 0x3BF8
To avoid any conflict with Flash/EE memory page erase cycles
that require 20 ms to complete a single page erase cycle and
kernel execution, only configure user software a minimum
timeout period of 30 ms.
Access:
Read and write
Timer3 Value Register
This 16-bit, read only MMR holds the current Timer3 count value.
If T3VAL reaches 0, a reset or an interrupt occurs depending
on T3CON, Bit 1. To avoid a reset or an interrupt event, write
any value to T3ICLR before T3VAL reaches zero to reload the
counter with T3LD and begin a new timeout period.
Name:
T3VAL
Address:
0xFFFF0364
Default value: 0x3BF8
Access: Read only
Once watchdog mode is entered, T3LD and T3CON are write
protected. These two registers cannot be modified until a
Rev. D | Page 94 of 102
Data Sheet
ADuC7120/ADuC7121
Timer3 Clear Register
Timer3 Control Register
This 8-bit, write only MMR is written (with any value) by user
code to refresh (reload) Timer3 in watchdog mode to prevent a
watchdog timer reset event.
The 16-bit MMR configures the mode of operation of Timer3
and is described in detail in Table 138.
Name:
T3CON
Name:
T3CLRI
Address:
0xFFFF0368
Address:
0xFFFF036C
Default value: 0x0000
Access: Read and write one time only
Default value: 0x0000
Access:
Write only
Table 138. T3CON MMR Bit Designations
Bit(s)
[15:9]
8
Setting
Description
These bits are reserved and should be written as 0s by user code.
Count up/down enable.
Set by user code to configure Timer3 to count up.
Cleared by user code to configure Timer3 to count down.
Timer3 enable.
7
Set by user code to enable Timer3.
Cleared by user code to disable Timer3.
6
Timer3 operating mode.
Set by user code to configure Timer3 to operate in periodic mode.
Cleared by user to configure Timer3 to operate in free running mode.
Watchdog timer mode enable.
5
Set by user code to enable watchdog mode.
Cleared by user code to disable watchdog mode.
Secure clear bit.
4
Set by the user to use the secure clear option.
Cleared by the user to disable the secure clear option by default.
Timer3 Clock (32.768 kHz) prescaler.
[3:2]
00 Source clock divide by 1 (default).
01 Reserved.
10 Reserved.
11 Reserved.
1
0
Watchdog timer IRQ enable.
Set by user code to produce an IRQ instead of a reset when the watchdog reaches 0.
Cleared by user code to disable the IRQ option.
Power-down off (PD_OFF).
Set by user code to stop Timer3 when the peripherals are powered down via Bit 4 in the POWCON MMR.
Cleared by user code to enable Timer3 when the peripherals are powered down via Bit 4 in the POWCON MMR.
Rev. D | Page 95 of 102
ADuC7120/ADuC7121
Data Sheet
Secure Clear Bit (Watchdog Mode Only)
Because of the properties of the polynomial, do not use the
0x00 value as an initial seed. Value 0x00 is always guaranteed to
force an immediate reset. The value of the LFSR cannot be read;
it must be tracked/generated in software.
The secure clear bit is provided for a higher level of protection.
When set, a specific sequential value must be written to T3CLRI
to avoid a watchdog reset. The value is a sequence generated by
the 8-bit linear feedback shift register (LFSR) polynomial =
X8 + X6 + X5 + X + 1.
Example of a sequence:
1. Enter initial seed, 0xAA, in T3CLRI before starting Timer3
in watchdog mode.
2. Enter 0xAA in T3CLRI; Timer3 is reloaded.
3. Enter 0x37 in T3CLRI; Timer3 is reloaded.
4. Enter 0x6E in T3CLRI; Timer3 is reloaded.
5. Enter 0x66. 0xDC was expected; the watchdog resets the chip.
The initial value or seed is written to T3CLRI before entering
watchdog mode. After entering watchdog mode, a write to
T3CLRI must match this expected value. If it matches, the LFSR
is advanced to the next state when the counter reload happens.
If it fails to match the expected state, reset is immediately
generated, even if the count is not expired.
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
7
6
5
4
3
2
1
0
CLOCK
Figure 41. 8-Bit LFSR
Rev. D | Page 96 of 102
Data Sheet
ADuC7120/ADuC7121
Timer4 Clear Register
TIMER4—GENERAL-PURPOSE TIMER
This 8-bit, write only MMR is written (with any value) by user
code to refresh (reload) Timer4.
Timer4 is a 32-bit general-purpose timer, count down or count up,
with a programmable prescaler. The prescaler source can be the
32 kHz oscillator, the core clock, or PLL undivided output. This
source can be scaled by a factor of 1, 16, 256, or 32,768, which
gives a minimum resolution of 42 ns when operating at CD
zero, and the core operates at 41.78 MHz with a prescaler of 1
(ignoring external GPIO).
Name:
T4CLRI
Address:
0xFFFF038C
Default value: 0x00
The counter can be formatted as a standard 32-bit value or as
hours: minutes: seconds: hundredths.
Access:
Write only
Timer4 Value Register
Timer4 has a capture register (T4CAP) that can be triggered by
a selected source initial assertion of the IRQ. Once triggered,
the current timer value is copied to T4CAP, and the timer
continues running. This feature can determine the assertion of
an event with increased accuracy.
T4VAL is a 32-bit register that holds the current value of Timer4.
Name:
T4VAL
Address:
0xFFFF0384
The Timer4 interface consists of the following five MMRS:
Default value: 0x00000000
Access: Read only
•
•
•
T4LD, T4VAL, and T4CAP are 32-bit registers and hold
32-bit unsigned integers; T4VAL and T4CAP are read only.
T4ICLR is an 8-bit register. Writing any value to this
register clears the Timer1 interrupt.
Timer4 Capture Register
This is a 32-bit register that holds the 32-bit value captured by
an enabled IRQ event.
T4CON is the configuration MMR.
If the devices are in low power mode, and Timer4 is clocked
from the GPIO or oscillator source, Timer4 continues to
operate.
Name:
T4CAP
Address:
0xFFFF0390
Timer4 reloads the value from T4LD either when Timer4
overflows or immediately when T4ICLR is written.
Default value: 0x00000000
Access: Read only
Timer4 Load Registers
T4LD is a 32-bit register that holds the 32-bit value that loads
into the counter.
Timer4 Control Register
This 32-bit MMR configures the mode of operation of Timer4.
Name:
T4LD
Name:
T4CON
Address:
0xFFFF0380
Address:
0xFFFF0388
Default value: 0x00000000
Access: Read and write
Default value: 0x0000
Access: Read and write
Table 139. T4CON MMR Bit Designations
Bit(s)
[31:18]
17
Setting Description
Reserved. Set by the user to 0.
Event select bit.
Set by the user to enable time capture of an event.
Cleared by the user to disable time capture of an event.
[16:12]
Event select range, 0 to 31. The events are described in the Timers section.
Rev. D | Page 97 of 102
ADuC7120/ADuC7121
Data Sheet
Bit(s)
Setting Description
Clock select.
[11:9]
000 32.768 kHz oscillator.
001 HCLK (core clock).
010 UCLK.
011 UCLK.
8
Count up.
Set by the user for Timer4 to count up.
Cleared by the user for Timer4 to count down (default).
Timer4 enable bit.
7
Set by the user to enable Timer4.
Cleared by the user to disable Timer4 (default).
Timer4 mode.
6
Set by the user to operate in periodic mode.
Cleared by the user to operate in free running mode (default).
Format.
[5:4]
00 Binary (default).
01 Reserved.
10 Hours: minutes: seconds: hundredths: 23 hours to 0 hour.
11 Hours: minutes: seconds: hundredths: 255 hours to 0 hour.
Prescaler.
[3:0]
0000 Source clock divide by 1 (default).
0100 Source clock divide by 16.
1000 Source clock divide by 256.
1111 Source clock divide by 32,768.
Rev. D | Page 98 of 102
Data Sheet
ADuC7120/ADuC7121
HARDWARE DESIGN CONSIDERATIONS
As an alternative to providing two separate power supplies, the
user can reduce noise on AVDD by placing a small series resistor
and/or ferrite bead between AVDD and IOVDD, and then
decouple AVDD separately to ground. An example of this
configuration is shown in Figure 43. With this configuration,
other analog circuitry (such as op amps, voltage reference, and
others) can be powered from the AVDD supply line as well.
BEAD
POWER SUPPLIES
The ADuC7120/ADuC7121 operational power supply voltage
range is 3.0 V to 3.6 V. Separate analog and digital power supply
pins (AVDD and IOVDD, respectively) allow AVDD to be kept
relatively free of noisy digital signals often present on the system
IOVDD line. In this mode, the devices can also operate with
split supplies, that is, using different voltage levels for each supply.
For example, the system can operate with an IOVDD voltage
level of 3.3 V while the AVDD level can be at 3 V, or vice versa.
A typical split supply configuration is shown in Figure 42.
DIGITAL SUPPLY
ANALOG SUPPLY
10µF
10µF
+
–
ADuC7120/
ADuC7121
DIGITAL SUPPLY
ANALOG SUPPLY
IOVDD
AVDD
AVDD
AVDD
AVDD
10µF
10µF
+
+
0.1µF
IOVDD
ADuC7120/
ADuC7121
–
–
IOVDD
0.1µF
0.1µF
0.1µF
AVDD
AVDD
AVDD
AVDD
IOVDD
0.1µF
0.1µF
0.1µF
0.1µF
IOGND
IOGND
0.1µF
AGND
AGND
AGND
AGND
0.1µF
IOGND
IOGND
AGND
AGND
AGND
AGND
Figure 43. External Single Supply Connections
Notice that in both Figure 42 and Figure 43, a large value
(10 µF) reservoir capacitor sits on IOVDD, and a separate 10 µF
capacitor sits on AVDD. In addition, local small value (0.1 µF)
capacitors are located at each AVDD and IOVDD pin of the
chip. As per standard design practice, include all of these
capacitors and ensure that the smaller capacitors are close to
each AVDD pin with trace lengths as short as possible. Connect
the ground terminal of each of these capacitors directly to the
underlying ground plane. The analog and digital ground pins on
the ADuC7120/ADuC7121 must be referenced to the same
system ground reference point at all times.
Figure 42. External Dual-Supply Connections
Rev. D | Page 99 of 102
ADuC7120/ADuC7121
Data Sheet
IOVDD Supply Sensitivity
on IOVDD to help improve line regulation performance of the
on-chip voltage regulator.
The IOVDD supply is sensitive to high frequency noise because
it is the supply source for the internal oscillator and PLL circuits.
When the internal PLL loses lock, the clock source is removed
by a gating circuit from the CPU, and the ARM7TDMI core stops
executing code until the PLL regains lock. This feature ensures
that no flash interface timings or ARM7TDMI timings are violated.
GROUNDING AND BOARD LAYOUT
RECOMMENDATIONS
As with all high resolution data converters, special attention
must be paid to grounding and PCB layout of ADuC7120/
ADuC7121-based designs to achieve optimum performance
from the ADCs and DAC.
Typically, frequency noise greater than 50 kHz and 50 mV p-p
on top of the supply causes the core to stop working.
Although the devices have separate pins for analog and digital
ground (AGND and IOGND), do not tie these to two separate
ground planes unless the two ground planes are connected close
to the device. A simplified example of this is shown in Figure 46.
If decoupling values recommended in the Power Supplies section
do not sufficiently dampen all noise sources below 50 mV on
IOVDD, a filter such as the one shown in Figure 44 is
recommended.
1µH
ADuC7120/
DIGITAL
SUPPLY
10µF
+
–
PLACE ANALOG
COMPONENTS HERE
PLACE DIGITAL
COMPONENTS HERE
ADuC7121
IOVDD
IOVDD
AGND
DGND
0.1µF
0.1µF
IOGND
IOGND
Figure 46. System Grounding Scheme Example of Two Ground Planes
Connected Close to the Devices
In systems where digital and analog ground planes are connected
together somewhere else (at the power supply of the system, for
example), the planes can not be reconnected near the device
because a ground loop can result. In these cases, tie all AGND
and IOGND pins of the ADuC7120/ADuC7121 to the analog
ground plane, as shown in Figure 47.
Figure 44. Recommended IOVDD Supply Filter
Linear Voltage Regulator
Each ADuC7120/ADuC7121 requires a single 3.3 V supply,
but the core logic requires a 2.6 V supply. An on-chip linear
regulator generates the 2.6 V from IOVDD for the core logic.
The DVDD pins are the 2.6 V supply for the core logic. An
external compensation capacitor of 0.47 μF must be connected
between each DVDD and DGND (as close as possible to these
pins) to act as a tank of charge as shown in Figure 45. The internal
IDACs require a 2.5 V supply. An internal LDO provides a stable
2.5 V supply. The AVDD_IDAC pin is the 2.5 V supply for the
IDACs. An external compensation capacitor of 0.47 μF must be
connected between AVDD_IDAC and AGND (as close as possible
to these pins) to act as a tank of charge as shown in Figure 45.
PLACE ANALOG
COMPONENTS
HERE
PLACE DIGITAL
COMPONENTS HERE
AGND
DGND
Figure 47. System Grounding Scheme Example of All AGND and IOGND Pins
Tied to the Analog Ground Plane
In systems with only one ground plane, ensure that the digital
and analog components are physically separated onto separate
halves of the board so digital return currents do not flow near
analog circuitry and vice versa. The ADuC7120/ADuC7121 can
then be placed between the digital and analog sections, as
shown in Figure 48.
ADuC7120/
ADuC7121
DVDD
0.47µF
DGND
DVDD
0.47µF
DGND
AVDD_IDAC
PLACE ANALOG
COMPONENTS HERE
PLACE DIGITAL
COMPONENTS HERE
0.47µF
AGND
DGND
Figure 45. Voltage Regulator Connections
Do not use the DVDD pins for any other chip. It is also
recommended to use excellent power supply decoupling
Figure 48. System Grounding Scheme Example of ADuC7120/ADuC7121
Placed Between the Digital and Analog Sections
Rev. D | Page 100 of 102
Data Sheet
ADuC7120/ADuC7121
In these three scenarios, and in more complicated real-life
applications, pay particular attention to the flow of current from
the supplies and back to ground. Ensure that the return paths
for all currents are as close as possible to the paths the currents
took to reach their destinations. For example, do not power
components on the analog side, as shown in Figure 47, with
IOVDD because that forces return currents from IOVDD to
flow through AGND.
CLOCK OSCILLATOR
An internal PLL or an external clock input can generate a clock
source for the ADuC7120/ADuC7121. To use the internal PLL,
connect a 32.768 kHz parallel resonant crystal between XTALI
and XTALO and connect a capacitor from each pin to ground
(see Figure 49). This crystal allows the PLL to lock correctly to
give a frequency of 41.78 MHz. If no external crystal is present, the
internal oscillator typically gives a frequency of 41.78 MHz 3%.
In addition, avoid digital currents flowing under analog circuitry,
which can occur if a noisy digital chip is placed on the left half
of the board, as shown in Figure 48. If possible, avoid large
discontinuities in the ground plane(s) (such as those formed by
a long trace on the same layer) because they force return signals
to travel a longer path. In addition, make all connections to the
ground plane directly, with little or no trace separating the pin
from its via to ground.
ADuC7120/
ADuC7121
XTALI
12pF
32.768kHz
TO
INTERNAL
PLL
12pF
XTALO
Figure 49. External Parallel Resonant Crystal Connections
When connecting fast logic signals (rise or fall times < 5 ns) to
any of the ADuC7120/ADuC7121 digital inputs, add a series
resistor to each relevant line to keep rise and fall times longer
than 5 ns at the input pins of the devices. A resistor value of
100 Ω or 200 Ω is usually sufficient enough to prevent high
speed signals from coupling capacitively into the devices and
affecting the accuracy of ADC conversions.
To use an external clock source input instead of the PLL (see
Figure 50), Bit 1 and Bit 0 of Register PLLCON must be
modified. The external clock uses P1.4 and XCLK.
ADuC7120/
ADuC7121
XTALO
XTALI
EXTERNAL
CLOCK
SOURCE
TO
FREQUENCY
DIVIDER
XCLK
Figure 50. Connecting an External Clock Source
Using an external clock source, the ADuC7120/ADuC7121
specified operational clock speed range is 50 kHz to 41.78 MHz
1% to ensure correct operation of the analog peripherals and
Flash/EE.
Rev. D | Page 101 of 102
ADuC7120/ADuC7121
OUTLINE DIMENSIONS
Data Sheet
7.10
7.00 SQ
6.90
A1 BALL
CORNER
12
10
8
6
4
2
3 1
11
9
7
5
A
B
C
D
E
F
BALL A1
PAD CORNER
5.50
BSC SQ
G
H
J
K
L
0.50
BSC
M
BOTTOM VIEW
TOP VIEW
DETAIL A
*
1.11 MAX
*
DETAIL A
1.40 MAX
0.15 MIN
COPLANARITY
0.08
0.35
0.30
0.25
SEATING
PLANE
BALL DIAMETER
*
COMPLIANT WITH JEDEC STANDARDS MO-195-BD WITH
EXCEPTION TO PACKAGE HEIGHT AND THICKNESS.
Figure 51. 108-Ball Chip Scale Package Ball Grid Array [CSP_BGA]
(BC-108-4)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
Package Description
Package Option
BC-108-4
BC-108-4
ADuC7120BBCZ
ADuC7120BBCZ-RL
ADuC7121BBCZ
ADuC7121BBCZ-RL
EVAL-ADuC7120QSPZ
EVAL-ADuC7121QSPZ
108-Ball CSP_BGA
108-Ball CSP_BGA, 13”Tape and Reel
108-Ball CSP_BGA
BC-108-4
BC-108-4
108-Ball CSP_BGA, 13”Tape and Reel
ADuC7120 QuickStart Development System
ADuC7121 QuickStart Development System
1 Z = RoHS Compliant Part.
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
©2011–2017 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09492-0-9/17(D)
Rev. D | Page 102 of 102
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