ADUC7128 [ADI]
Precision Analog Microcontroller ARM7TDMI MCU with 12-bit ADC & DDS DAC; 精密模拟微控制器ARM7TDMI微控制器与12位ADC和DAC的DDS
| 型号： | ADUC7128 |
| 厂家： | 
ADI |
| 描述： | Precision Analog Microcontroller ARM7TDMI MCU with 12-bit ADC & DDS DAC |
| 文件： | 总92页 (文件大小：744K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Precision Analog Microcontroller
ARM7TDMI® MCU with 12-bit ADC & DDS DAC
Preliminary Technical Data
ADuC7128
Memory
FEATURES
Analog I/O
Multi-Channel, 12-bit, 1MSPS ADC
- 10 ADC channels
- Fully differential and single-ended modes
- 0 to VREF Analog Input Range
10-bit DAC
126k Bytes Flash/EE Memory, 8k Bytes SRAM
In-Circuit Download, JTAG based Debug
Software triggered in-circuit re-programmability
On-Chip Peripherals
2 x UART, 2 x I2C® and SPI Serial I/O
28-Pin GPIO Port
5 X General Purpose Timers
Wake-up and Watchdog Timers
Power Supply Monitor
- 32-bit 21MHz DDS
- Current-to-Voltage (I/V) Conversion
- Integrated 2nd order LPF
16-bit PWM generator
Quadrature Encoder
- DDS Input to DAC
PLA – Programmable Logic (Array)
Power
- 100ohm Line Driver
On-Chip Voltage Reference
Specified for 3V operation
Active Mode: 11mA (@5MHz)
45mA (@41.78 MHz)
On-Chip Temperature Sensor ( 3ꢀC)
Uncommitted Voltage Comparator
Microcontroller
Packages and Temperature Range
64 lead LFCSP (9mm x 9mm) package –40ꢀC to 85ꢀC
Tools
Low-Cost QuickStart Development System
Full Third-Party Support
ARM7TDMI Core, 16/32-bit RISC architecture
JTAG Port supports code download and debug
External Watch crystal/ Clock Source
- 41.78 MHz PLL with 8 way Programmable Divider
- Optional Trimmed On-Chip Oscillator
FUNCTIONAL BLOCK DIAGRAM
ADC0
12-BIT SAR
ADC 1MSPS
MUX
T/H
VDAC
LD1TX
10-BIT
IOUT DAC
TEMP
SENSOR
DDS
I/V
LD2TX
+
CMP0
CMP1
-
BAND GAP
REFERENCE
CMPOUT
ADuC7128
VREF
PWM1
PWM2
PWM3
PWM4
PWM5
PWM6
ARM7TDMI - BASED MCU
WITH ADDITIONAL PERIPHERALS
PWM
5 GEN PURPOSE
2 KBYTES
TIMERS
RST
POR
OSC/PLL
PSM
8192 BYTES
SRAM
64 KBYTES
FLASH/EE
62 KBYTES
FLASH/EE
WAKE-UP/
RTC TIMER
XCLKI
XCLKO
XCLK
INTERRUPT
CONTROLLER
(2k x 32 bits)
(31k x 16 bits)
(32k x 16 bits)
S1
S2
Quad
Encoder
GPIO
CONTROL
I2C
UART0 UART1
JTAG
PLA
SPI
. . .
JTAG
. . .
. . .
. . .
. . .
Figure 1. Basic Block Diagram
Rev. PrA
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infringements of patents or other rights of third parties that may result from its use.
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Tel: 781.329.4700
Fax: 781.326.8703
www.analog.com
© 2006 Analog Devices, Inc. All rights reserved.
ADuC7128
Preliminary Technical Data
GENERAL DESCRIPTION
The ADuC7128 is a fully integrated, 1MSPS, 12-bit data
acquisition system incorporating a high performance multi-
channel ADC, DDS with line driver, a 16/32-bit MCU and
Flash/EE Memory on a single chip.
The device operates from an on-chip oscillator and PLL
generating an internal high-frequency clock of 41.78 MHz. This
clock is routed through a programmable clock divider from
which the MCU core clock operating frequency is generated.
The microcontroller core is an ARM7TDMI, 16/32-bit RISC
machine, offering up to 41 MIPS peak performance. 126k Bytes
of non-volatile Flash/EE are provided on-chip as well as 8k
Bytes of SRAM. The ARM7TDMI core views all memory and
registers as a single linear array.
The ADC consists of up to 10 single-ended inputs. The ADC
can operate in single-ended or differential input modes. The
ADC input voltage is 0 to VREF. Low drift bandgap reference,
temperature sensor and voltage comparator complete the ADC
peripheral set.
On-chip factory firmware supports in-circuit serial download
via the UART and JTAG serial interface ports while non-
intrusive emulation is also supported via the JTAG interface.
These features are incorporated into a low-cost QuickStart
Development System supporting this MicroConverter family.
The ADuC7128 also integrates a differential line driver output.
This line driver transmits a sine wave whose values are
calculated by an on chip DDS or a voltage output determined by
the DACDAT MMR.
The parts operate from 3.0V to 3.6V and are specified over an
industrial temperature range of -40°C to 85°C. When operating
at 41.78 MHz the power dissipation is 150mW. The line driver
output if enabled consumes and additional 30mW.
Rev. PrA | Page 2 of 92
Preliminary Technical Data
ADUC7128—SPECIFICATIONS
ADuC7128
Table 1. (AVDD = IOVDD = 3.0 V to 3.6 V, VREF = 2.5 V Internal Reference, fCORE = 41.78MHz, All specifications TA = TMAX to
TMIN, unless otherwise noted.)
Parameter
ADuC7128
Unit
Test Conditions/Comments
ADC CHANNEL SPECIFICATIONS
ADC Powerup Time
DC Accuracy1,2
5
us
Eight acquisition clocks and Fadc/2
Resolution
12
Bits
Integral Nonlinearity
±1.5
±±.ꢀ
±2.±
+1/-±.9
±±.5
+±.7/-±.ꢀ
1
LSB max
LSB typ
LSB typ
LSB max
LSB typ
LSB typ
LSB typ
2.5V internal reference
2.5V internal reference
1.±V external reference
2.5V internal reference
2.5V internal reference
1.±V external reference
ADC input is a dc voltage
Integral Nonlinearity3
Differential Nonlinearity
Differential Nonlinearity3
DC Code Distribution
ENDPOINT ERRORS4
Offset Error
±5
±1
±5
±1
LSB max
LSB typ
LSB max
LSB typ
Offset Error Match
Gain Error
Gain Error Match
DYNAMIC PERFORMANCE
Signal-to-Noise Ratio (SNR)
Total Harmonic Distortion (THD)
Peak Harmonic or Spurious Noise
Channel-to-Channel Crosstalk
ANALOG INPUT
Fin = 1±kHz Sine Wave, fSAMPLE = 1MSPS
ꢀ9
dB typ
dB typ
dB typ
dB typ
-78
-75
-8±
Input Voltage Ranges
Differential mode5
Single-ended mode
Leakage Current
VCM±VREF/2
± to VREF
±ꢀ
±1
2±
Volts
Volts
µA max
µA typ
pF typ
Input Capacitance
ON-CHIP VOLTAGE REFERENCE
Output Voltage
During ADC Acquisition
±.47µF from VREF to AGND
2.5
±5
±4±
75
V
Accuracy
mV max
ppm/°C typ
dB typ
Ω typ
Measured at TA = 25°C
Reference Temperature Coefficient
Power Supply Rejection Ratio
Output Impedance
7±
Internal VREF Power-On Time
EXTERNAL REFERENCE INPUTꢀ
Input Voltage Range
1
ms typ
±.ꢀ25
AVDD
ꢀ5
V min
V max
KΩ typ
Input Impedance
DAC CHANNEL SPECIFICATIONS
VDAC Output
RL = 5kΩ, CL = 1±±pF
VREF is the internal 2.5V reference
V mode selected
Voltage Swing
±.33*VREF ± ±.2*VREF
5±±
I/V output resistance
Low Pass Filter 3db point
Ω max
1
1.5
2
MHz min
MHz typ
MHz max
Bits
2-pole.
Resolution
1±
Rev. PrA | Page 3 of 92
ADuC7128
Preliminary Technical Data
Parameter
ADuC7128
±2
±.25
1.5
TBD
Unit
Test Conditions/Comments
Relative Accuracy
Differential Nonlinearity, +’ve
Differential Nonlinearity, -’ve
Offset Error
LSB typ
LSB Typ
LSB Typ
mV max
mV max
mV typ
ns max
Gain Error
TBD
DDS Mode
DAC Mode
TBD
Voltage Output Settling Time to ±.1%
ꢀ±±
As measured into a range of specified loads (see
Figure 2) at PL1/LD2TX unless otherwise noted
DDS operating at ꢀ91.2kHz.
Line Driver Output
Total Harmonic Distortion
Output Voltage Swing
±.3±
TBD
% typ
% max
±1.753
±1.7ꢀ8
±1.782
TBD
V min RMS
V typ RMS
V max RMS
V typ
Common Mode
AC Mode
Each output has a common mode of ±.5*AVDD
and swings ±.5*VREF above and below this. VREF is
the internal 2.5V reference
TBD
V typ
DC Mode
Each output has a common mode of ±.5*VREF
and swings ±.5*VREF above and below this. VREF is
the internal 2.5V reference
Differential Input Impedance
1±
12.5
5
Line Driver Buffer disabled
kΩ min
kΩ typ
uA max
uA max
Leakage current LD1TX, LD2TX
Leakage current LDIN
Line Driver Buffer disabled
5
Short Circuit Current
Digital to Analog Glitch Energy
Line Driver Tx Powerup time
COMPARATOR
±5±
TBD
2±
mA
nVsec typ
µs max
I LSB change at major carry
Input Offset Voltage
Input Bias Current
±15
mV typ
µA typ
1
Input Voltage Range
AGND to AVDD-1.2
Vmin/Vmax
pF typ
Input Capacitance
7
Hysteresis3,5
2
15
1
mV min
mv max
µs typ
Hysteresis can be turned on or off via the
CMPHYST bit in the CMPCON register
Response Time
Response time may be modified via the CMPRES
bits in the CMPCON register
TEMPERATURE SENSOR
Voltage Output at 25°C
Voltage TC
78±
-1.3
±3
mV typ
mV/°C typ
°C typ
Accuracy
POWER SUPPLY MONITOR (PSM)
IOVDD Trip Point Selection
2.79
3.±7
±2.5
5±
V
V
Two selectable Trip Points
Power Supply Trip Point Accuracy
Glitch Immunity on RESET Pin3
Watchdog Timer (WDT)
% typ
µs typ
Of the selected nominal Trip Point Voltage
Timeout Period
±
ms min
s max
512
Rev. PrA | Page 4 of 92
Preliminary Technical Data
ADuC7128
Parameter
Flash/EE MEMORY7,8
ADuC7128
Unit
Test Conditions/Comments
Endurance
Data Retention
1±,±±±
2±
Cycles min
Years min
TJ = 85°C
Digital Inputs
All digital inputs including XCLKI and XCLKO
Logic 1 Input Current
(leakage Current )
Logic ± Input Current
(leakage Current )
±1
µA max
µA typ
µA max
µA typ
µA max
V
INH = VDD or VINH = 5V
±±.2
-ꢀ±
-4±
-12±
-8±
V
INL = ±V, except TDI
VINL = ±V, TDI Only
µA typ
Input Capacitance
Logic Inputs3
1±
pF typ
All Logic inputs including XCLKI and XCLKO
VINL, Input Low Voltage
VINH, Input High Voltage
Quadrature Encoder Inputs S1/S2/CLR
(Schmitt-Triggered Inputs)
VT+
±.8
2.±
V max
V min
1.9
2.1
±.9
1.1
±.9
1.1
V min
V max
V min
V max
V min
V max
VT-
VT+ -VT-
Logic Outputs9
VOH, Output High Voltage
IOVDD – 4±±mV
±.4
V min
V max
ISOURCE = 1.ꢀmA
ISINK = 1.ꢀmA
VOL, Output Low Voltage
CRYSTAL INPUTS XCLKI and XCLKO
Logic Inputs, XCLKI Only
VINL, Input Low Voltage
V
1.1
1.7
2±
VINH, Input High Voltage
XCLKI Input Capacitance
XCLKO Output Capacitance
MCU CLOCK RATE (PLL)
V
pF
pF
2±
8 programmable core clock selections within this
range.
32ꢀ.4
kHz min
MHz max
kHz typ
% max
(32.7ꢀ8kHz x 1275)/128
(32.7ꢀ8kHz x 1275)/1
41.7792±±
32.7ꢀ8
±3
INTERNAL OSCILLATOR
Tolerance
STARTUP TIME
At Power-On
Core Clock = 41.78 MHz
TBD
From Pause/Nap Mode
From Sleep Mode
TBD
TBD
TBD
From Stop Mode
Programmable Logic Array (PLA)
Pin Propagation Delay
12
ns typ
From input pin to output pin
Rev. PrA | Page 5 of 92
ADuC7128
Preliminary Technical Data
Parameter
ADuC7128
Unit
Test Conditions/Comments
Element Propagation Delay
2.5
ns typ
POWER REQUIREMENTS
Power Supply Voltage Range
IOVDD, AVDD and DACVDD
(Supply Voltage to Chip)
LVDD
3.±
3.ꢀ
2.5
2.ꢀ
2.7
V min
V max
V min
V typ
(Regulator Output from Chip)
V max
Power Supply Current1±,11
Normal Mode
15
17
42
45
3±
mA typ
mA max
mA typ
mA max
mA max
5.52MHz clock
5.52MHz clock
41.78MHz clock
41.78MHz clock
ꢀ91kHz, max load (Fig. 2)
Additional Line Driver Tx Supply
Current
Pause Mode
3±
mA max
44.2MHz clock
Sleep Mode
25±
4±±
µA typ
µA max
External Crystal or Internal Osc ON
1 All ADC channel specifications are guaranteed during normal MicroConverter core operation.
2 Apply to all ADC input channels.
3 Not production tested but supported by design and/or characterization data on production release.
4 Measured using an external AD845 op amp as an input buffer stage as shown in Figure 38. Based on external ADC system components.
5 The input signal can be centered on any dc common-mode voltage (VCM) as long as this value is within the ADC voltage input range specified.
ꢀ When using an external reference input pin, the internal reference must be disabled by setting the LSB in the REFCON memory mapped register to ±.
7 Endurance is qualified as per JEDEC Std. 22 method A117 and measured at −4±°C, +25°C, and +85°C.
8 Retention lifetime equivalent at junction temperature (Tj) = 85°C as per JEDEC Std. 22 method A117. Retention lifetime derates with junction temperature.
9 Test carried out with a maximum of 8 I/O set to a low output level.
1±Power supply current consumption is measured in normal, pause and sleep modes under the following conditions:
Normal Mode: 3.ꢀ V supply, Pause Mode: 3.ꢀ V supply, Sleep Mode: 3.ꢀ V supply
11 IOVDD power supply current decreases typically by 2 mA during a Flash/EE erase cycle.
Rev. PrA | Page ꢀ of 92
Preliminary Technical Data
ADuC7128
100nF
LD1TX
94Ω
94Ω
118Ω
27.5uH
100nF
100nF
LD2TX
LD1TX
94Ω
94Ω
57Ω
8.9uH
100nF
LD2TX
Figure 2. Line Driver Load min (top) and max (bottom)
Rev. PrA | Page 7 of 92
ADuC7128
Preliminary Technical Data
Table 2. I2C Timing in Fast Mode (400 kHz)
Slave
Parameter
tLOW
tHIGH
tHD;STA
tSU;DAT
tHD;DAT
tSU;STA
tSU;STO
tBUF
Description
Min
2±±
1±±
3±±
1±±
5±
1±±
1±±
1.3
Max
Master Typ
13ꢀ±
114±
25135±
74±
4±±
Unit
ns
ns
ns
ns
SCLOCK low pulsewidth1
SCLOCK high pulsewidth1
Start condition hold time
Data setup time
Data hold time
Setup time for repeated start
STOP condition setup time
Bus-free time between a STOP condition and a START condition
Rise time for both CLOCK and SDATA
Fall time for both CLOCK and SDATA
Pulsewidth of spike suppressed
ns
ns
12.5135±
4±±
tR
tF
tSUP
1±±
ꢀ±
3±±
1±±
5±
2±±
2±
ns
ns
ns
1 tHCLK depends on the clock divider or CD bits in PLLCON MMR. THCLK = tUCLK/2CD
.
tBUF
tSUP
tR
MSB
tF
SDATA (I/O)
MSB
LSB
ACK
tDSU
tDSU
tDHD
tDHD
tPSU
tR
tSHD
tRSU
tH
1
2–7
8
9
1
SCLK (I)
tL
tSUP
PS
S(R)
tF
STOP
START
REPEATED
START
CONDITION CONDITION
Figure 3. I2C Compatible Interface Timing
Rev. PrA | Page 8 of 92
Preliminary Technical Data
ADuC7128
Table 3. SPI Master Mode Timing (PHASE Mode = 1)
Parameter
Description
Min
Typ
Max
Unit
tSL
SCLOCK low pulsewidth1
(SPIDIV + 1) ×
tHCLK
(SPIDIV + 1) ×
tHCLK
ns
tSH
SCLOCK high pulsewidth1
ns
tDAV
Data output valid after SCLOCK edge
2 x tHCLK + 2
× tUCLK
ns
tDSU
tDHD
tDF
tDR
tSR
Data input setup time before SCLOCK edge2
Data input hold time after SCLOCK edge2
Data output fall time
Data output rise time
SCLOCK rise time
1 × tUCLK
2 × tUCLK
ns
ns
ns
ns
ns
ns
5
5
5
5
12.5
12.5
12.5
12.5
tSF
SCLOCK fall time
1 tHCLK depends on the clock divider or CD bits in PLLCON MMR. THCLK = tUCLK/2CD
.
2 tUCLK = 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider.
SCLOCK
(POLARITY = 0)
tSH
tSL
tSR
tSF
SCLOCK
(POLARITY = 1)
tDAV
tDF
tDR
MOSI
MISO
MSB
BITS 6–1
LSB
MSB IN
tDSU
BITS 6–1
LSB IN
tDHD
Figure 4. SPI Master Mode Timing (PHASE Mode = 1)
Rev. PrA | Page 9 of 92
ADuC7128
Preliminary Technical Data
Table 4. SPI Master Mode Timing (PHASE Mode = 0)
Parameter
Description
Min
Typ
Max
Unit
ns
ns
tSL
tSH
tDAV
SCLOCK low pulsewidth1
SCLOCK high pulsewidth1
Data output valid after SCLOCK edge
(SPIDIV + 1) × tHCLK
(SPIDIV + 1) × tHCLK
2 x
ns
tHCLK
2 ×
+
tUCLK
tDOSU
tDSU
tDHD
tDF
tDR
tSR
Data output setup before SCLOCK edge
Data input setup time before SCLOCK edge2
Data input hold time after SCLOCK edge2
Data output fall time
Data output rise time
SCLOCK rise time
75
ns
ns
ns
ns
ns
ns
ns
1 × tUCLK
2 × tUCLK
5
5
5
5
12.5
12.5
12.5
12.5
tSF
SCLOCK fall time
1 tHCLK depends on the clock divider or CD bits in PLLCON MMR. THCLK = tUCLK/2CD
.
2 tUCLK = 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider.
SCLOCK
(POLARITY = 0)
tSH
tSL
tSR
tSF
SCLOCK
(POLARITY = 1)
tDAV
tDOSU
tDF
tDR
MOSI
MISO
MSB
BITS 6–1
LSB
MSB IN
tDSU
BITS 6–1
LSB IN
tDHD
Figure 5. SPI Master Mode Timing (PHASE Mode = 0)
Rev. PrA | Page 1± of 92
Preliminary Technical Data
ADuC7128
Table 5. SPI Slave Mode Timing (PHASE Mode = 1)
Parameter
Description
CS to SCLOCK edge1
Min
Typ
Max
Unit
ns
tCS
2 × tUCLK
tSL
tSH
tDAV
SCLOCK low pulsewidth2
SCLOCK high pulsewidth2
Data output valid after SCLOCK edge
(SPIDIV + 1) × tHCLK
(SPIDIV + 1) × tHCLK
ns
ns
ns
2 x
tHCLK
2 ×
+
tUCLK
tDSU
tDHD
tDF
tDR
tSR
Data input setup time before SCLOCK edge1
Data input hold time after SCLOCK edge1
Data output fall time
Data output rise time
SCLOCK rise time
1 × tUCLK
2 × tUCLK
ns
ns
ns
ns
ns
ns
ns
5
5
5
5
12.5
12.5
12.5
12.5
tSF
tSFS
SCLOCK fall time
CS high after SCLOCK edge
±
1 tUCLK = 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider.
2 tHCLK depends on the clock divider or CD bits in PLLCON MMR. THCLK = tUCLK/2CD
.
CS
tSFS
tCS
SCLOCK
(POLARITY = 0)
tSH
tSL
tSR
tSF
SCLOCK
(POLARITY = 1)
tDAV
tDF
tDR
MISO
MOSI
MSB
BITS 6–1
LSB
MSB IN
BITS 6–1
LSB IN
tDSU
tDHD
Figure 6. SPI Slave Mode Timing (PHASE Mode = 1)
Rev. PrA | Page 11 of 92
ADuC7128
Preliminary Technical Data
Table 6. SPI Slave Mode Timing (PHASE Mode = 0)
Parameter
Description
CS to SCLOCK edge1
Min
Typ
Max
Unit
ns
tCS
2 × tUCLK
tSL
tSH
tDAV
SCLOCK low pulsewidth2
SCLOCK high pulsewidth2
Data output valid after SCLOCK edge
(SPIDIV + 1) × tHCLK
(SPIDIV + 1) × tHCLK
ns
ns
ns
2 x
tHCLK
2 ×
+
tUCLK
tDSU
tDHD
tDF
tDR
tSR
tSF
tDOCS
tSFS
Data input setup time before SCLOCK edge1
Data input hold time after SCLOCK edge1
Data output fall time
Data output rise time
SCLOCK rise time
SCLOCK fall time
Data output valid after CS edge
CS high after SCLOCK edge
1 × tUCLK
2 × tUCLK
ns
ns
ns
ns
ns
ns
ns
ns
5
5
5
5
12.5
12.5
12.5
12.5
25
±
1 tUCLK = 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider.
2 tHCLK depends on the clock divider or CD bits in PLLCON MMR. THCLK = tUCLK/2CD
.
Rev. PrA | Page 12 of 92
Preliminary Technical Data
ADuC7128
CS
tCS
tSFS
SCLOCK
(POLARITY = 0)
tSH
tSL
tSF
tSR
SCLOCK
(POLARITY = 1)
tDAV
tDOCS
tDF
tDR
MISO
MOSI
MSB
BITS 6–1
LSB
MSB IN
tDSU
BITS 6–1
LSB IN
tDHD
Figure 7. SPI Slave Mode Timing (PHASE Mode = 0)
Rev. PrA | Page 13 of 92
ADuC7128
Preliminary Technical Data
ABSOLUTE MAXIMUM RATINGS
TA = 25°C unless otherwise noted. DVDD = IOVDD,
AGND = REFGND = DACGND = GNDREF.
Table 7.
Parameter
Rating
AVDD to DVDD
−±.3 V to +±.3 V
Stresses above those listed under Absolute Maximum Ratings may
cause permanent damage to the device. This is a stress rating only;
functional operation of the device at these or any other conditions
above those indicated in the operational section of this specification is
not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
AGND to DGND
−±.3 V to +±.3 V
−±.3 V to +ꢀ V
IOVDD to IOGND, AVDD to AGND
Digital Input Voltage to IOGND
Digital Output Voltage to IOGND
VREF to AGND
Analog Inputs to AGND
Analog Output to AGND
−±.3 V to IOVDD + ±.3 V
−±.3 V to IOVDD + ±.3 V
−±.3 V to AVDD + ±.3 V
−±.3 V to AVDD + ±.3 V
−±.3 V to AVDD + ±.3 V
–4±°C to +85°C
Only one absolute maximum rating may be applied at any one time.
Operating Temperature Range
Industrial ADuC7128
Storage Temperature Range
Junction Temperature
–ꢀ5°C to +15±°C
125°C
24°C/W
θJA Thermal Impedance (ꢀ4-pin CSP)
Peak Solder Reflow Temperature
SnPb Assemblies (1± sec to 3± sec) 24±°C
PbFree Assemblies (2± sec to 4± sec) 2ꢀ±°C
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4±±± V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. PrA | Page 14 of 92
Preliminary Technical Data
ADuC7128
PIN FUNCTION DESCRIPTIONS - ADUC7128
Pin# Mnemonic
Type
Function
1
2
3
4
ADC5
I
I
I
I
Single-ended or differential Analog input 5 / Line Driver input
Output from DAC buffer
VDACout
ADC9
Single-ended or differential Analog input 9
Single-ended or differential Analog input 1±
ADC1±
Ground voltage reference for the ADC. For optimal performance the analog
power supply should be separated from IOGND and DGND
5
GNDREF
S
Bias point or Negative Analog Input of the ADC in pseudo differential mode.
Must be connected to the ground of the signal to convert. This bias point
must be between ±V and 1V
ꢀ
ADCNEG
I
7
8
AVDD
S
Analog Power
Single-ended or differential Analog input 12 / DAC differential negative
output
ADC12/LD1TX
I/O
9
ADC13/ LD2TX
AGND
I/O
S
Single-ended or differential Analog input 13 / DAC differential Positive output
Analog Ground. Ground reference point for the analog circuitry
JTAG Test Port Input - Test Mode Select. Debug and download access
JTAG Test Port Input – Test Data In. Debug and download access
General Purpose Input-Output Port 4.ꢀ / Serial Port Mux pin 1±
General Purpose Input-Output Port 4.7 / Serial Port Mux pin 11
1±
11
12
13
14
TMS
I
TDI
I
P4.ꢀ/SPM1±
P4.7/SPM11
I.O
I.O
General Purpose Input-Output Port ±.± /Boot Mode. The ADuC7128 will enter
download mode if BM is low at reset and will execute code if BM is pulled
high at reset through a 1kOhm resistor/ Voltage Comparator Output
15
P±.±/BM/CMPOUT
I/O
1ꢀ
17
18
19
2±
P±.ꢀ/T1/MRST
TCK
O
I
General Purpose Output Port ±.ꢀ / Timer 1 Input / Power on reset output
JTAG Test Port Input - Test Clock. Debug and download access
JTAG Test Port Output - Test Data Out. Debug and download access
Ground for GPIO. Typically connected to DGND
TDO
O
S
S
IOGND
IOVDD
3.3V Supply for GPIO and input of the on-chip voltage regulator.
2.5V. Output of the on-chip voltage regulator. Must be connected to a ±.47µF
capacitor to DGND
21
LVDD
S
22
23
24
25
2ꢀ
DGND
S
Ground for core logic.
P3.±/PWM1
P3.1/PWM2
P3.2/PWM3
P3.3/PWM4
I/O
I/O
I/O
I/O
General Purpose Input-Output Port 3.±/ PWM 1 output
General Purpose Input-Output Port 3.1/ PWM 2 output
General Purpose Input-Output Port 3.2/ PWM 3 output
General Purpose Input-Output Port 3.3/ PWM 4 output
General Purpose Input-Output Port 3.3/ ADCBUSY signal / JTAG Test Port Input
– Test Reset. Debug and download access
27
P±.3/ADCBUSY/TRST
I/O
28
29
3±
RST
I
Reset Input. (active low)
P3.4/PWM5
P3.5/PWMꢀ
I/O
I/O
General Purpose Input-Output Port 3.4/ PWM 5 output
General Purpose Input-Output Port 3.5/ PWM ꢀ output
General Purpose Input-Output Port ±.5 / External Interrupt Request ±, active
high / Start conversion input signal for ADC
31
P±.4/IRQ±/CONVST
I/O
General Purpose Input-Output Port ±.ꢀ / External Interrupt Request 1, active
high / ADCBUSY signal
32
33
34
35
3ꢀ
P±.5/IRQ1/ADCBUSY
P2.±/SPM9
I/O
I/O
I/O
O
General Purpose Input-Output Port 2.± / Serial Port Mux pin 9
General Purpose Input-Output Port ±.7 / Serial Port Mux pin 8 / Output for
External Clock signal/ Input to the internal clock generator circuits
P±.7/SPM8/ECLK/XCLK
XCLKO
Output from the crystal oscillator inverter
Input to the crystal oscillator inverter and input to the internal clock
generator circuits
XCLKI
I
2.5V.PLL supply. Must be connected to a ±.1µF capacitor to DGND Should be
connected to 2.5V LDO output.
37
PVDD
S
Rev. PrA | Page 15 of 92
ADuC7128
Preliminary Technical Data
Pin# Mnemonic
Type
Function
38
39
4±
41
42
43
44
45
4ꢀ
47
48
49
5±
51
52
53
54
DGND
S
Ground for PLL.
P1.7/SPM7
P1.ꢀ/SPMꢀ
IOGND
I/O
I/O
S
General Purpose Input-Output Port 1.7/Serial Port Mux pin 7
General Purpose Input-Output Port 1.ꢀ/Serial Port Mux pin ꢀ
Ground for GPIO. Typically connected to DGND
IOVDD
S
3.3V Supply for GPIO and input of the on-chip voltage regulator.
General Purpose Input-Output Port 4.±/ Quadrature Input 1
General Purpose Input-Output Port 4.1 / Quadrature Input 2
General Purpose Input-Output Port 1.5/Serial Port Mux pin 5
General Purpose Input-Output Port 1.4/Serial Port Mux pin 4
General Purpose Input-Output Port 1.3/Serial Port Mux pin 3
General Purpose Input-Output Port 1.2/Serial Port Mux pin 2
General Purpose Input-Output Port 1.1/Serial Port Mux pin 1
General Purpose Input-Output Port 1.±/Serial Port Mux pin ±
General Purpose Input-Output Port 4.2
P4.±/S1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
P4.1/S2
P1.5/SPM5
P1.4/SPM4
P1.3/SPM3
P1.2/SPM2
P1.1/SPM1
P1.±/SPM±
P4.2
P4.3/ PWMTRIP
P4.4
General Purpose Input-Output Port 4.3/ PWM safety cut off
General Purpose Input-Output Port 4.4
P4.5
General Purpose Input-Output Port 4.5
2.5V internal Voltage Reference. Must be connected to a ±.47uF capacitor
when using the internal reference.
55
VREF
I/O
5ꢀ
57
58
DACGND
AGND
AVDD
S
S
S
Ground for the DAC. Typically connected to AGND
Analog Ground. Ground reference point for the analog circuitry
Analog Power
Power Supply for the DAC, This must be supplied with 2.5V. This can be
connected to the LDO output.
59
DACVDD
S
ꢀ±
ꢀ1
ꢀ2
ꢀ3
ꢀ4
ADC±
I
I
I
I
I
Single-ended or differential Analog input ±
ADC1
Single-ended or differential Analog input 1
ADC2/CMP±
ADC3/CMP1
ADC4
Single-ended or differential Analog input 2/ Comparator positive input
Single-ended or differential Analog input 3/ Comparator negative input
Single-ended or differential Analog input 4
Rev. PrA | Page 1ꢀ of 92
Preliminary Technical Data
ADuC7128
TYPICAL PERFORMANCE CHARACTERISTICS
1.0
1.0
0.8
fS = 774kSPS
fS = 774kSPS
0.8
0.6
0.4
0.6
0.4
0.2
0.2
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.2
–0.4
–0.6
–0.8
–1.0
0
1000
2000
3000
4000
0
1000
2000
3000
4000
ADC CODES
ADC CODES
Figure 8. Typical INL Error, fS = 774 kSPS
Figure 11. Typical DNL Error, fs = 774 kSPS
1.0
0.8
1.0
0.8
fS = 1MSPS
fS = 1MSPS
0.6
0.6
0.4
0.4
0.2
0.2
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.2
–0.4
–0.6
–0.8
–1.0
0
1000
2000
3000
4000
0
0
1000
2000
3000
4000
ADC CODES
ADC CODES
Figure 9. Typical INL Error, fS = 1 MSPS
Figure 12. Typical DNL Error, fS = 1 MSPS
1.0
0
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
–0.7
–0.8
–0.9
–1.0
–0.2
–0.3
–0.5
–0.6
–0.7
–0.8
–0.9
–1.0
WCN
WCP
WCP
WCN
1.0
1.5
2.0
2.5
3.0
1.0
1.5
2.0
2.5
3.0
EXTERNAL REFERENCE (V)
EXTERNAL REFERENCE (V)
Figure 10. Typical Worse Case INL Error vs. VREF, fS = 774 kSPS
Figure 13. Typical Worse Case DNL Error vs. VREF, fS = 774 kSPS
Rev. PrA | Page 17 of 92
ADuC7128
Preliminary Technical Data
9000
8000
7000
6000
5000
4000
3000
2000
1000
0
75
70
65
60
55
50
45
40
–76
–78
SNR
–80
–82
THD
–84
–86
–88
1161
1162
BIN
1163
1.0
1.5
2.0
2.5
3.0
EXTERNAL REFERENCE (V)
Figure 14. Code Histogram Plot
Figure 17. Typical Dynamic Performance vs. VREF
0
–20
1500
1450
1400
1350
1300
1250
1200
1150
1100
1050
1000
fS = 774kSPS,
SNR = 69.3dB,
THD = –80.8dB,
PHSN = –83.4dB
–40
–60
–80
–100
–120
–140
–160
0
100
200
–50
0
50
100
150
FREQUENCY (kHz)
TEMPERATURE (°C)
Figure 15. Dynamic Performance, fS = 774 kSPS
Figure 18. On-Chip Temperature Sensor Voltage Output vs.
Temperature
20
0
fS = 1MSPS,
39.8
39.7
39.6
39.5
39.4
39.3
39.2
39.1
39.0
38.9
SNR = 70.4dB,
THD = –77.2dB,
PHSN = –78.9dB
–20
–40
–60
–80
–100
–120
–140
–160
0
50
100
150
200
FREQUENCY (kHz)
–40
0
25
85
125
TEMPERATURE (°C)
Figure 16. Dynamic Performance, fS = 1 MSPS
Figure 19. Current Consumption vs. Temperature @ CD = 0
Rev. PrA | Page 18 of 92
Preliminary Technical Data
ADuC7128
12.05
12.00
11.95
11.90
11.85
11.80
11.75
11.70
11.65
11.60
11.55
Current consumption in sleep mode
300
250
200
150
100
50
0
-40
25
85
125
–40
0
25
85
125
TEM PERATURE (DEGREE C)
TEMPERATURE (°C)
Figure 20. Current Consumption vs. Temperature @ CD = 3
Figure 22. Current Consumption vs. Temperature in Sleep Mode
7.85
37.4
7.80
7.75
7.70
7.65
7.60
7.55
7.50
7.45
7.40
37.2
37.0
36.8
36.6
36.4
36.2
–40
0
25
85
125
TEMPERATURE (°C)
62.25
125.00
250.00
500.00
1000.00
SAMPLING FREQUENCY (kSPS)
Figure 21. Current Consumption vs. Temperature@t CD = 7
Figure 23. Current Consumption vs. ADC Speed
Rev. PrA | Page 19 of 92
ADuC7128
Preliminary Technical Data
TERMINOLOGY
ADC SPECIFICATIONS
Integral Nonlinearity
The maximum deviation of any code from a straight line
passing through the endpoints of the ADC transfer function.
The endpoints of the transfer function are zero scale, a point
½ LSB below the first code transition and full scale, a point
½ LSB above the last code transition.
The theoretical signal to (noise + distortion) ratio for an ideal
N-bit converter with a sine wave input is given by:
Signal to (Noise + Distortion) = (6.02 N + 1.76) dB
Thus, for a 12-bit converter, this is 74 dB.
Differential Nonlinearity
The difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
Total Harmonic Distortion
The ratio of the rms sum of the harmonics to the fundamental.
DAC SPECIFICATIONS
Offset Error
The deviation of the first code transition (0000 . . . 000) to
(0000 . . . 001) from the ideal, that is, +½ LSB.
Relative Accuracy
Otherwise known as endpoint linearity, relative accuracy is a
measure of the maximum deviation from a straight line passing
through the endpoints of the DAC transfer function. It is
measured after adjusting for zero error and full-scale error.
Gain Error
The deviation of the last code transition from the ideal AIN
voltage (full scale – 1.5 LSB) after the offset error has been
adjusted out.
Voltage Output Settling Time
The amount of time it takes for the output to settle to within a
1 LSB level for a full-scale input change.
Signal to (Noise + Distortion) Ratio
The measured ratio of signal to (noise + distortion) at the
output of the ADC. The signal is the rms amplitude of the
fundamental. Noise is the rms sum of all nonfundamental
signals up to half the sampling frequency (fS∕2), excluding dc.
The ratio is dependent upon the number of quantization levels
in the digitization process; the more levels, the smaller the
quantization noise.
Rev. PrA | Page 2± of 92
Preliminary Technical Data
ADuC7128
state, the processor registers can be inspected as well as the
Flash/EE, the SRAM and the memory mapped registers.
OVERVIEW OF THE ARM7TDMI CORE
The ARM7 core is a 32-bit Reduced Instruction Set Computer
(RISC). It uses a single 32-bit bus for instruction and data. The
length of the data can be 8, 16 or 32 bits. The length of the
instruction word is 32 bits.
EXCEPTIONS
ARM supports five types of exceptions, and a privileged
processing mode for each type. The five types of exceptions are:
The ARM7TDMI is an ARM7 core with 4 additional features:
- T support for the Thumb (16 bit) instruction set.
- D support for debug
1. Normal interrupt or IRQ. This is provided to service
general-purpose interrupt handling of internal and
external events.
- M support for long multiplies
- I include the embeddedICE module to support embedded
system debugging.
2. Fast interrupt or FIQ. This is provided to service data
transfer or communication channel with low latency. FIQ
has priority over IRQ.
Thumb mode (T)
3. Memory abort.
An ARM instruction is 32-bits long. The ARM7TDMI processor
supports a second instruction set that has been compressed
into 16-bits, called the thumb instruction set. Faster execution
from 16-bit memory and greater code density can usually be
achieved by using the thumb instruction set instead of the ARM
instruction set, which makes the ARM7TDMI core particularly
suitable for embedded applications.
4. Attempted execution of an undefined instruction.
5. Software interrupt instruction (SWI). This can be used to
make a call to an operating system.
Typically, the programmer defines interrupt as IRQ, but for
higher priority interrupt, that is, faster response time, the
programmer can define interrupt as FIQ.
However, the thumb mode has two limitations:
1. Thumb code usually uses more instructions for the same
job. As a result, ARM code is usually best for maximising
the performance of the time-critical code.
ARM REGISTERS
ARM7TDMI has a total of 37 registers: 31 general purpose
registers and six status registers. Each operating mode has
dedicated banked registers.
2. The thumb instruction set does not include some of the
instructions needed for exception handling, which
automatically switches the core to ARM code for exception
handling.
When writing user-level programs, 15 general-purpose 32-bit
registers (R0 to R14), the program counter (R15) and the
current program status register (CPSR) are usable. The
remaining registers are only used for system-level programming
and for exception handling.
See the ARM7TDMI user guide for details on the core
architecture, the programming model, and both the ARM and
ARM thumb instruction sets.
When an exception occurs, some of the standard registers are
replaced with registers specific to the exception mode. All
exception modes have replacement banked registers for the
stack pointer (R13) and the link register (R14) as represented in
Figure 24. The fast interrupt mode has more registers (R8 to
R12) for fast interrupt processing. This means the interrupt
processing can begin without the need to save or restore these
registers, and thus save critical time in the interrupt handling
process.
Long Multiply (M)
The ARM7TDMI instruction set includes four extra instruc-
tions that perform 32-bit by 32-bit multiplication with 64-bit
result, and 32-bit by 32-bit multiplication-accumulation (MAC)
with 64-bit result. This result is achieved in fewer cycles than
required on a standard ARM7 core.
EmbeddedICE (I)
EmbeddedICE provides integrated on-chip support for the
core. The EmbeddedICE module contains the breakpoint
and watchpoint registers that allow code to be halted for
de-bugging purposes. These registers are controlled through
the JTAG test port.
When a breakpoint or watchpoint is encountered, the
processor halts and enters debug state. Once in a debug
Rev. PrA | Page 21 of 92
ADuC7128
Preliminary Technical Data
r0
r1
r2
r3
r4
Memory organisation
usable in user mode
system modes only
The part incorporates three separate blocks of memory, 8kByte
of SRAM and two 64kByte of On-Chip Flash/EE memory.
126kByte of On-Chip Flash/EE memory are available to the
user, and the remaining 2kBytes are reserved for the factory
configured boot page. These two blocks are mapped as shown
in Figure 25.
r5
r6
r7
r8_fiq
r9_fiq
r10_fiq
r11_fiq
r12_fiq
r13_fiq
r14_fiq
r8
r9
r10
r11
r12
r13
r14
r15 (PC)
Note that by default, after a reset, the Flash/EE memory is
mirrored at address 0x00000000. It is possible to remap the
SRAM at address 0x00000000 by clearing bit 0 of the REMAP
MMR. This remap function is described in more details in the
Flash/EE memory chapter.
r13_und
r14_und
r13_irq
r13_abt
r14_abt
r13_svc
r14_svc
r14_irq
SPSR_und
SPSR_irq
FFFFFFFFh
SPSR_abt
MMRs
SPSR_svc
CPSR
SPSR_fiq
FFFF0000h
Reserved
user mode
fiq
mode
svc
abort
irq undefined
0009F800h
mode mode
mode
mode
Flash/EE
Figure 24: register organisation
00080000h
Reserved
More information relative to the programmer’s model and the
ARM7TDMI core architecture can be found in the following
documents from ARM:
00041FFFh
SRAM
00040000h
Reserved
0001FFFFh
- DDI0029G, ARM7TDMI Technical Reference Manual.
Re-mappable Memory Space
(Flash/EE or SRAM)
- DDI0100E, ARM Architecture Reference Manual.
00000000h
Interrupt latency
The worst case latency for an FIQ consists of the longest time
the request can take to pass through the synchronizer, plus the
time for the longest instruction to complete (the longest
instruction is an LDM) which loads all the registers including
the PC, plus the time for the data abort entry, plus the time for
FIQ entry. At the end of this time, the ARM7TDMI will be
executing the instruction at 0x1C (FIQ interrupt vector
address). The maximum total time is 50 processor cycles, which
is just over 1.1µS in a system using a continuous 41.78 MHz
processor clock. The maximum IRQ latency calculation is
similar, but must allow for the fact that FIQ has higher priority
and could delay entry into the IRQ handling routine for an
arbitrary length of time. This time can be reduced to 42 cycles
if the LDM command is not used, some compilers have an
option to compile without using this command. Another option
is to run the part in THUMB mode where this is reduced to 22
cycles.
Figure 25: Physical memory map
Memory Access
32
The ARM7 core sees memory as a linear array of 2 byte
location where the different blocks of memory are mapped as
outlined in Figure 25.
The ADuC7128 memory organisation is configured in little
endian format: the least significant byte is located in the lowest
byte address and the most significant byte in the highest byte
address.
bit0
Byte0
bit31
Byte3
Byte2 Byte1
0xFFFFFFFFh
B
7
3
A
6
2
9
5
1
8
4
0
0x00000004h
0x00000000h
The minimum latency for FIQ or IRQ interrupts is five cycles in
total which consists of the shortest time the request can take
through the synchronizer plus the time to enter the exception
mode.
32 bits
Figure 26: little endian format
Note that the ARM7TDMI will always be run in ARM (32-bit)
mode when in privileged modes, i.e. when executing interrupt
service routines.
Rev. PrA | Page 22 of 92
Preliminary Technical Data
ADuC7128
0xFFFFFFFF
0xFFFF0FBC
Flash/EE Memory
0xFFFF06BC
0xFFFF0690
0xFFFF0688
0xFFFF0670
0xFFFF0544
0xFFFF0500
0xFFFF04A8
0xFFFF0480
0xFFFF0448
0xFFFF0440
0xFFFF0434
PWM
QEN
The 128kBytes of Flash/EE are organised as two banks of 32k X
16 bits. In the first block 31k X 16 bits are user space and 1k X
16 bits is reserved for the factory configured boot page.. The
page size of this Flash/EE memory is 512Bytes.
DDS
DAC
ADC
0xFFFF0F00
0xFFFF0F18
0xFFFF0F00
0xFFFF0EA8
0xFFFF0E80
The second 64kByte block is organized in a similar manner. It is
arranged in 32k x 16 bits. All of this is available as user space.
Flash Control
Interface 1
0xFFFF0E28
0xFFFF0E00
0xFFFF0D70
0xFFFF0D00
0xFFFF0C30
0xFFFF0C00
0xFFFF0B54
0xFFFF0B00
126 kBytes of Flash/EE are available to the user as code and
non-volatile data memory. There is no distinction between data
and program as ARM code shares the same space. The real
width of the Flash/EE memory is 16 bits, which means that in
ARM mode (32-bit instruction), two accesses to the Flash/EE
are necessary for each instruction fetch. It is therefore
recommended to use Thumb mode when executing from
Flash/EE memory for optimum access speed. The maximum
access speed for the Flash/EE memory is 41.78MHz in Thumb
mode and 20.89MHz in full ARM mode. More details on
Flash/EE access time are outlined later in ‘Execution from
SRAM and Flash/EE’ section of this datasheet.
Bandgap
Reference
Flash Control
Interface 0
Power Supply
Monitor
GPIO
PLL &
Oscillator Control
External Memory
0xFFFF0400
0xFFFF0394
General Purpose
Timer 4
PLA
SPI
0xFFFF0380
0xFFFF0370
0xFFFF0A14
0xFFFF0A00
0xFFFF0948
0xFFFF0900
0xFFFF0848
0xFFFF0800
0xFFFF076C
Watchdog
Timer
0xFFFF0360
0xFFFF0350
0xFFFF0340
0xFFFF0334
0xFFFF0320
0xFFFF0318
0xFFFF0300
0xFFFF0240
0xFFFF0200
0xFFFF0110
0xFFFF0000
SRAM
Wake Up
Timer
2
I C1
8kBytes of SRAM are available to the user, organized as 2k X 32
bits, i.e. 2kWords. ARM code can run directly from SRAM at
41.78MHz , given that the SRAM array is configured as a 32-bit
wide memory array. More details on SRAM access time are
outlined later in ‘Execution from SRAM and Flash/EE’ section
of this datasheet.
General Purpose
Timer
2
I C0
Timer 0
UART 1
UART 0
0xFFFF0740
0xFFFF072C
Remap &
System Control
Memory Mapped Registers
0xFFFF0700
0xFFFF06E8
The Memory Mapped Register (MMR) space is mapped into
the upper 2 pages of the memory array and accessed by indirect
addressing through the ARM7 banked registers.
Interrupt
Controller
The MMR space provides an interface between the CPU and all
on-chip peripherals. All registers except the core registers
reside in the MMR area. All shaded locations shown in Figure 6
are unoccupied or reserved locations and should not be
accessed by user software. Table 8 shows a full MMR memory
map.
Figure 27: Memory Mapped
The access time reading or writing a MMR depends on the
advanced microcontroller bus architecture (AMBA) bus used
to access the peripheral. The processor has two AMBA busses:
advanced high performance bus (AHB) used for system
modules, and advanced peripheral bus (APB) used for lower
performance peripheral. Access to the AHB is one cycle, and
access to the APB is two cycles. All peripherals on the
ADuC7128 are on the APB except the Flash/EE memory and
the GPIOs.
Rev. PrA | Page 23 of 92
ADuC7128
Preliminary Technical Data
Address Name
Byte
Access
Type
W
Page
Table 8. Complete MMRs list
Cycle
Address Name
Byte
Access
Type
Page
±x±38C
±x±39±
T4ICLR
T4CAP
1
4
2
2
Cycle
R
IRQ address base = ±xFFFF±±±±
PLL base address = ±xFFFF±4±±
±x±±±±
±x±±±4
±x±±±8
±x±±±C
±x±±1±
±x±1±±
±x±1±4
±x±1±8
±x±1±C
IRQSTA
IRQSIG
IRQEN
4
4
4
4
4
4
4
4
4
R
1
1
1
1
1
1
1
1
1
±x±4±4
±x±4±8
±x±4±C
±x±41±
±x±414
±x±418
POWKEY1
POWCON
POWKEY2
PLLKEY1
PLLCON
2
2
2
2
2
2
W
2
2
2
2
2
2
R
RW
W
RW
W
W
R
IRQCLR
SWICFG
FIQSTA
FIQSIG
FIQEN
W
RW
W
PLLKEY2
R
PSM address base = ±xFFFF±44±
RW
W
±x±44±
±x±444
PSMCON
CMPCON
2
2
RW
RW
2
2
FIQCLR
System Control address base = ±xFFFF±2±±
Reference address base = ±xFFFF±48±
±x±22±
±x±23±
±x±234
REMAP
RSTSTA
RSTCLR
1
1
1
RW
R
1
1
1
±x±48C
REFCON
1
RW
2
ADC address base = ±xFFFF±5±±
W
±x±5±±
±x±5±4
±x±5±8
±x±5±C
±x±51±
±x±514
±x±53±
±x±534
ADCCON
ADCCP
2
1
1
1
4
1
2
2
RW
RW
RW
R
2
2
2
2
2
2
2
2
Timer address base = ±xFFFF±3±±
±x±3±±
±x±3±4
±x±3±8
±x±3±C
±x±31±
±x±314
±x±32±
±x±324
±x±328
±x±32C
±x±33±
±x±34±
±x±344
±x±348
±x±34C
±x±3ꢀ±
±x±3ꢀ4
±x±3ꢀ8
±x±3ꢀC
±x±38±
±x±384
±x±388
T±LD
2
2
4
4
1
2
4
4
4
1
4
4
4
4
1
2
2
2
1
4
4
4
RW
R
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
ADCCN
ADCSTA
ADCDAT
ADCRST
ADCGN
ADCOF
T±VAL±
T±VAL1
T±CON
T±ICLR
T±CAP
T1LD
R
R
RW
W
W
RW
RW
R
RW
R
DAC and DDS address base = ±xFFFF±ꢀ7±
T1VAL
T1CON
T1ICLR
T1CAP
T2LD
±x±ꢀ7±
±x±ꢀ9±
±x±ꢀ94
±x±ꢀ98
±x±ꢀA4
±x±ꢀB4
±x±ꢀB8
±x±ꢀBC
DACCON
DDSCON
DDSFRQ
DDSPHS
DACKEY±
DACDAT
DACEN
2
1
4
2
1
2
1
1
RW
RW
RW
RW
RW
RW
RW
RW
2
2
2
2
2
2
2
2
RW
W
R
RW
R
T2VAL
T2CON
T2ICLR
T3LD
RW
W
DACKEY1
RW
R
UART 0 base address = ±xFFFF±7±±
T3VAL
T3CON
T3ICLR
T4LD
±x±7±±
COM±TX
1
1
1
1
1
1
RW
R
2
2
2
2
2
2
RW
W
COM±RX
COM±DIV±
COM±IEN±
COM±DIV1
COM±IID±
RW
RW
R/W
R
RW
R
±x±7±4
±x±7±8
T4VAL
T4CON
RW
Rev. PrA | Page 24 of 92
Preliminary Technical Data
ADuC7128
Address Name
Byte
Access
Type
RW
Page
Address Name
Byte
Access
Type
Page
Cycle
Cycle
COM±CON±
±x±7±C
±x±71±
1
1
2
2
±x±838
±x±83C
±x±84±
±x±844
±x±848
±x±84C
I2C±ID±
I2C±ID1
I2C±ID2
I2C±ID3
I2C±SSC
I2C±FIF
1
1
1
1
1
1
RW
RW
RW
RW
RW
RW
2
2
2
2
2
2
COM±CON1
RW
COM±STA±
COM±STA1
±x±714
±x±718
1
1
R
R
2
2
±x±71C
±x±72±
±x±724
±x±728
±X±72C
COM±SCR
COM±IEN1
COM±IID1
COM±ADR
COM±DIV2
1
1
1
1
2
RW
RW
R
2
2
2
2
2
I2C1 base address = ±xFFFF±9±±
±x±9±±
±x±9±4
±x±9±8
±x±9±C
±x±91±
±x±914
±x±918
±x±91C
±x±924
±x±928
±x±92C
±x±93±
±x±938
±x±93C
±x±94±
±x±944
±x±948
±x±94C
I2C1MSTA
I2C1SSTA
I2C1SRX
I2C1STX
I2C1MRX
I2C1MTX
I2C1CNT
I2C1ADR
I2C1BYT
I2C1ALT
I2C1CFG
I2C1DIV
I2C1ID±
I2C1ID1
I2C1ID2
I2C1ID3
I2C1SSC
I2C1FIF
1
1
1
1
1
1
1
1
1
1
1
2
1
1
1
1
1
1
R
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
RW
RW
R
R
UART 1 base address = ±xFFFF±74±
W
±x±74±
COM1TX
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
RW
R
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
R
COM1RX
W
COM1DIV±
COM1IEN±
COM1DIV1
COM1IID±
COM1CON±
COM1CON1
COM1STA±
COM1STA1
RW
RW
R/W
R
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
±x±744
±x±748
±x±74C
±x±75±
±x±754
±x±758
±x±75C
±x±7ꢀ±
±x±7ꢀ4
±x±7ꢀ8
±X±7ꢀC
RW
RW
R
R
COM1SCR
COM1IEN1
COM1IID1
COM1ADR
COM1DIV2
RW
RW
R
RW
RW
SPI base address = ±xFFFF±A±±
I2C0 base address = ±xFFFF±8±±
±x±A±±
±x±A±4
±x±A±8
±x±A±C
±x±A1±
SPISTA
SPIRX
1
1
1
1
2
R
2
2
2
2
2
±x±8±±
±x±8±4
±x±8±8
±x±8±C
±x±81±
±x±814
±x±818
±x±81C
±x±824
±x±828
±x±82C
±x±83±
I2C±MSTA
I2C±SSTA
I2C±SRX
I2C±STX
I2C±MRX
I2C±MTX
I2C±CNT
I2C±ADR
I2C±BYT
I2C±ALT
I2C±CFG
I2C±DIV
1
1
1
1
1
1
1
1
1
1
1
2
R
2
2
2
2
2
2
2
2
2
2
2
2
R
R
SPITX
W
R
SPIDIV
SPICON
RW
RW
W
R
PLA base address = ±xFFFF±B±±
W
±x±B±±
±x±B±4
±x±B±8
±x±B±C
±x±B1±
±x±B14
PLAELM±
PLAELM1
PLAELM2
PLAELM3
PLAELM4
PLAELM5
2
2
2
2
2
2
RW
RW
RW
RW
RW
RW
2
2
2
2
2
2
RW
RW
RW
RW
RW
RW
Rev. PrA | Page 25 of 92
ADuC7128
Preliminary Technical Data
Address Name
Byte
Access
Type
Page
Address Name
Byte
Access
Type
Page
Cycle
Cycle
±x±B18
±x±B1C
±x±B2±
±x±B24
±x±B28
±x±B2C
±x±B3±
±x±B34
±x±B38
±x±B3C
±x±B4±
±x±B44
±x±B48
±x±B4C
±x±B5±
PLAELMꢀ
2
2
2
2
2
2
2
2
2
2
1
4
4
4
4
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
R
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
±x±Dꢀ8
±x±DꢀC
GP4CLR
GP4PAR
1
1
W
W
1
1
PLAELM7
PLAELM8
PLAELM9
PLAELM1±
PLAELM11
PLAELM12
PLAELM13
PLAELM14
PLAELM15
PLACLK
Flash/EE Block 0 base address = ±xFFFF±E±±
±x±E±±
±x±E±4
±x±E±8
±x±E±C
±x±E1±
±x±E18
±x±E1C
±x±E2±
FEE±STA
FEE±MOD
FEE±CON
FEE±DAT
FEE±ADR
FEE±SGN
FEE±PRO
FEE±HID
1
1
1
2
2
3
4
4
R
1
1
1
1
1
1
1
1
RW
RW
RW
RW
R
RW
RW
PLAIRQ
Flash/EE Block 1 base address = ±xFFFF±E8±
PLAADC
±x±E8±
±x±E84
±x±E88
±x±E8C
±x±E9±
±x±E98
±x±E9C
±x±EA±
FEE1STA
FEE1MOD
FEE1CON
FEE1DAT
FEE1ADR
FEE1SGN
FEE1PRO
FEE1HID
1
1
1
2
2
3
4
4
R
1
1
1
1
1
1
1
1
PLADIN
RW
RW
RW
RW
R
PLAOUT
GPIO base address = ±xFFFF±D±±
±x±D±±
±x±D±4
±x±D±8
±x±D±C
±x±D1±
±x±D2±
±x±D24
±x±D28
±x±D2C
±x±D3±
±x±D34
±x±D38
±x±D3C
±x±D4±
±x±D44
GP±CON
GP1CON
GP2CON
GP3CON
GP4CON
GP±DAT
GP±SET
GP±CLR
GP±PAR
GP1DAT
GP1SET
GP1CLR
GP1PAR
GP2DAT
GP2SET
4
4
4
4
4
4
1
1
4
4
1
1
4
4
1
RW
RW
RW
RW
RW
RW
W
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
RW
RW
QEN base address= ±xFFFF±F±±
±x±F±±
±x±F±4
±x±F±8
±x±F±C
±x±F14
±x±F18
QENCON
QENSTA
QENDAT
QENVAL
QENCLR
QENSET
2
1
2
2
1
1
RW
R
2
2
2
2
2
2
W
RW
R
RW
RW
W
W
W
W
PWM base address= ±xFFFF±F8±
PWMCON1
RW
RW
W
±x±F8±
±x±F84
±x±F88
±x±F8C
±x±F9±
±x±F94
±x±F98
±x±F9C
±x±FA±
±x±FA4
2
2
2
2
2
2
2
2
2
2
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
2
2
2
2
2
2
2
2
2
2
PWM1COM1
PWM1COM2
PWM1COM3
PWM1LEN
±x±D48
±x±D5±
±x±D54
±x±D58
±x±D5C
±x±Dꢀ±
±x±Dꢀ4
GP2CLR
GP3DAT
GP3SET
GP3CLR
GP3PAR
GP4DAT
GP4SET
1
4
1
1
4
4
1
W
1
1
1
1
1
1
1
RW
W
PWM2COM1
PWM2COM2
PWM2COM3
PWM2LEN
W
RW
RW
W
PWM3COM1
Rev. PrA | Page 2ꢀ of 92
Preliminary Technical Data
ADuC7128
Address Name
Byte
Access
Page
Type
RW
RW
RW
RW
W
Cycle
PWM3COM2
±x±FA8
±x±FAC
±x±FB±
±x±FB4
±x±FB8
2
2
2
2
2
2
2
2
2
2
PWM3COM3
PWM3LEN
PWMCON2
PWMICLR
The ‘Access’ column corresponds to the access time reading or
writing a MMR. It depends on the AMBA (Advanced
Microcontroller Bus Architecture) bus used to access the
peripheral. The processor has two AMBA busses, AHB
(Advanced High-performance Bus) used for system modules
and APB (Advanced Peripheral Bus) used for lower
performance peripheral.
Rev. PrA | Page 27 of 92
ADuC7128
Preliminary Technical Data
temperature sensor channel, measuring die temperature to an
accuracy of ±3°C.
ADC CIRCUIT INFORMATION
GENERAL OVERVIEW
ADC TRANSFER FUNCTION
The Analog Digital Converter (ADC) incorporates a fast, multi-
channel, 12-bit ADC. It can operate from 3.0V to 3.6V supplies
and is capable of providing a throughput of up to 1MSPS when
the clock source is 41.78MHz. This block provides the user with
multi-channel multiplexer, differential track-and-hold, on-chip
reference and ADC.
Pseudo-differential and single-ended modes
In pseudo-differential or single-ended mode, the input range is
0 V to VREF. The output coding is straight binary in pseudo
differential and single-ended modes with:
1 LSB = FS/4096 or
The ADC consists of a 12-bit successive-approximation
converter based around two capacitor DACs. Depending on the
input signal configuration, the ADC can operate in one of three
different modes
2.5 V/4096 = 0.61 mV or
610 µV when VREF = 2.5 V
The ideal code transitions occur midway between successive
integer LSB values (i.e. 1/2 LSB, 3/2 LSBs, 5/2 LSBs, . . ., FS –3/2
LSBs). The ideal input/output transfer characteristic is shown in
Figure 29.
1. Fully differential mode, for small and balanced signals.
2. Single-ended mode, for any single-ended signals.
OUTPUT
CODE
3. Pseudo differential mode, for any single-ended signals,
taking advantage of the common mode rejection offered by
the pseudo differential input.
1111 1111 1111
1111 1111 1110
1111 1111 1101
The converter accepts an analog input range of 0 to VREF when
operating in single-ended mode or pseudo-differential mode. In
fully differential mode, the input signal must be balanced
around a common mode voltage VCM, in the range 0V to AVDD
and with a maximum amplitude of 2 VREF (see Figure 28).
1111 1111 1100
FS
1LSB =
4096
0000 0000 0011
0000 0000 0010
0000 0000 0001
0000 0000 0000
AV
DD
V
2V
CM
0V 1LSB
REF
+FS - 1LSB
VOLTAGE INPUT
V
2V
CM
REF
Figure 29: ADC transfer function in pseudo differential mode or single-ended
mode
V
2V
CM
REF
0
Fully differential mode
The amplitude of the differential signal is the difference
between the signals applied to the VIN+ and VIN– pins (i.e., VIN+ –
VIN–). The maximum amplitude of the differential signal is
therefore –VREF to +VREF p-p (i.e. 2 X VREF). This is regardless of
the common mode (CM). The common mode is the average of
the two signals, i.e. (VIN+ + VIN–)/2 and is therefore the voltage
that the two inputs are centred on. This results in the span of
each input being CM ± VREF/2. This voltage has to be set up
externally and its range varies with VREF, (see driving the ADC).
Figure 28: examples of balanced signals for fully differential mode
A high precision, low drift, and factory calibrated 2.5 V
reference is provided on-chip. An external reference can also be
connected as described later in the Bandgap Reference section.
Single or continuous conversion modes can be initiated in
software. An external
pin, an output generated from
CONVSTART
the on-chip PLA or a Timer0 or a Timer1 overflow can also be
used to generate a repetitive trigger for ADC conversions.
The output coding is two’s complement in fully differential
mode with 1 LSB = 2VREF/4096 or 2x2.5 V/4096 = 1.22 mV
when VREF = 2.5 V. The output result is +/- 11 bits but this is
shifted by one to the right. This allows the result in ADCDAT to
be declared as a signed integer when writing ‘c’ code. The
designed code transitions occur midway between successive
integer LSB values (i.e., 1/2 LSB, 3/2 LSBs, 5/2 LSBs, . . ., FS –3/2
LSBs). The ideal input/output transfer characteristic is shown in
Figure 30.
If the signal has not been de asserted by the time the ADC
conversion is complete then a second conversion will begin
automatically.
A
voltage output from an on-chip bandgap reference
proportional to absolute temperature can also be routed
through the front end ADC multiplexer, effectively an
additional ADC channel input. This facilitates an internal
Rev. PrA | Page 28 of 92
Preliminary Technical Data
ADuC7128
ACQ
BIT TRIAL
WRITE
OUTPUT
SIGN BIT
CODE
ADC CLOCK
0
0
1111 1111 1110
1111 1111 1100
1111 1111 1010
2x
V
REF
1LSB =
4096
0
CONVT
START
0
0
1
0000 0000 0001
0000 0000 0000
1111 1111 1110
ADC
BUSY
DATA
ADCDAT
1
1
1
0000 0000 0100
0000 0000 0010
0000 0000 0000
ADCSTA = 0
ADCSTA = 1
ADC INTERRUPT
-V
+ 1LSB
0LSB
+V
- 1LSB
REF
REF
Figure 32. ADC Timing
VOLTAGE INPUT (Vin+ - Vin-)
Figure 30: ADC transfer function in differential mode
ADC MMRS interface
TYPICAL OPERATION
The ADC is controlled and configured via a number of MMRs
that are listed below and described in detail in the following
pages:
Once configured via the ADC control and channel selection
registers, the ADC will convert the analog input and provide a
11-bit result in the ADC data register.
- ADCCON: ADC Control Register allows the programmer to
enable the ADC peripheral, to select the mode of operation of
the ADC, either Single-ended, pseudo-differential or fully
differential mode and the conversion type. This MMR is
described Table 9.
The top 4 bits are the sign bits and the 11-bit result is placed
from bit 16 to 27 as shown in Figure 31. Again, it should be
noted that in fully differential mode, the result is represented in
two’s complement format shifted one bit to the right , and in
pseudo differential and single-ended mode, the result is
represented in straight binary format.
- ADCCP: ADC positive Channel selection Register
- ADCCN: ADC negative Channel selection Register
ADCSTA: ADC Status Register, indicates when an ADC
conversion result is ready. The ADCSTA register contains
only one bit, ADCReady, bit (bit 0), representing the status of
the ADC. This bit is set at the end of an ADC conversion
generating an ADC interrupt, it is cleared automatically by
reading the ADCDAT MMR. When the ADC is performing a
conversion, the status of the ADC can be read externally via
the ADCBusy pin. This pin is high during a conversion.
When the conversion is finished, ADCBusy goes back low.
This information can be available on P0.5 (see chapter on
GPIO) if enabled in GP0CON register.
31
27
16 15
0
SIGN BITS
12-bit ADC RESULT
Figure 31: ADC Result Format
Timing
Figure 32 gives details of the ADC timing. Users have control on
the ADC clock speed and on the number of acquisition clock in
the ADCCON MMR. By default, the acquisition time is eight
clocks and the clock divider is two. The number of extra clocks
(such as bit trial or write) is set to 19, which gives a sampling
rate of 819 kSPS. For conversion on temperature sensor, the
ADC acquisition time is automatically set to 16 clocks and the
ADC clock divider to 32.
ADCDAT: ADC Data Result Register, hold the 12-bit ADC
result as shown Figure 31
- ADCRST: ADC Reset Register. Resets all the ADC registers
to their default value.
Rev. PrA | Page 29 of 92
ADuC7128
Preliminary Technical Data
Table 9: ADCCON MMR Bit Designations
Bit
Description
12-
1±
ADC Speed (Fadc = Fcore, conversion = 14 ADC clocks + Acquisition time)
±±± – Fadc / 1
±±1 – Fadc / 2
±1± – Fadc / 4
±11 – Fadc / 8
1±± – Fadc / 1ꢀ
1±1 – Fadc / 32
9-8
ADC Acquisition Time (number of ADC clocks)
±± – 2
±1 – 4
1± – 8
11 – 1ꢀ
7
Enable Conversion
Set by the user to enable conversion mode
Cleared by the user to disable conversion mode
Reserved
ꢀ
5
This bit should be set to 0 by the user.
ADC power control:
Set by the user to place the ADC in normal mode, the ADC must be powered up for at least 5±±uS before it will convert
correctly.
Cleared by the user to place the ADC in power-down mode
4-3
2-±
Conversion Mode:
±±
±1
1±
11
Single Ended Mode
Differential Mode
Pseudo-Differential Mode
Reserved
Conversion Type:
±±±
±±1
±1±
±11
Enable CONVSTART pin as a conversion input
Enable timer 1 as a conversion input
Enable timer ± as a conversion input
Single software conversion, will be set to ±±± after conversion.
(Bit 7 of ADCCON MMR should be cleared after starting a single software conversion to avoid further
conversions triggered by the CONVSTART pin).
Rev. PrA | Page 3± of 92
Preliminary Technical Data
ADuC7128
1±±
Continuous software conversion
PLA conversion
1±1
11±
PWM conversion
Reserved
Other
Table 10: ADCCP* MMR bit designation
Table 11: ADCCN* MMR bit designation
Bit
7-5
4-±
Description
Bit
7-5
4-±
Description
Reserved
Reserved
Positive Channel Selection Bits
±±±±± ADC±
Negative Channel Selection Bits
±±±±± ADC±
±±±±1 ADC1
±±±±1 ADC1
±±±1± ADC2
±±±1± ADC2
±±±11 ADC3
±±±11 ADC3
±±1±± ADC4
±±1±± ADC4
±±1±1 ADC5
±±1±1 ADC5
±±11± ADCꢀ
±±11± ADCꢀ
±±111 ADC7
±±111 ADC7
±1±±± ADC8
±1±±± ADC8
±1±±1 ADC9
±1±±1 ADC9
±1±1± ADC1±
±1±11 ADC11
±11±± ADC12/LD2TX
±11±1 ADC13/LD1TX
±111± Reserved
±1111 Reserved
1±±±± Temperature sensor
1±±±1 AGND
±1±1± ADC1±
±1±11 ADC11
±11±± ADC12/LD2TX
±11±1 ADC13/LD1TX
±111± Reserved
±1111 Reserved
1±±±± Temperature sensor
Others Reserved
1±±1± Reference
1±±11 AVDD/2
* ADC channel availability depends on part model.
Others Reserved
Since ADC12 and ADC13 are shared with the Line Driver TX
pins a high level of crosstalk will be seen on these pins when
used in ADC mode.
Rev. PrA | Page 31 of 92
ADuC7128
Preliminary Technical Data
Pseudo-differential mode
CONVERTER OPERATION
In pseudo-differential mode, Channel- is linked to the VIN- pin
of the ADuC7128 and SW2 switches between A (Channel-) and
B (VREF). VIN- pin must be connected to Ground or a low
voltage. The input signal on VIN+ can then vary from VIN- to
VREF + VIN-. Note VIN- must be chosen so that VREF + VIN- does
not exceed AVDD.
The ADC incorporates a successive approximation (SAR)
architecture involving a charge-sampled input stage. This
architecture is described below for the three different modes of
operation.
Differential mode
CAPACITIVE
The ADuC7128 contains a successive approximation ADC
based on two capacitive DACs. Figure 33 and Figure 34 show
simplified schematics of the ADC in acquisition and conversion
phase, respectively. The ADC is comprised of control logic, a
SAR, and two capacitive DACs. In Figure 33 (the acquisition
phase), SW3 is closed and SW1 and SW2 are in Position A, the
comparator is held in a balanced condition, and the sampling
capacitor arrays acquire the differential signal on the input.
AIN0
DAC
COMPARATOR
C
s
B
A
Channel+
MUX
SW1
SW2
CONTROL
LOGIC
SW3
A
B
AIN11
VIN-
C
s
VREF
CAPACITIVE
DAC
Channel-
CAPACITIVE
DAC
Figure 35: ADC in pseudo-differential mode
AIN0
COMPARATOR
C
s
B
A
Channel+
Channel-
Single-ended mode
SW1
SW2
CONTROL
LOGIC
MUX
SW3
In Single-ended mode, SW2 is always connected internally to
ground. The VIN- pin can be floating. The input signal range on
A
B
C
s
VREF
AIN11
VIN+ is 0V to VREF
.
CAPACITIVE
DAC
CAPACITIVE
DAC
AIN0
Figure 33: ADC acquisition phase
COMPARATOR
C
s
B
A
Channel+
MUX
SW1
When the ADC starts a conversion (Figure 34), SW3 will open
and SW1 and SW2 will move to Position B, causing the
comparator to become unbalanced. Both inputs are
disconnected once the conversion begins. The control logic and
the charge redistribution DACs are used to add and subtract
fixed amounts of charge from the sampling capacitor arrays to
bring the comparator back into a balanced condition. When the
comparator is rebalanced, the conversion is complete. The
control logic generates the ADC’s output code. The output
impedances of the sources driving the VIN+ and VIN– pins must
be matched; otherwise, the two inputs will have different
settling times, resulting in errors.
CONTROL
LOGIC
SW3
Channel-
AIN11
VIN-
C
s
CAPACITIVE
DAC
Figure 36: ADC in single-ended mode
Analog Input Structure
Figure 37 shows the equivalent circuit of the analog input
structure of the ADC. The four diodes provides ESD protection
for the analog inputs. Care must be taken to ensure that the
analog input signals never exceed the supply rails by more than
300 mV. This would cause these diodes to become forward
biased and start conducting into the substrate. These diodes can
conduct up to 10 mA without causing irreversible damage to
the part.
CAPACITIVE
DAC
AIN0
COMPARATOR
C
s
B
A
Channel+
Channel-
SW1
SW2
CONTROL
LOGIC
MUX
SW3
A
B
C
s
V
REF
The capacitors C1 in Figure 37 are typically 4 pF and can
primarily be attributed to pin capacitance. The resistors are
lumped components made up of the ON resistance of the
AIN11
CAPACITIVE
DAC
switches. The value of these resistors is typically about 100 Ω
The capacitors, C2, are the ADC’s sampling capacitors and
.
Figure 34: ADC conversion phase
have a capacitance of 16 pF typically.
Rev. PrA | Page 32 of 92
Preliminary Technical Data
ADuC7128
THD will increase as the source impedance increases and the
performance will degrade.
AV
D
DD
C2
R1
DRIVING THE ANALOG INPUTS
D
C1
Internal or external reference can be used for the ADC. In
differential mode of operation, there are restrictions on
common mode input signal (VCM) that are dependant on
reference value and supply voltage used to ensure that the signal
remains within the supply rails. Table 12 gives some calculated
VCM min VCM max for some conditions.
AV
D
DD
C2
R1
D
C1
Table 12: VCM ranges
AVDD
VREF
V
CM min
VCM max
Signal
Peak-Peak
Figure 37: Equivalent Analog Input Circuit
Conversion Phase: Switches Open
Track Phase: Switches Closed
3.3V
2.5V
1.25V
1.024V
0.75V
1.25V
1.024V
0.75V
2.05V
2.276V
2.55V
1.75V
1.976V
2.25V
2.5V
2.048V
1.25
2.048V
1.25
For AC applications, removing high-frequency components
from the analog input signal is recommended by the use of an
RC low-pass filter on the relevant analog input pins. In
applications where harmonic distortion and signal-to-noise
ratio are critical, the analog input should be driven from a low
impedance source. Large source impedances will significantly
affect the AC performance of the ADC. This may necessitate
the use of an input buffer amplifier. The choice of the op amp
will be a function of the particular application. Figure 38 and
Figure 39 give an example of ADC front end.
3.0V
2.5V
2.5V
2.048V
1.25
2.048V
1.25
TEMPERATURE SENSOR
The ADuC7128 provides a voltage output from an on-chip
bandgap reference proportional to absolute temperature. It can
also be routed through the front end ADC multiplexer
(effectively an additional ADC channel input) facilitating an
internal temperature sensor channel, measuring die
temperature to an accuracy of ±3°C.
ADuC7229
10Ω
ADC0
0.01µ F
BANDGAP REFERENCE
The ADuC7128 provides an on-chip bandgap reference of 2.5V,
which can be used for the ADC and for the DAC. This internal
reference also appears on the VREF pin. When using the internal
reference, a capacitor of 0.47µF must be connected from the
external VREF pin to AGND, to ensure stability and fast response
during ADC conversions. This reference can also be connected
to an external pin (VREF) and used as a reference for other
circuits in the system. An external buffer would be required
because of the low drive capability of the VREF output. A
programmable option also allows an external reference input on
the VREF pin.
Figure 38. Buffering Single-Ended/Pseudo Differential Input
ADuC7229
ADC0
Vref
ADC1
The bandgap reference interface consists on a 8-bit MMR,
REFCON described in the following table.
Figure 39. Buffering Differential Inputs
When no amplifier is used to drive the analog input, the source
impedance should be limited to values lower than 1 kΩ . The
maximum source impedance will depend on the amount of
total harmonic distortion (THD) that can be tolerated. The
Rev. PrA | Page 33 of 92
ADuC7128
Preliminary Technical Data
Table 13: REFCON MMR bit designations
Bit
7-2
1
Description
Reserved
Internal reference powerdown enable
Set by user to place the internal reference in power-
down mode and use an external reference
Cleared by user to place the internal reference in
normal mode and use it for ADC conversions
Internal reference output enable
0
Set by user to connect the internal 2.5V reference to the
VREF pin. The reference can be used for external
component but will need to be buffered.
Cleared by user to disconnect the reference from the
VREF pin.
Note: The on chip DAC is only functional with the
internal reference output enable bit set. It will not work
with an external reference.
Rev. PrA | Page 34 of 92
Preliminary Technical Data
ADuC7128
code download and debug. An application note is available at
www.analog.com/microconverter describing the protocol via
JTAG.
NONVOLATILE FLASH/EE MEMORY
FLASH/EE MEMORY OVERVIEW
It is possible to write to a single Flash/EE location address
twice. If a single address is written to more than twice, then the
data within the Flash/EE memory could be corrupted. That is, it
is possible to walk zeros only byte wise.
The ADuC7128 incorporates Flash/EE memory technology on-
chip to provide the user with non-volatile, in-circuit
reprogrammable memory space.
Like EEPROM, Flash memory can be programmed in-system at
a byte level, although it must first be erased. The erase is
performed in page blocks. As a result, flash memory is often
and more correctly referred to as Flash/EE memory.
FLASH/EE MEMORY SECURITY
The 126 kB of Flash/EE memory available to the user can be
read and write protected.
Overall, Flash/EE memory represents a step closer to the ideal
memory device that includes non-volatility, in-circuit
programmability, high density, and low cost. Incorporated in
the ADuC7128, Flash/EE memory technology allows the user to
update program code space in-circuit, without the need to
replace one time programmable (OTP) devices at remote
operating nodes.
Bit 31 of the FEE0PRO/FEE0HID MMR protects the 126 kB
from being read through JTAG and also in parallel
programming mode. The other 31 bits of this register protect
writing to the flash memory; each bit protects 4 pages, that is, 2
kB. Write protection is activated for all type of access. FEE1PRO
and FEE1HID similarly protect the second 64kB block. All 32
bits of this are used to protect 4 pages at a time.
FLASH/EE MEMORY AND THE ADUC7128
Three Levels of Protection
The ADuC7128 contains two 64 kByte arrays of Flash/EE
Memory. In the first block the lower 62 Kbytes is available to the
user and the upper 2 kBytes of this Flash/EE program memory
array contain permanently embedded firmware, allowing in
circuit serial download. These 2 Kbytes of embedded firmware
also contain a power-on configuration routine that downloads
factory calibrated coefficients to the various calibrated
peripherals (bandgap references and so on). This 2 kByte
embedded firmware is hidden from user code. It is not possible
for the user to read, write or erase this page. In the second block
all 64kB of Flash/EE memory are available to the user.
1. Protection can be set and removed by writing directly into
FEExHID MMR. This protection does not remain after reset.
2. Protection can be set by writing into FEExPRO MMR. It
only takes effect after a save protection command (0×0C)
and a reset. The FEExPRO MMR is protected by a key to
avoid direct access. The key is saved once and must be
entered again to modify FEExPRO. A mass erase sets the
key back to 0×FFFF but also erases all the user code.
3. The Flash can be permanently protected by using the
FEEPRO MMR and a particular value of key:
0×DEADDEAD. Entering the key again to modify the
FEExPRO register is not allowed
The 126kBytes of Flash/EE memory can be programmed in-
circuit, using the serial download mode or the JTAG mode
provided.
Sequence to Write the Key
(1) Serial Downloading (In-Circuit Programming)
1. Write the bit in FEExPRO corresponding to the page to be
protected.
The ADuC7128 facilitates code download via the standard
UART serial port or via the I2C port. The ADuC7128 enters
serial download mode after a reset or power cycle if the BM pin
is pulled low through an external 1kOhm resistor. Once in serial
download mode, the user can download code to the full
126kBytes of Flash/EE memory while the device is in circuit in
its target application hardware. A PC serial download
executable is provided as part of the development system for
serial downloading via the UART. An application note is
available at www.analog.com/microconverter describing the
protocol for serial downloading via the UART and I2C.
2. Enable key protection by setting Bit 6 of FEExMOD (Bit 5
must be = 0).
3. Write a 32-bit key in FEExADR, FEExDAT.
4. Run the write key command 0×0C in FEExCON; wait for
the read to be successful by monitoring FEExSTA.
5. Reset the part.
To remove or modify the protection, the same sequence is
used with a modified value of FEExPRO. If the key chosen is
the value 0×DEAD, then the memory protection cannot be
removed. Only a mass erase unprotects the part, but it also
(2) JTAG access
The JTAG protocol uses the on-chip JTAG interface to facilitate
Rev. PrA | Page 35 of 92
ADuC7128
Preliminary Technical Data
erases all user code.
FEE1DAT Register
Name
Address
Default Value
Access
The sequence to write the key is illustrated in the following
example; this protects writing pages 4 to 7 of the Flash:
FEE1DAT
±xFFFF±E8C
±xXXXX
RW
FEE1DAT is a 16-bit data register.
FEE0PRO=0xFFFFFFFD; //Protect pages 4
to 7
FEE1ADR Register
FEE0MOD=0x48;
FEE0ADR=0x1234;
FEE0DAT=0x5678;
FEE0CON= 0x0C;
command
//Write key enable
//16 bit key value
//16 bit key value
// Write key
Name
Address
±xFFFF±E9±
Default Value
±x±±±±
Access
FEE1ADR
RW
FEE1ADR is another 16-bit address register.
The same sequence should be followed to protect the part
permanently with FEEADR = 0×DEAD and FEEDAT =
0×DEAD.
FEE1SGN Register
Name
Address
Default Value
Access
FEE1SGN
±xFFFF±E98
±xFFFFFF
R
FEE1SGN is a 24-bit code signature.
FLASH/EE CONTROL INTERFACE
FEE1PRO Register
FEE0DAT Register
Name
Address
±xFFFF±E9C
Default Value
±x±±±±±±±±
Access
Name
Address
Default Value
Access
FEE1PRO
RW
FEE±DAT
±xFFFF±E±C
±xXXXX
RW
FEE1PRO provides immediate protection MMR. It does not
require any software keys. See description in Table 17.
FEE0DAT is a 16-bit data register.
FEE0ADR Register
FEE1HID Register
Name
Address
±xFFFF±E1±
Default Value
±x±±±±
Access
Name
Address
Default Value
Access
FEE±ADR
RW
FEE1HID
±xFFFF±EA±
±xFFFFFFFF
RW
FEE0ADR is another 16-bit address register.
FEE1HID provides protection following subsequent reset
MMR. It requires a software key. See description in Table 18.
FEE0SGN Register
Name
Address
Default Value
Access
FEE±SGN
±xFFFF±E18
±xFFFFFF
R
FEE0SGN is a 24-bit code signature.
FEE0PRO Register
Name
Address
±xFFFF±E1C
Default Value
±x±±±±±±±±
Access
FEE±PRO
RW
FEE0PRO provides immediate protection MMR. It does not
require any software keys. See description in Table 17.
FEE0HID Register
Name
Address
Default Value
Access
FEE±HID
±xFFFF±E2±
±xFFFFFFFF
RW
FEE0HID provides protection following subsequent reset
MMR. It requires a software key. See description in Table 18.
Command Sequence for Executing a Mass Erase
FEE0DAT=0x3CFF;
FEE0ADR = 0xFFC3;
FEE0MOD= FEE0MOD|0x8; //Erase key enable
FEE0CON=0x06;
//Mass erase command
Rev. PrA | Page 3ꢀ of 92
Preliminary Technical Data
ADuC7128
Table 14: FEExSTA MMR bit designations
Bit
15-ꢀ
5
Description
Reserved
Burst command enable
Set when the command is a burst command: ±x±7, ±x±8 or ±x±9
Cleared when other command
Reserved
4
3
Flash interrupt status bit
Set automatically when an interrupt occurs, i.e. when a command is complete and the Flash/EE interrupt enable bit in the
FEExMOD register is set
Cleared when reading FEExSTA register
Flash/EE controller busy
2
1
±
Set automatically when the controller is busy
Cleared automatically when the controller is not busy
Command fail
Set automatically when a command completes unsuccessfully
Cleared automatically when reading FEExSTA register
Command complete
Set by MicroConverter when a command is complete
Cleared automatically when reading FEExSTA register
Table 15: FEExMOD MMR bit designations
Bit
7-5
4
Description
Reserved
Flash/EE interrupt enable:
Set by user to enable the Flash/EE interrupt. The interrupt will occur when a command is complete.
Cleared by user to disable the Flash/EE interrupt
3
Erase/write command protection. Set by user to enable the erase and write commands.
Clear to protect the Flash against erase/write command.
2
Reserved
1-±
Flash waitstates, when the kernel exits this with be set to 1. The user should first switch to the external 32kHz crystal
before setting the waitstates to ±. Both flash blocks must have the same wait state value for any change to take effect.
Table 16: command codes in FEExCON
Code
±x±±*
±x±1*
±x±2*
±x±3*
command
Null
Single Read
Single Write
Erase-Write
Description
Idle state
Load FEExDAT with the 1ꢀ-bit data indexed by FEExADR
Write FEExDAT at the address pointed by FEExADR. This operation takes 2±µs.
Erase the page indexed by FEExADR and write FEExDAT at the location pointed by FEExADR. This
operation takes 2±ms
Single Verify
Compare the contents of the location pointed by FEExADR to the data in FEExDAT. The result of the
comparison is returned in FEExSTA bit 1
±x±4*
Single Erase
Mass erase
Erase the page indexed by FEExADR
±x±5*
±x±ꢀ*
Erase user space. The 2kByte of kernel are protected in block ±. This operation takes 2.48s To prevent
accidental execution a command sequence is required to execute this instruction, this is described below.
Default command. No write is allowed. This operation takes 2 cycles
Write can handle a maximum of 8 data of 1ꢀ bits and takes a maximum of 8 x 2± µs
±x±7
±x±8
Burst read
Burst read-
write
±x±9
Erase Burst
read-write
Will automatically erase the page indexed by the write, allow to write pages without running an erase
command. This command takes 2± ms to erase the page + 2± µs per data to write
Rev. PrA | Page 37 of 92
ADuC7128
Preliminary Technical Data
±x±A
±x±B
±x±C
Burst
termination
Signature
Stops the running burst to allow execution from Flash/EE immediately
Give a signature of the ꢀ4kBytes of Flash/EE in the 24-bit FEExSIGN MMR. This operation takes 32778 clock
cycles.
This command can be run only once. The value of FEExPRO is saved and can be removed only with a mass
Protect
erase (±x±ꢀ) or with the key
Reserved
Reserved
No operation, interrupt generated
±x±D
±x±E
±x±F
Reserved
Reserved
Ping
* The FEExCON will always read ±x±7 immediately after execution of any of these commands.
Table 17: FEE0PRO and FEE0HID MMR bit designations
Bit
Description
31
Read protection
Cleared by user to protect block ±.
Set by user to allow reading block ±.
3±-±
Write protection for pages 123 to 12±, for pages 119 to 11ꢀ… and for pages ± to 3
Cleared by user to protect the pages in writing
Set by user to allow writing the pages
Table 18: FEE1PRO and FEE1HID MMR bit designations
Bit
Description
31
Read protection
Cleared by user to protect block 1.
Set by user to allow reading block 1.
3±
Write Protection for pages 127 to 12±
Cleared by user to protect the pages in writing
Set by user to allow writing the pages
Write protection for pages for pages 119 to 11ꢀ… and for pages ± to 3
Cleared by user to protect the pages in writing
Set by user to allow writing the pages
31-±
Rev. PrA | Page 38 of 92
Preliminary Technical Data
ADuC7128
that involve using the Flash/EE for data memory. If the
instruction to be executed is a control flow instruction, an extra
cycle is needed to decode the new address of the program
counter and then four cycles are needed to fill the pipe-line. A
data processing instruction involving only core register doesn’t
require any extra clock cycle but if it involves data in Flash/EE,
an extra clock cycle is needed to decode the address of the data
and two cycles to get the 32-bit data from Flash/EE. An extra
cycle must also be added before fetching another instruction.
Data transfer instruction are more complex and are
summarised Table 19.
Execution time from SRAM and FLASH/EE
This chapter describes SRAM and Flash/EE access times during
execution for applications where execution time is critical.
Execution from SRAM
Fetching instructions from SRAM takes one clock cycle as the
access time of the SRAM is 2ns and a clock cycle is 23ns
minimum. However, if the instruction involve reading or
writing data to memory, one extra cycle must be added if the
data is in SRAM, or three cycle if the data is in Flash/EE, one
cycle to execute the instruction and two cycles to get the 32-bit
data from Flash/EE. A control flow instruction, for example a
branch instruction will take one cycle to fetch but also two cycle
to fill the pipeline with the new instructions.
Table 19: execution cycles in ARM/Thumb mode
Instructions Fetch
cycles
Dead
time
Data access
Dead
time
LD
2/1
2/1
1
2
1
LDH
1
1
1
Execution from Flash/EE
LDM/PUSH 2/1
N
1
2 x n
N
1
Because the Flash/EE width is 16-bit and access time for 16-bit
words is 23ns, execution from Flash/EE cannot be done in one
cycle as from SRAM when CD bit =0. Also some dead times are
needed before accessing data for any value of CD bits.
STR
2/1
2/1
2/1
2 x 20µs
20µs
STRH
1
1
STRM/POP
N
N
2 x N x 20µs
In ARM mode, where instructions are 32 bits, two cycles are
needed to fetch any instruction when CD = 0 and in Thumb
mode, where instructions are 16 bits, one cycle is needed to
fetch any instruction.
With 1<N≤16, N number of data to load or store in the multiple
load/store instruction.
The SWAP instruction combine a LD and STR instruction with
only one fetch giving a total of 8 cycles plus 40µs.
Timing is identical in both mode when executing instructions
Rev. PrA | Page 39 of 92
ADuC7128
Preliminary Technical Data
RESET AND REMAP
The ARM exception vectors are all situated at the bottom of the
memory array, from address 0x00000000 to address 0x00000020
as shown Figure 40.
Remap operation
When a reset occurs on the ADuC7128, execution starts
automatically in factory programmed internal configuration
code. This so called kernel is hidden and cannot be accessed by
user code. If the ADuC7128 is in normal mode (BM pin is
high), it will execute the power-on configuration routine of the
kernel and then jump to the reset vector address, 0x00000000, to
execute the users reset exception routine.
FFFFFFFFh
0008FFFFh
kernel
Because the Flash/EE is mirrored at the bottom of the memory
array at reset, the reset interrupt routine must always be written
in Flash/EE.
The remap is done from Flash/EE by setting bit0 of the REMAP
register. Precaution must be taken to execute this command
from Flash/EE, above address 0x00080020, and not from the
bottom of the array as this will be replaced by the SRAM.
Flash/EE
interrupt
00080000h
00040000h
00000000h
service routines
00041FFFh
interrupt
service routines
SRAM
Mirror Space
This operation is reversible: the Flash/EE can be remapped at
address 0x00000000 by clearing Bit0 of the REMAP MMR.
Precaution must again be taken to execute the remap function
from outside the mirrored area. Any kind of reset will remap the
Flash /EE memory at the bottom of the array.
ARM exception
vector addresses
0x00000020
0x00000000
Figure 40: remap for exception execution
By default and after any reset, the Flash/EE is mirrored at the
bottom of the memory array. The remap function allows the
programmer to mirror the SRAM at the bottom of the memory
array, facilitating execution of exception routines from SRAM
instead of from Flash/EE. This means exceptions are executed
twice as fast, exception being executed in ARM mode (32 bit)
and the SRAM being 32-bit wide instead of 16-bit wide
Flash/EE memory.
Reset
There are four kinds of reset: external reset, Power-on-reset,
watchdog expiation and software force. The RSTSTA register
indicates the source of the last reset and RSTCLR allows to clear
the RSTSTA register. These registers can be used during a reset
exception service routine to identify the source of the reset. If
RSTSTA is null, the reset was external. Note: When clearing
RSTSTA all bits that are currently ‘1’ must be cleared, otherwise
a reset event will occur.
Table 20: REMAP MMR bit designations
Bit
Name
Description
±
Remap
Remap Bit.
Set by the user to remap the SRAM to address ±x±±±±±±±±.
Cleared automatically after reset to remap the Flash/EE memory to address ±x±±±±±±±±.
Table 21: RSTSTA MMR bit designations
Bit
7-3
2
Description
Reserved
Software reset
Set by user to force a software reset.
Cleared by setting the corresponding bit in RSTCLR
Watchdog timeout
Set automatically when a watchdog timeout occurs
Cleared by setting the corresponding bit in RSTCLR
Power-on-reset
1
±
Set automatically when a power-on-reset occurs
Cleared by setting the corresponding bit in RSTCLR
Rev. PrA | Page 4± of 92
Preliminary Technical Data
ADuC7128
OTHER ANALOG PERIPHERALS
DAC
The ADuC7128 features a 1±-bit current DAC which can be used to generate user defined waveforms or sine waves generated by the
DDS. The DAC consists of a 1± bit IDAC followed by a current to voltage conversion.
The current output of the IDAC is passed through a resistor and capacitor network where it is both filtered and converted to a
voltage. This voltage is then buffered by an op-amp and passed to the line driver.
The user may optionally disable the internal filter and place an external filter between VDAC and AIN5.
For the DAC to function the internal 2.5v voltage reference must be enabled and driven out onto an external capacitor, i.e. REFCON =
±x±1.
Once the DAC is enabled users will see a 5mV drop in the internal reference value. This is due to bias currents drawn from the
reference used in the DAC circuitry. It is recommended that if using the DAC then it is left powered on to avoid seeing variations in
ADC results.
Table 22: DACCON MMR bit designations
Bit
Description
1±-9
±±
±1
1±
11
Shuffle one increment at a time.
Shuffle based on an internal counter.
Shuffle based on the input data.
Reserved.
8
7
ꢀ
5
4
MSB Shuffle Enable Control
Set by user to enable MSB Shuffling
Cleared by user to disable MSB Shuffling
LSB Shuffle Enable Control
Set by user to enable LSB Shuffling
Cleared by user to disable LSB Shuffling
Power Reduction Control
Set by user to reduce power consumption of DAC and line driver, this will also reduce the performance of the circuit.
Cleared by user to operate in normal power mode.
Output Enable. This bit operates is all modes
Set by user to enable the Line Drive output.
Cleared by user to disable the Line Driver output. In this mode the line driver output is high impedance.
Single ended or Differential output Control.
Set by user to operated in differential mode, the output is the differential voltage between LD1TX and LD2TX
The voltage output range will be Vref/2 +/- Vref/2
Cleared by user to reference the LD1TX output to AGND
The voltage output rage will be AVdd/2 +/- Vref/2
3
Reserved, This bit should be set to ‘±’ by the user.
2-1
Operation Mode Control. This bit selects the mode of operation of the DAC.
±±
±1
1±
11
Powerdown
Reserved
Reserved
DDS and DAC mode, selected by DACEN
±
DAC update rate control This bit has no effect when in DDS or PLM mode.
Set by user to update the DAC on the negative edge of Timer 1. This allows the user to use any one of the core clk, osc
clk, baud clks or user clk and divide these down by 1, 1ꢀ, 25ꢀ or 327ꢀ8. A user can do waveform generation by writing
to the Dac Data Register from ram and update the dac at regular intervals via timer1.
Cleared by user to update the DAC on the negative edge of HCLK.
Rev. PrA | Page 41 of 92
ADuC7128
Preliminary Technical Data
DACEN Register
Name
Address
Default Value
Access
DACEN
±xFFFF±ꢀB8
±x±±
RW
DACEN MMR Bit Designations
Bit
7 to 1
±
Description
Reserved.
Set to ‘1’ by the user to enable DAC mode
Set to ‘±’ by the user to enable DDS mode
DACDAT Register
Name
Address
±xFFFF±ꢀB4
Default Value
±x±±±±
Access
DACDAT
RW
Table 23. DACDAT MMR Bit Designations
Bit
Description
15 to 1±
9 to ±
Reserved.
1±-bit data for DAC
The DACDAT MMR controls the output of the DAC. The data written to this register is a +/- 9 bits signed value. This means that
±x±±±± represents midscale, ±x±2±± represents zero scale and ±x±1FF full scale.
DACEN and DACDAT require key access, the write to these MMRs follow the sequence below,
DACEN
DACDAT
DACKEY± = ±x±7
DACEN = User Value
DACKEY1 = ±xB9
DACKEY± = ±x±7
DACDAT = User Value
DACKEY1 = ±xB9
Rev. PrA | Page 42 of 92
Preliminary Technical Data
ADuC7128
DDS
The DDS is used to generate a digital sine wave signal for the DAC on the ADuC7128. It can be enabled into a free running mode by
the user.
Both the phase and frequency can be controlled.
Table 24: DDSCON MMR bit designations
Bit
7-ꢀ
5
Description
Reserved
DDS Output Enable
Set by user to enable the DDS output, this only has effect if the DDS is selected in DACCON
Cleared by user to disable the DDS output.
Reserved
4
±
Binary Divide Control.
DIV
Scale Ratio
±±±±
±±±1
±±1±
±±11
±1±±
±1±1
±11±
±111
1xxx
±.±±±
±.125
±.25±
±.375
±.5±±
±.ꢀ25
±.75±
±.875
1.±±±
DDSFRQ Register
Name
Address
Default Value
±x±±±±±±±±
Access
RW
DDSFRQ
±xFFFF±ꢀ94
Table 25. DACDAT MMR Bit Designations
Bit
Description
31 to ±
FSW
The DDS Frequency is controlled via the DDSFRQ MMR. This MMR contains a 32 bit word (FSW, frequency select word) which
controls the frequency according to the following formula:
FSW × 20.8896MHz
Frequency =
232
DDSPHS Register
Name
Address
Default Value
±x±±±±±±±±
Access
RW
DDSPHS
±xFFFF±ꢀ98
Table 26. DDSPHS MMR Bit Designations
Bit
Description
31 to 12
11 to ±
Reserved.
Phase
Rev. PrA | Page 43 of 92
ADuC7128
Preliminary Technical Data
The DDS Phase offset is controlled via the DDSPHS MMR. This MMR contains a 12 bit value which controls the phase of the DDS
output according to the following formula:
2 ×π × Phase
Phaseoffset =
212
Rev. PrA | Page 44 of 92
Preliminary Technical Data
ADuC7128
POWER SUPPLY MONITOR
The Power Supply Monitor monitors the IOVDD supply on the
ADuC7128. It indicate when IOVDD supply pin drops below one
of two supply trip points. The monitor function is controlled via
the PSMCON register. If enabled in the IRQEN or FIQEN
register, the monitor will interrupt the core using the PSMI bit
in the PSMCON MMR. This bit will be cleared immediately
once CMP goes high. Note that if the interrupt generated is
exited before CMP goes high (i.e. IOVdd above the trip point)
then no further interrupts will be generated until CMP returns
high. The user should ensure that code execution remains
within the ISR until CMP returns high.
This monitor function allows the user to save working registers
to avoid possible data loss due to the low supply or brown-out
conditions, and also ensures that normal code execution will
not resume until a safe supply level has been established.
The PSM will not operate correctly when using JTAG debug. It
should be disabled in this mode.
Table 27: PSMCON MMR bit descriptions
Bit
Name
Description
3
CMP
Comparator Bit
This is a read-only bit and directly reflects the state of the comparator
Read ‘1’ indicates the IOVDD supply is above its selected trip point.
Read ‘0’ indicates the IOVDD supply is below its selected trip point.
Trip Point Selection Bits
2
TP
0 - 2.79V
1 - 3.07V
1
0
PSMEN
PSMI
Power Supply Monitor Enable Bit
Set to ‘1’ by the user to enable the Power Supply Monitor circuit
Clear to ‘0’ by the user to disable the Power Supply Monitor circuit
Power Supply Monitor Interrupt Bit.
This bit will be set high by the MicroConverter if CMP is low, indicating low I/O supply. The PSMI Bit
can be used to interrupt the processor. Once CMP returns high, the PSMI bit may be cleared by writing a
‘1’ to this location. A write of ‘0’ has no effect. There is no timeout delay, PSMI may be cleared
immediately once CMP goes high.
Rev. PrA | Page 45 of 92
ADuC7128
Preliminary Technical Data
COMP
OUT
V
V
H
H
COMPARATOR
The ADuC7128 also integrates an uncommitted voltage
comparator.
The positive input is multiplexed with ADC2 and the negative
input has two options: ADC3 or the internal reference. The
output of the comparator can be configured to generate a
system interrupt, can be routed directly to the Programmable
Logic Array, can start an ADC conversion or be on an external
COMP0
V
OS
Figure 41. Comparator Hysteresis Transfer Function
pin, CMPOUT
.
PLA
ADC2/CMP0
IRQ
Hysteresis
MUX
ADC START
CONVERSION
ADC3/CMP1
MUX
Figure 41 shows how the input offset voltage and hysteresis
terms are defined. Input offset voltage (VOS) is the difference
between the center of the hysteresis range and the ground level.
This can either be positive or negative. The hysteresis voltage
(VH) is one-half the width of the hysteresis range.
REF
P0.0/CMPOUT
Figure 42: Comparator
The comparator interface consists on a 16-bit MMR, CMPCON
described below.
Table 28: CMPCON MMR bit descriptions
Bit
Name
Description
15-11
10
Reserved
CMPEN
Comparator enable bit:
Set by user to enable the comparator, Note: A comparator interrupt will be generated on the enable of the
comparator, this should be cleared in the user software.
Cleared by user to disable the comparator
9-8
7-6
CMPIN
Comparator negative input select bits:
00
01
10
11
AVDD/2
ADC3 input
Vref * 0.6
Reserved
CMPOC
Comparator output configuration bits:
00
01
10
11
IRQ and PLA connections disabled
IRQ and PLA connections disabled
PLA Connections enabled
IRQ Connections enabled
5
CMPOL
Comparator output logic state bit
When low the comparator output is high when the positive input (CMP0) is above the negative input
(CMP1).
When high, the comparator output is high when the positive input is below the negative input
Response time
4-3
CMPRES
5 µs response time typical for large signals (2.5 V differential).
17 µs response time typical for small signals (±.ꢀ5 mV differential).
Reserved
00
01
10
11
Reserved
3 µs response time typical for any signal type.
Rev. PrA | Page 4ꢀ of 92
Preliminary Technical Data
ADuC7128
2
1
0
CMPHYST
CMPORI
CMPOFI
Comparator hysteresis bit:
Set by user to have an hysteresis of about 7.5mV
Cleared by user to have no hysteresis
Comparator output rising edge interrupt
Set automatically when a rising edge occurs on the monitored voltage (CMP0)
Cleared by user by writing a 1 to this bit.
Comparator output falling edge interrupt
Set automatically when a falling edge occurs on the monitored voltage (CMP0)
Cleared by user
Rev. PrA | Page 47 of 92
ADuC7128
Preliminary Technical Data
Figure 43: clocking system
OSCILLATOR AND PLL - POWER CONTROL
The ADuC7128 integrates a 32.768kHz oscillator, a clock
divider and a PLL. The PLL locks onto a multiple (1275) of the
internal oscillator to provide a stable 41.78 MHz clock for the
system. The core can operate at this frequency, or at binary
submultiples of it, to allow power saving. The default core clock
is the PLL clock divided by 8 (CD = 3) or 5.2 MHz. The core
clock frequency can be outputted on the ECLK pin as
described in the GPIO section. A power down mode is available
on the ADuC7128.
External Crystal Selection
To switch to external crystal, clear the OSEL bit in the PLLCON
MMR (see Table 31). In noisy environments, noise might couple
to the external crystal pins and PLL could loose lock
momentary. A PLL interrupt is provided in the interrupt
controller. The core clock is halted immediately and this
interrupt is only serviced once the lock has been restored.
In case of crystal loss, the watchdog timer should be used.
During initialisation a test on the RSTSTA can determine if the
reset came from the watchdog timer.
The operating mode, clocking mode and programmable clock
divider are controlled via two MMRs, PLLCON and POWCON.
PLLCON controls operating mode of the clock system while
POWCON controls the core clock frequency and the power-
down mode.
External Clock Selection
To switch to an external clock on P0.7, configure P0.7 in Mode
1 and MDCLK bits to 11. External clock can be up to 44 MHz
providing the tolerance is 1%.
XCLKO
XCLKI
INT. 32kHz *
OSCILLATOR
CRYSTAL
OSCILLATOR
WATCHDOG
TIMER
WAKEUP
TIMER
AT POWER UP
OCLK
32.768kHz
41.78MHz
PLL
P0.7/XCLK
MDCLK
ANALOG
UCLK
/2CD
I2C
CD
PERIPHERALS
CORE
HCLK
* 32.768kHz +/-3%
Rev. PrA | Page 48 of 92
Preliminary Technical Data
ADuC7128
Power Control System
A choice of operating modes is available on the ADuC7128. Table 29 describes what part of the ADuC7128 is powered on in the different
modes and indicates the power-up time. Table 30 gives some typical values of total the current consumption (analog + digital supply
currents) in the different modes depending on the clock divider bits. The ADC is turned off. Note that these values also include current
consumption of the regulator and other parts on the test board on which these values were measured.
Table 29. Operating Modes
Mode
Active
Pause
Nap
Sleep
Stop
Core
Peripherals
PLL
X
X
XTAL/T2/T3
XIRQ
Start up /power on Time
TBD at CD = ±
TBD at CD = ±. 3.±ꢀ µs at CD = 7
TBD at CD = ±. 3.±ꢀ µs at CD = 7
TBD
X
X
X
X
X
X
X
X
X
X
X
X
X
TBD
Table 30. Typical Current Consumption at 25°C
PC[2-0]
Mode
Active
Pause
Nap
CD = 0
CD = 1
CD = 2
CD = 3
CD = 4
CD = 5
CD = 6
CD = 7
±±±
±±1
±1±
±11
1±±
Sleep
Stop
POWCON Register
MMRs and Keys
Name
Address
Default Value
Access
The operating mode, clocking mode and programmable clock
divider are controlled via two MMRs, PLLCON (see Table 31)
and POWCON (see Table 32). PLLCON controls operating
mode of the clock system, while POWCON controls the core
clock frequency and the power-down mode.
POWCON
±xFFFF±4±8
±x±±±3
RW
Table 31. PLLCON MMR Bit Designations
Bit Value Name
Description
7, ꢀ
Reserved.
To prevent accidental programming, a certain sequence, shown
in Table 33, has to be followed to write in the PLLCON and
POWCON registers.
5
OSEL
32k Hz PLL input selection. Set by
the user to use the internal 32 kHz
oscillator. Set by default. Cleared by
user to use the external 32 kHz crystal.
4,
3, 2
1, ±
Reserved.
PLLKEYx Register
Name
Address
Default Value
±x±±±±
Access
W
W
MDCLK Clocking modes.
Reserved.
PLLKEY1
PLLKEY2
±xFFFF±41±
±xFFFF±418
±±
±1
1±
11
±x±±±±
PLL. Default configuration.
Reserved.
External clock on P±.7 pin.
PLLCON Register
Name
Address
Default Value
Access
PLLCON
±xFFFF±414
±x21
RW
POWKEYx Register
Name
Address
Default Value
±x±±±±
±x±±±±
Access
W
W
POWKEY1
POWKEY2
±xFFFF±4±4
±xFFFF±4±C
Rev. PrA | Page 49 of 92
ADuC7128
Preliminary Technical Data
Table 32. POWCON MMR Bit Designations
Bit
Value
Name
Description
7
Reserved.
ꢀ. 5. 4
PC
Operating modes.
Active mode.
Pause mode.
Nap.
Sleep mode. XIRQ±, XIRQ1, Timer2,
and Timer3 can wake-up the
ADuC7128
±±±
±±1
±1±
±11
1±±
Stop mode.
Others
Reserved.
3
RSVD
CD
Reserved
2, 1, ±
CPU clock divider bits.
41.7792±± MHz
2±.889ꢀ±± MHz
1±.4448±± MHz
5.2224±± MHz
2.ꢀ112±± MHz
1.3±5ꢀ±± MHz
ꢀ54.8±± kHz
±±±
±±1
±1±
±11
1±±
1±1
11±
111
32ꢀ.4±± kHz
Table 33. PLLCON and POWCON Write Sequence
PLLCON
POWCON
PLLKEY1 = ±xAA
PLLCON = ±x±1
PLLKEY2 = ±x55
POWKEY1 = ±x±1
POWCON = User Value
POWKEY2 = ±xF4
Rev. PrA | Page 5± of 92
Preliminary Technical Data
DIGITAL PERIPHERALS
ADuC7128
PWM
General overview
The ADuC7128 integrates a six channel PWM interface. The
PWM outputs can be configured to drive a H-Bridge or can
be used as standard PWM outputs. On power up the PWM
outputs default to H-Bridge mode. This ensures that the
motor is turned off by default. In standard PWM mode the
outputs are arranged as 3 pairs of PWM pins. Users have
control over the period of each pair of outputs and of the
duty cycle of each individual output.
The PWM clock is selectable via PWMCON1 with one of the
following values, UCLK /2, 4, 8, 1ꢀ, 32, ꢀ4, 128 or 25ꢀ.
The PWM has the following MMRs
Name
PWMCON1
Function
PWM Control
The length of a PWM period is defined by PWMxLEN.
The PWM waveforms are set by the count value of the 1ꢀ-bit
timer and the compare registers contents as shown with the
PWM1 and PWM2 waveforms above.
PWM1COM1
PWM1COM2
PWM1COM3
PWM1LEN
Compare register 1 for PWM o/ps 1 and 2
Compare register 2 for PWM o/ps 1 and 2
Compare register 3 for PWM o/ps 1 and 2
Frequency Control for PWM o/ps 1 and 2
Compare register 1 for PWM o/ps 3 and 4
Compare register 2 for PWM o/ps 3 and 4
Compare register 3 for PWM o/ps 3 and 4
Frequency Control for PWM o/ps 3 and 4
Compare register 1 for PWM o/ps 5 and ꢀ
Compare register 2 for PWM o/ps 5 and ꢀ
Compare register 3 for PWM o/ps 5 and ꢀ
Frequency Control for PWM o/ps 5 and ꢀ
PWM Convert Start Control
The low-side waveform, PWM2, goes high when the timer
count reaches PWM1LEN, and it goes low when the timer
count reaches the value held in PWM1COM3 or when the
high-side waveform PWM1 goes low.
PWM2COM1
PWM2COM2
PWM2COM3
PWM2LEN
The high-side waveform, PWM1, goes high when the timer
count reaches the value held in PWM1COM1, and it goes low
when the timer count reaches the value held in PWM1COM2.
PWM3COM1
PWM3COM2
PWM3COM3
PWM3LEN
Table 34. PWMCON1 MMR Bit Designations
Bit Value Name
Description
14
SYNC
Enables PWM synchronization
PWMCON2
PWMICLR
Set to ‘1’ by the user so that all PWM
counters are reset on the next clock
edge after the detection of a high to
low transition on the SYNC pin.
PWM Interrupt Clear
Cleared by the user to ignore
transitions on the SYNC pin.
PWMꢀINV Set to ‘1’ by the user to invert PWMꢀ
Cleared by the user to use PWMꢀ in
normal mode.
PWM4NV Set to ‘1’ by the user to invert PWM4
Cleared by the user to use PWM4 in
normal mode.
PWM2INV Set to ‘1’ by the user to invert PWM2
Cleared by the user to use PWM2 in
normal mode.
PWMTRIP Set to ‘1’ by the user to enable PWM
trip interrupt. When the PWMTRIP
In all modes the PWMxCOMx MMRs controls the point at
which the PWM outputs change state. An example of the first
pair of PWM outputs ( PWM1 and PWM2) is shown below.
13
12
11
1±
Figure 44 PWM Timing.
input is low the PWMEN bit is cleared
and an interrupt is generated.
Rev. PrA | Page 51 of 92
ADuC7128
Preliminary Technical Data
Cleared by the user to diable the
PWMTRIP interrupt.
9
ENA
If HOFF = ± and HMODE = 1
Set to ‘1’ by the user to enable PWM
outputs
In H-Bridge mdoe i.e. HMODE = 1 then the table below
determines the PWM outputs.
Cleared by the user to disable PWM
outputs.
If HOFF=1 and HMODE=1, see table
51
HS= High side, LS= Low side
Table 35.
PWMCOM1 MMR
PWM Outputs
In not H-Bridge mode this bit has no
effect.
PWM Clock prescaler bits.
Sets UCLCK divider.
PWM1
PWM2
PWMR3
PWM4
ENA
HOFF POINV DIR
8
7
ꢀ
PWMCP2
PWMCP1
PWMCP±
0
x
1
1
1
1
0
1
0
0
0
0
x
x
0
0
1
1
x
x
0
1
0
1
1
1
1
1
1
0
1
0
±±±
±±1
±1±
±11
1±±
1±1
11±
111
2
4
8
1ꢀ
32
ꢀ4
128
25ꢀ
0
0
HS
0
LS
0
HS
!HS
1
LS
!LS
1
1
1
!HS
!LS
5
4
POINV
HOFF
Set to ‘1’ by the user to invert all
PWM outputs
Cleared by the user to use PWM
outputs as normal.
Note on POWERUP PWMCON1 defaults to ±x12 i.e. HOFF = 1
and HMODE = 1. All GPIO pins associated with the PWM are
configured in PWM mode by default.
High side off.
Set to ‘1’ by the user to force PWM1
and PWM3 outputs high, this also
forces PWM2 and PWM4 low.
The compare registers are detailed below.
Cleared by the user to use the PWM
outputs as normal
Load compare regiseters.
Name
Address
Default Value
±x±±
Access
RW
PWM1COM1
PWM1COM2
PWM1COM3
PWM2COM1
PWM2COM2
PWM2COM3
PWM3COM1
PWM3COM2
PWM3COM3
±xFFFF±F84
±xFFFF±F88
±xFFFF±F8C
±xFFFF±F94
±xFFFF±F98
±xFFFF±F9C
±xFFFF±FA4
±xFFFF±FA8
±xFFFF±FAC
3
LCOMP
±x±±
RW
Set to ‘1’ by the user to load the
internal compare registers with the
values in PWMxCOMx on the next
transition of the PWM timer from
±x±± to ±x±1.
Cleared by the user to use the values
previously stored in the internal
compare registers.
±x±±
RW
±x±±
RW
±x±±
RW
±x±±
RW
±x±±
RW
±x±±
RW
2
DIR
Direction Control
±x±±
RW
Set to ‘1’ by the user to enalble
PWM1 and PWM2 as the output
signals while PWM3 and PWM4 are
held low.
Cleared by the user to enable PWM3
and PWM4 as the output signals
while PWM 1 and PWM2 are held
low.
The PWM Trip interrupt can be cleared by writing to the
PWMICLR MMR. Note: When using the PWM trip interrupt
users should make sure that the PWM interrupt has been
cleared before exiting the ISR. This avoids multiple interrupts
being generated.
1
±
HMODE
PWMEN
Enables H-Bridge mode
PWM Convert Start Control
Set to ‘1’ by the user to enable H-
Bridge mode and bits 1-5 of
PWMCON1.
Cleared by the user to operate the
PWMs in standard mode.
The PWM can be configured to generated an ADC convert
start signal after the active low side signal goes high. There is
a programmable delay between when the low side signal
goes high and the Convert Start signal is generated.
Set to ‘1’ by the user to enable all
PWM outputs.
This is controlled via the PWMCON2 MMR. If the delay
Rev. PrA | Page 52 of 92
Preliminary Technical Data
ADuC7128
selected is higher than the width of the PWM pulse, the
interrupt will remain low.
Table 36. PWMCON2 MMR Bit Designations
Bit Value Name Description
7
CSEN
Set to ‘1’ by the user to enable the PWM
to generate a convert start signal.
Cleared by the user to diable the PWM
convert start signal.
3-
±
CSD3
CSD2
CSD1
CSD±
Convert Start Delays. Delay the convert
start signal by a number of clock pulses.
4
±±±±
±±±1
±±1±
±±11
±1±±
±1±1
±11±
±111
1±±±
1±±1
1±1±
1±11
11±±
11±1
111±
1111
8
12
1ꢀ
2±
24
28
32
3ꢀ
4±
44
48
52
5ꢀ
ꢀ±
ꢀ4
When calculating the time from the convert start delay to the
start of an ADC conversion the user needs to take account of
internal delays. The example below shows the case for a delay of
4 clocks. One additional clock is required to pass the convert
start signal to the ADC logic. Once the ADC logic receives the
convert start signal an ADC conversion will begin on the next
ADC clock edge. See figure 32 in the ADC section.
Uclock
Low Side
Count
PWM Signal to Convst
Signal Passed to ADC Logic
Rev. PrA | Page 53 of 92
ADuC7128
Preliminary Technical Data
Quadrature Encoder
Input Filtering
A quadrature encoder is used to determine both the speed
and direction of a rotating shaft. In it’s most common form
there are two digital outputs S1 and S2. As the shaft rotates
both S1 and S2 will toggle, however they will be 9±° out of
phase. The leading output determines the direction of rota-
tion. The time between each transition indicates the speed of
rotation.
Filtering can be applied to the S1 input by setting the FILTEN
bit in QENCON. S1 normally acts as the clock to the counter,
however the filter can be used to ignore positive edges on S1
unless there has been a high or a low pulse on S2 between
two positive edges on S1. (See figure ).
Figure 46. S1 Input Filtering
Table 37. QENCON MMR Bit Designations
Bit
Value Name
Description
15-
11
Reserved.
1±
FILTEN
Set to ‘1’ by the user to enable
filtering on the S1 pin
Figure 45. Quadrate Encoder Input Values
Cleared by the user do disable
filtering on the S1 pin.
Reserved, This bit should be set to ‘±’
by the user.
Set to ‘1’ by the user to invert the S2
intput.
Cleared by the user to use the S2
input as normal.
The quadrature encoder takes the incremental input shown
above and increments or decrements a counter depending on
the direction and speed of the rotating shaft.
9
8
RSVD
S2INV
On the ADuC7128, the internal counter is clocked on the
rising edge of the S1 input, the S2 input indicates the
direction of rotation/count. The counter increments when S2
is high and decrements when it is low.
If the DIRCON bit is set, then S2INV
controls the direction fo the
counter. In this case:
In addition, if the software has prior knowledge of the
direction of rotation. Then one input can be ignored (S2) and
the other can act as a clock (S1).
Set to ‘1’ by the user to operate the
counter in increment mode.
Cleared by the user to operate the
counter in decrement mode.
For added flexibility, all inputs can be internally inverted prior
to use.
The Quadrature Encoder operates asynchronously from the
system clock.
7
ꢀ
S1INV
Set to ‘1’ by the user to invert the S1
intput.
Cleared by the user to use the S1
input as normal.
DIRCON
Direction Control.
Set to ‘1’ by the user to enable S1 as
the input to the counter clock. The
driection of the counter is controlled
via the S2INV bit.
Cleared by the user to operated in
normal mode.
5
S1IRQEN Set to ‘1’ by the user to geneate an
IRQ when a low to high transition is
Rev. PrA | Page 54 of 92
Preliminary Technical Data
ADuC7128
detected on S1.
QENDAT.
Cleared by the user to disable the
interrupt.
This bit should be set to ‘±’ by the
user.
Table 40. QENVAL
4
3
RSVD
Name
Address
Default Value
±x±±±±
Access
QENVAL
±xFFFF±F±C
RW
UIRQEN
Underflow IRQ enable.
This register contains the current value of the Quadrature
Encoder counter.
Set to ‘1’ by the user to generate an
interrupt if QENVAL underflows.
Cleared by the user to disable the
interrupt.
OIREQEN Overflow IRQ enable.
Table 41. QENCLR
Name
Address
Default Value
Access
2
QENCLR
±xFFFF±F14
±x±±±±±±±±
RW
Set to ‘1’ by the user to generate an
interrupt if QENVAL overflows.
Cleared by the user to disable the
interrupt.
This bit should be set to ‘±’ by the
user.
Enable Quadrature Encoder
Writing any value to this register clears the QENVAL register
to ±x±±±±. The bits in this register are undefined.
Table 42. QENSET
1
±
RSVD
Name
Address
Default Value
Access
QENSET
±xFFFF±F18
±x±±±±±±±±
RW
ENQEN
Set to ‘1’ by the user to enable the
quadrature encoder.
Cleared by the user to diable the
quadrature encoder.
Writing any value to this register loads the QENVAL register
with the value in QENDAT. The bits in this register are
undefined.
Note:
Table 38. QENSTA MMR Bit Designations
The interrupt conditions are ORed together to form one
interrupt to the interrupt controller. The Interrupt Service
Routine should check the QENSTA register to find out the
cause of the interrupt.
Bit
7-5
4
Value
Name
Description
Reserved.
S1 rising edge.
S1EDGE
•
•
•
The S1 and S2 inputs shall appear as the QENS1 and
QENS2 inputs in the GPIO list.
This bit is set automatically on a
rising edge of S1
Cleared by reading QENSTA
Reserved.
Underflow flag
This bit is set automatically if an
underflow occurs.
The motor speed can be measured by using the capture
facility in Timer ± or Timer 1.
3
2
RSVD
UNDER
An overflow of either timer can be checked by using an
ISR or by checking IRQSIG.
The counter with the quadrature encoder is gray encoded
to ensure reliable data transfer across
clock boundaries. When an underflow or overflow occurs
the count value does not jump to the
other end of the scale, instead the direction of count
changes. When this happens the value in QENDAT is
subtracted from the value derived from the gray count.
When the value in QENDAT changes the value read back
from QENVAL changes, however the gray encoded value
will not change.
Cleared by read QENSTA
This bit is set automatically if an
overflow has occurred.
Cleared by reading QENSTA
Direction of the counter
Set to ‘1’ by hardare to idicate
that the counter Is
1
±
OVER
DIR
incrementing.
Set to ‘±’ by hardware to
indicate that the counter is
decrementing.
This will only occur after an underflow or overflow.
If the value in QENDAT changes then there must be a
write to QENSET or QENCLR to ensure
Table 39. QENDAT
that a valid number is read back from QENVAL.
Name
Address
Default Value
Access
QENDAT
±xFFFF±F±8
±Xffff
RW
This register holds the maximum value allowed for the
QENVAL register. If the QENVAL register increments past the
value in this register then an overflow condition occurs.
When an overflow occurs the QENVAL register is reset to
±x±±±±. When the QENVAL register decrements past zero
during an underflow it will be loaded with the value in
Rev. PrA | Page 55 of 92
ADuC7128
Preliminary Technical Data
P1.7
P2.±
GPIO
GPIO
DTR±
SYNC
-
RTS1
CTS1
CSL
PLAO[±]
PLAO[5]
PLAO[ꢀ]
PLAO[7]
GENERAL PURPOSE I/O
2
3
4
SOUT
WS
RS
P2.12 GPIO
P2.22 GPIO
P2.32 GPIO
P2.42 GPIO
P2.52 GPIO
P2.ꢀ2 GPIO
P2.72 GPIO
The ADuC7128 provides 28 general purpose, bi-directional I/O
(GPIO) pind. All I/O pins are 5 V tolerant, which means that the
GPIOs support an input voltage of 5 V. In general, many of the
GPIO pins have multiple functions (see the pin function
definitions on page 14). By default, the GPIO pins are
configured in GPIO mode.
AE
RI1
MS±
MS1
MS2
MS3
AD±
AD1
AD2
AD3
AD4
AD5
ADꢀ
AD7
AD8
AD9
AD1±
DCD1
DSR1
DTR1
PWM1
PWM2
PWM3
PWM4
PWM5
PWMꢀ
PWM1
PWM3
QENS1
QENS2
All GPIO pins have internal pull-up resistor (of about 100 kΩ)
and their drive capability is 1.6 mA. Note that a maximum of
20 GPIO can drive 1.6 mA at the same time. The following
GPIO have programmable pull up: P0.0, P0.4, P0.5, P0.6, P0.7,
and the 8 GPIOs of P1.
P3.±
P3.1
P3.2
P3.3
P3.4
P3.5
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
PLAI[8]
PLAI[9]
PLAI[1±]
PLAI[11]
PLAI[12]
PLAI[13]
PLAI[14]
PLAI[15]
PLAO[8]
PLAO[9]
PLAO[1±]
The 40 GPIO are grouped in 5 ports, Port 0 to Port 4. Each port
is controlled by four or five MMRs, x representing the port
number.
P3.ꢀ2 GPIO
P3.72 GPIO
P4.±
P4.1
P4.2
GPIO
GPIO
GPIO
GPxCON Register
RSVD
Name
Address
Default Value
±x±±±±±±±±
±x±±±±±±±±
±x±±±±±±±±
0x11111111
±x±±±±±±±±
Access
RW
RW
RW
RW
P4.3
GPIO
AD11
PLAO[11]
Trip
GP±CON
GP1CON
GP2CON
GP3CON
GP4CON
±xFFFF±D±±
±xFFFF±D±4
±xFFFF±D±8
±xFFFF±D±C
±xFFFF±D1±
(Shutdown)
P4.4
P4.5
P4.ꢀ
P4.7
GPIO
GPIO
GPIO
GPIO
AD12
AD13
AD14
AD15
PLAO[12]
PLAO[13]
PLAO[14]
PLAO[15]
PLMIN
PLMOUT
SIN1
RW
Note that the kernel changes P0.6 from its default configuration
at reset (MRST) to GPIO mode. If MRST is used for external
circuitry, an external pull-up resistor should be used to insure
that the level on P0.6 does not drop when the kernel switches
mode. For example, if MRST is required for power down, it can
be reconfigured in GP0CON MMR.
SOUT1
1 When configured in Mode 1, PO.7 is ECLK by default, or core clock output.
To configure it as a clock output, MDCLK bits in PLLCON must be set to 11.
2 Only available on 8± pin ADuC7129 part.
GPxCON is the port x control register, and selects the function
of each pin of port X. as described in Table 43.
Table 44. GPxCON MMR Bit Descriptions
Bit
Description
Table 43. GPIO Pin Function Descriptions
31, 3±
29, 28
27, 2ꢀ
25, 24
23, 22
21, 2±
19, 18
17, 1ꢀ
15, 14
13, 12
11, 1±
9, 8
Reserved
Select function of Px.7 Pin
Reserved
Select function of Px.ꢀ Pin
Reserved
Select function of Px.5 Pin
Reserved
Select function of Px.4 Pin
Reserved
Select function of Px.3 Pin
Reserved
Select function of Px.2 Pin
Reserved
Select function of Px.1 Pin
Reserved
Configuration
Port Pin
± P±.±
00
01
10
11
GPIO
CMP
-
-
MS2
BLE
BHE
A1ꢀ
MS1
PLAI[7]
-
P±.12 GPIO
P±.22 GPIO
P±.3
P±.4
P±.5
P±.ꢀ
P±.7
P1.±
P1.1
P1.2
P1.3
P1.4
P1.5
P1.ꢀ
GPIO
TRST
ADCBUSY
PLAO[1]
GPIO/IRQ± CONVSTART
GPIO/IRQ1 ADCBUSY
GPIO/T1
GPIO
PLM_COMP PLAO[2]
AE
MRST
ECLK/XCLK1 SIN±
PLAO[3]
PLAO[4]
PLAI[±]
PLAI[1]
PLAI[2]
PLAI[3]
PLAI[4]
PLAI[5]
PLAI[ꢀ]
1
GPIO/T1
GPIO
GPIO
GPIO
GPIO/IRQ2 RI±
SIN±
SCL±
SDA±
SCL1
SDA1
CLK
7, ꢀ
5, 4
3, 2
1, ±
SOUT±
RTS±
CTS±
Select function of Px.± Pin
GPIO/IRQ3 DCD±
GPIO
MISO
MOSI
DSR±
Rev. PrA | Page 5ꢀ of 92
Preliminary Technical Data
ADuC7128
15 to 8
7 to ±
Reflect the state of port x pins at reset (read only).
Port x data input (read only).
GPxPAR Register
Name
Address
Default Value
±x2±±±±±±±
±x±±±±±±±±
±x±±222222
±x±±±±±±±±
Access
RW
RW
RW
RW
GP±PAR
GP1PAR
GP3PAR
GP4PAR
±xFFFF±D2C
±xFFFF±D3C
±xFFFF±D5C
±xFFFF±DꢀC
GPxSET Register
Name
Address
Default Value
±x±±±±±±XX
±x±±±±±±XX
±x±±±±±±XX
±x±±±±±±XX
±x±±±±±±XX
Access
GP±SET
GP1SET
GP2SET
GP3SET
GP4SET
±xFFFF±D24
±xFFFF±D34
±xFFFF±D44
±xFFFF±D54
±xFFFF±Dꢀ4
W
W
W
W
W
GPxPAR programs the parameters for Port 0, Port 1,,Port 3 and
Port 4. Note that the GPxDAT MMR must always be written after
changing the GPxPAR MMR.
Table 45. GPxPAR MMR Bit Descriptions
GPxSET is a data set port x register.
Table 47. GPxSET MMR Bit Descriptions
Bit Description
31 to 24 Reserved.
Bit
Description
31 to 29
Reserved
Pull up disable Px.7
Reserved
28
27, 2ꢀ, 25
23 to 1ꢀ Data port x set bit. Set to 1 by the user to set bit on
port x; also sets the corresponding bit in the GPxDAT
MMR. Clear to ± by the user; does not affect the data
out.
24
23, 22, 21
2±
19 , 18, 17
1ꢀ
15, 14, 13
Pull up disable Px.ꢀ
Reserved
Pull up disable Px.5
Reserved
Pull up disable Px.4
Reserved
15 to ±
Reserved.
12
11, 1±, 9
Pull up disable Px.3
Reserved
GPxCLR Register
8
Pull up disable Px.2
Reserved
Pull up disable Px.1
Reserved
Name
Address
Default Value
±x±±±±±±XX
±x±±±±±±XX
±x±±±±±±XX
±x±±±±±±XX
±x±±±±±±XX
Access
7, ꢀ, 5
4
3, 2, 1
±
GP±CLR
GP1CLR
GP2CLR
GP3CLR
GP4CLR
±xFFFF±D28
±xFFFF±D38
±xFFFF±D48
±xFFFF±D58
±xFFFF±Dꢀ8
W
W
W
W
W
Pull up disable Px.±
GPxCLR is a data clear port x register.
GPxDAT Register
Table 48. GPxCLR MMR Bit Descriptions
Name
Address
Default Value
Access
RW
RW
RW
RW
Bit
Description
GP±DAT
GP1DAT
GP2DAT
GP3DAT
GP4DAT
±xFFFF±D2±
±xFFFF±D3±
±xFFFF±D4±
±xFFFF±D5±
±xFFFF±Dꢀ±
±x±±±±±±XX
±x±±±±±±XX
±x±±±±±±XX
±x±±±±±±XX
±x±±±±±±XX
31 to 24 Reserved.
23 to 1ꢀ Data port x clear bit. Set to 1 by the user to clear bit
on port x; also clears the corresponding bit in the
GPxDAT MMR. Clear to ± by the user does not affect
the data out.
RW
15 to ±
Reserved.
GPxDAT is a port x configuration and data register. It
configures the direction of the GPIO pins of port x, sets the
output value for the pins configured as output, and receives the
stores the input value of the pins configured as input.
Table 46. GPxDAT MMR Bit Descriptions
Bit
Description
31 to 24 Direction of the data. Set to 1 by the user to
configure the GPIO pin as an output. Clear to ± by
the user to configure the GPIO pin as an input.
23 to 1ꢀ Port x data output.
Rev. PrA | Page 57 of 92
ADuC7128
Preliminary Technical Data
SERIAL PORT MUX
The Serial Port Mux multiplexes the serial port peripherals (two
I2C, SPI, two UARTs) and the Programmable Logic Array (PLA)
to a set of ten GPIO pins. Each pin must be configured to one of
its specific I/O function as described in Table 49.
Pin
Signal
SIN0
SOUT0
RTS0
CTS0
RI0
DCD0
DSR0
DTR0
SIN0
Description
SPM0 (mode 1)
SPM1 (mode 1)
SPM2 (mode 1)
SPM3 (mode 1)
SPM4 (mode 1)
SPM5 (mode 1)
SPM6 (mode 1)
SPM7 (mode 1)
SPM8 (mode 2)
SPM9 (mode 2)
Serial Receive Data
Serial Transmit Data
Request To Send
Clear To Send
Ring Indicator
Data Carrier Detect
Data Set Ready
Data Terminal Ready
Serial Receive Data
Serial Transmit Data
GPIO
00
UART
01
UART/I2C/SPI
10
PLA
11
SPM0
SPM1
SPM2
SPM3
SPM4
SPM5
SPM6
SPM7
SPM8
SPM9
SPM10
SPM11
SPM12
SPM13
SPM14
SPM15
SPM16
SPM17
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P0.7
SIN0
SOUT0
RTS0
CTS0
RI0
DCD0
DSR0
DTR0
ECLK
I2C0SCL
I2C0SDA
I2C1SCL
I2C1SDA
SPICLK
SPIMISO
SPIMOSI
SPICSL
SOUT0
Table 50: UART signal description
The serial communication adopts a asynchronous protocol that
supports various word length, stop bits and parity generation
options selectable in the configuration register.
SIN0
SOUT0
RS
P2.01 PWMSYNC
PLAO[7]
1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
RTS1
CTS1
RI1
DCD1
DSR1
DTR1
1
1
1
1
1
Baud rate generation
AE
MS0
MS1
MS2
MS3
AD14
AD15
There is two way of generating the UART baudrate.
- Normal 450 UART baudrate generation:
The baudrate is a divided version of the core clock using the
value in COM0DIV0 and COM0DIV1 MMRs (16-bit value,
DL).
PLAO[14]
PLAO[15]
P4.6
P4.7
SIN1
SOUT1
41.78MHz
2CD × 16 × 2 × DL
Baud rate =
Table 49: SPM configuration
1 Only available on 80 pin part.
The following table gives some common baudrate values:
Table 49 details the mode for each of the SPMUX GPIO pins.
This configuration has to be done via the GP0CON, GP1CON
and GP2CON MMRs. By default these 17 pins are configured as
GPIOs.
Baud Rate
9ꢀ±±
CD
±
DL
Actual Baud Rate
9ꢀ±±
% Error
±%
88 h
44 h
192±±
±
192±±
±%
1152±±
9ꢀ±±
±
3
3
3
±B h
11 h
8 h
118ꢀ91
9ꢀ±±
3%
±%
UART SERIAL INTERFACE
192±±
1152±±
2±4±±
1ꢀ32±±
ꢀ.25%
41.ꢀ7%
The ADuC7128 contains two identical UART blocks. Only
UART0 is described here, UART1 functions in the exact same
manner.
1 h
Table 51: baudrate using the normal baudrate generator
The UART peripheral is a full-duplex Universal Asynchronous
Receiver/Transmitter, fully compatible with the 16450 serial
port standard. The UART performs serial-to-parallel conversion
on data characters received from a peripheral device or a
MODEM, and parallel-to-serial conversion on data characters
received from the CPU. The UART includes a fractional divider
for baudrate generation and has a network addressable mode.
The UART function is made available on the following 10 pins
of the ADuC7128:
- Using the fractional divider:
The fractional divider combined with the normal baudrate
generator allows the generating of a wider range of more
accurate baudrates.
Rev. PrA | Page 58 of 92
Preliminary Technical Data
ADuC7128
FBEN
/2
Core Clock
UART registers definition
The UART interface consists on 12 registers namely:
/16DL
UART
- COMxTX: 8-bit transmit register
/(M+N/2048)
- COMxRX: 8-bit receive register
- COMxDIV0: divisor latch (low byte)
Figure 47: baudrate generation options
COMTX, COMRX and COMDIV0 share the same address
location. COMTX and COMTX can be accessed when bit 7
in COMCON0 register is cleared. COMDIV0 can be accessed
when bit 7 of COMCON0 is set.
- COMxDIV1: divisor latch (high byte)
- COMxCON0: line control register
Calculation of the baudrate using fractional divider is as follow:
41.78MHz
Baud rate =
N
2CD ×16× DL×2×(M +
)
2048
- COMxSTA0: line status register
41.78MHz
Baud rate × 2CD ×16× DL×2
- COMxIEN0: interrupt enable register
- COMxIID0: interrupt identification register
- COMxCON1: modem control register
N
M +
=
2048
For example:
- COMxSTA1: modem status register
Generation of 19200 baud with CD bits = 3 (Table 51 gives
DL = 8 h).
- COMxDIV2: 16-bit fractional baud divide register
- COMxSCR: 8-bit scratch register used for temporary storage.
Also used in network addressable UART mode.
41.78MHz
19200×23 ×16×8×2
N
M +
M +
=
2048
N
= 1.06
2048
where:
M = 1
N = 0.06 × 2048 = 128
41.78MHz
Baud rate =
128
23 ×16×8×2×
(
)
2048
where:
Baud rate = 19200 bps
Error = 0% compared to 6.25% with the normal baud rate
generator.
Table 52: COMxCON0 MMR Bit Descriptions
Bit
7
Name
DLAB
Description
Divisor latch access
Set by user to enable access to COMDIV± and COMDIV1 registers
Cleared by user to disable access to COMDIV± and COMDIV1 and enable access to COMRX and
COMTX
ꢀ
5
BRK
SP
Set break.
Set by user to force SOUT to ±
Cleared to operate in normal mode
Stick parity
Set by user to force parity to defined values:
1 if EPS = 1 and PEN = 1
± if EPS = ± and PEN = 1
Even parity select bit
Set for even parity
4
EPS
Cleared for odd parity
Rev. PrA | Page 59 of 92
ADuC7128
Preliminary Technical Data
3
PEN
Parity enable bit:
Set by user to transmit and check the parity bit
Cleared by user for no parity transmission or checking
Stop bit
2
STOP
Set by user to transmit 1.5 Stop bit if the Word Length is 5 bits or 2 Stop bits if the word length is ꢀ, 7
or 8 bits. The receiver checks the first Stop bit only, regardless of the number of Stop bits selected
Cleared by user to generate 1 Stop bit in the transmitted data
Word length select:
±± = 5 bits
1-±
WLS
±1 = ꢀ bits
1± = 7 bits
11 = 8 bits
Rev. PrA | Page ꢀ± of 92
Preliminary Technical Data
ADuC7128
Table 53: COMxSTA0 MMR Bit Descriptions
Bit
7
Name
Description
Reserved
ꢀ
TEMT
COMTX empty status bit
Set automatically if COMTX is empty
Cleared automatically when writing to COMTX
COMTX and COMRX empty
Set automatically if COMTX and COMRX are empty
Cleared automatically when one of the register receives data
Break error
Set when SIN is held low for more than the maximum word length
Cleared automatically
Framing error
Set when invalid stop bit
Cleared automatically
Parity error
Set when a parity error occurs
Cleared automatically
5
4
3
2
1
±
THRE
BI
FE
PE
OE
DR
Overrun error
Set automatically if data are overwrite before been read
Cleared automatically
Data ready
Set automatically when COMRX is full
Cleared by reading COMRX
Table 54: COMxIEN0 MMR Bit Descriptions
Bit
7-4
3
Name
Description
Reserved
EDSSI
Modem status interrupt enable bit
Set by user to enable generation of an interrupt if any of COMSTA1[3:±] are set
Cleared by user
RX status interrupt enable bit
Set by user to enable generation of an interrupt if any of COMSTA±[3:±] are set
Cleared by user
Enable transmit buffer empty interrupt
Set by user to enable interrupt when buffer is empty during a transmission
Cleared by user
2
1
±
ELSI
ETBEI
ERBFI
Enable receive buffer full interrupt
Set by user to enable interrupt when buffer is full during a reception
Cleared by user
Table 55: COMxIID0 MMR Bit Descriptions
Bit 2-1
Bit 0
Priority
Definition
Clearing operation
Status bits
NINT
±±
11
1±
±1
±±
1
±
±
±
±
No interrupt
1
2
3
4
Receive line status interrupt
Receive buffer full interrupt
Transmit buffer empty interrupt
Modem status interrupt
Read COMSTA±
Read COMRX
Write data to COMTX or read COMIID±
Read COMSTA1 register
Rev. PrA | Page ꢀ1 of 92
ADuC7128
Preliminary Technical Data
Table 56: COMxCON1 MMR Bit Descriptions
Bit
7-5
4
Name
Description
Reserved
LOOPBACK
Loop back
Set by user to enable loop back mode. In loop back mode the SOUT is forced high. Also the modem
signals are directly connected to the status inputs (RTS to CTS, DTR to DSR, OUT1 to RI and OUT2 to
DCD)
Request to send
Set by user to force the RTS output to ±
Cleared by user to force the RTS output to 1
Data terminal ready
1
±
RTS
DTR
Set by user to force the DTR output to ±
Cleared by user to force the DTR output to 1
Table 57: COMxSTA1 MMR Bit Descriptions
Bit
7
Name
DCD
RI
Description
Data carrier detect
Ring indicator
Data set ready
Clear to send
ꢀ
5
DSR
CTS
4
3
DDCD
Delta DCD
Set automatically if DCD changed state since COMSTA1 last read
Cleared automatically by reading COMSTA1
Trailing edge RI
Set if NRI changed from ± to 1 since COMSTA1 last read
Cleared automatically by reading COMSTA1
Delta DSR
Set automatically if DSR changed state since COMSTA1 last read
Cleared automatically by reading COMSTA1
Delta CTS
2
1
±
TERI
DDSR
DCTS
Set automatically if CTS changed state since COMSTA1 last read
Cleared automatically by reading COMSTA1
Table 58: COMxDIV2 MMR Bit Descriptions
Bit
Name
Description
15
FBEN
Fractional baudrate generator enable bit
Set by user to enable the fractional baudrate generator
Cleared by user to generate baudrate using the standard 45± UART baudrate generator
Reserved
14-13
12-11
1±-±
FBM[1-±]
FBN[1±-±]
M. if FBM = ±, M = 4
N
Rev. PrA | Page ꢀ2 of 92
Preliminary Technical Data
ADuC7128
In network address mode, the least significant bit of the
scratch register is the transmitted network address control bit.
If set to 1, the device is transmitting an address. If cleared to
0, the device is transmitting data.
- COMxIEN1: 8-bit network enable register.
- COMxIID1: 8-bit network interrupt register. Bit 7 to 4 are
reserved. See Table 54.
- COMxADR: 8-bit read and write network address register.
Holds the address the network addressable UART checks for.
On receiving this address the device interrupts the processor
and/or sets the appropriate status bit in COMIID1.
COMIEN1, COMIID1 and COMADR are used only in
network addressable UART mode.
Network addressable UART mode
This mode allows connecting the MicroConverter on a 256-
node serial network, either as a hardware single-master or via
software in a multi-master network. Bit 7 of COMxIEN1
(ENAM bit) must be set to enable UART in network
addressable mode.
Note that there is no parity check in this mode, the parity bit is
used for address.
Network addressable UART register definitions
Three additional register:
- COMxSCR: 8-bit scratch register used for temporary storage.
Table 59: COMxIEN1 MMR Bit Descriptions
Bit
Name
Description
7
ENAM
Network address mode Enable bit
set by user to enable network address mode
cleared by user to disable network address mode
9-bit transmit enable bit
Set by user to enable 9-bit transmit. ENAM must be set
Cleared by user to disable 9-bit transmit
9-bit receive enable bit
ꢀ
5
E9BT
E9BR
Set by user to enable 9-bit receive. ENAM must be set
Cleared by user to disable 9-bit receive
network interrupt Enable bit
4
3
ENI
E9BD
Word length
Set for 9-bit data. E9BT has to be cleared.
Cleared for 8-bit data
Transmitter pin driver Enable bit
2
ETD
Set by user to enable SOUT pin as an output in slave mode or multi-master mode
Cleared by user, SOUT is three-state
Network address bit, interrupt polarity bit
1
±
NABP
NAB
Network address bit
Set by user to transmit the slave’s address
Cleared by user to transmit data
Table 60: COMxIID1 MMR Bit Descriptions
Bit 3-1
Bit 0
priority
Definition
Clearing operation
Status bits
±±±
NINT
1
±
±
±
±
±
±
No interrupt
11±
2
3
1
2
3
4
Matching network address
Address transmitted, buffer empty
Receive line status interrupt
Receive buffer full interrupt
Transmit buffer empty interrupt
Modem status interrupt
Read COMxRX
1±1
Write data to COMTX or read COMxIID±
Read COMxSTA±
±11
±1±
Read COMxRX
±±1
Write data to COMxTX or read COMxIID±
Read COMxSTA1 register
±±±
Rev. PrA | Page ꢀ3 of 92
ADuC7128
Preliminary Technical Data
Chip Select (CS) Input Pin
SERIAL PERIPHERAL INTERFACE
CS
In SPI slave mode, a transfer is initiated by the assertion of
,.
The ADuC7128 integrates a complete hardware serial
peripheral interface (SPI) on-chip. SPI is an industry standard
synchronous serial interface that allows eight bits of data to be
synchronously transmitted and simultaneously received, that is,
full duplex up to a maximum bit rate of 1.6 Mb. The SPI
interface is only operational with core clock divider bits
POWCON[2:0] = 0, 1, or 2.
which is an active low input signal. The SPI port then transmits
and receives 8-bit data until the transfer is concluded by
CS
CS
desassertion of
. In slave mode,
is always an input.
SPI Registers
The following MMR registers are used to control the SPI
interface: SPISTA, SPIRX, SPITX, SPIDIV, and SPICON.
The SPI port can be configured for master or slave operation
and typically consists of four pins, namely: MISO, MOSI, SCL,
and CS.
SPISTA Register
Name
Address
Default Value
Access
SPISTA
±xFFFF±A±±
±x±±
RW
MISO (Master In, Slave Out) Data I/O Pin
SPISTA is an 8-bit read only status register.
The MISO pin is configured as an input line in master mode
and an output line in slave mode. The MISO line on the master
(data in) should be connected to the MISO line in the slave
device (data out). The data is transferred as byte wide (8-bit)
serial data, MSB first.
Table 61. SPISTA MMR Bit Descriptions
Bit
7, ꢀ
5
Description
Reserved.
SPIRX data register overflow status bit. Set if SPIRX is
overflowing. Cleared by reading SPISRX register.
MOSI (Master Out, Slave In) Pin
4
3
SPIRX data register IRQ. Set automatically if Bit 3 or Bit 5
is set. Cleared by reading SPIRX register.
SPIRX data register full status bit. Set automatically if a
valid data is present in the SPIRX register. Cleared by
reading SPIRX register.
The MOSI pin is configured as an output line in master mode
and an input line in slave mode. The MOSI line on the master
(data out) should be connected to the MOSI line in the slave
device (data in). The data is transferred as byte wide (8-bit)
serial data, MSB first.
2
1
±
SPITX data register underflow status bit. Set auto-
matically if SPITX is under flowing. Cleared by writing in
the SPITX register.
SPITX data register IRQ. Set automatically if bit ± is clear
or bit 2 is set. Cleared by writing in the SPITX register or if
finished transmission disabling the SPI.
SPITX data register empty status bit. Set by writing to
SPITX to send data. This bit is set during transmission of
data. Cleared when SPITX is empty.
SCL (Serial Clock) I/O Pin
The master serial clock (SCL) is used to synchronize the data
being transmitted and received through the MOSI SCL period.
Therefore, a byte is transmitted/received after eight SCL
periods. The SCL pin is configured as an output in master mode
and as an input in slave mode.
SPIRX Register
Name
Address
Default Value
Access
SPIRX
±xFFFF±A±4
±x±±
R
In master mode, polarity and phase of the clock are controlled
by the SPICON register, and the bit rate is defined in the
SPIDIV register as follows:
SPIRX is an 8-bit read only receive register.
SPITX Register
fHCLK
fserialclock
=
Name
Address
Default Value
Access
2× (1+ SPIDIV)
SPITX
±xFFFF±A±8
±x±±
W
In slave mode, the SPICON register must be configured with
the phase and polarity of the expected input clock. The slave
accepts data from an external master up to 1.6 Mbs at CD = 0.
SPITX is an 8-bit write only transmit register.
SPIDIV Register
Name
Address
Default Value
Access
In both master and slave modes, data is transmitted on one edge
of the SCL signal and sampled on the other. Therefore, it is
important that the polarity and phase are configured the same
for the master and slave devices.
SPIDIV
±xFFFF±A±C
±x1B
RW
SPIDIV is an 8-bit serial clock divider register.
Rev. PrA | Page ꢀ4 of 92
Preliminary Technical Data
ADuC7128
SPICON Register
Name
Address
Default Value
Access
SPICON
±xFFFF±A1±
±x±±±±
RW
SPICON is a 16-bit control register.
Table 62. SPICON MMR Bit Descriptions
Bit
Description
15 - 13
12
Reserved.
Continuous Transfer Enable. Set by user to enable continuous transfer. In master mode, the transfer continues until no valid data
is available in the TX register. CS is asserted and remains asserted for the duration of each 8-bit serial transfer until TX is empty.
Cleared by user to disable continuous transfer. Each transfer consists of a single 8-bit serial transfer. If valid data exists in the
SPITX register, then a new transfer is initiated after a stall period.
11
1±
9
Loop Back Enable. Set by user to connect MISO to MOSI and test software. Cleared by user to be in normal mode.
Slave Output Enable. Set by user to enable the slave output. Cleared by user to disable slave output.
Slave Select Input Enable. Set by user in master mode to enable the output.
8
SPIRX Overflow Overwrite Enable. Set by user, the valid data in the RX register is overwritten by the new serial byte received.
Cleared by user, the new serial byte received is discarded.
7
ꢀ
SPITX Underflow Mode. Set by user to transmit ±. Cleared by user to transmit the previous data.
Transfer and Interrupt Mode (Master Mode). Set by user to initiate transfer with a write to the SPITX register. Interrupt occurs
when TX is empty. Cleared by user to initiate transfer with a read of the SPIRX register. Interrupt occurs when RX is full.
5
4
LSB First Transfer Enable Bit. Set by user, the LSB is transmitted first. Cleared by user, the MSB is transmitted first.
Reserved.
Should be set to ‘±’
3
2
Serial Clock Polarity Mode Bit. Set by user, the serial clock idles high. Cleared by user, the serial clock idles low.
Serial Clock Phase Mode Bit. Set by user, the serial clock pulses at the beginning of each serial bit transfer. Cleared by user, the
serial clock pulses at the end of each serial bit transfer.
1
±
Master Mode Enable Bit. Set by user to enable master mode. Cleared by user to enable slave mode.
SPI Enable Bit. Set by user to enable the SPI. Cleared to disable the SPI.
Rev. PrA | Page ꢀ5 of 92
ADuC7128
Preliminary Technical Data
The I2C×DIV register corresponds to DIVH:DIVL.
2
I C COMPATIBLE INTERFACES
The ADuC7128 supports two fully licensed I2C interfaces.
The I2C interfaces are both implemented as a full hardware
master and slave interface. Because the two I2C interfaces are
identical, this document describes only I2C0 in detail. Note
that the two masters and slaves have individual interrupts.
Slave Addresses
The registers I2C0ID0, I2C0ID1, I2C0ID2 and I2C0ID3
contain the device IDs. The device compares the four I2C0IDx
registers to the address byte. The seven most significant bits of
either ID register must be identical to that of the seven most
significant bits of the first address byte received to be correctly
addressed. The LSB of the ID registers, transfer direction bit, is
ignored in the process of address recognition.
The two pins used for data transfer, SDA and SCL, are
configured in a Wired-AND format that allows arbitration in a
multi-master system.
The I2C bus peripheral’s addresses in the I2C bus system is
programmed by the user. This ID can be modified any time a
transfer is not in progress. The user can configure the interface
to respond to four slave addresses.
I2C Registers
The I2C peripheral interface consists of 18 MMRs, which are
discussed in this section.
The transfer sequence of an I2C system consists of a master
device initiating a transfer by generating a start condition while
the bus is idle. The master transmits the address of the slave
device and the direction of the data transfer in the initial
address transfer. If the master does not loose arbitration and
the slave acknowledges, then the data transfer is initiated. This
continues until the master issues a stop condition and the bus
becomes idle.
I2CxMSTA Register
Name
Address
Default Value
±x±±
Access
I2C±MSTA
I2C1MSTA
±xFFFF±8±±
±xFFFF±9±±
R
R
±x±±
I2CxMSTA is a status register for the master channel.
Table 63. I2C0MSTA MMR Bit Descriptions
Bit Description
The I2C peripheral master and slave functionality are
independent and can be simultaneously active. A slave is
activated when a transfer has been initiated on the bus. If it is
not addressed, it remains inactive until another transfer is
initiated. This also allows a master device, which looses
arbitration, to respond as a slave in the same cycle.
7
Master busy. Set automatically if the master is busy.
Cleared automatically.
ꢀ
Arbitration loss. Set in multi-master mode if another
master has the bus. Cleared when the bus becomes
available.
No ACK. Set automatically. If the master receive FIFO is full,
the master does not acknowledge the data received.
Cleared automatically.
Master receive FIFO overflow. Set automatically if the
master receive FIFO is overflowing. Cleared automatically
by reading I2C±MRX.
Master receive IRQ. Set after receiving data. Cleared
automatically by reading the I2C±MRX register.
Master transmit IRQ. Set at the end of a transmission.
Cleared automatically by writing to the I2C±MTX register.
Master transmit FIFO underflow. Set automatically if the
master transmit FIFO is underflowing. Cleared
automatically by writing to the I2C±MTX register.
Master TX FIFO empty. Set automatically if the master
transmit FIFO is empty. Cleared automatically by writing to
the I2C±MTX register.
5
4
Serial Clock Generation
The I2C master in the system generates the serial clock for a
transfer. The master channel can be configured to operate in
fast mode (400 kHz) or standard mode (100 kHz).
3
2
1
The bit rate is defined in the I2C0DIV MMR as follows:
fUCLK
fserialclock
=
(2 + DIVH) + (2 + DIVL)
±
where:
UCLK = clock before the clock divider
f
DIVH = the high period of the clock
DIVL = the low period of the clock.
Thus, for 100 kHz operation,
DIVH = DIVL = 0×CF
and for 400 kHz,
DIVH = DIVL = 0×32.
Rev. PrA | Page ꢀꢀ of 92
Preliminary Technical Data
ADuC7128
I2CxSSTA Register
Name
Address
Default Value
±x±1
Access
I2C±SSTA
I2C1SSTA
±xFFFF±8±4
±xFFFF±9±4
R
R
±x±1
I2CxSSTA is a status register for the slave channel.
Table 64. I2CxSSTA MMR Bit Descriptions
I2CxSRX Register
Bit
Value
Description
Name
I2C±SRX
I2C1SRX
Address
Default Value
Access
Access
31 to
15
Reserved. These bits should be written as ±.
±xFFFF±8±8
±xFFFF±9±8
±x±±
±x±±
R
R
14
START decode bit. Set by hardware if the device
receives a valid START + matching address.
Cleared by an I2C stop condition or an I2C
general call reset.
I2CxSRX is a receive register for the slave channel.
I2CxSTX Register
13
Repeated START decode bit. Set by hardware if
the device receives a valid repeated start +
matching address. Cleared by an I2C stop
condition, a read of the I2CSSTA register, or an
I2C general call reset.
Name
I2C±STX
I2C1STX
Address
±xFFFF±8±C
±xFFFF±9±C
Default Value
±x±±
±x±±
W
W
I2CxSTX is a transmit register for the slave channel.
12,
11
ID decode bits.
±±
±1
1±
11
Received address matched ID register ±.
Received address matched ID register 1.
Received address matched ID register 2.
Received address matched ID register 3.
I2CxMRX Register
Name
I2C±MRX
I2C1MRX
Address
±xFFFF±81±
±xFFFF±91±
Default Value
±x±±
±x±±
Access
R
R
1±
Stop after start and matching address interrupt.
Set by hardware if the slave device receives an
I2C STOP condition after a previous I2C START
condition and matching address. Cleared by a
read of the I2CxSSTA register.
General call ID.
No general call.
General call reset and program address.
General call program address.
General call matching alternative ID.
General call interrupt.
Slave Busy. Set automatically if the slave is busy.
Cleared automatically.
No ACK. Set if master asking for data and no
data is available. Cleared automatically.
Slave receive FIFO overflow. Set automatically if
the slave receive FIFO is overflowing. Cleared
automatically by reading I2C±SRX.
Slave receive IRQ. Set after receiving data. Cleared
automatically by reading the I2C±SRX register.
Slave Transmit IRQ. Set at the end of a
transmission. Cleared automatically by writing
to the I2C±STX register.
Slave transmit FIFO underflow. Set automatically if
the slave transmit FIFO is underflowing. Cleared
automatically by writing to the I2C±STX register.
Slave transmit FIFO empty. Set automatically if
the slave transmit FIFO is empty. Cleared
I2CxMRX is a receive register for the master channel.
I2CxMTX Register
Name
I2C±MTX
I2C1MTX
Address
±xFFFF±814
±xFFFF±914
Default Value
±x±±
±x±±
Access
9, 8
W
W
±±
±1
1±
11
I2CxSTX is a transmit register for the master channel.
I2CxCNT Register
7
ꢀ
Name
I2C±CNT
I2C1CNT
Address
±xFFFF±818
±xFFFF±918
Default Value
±x±±
±x±±
Access
RW
RW
5
4
I2CxCNT is a master receive data count register. If a master read
transfer sequence is initiated, the I2CxCNT register denotes the
number of bytes (−1) to be read from the slave device. By default
this counter is 0, which corresponds to expected 1 byte
3
2
I2CxADR Register
Name
I2C±ADR
I2C1ADR
Address
±xFFFF±81C
±xFFFF±91C
Default Value
±x±±
±x±±
Access
RW
RW
1
±
I2CxADR is a master address byte register. The I2CxADR value
is the device address that the master wants to communicate
with. It is automatically transmitted at the start of a master
transfer sequence if there is no valid data in the I2CxMTX
register when the master enable bit is set.
automatically by writing to the I2C±STX register.
Rev. PrA | Page ꢀ7 of 92
ADuC7128
Preliminary Technical Data
I2CxALT is a hardware general call ID register used in slave mode
I2CxCFG Register
I2CxBYTE Register
Name
I2C±BYT
I2C1BYT
Address
Default Value
±x±±
±x±±
Access
RW
RW
±xFFFF±824
±xFFFF±924
Name
I2C±CFG
I2C1CFG
Address
±xFFFF±82C
±xFFFF±92C
Default Value
±x±±
±x±±
Access
RW
RW
I2CxBYTE is a broadcast byte register.
I2CxCFG is a configuration register.
I2CxALT Register
Name
I2C±ALT
I2C1ALT
Address
±xFFFF±828
±xFFFF±928
Default Value
±x±±
±x±±
Access
RW
RW
Table 65. I2C0CFG MMR Bit Descriptions
Bit
Description
31 to 15
14
Reserved. These bits should be written by the user as ±.
Enable stop interrupt. Set by the user to generate an interrupt upon receiving a stop condition and after receiving a valid start
condition + matching address. Cleared by the user to disable the generation of an interrupt upon receiving a stop condition.
13
12
11
1±
9
Reserved. This bit should be written by the user as ±.
Reserved. This bit should be written by the user as ±.
Enable stretch SCL (holds SCL low). Set by the user to stretch the SCL line. Cleared by the user to disable stretching of the SCL line.
Reserved. This bit should be written by the user as ±.
Slave Tx FIFO request interrupt enable. Cleared by the user to generate an interrupt request just after the negative edge of the
clock for the R/W bit. This allows the user to input data into the slave Tx FIFO if it is empty. At 4±± ksps and the core clock running
at 41.78 MHz, the user has 55 clock cycles to take appropriate action, taking interrupt latency into account. Set by the user to
disable the slave Tx FIFO request interrupt.
8
7
ꢀ
5
4
General call status bit clear. Set by the user to clear the general call status bits. Cleared automatically by hardware after the general
call status bits have been cleared.
Master serial clock enable bit. Set by user to enable generation of the serial clock in master mode. Cleared by user to disable serial
clock in master mode.
Loop back enable bit. Set by user to internally connect the transition to the reception to test user software. Cleared by user to
operate in normal mode.
Start back-off disable bit. Set by user in multi-master mode. If losing arbitration, the master immediately tries to retransmit. Cleared
by user to enable start back-off. After losing arbitration, the master waits before trying to retransmit.
Hardware general call enable. (Bit 3 must be set.) Set by user to enable hardware general call. Cleared by user to disable hardware
general call.
General call enable bit. Set by user to address every device on the I2C bus. Cleared by user to operate in normal mode.
3
2
1
±
Reserved.
Master enable bit. Set by user to enable the master I2C channel. Cleared by user to disable the master I2C channel.
Slave enable bit. Set by user to enable the slave I2C channel. A slave transfer sequence is monitored for the device address in
I2C±ID±, I2C±ID1, I2C±ID2, and I2C±ID3. If the device address is recognized, the part participates in the slave transfer sequence.
Cleared by user to disable the slave I2C channel.
I2C1ID±
I2C1ID1
I2C1ID2
I2C1ID3
±xFFFF±938
±xFFFF±93C
±xFFFF±94±
±xFFFF±944
±x±±
±x±±
±x±±
±x±±
RW
RW
RW
RW
I2CxDIV Register
Name
I2C±DIV
I2C1DIV
Address
Default Value
±x1F1F
±x1F1F
Access
RW
RW
±xFFFF±83±
±xFFFF±93±
I2CxID0, I2CxID1, I2CxID2, and I2CxID3 are slave address
device ID registers of I2Cx.
I2CxDIV are the clock divider registers.
I2CxIDx Register
I2CxCCNT Register
Name
I2C±ID±
I2C±ID1
I2C±ID2
I2C±ID3
Address
±xFFFF±838
±xFFFF±83C
±xFFFF±84±
±xFFFF±844
Default Value
±x±±
±x±±
±x±±
±x±±
Access
Name
I2C±SSC
I2C1SSC
Address
±xFFFF±848
±xFFFF±948
Default Value
±x±1
±x±1
Access
RW
RW
RW
RW
RW
RW
I2CxCCNT is an 8-bit start/stop generation counter. It holds
off SDA low for start and stop conditions.
Rev. PrA | Page ꢀ8 of 92
Preliminary Technical Data
ADuC7128
I2C0FIF is an FIFO status register.
I2CxFIF Register
Name
I2C±FIF
I2C1FIF
Address
Default Value
±x±±±±
Access
±xFFFF±84C
±xFFFF±94C
R
R
±x±±±±
Table 66. I2C0FIF MMR Bit Descriptions
Bit
Value
Description
15 to 1±
9
Reserved.
Master transmit FIFO flush. Set by the user to flush the master Tx FIFO. Cleared automatically once the
master Tx FIFO is flushed.
8
Slave transmit FIFO flush. Set by the user to flush the slave Tx FIFO. Cleared automatically once the
slave Tx FIFO is flushed.
7, ꢀ
Master Rx FIFO status bits.
FIFO empty.
Byte written to FIFO.
1 byte in FIFO.
±±
±1
1±
11
FIFO full.
5, 4
3, 2
1, ±
Master Tx FIFO status bits.
FIFO empty.
Byte written to FIFO.
1 byte in FIFO.
FIFO full.
Slave Rx FIFO status bits.
FIFO empty.
Byte written to FIFO.
1 byte in FIFO.
FIFO full.
Slave Tx FIFO status bits.
FIFO empty.
Byte written to FIFO.
1 byte in FIFO.
±±
±1
1±
11
±±
±1
1±
11
±±
±1
1±
11
FIFO full.
*
Purchase of licensed I2C components of Analog Devices or one of its
sublicensed Associated Companies conveys a license for the purchaser
under the Philips I2C Patent Rights to use the ADuC7128 in an I2C system,
provided that the system conforms to the I2C Standard Specification as
defined by Philips.
Rev. PrA | Page ꢀ9 of 92
ADuC7128
Preliminary Technical Data
of block 0 is fed back to the input 0 of mux 0 of element 0 of
block 1.
PROGRAMMABLE LOGIC ARRAY (PLA)
The ADuC7128 integrates a fully Programmable Logic Array
(PLA) which consists of two independent but interconnected
PLA blocks. Each block consists of eight PLA elements, which
gives a total of 16 PLA elements.
PLA Block 0
PLA Block 1
Element Input Output Element Input Output
0
1
2
3
4
5
6
7
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P0.0
P1.7
P0.4
P0.5
P0.6
P0.7
P2.0
P2.1
P2.2
8
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
P4.0
P4.1
P4.2
P4.3
P4.4
P4.5
P4.6
P4.7
9
A PLA element contains a two-input lookup table that can be
configured to generate any logic output function based on two
inputs and a flip-flop as represented in Figure 48 below.
10
11
12
13
14
15
0
A
B
4
2
3
LOOK-UP
TABLE
1
Table 67: element input/output
PLA MMRs interface
Figure 48: PLA element
The PLA peripheral interface consists on 21 MMRs:
In total, 30 GPIO pins are available on the ADuC7128 for the
PLA. These include 16 input pins and 14 output pins. They need
to be configured in the GPxCON register as PLA pins before
using the PLA. Note that the comparator output is also included
as one of the 16 input pins.
- PLAELMx: element0 to element 15 control registers,
configure the input and output mux of each element, select
the function in the lookup table and bypass/use the flip-flop.
- PLACLK: clock selection for the flip-flops of block 0 and
clock selection for the flip-flops of block 1
- PLAIRQ: enable IRQ0 or/and IRQ1 and select the source of
the IRQ
- PLAADC: PLA source fro ADC start conversion signal
- PLADIN: data input MMR for PLA
- PLAOUT: data output MMR for PLA. This register is always
updated.
The PLA is configured via a set of user MMRs and the output(s)
of the PLA can be routed to the internal interrupt system, to the
CONVSTART signal of the ADC, to a MMR or to any of the 16
PLA output pins.
The interconnection between the two blocks is supported by
connecting output of element 7 of block 1 fed back to the input
0 of mux 0 of element 0 of block 0, and the output of element 7
A PLA tool is provided in the development system to easily
configure the PLA.
Table 68: PLAELMx MMR Bit Descriptions
Bit
Description
PLAELM0
PLAELM1 - 7
PLAELM8
PLAELM9-15
31-11
1±-9
Reserved
Mux (±) control, select feedback from:
±± – element 15
±1 – element 2
1± – element 4
11 – element ꢀ
±± – element 1
±1 – element 3
1± – element 5
11 – element 7
element ±
element 2
element 4
element ꢀ
element 1
element 3
element 5
element 7
element 7
element 1±
element 12
element 14
element 9
element 11
element 13
element 15
element 8
element 1±
element 12
element 14
element 9
element 11
element 13
element 15
8-7
Mux (1) control, select feedback from:
ꢀ
Mux (3) control
Set by user to select the output of mux (1)
Cleared by user to select the bit value from PLADIN
Mux (2) control
5
Set by user to select the input pin of the particular element
Cleared by user to select the output of mux (±)
Look-up table control ±±±± – ±
±±±1 – NOR
4-1
±±1± – B AND NOT A
Rev. PrA | Page 7± of 92
Preliminary Technical Data
ADuC7128
±±11 – NOT A
±1±± – A AND NOT B
±1±1 – NOT B
±11± – EXOR
±111 – NAND
1±±± – AND
1±±1 – EXNOR
1±1± – B
1±11 – NOT A OR B
11±± – A
11±1 – A OR NOT B
111± – OR
1111 – 1
±
Mux (4) control
Set by user to bypass the flip-flop
Cleared by user to select the flip-flop. Cleared by default
Table 69: PLACLK MMR Bit Descriptions
Bit
7
Description
Reserved
ꢀ-4
Block1 clock source selection:
±±± – GPIO clock on P±.5
±±1 – GPIO clock on P±.±
±1± – GPIO clock on P±.7
±11 – HCLK
1±± – OCLK
1±1 - Timer 1 overflow
11± - Timer 4 overflow
Other – Reserved
3
Reserved
2-±
Block± clock source selection:
±±± – GPIO clock on P±.5
±±1 – GPIO clock on P±.±
±1± – GPIO clock on P±.7
±11 – HCLK
1±± – OCLK
1±1 - Timer 1 overflow
11± - Timer 4 overflow
Other – Reserved
Table 70: PLAIRQ MMR Bit Descriptions
Bit
Description
Reserved
15-13
12
PLA IRQ1 enable bit
Set by user to enable IRQ1 output from PLA
Cleared by user to disable IRQ1 output from PLA
PLA IRQ1 source
11-8
±±±± – PLA element ±
±±±1 – PLA element 1
…
1111 – PLA element 15
Reserved
7-5
4
PLA IRQ± enable bit
Rev. PrA | Page 71 of 92
ADuC7128
Preliminary Technical Data
Set by user to enable IRQ± output from PLA
Cleared by user to disable IRQ± output from PLA
PLA IRQ± source
3-±
±±±± – PLA element ±
±±±1 – PLA element 1
…
1111 – PLA element 15
Table 71: PLAADC MMR Bit Descriptions
Bit
31-5
4
Description
Reserved
ADC start conversion enable bit
Set by user to enable ADC start conversion from PLA
Cleared by user to disable ADC start conversion from PLA
ADC start conversion source
±±±± – PLA element ±
3-±
±±±1 – PLA element 1
…
1111 – PLA element 15
Table 72: PLADIN MMR Bit Descriptions
Bit
Description
31-1ꢀ
15-±
Reserved
Input Bit to element 15-±
Table 73: PLAOUT MMR Bit Descriptions
Bit
Description
31-1ꢀ
15-±
Reserved
Output Bit from element 15-±
Rev. PrA | Page 72 of 92
Preliminary Technical Data
ADuC7128
26
27
28
29
30
External IRQ3
PLL Lock
PROCESSOR REFERENCE PERIPHERALS
INTERRUPT SYSTEM
There are 30 interrupt sources on the ADuC7128 which are
controlled by the Interrupt Controller. Most interrupts are
generated from the on-chip peripherals like ADC, UART, etc.
and two additional interrupt sources are generated from
external interrupt request pins, XIRQ0 and XIRQ1. The
ARM7TDMI CPU core will only recognise interrupts as one of
two types, a normal interrupt request IRQ and a fast interrupt
request FIQ. All the interrupts can be masked separately.
IRQ
The IRQ is the exception signal to enter the IRQ mode of the
processor. It is used to service general purpose interrupt
handling of internal and external events.
The four 32-bit registers dedicated to IRQ are:
The control and configuration of the interrupt system is
managed through nine interrupt-related registers, four
dedicated to IRQ, four dedicated to FIQ. An additional MMR is
used to select the programmed interrupt source. The bits in
each IRQ and FIQ registers represent the same interrupt source
as described in Table 74.
- IRQSIG, reflects the status of the different IRQ sources. If a
peripheral generate an IRQ signal, the corresponding bit in
the IRQSIG will be set, otherwise it is cleared. The IRQSIG
bits are cleared when the interrupt in the particular
peripheral is cleared. All IRQ sources can be masked in the
IRQEN MMR. IRQSIG is read-only.
- IRQEN, provides the value of the current enable mask. When
bit is set to 1, the source request is enabled to create an IRQ
exception. When bit is set to 0, the source request is disabled
or masked which will not create an IRQ exception. To clear a
bit in IRQEN, use the IRQCLR MMR.
- IRQCLR, (write-only register) allows clearing the IRQEN
register in order to mask an interrupt source. Each bit set to 1
will clear the corresponding bit in the IRQEN register
without affecting the remaining bits. The pair of registers
IRQEN and IRQCLR allows independent manipulation of
the enable mask without requiring an atomic read-modify-
write.
- IRQSTA, (read-only register) provides the current enabled
IRQ source status. When set to 1 that source should generate
an active IRQ request to the ARM7TDMI core. There is no
priority encoder or interrupt vector generation. This function
is implemented in software in a common interrupt handler
routine. All 32 bits are logically OR’ed to create the IRQ signal
to the ARM7TDMI core.
Table 74: IRQ/FIQ MMRs bit description
Bit
0
Description
FIQ source
1
SWI:
not used in IRQEN/CLR
and FIQEN/CLR
2
3
4
5
6
7
8
Timer 0
Timer 1
Wake Up timer – Timer 2
Watchdog timer – Timer 3
Timer 4
Flash Controler 0
Flash Controler 1
ADC
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
Quadrature Encoder
I2C0 Slave
I2C1 Slave
I2C0 Master
I2C1 Master
SPI Slave
SPI Master
UART 0
FIQ
The FIQ (Fast Interrupt reQuest) is the exception signal to
enter the FIQ mode of the processor. It is provided to service
data transferor communication channel tasks with low latency.
The FIQ interface is identical to the IRQ interface providing the
second level interrupt (highest priority). Four 32-bit registers
are dedicated to FIQ, FIQSIG, FIQEN, FIQCLR and FIQSTA.
UART 1
External IRQ0
Comparator
PSM
External IRQ1
PLA IRQ0
Bit 31 to 1 of FIQSTA are logically OR’ed to create the FIQ
signal to the core and the bit 0 of both the FIQ and IRQ
registers (FIQ source).
The logic for FIQEN and FIQCLR will not allow an interrupt
source to be enabled in both IRQ and FIQ masks. A bit set to ‘1’
in FIQEN will, as a side-effect, clear the same bit in IRQEN. A
bit set to ‘1’ in IRQEN will, as a side-effect, clear the same bit in
PLA IRQ1
External IRQ2
Rev. PrA | Page 73 of 92
ADuC7128
Preliminary Technical Data
FIQEN. An interrupt source can be disabled in both IRQEN
and FIQEN masks.
The 32-bit register dedicated to software interrupt is SWICFG
described in Table 75. This MMR allows the control of
programmed source interrupt.
Programmed interrupts
As the programmed interrupts are non-mask-able, they are
controlled by another register, SWICFG, which write into both
IRQSTA and IRQSIG registers or/and FIQSTA and FIQSIG
registers at the same time.
Table 75: SWICFG MMR Bit Descriptions
Bit
31-3
2
Description
Reserved
Programmed Interrupt-FIQ
Setting/clearing this bit correspond in setting/clearing bit 1 of FIQSTA and FIQSIG
Programmed Interrupt-IRQ
Setting/clearing this bit correspond in setting/clearing bit 1 of IRQSTA and IRQSIG
Reserved
1
0
Note that any interrupt signal must be active for at least the
equivalent of the interrupt latency time, to be detected by the
interrupt controller and to be detected by user in the
IRQSTA/FIQSTA register.
Rev. PrA | Page 74 of 92
Preliminary Technical Data
ADuC7128
TIMERS
Table 76. : Event Selection Numbers
The ADuC7128 has five general purpose Timer/Counters:
- Timer0,
- Timer1,
ES
Interrupt Number
Name
RTOS Timer (Timer ±)
±±±±±
±±±±1
±±±1±
±±±11
±±1±±
±±1±1
±±11±
±±111
±1±±±
±1±±1
±1±1±
±1±11
±11±±
±11±1
±111±
±1111
1±±±±
1±±±1
2
- Timer2 or Wake-up Timer,
- Timer3 or Watchdog Timer.
3
4
GP Timer ± (Timer 1)
Wake Up Timer (Timer 2)
Watchdog Timer (Timer 3)
GP Timer 1 (Timer 4)
Flash Control ±
Flash Control 1
ADC Channel
Quadrature Encoder
I2C Slave±
- Timer4
5
The five timers in their normal mode of operation can be either
free-running or periodic.
- In free-running mode the counter decrements/increments
from the maximum/minimum value until zero/full scale and
starts again at the maximum /minimum value.
- In periodic mode the counter decrements/increments from
the value in the Load Register(TxLD MMR,) until zero/full
scale and starts again at the value stored in the Load Register.
ꢀ
7
8
9
1±
11
12
13
14
15
1ꢀ
17
18
19
The value of a counter can be read at any time by accessing its
value register (TxVAL). Timers are started by writing in the
Control register of the corresponding timer (TxCON).
I2C Slave1
I2C Master±
In normal mode, an IRQ is generated each time the value of the
counter reaches zero, if counting down, or full-scale, if counting
up. An IRQ can be cleared by writing any value to Clear register
of the particular timer (TxICLR).
I2C Master1
SPI Slave
SPI Master
UART±
UART1
External irq±
Rev. PrA | Page 75 of 92
ADuC7128
Preliminary Technical Data
TIMER0 – LIFE-TIME TIMER
Timer0 is a general purpose 48-bit count-up, or a 16-bit count
up/down timer with a programmable prescalar. Timer0 is
clocked from the core clock, with a prescalar of 1,16, 256 or
32768. This gives a minimum resolution of 22ns when the core
is operating at 41.78MHz, and with a prescalar of 1.
Timer0 reloads the value from T0LD either when TIMER0
overflows, or immediately when T0ICLR is written.
Timer0 interface consists of six MMRS:
- T0LD is a 16-bit register which holds the 16 bit value that is
loaded into the counter. Only available in 16-bit mode.
- T0CAP is a 16-bit register which holds the 16-bit value
captured by an enabled IRQ event. Only available in 16-bit
mode.
- T0VAL0/T0VAL1 are 16-bit and 32-bit registers which hold
the 16 least significant bits and 32 most significant bits
respectively. T0VAL0 and T0VAL1 is read-only. In 16-bit
mode 16-bit T0VAL0 is used. In 48-bit mode both 16-bit
T0VAL0 and 32-bit T0VAL1 are used.
In 48-bit mode, Timer0 counts up from zero. The current
counter value may be read from T0VAL0 and T0VAL1.
In 16-Bit mode,Timer0 may count up or count down. A 16-bit
value may be written to T0LD which will be loaded into the
counter. The current counter value may be read from T0VAL0.
Timer0 has a capture register (T0CAP), which may be triggered
by a selected IRQ’s source initial assertion. Once triggered, the
current timer value is copied to T0CAP, and the timer keeps
running. This feature can be used to determine the assertion of
an event with more accuracy than by servicing an interrupt
alone.
- T0ICLR is an 8-bit register. Writing any value to this register
will clear the interrupt. Only available in 16-bit mode.
- T0CON is the configuration MMR described in Table 77.
16-bit Load
Prescaler
1 , 16, 256
or 32768
48-bit Up Counter
Timer0IRQ
Core Clock Frequency
16-Bit Up/Down Counter
Timer0 Value
Capture
IRQ[31:0]
Figure 49 : Timer 0 block diagram
Timer0 Value Register :
Timer0 Capture Register :
Name :
T0VAL0/T0VAL1
0xFFFF0304, 0xFFFF0308
0x00, 0x00
Name :
Address :
T0CAP
0xFFFF0314
Address :
Default Value :
Access :
Default Value :
Access :
0x00
Read Only
Read Only
Function :
T0VAL0 and T0VAL1 are 16-bit and 32-bit
Function :
This is a 16-bit register which holds the 16-
registers which hold the 16 least significant bits and 32 most
significant bits respectively. T0VAL0 and T0VAL1 is read-only.
In 16-bit mode 16-bit T0VAL0 is used. In 48-bit mode both 16-
bit T0VAL0 and 32-bit T0VAL1 are used.
bit value captured by an enabled IRQ event. Only available in
16-bit mode.
Rev. PrA | Page 7ꢀ of 92
Preliminary Technical Data
ADuC7128
Timer0 Control Register :
Name :
Address :
T0CON
0xFFFF030C
Default Value :
Access :
0x00
Read/Write
Function :
The 17-bit MMR configures the mode of operation of Timer0
Table 77 : T0CON MMR Bit Descriptions
Bit
Description
31-18 Reserved
17
Event Select bit:
Set by user to enable time capture of an event
Cleared by user to disable time capture of an event
1ꢀ-12 Event select range, ± to 31
The events are as described in the introduction to the timers..
11
Reserved
1±-9
8
Reserved
Count up: ( Only available in 1ꢀBit Mode )
Set by user for timer ± to count up
Cleared by user for timer ± to count down. ( Default )
Timer± enable bit:
Set by user to enable timer ±
Cleared by user to disable timer ±. ( Default )
7
ꢀ
Timer ± mode:
Set by user to operate in periodic mode
Cleared by user to operate in free-running mode. ( Default )
Reserved
5
4
Timer± Mode of Operation:
±
1
1ꢀ Bit operation ( Default )
48 Bit Operation
3-±
Prescalar:
±±±± Source clock / 1 ( Default )
±1±± Source clock / 1ꢀ
1±±± Source clock / 25ꢀ
1111 Source clock / 327ꢀ8
Timer0 Load Registers:
Timer0 Clear Register :
Name :
Address :
T0LD
0xFFFF0300
Name :
Address :
T0ICLR
0xFFFF0310
Default Value :
Access :
0x00
Read/Write
Default Value :
Access :
0x00
Write Only
Function :
This 8-bit, write-only MMR is written (with
Function :
T0LD0 is a 16-bit register which holds the
any value) by user code to refresh(reload) Timer0.
16 bit value that is loaded into the counter. Only available in
16-bit mode.
Rev. PrA | Page 77 of 92
ADuC7128
Preliminary Technical Data
TIMER1
Timer1 is a 32-bit general purpose timer, count-down or count-
up, with a programmable pre-scalar. The pre-scalar source can
the 32kHz oscillator, the core clock, or from one of two external
GPIO. This source can be scaled by a factor of 1, 16, 256 or
32768. This gives a minimum resolution of 42ns when
operating at CD zero, the core is operating at 41.78MHz, and
with a pre-scalar of 1 ( Ignoring external GPIO).
Timer1 reloads the value from T1LD either when TIMER01
overflows, or immediately when T1ICLR is written.
Timer1 Load Registers:
Name :
T1LD
Address :
Default Value :
Access :
0xFFFF0320
0x00000
Read/Write
The counter can be formatted as a standard 32-bit value or as
Hours:Minutes:Seconds:Hundreths.
Function :
T1LD is a 32 bit register which holds the 32
bit value that is loaded into the counter.
Timer1 has a capture register (T1CAP), which can be triggered
by a selected IRQ’s source initial assertion. Once triggered, the
current timer value is copied to T1CAP, and the timer keeps
running. This feature can be used to determine the assertion of
an event with increased accuracy.
Timer1 Clear Register :
Name :
T1ICLR
Address :
Default Value :
Access :
0xFFFF032C
0x00
Write Only
Timer1 interface consists of five MMRS:
Function :
This 8-bit, write-only MMR is written (with
- T1LD, T1VAL and T1CAP are 32-bit registers and hold 32-
bit unsigned integers. T1VAL and T1CAP are read-only.
- T1ICLR is an 8-bit register. Writing any value to this register
will clear the timer1 interrupt.
any value) by user code to refresh(reload) Timer1.
Timer1 Value Register :
Name :
T1VAL
- T1CON is the configuration MMR described in below.
Address :
Default Value :
Access :
0xFFFF0324
0x0000
Read Only
NOTE: If the part is in a low power mode, and Timer1 is
clocked from the GPIO or low power oscillator source
then, Timer1 will continue to be operate.
Function :
T1VAL is a 32-bit register which holds the
current value of Timer1
32-bit Load
32.768kHz Oscillator
Core Clock Frequency
Prescaler
1 , 16, 256
or 32768
32-bit Up/Down Counter
Timer1IRQ
GPIO
GPIO
Timer1 Value
Capture
IRQ[31:0]
Figure 50 : Timer 1 Block Diagram
Rev. PrA | Page 78 of 92
Preliminary Technical Data
ADuC7128
Timer1 Control Register :
Timer1 Capture Register :
Name :
T1CON
Name :
T1CAP
Address :
Default Value :
Access :
0xFFFF0328
0x0000
Read/Write
Address :
Default Value :
Access :
0xFFFF0330
0x00
Read Only
Function :
This 32-bit MMR configures the mode of
Function :
This is a 32-bit register which holds the 32-
operation of Timer1
bit value captured by an enabled IRQ event.
Table 78 : T1CON MMR Bit Descriptions
Bit
Description
31-18
Reserved
Should be set to‘±’by the user
17
Event Select bit:
Set by user to enable time capture of an event
Cleared by user to disable time capture of an event
Event select range, ± to 31
The events are as described in the introduction to the timers.
Clock select:
1ꢀ-12
11-9
±±±
±±1
±1±
Core clock ( Default )
32.7ꢀ8kHz Oscillator
P1.0
P0.6
±11
8
Count up:
Set by user for timer 1 to count up
Cleared by user for timer 1 to count down. ( Default )
Timer1 enable bit:
7
Set by user to enable timer 1
Cleared by user to disable timer 1. ( Default )
ꢀ
Timer 1 mode:
Set by user to operate in periodic mode
Cleared by user to operate in free-running mode. ( Default )
Format:
5-4
±± Binary ( Default )
±1 Reserved
1± Hr:Min:Sec:Hundredths – 23 hours to ± hour
11 Hr:Min:Sec:Hundredths – 255 hours to ± hour
Pre-Scalar:
3-±
±±±±
±1±±
1±±±
1111
Source clock / 1 ( Default )
Source clock / 1ꢀ
Source clock / 25ꢀ
Source clock / 327ꢀ8
Rev. PrA | Page 79 of 92
ADuC7128
Preliminary Technical Data
Timer2 Load Registers:
TIMER2 - WAKE-UP TIMER
Name :
T2LD
Address :
Default Value :
Access :
0xFFFF0340
0x00000
Read/Write
Timer2 is a 32-bit wake-up timer, count-down or count-up,
with a programmable prescalar. The pre-scalar is clocked
directly from 1 of 4 clock sources, namely, the Core Clock
(default selection), the internal 32.768kHz Oscillator, External
32.768kHz Watch Crystal, or the core clock. The selected clock
source can be scaled by a factor of 1, 16, 256 or 32768. The
wake-up timer will continue to run when the core clock is
disabled. This gives a minimum resolution of 22ns when
operating at CD zero, the core is operating at 41.78MHz, and
with a prescalar of 1. Capture of the current timer value is
enabled if the Timer2 interrupt is enabled via IRQEN[4].
Function :
bit value that is loaded into the counter.
T2LD is a 32 bit register which holds the 32
Timer2 Clear Register :
Name :
Address :
Default Value :
Access :
T2ICLR
0xFFFF034C
0x00
Write Only
The counter can be formatted as plain 32-bit value or as
Hours:Minutes:Seconds:Hundreths.
Function :
This 8-bit, write-only MMR is written (with
any value) by user code to refresh(reload) Timer2.
Timer2 reloads the value from T2LD either when TIMER2
overflows, or immediately when T2ICLR is written.
Timer2 Value Register :
Name :
T2VAL
0xFFFF0344
0x0000
Read Only
Timer2 interface consists of four MMRS:
Address :
Default Value :
Access :
Function :
current value of Timer2
- T2LD and T2VAL are 32-bit registers and hold 32-bit
unsigned integers. T2VAL is read-only.
- T2ICLR is an 8-bit register. Writing any value to this register
will clear the timer2 interrupt.
T2VAL is a 32-bit register which holds the
- T2CON is the configuration MMR described in Table 79.
32-bit Load
32-bit Up/Down Counter
Timer2 Value
External
32kHz Oscillator
Internal
32kHz Oscillator
Timer2IRQ
Prescaler
1, 16, 256
or 32768
Core Clock
Figure 51 : Timer 2 block diagram
Rev. PrA | Page 8± of 92
Preliminary Technical Data
ADuC7128
Timer2 Control Register :
Name :
T2CON
Address :
Default Value :
Access :
0xFFFF0348
0x0000
Read/Write
Function :
This 32-bit MMR configures the mode of operation of Timer2
Table 79 : T2CON MMR Bit Descriptions
Bit
Description
31-11 Reserved
1±-9
Clock Source Select:
±±
±1
1±
11
Core Clock ( Default )
Inernal 32.7ꢀ8kHz Oscillator
External 32.7ꢀ8kHz Watch Crystal
External 32.7ꢀ8kHz Watch Crystal
8
Count up:
Set by user for timer 2 to count up
Cleared by user for timer 2 to count down. ( Default )
Timer2 enable bit:
7
Set by user to enable timer 2
Cleared by user to disable timer 2. ( Default )
Timer 2 mode:
ꢀ
Set by user to operate in periodic mode
Cleared by user to operate in free-running mode. ( Default )
Format:
5-4
±±
±1
1±
11
Binary ( Default )
Reserved
Hr:Min:Sec:Hundredths – 23 hours to ± hour
Hr:Min:Sec:Hundredths – 255 hours to ± hour
3-±
Prescalar:
±±±± Source clock / 1 ( Default )
±1±± Source clock / 1ꢀ
1±±± Source clock / 25ꢀ ( This setting should be used in conjunction Timer2 Formats 1,± and 1,1 )
1111 Source clock / 327ꢀ8
Rev. PrA | Page 81 of 92
ADuC7128
Preliminary Technical Data
TIMER3 - WATCHDOG TIMER
memory page erase cycles, which require 20ms to complete a
single page erase cycle, and Kernel Execution..
Timer3 has two modes of operation, normal mode and
watchdog mode. The Watchdog timer is used to recover from
an illegal software state. Once enabled it requires periodic
servicing to prevent it from forcing a reset of the processor.
If T3VAL reaches 0, a reset or an interrupt occurs, depending on
T3CON[1]. To avoid a reset or an interrupt event, any value
must be written to T3ICLR before T3VAL reaches zero. This
reloads the counter with T3LD and begins a new timeout
period.
Timer3 reloads the value from T3LD either when TIMER3
overflows, or immediately when T3ICLR is written.
Normal mode:
Once watchdog mode is entered, T3LD and T3CON are write-
protected. These two registers can not be modified until a
Power On Reset event, resets the Watchdog Timer, after any
other reset event, the Watchdog Timer continues to count. The
Watchdog Timer should be configured in the initial lines of
user code to avoid an infinite loop of Watchdog Resets. User
software should only configure a minimum timeout period of
30msecs.
The Timer3 in normal mode is identical to Timer0, in 16-bit
mode of operation, except for the clock source. The clock
source is the 32.768kHz oscillator and can be scaled by a factor
of 1, 16, or 256. Timer3 also features a capture facility, which
allows the capture of the current timer value if the Timer2
interrupt is enabled via IRQEN[5].
Watchdog mode:
Timer3 is automatically halted during JTAG debug access and
will only recommence counting once JTAG has relinquished
control of the ARM7 core. By default, Timer3 continues to
count during power-down. This may be disabled by setting bit
zero in T3CON. It is recommended that the default value is
used, i.e. that the Watchdog Timer continues to count during
power-down.
Watchdog mode is entered by setting T3CON[5]. Timer3
decrements from the timeout value present in T3LD Register
until zero. The maximum timeout is 512 seconds, using the
maximum pre-scalar /256 and full-scale in T3LD.
User software should only configure a minimum timeout
period of 30msecs. This is to avoid any conflict with Flash/EE
16-bit Load
Prescaler
1, 16, 256
Watchdog Reset
Low Power
32.768kHz
16-bit Up/Down Counter
Timer3IRQ
Timer3 Value
Figure 52 : Timer3 Block Diagram
Timer3 Interface:
Timer3 Load Register :
Name :
Address :
Default Value : 0x03D7
Access :
Function :
value.
T3LD
0xFFFF0360
Timer3 interface consists of four MMRS:
- T3CON is the configuration MMR described in Table 8±
- T3LD and T3VAL are 16-bit registers (bit 0 to 15) and hold
16-bit unsigned integers. T3VAL is read-only.
- T3ICLR is an 8-bit register. Writing any value to this register
will clear the Timer3 interrupt in normal mode or will reset a
new timeout period in watchdog mode
Read/Write
This 16-bit MMR holds the Timer3 reload
Rev. PrA | Page 82 of 92
Preliminary Technical Data
ADuC7128
Timer3 Clear Register :
Timer3 Value Register :
Name :
T3ICLR
Name :
T3VAL
Address :
Default Value :
Access :
0xFFFF036C
0x00
Write Only
Address :
Default Value :
Access :
0xFFFF0364
0x03D7
Read Only
Function :
This 8-bit, write-only MMR is written (with
Function :
This 16-bit, read-only MMR holds the
any value) by user code to refresh(reload) Timer3 in watchdog
mode to prevent a watchdog timer reset event.
currentTimer3 count value.
Timer3 Control Register :
Name :
T3CON
Address :
Default Value :
Access :
0xFFFF0368
0x00
Read/Write Once Only
Function :
The 16-bit MMR configures the mode of operation of Timer3 as is described in detail in Table 80
Table 80 : T3CON MMR Bit Definition
Bit
1ꢀ-9
8
Description
These bits are reserved and should be written as ± by user code
Count Up/Down Enable
Set by user code to configure Timer3 to count up
Cleared by user code to configure Timer3 to count down.
7
ꢀ
Timer3 Enable
Set by user code to enable Timer 3
Cleared by user code to disable Timer 3. .
Timer3 Operating Mode
Set by user code to configure Timer3 to operate in periodic mode
Cleared by user to configure Timer3 to operate in free-running mode.
5
Watchdog Timer Mode Enable
Set by user code to enable watchdog mode
Cleared by user code to disable watchdog mode
Secure clear bit.
4
Set by user to use the secure clear option.
Cleared by user to disable the secure clear option by default.
3-2
Timer3 Clock(32.7ꢀ8kHz) Pre-Scalar
±±
±1
1±
11
Source clock / 1 ( Default )
Reserved
Reserved
Reserved
1
±
Watchdog Timer IRQ Enable
Set by user code to produce an IRQ instead of a reset when the watchdog reaches ±
Cleared by user code to disable the IRQ option.
PD_OFF
Set by the user code to stop Timer3 when the peripherals are powered down via bit 4 in the POWCON MMR.
Cleared by the user code to enable Timer3 when the peripherals are powered down via bit 4 in the POWCON MMR.
Rev. PrA | Page 83 of 92
ADuC7128
Preliminary Technical Data
Secure Bit Clear (Watchdog Mode Only)
The secure clear bit is provided for a higher level of protection. When set, a specific sequential value must be written to T3ICLR to avoid a
watchdog reset. The value is a sequence generated by the 8-bit linear feedback shift register (LFSR) polynomial = X8 + X6 + X5 + X + 1 as
shown Figure 53.
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
7
6
5
4
3
2
1
0
CLOCK
Figure 53. 8-Bit LFSR
The initial value or seed is written to T3ICLR before entering watchdog mode. After entering watchdog mode, a write to T3ICLR must
match this expected value. If it matches, the LFSR is advanced to the next state when the counter reload happens. If it fails to match the
expected state, reset is immediately generated, even if the count has not yet expired. The value 0×00 should not be used as an initial seed
due to the properties of the polynomial. The value 0×00 is always guaranteed to force an immediate reset. The value of the LFSR can not
be read; it must be tracked/generated in software.
Example of a sequence:
1. Enter initial seed, 0×AA, in T3ICLR before starting timer3 in watchdog mode.
2. Enter 0×AA in T3ICLR; timer3 is reloaded.
3. Enter 0×37 in T3ICLR; timer3 is reloaded.
4. Enter 0×6E in T3ICLR; timer3 is reloaded.
5. Enter 0×66. 0×DC was expected; the watchdog reset the chip.
Rev. PrA | Page 84 of 92
Preliminary Technical Data
ADuC7128
TIMER4
overflows, or immediately when T4ICLR is written.
Timer4 is a 32-bit general purpose timer, count-down or count-
up, with a programmable pre-scalar. The pre-scalar source can
the 32kHz oscillator, the core clock, or from one of two external
GPIO. This source can be scaled by a factor of 1, 16, 256 or
32768. This gives a minimum resolution of 42ns when
operating at CD zero, the core is operating at 41.78MHz, and
with a pre-scalar of 1 ( Ignoring external GPIO).
Timer4 Load Registers:
Name :
T4LD
Address :
Default Value :
Access :
0xFFFF0380
0x00000
Read/Write
Function :
bit value that is loaded into the counter.
T4LD is a 32 bit register which holds the 32
The counter can be formatted as a standard 32-bit value or as
Hours:Minutes:Seconds:Hundreths.
Timer4 has a capture register (T4CAP), which can be triggered
by a selected IRQ’s source initial assertion. Once triggered, the
current timer value is copied to T4CAP, and the timer keeps
running. This feature can be used to determine the assertion of
an event with increased accuracy.
Timer4 Clear Register :
Name :
T4ICLR
Address :
Default Value :
Access :
0xFFFF038C
0x00
Write Only
Function :
This 8-bit, write-only MMR is written (with
Timer4 interface consists of five MMRS:
any value) by user code to refresh(reload) Timer4.
- T4LD, T4VAL and T4CAP are 32-bit registers and hold 32-
bit unsigned integers. T4VAL and T4CAP are read-only.
- T4ICLR is an 8-bit register. Writing any value to this register
will clear the timer1 interrupt.
Timer4Value Register :
Name :
Address :
Default Value :
Access :
T4VAL
0xFFFF0384
0x0000
Read Only
- T4CON is the configuration MMR described in Table 81.
NOTE: If the part is in a low power mode, and Timer4 is
clocked from the GPIO or oscillator source then,
Timer4 will continue to be operate.
Function :
current value of Timer4
T4VAL is a 32-bit register which holds the
Timer4 reloads the value from T4LD either when TIMER04
32-bit Load
32.768kHz Oscillator
Core Clock Frequency
Prescaler
1 , 16, 256
or 32768
32-bit Up/Down Counter
Timer4IRQ
GPIO
GPIO
Timer1 Value
Capture
IRQ[31:0]
Figure 54 : Timer 4 Block Diagram
Rev. PrA | Page 85 of 92
ADuC7128
Preliminary Technical Data
Timer4 Control Register :
Timer4 Capture Register :
Name :
T4CON
Name :
T4CAP
Address :
0xFFFF0388
Address :
Default Value :
Access :
0xFFFF0390
0x00
Read Only
Default Value :
Access :
0x0000
Read/Write
Function :
This 32-bit MMR configures the mode of
Function :
This is a 32-bit register which holds the 32-
operation of Timer4
bit value captured by an enabled IRQ event.
Table 81 : T4CON MMR Bit Descriptions
Bit
Description
31-18
Reserved
Should be set to‘±’by the user
17
Event Select bit:
Set by user to enable time capture of an event
Cleared by user to disable time capture of an event
Event select range, ± to 31
The events are as described in the introduction to the timers.
Clock select:
1ꢀ-12
11-9
±±±
±±1
±1±
Core clock ( Default )
32.7ꢀ8kHz Oscillator
P4.6
P4.7
±11
8
Count up:
Set by user for timer 4 to count up
Cleared by user for timer 4 to count down. ( Default )
Timer 4 enable bit:
7
Set by user to enable timer 4
Cleared by user to disable timer 4. ( Default )
ꢀ
Timer 4 mode:
Set by user to operate in periodic mode
Cleared by user to operate in free-running mode. ( Default )
Format:
5-4
±± Binary ( Default )
±1 Reserved
1± Hr:Min:Sec:Hundredths – 23 hours to ± hour
11 Hr:Min:Sec:Hundredths – 255 hours to ± hour
Pre-Scalar:
3-±
±±±±
±1±±
1±±±
1111
Source clock / 1 ( Default )
Source clock / 1ꢀ
Source clock / 25ꢀ
Source clock / 327ꢀ8
Rev. PrA | Page 8ꢀ of 92
Preliminary Technical Data
ADuC7128
Finally, on the CSP package, the paddle on the bottom of the
package should be soldered to a metal plate to provide
mechanical stability. This metal plate should be connected to
ground.
ADuC7128 Hardware Design considerations
POWER SUPPLIES
The ADuC7128 operational power supply voltage range is 3.0V
to 3.6V. Separate analog and digital power supply pins (AVDD
and IOVDD, respectively) allow AVDD to be kept relatively free
of noisy digital signals often present on the system IOVDD line.
In this mode, the part can also operate with split supplies; that
is, using different voltage supply levels for each supply. For
example, this means that the system can be designed to operate
with a IOVDD voltage level of 3.3 V while the AVDD level can be
at 3 V, or vice versa if required. A typical split supply
configuration is shown in Figure 55.
Linear Voltage regulator
The ADuC7128 requires a single 3.3V supply but the core logic
requires a 2.5V supply. An on-chip linear regulator generates the
2.5V from IOVDD for the core logic. LVDD pin 21 is the 2.5V
supply for the core logic. The DAC logic and PLL logic also
require a 2.5V supply, this must be connected externally from
the LVdd pin to the DACVdd and PVdd pins. An external
compensation capacitor of 0.47 µF must be connected between
LVDD and DGND (as close as possible to these pins) to act as a
tank of charge as shown inFigure 57. 0.1 µF decoupling
capacitors also must be placed as close as possible to the PVdd
and DACVdd pins.
DIGITAL SUPPLY
ANALOG SUPPLY
10µF
+
-
10µF
+
-
IOVDD
AVDD
LVDD
0.1µF
PVDD
0.1µF
GNDREF
0.1µF
DACVDD
LV
DD
0.47µF
DACGND
AGND
PV
DD
0.1µF
IOGND
DACV
DD
REFGND
0.47µF
Figure 55: External dual supply connections
Figure 57: voltage regulator connections
As an alternative to providing two separate power supplies, the
user can help keep AVDD quiet by placing a small series resistor
and/or ferrite bead between it and IOVDD, and then decoupling
AVDD separately to ground. An example of this configuration is
shown in Figure 56. With this configuration other analog
circuitry (such as op amps, voltage reference, and so on) can be
powered from the AVDD supply line as well.
The LVDD pin should not be used for any other chip. It is also
recommended that the IOVDD has excellent power supply
decoupling this to help improving line regulation performance
of the on-chip voltage regulator.
GROUNDING AND BOARD LAYOUT
RECOMMENDATIONS
BEAD
DIGITAL SUPPLY
10uF
+
-
1.6V
10uF
As with all high resolution data converters, special attention
must be paid to grounding and PC board layout of ADuC7128-
based designs in order to achieve optimum performance from
the ADCs and DAC.
IOVDD
AVDD
LVDD
0.1µF
PVDD
0.1µF
GNDREF
0.1µF
DACVDD
0.47µF
DACGND
AGND
IOGND
Although the ADuC7128 has separate pins for analog and
digital ground (AGND and IOGND), the user must not tie
these to two separate ground planes unless the two ground
planes are connected together very close to the ADuC7128, as
illustrated in the simplified example of Figure 58a. In systems
where digital and analog ground planes are connected together
somewhere else (at the system’s power supply for example),
they cannot be connected again near the ADuC7128 since a
ground loop would result. In these cases, tie the ADuC7128’s
AGND and IOGND Pins all to the analog ground plane, as
illustrated in Figure 58b. In systems with only one ground
plane, ensure that the digital and analog components are
physically separated onto separate halves of the board such that
digital return currents do not flow near analog circuitry and
vice versa. The ADuC7128 can then be placed between the
REFGND
Figure 56: external single supply connections
Notice that in both Figure 56 and Figure 57, a large value (10
µF) reservoir capacitor sits on IOVDD and a separate 10 µF
capacitor sits on AVDD. Also, local small-value (0.1 µF)
capacitors are located at each AVDD and IOVDD pin of the chip.
As per standard design practice, be sure to include all of these
capacitors, and ensure the smaller capacitors are close to each
AVDD pin with trace lengths as short as possible. Connect the
ground terminal of each of these capacitors directly to the
underlying ground plane. It should also be noted that, at all
times, the analog and digital ground pins on the ADuC7128
must be referenced to the same system ground reference point.
Rev. PrA | Page 87 of 92
ADuC7128
Preliminary Technical Data
digital and analog sections, as illustrated in Figure 58c.
XCLKI and XCLKO as shown Figure 59. External capacitors
should be connected as per the crystal manufacturer’s
recommendations. Note that the crystal pads already have an
internal capacitance of typically 10pF. User should ensure that
the total capacitance (10pF internal + external capacitance)
doesn’t exceed the manufacturer rating.
PLACE DIGITAL
PLACE ANALOG
COMPONENTS HERE
a.
b.
c.
COMPONENTS HERE
AGND
DGND
This 32kHz crystal allows the PLL to lock correctly to give a
frequency of 41.78 MHz. If no external crystal is present, the
internal oscillator will be used to give a frequency of 41.78MHz
±3% typically.
PLACE ANALOG
COMPONENTS
HERE
PLACE DIGITAL
COMPONENTS
HERE
XCLKO
12pF
AGND
DGND
32.768kHz
TO INTERNAL
PLL
12pF
XCLKI
Figure 59: external parallel resonant crystal connections
To use an external source clock input instead of the PLL, bit 1
and bit 0 of PLLCON must be modified. The external clock
uses pin 17, XCLK.
PLACE ANALOG
COMPONENTS
HERE
PLACE DIGITAL
COMPONENTS
HERE
GND
XCLKI
Figure 58:. System grounding schemes
EXTERNAL
TO FREQUENCY
CLOCK
In all of these scenarios, and in more complicated real-life
applications, keep in mind the flow of current from the supplies
and back to ground. Make sure the return paths for all currents
are as close as possible to the paths the currents took to reach
their destinations. For example, do not power components on
the analog side of Figure 58b with IOVDD since that would force
return currents from IOVDD to flow through AGND. Also, try
to avoid digital currents flowing under analog circuitry, which
could happen if the user placed a noisy digital chip on the left
half of the board in Figure 58c. Whenever possible, avoid large
discontinuities in the ground plane(s) (such as are formed by a
long trace on the same layer), since they force return signals to
travel a longer path. And of course, make all connections to the
ground plane directly, with little or no trace separating the pin
from its via to ground.
DIVIDER
SOURCE
XCLK
Figure 60:connecting an external clock source
Whether using the internal PLL or an external clock source, the
ADuC7128’s specified operational clock speed range is 50kHz
to 41.78 MHz to ensure correct operation of the analog
peripherals and Flash/EE.
POWER-ON RESET OPERATION
An internal POR (Power-On Reset) is implemented on the
ADuC7128. For LVDD below 2.45 V, the internal POR will hold
the ADuC7128 in reset. As LVDD rises above 2.45 V, an internal
timer will time out for typically 64 ms before the part is released
from reset. The user must ensure that the power supply IOVDD
has reached a stable 3.0 V minimum level by this time. Likewise
on power-down, the internal POR will hold the ADuC7128 in
reset until LVDD has dropped below 2.45V. Figure 61 illustrates
the operation of the internal POR in detail.
If the user plans to connect fast logic signals (rise/fall time < 5
ns) to any of the ADuC7128’s digital inputs, add a series
resistor to each relevant line to keep rise and fall times longer
than 5 ns at the ADuC7128 input pins. A value of 100Ω or
200Ω is usually sufficient to prevent high speed signals from
coupling capacitively into the ADuC7128 and affecting the
accuracy of ADC conversions.
CLOCK OSCILLATOR
The clock source for the ADuC7128 can be generated by the
internal PLL or by an external clock input. To use the internal
PLL, connect a 32.768kHz parallel resonant crystal between
Rev. PrA | Page 88 of 92
Preliminary Technical Data
ADuC7128
3.3V
IOVDD
2.6V
2.4V TYP
2.4V TYP
LVDD
64ms TYP
POR
0.12ms TYP
MRST
Figure 61:. ADuC7128 Internal Power-on-Reset operation
TYPICAL SYSEM CONFIGURATION
A typical ADuC7128 configuration is shown in Figure 62. It summarizes some of the hardware considerations discussed in the previous
paragraphs.
Figure 62:. Typical System Configuration
Rev. PrA | Page 89 of 92
ADuC7128
Preliminary Technical Data
DEVELOPMENT TOOLS
An entry level, low cost development system is available for the
ADuC7128 family. This system consists of the following PC-
based (Windows® compatible) hardware and software
development tools:
IN-CIRCUIT SERIAL DOWNLOADER
The Serial Downloader is a Windows application that allows
the user to serially download an assembled program to the on-
chip program FLASH/EE memory via the serial port on a
standard PC.
Hardware:
- ADuC7128 Evaluation board
- Serial Port programming cable
- JTAG emulator
Software:
- Integrated Development Environment, incorporating
assembler, compiler and non intrusive JTAG-based
debugger
- Serial Downloader software
- Example Code
Miscellaneous:
- CD-ROM Documentation
Rev. PrA | Page 9± of 92
Preliminary Technical Data
OUTLINE DIMENSIONS
ADuC7128
On the CSP package, the paddle on the bottom of the package should be soldered to a metal plate to provide mechanical stability. This
metal plate should be connected to ground.
64-Lead Lead Frame Chip Scale Package [LFCSP]
9 x 9 mm Body
(CP-64-1)
Dimensions shown in millimeters
0.30
9.00
BSC SQ
0.25
0.18
0.60 MAX
0.60 MAX
64
49
48
PIN 1
INDICATOR
1
PIN 1
INDICATOR
4.85
4.70 SQ
4.55
8.75
BSC SQ
EXPOSED PAD
(BOTTOM VIEW)
TOP
VIEW
0.45
0.40
0.35
33
3 2
1 6
17
7.50
REF
0.80 MAX
0.65 TYP
1.00
0.85
0.80
12 ° MAX
0.05 MAX
0.02 NOM
0.50 BSC
0.20 REF
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-VMMD
Figure 63. 64-Lead Frame Chip Scale Package [LFCSP] (CP-64-1)—Dimensions shown in millimetres
Rev. PrA | Page 91 of 92
ADuC7128
NOTES
Preliminary Technical Data
Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent
Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
PR06020-0-3/06(PrA)
Rev. PrA | Page 92 of 92
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