ADUC846_技术文档

PRELIMINARY TECHNICAL DATA

MicroConverter, Dual 16-Bit ADCs

with Embedded 62kB FLASH MCU

a

Preliminary Technical Data

ADuC846

FEATURES

FUNCTIONAL BLOCK DIAGRAM

High Resolution Sigma-Delta ADCs

Two Independent ADCs (16-Bit Resolution)

16-Bit No Missing Codes

16-Bit rms (16 Bit p-p) Effective Resolution @ 20 Hz

Offset Drift 10 nV/°C, Gain Drift 0.5 ppm/°C

Memory

62 Kbytes On-Chip Flash/EE Program Memory

4 Kbytes On-Chip Flash/EE Data Memory

Flash/EE, 100 Year Retention, 100 Kcycles Endurance

3 Levels of Flash/EE Program Memory Security

In-Circuit Serial Download (No External Hardware)

High Speed User Download (5 Seconds)

2304 Bytes On-Chip Data RAM

8051-Based Core

8051 Compatible Instruction Set

High Performance Single Cycle Core

32 kHz External Crystal

On-Chip Programmable PLL (12.58 MHz Max)

3 × 16-Bit Timer/Counter

26 Programmable I/O Lines

11 Interrupt Sources, Two Priority Levels

GENERAL DESCRIPTION

Dual Data Pointer, Extended 11-Bit Stack Pointer

On-Chip Peripherals

The ADuC846 is a complete smart transducer front end, integrating

two high resolution sigma-delta ADCs, an 8-bit MCU, and

program/data Flash/EE memory on a single chip.

Internal Power on Reset Circuit

12-Bit Voltage Output DAC

Dual 16-Bit S-D DACs/PWMs

The two independent ADCs (primary and auxiliary) include a

temperature sensor and a PGA (allowing direct measurement of low

level signals). The ADCs with on-chip digital filtering and

programmable output data rates are intended for the measurement of

wide dynamic range, low frequency signals, such as those in weigh

scale, strain-gage, pressure transducer, or temperature measurement

applications.

On-Chip Temperature Sensor

Dual Excitation Current Sources

Time Interval Counter (Wakeup/RTC Timer)

®

2 ®

UART, SPI , and I C Serial I/O

High Speed Baud Rate Generator (incl 115,200)

Watchdog Timer (WDT)

Power Supply Monitor (PSM)

The device operates from a 32 kHz crystal with an on-chip PLL

generating a high frequency clock of 12.58 MHz. This clock is routed

through a programmable clock divider from which the MCU core

clock operating frequency is generated. The microcontroller core is an

optimized single cycle 8052 offering up to 12.58MIPs performance

while maintaining the 8051 instruction set compatibility.

Power

Normal: 2.3mA Max @ 3.6 V (Core CLK = 1.57 MHz)

Power-Down: 20µA Max with Wakeup Timer Running

Specified for 3 V and 5 V Operation

Package and Temperature Range

52-Lead MQFP (14 mm × 14 mm), –40°C to +125°C

56-Lead CSP (8 mm × 8 mm), –40°C to +85°C

APPLICATIONS

62 Kbytes of nonvolatile Flash/EE program memory, 4 Kbytes of

nonvolatile Flash/EE data memory, and 2304 bytes of data RAM are

provided on-chip. The program memory can be configured as data

memory to give up to 60 Kbytes of NV data memory in data logging

applications.

Intelligent Sensors

WeighScales

Portable Instrumentation, Battery Powered Systems

4-20mA Transmitters

On-chip factory firmware supports in-circuit serial download and

debug modes (via UART), as well as single-pin emulation mode via

the EA pin. The ADuC846 is supported by a QuickStart™

development system featuring low cost software and hardware

development tools.

Data Logging

Precision System Monitoring

REV. PrA

Information furnished by Analog Devices is believed to be accurate and reliable.

However, no responsibility is assumed by Analog Devices for its use, nor for any

infringements of patents or other rights of third parties that may result from its use.

No license is granted by implication or otherwise under any patent or patent rights

of Analog Devices. Trademarks and registered trademarks are the property of

their respective companies.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700

Fax: 781/326-8703

www.analog.com

PRELIMINARY TECHNICAL DATA

SPECIFICATIONS¹

(AVDD = 2.7 V to 3.6 V or 4.75 V to 5.25 V, DVDD = 2.7 V to 3.6 V or 4.75 V to 5.25 V, REFIN(+)

= 2.5 V, REFIN(–) = AGND; AGND = DGND = 0 V; XTAL1/XTAL2 = 32.768 kHz Crystal; all

specifications T_MIN, to T_MAXunless otherwise noted.).

PARAMETER

MIN

TYP

MAX

UNITS

CONDITION

PRIMARY ADC

Conversion Rate

No Missing Codes²

Resolution

5.35

16

19.79

105

Hz

On Both Channels

Bits

19.79Hz Update Rate

13.5

16

Bits Pk-Pk

Range = ± 20mV, 20Hz Update Rate

Range = ± 2.56V, 20Hz Update Rate

Output Noise varies with selected Update Rates

and Gain Range

Output Noise

See Tables X and XI in

ADuC836 Datasheet

Integral Non Linearity

Offset Error³

± 15

ppm of FSR 1 LSB₁₆

± 3

± 10

± 0.5

± 2

µV

nV/°C

µV

Offset Error Drift (vs. Temp)

Full-Scale Error⁴

Gain Error Drift⁵(vs. Temp)

ADC Range Matching

Power Supply Rejection

ppm/°C

AIN=18mV

µV

dBs

80

95

AIN=1V, Range=± 2.56V

113

AIN=7.8mV, Range=± 20mV

Common Mode DC Rejection

On AIN

dBs

@DC, AIN=7.8mV, Range=± 20mV

@DC, AIN=1V, Range=± 2.56V

20 Hz Update Rate

On AIN

113

Common Mode 50/60Hz Rejection

On AIN

95

90

dBs

50/60Hz ± 1Hz, AIN=7.8mV, Range=± 20mV

50/60Hz ± 1Hz, AIN=1V, Range=± 2.56V

On AIN

Normal Mode 50/60 Hz Rejection

On AIN

60

dBs

50/60Hz ± 1Hz, 20 Hz Update Rate

PRIMARY ADC ANALOG INPUTS

Differential Input Voltage Ranges^9,10

Bipolar Mode (ADC0CON.5 = 0)

± 1.024 x V_REF/GAIN

V

V_REF= REFIN(+) - REFIN(-) (or Int 1.25V Ref)

GAIN = 1 to 128

Unipolar Mode (ADC0CON.5 = 1)

Analog Input Current²

0 Æ 1.024 x REFIN/GAIN

V_REF= REFIN(+) - REFIN(-)

GAIN=1 to 128

± 1

nA

T_MAX= 85°C

± 5

T_MAX= 125°C

Analog Input Current Drift

Absolute AIN Voltage Limits²

± 5

pA/°C

V

T_MAX= 85°C

± 15

T_MAX= 125°C

A_GND+ 0.1

1

AV_DD– 0.1

AV_DD

EXTERNAL REFERENCE INPUTS

REFIN(+) to REFIN(–) Range²

2.5

V

µA/V

nA/V/°C

V

Average Reference Input Current

Average Reference Input Current Drift

‘NO Ext. REF’ Trigger Voltage

+/- 1

Both ADCs Enabled

+/- 0.01

0.3

0.65

NOXREF bit active if VREF<0.3V

NOXREF bit Inactive if VREF>0.65

@DC, AIN=1V, Range=± 2.56V

Common Mode DC Rejection

125

90

dBs

Common Mode 50/60Hz Rejection

Normal Mode 50/60 Hz Rejection

50/60Hz ± 1Hz, AIN=1V, Range=± 2.56V

50/60Hz ± 1Hz, 59.4 Hz Update Rate

60

-2-

REV. PrA

PRELIMINARY TECHNICAL DATA

ADuC846

PARAMETER

MIN

TYP

MAX

UNITS

CONDITION

AUXILIARY ADC

No Missing Codes²

Resolution

16

Bits

20 Hz Update Rate

16

Bits Pk-Pk

Range = ± 2.5V, 20Hz Update Rate

Output Noise

See Table XII in ADuC836

Output Noise varies with selected Update Rates

Datasheet

Integral Non Linearity

Offset Error³

± 15

ppm of FSR 1 LSB₁₆

-2

LSB

µV /°C

LSBs

Offset Error Drift

1

Fullscale Error⁴

-2.5

Gain Error Drift⁵

Power Supply Rejection

Normal Mode 50/60 Hz Rejection

On AIN

± 0.5

80

ppm/°C

dBs

AIN=1V, Range=± 2.56V

60

dBs

50/60Hz ± 1Hz, 19.79Hz Update Rate

On REFIN

AUXILIARY ADC ANALOG INPUTS

Differential Input Voltage Ranges^{9, 10}

(Bipolar Mode – ADC0CON3 = 0)

(Unipolar Mode – ADC0CON3 = 1)

Average Analog Input Current

± REFIN

V

REFIN=REFIN(+)-REFIN(-) (or Int 1.25V Ref)

0 Æ REFIN

125

V

nA/V

pA/V/°C

V

Analog Input Current Drift

± 2

Absolute AIN Voltage Limits^{2, 11}

A_GND

- 0.03

A_VDD

+ 0.03

ADC SYSTEM CALIBRATION

Full Scale Calibration Limit

Zero Scale Calibration Limit

Input Span

+1.05 x FS

2.1 x FS

V

-1.05 x FS

0.8 x FS

DAC

Voltage Range

0 Æ V_REF

V

DACCON.2 = 0

0 Æ AV_DD

DACCON.2 = 1

Resistive Load

Capactive Load

Output Impedance

I_SINK

10

100

0.5

50

From DAC Output to AGND

kΩ

pF

Ω

µA

DC Specifications⁷

Resolution

12

Relative Accuracy

Differential NonLinearity

Offset Error

± 3

± 1

LSBs

Bit

mV

%

-1

Guaranteed 12-Bit Monotonic

± 50

± 1

Gain Error⁸

AV_DDRange

V_REFRange

%

AC Specifications^2,7

Voltage Output Settling Time

Digital to Analog Glitch Energy

15

10

us

Setling time to 1LSB of final value

1 LSB change at major carry

nVs

REV. PrA

-3-

PRELIMINARY TECHNICAL DATA

ADuC846 SPECIFICATIONS¹

PARAMETER

MIN

TYP

MAX

UNITS

CONDITION

INT REFERENCE

ADC Reference

Reference Voltage

1.237

1.25

45

1.2625

V

initial tolerance @ 25°C, VDD=5V

Power Supply Rejection

dBs

Reference Tempco

100

ppm/°C

DAC Reference

Reference Voltage

2.475

2.5

50

1.525

V

initial tolerance @ 25°C, VDD=5V

Power Supply Rejection

dBs

Reference Tempco

± 100

ppm/°C

TEMPERATURE SENSOR

Accuracy

+/- 2

90

°C

Thermal Impedance

°C/W

MQFP Package

CSP Package

52

TRANSDUCER BURNOUT CURRENT SOURCES

AIN+ Current

-100

100

nA

AIN+ is the selected positive input to the

primary ADC

AIN- Current

AIN- is the selected negative input to the

primary ADC

Initial Tolerance at 25°C

Drift

+/- 10

0.03

%

%/°C

EXCITATION CURRENT SOURCES

Output Current

-200

+/-10

200

+/-1

20

Available from each Current Source

µA

%

Initial Tolerance at 25°C

Drift

ppm/°C

%

Initial Current Matching at 25°C

Drift Matching

Matching between both Current Sources

AV_DD=5V +/- 5%

ppm/°C

µA/V

V

Line Regulation (AV_DD

)

1

Load Regulation

0.1

Output Compliance

A_GND

2.63

AV_DD-0.6

V

POWER SUPPLY MONITOR (PSM)

AV_DDTrip Point Selection Range

AV_DDTrip Point Accuracy

4.63

V

%

V

Four Trip Points selectable in this range

T_MAX= 85°C

+/- 3.0

4.63

AV_DDTrip Point Accuracy

T_MAX= 125°C

DV_DDTrip Point Selection Range

DV_DDTrip Point Accuracy

2.63

Four Trip Points selectable in this range

T_MAX= 85°C

+/- 3.0

%

DV_DDTrip Point Accuracy

T_MAX= 125°C

CRYSTAL OSCILLATOR (XTAL 1AND XTAL2)

Logic Inputs, XTAL1 Only²

V_INL, Input Low Voltage

0.8

0.4

V

DV_DD= 5V

DV_DD= 3V

DV_DD= 5V

DV_DD= 3V

V_INH, Input Low Voltage

3.5

2.5

V

XTAL1 Input Capacitance

XTAL2 Output Capacitance

18

pF

-4-

REV. PrA

PRELIMINARY TECHNICAL DATA

ADuC846

PARAMETER

MIN

TYP

MAX

UNITS

CONDITION

LOGIC INPUTS

All Inputs except SCLOCK, RESET

and XTAL1²

V_INL, Input Low Voltage

0.8

0.4

V

DV_DD= 5V

DV_DD= 3V

V_INH, Input Low Voltage

SCLOCK and RESET Only

(Schmidt Triggered Inputs) ²

V_T+

2.0

1.3

0.95

0.8

3.0

2.5

V

DV_DD= 5V

DV_DD= 3V

V_T-

1.4

DV_DD= 5V

0.4

1.1

DV_DD= 3V

V_T+- V_T-

0.3

0.85

DV_DD= 5V or 3V

Input Currents

2.0

-10

V

+/- 10

-40

+/-10

105

+/-10

-660

-75

V

_IN= 0V or V_DD

Port 0, P1.2ÆP1.7, EA

µA

pF

SCLOCK, MOSI,MISO SS¹³

V

_IN= 0V, DV_DD=5V, Internal Pullup

V_IN= DV_DD, DV_DD=5V

V_IN= 0V, DV_DD=5V

RESET

35

V_IN= DV_DD, DV_DD=5V, Internal Pull-Down

V_IN= DV_DD, DV_DD=5V

V_IN= 2V, DV_DD=5V

P1.0, P1.1, Port 2, Port 3

-180

-20

V_IN= 0.45V, DV_DD=5V

All Digital Inputs

Input Capacitance

5

LOGIC OUTPUTS

All Digital Outputs except XTAL2²

V_OH, Output High Voltage

2.4

V

DV_DD= 5V, I_SOURCE= 80 µA

DV_DD= 3V, I_SOURCE= 20 µA

I_SINK= 8mA, SCLOCK, MOSI/SDATA

I_SINK= 10mA, P1.0, P1.1

V_OL, Output Low Voltage¹⁴

0.8

V

0.8

V

I_SINK= 1.6mA, All Other Outputs

Floating State Leakage Current

Floating State Output Capacitance

+/-10

µA

pF

START UP TIME

At Power On

300

3

ms

us

After External RESET in Normal Mode

After WDT RESET in Normal Mode

From Idle Mode

3

Controlled via WDCON SFR

PLLCON.7 = 0

10

From Power-Down Mode

Oscillator Running

Wakeup with INT0 Interrupt

Wakeup with SPI Interrupt

Wakeup with TIC Interrupt

Wakeup with External RESET

Oscillator Powered Down

Wakeup with INT0 Interrupt

Wakeup with SPI Interrupt

Wakeup with External RESET

20

3

us

PLLCON.7 = 1

20

5

us

ms

REV. PrA

-5-

PRELIMINARY TECHNICAL DATA

ADuC846 SPECIFICATIONS¹

PARAMETER

MIN

TYP

MAX

UNITS

CONDITION

FLAH/EE MEMORY RELIABILITY CHARACTERISTICS

Endurance¹⁶

100,000 700,000

100

Cycles

Data Retention¹⁷

POWER REQUIREMENTS

Power Supply Voltages

AV_DD3V Nominal

2.7

4.75

2.7

3.6

5.25

3.6

V

AV_DD5V Nominal

DV_DD3V Nominal

DV_DD5V Nominal

4.75

5.25

4.75V < DVDD <5.25V, AVDD= 5.25V

5V POWER CONSUMPTION

Normal Mode^{18, 19}

DV_DDCurrent

4

mA

µA

core clock = 1.57MHz

core clock = 12.58MHz

13

16

AV_DDCurrent

Power-Down Mode^{18, 19}

DV_DDCurrent

180

53

100

30

80

1

T_MAX= 85°C; Osc ON;TIC ON

T_MAX= 125°C; Osc ON; TIC ON

T_MAX= 85°C; Osc OFF

T_MAX= 125°C; Osc OFF

T_MAX= 85°C; Osc ON or OFF

T_MAX= 125°C; Osc ON or OFF

µA

DV_DDCurrent

AV_DDCurrent

3

Typical Additional Peripheral Currents (AI_DDand D I_DD

)

Primary ADC

1

mA

µA

Auxiliary ADC

0.5

50

Power Supply Monitor

DAC

150

400

Dual Excitation Current Sources

4.75V < DVDD <5.25V, AVDD= 5.25V

3V POWER CONSUMPTION

Normal Mode^{18, 19}

DV_DDCurrent

2.3

10

mA

µA

core clock = 1.57MHz

core clock = 12.58MHz

8

AV_DDCurrent

Power-Down Mode^{18, 19}

DV_DDCurrent

180

20

40

T_MAX= 85°C; Osc ON;TIC ON

T_MAX= 125°C; Osc ON; TIC ON

Osc OFF

T_MAX= 125°C; Osc OFF

T_MAX= 85°C; Osc ON or OFF

T_MAX= 125°C; Osc ON or OFF

µA

DV_DDCurrent

AV_DDCurrent

10

80

1

3

-6-

REV. PrA

PRELIMINARY TECHNICAL DATA

ADuC846

NOTES

1

Temperature Range for ADuC844BS (MQFP package) is –40°C to +125°C.

Temperature Range for ADuC844BCP (CSP package) is –40°C to +85°C.

2

3

These numbers are not production tested but are guaranteed by design and/or characterization data on production release.

System Zero-Scale Calibration can remove this error.

4

^{The primary ADC is factory calibrated at 25°C with AVDD = DVDD = 5 V yielding this full-scale error of 10}µV. If user power supply or temperature

^{conditions are significantly different from these, an Internal Full-Scale Calibration will restore this error to 10}µV. A system zero-scale and full-scale

calibration will remove this error altogether.

5

6

Gain Error Drift is a span drift. To calculate Full-Scale Error Drift, add the Offset Error Drift to the Gain Error Drift times the full-scale input.

The auxiliary ADC is factory calibrated at 25°C with AVDD = DVDD = 5 V yielding this full-scale error of –2.5 LSB. A system zero-scale and full-scale

calibration will remove this error altogether.

7

8

9

DAC linearity and ac specifications are calculated using: reduced code range of 48 to 4095, 0 to VREF, reduced code range of 100 to 3950, 0 to VDD.

Gain Error is a measure of the span error of the DAC.

In general terms, the bipolar input voltage range to the primary ADC is given by RangeADC = ±(VREF 2^RN)/125, where:

VREF = REFIN(+) to REFIN(–) voltage and VREF = 1.25 V when internal ADC VREF is selected.

RN = decimal equivalent of RN2, RN1, RN0

e.g., VREF = 2.5 V and RN2, RN1, RN0 = 1, 1, 0 the RangeADC = ±1.28 V, In unipolar mode, the effective range is 0 V to 1.28 V in our example.

10 1.25 V is used as the reference voltage to the ADC when internal VREF is selected via XREF0 and XREF1 bits in ADC0CON and ADC1CON, respectively.

11 In bipolar mode, the Auxiliary ADC can only be driven to a minimum of AGND – 30 mV as indicated by the Auxiliary ADC absolute AIN voltage limits. The

bipolar range is still –VREF to +VREF; however, the negative voltage is limited to –30 mV.

12 The ADuC846BCP (CSP Package) has been qualified and tested with the base of the CSP Package floating.

13 Pins configured in SPI Mode, pins configured as digital inputs during this test.

14 Pins configured in I²C Mode only.

15 Flash/EE Memory Reliability Characteristics apply to both the Flash/EE program memory and Flash/EE data memory.

16 Endurance is qualified to 100 Kcycles as per JEDEC Std. 22 method A117 and measured at –40 °C, +25°C, +85°C, and +125°C. Typical endurance at 25°C is

700 Kcycles.

17 Retention lifetime equivalent at junction temperature (TJ) = 55°C as per JEDEC Std. 22, Method A117. Retention lifetime based on an activation energy of

0.6eV will derate with junction temperature.

18 Power Supply current consumption is measured in Normal, Idle, and Power-Down Modes under the following conditions:

Normal Mode: Reset = 0.4 V, Digital I/O pins = open circuit, Core Clk changed via CD bits in PLLCON, Core Executing internal software loop.

Idle Mode: Reset = 0.4 V, Digital I/O pins = open circuit, Core Clk changed via CD bits in PLLCON, PCON.0 = 1, Core Execution suspended in idle mode.

Power-Down Mode: Reset = 0.4 V, All P0 pins and P1.2–P1.7 Pins = 0.4 V, All other digital I/O pins are open circuit, Core Clk changed via CD bits in

PLLCON, PCON.1 = 1, Core Execution suspended in power-down mode, OSC turned ON or OFF via OSC_PD bit (PLLCON.7) in PLLCON SFR.

19 DVDD power supply current will increase typically by 3 mA (3 V operation) and 10 mA (5 V operation) during a Flash/EE memory program or erase cycle.

Specifications subject to change without notice

REV. PrA

-7-

PRELIMINARY TECHNICAL DATA

ADuC846

ABSOLUTE MAXIMUM RATINGS¹

(T = 25°C unless otherwise noted)

PIN CONFIGURATION

52-Lead MQFP

A

AV

DV

to AGND

to DGND

to AGND

to DGND

–0.3 V to +7 V

DD

2

AGND to DGND

–0.3 V to +0.3 V

–2 V to +5 V

AV

DD

to DV

DD

Analog Input Voltage to AGND³

Reference Input Voltage to AGND

–0.3 V to AV

+0.3 V

DD

–0.3 V to AV

+0.3 V

AIN/REFIN Current (Indefinite)

30 mA

+0.3 V

Digital Input Voltage to DGND

–0.3 V to DV

DD

Digital Output Voltage to DGND

Operating Temperature Range

Storage Temperature Range

Junction Temperature

–40°C to +125°C

–65°C to +150°C

150°C

56-Lead CSP

θ

JA

Thermal Impedance

90°C/W

Lead Temperature, Soldering

Vapor Phase (60 sec)

Infrared (15 sec)

215°C

220°C

1

Stresses above those listed under Absolute Maximum Ratings may cause

permanent damage to the device. This is a stress rating only; functional

operation of the device at these or any other conditions above those listed in

the operational sections of this specification is not implied. Exposure to

absolute maximum rating conditions for extended periods may affect device

reliability.

2

3

AGND and DGND are shorted internally on the ADuC846.

Applies to P1.2 to P1.7 pins operating in analog or digital input modes.

ORDERING GUIDE

Temperature Voltage Range

User Code

Space

Package

Option

MODEL

Package Description

Range (^oC)

(V)

-40 Æ+125

-40 Æ+85

4.75 Æ 5.25

2.75 Æ 3.60

4.75 Æ 5.25

2.75 Æ 3.60

4.75 Æ 5.25

2.75 Æ 3.60

4.75 Æ 5.25

2.75 Æ 3.60

62 kBytes

32 kBytes

8 kBytes

52-Lead Plastic Quad Flatpack

56-Lead Chip Scale Package

QuickStart Development System

QuickStart Plus Development System

S-52

ADuC846BS62-5

ADuC846BS62-3

ADuC846BCP62-5

ADuC846BCP62-3

ADuC846BCP32-5

ADuC846BCP32-3

ADuC846BCP8-5

ADuC846BCP8-3

EVAL-ADuC846QS

EVAL-ADuC846QSP

S-52

CP-56

8 kBytes

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V

readily accumulate on the human body and test equipment and can discharge without

detection. Although the ADuC846 features proprietary ESD protection circuitry,

permanent damage may occur on devices subjected to high-energy electrostatic

discharges. Therefore, proper ESD precautions are recommended to avoid performance

degradation or loss of functionality.

-8-

REV. PrA

PRELIMINARY TECHNICAL DATA

ADuC846

PIN FUNCTION DESCRIPTIONS

Pin No:

52-MQFP

Pin No:

56-CSP

Mnemonic

Type*

Description

1, 2

56, 1

P1.0/P1.1

P1.0/T2/PWM0

P1.1/T2EX/PWM1

P1.2 ÆP1.7

I/O

P1.0 and P1.1 can function as a digital inputs or digital outputs and have a pull-

up configuration as described below for Port 3. P1.0 and P1.1 have an increased

current drive sink capability of 10mA.

P1.0 and P1.1 also have various secondary functions as described below.

P1.0 can also be used to provide a clock input to Timer 2. When enabled,

counter 2 is incremented in response to a negative transition on the T2 input

pin.

I/O

I

If the PWM is enabled, the PWM0 output will appear at this pin.

P1.1 can also be used to provide a control input to Timer 2. When enabled, a

negative transition on the T2EX input pin will cause a Timer 2 capture or reload

event.

If the PWM is enabled, the PWM1 output will appear at this pin.

Port 1.2 to Port 1.7 have no digital output driver; they can function as a digital

input for which ‘0’ must be written to the port bit. As a digital input, these pins

must be driven high or low externally.

3 Æ 4

2 Æ3

9 Æ 12

11 Æ14

These pins also have the following analog functionality:

The voltage output from the DAC or one or both current sources (200uA or 2 x

200uA) can be configured to appear at this pin.

P1.2/DAC/IEXC1

P1.3/AIN5/IEXC2

I/O

Auxiliary ADC Input or one or both current sources can be configured at this

pin.

P1.4/AIN1

P1.5/AIN2

I

Primary ADC, Positive Analog Input

I

Primary ADC, Negative Analog Input

P1.6/AIN3

I

Auxiliary ADC Input or Muxed Primary ADC, Positive Analog Input

P1.7/AIN4/DAC

I/O

Auxiliary ADC Input or Muxed Primary ADC, Negative Analog Input. The

voltage

5

6

4

5

AVDD

AGND

REFIN-

REFIN+

SS

S

I

Analog Supply Voltage

Analog Ground.

N/C

7

6

A second Analog ground is provided with the CSP version only.

External Reference Input, negative terminal

External Reference Input, positive terminal

7

8

I

13

15

I

The slave select input for the SPI Interface is present at this pin. A weak pull-up

is present on this pin.

14

15

16

17

MISO

I

Master Input/Slave Output for the SPI Interface. There is a weak pull-up on this

input pin.

RESET

Reset Input. A high level on this pin for 16 core clock cycles while the

oscillator is running resets the device. There is an internal weak pull-down and

a Schmitt trigger input stage on this pin.

REV. PrA

-9-

PRELIMINARY TECHNICAL DATA

ADuC846

Pin No:

56-CSP

Mnemonic

Type*

Description

52-MQFP

16-19

22-25

18-21

24-27

P3.0 Æ P3.7

I/O

P3.0–P3.7 are bi-directional port pins with internal pull-up resistors. Port 3

pins that have 1s written to them are pulled high by the internal pull-up

resistors, and in that state can be used as inputs. As inputs, Port 3 pins being

pulled externally low will source current because of the internal pull-up

resistors. When driving a 0-to-1 output transition, a strong pull-up is active for

two core clock periods of the instruction cycle.

Port 3 pins also have various secondary functions described below.

Receiver Data for UART serial Port

16

17

18

19

20

P3.0/RXD

P3.1/TXD

P3.2/INT0

Transmitter Data for UART serial Port

External Interrupt 0. This pin can also be used as a gate control input to

Timer0.

External Interrupt 1. This pin can also be used as a gate control input to

Timer1.

19

22

21

24

P3.3/INT1

Timer/Counter 0 External Input

P3.4/T0/PWMCLK

If the PWM is enabled, an external clock may be input at this pin.

Timer/Counter 1 External Input

23

24

25

26

P3.5/T1

P3.6/WR

External Data Memory Write Strobe. Latches the data byte from Port 0 into an

external data memory.

25

27

P3.7/RD

External Data Memory Read Strobe. Enables the data from an external data

memory to Port 0.

20, 34, 48

21, 35, 47

22, 36, 51

23, 37, 50

DVDD

DGND

S

Digital Supply Voltage

Digital Ground.

26

28

SCLOCK

I/O

Serial interface clock for either the I²C or SPI interface. As an input, this pin

is a Schmitt-triggered input and a weak internal pull-up is present on this pin

unless it is outputting logic low. This pin can also be directly controlled in

software as a digital output pin.

27

29

MOSI/SDATA

I/O

Serial Data I/O for the I²C Interface or Master Output/Slave Input for the SPI

Interface. A weak internal pull-up is present on this pin unless it is outputting

logic low. This pin can also be directly controlled in software as a digital

output pin.

28 Æ 31

36 Æ 39

30 Æ 32

38 Æ 42

P2.0 Æ P2.7

I/O

Port 2 is a bidirectional port with internal pull-up resistors. Port 2 pins that

have 1s written to them are pulled high by the internal pull-up resistors, and in

that state can be used as inputs. As inputs, Port 2 pins being pulled externally

low will source current because of the internal pull-up resistors.

Port 2 emits the high order address bytes during fetches from external

program memory and middle and high order address bytes during accesses to

the 24-bit external data memory space.

32

33

34

35

XTAL1

XTAL2

I

Input to the crystal oscillator inverter.

O

Output from the crystal oscillator inverter. (see “Hardware Design

Considerations” for description)

40

43

External Access Enable, Logic Input. When held high, this input enables the

device to fetch code from internal program memory locations 0000h to

F7FFh. When held low this input enables the device to fetch all instructions

from external program memory. To determine the mode of code execution,

i.e., internal or external, the EA pin is sampled at the end of an external

RESET assertion or as part of a device power cycle.

EA may also be used as an external emulation I/O pin and therefore the

voltage level at this pin must not be changed during normal mode operation as

it may cause an emulation interrupt that will halt code execution.

EA

-10-

REV. PrA

PRELIMINARY TECHNICAL DATA

ADuC846

Pin No:

52-MQFP

41

Pin No:

56-CSP

44

Mnemonic

PSEN

Type*

Description

Program Store Enable, Logic Output. This output is a control signal that

enables the external program memory to the bus during external fetch

operations. It is active every six oscillator periods except during external data

memory accesses. This pin remains high during internal program execution.

PSEN can also be used to enable serial download mode when pulled low

through a resistor at the end of an external RESET assertion or as part of a

device power cycle.

42

45

ALE

Address Latch Enable, Logic Output. This output is used to latch the low byte

(and page byte for 24-bit data address space accesses) of the address to

external memory during external code or data memory access cycles. It is

activated every six oscillator periods except during an external data memory

access. It can be disabled by setting the PCON.4 bit in the PCON SFR.

43 Æ 46

49 Æ 52

46 Æ 49

52 Æ 55

P0.0 Æ P0.7

I/O

P0.0–P0.7, these pins are part of Port0 which is an 8-bit open-drain

bidirectional I/O port. Port 0 pins that have 1s written to them float and in that

state can be used as high impedance inputs. An external pull-up resistor will

be required on P0 outputs to force a valid logic high level externally. Port 0 is

also the multiplexed low-order address and data bus during accesses to

external program or data memory. In this application it uses strong internal

pull-ups when emitting 1s.

*I = Input, O = Output, S = Supply.

REV. PrA

-11-

PRELIMINARY TECHNICAL DATA

ADuC846

DETAILED BLOCK DIAGRAM WITH PIN NUMBERS

Figure 1: Detailed Block Diagram of the ADuC846

-12-

REV. PrA

PRELIMINARY TECHNICAL DATA

ADuC846

Reset initializes the stack pointer to location 07 hex. Any call or push

pre-increments the SP before loading the stack. Hence loading the

stack starts from locations 08 hex which is also the first register (R0)

of register bank 1. Thus, if one is going to use more than one register

bank, the stack pointer should be initialized to an area of RAM not

used for data storage.

memory address space, and the stack depth can be expanded up to

2048 bytes.

INTRODUCTION

The ADuC846 is a pin compatible upgrade to the ADuC836 and

provides increased core performance. The ADUC846 has a single

cycle 8052 core allowing operation at up to 12.58MIPs. It has all the

same features as the ADuC836 but the standard 12-cycle 8052 core

has been replaced with a 12.6MIPs single cycle core.

Since the ADuC846 and ADuC836 share the same feature set only

the differences between the two chips are documented here. For full

documentation on the ADuC836 please consult the datasheet

available at http://www.analog.com/microconverter

7FH

GENERAL-PURPOSE

AREA

MEMORY7 ORGANISATION

30H

The ADuC846 contains 4 different memory blocks namely:

- 62kBytes of On-Chip Flash/EE Program Memory

- 4kBytes of On-Chip Flash/EE Data Memory

- 256 Bytes of General Purpose RAM

2FH

BANKS

BIT-ADDRESSABLE

SELECTED

VIA

(BIT ADDRESSES)

20H

18H

10H

BITS IN PSW

- 2kBytes of Internal XRAM

1FH

17H

0FH

07H

11

10

01

00

(1) Flash/EE Program Memory

The ADuC846 provides 62kBytes of Flash/EE program memory to

run user code. The user can choose to run code from this internal

memory or run code from an external program memory.

If the user applies power or resets the device while the EA pin is

pulled low externally, the part will execute code from the external

program space, otherwise if EA is pulled high externally the part

defaults to code execution from its internal 62kBytes of Flash/EE

program memory. The ADuC846 does not support the rollover from

F7FFh in internal code space to F800h in external code space. Instead

the 2048 bytes between F800h and FFFFh will appear as NOP

instructions to user code.

FOUR BANKS OF EIGHT

REGISTERS

R0 R7

08H

00H

RESET VALUE OF

STACK POINTER

Figure 2. Lower 128 Bytes of Internal Data Memory

(4) Internal XRAM

The ADuC846 contains 2kBytes of on-chip extended data memory.

This memory although on-chip is accessed via the MOVX

instruction. The 2kBytes of internal XRAM are mapped into the

bottom 2kBytes of the external address space if the CFG846.0 bit is

set, otherwise access to the external data memory will occur just like

a standard 8051.

Permanently embedded firmware allows code to be serially

downloaded to the 62kBytes of internal code space via the UART

serial port while the device is in-circuit. No external hardware is

required.

56kBytes of the program memory can be repogrammed during

runtime hence the code space can be upgraded in the field using a

user defined protocol or it can be used as a data memory. This will be

discussed in more detail in the Flash/EE Memory section of the

datasheet.

Even with the CFG846.0 bit set access to the external XRAM will

occur once the 24 bit DPTR is greater than 0007FFH.

FFFFFFH

(2) Flash/EE Data Memory

4kBytes of Flash/EE Data Memory are available to the user and can

be accessed indirectly via a group of registers mapped into the

Special Function Register (SFR) area. Access to the Flash/EE Data

memory is discussed in detail later as part of the Flash/EE memory

section in this data sheet.

EXTERNAL

DATA

EXTERNAL

DATA

MEMORY

SPACE

MEMORY

SPACE

(24-BIT

ADDRESS

SPACE)

(24-BIT

ADDRESS

SPACE)

(3) General Purpose RAM

The general purpose RAM is divided into two seperate memories,

namely the upper and the lower 128 bytes of RAM. The lower 128

bytes of RAM can be accessed through direct or indirect addressing

while the upper 128 bytes of RAM can only be accessed through

indirect addressing as it shares the same address space as the SFR

space which can only be accessed through direct addressing.

The lower 128 bytes of internal data memory are mapped as shown in

Figure 2. The lowest 32 bytes are grouped into four banks of eight

registers addressed as R0 through R7. The next 16 bytes (128 bits),

locations 20Hex through 2FHex above the register banks, form a

block of directly addressable bit locations at bit addresses 00H

through 7FH. The stack can be located anywhere in the internal

000800H

0007FFH

2 KBYTES

ON-CHIP

XRAM

000000H

CFG845.0=1

CFG845.0=0

Figure 3: Internal and External XRAM

When accessing the internal XRAM the P0, P2 port pins as well as

the RD and WR strobes will not be output as per a standard 8051

REV. PrA

-13-

PRELIMINARY TECHNICAL DATA

ADuC846

MOVX instruction. This allows the user to use these port pins as

standard I/O.

SPECIAL FUNCTION REGISTERS (SFRs)

The upper 1792 bytes of the internal XRAM can be configured to be

used as an extended 11-bit stack pointer.

The SFR space is mapped into the upper 128 bytes of internal data

memory space and accessed by direct addressing only. It provides an

interface between the CPU and all on chip peripherals. A block

diagram showing the programming model of the ADuC846 via the

SFR area is shown in Figure 5.

By default the stack will operate exactly like an 8052 in that it will

rollover from FFh to 00h in the general purpose RAM. On the

ADuC844 however it is possible (by setting CFG844.7) to enable the

11-bit extended stack pointer. In this case the stack will rollover from

FFh in RAM to 0100h in XRAM.

All registers except the Program Counter (PC) and the four general-

purpose register banks, reside in the SFR area. The SFR registers

include control, configuration, and data registers that provide an

interface between the CPU and all on-chip peripherals.

The 11-bit stack pointer is visable in the SP and SPH SFRs. The SP

SFR is located at 81h as with a standard 8052. The SPH SFR is

located at B7h. The 3 LSBs of this SFR contain the 3 extra bits

necessary to extend the 8-bit stack pointer into an 11-bit stack

pointer.

4 KBYTE

ELECTRICALLY

REPROGRAMMABLE

NONVOLATILE

FLASH/EE DATA

MEMORY

62 KBYTE ELECTRICALLY

REPROGRAMMABLE

NONVOLATILE FLASH/EE

PROGRAM MEMORY

07FFH

128-BYTE

SPECIAL

FUNCTION

REGISTER

AREA

8051-

COMPATIBLE

CORE

DUAL

SIGMA-DELTA

ADCs

UPPER 1792

BYTES OF

ON-CHIP XRAM

(DATA +STACK

FOR EXSP=1,

DATA ONLY

OTHER ON-CHIP

PERIPHERALS

256 BYTES RAM

2K XRAM

TEMP SENSOR

CURRENT SOURCES

12-BIT DAC

FOR EXSP=0)

CFG845.7 = 1

CFG845.7 = 0

SERIAL I/O

WDT, PSM

TIC, PLL

100H

FFH

Figure 5. Programming Model

Accumulator SFR (ACC)

LOWER 256

BYTES OF

256 BYTES OF

ON-CHIP DATA

RAM

ON-CHIP XRAM

(DATA ONLY)

(DATA + STACK)

00H

ACC is the Accumulator register and is used for math operations

including addition, subtraction, integer multiplication and division,

and Boolean bit manipulations. The mnemonics for accumulator-

specific instructions refer to the Accumulator as A.

Figure 4. Extended Stack Pointer Operation

External Data Memory (External XRAM)

Just like a standard 8051 compatible core the ADuC846 can access

external data memory using a MOVX instruction. The MOVX

instruction automatically outputs the various control strobes required

to access the data memory.

B SFR (B)

The B register is used with the ACC for multiplication and division

operations. For other instructions it can be treated as a general-

purpose scratchpad register.

The ADuC846 however, can access up to 16MBytes of extrenal data

memory. This is an enhancement of the 64kBytes external data

memory space available on a standard 8051 compatible core.

The external data memory is discussed in more detail in the

ADuC846 Hardware Design Considerations section.

Data Pointer (DPTR)

The Data Pointer is made up of three 8-bit registers, named DPP

(page byte), DPH (high byte) and DPL (low byte). These are used to

provide memory addresses for internal and external code access and

external data access. It may be manipulated as a 16-bit register

(DPTR = DPH, DPL), although INC DPTR instructions will

automatically carry over to DPP, or as three independent 8-bit

registers (DPP, DPH, DPL).

The ADuC846 supports dual data pointers. Refer to the Dual Data

Pointer section later in this datasheet.

Stack Pointer (SP and SPH)

The SP SFR is the stack pointer and is used to hold an internal RAM

address that is called the ‘top of the stack.’ The SP register is

incremented before data is stored during PUSH and CALL

executions. While the Stack may reside anywhere in on-chip RAM,

the SP register is initialized to 07H after a reset. This causes the stack

to begin at location 08H.

As mentioned earlier the ADuC846 offers an extended 11-bit stack

pointer. The 3 extra bits to make up the 11-bit stack pointer are the 3

LSBs of the SPH byte located at B7h. To enable the SPH SFR the

-14-

REV. PrA

PRELIMINARY TECHNICAL DATA

ADuC846

EXSP (CFG846.7) bit must be set otherwise the SPH SFR cannot be

read or written to.

The CFG846 SFR contains the necessary bits to configure the

internal XRAM and the extended SP. By default it configures the

user into 8051 mode. i.e. extended SP is disabled, internal XRAM is

disabled.

Program Status Word (PSW)

The PSW SFR contains several bits reflecting the current status of the

CPU as detailed in Table I.

SFR Address

AFhH

00H

No

SFR Address

D0H

00H

Yes

Power ON Default Value

Bit Addressable

Power ON Default Value

Bit Addressable

Table III. CFG846 SFR Bit Designations

Table I. PSW SFR Bit Designations

Description

Bit Name

Description

7

EXSP

Extended SP Enable

Bit Name

7

6

5

4

3

CY

AC

F0

Carry Flag

If this bit is set then the stack will

Auxiliary Carry Flag

General-Purpose Flag

Register Bank Select Bits

RS1 RS0 Selected Bank

rollover from SPH/SP = 00FFh to

0100h.

RS1

RS0

If this bit is clear then the SPH SFR will be

disabled and the stack will rollover from SP=FFh to

0

1

0

1

0

1

0

1

2

3

SP = 00h

----

6

5

4

3

2

1

0

----

2

1

0

OV

F1

P

Overflow Flag

----

General-Purpose Flag

Parity Bit

----

XRAMEN XRAM Enable Bit

The PCON SFR contains bits for power-saving options and general-

purpose status flags as shown in Table II.

If this bit is set then the internal

XRAM will be mapped into the lower

2kBytes of the external address space.

If this bit is clear then the internal

XRAM will not be accessible and the

external data memory will be mapped

into the lower 2kBytes of external data

memory. (see figure 3)

SFR Address

87H

00H

No

Power ON Default Value

Bit Addressable

Table II. PCON SFR Bit Designations

Description

Bit Name

7

6

5

4

3

2

1

0

SMOD

Double UART Baud Rate

SERIPD SPI Power-Down Interrupt Enable

INT0PD INT0 Power-Down Interrupt Enable

ALEOFF Disable ALE Output

GF1

GF0

PD

General-Purpose Flag Bit

Power-Down Mode Enable

Idle Mode Enable

IDL

REV. PrA

-15-

PRELIMINARY TECHNICAL DATA

ADuC846

COMPLETE SFR MAP

Figure 6 below shows a full SFR memory map and the SFR contents after RESET. NOT USED indicates unoccupied SFR locations. Unoccupied locations

in the SFR address space are not implemented; i.e., no register exists at this location. If an unoccupied location is read, an unspecified value is

returned. SFR locations that are reserved for future use are shaded (RESERVED) and should not be accessed by user software.

Figure 6: Complete SFR Map

-16-

REV. PrA

PRELIMINARY TECHNICAL DATA

ADuC846

8052 Instruction Set

ALE

The following pages document the number of clock cycles required

for each instruction. Most instructions are executed in one or two

clock cycles resulting in 12.6MIPs peak performance when

operating at PLLCON = 00H.

The output on the ALE pin on the ADuC836 was a clock at 1/6th of

the core operating frequency. On the ADuC846 the ALE pin

operates as follows.

For a single machine cycle instruction: ALE is high for the first

half of the machine cycle and low for the second half. The ALE

output is at the core operating frequency.For a two or more

machine cycle instruction: ALE is high for the first half of the first

machine cycle and then low for the rest of the machine cycles.

Timer Operation

Timers on a standard 8052 increment by one with each machine

cycle. On the ADuC846 one machine cycle is equal to one clock

cycle hence the timers will increment at the same rate as the core

clock.

External Memory Access

There is no support for external program memory access on the

ADuC846. When accessing external RAM the EWAIT register

may need to be programmed in order to give extra machine cycles

to MOVX commands. This is to account for differing external

RAM access speeds.

INSTRUCTION TABLE

TABLE IV: Optimized Single Cycle 8051 Instruction Set

Description

Mnemonic Arithmetic

ARITHMETIC

Bytes

Cycles

ADD A,Rn

ADD A,@Ri

ADDC A,Rn

ADDC A,@Ri

ADD A,dir

ADD A,#data

SUBB A,Rn

SUBB A,@Ri

SUBB A,dir

SUBB A,#data

INC A

Add register to A

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

3

1

2

9

2

Add indirect memory to A

Add register to A with carry

Add indirect memory to A with carry

Add direct byte to A

Add direct byte to A with carry

Subtract register from A with borrow

Subtract indirect memory from A with borrow

Subtract direct from A with borrow

Subtract immediate from A with borrow

Increment A

INC Rn

Increment register

INC @Ri

Increment indirect memory

Increment direct byte

INC dir

INC DPTR

DEC A

Increment data pointer

Decrement A

DEC Rn

Decrement Register

DEC @Ri

DEC dir

Decrement indirect memory

Decrement direct byte

MUL AB

Multiply A by B

DIV AB

Divide A by B

DA A

Decimal Adjust A

REV. PrA

-17-

PRELIMINARY TECHNICAL DATA

ADuC846

Mnemonic Arithmetic

Description

Bytes

Cycles

LOGIC

ANL A,Rn

ANL A,@Ri

ANL A,dir

ANL A,#data

ANL dir,A

ANL dir,#data

ORL A,Rn

ORL A,@Ri

ORL A,dir

ORL A,#data

ORL dir,A

ORL dir,#data

XRL A,Rn

XRL A,@Ri

XRL A,#data

XRL dir,A

XRL A,dir

XRL dir,#data

CLR A

AND register to A

1

2

3

1

2

3

1

2

3

1

2

3

1

2

3

1

2

3

1

AND indirect memory to A

AND direct byte to A

AND immediate to A

AND A to direct byte

AND immediate data to direct byte

OR register to A

OR indirect memory to A

OR direct byte to A

OR immediate to A

OR A to direct byte

OR immediate data to direct byte

Exclusive-OR register to A

Exclusive-OR indirect memory to A

Exclusive-OR immediate to A

Exclusive-OR A to direct byte

Exclusive-OR indirect memory to A

Exclusive-OR immediate data to direct

Clear A

CPL A

Complement A

SWAP A

Swap Nibbles of A

RL A

Rotate A left

RLC A

Rotate A left through carry

Rotate A right

RR A

RRC A

Rotate A right through carry

BOOLEAN

CLR C

Clear carry

1

2

1

2

1

2

1

2

1

2

1

2

CLR bit

Clear direct bit

SETB C

Set Carry

SETB bit

Set direct bit

CPL C

Complement carry

Complement direct bit

AND direct bit and carry

AND direct bit inverse to carry

OR direct bit and carry

OR direct bit inverse to carry

Move direct bit to carry

Move carry to direct bit

CPL bit

ANL C,bit

ANL C,/bit

ORL C,bit

ORL C,/bit

MOV C,bit

MOV bit,C

-18-

REV. PrA

PRELIMINARY TECHNICAL DATA

ADuC846

Mnemonic Arithmetic

Description

Bytes

Cycles

BRANCHING

JMP @A+DPTR

RET

Jump indirect relative to DPTR

1

2

3

4

3

4

Return from subroutine

RETI

Return from interrupt

ACALL addr11

AJMP addr11

SJMP rel

Absolute jump to subroutine

Absolute jump unconditional

Short jump (relative address)

Jump on carry = 1

JC rel

JNC rel

Jump on carry = 0

Jump on accumulator = 0

JZ rel

JNZ rel

Jump on accumulator != 0

Decrement register, jnz relative

Long jump unconditional

DJNZ Rn,rel

LJMP

LCALL addr16

JB bit,rel

Long jump to subroutine

Jump on direct bit = 1

JNB bit,rel

JBC bit,rel

Jump on direct bit = 0

Jump on direct bit = 1 and clear

Compare A, direct JNE relative

Compare A, immediate JNE relative

Compare register, immediate JNE relative

Compare indirect, immediate JNE relative

Decrement direct byte, JNZ relative

CJNE A,dir,rel

CJNE A,#data,rel

CJNE Rn,#data,rel

CJNE @Ri,#data,rel

DJNZ dir,rel

MISCELLANEOUS

NOP

No operation

1

Notes:

1. One cycle is one clock.

2. Cycles of MOVX instructions are 4 cycles when they have 0 wait state. Cycles of MOVX instructions are 4+N cycles when they have N wait

states.

3. Cycles of LCALL instruction are 3 cycles when the LCALL instruction comes from interrupt.

REV. PrA

-19-

PRELIMINARY TECHNICAL DATA

ADuC846

-20-

REV. PrA


型号：	ADUC846
厂家：	ADI
描述：	MicroConverter, Dual 16-Bit ADCs with Embedded 62kB FLASH MCU 微转换器，双通道16位ADC，内置62KB闪存MCU 转换器闪存
文件：	总20页 (文件大小：1837K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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