ADUC848BS8-5_技术文档

MicroConverter^®Multichannel

24-/16-Bit ADCs with Embedded 62 kB

Flash and Single-Cycle MCU

ADuC845/ADuC847/ADuC848

Power

FEATURES

High resolution Σ-∆ ADCs

Normal: 4.8 mA max @ 3.6 V (core CLK = 1.57 MHz)

Power-down: 20 µA max with wake-up timer running

Specified for 3 V and 5 V operation

Two independent 24-bit ADCs on the ADuC845

Single 24-bit ADC on the ADuC847 and

single 16-bit ADC on the ADuC848

Package and temperature range:

Up to 10 ADC input channels on all parts

24-bit no missing codes

52-lead MQFP (14 mm × 14 mm), −40°C to +125°C

56-lead CSP (8 mm × 8 mm), −40°C to +85°C

22-bit rms (19.5 bit p-p) effective resolution

Offset drift 10 nV/°C, gain drift 0.5 ppm/°C chop enabled

APPLICATIONS

Multichannel sensor monitoring

Memory

Industrial/environmental instrumentation

Weigh scales, pressure sensors, temperature monitoring

Portable instrumentation, battery-powered systems

Data logging, precision system monitoring

62-kbyte on-chip Flash/EE program memory

4-kbyte on-chip Flash/EE data memory

Flash/EE, 100 year retention, 100 kcycle endurance

3 levels of Flash/EE program memory security

In-circuit serial download (no external hardware)

High speed user download (5 seconds)

2304 bytes on-chip data RAM

FUNCTIONAL BLOCK DIAGRAM

AV_DD

ADuC845

AVCO

IEXC1

IEXC2

CURRENT

SOURCE

8051-based core

AIN0

8051-compatible instruction set

High performance single-cycle core

32 kHz external crystal

PRIMARY

24-BIT Σ-∆ ADC

BUF

PGA

12-BIT

DAC

BUF

MUX

AGND

On-chip programmable PLL (12.58 MHz max)

3 × 16-bit timer/counter

AIN9

DUAL 16-BIT

Σ-∆ DAC

PWM0

PWM1

AUXILIARY

24-BIT Σ-∆ ADC

AINCOM

MUX

TEMP

SENSOR

DUAL 16-BIT

PWM

24 programmable I/O lines, plus 8 analog or

digital input lines

REFIN2+

REFIN2–

11 interrupt sources, two priority levels

Dual data pointer, extended 11-bit stack pointer

REFIN–

REFIN+

EXTERNAL

V_REF

DETECT

INTERNAL

BAND GAP

V_REF

SINGLE-CYCLE 8061 BASED MCU

RESET

DV_DD

62 kBYTES FLASH/EE PROGRAM MEMORY

4 kBYTES FLASH/EE DATA MEMORY

2304 BYTES USER RAM

POR

On-chip peripherals

Internal power-on reset circuit

12-bit voltage output DAC

DGND

PLL AND PRG

CLOCK DIV

3 × 16 BIT TIMERS

BAUD RATE TIMER

POWER SUPPLY MON

WATCHDOG TIMER

WAKE-UP/

RTC TIMER

UART, SPI, AND I ²

SERIAL I/O

C

4 × PARALLEL

PORTS

OSC

Dual 16-bit Σ-∆ DACs

On-chip temperature sensor (ADuC845 only)

Dual excitation current sources (200 µA)

Time interval counter (wake-up/RTC timer)

UART, SPI®, and I²C® serial I/O

XTAL1 XTAL2

Figure 1. ADuC845 Functional Block Diagram

High speed dedicated baud rate generator (incl 115,200)

Watchdog timer (WDT)

Power supply monitor (PSM)

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable.

However, no responsibility is assumed by Analog Devices for its use, nor for any

infringements of patents or other rights of third parties that may result from its use.

Specifications subject to change without notice. No license is granted by implication

or otherwise under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.326.8703

www.analog.com

ADuC845/ADuC847/ADuC848

TABLE OF CONTENTS

Specifications..................................................................................... 4

ADC SFR Interface..................................................................... 39

ADCSTAT (ADC Status Register) ........................................... 40

ADCMODE (ADC Mode Register)......................................... 41

ADC0CON1 (Primary ADC Control Register)..................... 43

ADC0CON2 (Primary ADC Channel Select Register) ........ 44

SF (ADC Sinc Filter Control Register).................................... 46

ICON (Excitation Current Sources Control Register).......... 47

Nonvolatile Flash/EE Memory Overview............................... 48

Flash/EE Program Memory...................................................... 49

User Download Mode (ULOAD)............................................. 50

Using Flash/EE Data Memory.................................................. 51

Flash/EE Memory Timing ........................................................ 52

DAC Circuit Information.......................................................... 53

Pulse-Width Modulator (PWM).............................................. 55

On-Chip PLL (PLLCON).......................................................... 60

I²C Serial Interface ..................................................................... 61

SPI Serial Interface..................................................................... 64

Using the SPI Interface .............................................................. 66

Dual Data Pointers..................................................................... 67

Power Supply Monitor............................................................... 68

Watchdog Timer......................................................................... 69

Time Interval Counter (TIC).................................................... 70

8052 Compatible On-Chip Peripherals................................... 73

Timers/Counters ........................................................................ 75

UART Serial Interface................................................................ 80

Interrupt System......................................................................... 85

Interrupt Priority........................................................................ 86

Interrupt Vectors ........................................................................ 86

Hardware Design Considerations ................................................ 87

External Memory Interface....................................................... 87

Power Supplies............................................................................ 87

Abosolute Maximum Ratings ....................................................... 10

ESD Caution................................................................................ 10

Pin Configuration and Function Descriptions........................... 11

General Description....................................................................... 15

8052 Instruction Set ................................................................... 18

Timer Operation......................................................................... 18

ALE............................................................................................... 18

External Memory Access........................................................... 18

Complete SFR Map .................................................................... 19

Functional Description.................................................................. 20

8051 Instruction Set ................................................................... 20

Memory Organization ............................................................... 22

Special Function Registers (SFRs)............................................ 24

ADC Circuit Information.......................................................... 26

Auxiliary ADC (ADuC845 Only) ............................................ 32

Reference Inputs ......................................................................... 32

Burnout Current Sources .......................................................... 32

Reference Detect Circuit ........................................................... 33

Sinc Filter Register (SF) ............................................................. 33

Σ-∆ Modulator............................................................................ 33

Digital Filter ................................................................................ 33

ADC Chopping........................................................................... 34

Calibration................................................................................... 34

Programmable Gain Amplifier................................................. 35

Bipolar/Unipolar Configuration .............................................. 35

Data Output Coding .................................................................. 36

Excitation Currents .................................................................... 36

ADC Power-On .......................................................................... 36

Typical Performance Characteristics ........................................... 37

Functional Description.................................................................. 39

Rev. A | Page 2 of 108

ADuC845/ADuC847/ADuC848

Power-On Reset Operation........................................................88

Power Consumption...................................................................88

Power-Saving Modes ..................................................................88

Grounding and Board Layout Recommendations .................89

Other Hardware Considerations...............................................90

QuickStart Development System ..................................................94

QuickStart-PLUS Development System ..................................94

Timing Specifications .....................................................................95

Outline Dimensions......................................................................104

Ordering Guide .........................................................................105

REVISION HISTORY

6/04—Changed from Rev. 0 to Rev. A

Changes to Figure 5.........................................................................17

Changes to Figure 6.........................................................................18

Changes to Figure 7.........................................................................19

Changes to Table 5 ..........................................................................24

Changes to Table 24 ........................................................................41

Changes to Table 25 ........................................................................43

Changes to Table 26 ........................................................................44

Changes to Table 27 ........................................................................45

Changes to User Download Mode Section..................................50

Added Figure 51 and Renumbered Subsequent Figures............50

Edits to the DACH/DACL Data Registers Section .....................53

Changes to Table 34 ........................................................................56

Added SPIDAT: SPI Data Register Section..................................65

Changes to Table 42 ........................................................................67

Changes to Table 43 ........................................................................68

Changes to Table 44 ........................................................................69

Changes to Table 45 ........................................................................71

Changes to Table 50 ........................................................................75

Changes to Timer/Counter 0 and 1 Data Registers Section......76

Changes to Table 54 ........................................................................80

Added the SBUF—UART Serial Port Data Register Section.....80

Addition to the Timer 3 Generated Baud Rates Section............83

Added Table 57 and Renumbered Subsequent Tables................84

Changes to Table 61 ........................................................................86

4/04—Revision 0: Initial Version

Rev. A | Page 3 of 108

ADuC845/ADuC847/ADuC848

SPECIFICATIONS¹

AV_DD= 2.7 V to 3.6 V or 4.75 V to 5.25 V, DV_DD= 2.7 V to 3.6 V or 4.75 V to 5.25 V, REFIN(+) = 2.5 V, REFIN(–) = AGND; AGND =

DGND = 0 V; XTAL1/XTAL2 = 32.768 kHz crystal; all specifications T_MINto T_MAX, unless otherwise noted. Input buffer on for primary

ADC, unless otherwise noted. Core speed = 1.57 MHz (default CD = 3), unless otherwise noted.

Table 1.

Parameter

Min

Typ

Max

Unit

Conditions

PRIMARY ADC

Conversion Rate

5.4

105

Hz

Chop on (ADCMODE.3 = 0)

16.06

24

1365

Hz

Bits

Chop off (ADCMODE.3 = 1)

≤26.7 Hz update rate with chop enabled

≤80.3 Hz update rate with chop disabled

No Missing Codes²

Resolution (ADuC845/ADuC847)

Resolution (ADuC848)

See Table 11 and Table 15

See Table 13 and Table 17

Output Noise (ADuC845/ADuC847) See Table 10 and Table 14

µV (rms)

Output noise varies with selected update rates,

gain range, and chop status.

Output noise varies with selected update rates,

gain range and chop status.

Output Noise (ADuC848)

See Table 12 and Table 16

3

Integral Nonlinearity

Offset Error³

15

ppm of FSR 1 LSB₁₆

µV

Chop on

Chop off, offset error is in the order of the noise

for the programmed gain and update rate

following a calibration.

Chop on (ADCMODE.3 = 0)

Chop off (ADCMODE.3 = 1)

Offset Error Drift vs. Temperature²

10

200

nV/°C

Full-Scale Error⁴

ADuC845/ADuC847

ADuC848

10

0.5

µV

LSB₁₆

ppm/°C

20 mV to 2.56 V

20 mV to 640 mV

1.28 V to 2.56 V

Gain Error Drift vs. Temperature⁴

Power Supply Rejection

80

dB

AIN = 1 V, 2.56 V, chop enabled

AIN = 7.8 mV, 20 mV, chop enabled

AIN = 1 V, 2.56 V, chop disabled²

113

80

PRIMARY ADC ANALOG INPUTS

Differential Input Voltage Ranges^{5, 6}

Bipolar Mode (ADC0CON1.5 = 0)

Gain = 1 to 128

V_REF= REFIN(+) − REFIN(−) or

1.024 ꢀ

V

V_REF/GAIN

0 – 1.024 ꢀ

V_REF/GAIN

REFIN2(+) − REFIN2(−) (or Int 1.25 V_REF

V_REF= REFIN(+) − REFIN(−) or

REFIN2(+) − REFIN2(−) (or Int 1.25 V_REF

)

Unipolar Mode (ADC0CON1.5 = 1)

V

ADC Range Matching

Common-Mode Rejection DC

On AIN

2

µV

AIN = 18 mV, chop enabled

Chop enabled, chop disabled

AIN = 7.8 mV, range = 20 mV

AIN = 1 V, range = 2.56 V

95

dB

113

Common-Mode Rejection

50 Hz/60 Hz²

50 Hz/60 Hz 1 Hz, 16.6 Hz and 50 Hz update

rate, chop enabled, REJ60 enabled

On AIN

95

90

dB

AIN = 7.8 mV, range = 20 mV

AIN = 1 V, range = 2.56 V

Footnotes at end of table.

Rev. A | Page 4 of 108

ADuC845/ADuC847/ADuC848

Parameter

Normal Mode Rejection 50 Hz/60 Hz²

Min

Typ

Max

Unit

Conditions

On AIN

75

dB

50 Hz/60 Hz 1 Hz, 16.6 Hz Fadc, SF = 52H,

chop on, REJ60 on

100

67

dB

50 Hz 1 Hz, 16.6 Hz Fadc, SF = 52H, chop on

50 Hz/60 Hz 1 Hz, 50 Hz Fadc, SF = 52H,

chop off, REJ60 on

100

dB

nA

50 Hz 1 Hz, 50 Hz Fadc, SF = 52H, chop off

T_MAX= 85°C, buffer on

T_MAX= 125°C, buffer on

Analog Input Current²

1

5

Analog Input Current Drift

5

15

125

2

pA/°C

nA/V

pA/V/°C

V

T_MAX= 85°C, buffer on

T_MAX= 125°C, buffer on

2.56 V range, buffer bypassed

Buffer bypassed

AIN1…AIN10 and AINCOM with buffer enabled

Average Input Current

Average Input Current Drift

Absolute AIN Voltage Limits²

A_GND

0.1

A_GND

0.03

+

−

AV_DD

0.1

AV_DD

0.03

−

+

Absolute AIN Voltage Limits²

V

AIN1…AIN10 and AINCOM with buffer bypassed

EXTERNAL REFERENCE INPUTS

REFIN(+) to REFIN(–) Voltage

REFIN(+) to REFIN(–) Range²

Average Reference Input Current

Drift

2.5

1

V

µA/V

REFIN refers to both REFIN and REFIN2

Both ADCs enabled

1

AV_DD

0.65

0.1

nA/V/°C

V

NOXREF Trigger Voltage

0.3

NOXREF (ADCSTAT.4) bit active if V_REF> 0.3 V, and

inactive if V_REF> 0.65 V

Common-Mode Rejection

DC Rejection

125

dB

AIN = 1 V, range = 2.56 V

50 Hz/60 Hz 1 Hz, AIN = 1 V,

range = 2.56 V, SF = 82

50 Hz/60 Hz 1 Hz, AIN = 1 V, range = 2.56 V,

SF = 52H, chop on, REJ60 on

50 Hz 1 Hz, AIN = 1 V, range = 2.56 V,

SF = 52H, chop on

50 Hz/60 Hz 1 Hz, AIN = 1 V, range = 2.56 V,

SF = 52H, chop off, REJ60 on

50 Hz 1 Hz, AIN = 1 V, range = 2.56 V,

SF = 52H, chop off

50 Hz/60 Hz Rejection²

90

Normal Mode Rejection 50 Hz/60 Hz²

75

dB

100

67

100

AUXILIARY ADC (ADuC845 Only)

Conversion Rate

5.4

105

Hz

Chop on

16.06

24

1365

Hz

Bits

Chop off

No Missing Codes²

≤26.7 Hz update rate, chop enabled

80.3 Hz update rate, chop disabled

Resolution

See Table 19 and Table 21

See Table 18 and Table 20

Output Noise

Integral Nonlinearity

Offset Error³

Output noise varies with selected update rates.

15

ppm of FSR 1 LSB₁₆

3

µV

Chop on

Chop off

Chop on

Chop off

0.25

10

LSB₁₆

nV/°C

LSB₁₆

ppm/°C

dB

Offset Error Drift²

200

0.5

Full-Scale Error⁴

Gain Error Drift⁴

Power Supply Rejection

80

AIN = 1 V, range = 2.56 V, chop enabled

AIN = 1 V, range = 2.56 V, chop disabled

80

dB

Footnotes at end of table.

Rev. A | Page 5 of 108

ADuC845/ADuC847/ADuC848

Parameter

Min

Typ

Max

Unit

Conditions

AUXILIARY ADC ANALOG INPUTS

(ADuC845 Only)

Differential Input Voltage Ranges^{5, 6}

Bipolar Mode (ADC1CON.5 = 0)

Unipolar Mode (ADC1CON.5 = 1)

Average Analog Input Current

Analog Input Current Drift

V_REF

V

REFIN = REFIN(+) − REFIN(−) (or Int 1.25 V_REF

)

0 – V_REF

125

2

nA/V

pA/V/°C

V

Absolute AIN/AINCOM Voltage

A_GND

0.03

−

AV_DD

0.03

+

Limits^{2, 7}

Normal Mode Rejection 50 Hz/60 Hz²

On AIN and REFIN

75

dB

50 Hz/60 Hz 1 Hz, 16.6 Hz Fadc, SF = 52H,

chop on, REJ60 on

100

67

dB

50 Hz 1 Hz, 16.6 Hz Fadc, SF = 52H, chop on

50 Hz/60 Hz 1 Hz, 50 Hz Fadc, SF = 52H,

chop off, REJ60 on

100

dB

50 Hz 1 Hz, 50 Hz Fadc, SF = 52H, chop off

ADC SYSTEM CALIBRATION

Full-Scale Calibration Limit

Zero-Scale Calibration Limit

Input Span

+1.05 ꢀ FS

2.1 ꢀ FS

V

−1.05 ꢀ FS

0.8 ꢀ FS

DAC

Voltage Range

0 – V_REF

0 – AV_DD

10

100

0.5

V

kΩ

pF

Ω

DACCON.2 = 0

DACCON.2 = 1

From DAC output to AGND

Resistive Load

Capactive Load

Output Impedance

I_SINK

50

µA

DC Specifications⁸

Resolution

12

Bits

LSB

mV

%

Relative Accuracy

Differential Non Linearity

Offset Error

3

−1

50

1

Guaranteed 12-bit monotonic

Gain Error

AV_DDrange

V_REFrange

1

%

AC Specifications^{2, 8}

Voltage Output Settling Time

Digital-to-Analog Glitch Energy

INTERNAL REFERENCE

ADC Reference

15

10

µs

nVs

Settling time to 1 LSB of final value

1 LSB change at major carry

Chop enabled

1.25 − 1%

2.5 – 1%

Reference Voltage

Power Supply Rejection

Reference Tempco

DAC Reference

Reference Voltage

1.25

45

100

1.25 + 1%

2.5 + 1%

V

dB

ppm/°C

Initial tolerance @ 25°C, V_DD= 5 V

2.5

50

100

1% V

dB

ppm/°C

Initial tolerance @ 25°C, V_DD= 5 V

Power Supply Rejection

Reference Tempco

TEMPERATURE SENSOR

(ADuC845 Only)

Accuracy

Thermal Impedance

2

90

52

°C

°C/W

MQFP package

CSP package

Footnotes at end of table.

Rev. A | Page 6 of 108

ADuC845/ADuC847/ADuC848

Parameter

Min

Typ

Max

Unit

Conditions

TRANSDUCER BURNOUT CURRENT

SOURCES

AIN+ Current

−100

100

nA

AIN+ is the selected positive input (AIN4 or AIN6

only) to the primary ADC

AIN− is the selected negative input (AIN5 or AIN7

only) to the primary ADC

AIN− Current

Initial Tolerance at 25°C

Drift

10

0.03

%

%/°C

EXCITATION CURRENT SOURCES

Output Current

Initial Tolerance at 25°C

Drift

Initial Current Matching at 25°C

Drift Matching

200

10

200

1

20

1

µA

%

Available from each current source

ppm/°C

%

ppm/°C

µA/V

V

Matching between both current sources

AV_DD= 5 V 5%

Line Regulation (AV_DD

)

Load Regulation

Output Compliance²

0.1

AV_DD− 0.6

AGND

2.63

POWER SUPPLY MONITOR (PSM)

AV_DDTrip Point Selection Range

AV_DDTrip Point Accuracy

4.63

3.0

4.0

4.63

3.0

4.0

V

Four trip points selectable in this range

T_MAX= 85°C

T_MAX= 125°C

Four trip points selectable in this range

T_MAX= 85°C

T_MAX= 125°C

%

V

%

DV_DDTrip Point Selection Range

DV_DDTrip Point Accuracy

2.63

CRYSTAL OSCILLATOR

(XTAL1 AND XTAL2)

Logic Inputs, XTAL1 Only²

V_INL, Input Low Voltage

0.8

0.4

V

DV_DD= 5 V

DV_DD= 3 V

DV_DD= 5 V

DV_DD= 3 V

V_INH, Input Low Voltage

3.5

2.5

XTAL1 Input Capacitance

XTAL2 Output Capacitance

LOGIC INPUTS

18

pF

All inputs except SCLOCK, RESET,

and XTAL1²

V_INL, Input Low Voltage

0.8

0.4

V

DV_DD= 5 V

DV_DD= 3 V

V_INH, Input Low Voltage

2.0

SCLOCK and RESET Only

(Schmidt Triggered Inputs)²

V_T+

1.3

0.95

0.8

0.4

0.3

3.0

2.5

1.4

1.1

0.85

V

DV_DD= 5 V

DV_DD= 3 V

DV_DD= 5 V

DV_DD= 3 V

V_T−

V_T+− V_T−

DV_DD= 5 V or 3 V

Input Currents

Port 0, P1.0 to P1.7, EA

RESET

10

105

10

−660

−75

µA

pF

V_IN= 0 V or V_DD

V_IN= 0 V, DV_DD= 5 V

35

V_IN= DV_DD, DV_DD= 5 V, internal pull-down

V_IN= DV_DD, DV_DD= 5 V

V_IN= 2 V, DV_DD= 5 V

V_IN= 0.45 V, DV_DD= 5 V

All digital inputs

Port 2, Port 3

−180

−20

Input Capacitance

10

Rev. A | Page 7 of 108

ADuC845/ADuC847/ADuC848

Parameter

Min

Typ

Max

Unit

Conditions

LOGIC OUTPUTS

(All Digital Outputs except XTAL2)

V_OH, Output High Voltage²

2.4

V

µA

pF

DV_DD= 5 V, I_SOURCE= 80 µA

DV_DD= 3 V, I_SOURCE= 20 µA

I_SINK= 8 mA, SCLOCK, SDATA

I_SINK= 1.6 mA on P0, P1, P2

V_OL, Output Low Voltage

0.4

10

Floating State Leakage Current²

Floating State Output Capacitance

START-UP TIME

10

At Power-On

600

3

2

ms

After Ext RESET in Normal Mode

After WDT RESET in Normal Mode

From Power-Down Mode

Oscillator Running

Controlled via WDCON SFR

PLLCON.7 = 0

Wake-Up with INT0 Interrupt

Wake-Up with SPI Interrupt

Wake-Up with TIC Interrupt

Oscillator Powered Down

Wake-Up with INT0 Interrupt

20

µs

PLLCON.7 = 1

30

µs

Wake-Up with SPI Interrupt

FLASH/EE MEMORY RELIABILITY

CHARACTERISTICS

Endurance⁹

Data Retention¹⁰

100,000

100

Cycles

Years

POWER REQUIREMENTS

Power Supply Voltages

AV_DD3 V Nominal

AV_DD5 V Nominal

DV_DD3 V Nominal

DV_DD5 V Nominal

5 V Power Consumption

Normal Mode^{11, 12}

DV_DDCurrent

2.7

4.75

2.7

3.6

5.25

3.6

V

4.75

5.25

4.75 V < DV_DD< 5.25 V, AV_DD= 5.25 V

10

31

180

mA

µA

Core clock = 1.57 MHz

Core clock = 12.58 MHz

25

AV_DDCurrent

Power-Down Mode^{11, 12}

DV_DDCurrent

40

50

20

30

53

33

µA

T_MAX= 85°C; OSC on; TIC on

T_MAX= 125°C; OSC on; TIC on

T_MAX= 85°C; OSC off

T_MAX= 125°C; OSC off

AV_DDCurrent

1

3

T_MAX= 85°C; OSC on or off

T_MAX= 125°C; OSC on or off

5 V V_DD, CD = 3

Typical Additional Peripheral

Currents (AI_DDand DI_DD

)

Primary ADC

1

mA

µA

Auxiliary ADC (ADuC845 Only)

Power Supply Monitor

DAC

0.5

30

60

200

DACH/L = 000H

200 µA each. Can be combined to give 400 µA on

a single output.

Dual Excitation Current Sources

ALE Off

WDT

−20

10

µA

PCON.4 = 1 (see Table 6)

Footnotes at end of table.

Rev. A | Page 8 of 108

ADuC845/ADuC847/ADuC848

Parameter

Min

Typ

Max

Unit

Conditions

PWM

−Fxtal

−Fvco

TIC

3

0.5

1

µA

mA

µA

3 V Power Consumption

Normal Mode^{11, 12}

DV_DDCurrent

2.7 V < DV_DD< 3.6 V, AV_DD= 3.6 V

4.8

11

180

mA

µA

Core clock = 1.57 MHz

Core clock = 6.29 MHz (CD = 1)

ADC not enabled

9

AV_DDCurrent

Power-Down Mode^{11, 12}

DV_DDCurrent

20

29

14

21

26

20

µA

T_MAX= 85°C; OSC on; TIC on

T_MAX= 125°C; OSC on; TIC on

T_max= 85°C; OSC off

T_MAX= 125°C; OSC off

T_MAX= 85°C; OSC on or off

T_MAX= 125°C; OSC on or off

AV_DDCurrent

1

3

¹Temperature range is for ADuC845BS; for the ADuC847BS and ADuC848BS (MQFP package), the range is –40°C to +125°C.

Temperature range for ADuC845BCP, ADuC847BCP, and ADuC848BCP (CSP package) is –40°C to +85°C.

²These numbers are not production tested but are guaranteed by design and/or characterization data on production release.

³System zero-scale calibration can remove this error.

⁴Gain error drift is a span drift. To calculate full-scale error drift, add the offset error drift to the gain error drift times the full-scale input.

⁵In general terms, the bipolar input voltage range to the primary ADC is given by the ADC range = (V_REF2^RN)/1.25, where:

V_REF= REFIN(+) to REFIN(–) voltage and V_REF= 1.25 V when internal ADC V_REFis selected. RN = decimal equivalent of RN2, RN1, RN0. For example, if V_REF= 2.5 V and RN2,

RN1, RN0 = 1, 1, 0, respectively, then the ADC range = 1.28 V. In unipolar mode, the effective range is 0 V to 1.28 V in this example.

⁶1.25 V is used as the reference voltage to the ADC when internal V_REFis selected via XREF0/XREF1 or AXREF bits in ADC0CON2 and ADC1CON, respectively.

(AXREF is available only on the ADuC845.)

⁷In bipolar mode, the auxiliary ADC can be driven only to a minimum of AGND – 30 mV as indicated by the auxiliary ADC absolute AIN voltage limits. The bipolar range is

still –V_REFto +V_REF

.

⁸DAC linearity and ac specifications are calculated using a reduced code range of 48 to 4095, 0 V to V_REF, reduced code range of 100 to 3950, 0 V to VDD.

⁹Endurance is qualified to 100 kcycle per JEDEC Std. 22 method A117 and measured at –40°C, +25°C, +85°C, and +125°C. Typical endurance at 25°C is 700 kcycles.

¹⁰Retention lifetime equivalent at junction temperature (T_J) = 55°C per JEDEC Std. 22, Method A117. Retention lifetime based on an activation energy of 0.6 eV derates

with junction temperature.

¹¹Power supply current consumption is measured in normal mode following the power-on sequence, and in power-down modes under the following conditions:

Normal mode: reset = 0.4 V, digital I/O pins = open circuit, Core Clk changed via CD bits in PLLCON, core executing internal software loop.

Power-down mode: reset = 0.4 V, all P0 pins and P1.2 to P1.7 pins = 0.4 V. All other digital I/O pins are open circuit, core Clk changed via CD bits in PLLCON, PCON.1 = 1,

core execution suspended in power-down mode, OSC turned on or off via OSC_PD bit (PLLCON.7) in PLLCON SFR.

¹²DV_DDpower supply current increases typically by 3 mA (3 V operation) and 10 mA (5 V operation) during a Flash/EE memory program or erase cycle.

General Notes about Specifications

•

DAC gain error is a measure of the span error of the DAC.

The ADuC845BCP, ADuC847BCP, and ADuC848BCP (CSP package) have been qualified and tested with the base of the CSP

package floating. The base of the CSP package should be soldered to the board, but left floating electrically, to ensure good

mechanical stability.

•

Flash/EE memory reliability characteristics apply to both the Flash/EE program memory and Flash/EE data memory.

Rev. A | Page 9 of 108

ADuC845/ADuC847/ADuC848

ABOSOLUTE MAXIMUM RATINGS

T_A= 25°C, unless otherwise noted.

Table 2.

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those listed in the operational sections

of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Parameter

Rating

AV_DDto AGND

AV_DDto DGND

DV_DDto DGND

AGND to DGND¹

AV_DDto DV_DD

–0.3 V to +7 V

–0.3 V to +0.3 V

–2 V to +5 V

Analog Input Voltage to AGND²

Reference Input Voltage to AGND

AIN/REFIN Current (Indefinite)

Digital Input Voltage to DGND

Digital Output Voltage to DGND

Operating Temperature Range

Storage Temperature Range

Junction Temperature

θ_JAThermal Impedance (MQFP)

θ_JAThermal Impedance (LFCSP)

Lead Temperature, Soldering

Vapor Phase (60 sec)

–0.3 V to AV_DD+ 0.3 V

30 mA

–0.3 V to DV_DD+ 0.3 V

–40°C to +125°C

–65°C to +150°C

150°C

90°C/W

52°C/W

215°C

220°C

Infrared (15 sec)

________________________

¹AGND and DGND are shorted internally on the ADuC845, ADuC847, and ADuC848.

²Applies to the P1.0 to P1.7 pins operating in analog or digital input modes.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on

the human body and test equipment and can discharge without detection. Although this product features

proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy

electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance

degradation or loss of functionality.

Rev. A | Page 10 of 108

ADuC845/ADuC847/ADuC848

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

52 51 50 49 48 47 46 45 44 43 42 41 40

P2.7/PWMCLK

P2.6/PWM1

P2.5/PWM0

P2.4/T2EX

DGND

1

2

39

38

37

36

35

34

33

32

31

30

29

28

27

P1.0/AIN1

P1.1/AIN2

P1.2/AIN3/REFIN2+

P1.3/AIN4/REFIN2–

1

2

P2.7/PWMCLK

42

PIN 1

IDENTIFIER

41

40

39

38

37

36

P2.6/PWM1

P2.5/PWM0

P2.4/T2EX

DGND

PIN 1

3

4

IDENTIFIER

P1.2/AIN3/REFIN2+

P1.3/AIN4/REFIN2–

3

AV

DD

4

5

AV

DD

AGND

5

ADuC845/ADuC847/ADuC848

DV

DD

AGND

6

7

6

DGND

ADuC845/ADuC847/ADuC848

REFIN–

XTAL2

REFIN–

REFIN+

P1.4/AIN5

7

DV

DD

TOP VIEW

(Not to Scale)

REFIN+

8

9

XTAL1

8

35

34

33

XTAL2

TOP VIEW

(Not to Scale)

P1.4/AIN5

P2.3/SS/T2

P2.2/MISO

P2.1/MOSI

P2.0/SCLOCK (SPI)

SDATA

9

XTAL1

P1.5/AIN6

P1.6/AIN7/IEXC1

P1.7/AIN8/IEXC2

P1.5/AIN6 10

10

11

12

13

14

P2.3/SS/T2

P2.2/MISO

P2.1/MOSI

11

12

32

31

30

29

P1.6/AIN7/IEXC1

P1.7/AIN8/IEXC2

AINCOM/DAC

DAC

P2.0/SCLOCK (SPI)

SDATA

AINCOM/DAC 13

14 15 16 17 18 19 20 21 22 23 24 25 26

Figure 3. 56-Lead CSP Pin Configuration

Figure 2. 52-Lead MQFP Pin Configuration

Table 3. Pin Function Descriptions

Pin No: Pin No:

52-MQFP 56-CSP

Mnemonic

Type¹

Description

1

2

3

56

P1.0/AIN1

I

By power-on default, P1.0/AIN1 is configured as the AIN1 analog input.

AIN1 can be used as a pseudo differential input when used with AINCOM or as

the positive input of a fully differential pair when used with AIN2.

P1.0 has no digital output driver. It can function as a digital input for which 0

must be written to the port bit. As a digital input, this pin must be driven high or

low externally.

On power-on default, P1.1/AIN2 is configured as the AIN2 analog input.

AIN2 can be used as a pseudo differential input when used with AINCOM or as

the negative input of a fully differential pair when used with AIN1.

P1.1 has no digital output driver. It can function as a digital input for which 0

must be written to the port bit. As a digital input, this pin must be driven high or

low externally.

1

P1.1/AIN2

I

2

P1.2/AIN3/REFIN2+

On power-on default, P1.2/AIN3 is configured as the AIN3 analog input.

AIN3 can be used as a pseudo differential input when used with AINCOM or as

the positive input of a fully differential pair when used with AIN4.

P1.2 has no digital output driver. It can function as a digital input for which 0

must be written to the port bit. As a digital input, this pin must be driven high or

low externally. This pin also functions as a second external differential reference

input, positive terminal.

4

3

P1.3/AIN4/REFIN2−

I

On power-on default, P1.3/AIN4 is configured as the AIN4 analog input.

AIN4 can be used as a pseudo differential input when used with AINCOM or as

the negative input of a fully differential pair when used with AIN3.

P1.3 has no digital output driver. It can function as a digital input for which 0

must be written to the port bit. As a digital input, this pin must be driven high or

low externally. This pin also functions as a second external differential reference

input, negative terminal.

5

6

---

4

5

6

AV_DD

AGND

S

Analog Supply Voltage.

Analog Ground.

A second analog ground is provided with the CSP version only.

Footnotes at end of table.

Rev. A | Page 11 of 108

ADuC845/ADuC847/ADuC848

Pin No:

52-MQFP 56-CSP

Pin No:

Mnemonic

REFIN−

REFIN+

Type¹

Description

7

8

9

7

8

9

I

External Differential Reference Input, Negative Terminal.

External Differential Reference Input, Positive Terminal.

On power-on default, P1.4/AIN5 is configured as the AIN5 analog input.

P1.4/AIN5

AIN5 can be used as a pseudo differential input when used with AINCOM or as

the positive input of a fully differential pair when used with AIN6.

P1.0 has no digital output driver. It can function as a digital input for which 0

must be written to the port bit. As a digital input, this pin must be driven high or

low externally.

10

11

10

11

P1.5/AIN6

I

On power-on default, P1.5/AIN6 is configured as the AIN6 analog input.

AIN6 can be used as a pseudo differential input when used with AINCOM or as

the negative input of a fully differential pair when used with AIN5.

P1.1 has no digital output driver. It can function as a digital input for which 0

must be written to the port bit. As a digital input, this pin must be driven high or

low externally.

P1.6/AIN7/IEXC1

I/O

On power-on default, P1.6/AIN7 is configured as the AIN7 analog input.

AIN7 can be used as a pseudo differential input when used with AINCOM or as

the positive input of a fully differential pair when used with AIN8. One or both

current sources can also be configured at this pin.

P1.6 has no digital output driver. It can, however, function as a digital input for

which 0 must be written to the port bit. As a digital input, this pin must be

driven high or low externally.

12

13

12

13

P1.7/AIN8/IEXC2

AINCOM/DAC

I/O

On power-on default, P1.7/AIN8 is configured as the AIN8 analog input.

AIN8 can be used as a pseudo differential input when used with AINCOM or as

the negative input of a fully differential pair when used with AIN7. One or both

current sources can also be configured at this pin.

P1.7 has no digital output driver. It can, however, function as a digital input for

which 0 must be written to the port bit. As a digital input, this pin must be

driven high or low externally.

All analog inputs can be referred to this pin, provided that a relevant pseudo

differential input mode is selected. This pin also functions as an alternative pin

out for the DAC.

14

----

14

15

DAC

AIN9

O

I

The voltage output from the DAC, if enabled, appears at this pin.

AIN9 can be used as a pseudo differential analog input when used with AINCOM

or as the positive input of a fully differential pair when used with AIN10 (CSP

version only).

----

15

16

17

AIN10

I

AIN10 can be used as a pseudo differential analog input when used with

AINCOM or as the negative input of a fully differential pair when used with AIN9

(CSP version only).

Reset Input. A high level on this pin for 16 core clock cycles while the oscillator is

running resets the device. This pin has an internal weak pull-down and a Schmitt

trigger input stage.

RESET

I

16–19

22–25

18–21

24–27

P3.0–P3.7

I/O

P3.0 to P3.7 are bidirectional port pins with internal pull-up resistors. Port 3 pins

that have 1s written to them are pulled high by the internal pull-up resistors,

and in that state can be used as inputs. As inputs, Port 3 pins being pulled

externally low source current because of the internal pull-up resistors. When

driving a 0-to-1 output transition, a strong pull-up is active for one core clock

period of the instruction cycle.

Port 3 pins also have the various secondary functions described below.

Receiver Data for UART Serial Port.

Transmitter Data for UART Serial Port.

External Interrupt 0. This pin can also be used as a gate control input to Timer 0.

External Interrupt 1. This pin can also be used as a gate control input to Timer 1.

Timer/Counter 0 External Input.

Timer/Counter 1 External Input.

External Data Memory Write Strobe. This pin latches the data byte from Port 0

into an external data memory.

16

17

18

19

22

23

24

18

19

20

21

24

25

26

P3.0/RxD

P3.1/TxD

P3.2/INT0

P3.3/INT1

P3.4/T0

P3.5/T1

P3.6/WR

Rev. A | Page 12 of 108

ADuC845/ADuC847/ADuC848

Pin No:

52-MQFP 56-CSP

Pin No:

Mnemonic

Type¹

Description

25

27

P3.7/RD

External Data Memory Read Strobe. This pin enables the data from an external

data memory to Port 0.

22, 36, 51

20, 34, 48

21, 35, 47

DV_DD

DGND

S

Digital Supply Voltage.

Digital Ground.

23, 37,

38, 50

28

26

SCLK (I²C)

I/O

Serial Interface Clock for the I²C Interface. As an input, this pin is a Schmitt-

triggered input. A weak internal pull-up is present on this pin unless it is

outputting logic low. This pin can also be controlled in software as a digital

output pin.

27

29

SDATA

I/O

Serial Data Pin for the I²C Interface. As an input, this pin has a weak internal pull-

up present unless it is outputting logic low.

28–31,

36–39

30–33,

39–42

P2.0–P2.7

Port 2 is a bidirectional port with internal pull-up resistors. Port 2 pins that have

1s written to them are pulled high by the internal pull-up resistors, and in that

state can be used as inputs. As inputs, Port 2 pins being pulled externally low

source current because of the internal pull-up resistors. Port 2 emits the middle

and high-order address bytes during accesses to the 24-bit external data

memory space.

Port 2 pins also have the various secondary functions described below.

28

29

30

31

P2.0/SCLOCK (SPI)

P2.1/MOSI

Serial Interface Clock for the SPI Interface. As an input this pin is a Schmitt-

triggered input. A weak internal pull-up is present on this pin unless it is

outputting logic low.

Serial Master Output/Slave Input Data for the SPI Interface. A strong internal

pull-up is present on this pin when the SPI interface outputs a logic high. A

strong internal pull-down is present on this pin when the SPI interface outputs a

logic low.

30

31

32

33

P2.2/MISO

P2.3/SS/T2

Master Input/Slave Output for the SPI Interface. A weak pull-up is present on this

input pin.

Slave Select Input for the SPI Interface. A weak pull-up is present on this pin.

For both package options, this pin can also be used to provide a clock input to

Timer 2. When enabled, Counter 2 is incremented in response to a negative

transition on the T2 input pin.

36

39

P2.4/T2EX

Control Input to Timer 2. When enabled, a negative transition on the T2EX input

pin causes a Timer 2 capture or reload event.

37

38

39

32

33

40

41

42

34

35

P2.5/PWM0

P2.6/PWM1

P2.7/PWMCLK

XTAL1

If the PWM is enabled, the PWM0 output appears at this pin.

If the PWM is enabled, the PWM1 output appears at this pin.

If the PWM is enabled, an external PWM clock can be provided at this pin.

Input to the Crystal Oscillator Inverter.

Output from the Crystal Oscillator Inverter. See the Hardware Design

Considerations section for a description.

I

O

XTAL2

40

43

EA

External Access Enable, Logic Input. When held high, this input enables the

device to fetch code from internal program memory locations 0000H to F7FFH.

No external program memory access is available on the ADuC845, ADuC847, or

ADuC848. To determine the mode of code execution, the EA pin is sampled at

the end of an external RESET assertion or as part of a device power cycle. EA can

also be used as an external emulation I/O pin, and therefore the voltage level at

this pin must not be changed during normal operation because this might

cause an emulation interrupt that halts code execution.

41

42

44

45

PSEN

ALE

O

Program Store Enable, Logic Output. This function is not used on the ADuC845,

ADuC847, or ADuC848. This pin remains high during internal program execution.

PSEN can also be used to enable serial download mode when pulled low

through a resistor at the end of an external RESET assertion or as part of a device

power cycle.

Address Latch Enable, Logic Output. This output is used to latch the low byte

(and page byte for 24-bit data address space accesses) of the address to external

memory during external data memory access cycles. It can be disabled by

setting the PCON.4 bit in the PCON SFR.

Footnotes at end of table.

Rev. A | Page 13 of 108

ADuC845/ADuC847/ADuC848

Pin No:

52-MQFP 56-CSP

Pin No:

Mnemonic

Type¹

Description

43–46,

49–52

46–49,

52–55

P0.0–P0.7

I/O

These pins are part of Port 0, which is an 8-bit open-drain bidirectional I/O port.

Port 0 pins that have 1s written to them float, and, in that state, can be used as

high impedance inputs. An external pull-up resistor is required on P0 outputs to

force a valid logic high level externally. Port 0 is also the multiplexed low-order

address and data bus during accesses to external data memory. In this

application, Port 0 uses strong internal pull-ups when emitting 1s.

¹I = input, O = output, S = supply.

Rev. A | Page 14 of 108

ADuC845/ADuC847/ADuC848

GENERAL DESCRIPTION

The ADuC845, ADuC847, and ADuC848 are single-cycle,

12.58 MIPs, 8052 core upgrades to the ADuC834 and ADuC836.

They include additional analog inputs for applications requiring

more ADC channels.

The devices operate from a 32 kHz crystal with an on-chip PLL

generating a high frequency clock of 12.58 MHz. This clock is

routed through a programmable clock divider from which the

MCU core clock operating frequency is generated. The micro-

controller core is an optimized single-cycle 8052 offering up to

12.58 MIPs performance while maintaining 8051 instruction set

compatibility.

The ADuC845, ADuC847, and ADuC848 are complete smart

transducer front ends. The family integrates high resolution Σ-Δ

ADCs with flexible, up to 10-channel input multiplexing, a fast

8-bit MCU, and program/data Flash/EE memory on a single chip.

The available nonvolatile Flash/EE program memory options

are 62 kbytes, 32 kbytes, and 8 kbytes. 4 kbytes of nonvolatile

Flash/EE data memory and 2304 bytes of data RAM are also

provided on-chip. The program memory can be configured as

data memory to give up to 60 kbytes of NV data memory in

data logging applications.

The ADuC845 includes two (primary and auxiliary) 24-bit Σ-Δ

ADCs with internal buffering and PGA on the primary ADC.

The ADuC847 includes the same primary ADC as the ADuC845

(auxiliary ADC removed). The ADuC848 is a 16-bit ADC

version of the ADuC847.

On-chip factory firmware supports in-circuit serial download

and debug modes (via UART), as well as single-pin emulation

The ADCs incorporate flexible input multiplexing, a temperature

sensor (ADuC845 only), and a PGA (primary ADC only)

allowing direct measurement of low-level signals. The ADCs

include on-chip digital filtering and programmable output data

rates that are intended for measuring wide dynamic range, low

frequency signals, such as those in weigh scale, strain gage,

pressure transducer, or temperature measurement applications.

mode via the

pin. The ADuC845, ADuC847, and ADuC848

EA

are supported by the QuickStart™ development system featuring

low cost software and hardware development tools.

Rev. A | Page 15 of 108

ADuC845/ADuC847/ADuC848

46 47 48 49 52 53 54 55

56

1

2

3

9

10 11 12

30 31 32 33 39 40 41 42

16 17 18 19 22 23 24 25

56

1

AIN1

AIN2

AIN3

AIN4

AIN5

ADuC845

12-BIT

VOLTAGE

OUTPUT DAC

2

ADC

CONTROL

AND

DAC

CONTROL

BUF

14

PRIMARY ADC

24-BIT

Σ-∆ ADC

DAC

3

BUF

PGA

9

CALIBRATION

AIN

MUX

AIN6 10

AIN7 11

DUAL

16-BIT

40

41

42

ADC

CONTROL

AND

PWM0

PWM1

AUXILIARY ADC

24-BIT

PWM

CONTROL

Σ-∆ DAC

AIN8 12

MUX

DUAL

16-BIT

PWM

Σ-∆ ADC

AIN9* 15

AIN10* 16

AINCOM 13

CALIBRATION

PWMCLK

62 kBYTES PROGRAM/

FLASH/EE

BAND GAP

REFERENCE

2304 BYTES

USER RAM

24

25

33

39

T0

T1

16-BIT

COUNTER

TIMERS

SINGLE-

CYCLE

8052

TEMP

SENSOR

WATCHDOG

TIMER

4 kBYTES DATA/

FLASH/EE

T2

REFIN+

REFIN–

8

7

V

REF

T2EX

DETECT

MCU

POWER SUPPLY

MONITOR

CORE

2 × DATA POINTERS

11-BIT STACK POINTER

20

21

INT0

INT1

PLL WITH PROG.

CLOCK DIVIDER

200µA

DOWNLOADER

DEBUGGER

WAKE-UP/

RTC TIMER

CURRENT

SOURCE

MIX

IEXC1 11

IEXC1 12

2

UART

TIMER

SPI SERIAL

I C SERIAL

UART

SERIAL PORT

POR

INTERFACE INTERFACE

OSC

4

5

6

22 36 51

23 37 38 50

17

18 19

44 43 45

30 31 32 33

28 29

34

35

*THE PIN NUMBERS REFER TO THE CSP PACKAGE ONLY.

SHADED AREAS ARE UPGRADES FROM THE ADuC834, AND INCLUDE A SINGLE-CYCLE CORE, UP TO 10 ADC INPUT

CHANNELS (8 ON THE MQFP PACKAGE). THE AUXILIARY ADC IS NOW 24-BIT.

Figure 4. Detailed Block Diagram of the ADuC845

Rev. A | Page 16 of 108

ADuC845/ADuC847/ADuC848

46 47 48 49 52 53 54 55

56

1

2

3

9

10 11 12

30 31 32 33 39 40 41 42

16 17 18 19 22 23 24 25

56

1

AIN1

AIN2

AIN3

AIN4

AIN5

ADuC847

12-BIT

VOLTAGE

OUTPUT DAC

2

ADC

CONTROL

AND

DAC

CONTROL

PRIMARY ADC

24-BIT

Σ-∆ ADC

BUF

14

DAC

3

BUF

PGA

9

CALIBRATION

AIN

MUX

AIN6 10

AIN7 11

AIN8 12

AIN9* 15

DUAL

16-BIT

40

41

42

PWM0

PWM1

PWM

CONTROL

Σ-∆ DAC

MUX

DUAL

16-BIT

PWM

16

13

AIN10*

PWMCLK

AINCOM

62 kBYTES PROGRAM/

FLASH/EE

BAND GAP

REFERENCE

2304 BYTES

USER RAM

24

25

33

39

T0

T1

16-BIT

COUNTER

TIMERS

SINGLE-

CYCLE

8052

WATCHDOG

TIMER

4 kBYTES DATA/

FLASH/EE

T2

REFIN+

REFIN–

8

7

V

REF

T2EX

DETECT

MCU

CORE

POWER SUPPLY

MONITOR

2 × DATA POINTERS

11-BIT STACK POINTER

20

21

INT0

INT1

PLL WITH PROG.

CLOCK DIVIDER

200µA

DOWNLOADER

DEBUGGER

WAKE-UP/

RTC TIMER

CURRENT

SOURCE

MIX

IEXC1 11

IEXC1 12

2

SPI SERIAL

I C SERIAL

UART

SERIAL PORT

UART

TIMER

POR

INTERFACE INTERFACE

OSC

4

5

6

22 36 51

23 37 38 50

17

18 19

44 43 45

30 31 32 33

28 29

34

35

*THE PIN NUMBERS REFER TO THE CSP PACKAGE ONLY.

SHADED AREAS ARE UPGRADES FROM THE ADuC834, AND INCLUDE A SINGLE-CYCLE CORE, UP TO 10 ADC INPUT

CHANNELS (8 ON THE MQFP PACKAGE).

Figure 5. Detailed Block Diagram of the ADuC847

Rev. A | Page 17 of 108

ADuC845/ADuC847/ADuC848

46 47 48 49 52 53 54 55

56

1

2

3

9

10 11 12

30 31 32 33 39 40 41 42

16 17 18 19 22 23 24 25

56

1

AIN1

AIN2

AIN3

AIN4

AIN5

ADuC848

12-BIT

VOLTAGE

OUTPUT DAC

2

ADC

CONTROL

AND

DAC

CONTROL

PRIMARY ADC

16-BIT

Σ-∆ ADC

BUF

14

DAC

3

BUF

PGA

9

CALIBRATION

AIN

MUX

AIN6 10

AIN7 11

DUAL

16-BIT

40

41

42

PWM0

PWM1

PWM

CONTROL

Σ-∆ DAC

AIN8 12

MUX

DUAL

16-BIT

PWM

AIN9* 15

AIN10* 16

AINCOM 13

PWMCLK

62 kBYTES PROGRAM/

FLASH/EE

BAND GAP

REFERENCE

2304 BYTES

USER RAM

24

25

33

39

T0

T1

16-BIT

COUNTER

TIMERS

SINGLE-

CYCLE

8052

WATCHDOG

TIMER

4 kBYTES DATA/

FLASH/EE

T2

REFIN+

REFIN–

8

7

V

REF

T2EX

DETECT

MCU

CORE

POWER SUPPLY

MONITOR

2 × DATA POINTERS

11-BIT STACK POINTER

20

21

INT0

INT1

PLL WITH PROG.

CLOCK DIVIDER

200µA

DOWNLOADER

DEBUGGER

WAKE-UP/

RTC TIMER

CURRENT

SOURCE

MIX

IEXC1 11

IEXC1 12

2

UART

TIMER

SPI SERIAL

I C SERIAL

UART

SERIAL PORT

POR

INTERFACE INTERFACE

OSC

4

5

6

22 36 51

23 37 38 50

17

18 19

44 43 45

30 31 32 33

28 29

34

35

*THE PIN NUMBERS REFER TO THE CSP PACKAGE ONLY.

SHADED AREAS ARE UPGRADES FROM THE ADuC834, AND INCLUDE A SINGLE-CYCLE CORE, UP TO 10 ADC INPUT

CHANNELS (8 ON THE MQFP PACKAGE).

Figure 6. Detailed Block Diagram of the ADuC848

8052 INSTRUCTION SET

ALE

Table 4 documents the number of clock cycles required for each

instruction. Most instructions are executed in one or two clock

cycles resulting in 12.58 MIPs peak performance when operating

at PLLCON = 00H.

On the ADuC834, the output on the ALE pin is a clock at 1/6th

of the core operating frequency. On the ADuC845, ADuC847,

and ADuC848, the ALE pin operates as follows. For a single

machine cycle instruction, ALE is high for the entire machine

cycle. For a two or more machine cycle instruction, ALE is high

for the first machine cycle and then low for the remainder of

the machine cycles.

TIMER OPERATION

Timers on a standard 8052 increment by one with each machine

cycle. On the ADuC845, ADuC847, and ADuC848, one machine

cycle is equal to one clock cycle; therefore, the timers increment

at the same rate as the core clock.

EXTERNAL MEMORY ACCESS

The ADuC845, ADuC847, and ADuC848 do not support

external program memory access, but the parts can access up to

16 MB (24 address bits) of external data memory. When

accessing external RAM, the EWAIT register might need to be

programmed in order to give extra machine cycles to MOVX

commands to allow for differing external RAM access speeds.

Rev. A | Page 18 of 108

ADuC845/ADuC847/ADuC848

COMPLETE SFR MAP

SPICON

DACL

DACH

DACCON

ISPI

FFH

WCOL

SPE

FDH

SPIM

FCH

CPOL CPHA SPR1

SPR0

F8H

RESERVED RESERVED

SPIDAT

RESERVED RESERVED RESERVED

BITS

0

FEH

0

FBH

0

FAH

1

F9H

0

F8H

05H

FBH 00H FCH 00H FDH 00H

I2CADD1

RESERVED

B

NOT USED

GN0H ²

F7H

EFH

E7H

0

F6H

0

F5H

MCO

F4H

MDI

F3H

F2H

0

F1H

F0H

I2CI

E8H

E0H

D8H

F0H

00H

F2H

7FH

F7H

00H

GN0M ²

GN1L²

GN1H ²

MDO

MDE

GN0L²

OF0L

I2CCON

E8H

ACC

E0H 00H E1H

ADCSTAT

D8H

I2CM

EBH

I2CRS I2CTX

EAH

RESERVED RESERVED

ADuC845 ONLY ADuC845 ONLY

xxH ECH xxH EDH xxH

0

EEH

E6H

DEH

EDH

ECH

0

E9H

E1H

D9H

0

00H E9H

xxH EAH

xxH EBH

OF0M

xxH E2H

OF0H

OF1L OF1H

ADC0CON2

RESERVED

ADuC845 ONLY ADuC845 ONLY

xxH E5H

BITS

E5H

E4H

E3H

E2H

xxH E3H

xxH E4H

xxH E6H

00H

ADC0L

NOT AVAILABLE

ON ADuC848

ADC0M

ADC0H

ADC1M ADC1H

ADC1L

PSMCON

DFH DEH

PLLCON

RDY0

DFH

RDY1

CAL NOXREF ERR0

DDH

ERR1

DAH

ADuC845 ONLY ADuC845 ONLY ADuC845 ONLY

0

DCH

0

DBH

0

00H D9H

00H DAH 00H DBH 00H DCH 00H

DDH 00H DEH 00H

PSW

ADCMODE ADC0CON1 ADC1CON

SF

ICON

CY

D7H

AC

D6H

F0

D5H

RS1

D4H

RS0

D3H

OV

D2H

FI

D1H

P

D0H

RESERVED

ADuC845 ONLY

07H D3H 00H D4H

0

D0H 00H D1H

08H D2H

45H D5H

00H

D7H

53H

T2CON

C8H 00H

RCAP2L

RCAP2H

TL2 TH2

TF2

CFH

EXF2

CEH

RCLK

CDH

TCLK EXEN2

CCH

TR2

CNT2

C9H

CAP2

C8H

RESERVED

RESERVED RESERVED

0

CBH

0 CAH

CAH 00H CBH 00H CCH 00H CDH 00H

CHIPID

EDARH

00H C7H

00H

EDARL

WDCON

C0H 10H

PRE3

PRE2

C6H

PRE1

C5H

WDIR

C3H

WDS

C2H

WDE WDWR

PRE0

C4H

RESERVED

ECON

RESERVED RESERVED

RESERVED

C7H

0

1

0

C1H

0

C0H

0

C2H

A0H

C6H

IP

EDATA1

EDATA2

EDATA3

EDATA4

BFH 00H

SPH

PADC

BEH

PT2

BDH

PS

BCH

PT1

BBH

PX1

BAH

PT0

B9H

PX0

B8H

RESERVED RESERVED

BFH

0

1

0

1

0

1

0

1

0

B8H

B0H

00H B9H

00H

BCH 00H BDH 00H BEH 00H

PWM1L

B3H

PWM1H

P3

PWM0L

PWM0H

B2H

RD

B7H

WR

B6H

T1

B5H

T0

B4H

INT1

B3H

INT0

B2H

TxD

B1H

RxD

B0H

RESERVED RESERVED

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

B4H

00H

FFH

B1H

00H

CFG845/7/8

00H

B7H

PWMCON

IE

IEIP2

00H A9H A 0H

TIMECON HTHSEC¹

A1H

SBUF

00H 99H 00H 9AH

EA

AFH

EADC

ET2

ES

ACH

ET1

ABH

EX1

AAH

ET0

A9H

EX0

A8H

RESERVED RESERVED RESERVED RESERVED

AEH

0

ADH

A5H

0

1

0

1

0

1

AEH

00H

AFH

DPCON

A7H 00H

EWAIT

00H

A8H

A0H

HOUR¹

A5H 00H

T3FD

9DH

INTVAL

MIN¹

00H A4H 00H

I2CADD

9BH 55H

P2

SEC¹

00H A3H

I2CDAT

00H

A7H

A6H

1

A4H

A3H

A2H

A1H

A0H

A6H

00H

FFH

00H A2H

T3CON

SCON

SM0

9FH

SM1

SM2

REN

9CH

TB8

9BH

RB8

9AH

TI

99H

RI

98H

RESERVED

9EH

0

9DH

95H

98H

00H 9EH

00H 9FH

P1

T2EX

91H

T2

90H

RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED

97H

96H

1

0

1

94H

93H

92H

90H

FFH

TCON

TMOD

TL0

TL1

TH0

TH1

00H

TF1

8FH

TR1

8EH

TF0

8DH

TR0

8CH

IE1

8BH

IT1

8AH

IE0

89H

IT0

88H

RESERVED RESERVED

88H 00H 89H

00H 8AH

00H 8BH

00H 8CH

00H 8DH

P0

SP

DPL

DPH

DPP

00H

PCON

RESERVED

87H

86H

85H

84H

83H

82H

81H

80H

FFH 81H

07H 82H 00H 83H

00H 84H

87H

00H

1

2

THESE SFRs MAINTAIN THEIR PRE-RESET VALUES AFTER A RESET IF TIMECON.0 = 1.

CALIBRATION COEFFICIENTS ARE PRECONFIGURED ON POWER-UP TO FACTORY CALIBRATED VALUES.

SFR MAP KEY:

THESE BITS ARE CONTAINED IN THIS BYTE.

MNEMONIC

TCON

IT0

88H

BIT MNEMONIC

BIT ADDRESS

IE0

89H

0

RESET DEFAULT VALUE

88H 00H

RESET DEFAULT BIT VALUE

SFR ADDRESS

SFR NOTE:

SFRs WHOSE ADDRESSES END IN 0H OR 8H ARE BIT ADDRESSABLE.

Figure 7. Complete SFR Map for the ADuC845, ADuC847, and ADuC848

Rev. A | Page 19 of 108

ADuC845/ADuC847/ADuC848

FUNCTIONAL DESCRIPTION

8051 INSTRUCTION SET

Table 4. Optimized Single-Cycle 8051 Instruction Set

Mnemonic

Arithmetic

A A,Rn

Description

Bytes

Cycles¹

Add register to A

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

3

1

2

4

9

2

ADD A,@Ri

ADD A,dir

ADD A,#data

ADDC A,Rn

ADDC A,@Ri

ADDC A,dir

ADD A,#data

SUBB A,Rn

SUBB A,@Ri

SUBB A,dir

SUBB A,#data

INC A

INC Rn

INC @Ri

INC dir

INC DPTR

DEC A

Add indirect memory to A

Add direct byte to A

Add immediate to A

Add register to A with carry

Add indirect memory to A with carry

Add direct byte to A with carry

Add immediate to A with carry

Subtract register from A with borrow

Subtract indirect memory from A with borrow

Subtract direct from A with borrow

Subtract immediate from A with borrow

Increment A

Increment register

Increment indirect memory

Increment direct byte

Increment data pointer

Decrement A

Decrement register

DEC Rn

DEC @Ri

DEC dir

MUL AB

DIV AB

DA A

Decrement indirect memory

Decrement direct byte

Multiply A by B

Divide A by B

Decimal adjust A

Logic

ANL A,Rn

ANL A,@Ri

ANL A,dir

ANL A,#data

ANL dir,A

ANL dir,#data

ORL A,Rn

ORL A,@Ri

ORL A,dir

ORL A,#data

ORL dir,A

ORL dir,#data

XRL A,Rn

XRL A,@Ri

XRL A,#data

XRL dir,A

XRL A,dir

XRL dir,#data

CLR A

AND register to A

AND indirect memory to A

AND direct byte to A

AND immediate to A

AND A to direct byte

AND immediate data to direct byte

OR register to A

OR indirect memory to A

OR direct byte to A

OR immediate to A

OR A to direct byte

OR immediate data to direct byte

Exclusive-OR register to A

Exclusive-OR indirect memory to A

Exclusive-OR immediate to A

Exclusive-OR A to direct byte

Exclusive-OR indirect memory to A

Exclusive-OR immediate data to direct

Clear A

1

2

3

1

2

3

1

2

3

1

2

3

1

2

3

1

2

3

1

CPL A

SWAP A

RL A

Complement A

Swap Nibbles of A

Rotate A left

Rev. A | Page 20 of 108

ADuC845/ADuC847/ADuC848

Mnemonic

RLC A

RR A

Description

Bytes

Cycles¹

Rotate A left through carry

Rotate A right

Rotate A right through carry

1

RRC A

Data Transfer

MOV A,Rn

MOV A,@Ri

MOV Rn,A

MOV @Ri,A

MOV A,dir

MOV A,#data

MOV Rn,#data

MOV dir,A

MOV Rn, dir

MOV dir, Rn

MOV @Ri,#data

MOV dir,@Ri

MOV @Ri,dir

MOV dir,dir

MOV dir,#data

MOV DPTR,#data

MOVC A,@A+DPTR

MOVC A,@A+PC

MOVX²A,@Ri

MOVX²A,@DPTR

MOVX²@Ri,A

MOVX²@DPTR,A

PUSH dir

Move register to A

Move indirect memory to A

Move A to register

Move A to indirect memory

Move direct byte to A

Move immediate to A

Move register to immediate

Move A to direct byte

Move register to direct byte

Move direct to register

Move immediate to indirect memory

Move indirect to direct memory

Move direct to indirect memory

Move direct byte to direct byte

Move immediate to direct byte

Move immediate to data pointer

Move code byte relative DPTR to A

Move code byte relative PC to A

Move external (A8) data to A

Move external (A16) data to A

Move A to external data (A8)

Move A to external data (A16)

Push direct byte onto stack

Pop direct byte from stack

Exchange A and register

1

2

3

1

2

1

2

1

2

1

2

3

4

2

1

2

POP dir

XCH A,Rn

XCH A,@Ri

XCHD A,@Ri

XCH A,dir

Exchange A and indirect memory

Exchange A and indirect memory nibble

Exchange A and direct byte

Boolean

CLR C

CLR bit

SETB C

SETB bit

CPL C

CPL bit

ANL C,bit

ANL C,/bit

ORL C,bit

Clear carry

Clear direct bit

Set carry

Set direct bit

Complement carry

Complement direct bit

AND direct bit and carry

AND direct bit inverse to carry

OR direct bit and carry

OR direct bit inverse to carry

Move direct bit to carry

Move carry to direct bit

1

2

1

2

1

2

1

2

1

2

1

2

ORL C,/bit

MOV C,bit

MOV bit,C

Branching

JMP @A+DPTR

RET

Jump indirect relative to DPTR

Return from subroutine

Return from interrupt

Absolute jump to subroutine

Absolute jump unconditional

1

2

3

4

3

RETI

ACALL addr11

AJMP addr11

Footnotes at end of table.

Rev. A | Page 21 of 108

ADuC845/ADuC847/ADuC848

Mnemonic

SJMP rel

JC rel

JNC rel

JZ rel

Description

Bytes

Cycles¹

Short jump (relative address)

Jump on carry = 1

Jump on carry = 0

Jump on accumulator = 0

Jump on accumulator ! = 0

Decrement register, JNZ relative

Long jump unconditional

Long jump to subroutine

2

3

4

JNZ rel

DJNZ Rn,rel

LJMP

LCALL³addr16

JB bit,rel

Jump on direct bit = 1

Jump on direct bit = 0

JNB bit,rel

JBC bit,rel

CJNE A,dir,rel

CJNE A,#data,rel

CJNE Rn,#data,rel

CJNE @Ri,#data,rel

DJNZ dir,rel

Miscellaneous

NOP

Jump on direct bit = 1 and clear

Compare A, direct JNE relative

Compare A, immediate JNE relative

Compare register, immediate JNE relative

Compare indirect, immediate JNE relative

Decrement direct byte, JNZ relative

No operation

1

¹One cycle is one clock.

²MOVX instructions are four cycles when they have 0 wait state. Cycles of MOVX instructions are 4 + n cycles when they have n wait states as programmed via EWAIT.

³LCALL instructions are three cycles when the LCALL instruction comes from an interrupt.

Flash/EE Data Memory

MEMORY ORGANIZATION

The user has 4 kbytes of Flash/EE data memory available that

The ADuC845, ADuC847, and ADuC848 contain four memory

can be accessed indirectly by using a group of registers mapped

blocks:

into the special function register (SFR) space. For details, see the

•

62 kbytes/32 kbytes/8 kbytes of on-chip Flash/EE program

memory

Nonvolatile Flash/EE Memory section.

General-Purpose RAM

•

4 kbytes of on-chip Flash/EE data memory

256 bytes of general-purpose RAM

2 kbytes of internal XRAM

The general-purpose RAM is divided into two separate

memories, the upper and the lower 128 bytes of RAM. The

lower 128 bytes of RAM can be accessed through direct or

indirect addressing. The upper 128 bytes of RAM can be

accessed only through indirect addressing becuase it shares the

same address space as the SFR space, which must be accessed

through direct addressing.

Flash/EE Program Memory

The parts provide up to 62 kbytes of Flash/EE program memory

to run user code. All further references to Flash/EE program

memory assume the 62-kbyte option.

The lower 128 bytes of internal data memory are mapped as

shown in Figure 8. The lowest 32 bytes are grouped into four

banks of eight registers addressed as R0 to R7. The next 16 bytes

(128 bits), locations 20H to 2FH above the register banks, form

a block of directly addressable bit locations at Bit Addresses

00H to 7FH. The stack can be located anywhere in the internal

memory address space, and the stack depth can be expanded up

to 2048 bytes.

When

is pulled high externally during a power cycle or a

EA

hardware reset, the parts default to code execution from their

internal 62 kbytes of Flash/EE program memory. The parts do

not support the rollover from internal code space to external

code space. No external code space is available on the parts.

Permanently embedded firmware allows code to be serially

downloaded to the 62 kbytes of internal code space via the

UART serial port while the device is in-circuit. No external

hardware is required.

Reset initializes the stack pointer to location 07H. Any call or

push pre-increments the SP before loading the stack. Therefore,

loading the stack starts from location 08H, which is also the

first register (R0) of Register Bank 1. Thus, if one is going to use

more than one register bank, the stack pointer should be

initialized to an area of RAM not used for data storage.

During run time, 56 kbytes of the 62-kbyte program memory

can be reprogrammed. This means that the code space can be

upgraded in the field by using a user-defined protocol running

on the parts, or it can be used as a data memory. For details, see

the Nonvolatile Flash/EE Memory section.

Rev. A | Page 22 of 108

ADuC845/ADuC847/ADuC848

7FH

2FH

is possible (by setting CFG845.7/ADuC847.7/ADuC848.7) to

enable the 11-bit extended stack pointer. In this case, the stack

rolls over from FFH in RAM to 0100H in XRAM.

GENERAL-PURPOSE

AREA

30H

The 11-bit stack pointer is visible in the SPH and SP SFRs. The

SP SFR is located at 81H as with a standard 8052. The SPH SFR

is located at B7H. The 3 LSBs of the SPH SFR contain the 3

extra bits necessary to extend the 8-bit stack pointer in the SP

SFR into an 11-bit stack pointer.

BIT-ADDRESSABLE

(BIT ADDRESSES)

BANKS

SELECTED

VIA

20H

18H

10H

BITS IN PSW

1FH

17H

0FH

07H

11

10

01

00

07FFH

FOUR BANKS OF EIGHT

REGISTERS

R0 TO R7

08H

00H

UPPER 1792

BYTES OF

ON-CHIP XRAM

(DATA + STACK

FOR EXSP = 1,

DATA ONLY

RESET VALUE OF

STACK POINTER

Figure 8. Lower 128 Bytes of Internal Data Memory

FOR EXSP = 0)

Internal XRAM

CFG845/7/8.7 = 0 CFG845/7/8.7 = 1

The ADuC845, ADuC847, and ADuC848 contain 2 kbytes of

on-chip extended data memory. This memory, although on-

chip, is accessed via the MOVX instruction. The 2 kbytes of

internal XRAM are mapped into the bottom 2 kbytes of the

external address space if the CFG84x.0 (Table 7) bit is set;

otherwise, access to the external data memory occurs just like a

standard 8051.

100H

FFH

256 BYTES OF

LOWER 256

ON-CHIP DATA

BYTES OF

RAM

(DATA +

STACK)

ON-CHIP XRAM

(DATA ONLY)

00H

Figure 10. Extended Stack Pointer Operation

External Data Memory (External XRAM)

Even with the CFG84x.0 bit set, access to the external (off chip),

XRAM occurs once the 24-bit DPTR is greater than 0007FFH.

There is no support for external program memory access to the

parts. However, just like a standard 8051 compatible core, the

ADuC845/ADuC847/ADuC848 can access external data

memory using a MOVX instruction. The MOVX instruction

automatically outputs the various control strobes required to

access the data memory. The parts, however, can access up to

16 Mbytes of external data memory. This is an enhancement of

the 64 kbytes of external data memory space available on a

standard 8051 compatible core. See the Hardware Design

Considerations section for details.

FFFFFFH

EXTERNAL

DATA

MEMORY

SPACE

EXTERNAL

DATA

MEMORY

SPACE

(24-BIT

ADDRESS

SPACE)

(24-BIT

ADDRESS

SPACE)

When accessing external RAM, the EWAIT register might need

to be programmed to give extra machine cycles to the MOVX

operation. This is to account for differing external RAM access

speeds.

000800H

0007FFH

2 kBYTES

ON-CHIP

XRAM

000000H

CFG845/7/8.0 = 0

CFG845/7/8.0 = 1

EWAIT SFR

SFR Address:

Power-On Default:

Bit Addressable:

9FH

00H

No

Figure 9. Internal and External XRAM

When enabled and when accessing the internal XRAM, the P0

and P2 port pin operations, as well as the and strobes,

RD

WR

This special function register (SFR), when programmed,

dictates the number of wait states for the MOVX instruction.

The value can vary between 0H and 7H. The MOVX instruction

increases by one machine cycle (4 + n, where n = EWAIT

number in decimal) for every increase in the EWAIT value.

do not operate as a standard 8051 MOVX instruction. This

allows the user to use these port pins as standard I/O. The

internal XRAM can be configured as part of the extended 11-bit

stack pointer. By default, the stack operates exactly like an 8052

in that it rolls over from FFH to 00H in the general-purpose

RAM. On the ADuC845, ADuC847, and ADuC848, however, it

Rev. A | Page 23 of 108

ADuC845/ADuC847/ADuC848

Data Pointer (DPTR)

SPECIAL FUNCTION REGISTERS (SFRs)

The data pointer is made up of three 8-bit registers: DPP (page

byte), DPH (high byte), and DPL (low byte). These provide

memory addresses for internal code and data memory access.

The DPTR can be manipulated as a 16-bit register (DPTR =

DPH, DPL), although INC DPTR instructions automatically

carry over to DPP, or as three independent 8-bit registers (DPP,

DPH, DPL).

The SFR space is mapped into the upper 128 bytes of internal

data memory space and accessed by direct addressing only. It

provides an interface between the CPU and all on-chip periph-

erals. A block diagram showing the programming model of the

ADuC845/ADuC847/ADuC848 via the SFR area is shown in

Figure 11.

All registers except the program counter (PC) and the four

general-purpose register banks reside in the SFR area. The SFR

registers include control, configuration, and data registers that

provide an interface between the CPU and all on-chip peripherals.

The ADuC845/ADuC847/ADuC848 supports dual data

pointers. See the Dual Data Pointers section.

Stack Pointer (SP and SPH)

The SP SFR is the stack pointer, which is used to hold an

internal RAM address called the top of the stack. The SP register

is incremented before data is stored during PUSH and CALL

executions. Although the stack can reside anywhere in on-chip

RAM, the SP register is initialized to 07H after a reset. This

causes the stack to begin at location 08H.

62-kBYTE

ELECTRICALLY

REPROGRAMMABLE

NONVOLATILE

4-kBYTE

ELECTRICALLY

REPROGRAMMABLE

NONVOLATILE

FLASH/EE PROGRAM

FLASH/EE DATA

MEMORY

128-BYTE

SPECIAL

FUNCTION

REGISTER

AREA

8051

COMPATIBLE

CORE

As mentioned earlier, the parts offer an extended 11-bit stack

pointer. The 3 extra bits needed to make up the 11-bit stack

pointer are the 3 LSBs of the SPH byte located at B7H. To enable

the SPH SFR, the EXSP (CFG84x.7) bit must be set; otherwise,

the SPH SFR can be neither written to nor read from.

Σ-∆ ADC

OTHER ON-CHIP

PERIPHERALS

TEMPERATURE

SENSOR

CURRENT SOURCES

12-BIT DAC

SERIAL I/O

WDT

256 BYTES RAM

2kBYTES XRAM

Program Status Word (PSW)

The PSW SFR contains several bits that reflect the current

status of the CPU as listed in Table 5.

PSM

TIC

PWM

SFR Address:

Power-On Default:

Bit Addressable:

D0H

00H

Yes

Figure 11. Programming Model

Accumulator SFR (ACC)

ACC is the accumulator register, which is used for math opera-

tions including addition, subtraction, integer multiplication and

division, and Boolean bit manipulations. The mnemonics for

accumulator-specific instructions usually refer to the accumulator

as A.

Table 5. PSW SFR Bit Designations

Bit No.

Name

Description

7

CY

Carry Flag.

6

5

AC

F0

Auxiliary Carry Flag.

General-Purpose Flag.

B SFR (B)

The B register is used with the accumulator for multiplication

and division operations. For other instructions, it can be treated

as a general-purpose scratch pad register.

4, 3

RS1, RS0 Register Bank Select Bits.

RS1 RS0 Selected Bank

0

1

0

1

0

1

0

1

2

3

2

1

0

OV

F1

P

Overflow Flag.

General-Purpose Flag.

Parity Bit.

Rev. A | Page 24 of 108

ADuC845/ADuC847/ADuC848

Power Control Register (PCON)

ADuC845/ADuC847/ADuC848 Configuration Register

(CFG845/CFG847/CFG848)

The PCON SFR contains bits for power-saving options and

general-purpose status flags as listed in Table 6.

The CFG845/CFG847/CFG848 SFR contains the bits necessary

to configure the internal XRAM and the extended SP. By default,

it configures the user into 8051 mode, that is, extended SP, and

the internal XRAM are disabled. When using in a program, use

the part name only, that is, CFG845, CFG847, or CFG848.

SFR Address:

Power-On Default:

Bit Addressable:

87H

00H

No

SFR Address:

Power-On Default:

Bit Addressable:

AFH

00H

No

Table 6. PCON SFR Bit Designations

Bit No.

Name

Description

7

SMOD

Double UART Baud Rate.

0 = Normal, 1 = Double Baud Rate.

Table 7. CFG845/CFG847/CFG848 SFR Bit Designations

6

5

SERIPD Serial Power-Down Interrupt Enable. If this

bit is set, a serial interrupt from either SPI

or I²C can terminate the power-down

mode.

INT0PD INT0 Power-Down Interrupt Enable.

If this bit is set, either a level (IT0 = 0) or a

negative-going transition (IT0 = 1) on the

INT0 pin terminates power-down mode.

ALEOFF If set to 1, the ALE output is disabled.

Bit No.

Name

Description

7

EXSP

Extended SP Enable.

If this bit is set to 1, the stack rolls over

from SPH/SP = 00FFH to 0100H.

If this bit is cleared to 0, SPH SFR is

disabled and the stack rolls over from

SP = FFH to SP = 00H.

4

3

2

1

6

5

4

3

2

1

0

----

Not Implemented. Write Don’t Care.,

Not Implemented. Write Don’t Care.

GF1

GF0

PD

General-Purpose Flag Bit.

Power-Down Mode Enable. If set to 1, the

part enters power-down mode.

0

-----

Not Implemented. Write Don’t Care.

XRAMEN If this bit is set to 1, the internal XRAM is

mapped into the lower 2 kbytes of the

external address space.

If this bit is cleared to 0, the internal XRAM

is accessible and up to 16 MB of external

data memory become available. See

Figure 8.

Rev. A | Page 25 of 108

ADuC845/ADuC847/ADuC848

capacitor (10 nF to 100 nF) be placed on the input to the ADC

(usually as part of an antialiasing filter) to aid in noise

performance.

ADC CIRCUIT INFORMATION

The ADuC845 incorporates two 10-channel (8-channel on the

MQFP package) 24-bit Σ-∆ ADCs, while the ADuC847 and

ADuC848 each incorporate a single 10-channel (8-channel on

the MQFP package) 24-bit and 16-bit Σ-∆ ADC.

The input channels are intended to convert signals directly from

sensors without the need for external signal conditioning. With

internal buffering disabled (relevant bits set/cleared in

ADC0CON1), external buffering might be required.

Each part also includes an on-chip programmable gain

amplifier and configurable buffering (neither is available on the

auxiliary ADC on the ADuC845). The parts also incorporate

digital filtering intended for measuring wide dynamic range and

low frequency signals such as those in weigh-scale, strain-gage,

pressure transducer, or temperature measurement applications.

When the internal buffer is enabled, it might be necessary to

offset the negative input channel by +100 mV and to offset the

positive channel by −100 mV if the reference range is AV_DD

.

This accounts for the restricted common-mode input range in

the buffer. Some circuits, for example, bridge circuits, are

inherently suitable to use without having to offset where the

output voltage is balanced around V_REF/2 and is not sufficiently

large to encroach on the supply rails. Internal buffering is not

available on the auxiliary ADC (ADuC845 only). The auxiliary

ADC (ADuC845 only) is fixed at a gain range of 2.50 V.

The ADuC845/ADuC847/ADuC848 can be configured as four

or five (MQFP/LFCSP package) fully-differential input channels

or as eight or ten (MQFP/LFCSP package) pseudo differential

input channels referenced to AINCOM. The ADC on each part

(primary only on the ADuC845) can be fully buffered internally,

and can be programmed for one of eight input ranges from

20 mV to 2.56 V (V_REF× 1.024). Buffering the input channel

means that the part can handle significant source impedances

on the selected analog input and that RC filtering (for noise

rejection or RFI reduction) can be placed on the analog inputs.

It should be noted that if the ADC is used with internal buffering

disabled (ADC0CON1.7 = 1, ADC0CON1.6 = 0), these un-

buffered inputs provide a dynamic load to the driving source.

Therefore, resistor/capacitor combinations on the inputs can

cause dc gain errors, depending on the output impedance of the

source that is driving the ADC inputs.

The ADCs use a Σ-Δ conversion technique to realize up to

24 bits on the ADuC845 and the ADuC847 and up to 16 bits on

the ADuC848 of no missing codes performance (20 Hz update

rate, chop enabled). The Σ-Δ modulator converts the sampled

input signal into a digital pulse train whose duty cycle contains

the digital information. A sinc³programmable low-pass filter

(see Table 28) is then used to decimate the modulator output

data stream to give a valid data conversion result at program-

mable output rates. The signal chain has two modes of operation,

chop enabled and chop disabled. The

bit in the

CHOP

ADCMODE register enables or disables the chopping scheme.

Table 8 and Table 9 show the allowable external resistance/

capacitance values for unbuffered mode such that no gain error

at the 16-bit and 20-bit levels, respectively, is introduced. When

used with internal buffering enabled, it is recommended that a

Table 8. Maximum Resistance for No 16-Bit Gain Error (Unbuffered Mode)

External Capacitance

Gain

0 pF

50 pF

100 pF

16.7 kΩ

8.1 kΩ

3.9 kΩ

1.7 kΩ

500 pF

4.5 kΩ

2.2 kΩ

1.0 kΩ

480 Ω

1000 pF

2.58 kΩ

1.26 kΩ

600 Ω

5000 pF

700 Ω

360 Ω

170 Ω

75 Ω

1

2

4

111.3 kΩ

53.7 kΩ

25.4 kΩ

10.7 kΩ

27.8 kΩ

13.5 kΩ

6.4 kΩ

2.9 kΩ

8–128

270 Ω

Table 9. Maximum Resistance for No 20-Bit Gain Error (Unbuffered Mode)

External Capacitance

Gain

0 pF

50 pF

100 pF

12.5 kΩ

6.1 kΩ

2.9 kΩ

1.3 k Ω

500 pF

3.2 kΩ

1.6 kΩ

790 Ω

370 Ω

1000 pF

1.77 kΩ

880 Ω

430 Ω

195 Ω

5000 pF

440 Ω

220 Ω

110 Ω

50 Ω

1

2

4

84.9 kΩ

42.0 kΩ

20.5 kΩ

8.8 kΩ

21.1 kΩ

10.4 kΩ

5.0 kΩ

2.3 k Ω

8–128

Rev. A | Page 26 of 108

ADuC845/ADuC847/ADuC848

Signal Chain Overview (Chop Enabled,

= 0)

CHOP

With chop enabled, the ADC repeatedly reverses its inputs. The

decimated digital output words from the Sinc³filter, therefore,

have a positive offset and a negative offset term included. As a

result, a final summing stage is included so that each output

word from the filter is summed and averaged with the previous

filter output to produce a new valid output result to be written

to the ADC data register. Programming the Sinc³decimation

factor is restricted to an 8-bit register called SF (see Table 28),

the actual decimation factor is the register value times 8.

Therefore, the decimated output rate from the Sinc³filter (and

the ADC conversion rate) is

CHOP

With the

bit = 0 (see the ADCMODE SFR bit designa-

tions in Table 24), the chopping scheme is enabled. This is the

default condition and gives optimum performance in terms of

offset errors and drift performance. With chop enabled, the

available output rates vary from 5.35 Hz to 105 Hz (SF = 255

and 13, respectively). A typical block diagram of the ADC input

channel with chop enabled is shown in Figure 12.

The sampling frequency of the modulator loop is many times

higher than the bandwidth of the input signal. The integrator in

the modulator shapes the quantization noise (which results

from the analog-to-digital conversion) so that the noise is pushed

toward one-half of the modulator frequency. The output of the

Σ-Δ modulator feeds directly into the digital filter. The digital

filter then band-limits the response to a frequency significantly

lower than one-half of the modulator frequency. In this manner,

the 1-bit output of the comparator is translated into a band

limited, low noise output from the ADCs.

1

3

1

f_ADC

=

×

× f_MOD

8× SF

where:

_ADCis the ADC conversion rate.

f

SF is the decimal equivalent of the word loaded to the filter

register.

f

_MODis the modulator sampling rate of 32.768 kHz.

The ADC filter is a low-pass Sinc³or (sinx/x)³filter whose

primary function is to remove the quantization noise introduced

at the modulator. The cutoff frequency and decimated output

data rate of the filter are programmable via the Sinc filter word

loaded into the filter (SF) register (see Table 28). The complete

signal chain is chopped, resulting in excellent dc offset and

offset drift specifications and is extremely beneficial in applica-

tions where drift, noise rejection, and optimum EMI rejection

are important.

The chop rate of the channel is half the output data rate:

1

f_CHOP

=

2× f_ADC

As shown in the block diagram (Figure 12), the Sinc³filter

outputs alternately contain +V_OSand −V_OS, where V_OSis the

respective channel offset.

F

ADC

CHOP

IN

MOD

CHOP

Σ-∆

2

Σ-∆

MOD

ANALOG

INPUT

DIGITAL

OUTPUT

3

XOR

MUX

BUF

PGA

SINC FILTER

3 × (8 × SF)

AIN + V

AIN – V

OS

Figure 12. Block Diagram of the ADC Input Channel with Chop Enabled

Rev. A | Page 27 of 108

ADuC845/ADuC847/ADuC848

This offset is removed by performing a running average of 2.

This average by 2 means that the settling time to any change in

programming of the ADC is twice the normal conversion time,

while an asynchronous step change on the analog input is not

fully reflected until the third subsequent output. See Figure 13.

The allowable range for SF (chop enabled) is 13 to 255 with

a default of 69 (45H). The corresponding conversion rates,

rms and peak-to-peak noise performances are shown in

Table 10, Table 11, Table 12, and Table 13. The numbers are

typical and generated at a differential input voltage of 0 V

and a common-mode voltage of 2.5 V. Note that the con-

version time increases by 0.732 ms for each increment in SF.

2

t_SETTLE

=

= 2×t_ADC

f_ADC

SYNCHRONOUS CHANGE

(I.E. CHANNEL CHANGE)

SAMPLE 1

SAMPLE 2

SAMPLE 3

SAMPLE 4

SAMPLE 5

SAMPLE 6

NO/INVALID

OUTPUT

SAMPLE 3 + SAMPLE 4

2

SAMPLE 1 + SAMPLE 2

2

NO OUTPUT

VALID OUTPUT

SAMPLE 2 + SAMPLE 3

SAMPLE 4 + SAMPLE 5

2

VALID OUTPUT

SAMPLE 5 + SAMPLE 6

2

VALID OUTPUT

Figure 13. ADC Settling Time Following a Synchronous Change with

Chop Enabled

ASYNCHRONOUS CHANGE

(I.E. DISCONTINUOUS INPUT CHANGE)

SAMPLE 1

SAMPLE 2

SAMPLE 3

SAMPLE 4

SAMPLE 5

SAMPLE 6

NO OUTPUT

SAMPLE 3 + SAMPLE 4

2

SAMPLE 1 + SAMPLE 2

2

UNSETTLED OUTPUT

VALID OUTPUT

SAMPLE 2 + SAMPLE 3

SAMPLE 4 + SAMPLE 5

2

VALID OUTPUT

UNSETTLED OUTPUT

SAMPLE 5 + SAMPLE 6

2

VALID OUTPUT

Figure 14. ADC Settling Time Following an Asynchronous Change with

Chop Enabled

Rev. A | Page 28 of 108

ADuC845/ADuC847/ADuC848

ADC Noise Performance with Chop Enabled (

= 0)

CHOP

used in the implementation of the modulator. The second

source is quantization noise, which is added when the analog

input is converted to the digital domain. The device noise is at a

low level and is independent of frequency. The quantization

noise starts at an even lower level but rises rapidly with increasing

frequency to become the dominant noise source.

Table 10, Table 11, Table 12, and Table 13 show the output rms

noise and output peak-to-peak resolution in bits (rounded to

the nearest 0.5 LSB) for some typical output update rates for the

ADuC845, ADuC847, and ADuC848. The numbers are typical

and are generated at a differential input voltage of 0 V and a

common-mode voltage of 2.5 V. The output update rate is

selected via the SF7 to SF0 bits in the SF filter register. It is

important to note that the peak-to-peak resolution figures

represent the resolution for which there is no code flicker

within a 6-sigma limit.

The numbers in the tables are given for the bipolar input ranges.

For the unipolar ranges, the rms noise numbers are in the same

range as the bipolar figures, but the peak-to-peak resolution is

based on half the signal range, which effectively means losing

1 bit of resolution.

The output noise comes from two sources. The first source is

the electrical noise in the semiconductor devices (device noise)

Table 10. ADuC845 and ADuC847 Typical Output RMS Noise (µV) vs. Input Range and Update Rate with Chop Enabled

Input Range

SF Word

13

23

27

69

Data Update Rate (Hz)

20 mV

1.75

1.25

1.0

0.63

0.31

40 mV

1.30

0.95

1.0

0.68

0.38

80 mV

1.65

1.08

0.85

0.52

0.34

160 mV

1.5

0.94

0.85

0.7

320 mV

2.1

1.0

1.13

0.61

0.4

640 mV

3.1

1.87

1.56

1.1

1.28 V

7.15

3.24

2.9

1.3

0.68

2.56 V

13.3

7.1

3.6

2.75

1.22

105.03

59.36

50.56

19.79

5.35

255

0.32

0.45

Table 11. ADuC845 and ADuC847 Typical Peak-to-Peak Resolution (Bits) vs. Input Range and Update Rate with Chop Enabled

Input Range

SF Word

13

23

27

69

Data Update Rate (Hz)

20 mV

12

12.5

13

14.5

40 mV

13

13.5

14

80 mV

14

14.5

15

15.5

16

160 mV

15

15.5

16

17

320 mV

15.5

16.5

17.5

18

640 mV

16

16.5

17

17.5

18.5

1.28 V

16

17

18

19

2.56 V

16

16.5

17.5

18

105.03

59.36

50.56

19.79

5.35

255

15

19.5

Table 12. ADuC848 Typical Output Noise (µV) vs. Input Range and Update Rate with Chop Enabled

Input Range

SF Word

13

23

27

69

Data Update Rate (Hz)

20 mV

1.75

1.25

1.0

0.63

0.31

40 mV

1.30

0.95

1.0

0.68

0.38

80 mV

1.65

1.08

0.85

0.52

0.34

160 mV

1.5

0.94

0.85

0.7

320 mV

2.1

1.0

1.13

0.61

0.4

640 mV

3.1

1.87

1.56

1.1

1.28 V

2.56 V

105.03

59.36

50.56

19.79

5.35

7.15

3.24

2.9

1.3

0.68

13.3

7.1

3.6

2.75

1.22

255

0.32

0.45

Table 13. ADuC848 Typical Peak-to-Peak Resolution (Bits) vs. Input Range and Update Rate with Chop Enabled

Input Range

SF Word

13

23

27

69

Data Update Rate (Hz)

20 mV

12

12.5

13

14.5

40 mV

13

13.5

14

80 mV

14

14.5

15

15.5

16

160 mV

15

15.5

16

320 mV

15.5

16

640 mV

16

1.28 V

2.56 V

105.03

59.36

50.56

19.79

5.35

16

17

16

255

15

Rev. A | Page 29 of 108

ADuC845/ADuC847/ADuC848

Signal Chain Overview with Chop Disabled (

= 1)

CHOP

The settling time to a step input is governed by the digital filter.

A synchronized step change requires a settling time of three

times the programmed update rate; a channel change can be

treated as a synchronized step change. This is one conversion

longer than the case for chop enabled. However, because the

ADC throughput is three times faster with chop disabled than it

is with chop enabled, the actual time to a settled ADC output is

significantly less also. This means that following a synchronized

step change, the ADC requires three conversions (note: data is

not output following a synchronized ADC change until data has

settled) before the result accurately reflects the new input

voltage.

With

= 1, chop is disabled and the available output rates

CHOP

vary from 16.06 Hz to 1.365 kHz. The range of applicable SF

words is from 3 to 255. When switching between channels with

chop disabled, the channel throughput rate is higher than when

chop is enabled. The drawback with chop disabled is that the

drift performance is degraded and offset calibration is required

following a gain range change or significant temperature

change. A block diagram of the ADC input channel with chop

disabled is shown in Figure 15.

The signal chain includes a multiplex or buffer, PGA, Σ-Δ

modulator, and digital filter. The modulator bit stream is applied

to a Sinc³filter. Programming the Sinc³decimation factor is

restricted to an 8-bit register SF; the actual decimation factor is

the register value times 8. The decimated output rate from the

Sinc³filter (and the ADC conversion rate) is therefore

3

t_SETTLE

=

= 3×t_ADC

f_ADC

An unsynchronized step change requires four conversions to

accurately reflect the new analog input at its output. Note that

with an unsynchronized change the ADC continues to output

data and so the user must take unsettled outputs into account.

Again, this is one conversion longer than with chop enabled, but

because the ADC throughput with chop disabled is faster than

with chop enabled, the actual time taken to obtain a settled

ADC output is less.

1

f_ADC

=

× f_MOD

8× SF

where:

_ADCis the ADC conversion rate.

f

SF is the decimal equivalent of the word loaded to the filter

register, valid range is from 3 to 255.

f

_MODis the modulator sampling rate of 32.768 kHz.

The allowable range for SF is 3 to 255 with a default of 69 (45H).

The corresponding conversion rates, rms, and peak-to-peak

noise performances are shown in Table 14, Table 15, Table 16,

and Table 17. Note that the conversion time increases by 0.244 ms

for each increment in SF.

F

ADC

IN

MOD

Σ-∆

MOD

ANALOG

INPUT

DIGITAL

OUTPUT

3

MUX

BUF

PGA

SINC FILTER

8 × SF

Figure 15. Block Diagram of ADC Input Channel with Chop Disabled

Rev. A | Page 30 of 108

ADuC845/ADuC847/ADuC848

ADC Noise Performance with Chop Disabled (

= 1)

CHOP

source is quantization noise, which is added when the analog

input is converted to the digital domain. The device noise is at a

low level and is independent of frequency. The quantization

noise starts at an even lower level but rises rapidly with increasing

frequency to become the dominant noise source.

Table 14, Table 15, Table 16, and Table 17 show the output rms

noise and output peak-to-peak resolution in bits (rounded to

the nearest 0.5 LSB) for some typical output update rates. The

numbers are typical and are generated at a differential input

voltage of 0 V and a common-mode voltage of 2.5 V. The output

update rate is selected via the SF7 to SF0 bits in the SF filter

register. Note that the peak-to-peak resolution figures represent

the resolution for which there is no code flicker within a 6-

sigma limit.

The numbers in the tables are given for the bipolar input ranges.

For the unipolar ranges, the rms noise numbers are the same as

the bipolar range, but the peak-to-peak resolution is based on

half the signal range, which effectively means losing 1 bit of

resolution. Typically, the performance of the ADC with chop

disabled shows a 0.5 LSB degradation over the performance

with chop enabled.

The output noise comes from two sources. The first source is

the electrical noise in the semiconductor devices (device noise)

used in the implementation of the modulator. The second

Table 14. ADuC845 and ADuC847 Typical Output RMS Noise (µV) vs. Input Range and Update Rate with Chop Disabled

Input Range

Data Update

SF Word

Rate (Hz)

1365.33

315.08

59.36

±20 mV

30.64

2.07

±40 mV

24.5

1.95

0.79

±80 mV

56.18

2.28

±160 mV

100.47

3.24

±320 mV

248.39

8.22

±640 mV

468.65

13.9

±1.28 V

774.36

20.98

2.3

±2.56 V

1739.5

49.26

3.7

3

13

68

82

255

0.85

1.01

0.99

0.79

1.29

49.95

0.83

0.77

0.85

0.77

0.91

1.12

1.59

3.2

16.06

0.52

0.58

0.59

0.48

0.52

0.57

1.16

1.68

Table 15. ADuC845 and ADuC847 Typical Peak-to-Peak Resolution (Bits) vs. Input Range and Update Rate with Chop Disabled

Input Range

Data Update

SF Word

Rate (Hz)

1365.33

315.08

59.36

±20 mV

7.5

11.5

13

±40 mV

9

12.5

14

±80 mV

9

13.5

14.5

15

±160 mV

9

14

15.5

16

±320 mV

9

13.5

17

16.5

17.5

±640 mV

9

±1.28 V

9

±2.56 V

9

3

13

68

82

255

14

17

17.5

18.5

14

17.5

18

14

18

19

49.95

16.06

13.5

14.5

15.5

16.5

18.5

Table 16. ADuC848 Typical Output RMS Noise (µV) vs. Input Range and Update Rate with Chop Disabled

Input Range

Data Update

SF Word

Rate (Hz)

1365.33

315.08

59.36

±20 mV

30.64

2.07

±40 mV

24.5

1.95

0.79

±80 mV

56.18

2.28

±160 mV

100.47

3.24

±320 mV

248.39

8.22

±640 mV

468.65

13.9

±1.28 V

774.36

20.98

2.3

±2.56 V

1739.5

49.26

3.7

3

13

69

82

255

0.85

1.01

0.99

0.79

1.29

49.95

0.83

0.77

0.85

0.77

0.91

1.12

1.59

3.2

16.06

0.52

0.58

0.59

0.48

0.52

0.57

1.16

1.68

Table 17. ADuC848 Typical Peak-to-Peak Resolution (Bits) vs. Input Range and Update Rate with Chop Disabled

Input Range

160 mV 320mV

Data Update Rate

SF Word (Hz)

20 mV

7.5

40 mV

80 mV

640mV

1.28 V

2.56 V

3

1365.33

315.08

59.36

9

12.5

14

9

13.5

16

9

13

68

82

255

11.5

13

13.5

14.5

15

14

15.5

16

14

16

14

16

14

16

49.95

13

14

16

16.06

13.5

14.5

15.5

16

Rev. A | Page 31 of 108

ADuC845/ADuC847/ADuC848

When an external reference voltage is used, the primary ADC

sees this internally as a 2.56 V reference (V_REF× 1.024).

Therefore, any calculations of LSB size should account for this.

For instance, with a 2.5 V external reference connected and

using a gain of 1 on a unipolar range (2.56 V), the LSB size is

(2.56/2²⁴) = 152.6 nV (if using the 24-bit ADC on the ADuC845

or ADuC847). If a bipolar gain of 4 is used ( 640 mV), the LSB

size is ( 640 mV)/2²⁴) = 76.3 nV (again using the 24-bit ADC

on the ADuC845 or ADuC847).

AUXILIARY ADC (ADUC845 ONLY)

Table 18. ADuC845 Typical Output RMS Noise (µV) vs.

Update Rate with Chop Enabled

SF Word

Data Update Rate (Hz)

µV

13

23

27

69

105.03

59.36

50.56

19.79

5.35

17.46

3.13

4.56

2.66

1.13

255

The ADuC845/ADuC847/ADuC848 can also be configured to

use the on-chip band gap reference via the XREF0/1 bits in the

ADC0CON2 SFR (for primary ADC) or the AXREF bit in

ADC1CON (for auxiliary ADC (ADuC845 only)). In this mode

of operation, the ADC sees the internal reference of 1.25 V,

thereby halving all the input ranges. A consequence of using the

internal band gap reference is a noticeable degradation in peak-

to-peak resolution. For this reason, operation with an external

reference is recommended.

Table 19. ADuC845 Typical Peak-to-Peak Resolution (Bits) vs.

Update Rate¹with Chop Enabled

SF Word

Data Update Rate (Hz)

Bits

15.5

18

13

23

105.03

59.36

50.56

19.79

5.35

27

69

17.5

18

255

19.5

¹ADC converting in bipolar mode.

In applications where the excitation (voltage or current) for the

transducer on the analog input also drives the reference inputs

for the part, the effect of any low frequency noise in the

excitation source is removed because the application is ratio-

metric. If the parts are not used in a ratiometric configuration, a

low noise reference should be used. Recommended reference

voltage sources for the ADuC845/ADuC847/ADuC848 include

ADR421, REF43, and REF192.

Table 20. ADuC845 Typical Output RMS Noise (µV) vs.

Update Rate with Chop Disabled

SF Word

Data Update Rate (Hz)

µV

3

1365.33

315.08

62.06

59.36

50.57

1386.58

34.94

3.2

3.19

3.14

1.71

13

66

69

81

255

The reference inputs provide a high impedance, dynamic load

to external connections. Because the impedance of each reference

input is dynamic, resistor/capacitor combinations on these pins

can cause dc gain errors, depending on the output impedance of

the source that is driving the reference inputs. Reference voltage

sources, such as those mentioned above, for example, the ADR421,

typically have low output impedances, and, therefore, decoupling

capacitors on the REFIN or REFIN2 inputs would be recom-

mended (typically 0.1 µF). Deriving the reference voltage from

an external resistor configuration means that the reference input

sees a significant external source impedance. External decoupling

of the REFIN and/or REFIN2 inputs is not recommended in

this type of configuration.

16.06

Table 21. ADuC845 Peak-to-Peak Resolution (Bits) vs.

Update Rate with Chop Disabled

SF Word

Data Update Rate (Hz)

Bits

3

1365.33

315.08

62.06

59.36

50.57

9

14.5

18

13

66

69

81

255

16.06

19

BURNOUT CURRENT SOURCES

The primary ADC on the ADuC845 and the ADC on the

ADuC847 and ADuC848 incorporate two 200 µA constant

current generators, one sourcing current from the AV_DDto

AIN(+), and one sinking current from AIN(−) to AGND. These

currents are only configurable for use on AIN4 to AIN5 and/or

AIN6 to AIN7 in differential mode only, from the ICON.6 bit in

the ICON SFR (see Table 30). These burnout current sources are

also available only with buffering enabled via the BUF0/BUF1 bits

in the ADC0CON1 SFR. Once the burnout currents are turned

on, a current flows in the external transducer circuit, and a

measurement of the input voltage on the analog input channel

REFERENCE INPUTS

The ADuC845/ADuC847/ADuC848 each have two separate

differential reference inputs, REFIN and REFIN2 . While both

references are available for use with the primary ADC, only

REFIN is available for the auxiliary ADC (ADuC845 only).

The common-mode range for these differential references is

from AGND to AV_DD. The nominal external reference voltage is

2.5 V, with the primary and auxiliary (ADuC845 only)reference

select bits configured from the ADC0CON2 and ADC1CON

(ADuC845 only), respectively.

Rev. A | Page 32 of 108

ADuC845/ADuC847/ADuC848

can be taken. When the resulting voltage measured is full scale,

the transducer has gone open circuit. When the voltage measured

is 0 V, this indicates that the transducer has gone short circuit.

The current sources work over the normal absolute input

voltage range specifications.

ADC clock (modulator rate) of 32.768 kHz. During calibration,

the current (user-written) value of the SF register is used.

Σ-∆ MODULATOR

A Σ-∆ ADC usually consists of two main blocks, an analog

modulator, and a digital filter. For the ADuC845/ADuC847/

ADuC848, the analog modulator consists of a difference

amplifier, an integrator block, a comparator, and a feedback

DAC as shown in Figure 16.

REFERENCE DETECT CIRCUIT

The main and auxiliary (ADuC845 only) ADCs can be

configured to allow the use of the internal band gap reference or

an external reference that is applied to the REFIN pins by

means of the XREF0/1 bit in the Control Registers AD0CON2

and AD1CON (ADuC845 only). A reference detection circuit is

provided to detect whether a valid voltage is applied to the

REFIN pins. This feature arose in connection with strain-gage

sensors in weigh scales where the reference and signal are

provided via a cable from the remote sensor. It is desirable to

detect whether the cable is disconnected. If either of the pins is

floating or if the applied voltage is below a specified threshold, a

flag (NOXREF) is set in the ADC status register (ADCSTAT),

conversion results are clamped, and calibration registers are not

updated if a calibration is in progress.

DIFFERENCE

COMPARATOR

AMP

HIGH

FREQUENCY

BIT STREAM

TO DIGITAL

FILTER

ANALOG

INPUT

INTEGRATOR

DAC

Figure 16. Σ-∆ Modulor Simplified Block Diagram

In operation, the analog signal is fed to the difference amplifier

along with the output from the feedback DAC. The difference

between these two signals is integrated and fed to the comparator.

The output from the comparator provides the input to the feed-

back DAC so the system functions as a negative feedback loop

that tries to minimize the difference signal. The digital data that

represents the analog input voltage is contained in the duty

cycle of the pulse train appearing at the output of the comparator.

This duty cycle data can be recovered as a data-word by using a

subsequent digital filter stage. The sampling frequency of the

modulator loop is many times higher than the bandwidth of the

input signal. The integrator in the modulator shapes the

quantization noise (that results from the analog-to-digital

conversion) so that the noise is pushed toward one-half of the

modulator frequency.

Note that the reference detect does not look at REFIN2 pins.

If, during either an offset or gain calibration, the NOEXREF bit

becomes active, indicating a incorrect V_REF, updating the relevant

calibration register is inhibited to avoid loading incorrect data

into these registers, and the appropriate bits in ADCSTAT (ERR0

or ERR1) are set. If the user needs to verify that a valid

reference is in place every time a calibration is performed, the

status of the ERR0 and ERR1 bits should be checked at the end

of every calibration cycle.

SINC FILTER REGISTER (SF)

DIGITAL FILTER

The number entered into the SF register sets the decimation

factor of the Sinc³filter for the ADC. See Table 28 and Table 29.

The output of the ∑-∆ modulator feeds directly into the digital

filter. The digital filter then band-limits the response to a

frequency significantly lower than one-half of the modulator

frequency. In this manner, the 1-bit output of the comparator is

translated into a band-limited, low noise output from the part.

The range of operation of the SF word depends on whether

ADC chop is on or off. With chop disabled, the minimum SF

word is 3 and the maximum is 255. This gives an ADC through-

put rate from 16.06 Hz to 1.365 kHz. With chop enabled, the

minimum SF word is 13 (all values lower than 13 are clamped

to 13) and the maximum is 255. This gives an ADC throughput

rate of from 5.4 Hz to 105 Hz. See the f_ADCequation in the ADC

description preceding section.

The ADuC845/ADuC847/ADuC848 filter is a low-pass, Sinc³or

[(SINx)/x]³filter whose primary function is to remove the

quantization noise introduced at the modulator. The cutoff

frequency and decimated output data rate of the filter are

programmable via the SF (Sinc filter) SFR as listed in Table 28

and Table 29.

An additional feature of the Sinc³filter is a second notch filter

positioned in the frequency response at 60 Hz. This gives

simultaneous 60 Hz rejection to whatever notch is defined by

the SF filter. This 60 Hz filter is enabled via the REJ60 bit in the

ADCMODE register (ADCMODE.6). The notch is valid only

for SF words ≥ 68; otherwise, ADC errors occur, and, in fact, the

notch is best used with an SF word of 82d giving simultaneous

50 Hz and 60 Hz rejection. This function is useful only with an

Figure 22, Figure 23, Figure 24, and Figure 25 show the frequency

response of the ADC, yielding an overall output rate of 16.6 Hz

with chop enabled and 50 Hz with chop disabled. Also detailed

in these plots is the effect of the fixed 60 Hz drop-in notch filter

(REJ60 bit, ADCMODE.6). This fixed filter can be enabled or

disabled by setting or clearing the REJ60 bit in the ADCMODE

register (ADCMODE.6). This 60 Hz drop-in notch filter can be

Rev. A | Page 33 of 108

ADuC845/ADuC847/ADuC848

enabled for any SF word that yields an ADC throughput that is

less than 20 Hz with chop enabled (SF ≥ 68 decimal).

output for two input conditions: zero-scale and full-scale points.

These points are derived by performing a conversion on the

different input voltages (zero-scale and full-scale) provided to the

input of the modulator during calibration. The result of the

zero-scale calibration conversion is stored in the offset

calibration registers for the appropriate ADC. The result of the

full-scale calibration conversion is stored in the gain calibration

registers for the appropriate ADC. With these readings, the

calibration logic can calculate the offset and the gain slope for

the input-to-output transfer function of the converter.

ADC CHOPPING

The ADCs on the ADuC845/ADuC847/ADuC848 implement a

chopping scheme whereby the ADC repeatedly reverses its inputs.

The decimated digital output words from the Sinc³filter, there-

fore, have a positive and negative offset term included. As a

result, a final summing stage is included in each ADC so that

each output word from the filter is summed and averaged with

the previous filter output to produce a new valid output result

to be written to the ADC data SFRs. The ADC throughput or

update rate is listed in Table 29. The chopping scheme incor-

porated into the parts results in excellent dc offset and offset

drift specifications and is extremely beneficial in applications

where drift, noise rejection, and optimum EMI performance are

important. ADC chop can be disabled via the chop bit in the

ADCMODE SFR (ADCMODE.3). Setting this bit to 1 (logic

high) disables chop mode.

During an internal zero-scale or full-scale calibration, the

respective zero-scale input or full-scale input is automatically

connected to the ADC inputs internally. A system calibration,

however, expects the system zero-scale and system full-scale

voltages to be applied externally to the ADC pins by the user

before the calibration mode is initiated. In this way, external

errors are taken into account and minimized. Note that all

ADuC845/ADuC847/ADuC848 ADC calibrations are carried

out at the user-selected SF word update rate. To optimize

calibration accuracy, it is recommended that the slowest possible

update rate be used.

CALIBRATION

The ADuC845/ADuC847/ADuC848 incorporate four calibration

modes that can be programmed via the mode bits in the

ADCMODE SFR detailed in Table 24. Every part is calibrated

before it leaves the factory. The resulting offset and gain

calibration coefficients for both the primary and auxiliary

(ADuC845 only) ADCs are stored on-chip in manufacturing-

specific Flash/EE memory locations. At power-on or after a

reset, these factory calibration registers are automatically

downloaded to the ADC calibration registers in the part’s SFR

space. To facilitate user calibration, each of the primary and

auxiliary (ADuC845 only) ADCs have dedicated calibration

control SFRs, which are described in the ADC SFR Interface

section. Once a user initiates a calibration procedure the factory

calibration values that were initially downloaded during the

power-on sequence to the ADC calibration SFRs are overwritten.

The ADC to be calibrated must be enabled via the ADC enable

bits in the ADCMODE register.

Internally in the parts, the coefficients are normalized before

being used to scale the words coming out of the digital filter.

The offset calibration coefficient is subtracted from the result

prior to the multiplication by the gain coefficient.

From an operational point of view, a calibration should be

treated just like an ordinary ADC conversion. A zero-scale

calibration (if required) should always be carried out before a

full-scale calibration. System software should monitor the

relevant ADC RDY0/1 bit in the ADCSTAT SFR to determine

the end of calibration by using a polling sequence or an interrupt

driven routine. If required, the NOEXREF0/1 bits can be moni-

tored to detect unconnected or low voltage errors in the reference

during conversion. In the event of the reference becoming

disconnected, causing a NOXREF flag during a calibration, the

calibration is immediately halted and no write to the calibration

SFRs takes place.

Even though an internal offset calibration mode is described in

this section, note that the ADCs can be chopped. This chopping

scheme inherently minimizes offset errors and means that an

offset calibration should never be required. Also, because

factory 5 V/25°C gain calibration coefficients are automatically

present at power-on, an internal full-scale calibration is required

only if the part is operated at 3 V or at temperatures significantly

different from 25°C.

Internal Calibration Example

With chop enabled, a zero-scale or offset calibration should

never be required, although a full-scale or offset calibration may

be required. However, if a full internal calibration is required,

the procedure should be to select a PGA gain of 1 ( 2.56 V) and

perform a zero-scale calibration (MD2...0 = 100B in the

ADCMODE register). Next, select and perform full-scale

calibration by setting MD2...0 = 101B in the ADCMODE SFR.

Now select the desired PGA range and perform a zero-scale

calibration again (MD2..0 = 100B in ADCMODE) at the new

PGA range. The reason for the double zero-scale calibration is

that the internal calibration procedure for full-scale calibration

automatically selects the reference in voltage at PGA = 1.

Therefore, the full-scale endpoint calibration automatically

If the part is operated in chop disabled mode, a calibration may

need to be done with every gain range change that occurs via

the PGA.

The ADuC845/ADuC847/ADuC848 each offer internal or

system calibration facilities. For full calibration to occur on the

selected ADC, the calibration logic must record the modulator

Rev. A | Page 34 of 108

ADuC845/ADuC847/ADuC848

subtracts the offset calibration error, it is advisable to perform

an offset calibration at the same gain range as that used for full-

scale calibration. There is no penalty to the full-scale calibration

in redoing the zero-scale calibration at the required PGA range

because the full-scale calibration has very good matching at all

the PGA ranges.

mixed-signal solutions available on the market. The auxiliary

(ADuC845 only) ADC does not incorporate a PGA, and the

gain is fixed at 0 V to 2.50 V in unipolar mode, and 2.50 V in

bipolar mode.

BIPOLAR/UNIPOLAR CONFIGURATION

The analog inputs of the ADuC845/ADuC847/ADuC848 can

accept either unipolar or bipolar input voltage ranges. Bipolar

input ranges do not imply that the part can handle negative

voltages with respect to system AGND, but rather with respect

to the negative reference input. Unipolar and bipolar signals on

the AIN(+) input on the ADC are referenced to the voltage on

the respective AIN(−) input. AIN(+) and AIN(−) refer to the

signals seen by the ADC.

This procedure also applies when chop is disabled.

Note that for internal calibration to be effective, the AIN− pin

should be held at a steady voltage, within the allowable common-

mode range to keep it from floating during calibration.

System Calibration Example

With chop enabled, a system zero-scale or offset calibration

should never be required. However, if a full-scale or gain

calibration is required for any reason, use the following typical

procedure for doing so.

For example, if AIN(−) is biased to 2.5 V (tied to the external

reference voltage) and the ADC is configured for a unipolar

analog input range of 0 mV to > 20 mV, the input voltage range

on AIN(+) is 2.5 V to 2.52 V. On the other hand, if AIN(−) is

biased to 2.5 V (again the external reference voltage) and the

ADC is configured for a bipolar analog input range of 1.28 V,

the analog input range on the AIN(+) is 1.22 V to 3.78 V, that is,

2.5 V 1.28 V.

1. Apply a differential voltage of 0 V to the selected analog

inputs (AIN+ to AIN−) that are held at a common-mode

voltage.

Perform a system zero-scale or offset calibration by setting

the MD2...0 bits in the ADCMODE register to 110B.

The modes of operation for the ADC are fully differential mode

or pseudo differential mode. In fully differential mode, AIN1 to

AIN2 are one differential pair, AIN3 to AIN4 are another pair

(AIN5 to AIN6, AIN7 to AIN8, and AIN9 to AIN10 are the

others). In differential mode, all AIN(−) pin names imply the

negative analog input of the selected differential pair, that is,

AIN2, AIN4, AIN6, AIN8, AIN10. The term AIN(+) implies the

positive input of the selected differential pair, that is, AIN1,

AIN3, AIN5, AIN7, AIN9. In pseudo differential mode, each

analog input is paired with the AINCOM pin, which can be

biased up or tied to AGND. In this mode, the AIN(−) implies

AINCOM and AIN(+) implies any one of the ten analog input

channels.

2. Apply a full-scale differential voltage across the ADC

inputs again at the same common-mode voltage.

Perform a system full-scale or gain calibration by setting

the MD2...0 bits in the ADCMODE register to 111B.

Perform a system calibration at the required PGA range to be

used since the ADC scales to the differential voltages that are

applied to the ADC during the calibration routines.

In bipolar mode, the zero-scale calibration determines the mid-

scale point of the ADC (800000H) or 0 V.

PROGRAMMABLE GAIN AMPLIFIER

The primary ADC incorporates an on-chip programmable gain

amplifier (PGA). The PGA can be programmed through eight

different ranges, which are programmed via the range bits (RN0

to RN2) in the ADC0CON1 register. With an external 2.5 V

reference applied, the unipolar ranges are 0 mV to 20 mV, 0 mV

to 40 mV, 0 mV to 80 mV, 0 mV to 160 mV, 0 mV to 320 mV,

0 mV to 640 mV, 0 V to 1.28 V and 0 V to 2.56 V, while in

bipolar mode the ranges are 20 mV, 40 mV, 80 mV, 160 mV,

320 mV, 64 0 mV, 1.28 V, and 2.56 V. These ranges should

appear on the input to the on-chip PGA. The ADC range-

matching specification of 2 µV (typical with chop enabled)

means that calibration need only be carried out on a single

range and need not be repeated when the ADC range is

changed. This is a significant advantage compared to similar

The configuration of the inputs (unipolar versus bipolar) is

shown in Figure 17.

AIN1

AIN2

AIN3

AIN4

AIN5

AIN6

AIN7

AIN8

AIN9

AIN1

AIN2

AIN3

AIN4

AIN5

AIN6

AIN7

AIN8

AIN9

FULLY DIFFERENTIAL

AIN10

AINCOM

Figure 17. Unipolar and Bipolar Channel Pairs

Rev. A | Page 35 of 108

ADuC845/ADuC847/ADuC848

DATA OUTPUT CODING

EXCITATION CURRENTS

When the primary ADC is configured for unipolar operation,

the output coding is natural (straight) binary with a zero differ-

ential input voltage resulting in a code of 000...000, a midscale

voltage resulting in a code of 100...000, and a full-scale voltage

resulting in a code of 111...111. The output code for any analog

input voltage on the main ADC can be represented as follows:

The ADuC845/ADuC847/ADuC848 contain two matched,

software-configurable 200 µA current sources. Both source

current from AV_DD, which is directed to either or both of the

IEXC1 (Pin 11 whose alternate functions are P1.6/AIN6) or

IEXC2 (Pin 12, whose alternate functions are P1.7/AIN7) pins

on the device. These currents are controlled via the lower four

bits in the ICON register (Table 30). These bits not only enable

the current sources but also allow the configuration of the

currents such that 200 µA can be sourced individually from

both pins or can be combined to give a 400 µA source from one

or the other of the outputs. These sources can be used to excite

external resistive bridge or RTD sensors (see Figure 70).

Code – (AIN × GAIN × 2^N) / (1.024 × V_REF

where:

AIN is the analog input voltage.

)

GAIN is the PGA gain setting, that is, 1 on the 2.56 V range and

128 on the 20 mV range, and N = 24 (16 on the ADuC848).

ADC POWER-ON

The output code for any analog input voltage on the auxiliary

ADC can be represented as follows:

The ADC typically takes 0.5 ms to power up from an initial

start-up sequence or following a power-down event.

Code = (AIN × 2^N) / (V_REF

)

with the same definitions as used for the primary ADC above.

When the primary ADC is configured for bipolar operation, the

coding is offset binary with negative full-scale voltage resulting

in a code of 000...000, a zero differential voltage resulting in a

code of 800…000, and a positive full-scale voltage resulting in a

code of 111...111. The output from the primary ADC for any

analog input voltage can be represented as follows:

Code = 2^N−1[(AIN × GAIN) / (1.024 ×V_REF) + 1]

where:

AIN is the analog input voltage.

GAIN is the PGA gain, that is, 1 on the 2.56 V range and

128 on the 20 mV range.

N = 24 (16 on the ADuC848).

The output from the auxiliary ADC in bipolar mode can be

represented as follows:

Code = 2^N−1[(AIN / V_REF) + 1]

Rev. A | Page 36 of 108

ADuC845/ADuC847/ADuC848

TYPICAL PERFORMANCE CHARACTERISTICS

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

–110

–120

0

10

20

30 40

50

60

70

80

90 100 110

10 30 50 70 90 110 130 150 170 190 210 230 250

SF (Decimal)

FREQUENCY (Hz)

Figure 18. Filter Response, Chop On, SF = 69 Decimal

Figure 21. 60 Hz Normal Mode Rejection vs. SF, Chop On

10

–10

–30

–10

–30

–50

–70

–50

–70

–90

–110

–130

–150

–130

–150

0

10

20

30 40

50

60

70

80

90 100

FREQUENCY (Hz)

Figure 19. Filter Response, Chop On, SF = 255 Decimal

Figure 22. Chop Off, Fadc = 50 Hz, SF = 52H

0

10

–10

–30

–50

–70

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–190

–110

–130

–150

–110

–120

10 30 50 70 90 110 130 150 170 190 210 230 250

SF (Decimal)

FREQUENCY (Hz)

Figure 20. 50 Hz Normal Mode Rejection vs. SF Word, Chop On

Figure 23. Chop Off, SF = 52H, REJ60 Enabled

Rev. A | Page 37 of 108

ADuC845/ADuC847/ADuC848

0

–20

–40

–60

–80

–40

–60

–80

–100

–120

–100

–120

FREQUENCY (Hz)

Figure 24. Chop On, Fadc = 16.6 Hz, SF = 52H

Figure 25. Chop On, Fadc = 16.6 Hz, SF = 52H, REJ60 Enabled

Rev. A | Page 38 of 108

ADuC845/ADuC847/ADuC848

FUNCTIONAL DESCRIPTION

ADC SFR INTERFACE

The ADCs are controlled and configured via a number of SFRs that are mentioned here and described in more detail in the following

sections.

Table 22. ADC SFR Interface

Name

Description

ADCSTAT

ADCMODE

ADC Status Register. Holds the general status of the primary and auxiliary (ADuC845 only) ADCs.

ADC Mode Register. Controls the general modes of operation for primary and auxiliary (ADuC845 only) ADCs.

ADC0CON1 Primary ADC Control Register 1. Controls the specific configuration of the primary ADC.

ADC0CON2 Primary ADC Control Register 2. Controls the specific configuration of the primary ADC.

ADC1CON

SF

Auxiliary ADC Control Register. Controls the specific configuration of the auxiliary ADC. ADuC845 only.

Sinc Filter Register. Configures the decimation factor for the Sinc³filter and, therefore, the primary and auxiliary (ADuC845

only) ADC update rates.

ICON

Current Source Control Register. Allows user control of the various on-chip current source options.

ADC0L/M/H Primary ADC 24-bit (16-bit on the ADuC848) conversion result is held in these three 8-bit registers. ADC0L is not available on

the ADuC848.

ADC1L/M/H Auxiliary ADC 24-bit conversion result is held in these two 8-bit registers. ADuC845 only.

OF0L/M/H

OF1L/H

Primary ADC 24-bit offset calibration coefficient is held in these three 8-bit registers. OF0L is not available on the ADuC848.

Auxiliary ADC 16-bit offset calibration coefficient is held in these two 8-bit registers. ADuC845 only.

GN0L/M/H

GN1L/H

Primary ADC 24-bit gain calibration coefficient is held in these three 8-bit registers. GN0L is not available on the ADuC848.

Auxiliary ADC 16-bit gain calibration coefficient is held in these two 8-bit registers. ADuC845 only.

Rev. A | Page 39 of 108

ADuC845/ADuC847/ADuC848

ADCSTAT (ADC STATUS REGISTER)

This SFR reflects the status of both ADCs including data ready, calibration, and various (ADC-related) error and warning conditions

including REFIN reference detect and conversion overflow/underflow flags.

SFR Address:

Power-On Default:

Bit Addressable:

D8H

00H

Yes

Table 23. ADCSTAT SFR Bit Designation

Bit No.

Name

Description

7

RDY0

Ready Bit for the Primary ADC.

Set by hardware on completion of conversion or calibration.

Cleared directly by the user or indirectly by a write to the mode bits to start calibration. The primary ADC is

inhibited from writing further results to its data or calibration registers until the RDY0 bit is cleared.

6

5

RDY1

CAL

Ready Bit for Auxiliary (ADuC845 only) ADC.

Same definition as RDY0 referred to the auxiliary ADC. Valid on the ADuC845 only.

Calibration Status Bit.

Set by hardware on completion of calibration.

Cleared indirectly by a write to the mode bits to start another ADC conversion or calibration.

Note that calibration with the temperature sensor selected (auxiliary ADC on the ADuC845 only) fails to complete.

No External Reference Bit (only active if primary or auxiliary (ADuC845 only) ADC is active).

Set to indicate that one or both of the REFIN pins is floating or the applied voltage is below a specified threshold.

When set, conversion results are clamped to all 1s. Only detects invalid REFIN , does not check REFIN2 .

4

3

NOXREF

ERR0

Cleared to indicate valid V_REF

Primary ADC Error Bit.

.

Set by hardware to indicate that the result written to the primary ADC data registers has been clamped to all 0s or

all 1s. After a calibration, this bit also flags error conditions that caused the calibration registers not to be written.

Cleared by a write to the mode bits to initiate a conversion or calibration.

Auxiliary ADC Error Bit. Same definition as ERR0 referred to the auxiliary ADC. Valid on the ADuC845 only.

Not Implemented. Write Don’t Care.

2

1

0

ERR1

–––

Not Implemented. Write Don’t Care.

Rev. A | Page 40 of 108

ADuC845/ADuC847/ADuC848

ADCMODE (ADC MODE REGISTER)

Used to control the operational mode of both ADCs.

SFR Address:

Power-On Default:

Bit Addressable:

D1H

08H

No

Table 24. ADCMODE SFR Bit Designations

Bit No.

Name

Description

7

6

–––

REJ60

Not Implemented. Write Don’t Care.

Automatic 60 Hz Notch Select Bit.

Setting this bit places a notch in the frequency response at 60 Hz, allowing simultaneous 50 Hz and 60 Hz

rejection at an SF word of 82 decimal. This 60 Hz notch can be set only if SF ≥ 68 decimal, that is, the regular

filter notch must be ≤ 60 Hz. This second notch is placed at 60 Hz only if the device clock is at 32.768 kHz.

5

4

ADC0EN

Primary ADC Enable.

Set by the user to enable the primary ADC and place it in the mode selected in MD2–MD0 below.

Cleared by the user to place the primary ADC into power-down mode.

Auxiliary (ADuC845 only) ADC Enable.

ADC1EN

(ADuC845 only)

Set by the user to enable the auxiliary (ADuC845 only) ADC and place it in the mode selected in MD2–MD0

below.

Cleared by the user to place the auxiliary (ADuC845 only) ADC in power-down mode.

Chop Mode Disable.

3

CHOP

Set by the user to disable chop mode on both the primary and auxiliary (ADuC845 only) ADC allowing a

three times higher ADC data throughput. SF values as low as 3 are allowed with this bit set, giving up to

1.3 kHz ADC update rates.

Cleared by the user to enable chop mode on both the primary and auxiliary (ADuC845 only) ADC.

Primary and Auxiliary (ADuC845 only) ADC Mode Bits.

2, 1, 0

MD2, MD1, MD0

These bits select the operational mode of the enabled ADC as follows:

MD2 MD1 MD0

0

1

ADC Power-Down Mode (Power-On Default).

Idle Mode. In idle mode, the ADC filter and modulator are held in a reset state

although the modulator clocks are still provided.

0

1

0

Single Conversion Mode. In single conversion mode, a single conversion is performed

on the enabled ADC. Upon completion of a conversion, the ADC data registers

(ADC0H/M/L and/or ADC1H/M/L (ADuC845 only)) are updated. The relevant flags in

the ADCSTAT SFR are written, and power-down is re-entered with the MD2−MD0

accordingly being written to 000.

Note that ADC0L is not available on the ADuC848.

0

1

Continuous Conversion. In continuous conversion mode, the ADC data registers are

regularly updated at the selected update rate (see the Sinc Filter SFR Bit Designations

in Table 28).

1

0

1

Internal Zero-Scale Calibration. Internal short automatically connected to the

enabled ADC input(s).

Internal Full-Scale Calibration. Internal or external REFIN or REFIN2 V_REF(as

determined by XREF bits in ADC0CON2 and/or AXREF (ADuC845 only) in ADC1CON

(ADuC845 only) is automatically connected to the enabled ADC input(s) for this

calibration.

1

0

1

System Zero-Scale Calibration. User should connect system zero-scale input to the

enabled ADC input(s) as selected by CH3–CH0 and ACH3–ACH0 bits in the

ADC0CON2 and ADC1CON (ADuC845 only) registers.

System Full-Scale Calibration. User should connect system full-scale input to the

enabled ADC input(s) as selected by CH3–CH0 and ACH3–ACH0 bits in the

ADC0CON2 and ADC1CON (ADuC845 only) registers.

Rev. A | Page 41 of 108

ADuC845/ADuC847/ADuC848

Notes on the ADCMODE Register

•

Any change to the MD bits immediately resets both ADCs

(auxiliary ADC only applicable to the ADuC845). A write

to the MD2–MD0 bits with no change in contents is also

treated as a reset. (See the exception to this in the third

note of this section.)

•

If the parts are powered down via the PD bit in the PCON

register, the current ADCMODE bits are preserved, that is,

they are not reset to default state. Upon a subsequent

resumption of normal operating mode, the ADCs restarts

the selected operation defined by the ADCMODE register.

•

If ADC0CON is written when ADC0EN = 1, or if

ADC0EN is changed from 0 to 1, both ADCs are also

immediately reset. In other words, the primary ADC is

given priority over the auxiliary ADC and any change

requested on the primary ADC is immediately responded

to. Only applicable to the ADuC845.

Once ADCMODE has been written with a calibration

mode, the RDY0/1 (ADuC845 only) bits (ADCSTAT) are

reset and the calibration commences. On completion, the

appropriate calibration registers are written, the relevant

bits in ADCSTAT are written, and the MD2–MD0 bits are

reset to 000b to indicate that the ADC is back in power-

down mode.

•

On the other hand, if ADC1CON is written to or if

ADC1EN is changed from 0 to 1, only the auxiliary ADC is

reset. For example, if the primary ADC is continuously

converting when the auxiliary ADC change or enable

occurs, the primary ADC continues undisturbed. Rather

than allow the auxiliary ADC to operate with a phase

difference from the primary ADC, the auxiliary ADC falls

into step with the outputs of the primary ADC. The result

is that the first conversion time for the auxiliary ADC is

delayed by up to three outputs while the auxiliary ADC

update rate is synchronized to the primary ADC. Only

applicable to ADuC845. If the ADC1CON write occurs

after the primary ADC has completed its operation, the

auxiliary ADC can respond immediately without having to

fall into step with the primary ADCs output cycle.

•

Any calibration request of the auxiliary ADC while the

temperature sensor is selected fails to complete. Although

the RDY1 bit is set at the end of the calibration cycle, no

update of the calibration SFRs takes place, and the ERR1

bit is set. ADuC845 only.

•

Calibrations performed at maximum SF (see Table 28)

value (slowest ADC throughput rate) help to ensure

optimum calibration.

The duration of a calibration cycle is 2/Fadc for chop-on

mode and 4/Fadc for chop-off mode.

Rev. A | Page 42 of 108

ADuC845/ADuC847/ADuC848

ADC0CON1 (PRIMARY ADC CONTROL REGISTER)

ADC0CON1 is used to configure the primary ADC for buffer, unipolar, or bipolar coding, and ADC range configuration.

SFR Address:

Power-On Default:

Bit Addressable:

D2H

07H

No

Table 25. ADC0CON1 SFR Bit Designations

Bit No.

Name

Description

7, 6

BUF1, BUF0

Buffer Configuration Bits.

BUF1 BUF0

Buffer Configuration

ADC0+ and ADC0− are buffered

Reserved

Buffer Bypass

Reserved

0

1

0

1

0

1

5

UNI

Primary ADC Unipolar Bit.

Set by the user to enable unipolar coding; zero differential input results in 000000H output.

Cleared by the user to enable bipolar coding; zero differential input results in 800000H output.

Not Implemented. Write Don’t Care.

4

–––

3

–––

Not Implemented. Write Don’t Care.

2, 1, 0

RN2, RN1, RN0

Primary ADC Range Bits. Written by the user to select the primary ADC input range as follows:

RN2

0

1

RN1

0

1

0

1

RN0

0

1

0

1

0

1

0

Selected primary ADC input range (V_REF= 2.5 V)

20 mV (0 mV–20 mV in unipolar mode)

40 mV (0 mV–40 mV in unipolar mode)

80 mV (0 mV–80 mV in unipolar mode)

160 mV (0 mV–160 mV in unipolar mode)

320 mV (0 mV–320 mV in unipolar mode)

640 mV (0 mV–640 mV in unipolar mode)

1.28 V (0 V–1.28 V in unipolar mode)

1

2.56 V (0 V–2.56 V in unipolar mode)

Rev. A | Page 43 of 108

ADuC845/ADuC847/ADuC848

ADC0CON2 (PRIMARY ADC CHANNEL SELECT REGISTER)

ADC0CON2 is used to select a reference source and channel for the primary ADC.

SFR Address:

Power-On Default:

Bit Addressable:

E6H

00H

No

Table 26. ADC0CON2 SFR Bit Designations

Bit No.

Name

Description

7, 6

XREF1, XREF0

Primary ADC External Reference Select Bit.

Set by the user to enable the primary ADC to use the external reference via REFIN or REFIN2 .

Cleared by the user to enable the primary ADC to use the internal band gap reference (V_REF= 1.25 V).

XREF1 XREF0

0

1

0

1

0

1

Internal 1.25 V Reference.

REFIN Selected.

REFIN2 (AIN3/AIN4) Selected.

Reserved.

5

4

–––

Not Implemented. Write Don’t Care.

3, 2, 1, 0 CH3, CH2, CH1, CH0

Primary ADC Channel Select Bits. Written by the user to select the primary ADC channel as follows:

CH3 CH2

CH1

0

1

0

1

0

1

0

1

CH0 Selected Primary ADC Input Channel.

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

AIN1–AINCOM

AIN2–AINCOM

AIN3–AINCOM

AIN4–AINCOM

AIN5–AINCOM

AIN6–AINCOM

AIN7–AINCOM

AIN8–AINCOM

AIN9–AINCOM (CSP package only; not a valid selection on the MQFP package)

AIN10–AINCOM (CSP package only; not a valid selection on the MQFP package)

AIN1–AIN2

AIN3–AIN4

AIN5–AIN6

AIN7–AIN8

AIN9–AIN10 (CSP package only; not a valid selection on the MQFP package)

AINCOM–AINCOM

Note that because the reference-detect does not operate on the REFIN2 pair, the REFIN2 pins can go below 1 V.

Rev. A | Page 44 of 108

ADuC845/ADuC847/ADuC848

ADC1CON (AUXILIARY ADC CONTROL REGISTER) (ADuC845 ONLY)

ADC1CON is used to configure the auxiliary ADC for reference, channel selection, and unipolar or bipolar coding. The auxiliary ADC is

available only on the ADuC845.

SFR Address:

Power-On Default:

Bit Addressable:

D3H

00H

No

Table 27. ADC1CON SFR Bit Designations

Bit No.

Name

Description

7

6

–––

AXREF

Not Implemented. Write Don’t Care.

Auxiliary (ADuC845 only) ADC External Reference Bit.

Set by the user to enable the auxiliary ADC to use the external reference via REFIN .

Cleared by the user to enable the auxiliary ADC to use the internal band gap reference.

Auxiliary ADC cannot use the REFIN2 reference inputs.

5

AUNI

Auxiliary (ADuC845 only) ADC Unipolar Bit.

Set by the user to enable unipolar coding, that is, zero input results in 000000H output.

Cleared by the user to enable bipolar coding, zero input results in 800000H output.

Not Implemented. Write Don’t Care.

4

–––

3, 2, 1, 0

ACH3, ACH2, ACH1, ACH0

Auxiliary ADC Channel Select Bits. Written by the user to select the auxiliary ADC channel.

ACH3 ACH2 ACH1 ACH0 Selected Auxiliary ADC Input Range (V_REF= 2.5 V).

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

AIN1–AINCOM

AIN2–AINCOM

AIN3–AINCOM

AIN4–AINCOM

AIN5–AINCOM

AIN6–AINCOM

AIN7–AINCOM

AIN8–AINCOM

AIN9–AINCOM (not a valid selection on the MQFP package)

AIN10–AINCOM (not a valid selection on the MQFP package)

AIN1–AIN2

AIN3–AIN4

AIN5–AIN6

AIN7–AIN8

Temperature Sensor¹

AINCOM–AINCOM

¹Note the following about the temperature sensor:

– When the temperature sensor is selected, user code must select the internal reference via the AXREF bit and clear the AUNI bit (ADC1CON.5) to select bipolar coding.

– Chop mode must be enabled for correct temperature sensor operation.

– The temperature sensor is factory calibrated to yield conversion results 800000H at 0°C (ADC chop on).

– A +1°C change in temperature results in a +1 LSB change in the ADC1H register ADC conversion result.

– The temperature sensor is not available on the ADuC847 or ADuC848.

Rev. A | Page 45 of 108

ADuC845/ADuC847/ADuC848

SF (ADC SINC FILTER CONTROL REGISTER)

The SF register is used to configure the decimation factor for the ADC, and therefore, has a direct influence on the ADC throughput rate.

SFR Address:

Power-On Default:

Bit Addressable:

D4H

45H

No

Table 28. Sinc Filter SFR Bit Designations

SF.7

SF.6

SF.5

SF.4

SF.3

SF.2

SF.1

SF.0

0

1

0

1

0

1

The bits in this register set the decimation factor of the ADC. This has a direct bearing on the throughput rate of the ADC along with the

chop setting. The equations used to determine the ADC throughput rate are

1

Fadc (Chop On) =

× 32.768 kHz

3×8× SFword

where SFword is in decimal.

1

Fadc (Chop Off) =

8× SFword

× 32.768 kHz

where SFword is in decimal.

Table 29. SF SFR Bit Examples

Chop Enabled (ADCMODE.3 = 0)

SF (Decimal) SF (Hexadecimal) Fadc (Hz) Tadc (ms) Tsettle (ms)

13¹

69

82

255

0D

45

52

FF

105.3

19.79

16.65

5.35

9.52

19.04

101.1

120.1

373.54

50.53

60.06

186.77

Chop Disabled (ADCMODE.3 = 1)

SF (Decimal) SF (Hexadecimal) Fadc (Hz) Tadc (ms) Tsettle (ms)

3

03

45

52

FF

1365.3

59.36

49.95

16.06

0.73

2.2

69

82

255

16.84

20.02

62.25

50.52

60.06

186.8

¹With chop enabled, if an SF word smaller than 13 is written to this SF register, the filter automatically defaults to 13.

During ADC calibration, the user-programmed value of SF word is used. The SF word does not default to the maximum setting (255) as it

did on previous MicroConverter® products. However, for optimum calibration results, it is recommended that the maximum SF word be set.

Rev. A | Page 46 of 108

ADuC845/ADuC847/ADuC848

ICON (EXCITATION CURRENT SOURCES CONTROL REGISTER)

The ICON register is used to configure the current sources and the burnout detection source.

SFR Address:

Power-On Default:

Bit Addressable:

D5H

00H

No

Table 30. Excitation Current Source SFR Bit Designations

Bit No.

Name

Description

7

6

–––

ICON.6

Not Implemented. Write Don’t Care.

Burnout Current Enable Bit.

When set, this bit enables the sensor burnout current sources on primary ADC channels AIN4/AIN5 or

AIN6/AIN7. Not available on any other ADC input pins or on the auxiliary ADC (ADuC845 only).

5

4

3

2

1

0

ICON.5

ICON.4

ICON.3

ICON.2

ICON.1

ICON.0

Not Implemented. Write Don’t Care.

IEXC2 Pin Select (0 = AIN 8/AIN1 = AIN7).

IEXC1 Pin Select (0 = AIN7/AIN1 = AIN 8).

IEXC2 Enable Bit (0 = disable).

IEXC1 Enable Bit (0 = disable).

Note that a write to the ICON register has an immediate effect but does not reset the ADCs. Therefore, if a current source is changed while

an ADC is already converting, the user must wait until the third or fourth output at least (depending on the status of the chop mode) to

see a fully settled new output.

Rev. A | Page 47 of 108

ADuC845/ADuC847/ADuC848

The following sections use the 62-kbyte program space as an

example when referring to program and ULOAD mode. For the

other memory models (32-kbyte and 8-kbyte), the ULOAD

space moves to the top 6 kbytes of the on-chip program memory,

that is, for the 32-kbyte memory model, the ULOAD space is

from 26 kbytes to 32 kbytes. The kernel still resides in the

protected area from 60 kbytes to 62 kbytes. The ULOAD space

resides from 2 kbytes to 8 kbytes on the 8-byte part.

NONVOLATILE FLASH/EE MEMORY OVERVIEW

The ADuC845/ADuC847/ADuC848 incorporate Flash/EE

memory technology on-chip to provide the user with nonvolatile,

in-circuit reprogrammable code and data memory space.

Like EEPROM, flash memory can be programmed in-system at

the byte level, although it must first be erased, in page blocks.

Thus, flash memory is often and more correctly referred to as

Flash/EE memory.

Flash/EE Memory Reliability

The Flash/EE program and data memory arrays on the

ADuC845/ADuC847/ADuC848 are fully qualified for two key

Flash/EE memory characteristics: Flash/EE memory cycling

endurance and Flash/EE memory data retention.

EPROM

TECHNOLOGY

EEPROM

TECHNOLOGY

SPACE EFFICIENT/

DENSITY

IN-CIRCUIT

REPROGRAMMABLE

FLASH/EE MEMORY

TECHNOLOGY

Endurance quantifies the ability of the Flash/EE memory to be

cycled through many program, read, and erase cycles. In real

terms, a single endurance cycle is composed of four

independent, sequential events:

Figure 26. Flash/EE Memory Development

Overall, Flash/EE memory represents a step closer to the ideal

memory device that includes nonvolatility, in-circuit program-

mability, high density, and low cost. The Flash/EE memory

technology incorporated allows the user to update program

code space in-circuit, without needing to replace onetime

programmable (OTP) devices at remote operating nodes.

1. Initial page erase sequence

2. Read/verify sequence

3. Byte program sequence

4. Second read/verify sequence

Flash/EE Memory on the ADuC845, ADuC847, ADuC848

The ADuC845/ADuC847/ADuC848 provide two arrays of

Flash/EE memory for user applications—up to 62 kbytes of

Flash/EE program space and 4 kbytes of Flash/EE data memory

space. Also, 8-kbyte and 32-kbyte program memory options are

available. All examples and references in this datasheet use the

62-kbyte option; however, similar protocols and procedures are

applicable to the 32-kbyte and 8-kbyte options, provided that

the difference in memory size is taken into account.

In reliability qualification, every byte in both the program and

data Flash/EE memory is cycled from 00H to FFH until a first

fail is recorded, signifying the endurance limit of the on-chip

Flash/EE memory.

As indicated in the specification table, the ADuC845/ADuC847/

ADuC848 Flash/EE memory endurance qualification has been

carried out in accordance with JEDEC Specification A117 over

the industrial temperature range of –40°C, +25°C, +85°C, and

+125°C. (The CSP package is qualified to +85°C only.) The

results allow the specification of a minimum endurance figure

over supply and temperature of 100,000 cycles, with an endurance

figure of 700,000 cycles being typical of operation at 25°C.

The 62 kbytes Flash/EE code space are provided on-chip to

facilitate code execution without any external discrete ROM

device requirements. The program memory can be programmed

in-circuit, using the serial download mode provided, using

conventional third party memory programmers, or via any

user-defined protocol in user download (ULOAD) mode.

Retention is the ability of the Flash/EE memory to retain its

programmed data over time.Again, the parts have been qualified

in accordance with the formal JEDEC Retention Lifetime

Specification (A117) at a specific junction temperature (T_J=

55°C). As part of this qualification procedure, the Flash/EE

memory is cycled to its specified endurance limit described

previously, before data retention is characterized. This means

that the Flash/EE memory is guaranteed to retain its data for its

full specified retention lifetime every time the Flash/EE memory

is reprogrammed. It should also be noted that retention lifetime,

based on an activation energy of 0.6 eV, derates with T_Jas shown

in Figure 27.

The 4-kbyte Flash/EE data memory space can be used as a

general-purpose, nonvolatile scratchpad area. User access to this

area is via a group of seven SFRs. This space can be programmed

at a byte level, although it must first be erased in 4-byte pages.

Rev. A | Page 48 of 108

ADuC845/ADuC847/ADuC848

300

Serial Downloading (In-Circuit Programming)

The ADuC845/ADuC847/ADuC848 facilitates code download

via the standard UART serial port. The parts enter serial down-

250

200

150

100

50

load mode after a reset or a power cycle if the

pin is pulled

PSEN

ADI SPECIFICATION

100 YEARS MIN.

low through an external 1 kΩ resistor. Once in serial download

mode, the hidden embedded download kernel executes. This

allows the user to download code to the full 62 kbytes of Flash/EE

program memory while the device is in circuit in its target

application hardware.

AT T = 55°C

J

A PC serial download executable (WSD.EXE) is provided as

part of the ADuC845/ADuC847/ADuC848 Quick Start

development system. Application Note uC004 fully describes

the serial download protocol that is used by the embedded

download kernel. This application note is available at

www.analog.com/microconverter.

0

40

50

60

70

80

90

100

110

T

JUNCTION TEMPERATURE (°C)

J

Figure 27. Flash/EE Memory Data Retention

FLASH/EE PROGRAM MEMORY

Parallel Programming

The ADuC845/ADuC847/ADuC848 contain a 64-kbyte array of

Flash/EE program memory. The lower 62 kbytes of this program

memory are available to the user for program storage or as

additional NV data memory.

The parallel programming mode is fully compatible with

conventional third-party flash or EEPROM device programmers.

A block diagram of the external pin configuration required to

support parallel programming is shown in Figure 29. In this

mode, Ports 0 and 2 operate as the external address bus interface,

P3 operates as the external data bus interface, and P1.0 operates

as the write enable strobe. P1.1, P1.2, P1.3, and P1.4 are used as

general configuration ports that configures the device for

various program and erase operations during parallel

programming.

The upper 2 kbytes of this Flash/EE program memory array

contain permanently embedded firmware, allowing in-circuit

serial download, serial debug, and nonintrusive single-pin

emulation. These 2 kbytes of embedded firmware also contain a

power-on configuration routine that downloads factory

calibrated coefficients to the various calibrated peripherals such

as ADC, temperature sensor, current sources, band gap, and

references.

+5V

ADuC845/

ADuC847/

ADuC848

These 2 kbytes of embedded firmware are hidden from the user

code. Attempts to read this space read 0s; therefore, the embedded

firmware appears as NOP instructions to user code.

P1.4–P1.1

COMMAND

P3.7–P3.0

DATA

In normal operating mode (power-on default), the 62 kbytes of

user Flash/EE program memory appear as a single block. This

block is used to store the user code as shown in Figure 28.

P1.7–P1.5

P1.0

TIMING

GND

EA

ENABLE

RESET

V

DD

EMBEDDED DOWNLOAD/DEBUG KERNEL

PERMANENTLY EMBEDDED FIRMWARE ALLOWS

FFFFH

2kBYTE

F800H

CODE TO BE DOWNLOADED TO ANY OF THE

62 kBYTES OF ON-CHIP PROGRAM MEMORY.

THE KERNEL PROGRAM APPEARS AS NOP

INSTRUCTIONS TO USER CODE.

Figure 29. Flash/EE Memory Parallel Programming

The command words that are assigned to P1.1, P1.2, P1.3, and

P1.4 are described in Table 31.

Table 31. Flash/EE Memory Parallel Programming Modes

Port 1 Pins

P1.4 P1.3 P1.2 P1.1 Programming Mode

USER PROGRAM MEMORY

62 kBYTES OF FLASH/EE PROGRAM MEMORY

ARE AVAILABLE TO THE USER. ALL OF THIS

SPACE CAN BE PROGRAMMED FROM THE

PERMANENTLY EMBEDDED DOWNLOAD/DEBUG

KERNEL OR IN PARALLEL PROGRAMMING MODE.

F7FFH

62kBYTE

0000H

0

Erase Flash/EE Program, Data, and

Security Mode

1

0

1

0

1

0

1

0

1

0

1

Program Code Byte

Program Data Byte

Read Code Byte

Figure 28. Flash/EE Program Memory Map in Normal Mode

Read Data Byte

In normal mode, the 62 kbytes of Flash/EE program memory

can be programmed by serial downloading and by parallel

programming.

Program Security Modes

Read/Verify Security Modes

Redundant

All other codes

Rev. A | Page 49 of 108

ADuC845/ADuC847/ADuC848

USER DOWNLOAD MODE (ULOAD)

The 32-kbyte memory parts have the user bootload space

starting at 6000H. The memory mapping is shown in Figure 31.

Figure 28 shows that it is possible to use the 62 kbytes of

Flash/EE program memory available to the user as one single

block of memory. In this mode, all the Flash/EE memory is

read-only to user code.

EMBEDDED DOWNLOAD/DEBUG KERNEL

PERMANENTLY EMBEDDED FIRMWARE ALLOWS

FFFFH

2kBYTE

F800H

CODE TO BE DOWNLOADED TO ANY OF THE

32 kBYTES OF ON-CHIP PROGRAM MEMORY.

THE KERNEL PROGRAM APPEARS AS NOP

INSTRUCTIONS TO USER CODE.

However, most of the Flash/EE program memory can also be

written to during run time simply by entering ULOAD mode.

In ULOAD mode, the lower 56 kbytes of program memory can

be erased and reprogrammed by the user software as shown in

Figure 30. ULOAD mode can be used to upgrade the code in

the field via any user-defined download protocol. By configuring

the SPI port on the ADuC845/ADuC847/ADuC848 as a slave, it

is possible to completely reprogram the 56 kbytes of Flash/EE

program memory in under 5 s (see Application Note uC007,

“User Download Mode” at www.analog.com/microconverter).

NOT AVAILABLE TO USER

USER BOOTLOADER SPACE

THE USER BOOTLOADER

8000H

8kBYTE

6000H

SPACE CAN BE PROGRAMMED IN

DOWNLOAD/DEBUG MODE VIA THE

KERNEL BUT IS READ ONLY WHEN

32 kBYTES

EXECUTING USER CODE

OF USER

CODE

MEMORY

5FFFH

24kBYTE

0000H

USER DOWNLOADER SPACE

EITHER THE DOWNLOAD/DEBUG

KERNEL OR USER CODE (IN ULOAD

MODE) CAN PROGRAM THIS SPACE

Alternatively, ULOAD mode can be used to save data to the

56 kbytes of Flash/EE memory. This can be extremely useful in

data logging applications where the parts can provide up to

60 kbytes of data memory on-chip (4 kbytes of dedicated

Flash/EE data memory also exist).

Figure 31. Flash/EE Program Memory Map in ULOAD Mode (32-kbyte Part)

ULOAD mode is not available on the 8-kbyte Flash/EE program

memory parts.

Flash/EE Program Memory Security

The upper 6 kbytes of the 62 kbytes of Flash/EE program

memory (8 kbytes on the 32-kbyte parts) are programmable

only via serial download or parallel programming. This means

that this space appears as read-only to user code; therefore, it

cannot be accidentally erased or reprogrammed by erroneous

code execution, making it very suitable to use the 6 kbytes as a

bootloader. A bootload enable option exists in the Windows®

serial downloader (WSD) to “Always RUN from E000H after

Reset.” If using a bootloader, this option is recommended to

ensure that the bootloader always executes correct code after

reset.

The ADuC845/ADuC847/ADuC848 facilitate three modes of

Flash/EE program memory security: the lock, secure, and serial

safe modes. These modes can be independently activated,

restricting access to the internal code space. They can be

enabled as part of serial download protocol, as described in

Application Note uC004, or via parallel programming.

Lock Mode

This mode locks the code memory, disabling parallel program-

ming of the program memory. However, reading the memory in

parallel mode and reading the memory via a MOVC command

from external memory are still allowed. This mode is deactivated

by initiating an ERASE CODE AND DATA command in serial

download or parallel programming modes.

Programming the Flash/EE program memory via ULOAD

mode is described in the Flash/EE Memory Control SFR section

of ECON and also in Application Note uC007

Secure Mode

(www.analog.com/microconverter).

This mode locks the code memory, disabling parallel program-

ming of the program memory. Reading/verifying the memory

in parallel mode and reading the internal memory via a MOVC

command from external memory are also disabled. This mode

is deactivated by initiating an ERASE CODE AND DATA

command in serial download or parallel programming modes.

EMBEDDED DOWNLOAD/DEBUG KERNEL

PERMANENTLY EMBEDDED FIRMWARE ALLOWS

CODE TO BE DOWNLOADED TO ANY OF THE

FFFFH

2kBYTE

F800H

62 kBYTES OF ON-CHIP PROGRAM MEMORY.

THE KERNEL PROGRAM APPEARS AS NOP

INSTRUCTIONS TO USER CODE.

F7FFH

6kBYTE

E000H

USER BOOTLOADER SPACE

THE USER BOOTLOADER

SPACE CAN BE PROGRAMMED IN

DOWNLOAD/DEBUG MODE VIA THE

KERNEL BUT IS READ ONLY WHEN

Serial Safe Mode

This mode disables serial download capability on the device. If

serial safe mode is activated and an attempt is made to reset the

part into serial download mode, that is, RESET asserted (pulled

62 kBYTES

OF USER

CODE

EXECUTING USER CODE

dFFFH

56kBYTE

0000H

USER DOWNLOADER SPACE

MEMORY

EITHER THE DOWNLOAD/DEBUG

KERNEL OR USER CODE (IN

ULOAD MODE) CAN PROGRAM

THIS SPACE

high) and de-asserted (pulled low) with

low, the part

PSEN

interprets the serial download reset as a normal reset only. It

therefore does not enter serial download mode, but executes only

a normal reset sequence. Serial safe mode can be disabled only

by initiating an ERASE CODE AND DATA command in

parallel programming mode.

Figure 30. Flash/EE Program Memory Map in ULOAD Mode (62-kbyte Part)

Rev. A | Page 50 of 108

ADuC845/ADuC847/ADuC848

BYTE 1

(0FFCH)

BYTE 3

(0FFEH)

BYTE 2

BYTE 4

(0FFFH)

USING FLASH/EE DATA MEMORY

3FFH

3FEH

(0FFDH)

BYTE 1

(0FF8H)

BYTE 2

(0FF9H)

BYTE 3

(0FFAH)

BYTE 4

(0FFBH)

The 4 kbytes of Flash/EE data memory are configured as 1024

pages, each of 4 bytes. As with the other ADuC845/ADuC847/

ADuC848 peripherals, the interface to this memory space is via

a group of registers mapped in the SFR space. A group of four

data registers (EDATA1–4) holds the 4 bytes of data at each

page. The page is addressed via the EADRH and EADRL

registers. Finally, ECON is an 8-bit control register that can be

written to with one of nine Flash/EE memory access commands

to trigger various read, write, erase, and verify functions. A block

diagram of the SFR interface to the Flash/EE data memory array

is shown in Figure 32.

BYTE 1

(000CH)

BYTE 3

(000EH)

BYTE 4

(000FH)

BYTE 2

(000DH)

03H

02H

01H

00H

BYTE 1

(0008H)

BYTE 3

(000AH)

BYTE 4

(000BH)

BYTE 2

(0009H)

BYTE 1

(0004H)

BYTE 3

(0006H)

BYTE 4

(0007H)

BYTE 2

(0005H)

BYTE 1

(0000H)

BYTE 3

(0002H)

BYTE 4

(0003H)

BYTE 2

(0001H)

BYTE

ADDRESSES

ARE GIVEN IN

BRACKETS

ECON—Flash/EE Memory Control SFR

Programming either Flash/EE data memory or Flash/EE

program memory is done through the Flash/EE memory

control SFR (ECON). This SFR allows the user to read, write,

erase, or verify the 4 kbytes of Flash/EE data memory or the

56 kbytes of Flash/EE program memory.

Figure 32. Flash/EE Data Memory Control and Configuration

Table 32. ECON—Flash/EE Memory Commands

Command Description

(Normal Mode, Power-On Default)

Command Description

(ULOAD Mode)

ECON Value

01H Read

4 bytes in the Flash/EE data memory, addressed by the

page address EADRH/L, are read into EDATA1–4.

Not implemented. Use the MOVC instruction.

02H Write

Results in 4 bytes in EDATA1–4 being written to the

Flash/EE data memory, at the page address given by

Bytes 0 to 255 of internal XRAM are written to the 256 bytes of

Flash/EE program memory at the page address given by

EADRH (0 ≤ EADRH < 0400H). Note that the 4 bytes in the EADRH/L (0 ≤ EADRH/L < E0H).

page being addressed must be pre-erased.

Note that the 256 bytes in the page being addressed must be

pre-erased.

03H

Reserved.

04H Verify

Verifies that the data in EDATA1–4 is contained in the

page address given by EADRH/L. A subsequent read of

the ECON SFR results in a 0 being read if the verification

is valid, or a nonzero value being read to indicate an

invalid verification.

Not implemented. Use the MOVC and MOVX instructions to

verify the Write in software.

05H Erase Page 4-byte page of Flash/EE data memory address is erased

by the page address EADRH/L.

64-byte page of FLASH/EE program memory addressed by the

byte address EADRH/L is erased. A new page starts when EADRL

is equal to 00H, 80H, or C0H.

06H Erase All

81H ReadByte

4 kbytes of Flash/EE data memory are erased.

The entire 56 kbytes of ULOAD are erased.

Not implemented. Use the MOVC command.

The byte in the Flash/EE data memory, addressed by the

byte address EADRH/L, is read into EDATA1 (0 ≤ EADRH/L

≤ 0FFFH).

82H WriteByte

0FH EXULOAD

F0H ULOAD

The byte in EDATA1 is written into Flash/EE data memory The byte in EDATA1 is written into Flash/EE program memory at

at the byte address EADRH/L.

the byte address EADRH/L (0 ≤ EADRH/L ≤ DFFFH).

Configures the ECON instructions (above) to operate on

Flash/EE data memory.

Enters normal mode, directing subsequent ECON instructions to

operate on the Flash/EE data memory.

Enters ULOAD mode; subsequent ECON instructions

operate on Flash/EE program memory.

Enables the ECON instructions to operate on the Flash/EE

program memory. ULOAD entry mode.

Rev. A | Page 51 of 108

ADuC845/ADuC847/ADuC848

Example: Programming the Flash/EE Data Memory

FLASH/EE MEMORY TIMING

A user wants to program F3H into the second byte on Page 03H

of the Flash/EE data memory space while preserving the other

3 bytes already in this page. A typical program of the Flash/EE

data array involves

Typical program and erase times for the parts are as follows:

Normal Mode (Operating on Flash/EE Data Memory)

Command

Bytes Affected

4 bytes

4 kbytes

1 byte

READPAGE

WRITEPAGE

VERIFYPAGE

ERASEPAGE

ERASEALL

25 machine cycles

380 µs

25 machine cycles

2 ms

10 machine cycles

200 µs

1. Setting EADRH/L with the page address.

2. Writing the data to be programmed to the EDATA1–4.

3. Writing the ECON SFR with the appropriate command.

READBYTE

WRITEBYTE

Step 1: Set Up the Page Address

Address registers EADRH and EADRL hold the high byte

address and the low byte address of the page to be addressed.

The assembly language to set up the address may appear as

ULOAD Mode (Operating on Flash/EE Program Memory)

WRITEPAGE

ERASEPAGE

ERASEALL

256 bytes

64 bytes

56 kbytes

1 byte

15 ms

2 ms

MOV EADRH, #0

MOV EADRL, #03H

;Set Page Address Pointer

Step 2: Set Up the EDATA Registers

WRITEBYTE

200 µs

Write the four values to be written into the page into the four

SFRs EDATA1–4. Unfortunately, the user does not know three

of them. Thus, the user must read the current page and overwrite

the second byte.

Note that a given mode of operation is initiated as soon as the

command word is written to the ECON SFR. The core micro-

controller operation is idled until the requested program/read

or erase mode is completed. In practice, this means that even

though the Flash/EE memory mode of operation is typically

initiated with a two-machine-cycle MOV instruction (to write

to the ECON SFR), the next instruction is not executed until the

Flash/EE operation is complete. This means that the core cannot

respond to interrupt requests until the Flash/EE operation is

complete, although the core peripheral functions such as counter/

timers continue to count as configured throughout this period.

MOV ECON,

#1

;Read Page into EDATA1-4

MOV EDATA2, #0F3H ;Overwrite Byte 2

Step 3: Program Page

A byte in the Flash/EE array can be programmed only if it has

previously been erased. Specifically, a byte can be programmed

only if it already holds the value FFH. Because of the Flash/EE

architecture, this erasure must happen at a page level; therefore,

a minimum of 4 bytes (1 page) are erased when an erase

command is initiated. Once the page is erased, the user can

program the 4 bytes in-page and then perform a verification of

the data.

MOV ECON, #5

MOV ECON, #2

MOV ECON, #4

MOV A, ECON

;ERASE Page

;WRITE Page

;VERIFY Page

;Check if ECON = 0 (OK!)

Although the 4 kbytes of Flash/EE data memory are factory pre-

erased, that is, byte locations set to FFH, it is good programming

practice to include an ERASEALL routine as part of any

configuration/set-up code running on the parts. An ERASEALL

command consists of writing 06H to the ECON SFR, which

initiates an erase of the 4-kbyte Flash/EE array. This command

coded in 8051 assembly language would appear as

MOV ECON, #06H

;ERASE all Command

;2ms duration

Rev. A | Page 52 of 108

ADuC845/ADuC847/ADuC848

DAC CIRCUIT INFORMATION

The ADuC845/ADuC847/ADuC848 incorporate a 12-bit,

voltage output DAC on-chip. It has a rail-to-rail voltage output

buffer capable of driving 10 kΩ/100 pF, and has two selectable

ranges, 0 V to V_REFand 0 V to AV_DD. It can operate in 12-bit or

8-bit mode. The DAC has a control register, DACCON, and two

data registers, DACH/L. The DAC output can be programmed

to appear at Pin 14 or Pin 13 (AINCOM).

Note that in 12-bit mode, the DAC voltage output is updated as

soon as the DACL data SFR is written; therefore, the DAC data

registers should be updated as DACH first, followed by DACL.

The 12-bit DAC data should be written into DACH/L right-

justified such that DACL contains the lower 8 bits, and the

lower nibble of DACH contains the upper 4 bits.

DACCON Control Register

SFR Address:

Power-On Default:

Bit Addressable:

FDH

00H

No

Table 33. DACCON—DAC Configuration Commands

Bit No.

Name

Description

7

6

5

4

–––

DACPIN

Not Implemented. Write Don’t Care.

DAC Output Pin Select.

Set to 1 by the user to direct the DAC output to Pin 13 (AINCOM).

Cleared to 0 by the user to direct the DAC output to Pin 14 (DAC).

DAC 8-Bit Mode Bit.

3

DAC8

Set to 1 by the user to enable 8-bit DAC operation. In this mode, the 8 bits in DACL SFR are routed to the 8 MSBs

of the DAC, and the 4 LSBs of the DAC are set to 0.

Cleared to 0 by the user to enable 12-bit DAC operation. In this mode, the 8 LSBs of the result are routed to

DACL, and the upper 4 MSB bits are routed to the lower 4 bits of DACH.

2

1

0

DACRN

DACCLR

DACEN

DAC Output Range Bit.

Set to 1 by the user to configure the DAC range of 0 V to AV_DD

.

Cleared to 0 by the user to configure the DAC range of 0 V to 2.5 V (V_REF).

DAC Clear Bit.

Set to 1 by the user to enable normal DAC operation.

Cleared to 0 by the user to reset the DAC data registers DACL/H to 0.

DAC Enable Bit.

Set to 1 by the user to enable normal DAC operation.

Cleared to 0 by the user to power down the DAC.

DACH/DACL Data Registers

These DAC data registers are written to by the user to update

the DAC output.

SFR Address:

DACL (DAC Data Low Byte)—FBH

DACH (DAC Data High Byte)—FCH

00H (Both Registers)

Power-On Default:

Bit Addressable:

No (Both Registers)

Rev. A | Page 53 of 108

ADuC845/ADuC847/ADuC848

V

DD

Using the DAC

V

–50mV

DD

The on-chip DAC architecture consists of a resistor string DAC

followed by an output buffer amplifier, the functional equivalent

of which is shown in Figure 33.

V

–100mV

DD

AV

DD

V

REF

R

OUTPUT

BUFFER

100mV

14

50mV

0mV

FFFH

000H

HIGH-Z

DISABLE

(FROM MCU)

Figure 34. Endpoint Nonlinearities Due to Amplifier Saturation

R

The endpoint nonlinearities shown in Figure 34 become worse

as a function of output loading. Most data sheet specifications

assume a 10 kΩ resistive load to ground at the DAC output. As

the output is forced to source or sink more current, the nonlinear

regions at the top or bottom, respectively, of Figure 34 become

larger. With larger current demands, this can significantly limit

output voltage swing. Figure 35 and Figure 36 illustrate this

behavior. Note that the upper trace in each of these figures is

valid only for an output range selection of 0 V to AV_DD. In 0 V-

to-V_REFmode, DAC loading does not cause high-side voltage

nonlinearities while the reference voltage remains below the

Figure 33. Resistor String DAC Functional Equivalent

Features of this architecture include inherent guaranteed

monotonicity and excellent differential linearity. As shown in

Figure 33, the reference source for the DAC is user-selectable in

software. It can be either AV_DDor V_REF. In 0 V-to-AV_DDmode,

the DAC output transfer function spans from 0 V to the voltage

at the AV_DDpin. In 0 V-to-V_REFmode, the DAC output transfer

function spans from 0 V to the internal V_REF(2.5 V). The DAC

output buffer amplifier features a true rail-to-rail output stage

implementation. This means that, unloaded, each output is

capable of swinging to within less than 100 mV of both AV_DD

and ground. Moreover, the DAC’s linearity specification (when

driving a 10 kΩ resistive load to ground) is guaranteed through

the full transfer function except Codes 0 to 48 in 0 V-to-V_REF

mode and 0 to 100 and 3950 to 4095 in 0 V-to-V_DDmode.

upper trace in the corresponding figure. For example, if AV_DD

3 V and V_REF= 2.5 V, the high-side voltage is not affected by

loads of less than 5 mA. But around 7 mA, the upper curve in

Figure 36 drops below 2.5 V (V_REF), indicating that at these

=

higher currents, the output is not capable of reaching V_REF

.

5

DAC LOADED WITH 0FFFH

4

Linearity degradation near ground and V_DDis caused by satura-

tion of the output amplifier; a general representation of its effects

(neglecting offset and gain error) is shown in Figure 34. The

dotted line indicates the ideal transfer function, and the solid

line represents what the transfer function might look like with

endpoint nonlinearities due to saturation of the output amplifier.

3

2

1

DAC LOADED WITH 0000H

Note that Figure 34 represents a transfer function in 0-to-V_DD

mode only. In 0 V-to-V_REFmode (with V_REF< V_DD), the lower

nonlinearity would be similar, but the upper portion of the

transfer function would follow the ideal line to the end, showing

no signs of the high-end endpoint linearity error.

0

5

10

15

SOURCE/SINK CURRENT (mA)

Figure 35. Source and Sink Current Capability with V_REF= AV_DD= 5 V

Rev. A | Page 54 of 108

ADuC845/ADuC847/ADuC848

3

2

1

0

PULSE-WIDTH MODULATOR (PWM)

The ADuC845/ADuC847/ADuC848 has a highly flexible PWM

offering programmable resolution and an input clock. The

PWM can be configured in six different modes of operation.

Two of these modes allow the PWM to be configured as a Σ-∆

DAC with up to 16 bits of resolution. A block diagram of the

PWM is shown in Figure 38.

DAC LOADED WITH 0FFFH

12.583MHz (F_VCO)

EXTERNAL CLOCK ON P2.7

32.768kHz (F_XTAL)

CLOCK

SELECT

PROGRAMMABLE

DIVIDER

DAC LOADED WITH 0000H

32.768kHz/15

0

5

10

15

16-BIT PWM COUNTER

SOURCE/SINK CURRENT (mA)

Figure 36. Source and Sink Current Capability with V_REF= AV_DD= 3 V

P2.5

P2.6

For larger loads, the current drive capability may not be sufficient.

To increase the source and sink current capability of the DAC,

an external buffer should be added as shown in Figure 37.

COMPARE

MODE

PWM0H/L PWM1H/L

Figure 38. PWM Block Diagram

The PWM uses control SFR, PWMCON, and four data SFRs:

PWM0H, PWM0L, PWM1H, and PWM1L.

ADuC845/

ADuC847/ _DAC

ADuC848

14

PWMCON (as described in Table 34) controls the different

modes of operation of the PWM as well as the PWM clock

frequency. PWM0H/L and PWM1H/L are the data registers that

determine the duty cycles of the PWM outputs at P2.5 and P2.6.

Figure 37. Buffering the DAC Output

The internal DAC output buffer also features a high impedance

disable function. In the chip’s default power-on state, the DAC is

disabled and its output is in a high impedance state (or three-

state) where it remains inactive until enabled in software. This

means that if a zero output is desired during power-on or

power-down transient conditions, a pull-down resistor must be

added to each DAC output. Assuming that this resistor is in

place, the DAC output remains at ground potential whenever

the DAC is disabled.

To use the PWM user software, first write to PWMCON to

select the PWM mode of operation and the PWM input clock.

Writing to PWMCON also resets the PWM counter. In any of

the 16-bit modes of operation (Modes 1, 3, 4, 6), user software

should write to the PWM0L or PWM1L SFRs first. This value is

written to a hidden SFR. Writing to the PWM0H or PWM1H

SFRs updates both the PWMxH and the PWMxL SFRs but does

not change the outputs until the end of the PWM cycle in

progress. The values written to these 16-bit registers are then

used in the next PWM cycle.

Rev. A | Page 55 of 108

ADuC845/ADuC847/ADuC848

PWMCON PWM Control SFR

SFR Address:

Power-On Default:

Bit Addressable:

AEH

00H

No

Table 34. PWMCON PWM Control SFR

Bit No. Name Description

Not Implemented. Write Don’t Care.

7

–––

6, 5, 4

PWM2, PWM1, PWM0 PMW Mode Selection.

PWM2 PWM1 PWM0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Mode 0: PWM disabled.

Mode 1: Single 16-bit output with programmable pulse and cycle time.

Mode 2: Twin 8-bit outputs.

Mode 3: Twin 16-bit outputs.

Mode 4: Dual 16-bit pulse density outputs.

Mode 5: Dual 8-bit outputs.

Mode 6: Dual 16-bit pulse density RZ outputs.

Mode 7: PWM counter reset with outputs not used.

3, 2

1, 0

PWS1, PWS0

PWC1, PWC0

PWM Clock Source Divider.

PWS1

PWS0

0

1

0

1

0

1

Selected clock.

Selected clock divided by 4.

Selected clock divided by 16.

Selected clock divided by 64.

PWM Clock Source Selection.

PWC1 PWC0

0

1

0

1

0

1

F_XTAL/15 (2.184 kHz).

F_XTAL(32.768 kHz).

External input on P2.7.

F_VCO(12.58 MHz).

PWM Pulse Width High Byte (PWM0H)

SFR Address:

Power-On Default:

Bit Addressable:

B2H

00H

No

Table 35. PWM0H: PWM Pulse Width High Byte

PWM0H.7

PWM0H.6

PWM0H.5

PWM0H.4

PWM0H.3

PWM0H.2

PWM0H.1

PWM0H.0

0

R/W

PWM Pulse Width Low Byte (PWM0L)

SFR Address:

Power-On Default:

Bit Addressable:

B1H

00H

No

Table 36. PWM0L: PWM Pulse Width Low Byte

PWM0L.7

PWM0L.6

PWM0L.5

PWM0L.4

PWM0L.3

PWM0L.2

PWM0L.1

PWM0L.0

0

R/W

Rev. A | Page 56 of 108

ADuC845/ADuC847/ADuC848

PWM Cycle Width High Byte (PWM1H)

SFR Address:

Power-On Default:

Bit Addressable:

B4H

00H

No

Table 37. PWM1H: PWM Cycle Width High Byte

PWM1H.7

PWM1H.6

PWM1H.5

PWM1H.4

PWM1H.3

PWM1H.2

PWM1H.1

PWM1H.0

0

R/W

PWM Cycle Width Low Byte (PWM1L)

SFR Address:

Power-On Default:

Bit Addressable:

B3H

00H

No

Table 38. PWM1L: PWM Cycle Width Low Byte

PWM1L.7

PWM1L.6

PWM1L.5

PWM1L.4

PWM1L.3

PWM1L.2

PWM1L.1

PWM1L.0

0

R/W

Mode 0

Mode 2 (Twin 8-Bit PWM)

In Mode 0, the PWM is disabled, allowing P2.5 and P2.6 to be

used as normal digital I/Os.

In Mode 2, the duty cycle and the resolution of the PWM

outputs are programmable. The maximum resolution of the

PWM output is 8 bits.

Mode 1 (Single-Variable Resolution PWM)

In Mode 1, both the pulse length and the cycle time (period) are

programmable in user code, allowing the resolution of the PWM

to be variable. PWM1H/L sets the period of the output waveform.

Reducing PWM1H/L reduces the resolution of the PWM output

but increases the maximum output rate of the PWM. For

example, setting PWM1H/L to 65536 gives a 16-bit PWM with

a maximum output rate of 192 Hz (12.583 MHz/65536). Setting

PWM1H/L to 4096 gives a 12-bit PWM with a maximum

output rate of 3072 Hz (12.583 MHz/4096).

PWM1L sets the period for both PWM outputs. Typically, this is

set to 255 (FFH) to give an 8-bit PWM, although it is possible to

reduce this as necessary. A value of 100 could be loaded here to

give a percentage PWM, that is, the PWM is accurate to 1%.

The outputs of the PWM at P2.5 and P2.6 are shown in Figure 40.

As can be seen, the output of PWM0 (P2.5) goes low when the

PWM counter equals PWM0L. The output of PWM1 (P2.6) goes

high when the PWM counter equals PWM1H and goes low

again when the PWM counter equals PWM0H. Setting PWM1H

to 0 ensures that both PWM outputs start simultaneously.

PWM0H/L sets the duty cycle of the PWM output waveform as

shown in Figure 39.

PWM1L

PWM COUNTER

PWM1H/L

PWM COUNTER

PWM0H

PWM0L

PWM0H/L

PWM1H

0

P2.5

P2.6

Figure 39. PWM in Mode 1

Figure 40. PWM Mode 2

Rev. A | Page 57 of 108

ADuC845/ADuC847/ADuC848

Mode 3 (Twin 16-Bit PWM)

Mode 4 (Dual NRZ 16-Bit Σ-∆ DAC)

In Mode 3, the PWM counter is fixed to count from 0 to 65536,

giving a fixed 16-bit PWM. Operating from the 12.58 MHz core

clock results in a PWM output rate of 192 Hz. The duty cycle of

the PWM outputs at P2.5 and P2.6 are independently

programmable.

Mode 4 provides a high speed PWM output similar to that of a

Σ-∆ DAC. Typically, this mode is used with the PWM clock

equal to 12.58 MHz.

In this mode, P1.0 and P1.1 are updated every PWM clock

(80 ns in the case of 12.58 MHz). Over any 65536 cycles (16-bit

PWM), PWM0 (P1.0) is high for PWM0H/L cycles and low for

(65536 – PWM0H/L) cycles. Similarly, PWM1 (P1.1) is high for

PWM1H/L cycles and low for (65536 – PWM1H/L) cycles.

As shown in Figure 41, while the PWM counter is less than

PWM0H/L, the output of PWM0 (P2.5) is high. Once the PWM

counter equals PWM0H/L, PWM0 (P2.5) goes low and remains

low until the PWM counter rolls over.

If PWM1H is set to 4010H (slightly above one-quarter of FS),

typically P1.1 is low for three clocks and high for one clock

(each clock is approximately 80 ns). Over every 65536 clocks,

the PWM compromises for the fact that the output should be

slightly above one-quarter of full scale, by having a high cycle

followed by only two low cycles.

Similarly, while the PWM counter is less than PWM1H/L, the

output of PWM1 (P2.6) is high. Once the PWM counter equals

PWM1H/L, PWM1 (P2.6) goes low and remains low until the

PWM counter rolls over.

In this mode, both PWM outputs are synchronized, that is, once

the PWM counter rolls over to 0, both PWM0 (P2.5) and PWM1

(P2.6) go high.

PWM0H/L = C000H

CARRY OUT AT P2.5

0

1

16-BIT

65536

PWM COUNTER

PWM1H/L

80µs

16-BIT

PWM0H/L

0

12.583MHz

16-BIT

LATCH

P2.5

P2.6

16-BIT

0

1

CARRY OUT AT P2.6

16-BIT

Figure 41. PWM Mode 3

80µs

PWM1H/L = 4000H

Figure 42. PWM Mode 4

For faster DAC outputs (at lower resolution), write 0s to the

LSBs that are not required with a 1 in the LSB position. If, for

example, only 12-bit performance is required, write 0001 to the

4 LSBs. This means that a 12-bit accurate Σ -Δ DAC output can

occur at 3 kHz. Similarly, writing 00000001 to the 8 LSBs gives

an 8-bit accurate Σ-Δ DAC output at 49 kHz.

Rev. A | Page 58 of 108

ADuC845/ADuC847/ADuC848

Mode 5 (Dual 8-Bit PWM)

The output resolution is set by the PWM1L and PWM1H SFRs

for the P2.5 and P2.6 outputs, respectively. PWM0L and PWM0H

set the duty cycles of the PWM outputs at P2.5 and P2.6,

respectively. Both PWMs have the same clock source and clock

divider.

In Mode 5, the duty cycle and the resolution of the PWM outputs

are individually programmable. The maximum resolution of the

PWM output is 8 bits.

PWM1L

PWM COUNTERS

PWM0H/L = C000H

PWM1H

PWM0L

CARRY OUT AT P2.5

0

1

16-BIT

PWM0H

0

318µs

16-BIT

P2.5

P2.6

3.146MHz

16-BIT

LATCH

Figure 43. PWM Mode 5

16-BIT

Mode 6 (Dual RZ 16-Bit Σ-∆ DAC)

0

1

0

Mode 6 provides a high speed PWM output similar to that of a

Σ-Δ DAC. Mode 6 operates very similarly to Mode 4; however,

the key difference is that Mode 6 provides return to zero (RZ)

Σ-Δ DAC output. Mode 4 provides non-return-to-zero Σ-Δ

DAC outputs. RZ mode ensures that any difference in the rise

and fall times does not affect the Σ-Δ DAC INL. However, RZ

mode halves the dynamic range of the Σ-Δ DAC outputs from 0

V− to AV_DDdown to 0 V to AV_DD/2. For best results, this mode

should be used with a PWM clock divider of 4.

0, 3/4, 1/2, 1/4, 0

CARRY OUT AT P2.6

16-BIT

318µs

PWM1H/L = 4000H

Figure 44. PWM Mode 6

Mode 7

In Mode 7, the PWM is disabled, allowing P2.5 and P2.6 to be

used as normal.

If PWM1H is set to 4010H (slightly above one-quarter of FS),

typically P2.6 is low for three full clocks (3 × 80 ns), high for

one-half a clock (40 ns), and then low again for one-half a clock

(40 ns) before repeating itself. Over every 65536 clocks, the

PWM compromises for the fact that the output should be

slightly above one-quarter of full scale by leaving the output

high for two half clocks in four every so often.

For faster DAC outputs (at lower resolution), write 0s to the

LSBs that are not required with a 1 in the LSB position. If, for

example, only 12-bit performance is required, write 0001 to the

4 LSBs. This means that a 12-bit accurate Σ-Δ DAC output can

occur at 3 kHz. Similarly, writing 00000001 to the 8 LSBs gives

an 8-bit accurate Σ-Δ DAC output at 49 kHz.

Rev. A | Page 59 of 108

ADuC845/ADuC847/ADuC848

ON-CHIP PLL (PLLCON)

The ADuC845/ADuC847/ADuC848 are intended for use with a

32.768 kHz watch crystal. A PLL locks onto a multiple (384) of

this to provide a stable 12.582912 MHz clock for the system.

The core can operate at this frequency or at binary submultiples

of it to allow power saving when maximum core performance is

not required. The default core clock is the PLL clock divided by

8 or 1.572864 MHz. The ADC clocks are also derived from the

PLL clock, with the modulator rate being the same as the crystal

oscillator frequency. The control register for the PLL is called

PLLCON and is described as follows.

The 5 V parts can be set to a maximum core frequency of

12.58 MHz (CD2...0 = 000) while at 3 V, the maximum core

clock rate is 6.29 MHz (CD2...0 = 001). The CD bits should not

be set to 000b on the 3 V parts.

The 3 V parts are limited to a core clock speed of 6.29 MHz

(CD = 1).

PLLCON PLL Control Register

SFR Address:

Power-On Default:

Bit Addressable:

D7H

53H

No

Table 39. PLLCON PLL Control Register

Bit No.

Name

Description

7

OSC_PD

Oscillator Power-Down Bit.

If low, the 32 kHz crystal oscillator continues running in power-down mode.

If high, the 32.768 kHz oscillator is powered down.

When this bit is low, the seconds counter continues to count in power-down mode and can interrupt the CPU

to exit power-down. The oscillator is always enabled in normal mode.

6

LOCK

PLL Lock Bit. This is a read-only bit.

Set automatically at power-on to indicate that the PLL loop is correctly tracking the crystal clock. After power-

down, this bit can be polled to wait for the PLL to lock.

Cleared automatically at power-on to indicate that the PLL is not correctly tracking the crystal clock. This

might be due to the absence of a crystal clock or an external crystal at power-on. In this mode, the PLL output

can be 12.58 MHz 20%. After the part wakes up from power-down, user code can poll this bit to wait for the

PLL to lock. If LOCK = 0, the PLL is not locked.

5

4

3

–––

LTEA

FINT

Not Implemented. Write Don’t Care.

EA Status. Read-only bit. Reading this bit returns the state of the external EA pin latched at reset or power-on.

Fast Interrupt Response Bit.

Set by the user to enable the response to any interrupt to be executed at the fastest core clock frequency.

Cleared by the user to disable the fast interrupt response feature.

2, 1, 0

CD2, CD1, CD0

CPU (Core Clock) Divider Bits. This number determines the frequency at which the core operates.

CD2

0

CD1

0

CD0

0

Core Clock Frequency (MHz)

12.582912

0

1

6.291456 (Maximum core clock rate allowed on the 3 V parts)

0

1

0

3.145728

0

1

1.572864 (Default core frequency)

1

0

1

0

1

0

1

0.786432

0.393216

0.196608

0.098304

Rev. A | Page 60 of 108

ADuC845/ADuC847/ADuC848

Note that when using the I²C and SPI interfaces simultaneously,

they both use the same interrupt routine (Vector Address 3BH).

When an interrupt occurs from one of these, it is necessary to

interrogate each interface to see which one has triggered the ISR

request.

I²C SERIAL INTERFACE

The ADuC845/ADuC847/ADuC848 support a fully licensed

I²C serial interface. The I²C interface is implemented as a full

hardware slave and software master. SDATA (Pin 27 on the

MQFP package and Pin 29 on the CSP package) is the data I/O

pin. SCLK (Pin 26 on the MQFP package and Pin 28 on the CSP

package) is the serial interface clock for the SPI interface. The

I²C interface on the parts is fully independent of all other pin/

function multiplexing. The I²C interface incorporated on the

ADuC845/ADuC847/ADuC848 also includes a second address

register (I2CADD1) at SFR Address F2H with a default power-

on value of 7FH. The I²C interface is always available to the user

and is not multiplexed with any other I/O functionality on the

chip. This means that the I²C and SPI interfaces can be used at

the same time.

The four SFRs are used to control the I²C interface are

described next.

I2CCON—I²C Control Register

SFR Address:

Power-On Default:

Bit Addressable:

E8H

00H

Yes

Table 40. I2CCON SFR Bit Designations

Bit No.

Name

Description

I²C Software Master Data Output Bit (master mode only).

7

MDO

This data bit is used to implement a master I²C transmitter interface in software. Data written to this bit is output on

the SDATA pin if the data output enable bit (MDE) is set.

6

MDE

I²C Software Output Enable Bit (master mode only).

Set by the user to enable the SDATA pin as an output (Tx).

Cleared by the user to enable the SDATA pin as an input (Rx).

I²C Software Master Clock Output Bit (master mode only).

This bit is used to implement the SCLK for a master I²C transmitter in software. Data written to this bit is output on

the SCLK pin.

I²C Software Master Data Input Bit (master mode only).

This data bit is used to implement a master I²C receiver interface in software. Data on the SDATA pin is latched into

this bit on an SCLK transition if the data output enable (MDE) bit is 0.

I²C Master/Slave Mode Bit.

5

4

3

MCO

MDI

I2CM

Set by the user to enable I²C software master mode.

Cleared by the user to enable I²C hardware slave mode.

I²C Reset Bit (slave mode only).

2

1

0

I2CRS

I2CTX

I2CI

Set by the user to reset the I²C interface.

Cleared by the user code for normal I²C operation.

I²C Direction Transfer Bit (slave mode only).

Set by the MicroConverter if the I²C interface is transmitting.

Cleared by the MicroConverter if the I²C interface is receiving.

I²C Interrupt Bit (slave mode only).

Set by the MicroConverter after a byte has been transmitted or received.

Cleared by the MicroConverter when the user code reads the I2CDAT SFR. I2CI should not be cleared by user code.

Rev. A | Page 61 of 108

ADuC845/ADuC847/ADuC848

I2CADD—I²C Address Register 1

Function:

Holds one of the I²C peripheral addresses for the part. It may be overwritten by user code. Application Note

uC001 at http://www.analog.com/microconverter describes the format of the I²C standard 7-bit address.

SFR Address:

Power-On Default:

Bit Addressable:

9BH

55H

No

I2CADD1—I²C Address Register 2

Function:

Same as the I2CADD.

SFR Address:

Power-On Default:

Bit Addressable:

F2H

7FH

No

I2CDAT—I²C Data Register

Function:

The I2CDAT SFR is written to by user code to transmit data, or read by user code to read data just received by

the I²C interface. Accessing I2CDAT automatically clears any pending I²C interrupt and the I2CI bit in the

I2CCON SFR. User code should access I2CDAT only once per interrupt cycle.

SFR Address:

Power-On Default:

Bit Addressable:

9AH

00H

No

Software Master Mode

The main features of the MicroConverter I²C interface are

The ADuC845/ADuC847/ADuC848 can be used as an I²C

master device by configuring the I²C peripheral in master mode

and writing software to output the data bit-by-bit. This is

referred to as a software master. Master mode is enabled by

setting the I2CM bit in the I2CCON register.

•

Only two bus lines are required: a serial data line (SDATA)

and a serial clock line (SCLOCK).

•

An I²C master can communicate with multiple slave

devices. Because each slave device has a unique 7-bit

address, single master/slave relationships can exist at all

times even in a multislave environment.

To transmit data on the SDATA line, MDE must be set to enable

the output driver on the SDATA pin. If MDE is set, the SDATA

pin is pulled high or low depending on whether the MDO bit is

set or cleared. MCO controls the SCLOCK pin and is always

configured as an output in master mode. In master mode, the

SCLOCK pin is pulled high or low depending on the whether

MCO is set or cleared.

•

The ability to respond to two separate addresses when

operating in slave mode.

On-chip filtering rejects <50 ns spikes on the SDATA and

the SCLOCK lines to preserve data integrity.

To receive data, MDE must be cleared to disable the output

driver on SDATA. Software must provide the clocks by toggling

the MCO bit and reading the SDATA pin via the MDI bit. If

MDE is cleared, MDI can be used to read the SDATA pin. The

value of the SDATA pin is latched into MDI on a rising edge of

SCLOCK. MDI is set if the SDATA pin is high on the last rising

edge of SCLOCK. MDI is cleared if the SDATA pin is low on

the last rising edge of SCLOCK.

DV

DD

2

I C

MASTER

SLAVE 1

2

I C

SLAVE 2

Figure 45. Typical I²C System

Software must control MDO, MCO, and MDE appropriately to

generate the start condition, slave address, acknowledge bits,

data bytes, and stop conditions. These functions are described

in Application Note uC001.

Rev. A | Page 62 of 108

ADuC845/ADuC847/ADuC848

Hardware Slave Mode

The I2CTX bit contains the R/W bit sent from the master. If

I2CTX is set, the master is ready to receive a byte; therefore the

slave transmits data by writing to the I2CDAT register. If I2CTX

is cleared, the master is ready to transmit a byte; therefore the

slave receives a serial byte. Software can interrogate the state of

I2CTX to determine whether it should write to or read from

I2CDAT.

After reset, the ADuC845/ADuC847/ADuC848 default to

hardware slave mode. The I²C interface is enabled by clearing

the SPE bit in SPICON. Slave mode is enabled by clearing the

I2CM bit in I2CCON. The parts have a full hardware slave. In

slave mode, the I²C address is stored in the I2CADD register.

Data received or to be transmitted is stored in the I2CDAT

register.

Once the part has received a valid address, hardware holds

SCLOCK low until the I2CI bit is cleared by software. This

allows the master to wait for the slave to be ready before

transmitting the clocks for the next byte.

Once enabled in I²C slave mode, the slave controller waits for

a start condition. If the parts detect a valid start condition,

followed by a valid address, followed by the R/W bit, then the

I2CI interrupt bit is automatically set by hardware. The I²C

peripheral generates a core interrupt only if the user has pre-

configured the I²C interrupt enable bit in the IEIP2 SFR as well

as the global interrupt bit, EA, in the IE SFR. Therefore,

The I2CI interrupt bit is set every time a complete data byte is

received or transmitted, provided that it is followed by a valid

ACK. If the byte is followed by a NACK, an interrupt is not

generated.

MOV IEIP2, #01h

SETB EA

;Enable I²C Interrupt

The part continues to issue interrupts for each complete data

byte transferred until a stop condition is received or the interface

is reset.

An autoclear of the I2CI bit is implemented on the parts so that

this bit is cleared automatically upon read or write access to the

I2CDAT SFR.

When a stop condition is received, the interface resets to a state

in which it is waiting to be addressed (idle). Similarly, if the

interface receives a NACK at the end of a sequence, it also

returns to the default idle state. The I2CRS bit can be used to

reset the I²C interface. This bit can be used to force the interface

back to the default idle state.

MOV I2CDAT, A

MOV A, I2CDAT

;I2CI auto-cleared

If for any reason the user tries to clear the interrupt more than

once, that is, access the data SFR more than once per interrupt,

the I²C controller stops. The interface then must be reset by

using the I2CRS bit.

The user can choose to poll the I2CI bit or to enable the

interrupt. In the case of the interrupt, the PC counter vectors to

003BH at the end of each complete byte. For the first byte, when

the user gets to the I2CI ISR, the 7-bit address and the R/W bit

appear in the I2CDAT SFR.

Rev. A | Page 63 of 108

ADuC845/ADuC847/ADuC848

MISO (Master In, Slave Out Pin)

SPI SERIAL INTERFACE

Pin 30 (MQFP Package), Pin 32 (CSP Package)

The MISO pin is configured as an input line in master mode

and an output line in slave mode. The MISO line on the master

(data in) should be connected to the MISO line in the slave

device (data out). The data is transferred as byte-wide (8-bit)

serial data, MSB first.

The ADuC845/ADuC847/ADuC848 integrate a complete

hardware serial peripheral interface (SPI) interface on-chip. SPI

is an industry-standard synchronous serial interface that allows

8 bits of data to be synchronously transmitted and received

simultaneously, that is, full duplex. Note that the SPI pins are

multiplexed with the Port 2 pins (P2.0, P2.1, P2.2, and P2.3).

These pins have SPI functionality only if SPE is set. Otherwise,

with SPE cleared, standard Port 2 functionality is maintained.

SPI can be configured for master or slave operation and typically

MOSI (Master Out, Slave In Pin)

Pin 29 (MQFP Package), Pin31 (CSP Package)

The MOSI pin is configured as an output line in master mode

and an input line in slave mode. The MOSI line on the master

(data out) should be connected to the MOSI line in the slave

device (data in). The data is transferred as byte-wide (8-bit)

serial data, MSB first.

consists of pins SCLOCK, MISO, MOSI, and

.

SS

SCLOCK (Serial Clock I/O Pin)

Pin 28 (MQFP Package), Pin 30 (CSP Package)

The master clock (SCLOCK) is used to synchronize the data

transmitted and received through the MOSI and MISO data

lines.

(Slave Select Input Pin)

SS

Pin 31 (MQFP Package), Pin 33 (CSP Package)

The pin is used only when the ADuC845/ADuC847/

SS

A single data bit is transmitted and received in each SCLOCK

period. Therefore, a byte is transmitted/received after eight

SCLOCK periods. The SCLOCK pin is configured as an output

in master mode and as an input in slave mode. In master mode,

the bit rate, polarity, and phase of the clock are controlled by the

CPOL, CPHA, SPR0, and SPR1 bits in the SPICON SFR (see

Table 41). In slave mode, the SPICON register must be configured

with the same phase and polarity (CPHA and CPOL) as the

master. The data is transmitted on one edge of the SCLOCK

signal and sampled on the other.

ADuC848 are configured in SPI slave mode. This line is active

low. Data is received or transmitted in slave mode only when

the pin is low, allowing the parts to be used in single-master,

SS

multislave SPI configurations. If CPHA = 1, the input can be

SS

pulled low permanently. If CPHA = 0, the input must be

SS

driven low before the first bit in a byte-wide transmission or

reception and must return high again after the last bit in that

byte-wide transmission or reception. In SPI slave mode, the

logic level on the external pin (Pin 31/ Pin 33) can be read

SS

via the SPR0 bit in the SPICON SFR.

The SFR register in Table 41 is used to control the SPI interface.

Rev. A | Page 64 of 108

ADuC845/ADuC847/ADuC848

SPICON—SPI Control Register

SFR Address:

Power-On Default:

Bit Addressable:

F8H

05H

Yes

Table 41. SPICON SFR Bit Designations

Bit No.

Name

Description

7

ISPI

SPI Interrupt Bit.

Set by the MicroConverter at the end of each SPI transfer.

Cleared directly by user code or indirectly by reading the SPIDAT SFR.

Write Collision Error Bit.

Set by the MicroConverter if SPIDAT is written to while an SPI transfer is in progress.

Cleared by user code.

6

WCOL

SPE

5

SPI Interface Enable Bit.

Set by user code to enable SPI functionality.

Cleared by user code to enable standard Port 2 functionality.

SPI Master/Slave Mode Select Bit.

4

SPIM

Set by user code to enable master mode operation (SCLOCK is an output).

Cleared by user code to enable slave mode operation (SCLOCK is an input).

Clock Polarity Bit.

Set by user code to enable SCLOCK idle high.

Cleared by user code to enable SCLOCK idle low.

Clock Phase Select Bit.

3

CPOL¹

CPHA¹

2

Set by user code if the leading SCLOCK edge is to transmit data.

Cleared by user code if the trailing SCLOCK edge is to transmit data.

1, 0

SPR1, SPR0 SPI Bit-Rate Bits.

SPR1

SPR0

Selected Bit Rate

f_core/2

f_core/4

f_core/8

f_core/16

0

1

0

1

0

1

¹The CPOL and CPHA bits should both contain the same values for master and slave devices.

Note that both SPI and I²C use the same ISR (Vector Address 3BH); therefore, when using SPI and I²C simultaneously, it is necessary to

check the interfaces following an interrupt to determine which one caused the interrupt.

SPIDAT: SPI Data Register

SFR Address:

Power-On Default:

Bit Addressable:

7FH

00H

No

Rev. A | Page 65 of 108

ADuC845/ADuC847/ADuC848

SPI Interface—Master Mode

USING THE SPI INTERFACE

In master mode, the SCLOCK pin is always an output and

generates a burst of eight clocks whenever user code writes to

the SPIDAT register. The SCLOCK bit rate is determined by

Depending on the configuration of the bits in the SPICON

SFR shown in Table 41, the SPI interface transmits or receives

data in a number of possible modes. Figure 46 shows all

possible ADuC845/ADuC847/ADuC848 SPI configurations

and the timing relationships and synchronization among the

signals involved. Also shown in this figure is the SPI interrupt

bit (ISPI) and how it is triggered at the end of each byte-wide

communication.

SPR0 and SPR1 in SPICON. Also note that the pin is not

SS

used in master mode. If the parts need to assert the pin on an

SS

external slave device, a port digital output pin should be used.

In master mode, a byte transmission or reception is initiated by

a byte write to SPIDAT. The hardware automatically generates

eight clock periods via the SCLOCK pin, and the data is

transmitted via MOSI. With each SCLOCK period, a data bit is

also sampled via MISO. After eight clocks, the transmitted byte

is completely transmitted (via MOSI), and the input byte (if

required) is waiting in the input shift register (after being

received via MISO). The ISPI flag is set automatically, and an

interrupt occurs if enabled. The value in the input shift register

is latched into SPIDAT.

SCLOCK

(CPOL = 1)

SCLOCK

(CPOL = 0)

SS

SAMPLE INPUT

?

MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB

DATA OUTPUT

(CPHA = 1)

SPI Interface—Slave Mode

In slave mode, the SCLOCK is an input. The pin must also be

SS

ISPI FLAG

driven low externally during the byte communication. Trans-

mission is also initiated by a write to SPIDAT. In slave mode, a

data bit is transmitted via MISO, and a data bit is received via

MOSI through each input SCLOCK period. After eight clocks,

the transmitted byte is completely transmitted, and the input

byte is waiting in the input shift register. The ISPI flag is set

automatically, and an interrupt occurs, if enabled. The value in

the shift register is latched into SPIDAT only when the trans-

mission/reception of a byte has been completed. The end of

transmission occurs after the eighth clock has been received if

SAMPLE INPUT

DATA OUTPUT

MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB

(CPHA = 0)

ISPI FLAG

Figure 46. SPI Timing, All Modes

CPHA = 1, or when returns high if CPHA = 0.

SS

Rev. A | Page 66 of 108

ADuC845/ADuC847/ADuC848

DPCON—Data Pointer Control SFR

DUAL DATA POINTERS

The parts incorporate two data pointers. The second data

pointer is a shadow data pointer and is selected via the data

pointer control SFR (DPCON). DPCON features automatic

hardware post-increment and post-decrement as well as an

automatic data pointer toggle.

SFR Address:

Power-On Default:

Bit Addressable:

A7H

00H

No

Table 42. DPCON SFR Bit Designations

Bit No.

Name

Description

7

6

----

DPT

Not Implemented. Write Don’t Care.

Data Pointer Automatic Toggle Enable.

Cleared by the user to disable autoswapping of the DPTR.

Set in user software to enable automatic toggling of the DPTR after each MOVX or MOVC instruction.

5, 4

DP1m1, DP1m0 Shadow Data Pointer Mode. These bits enable extra modes of the shadow data pointer operation, allowing

more compact and more efficient code size and execution.

DP1m1 DP1m0 Behavior of the Shadow Data Pointer

0

1

0

1

0

1

8052 behavior.

DPTR is post-incremented after a MOVX or a MOVC instruction.

DPTR is post-decremented after a MOVX or MOVC instruction.

DPTR LSB is toggled after a MOVX or MOVC instruction. (This instruction can be useful for

moving 8-bit blocks to/from 16-bit devices.)

3, 2

DP0m1, DP0m0 Main Data Pointer Mode. These bits enable extra modes of the main data pointer operation, allowing more

compact and more efficient code size and execution.

DP0m1 DP0m0 Behavior of the Main Data Pointer

0

1

0

1

0

1

8052 behavior.

DPTR is post-incremented after a MOVX or a MOVC instruction.

DPTR is post-decremented after a MOVX or MOVC instruction.

DPTR LSB is toggled after a MOVX or MOVC instruction. (This instruction is useful for

moving 8-bit blocks to/from 16-bit devices.)

1

0

----

DPSEL

Not Implemented. Write Don’t Care.

Data Pointer Select.

Cleared by the user to select the main data pointer. This means that the contents of this 24-bit register are

placed into the DPL, DPH, and DPP SFRs.

Set by the user to select the shadow data pointer. This means that the contents of a separate 24-bit register

appear in the DPL, DPH, and DPP SFRs.

Note the following:

MOV DPTR,#0

;Main DPTR = 0

•

The Dual Data Pointer section is the only place in which

main and shadow data pointers are distinguished.

Whenever the DPTR is mentioned elsewhere in this data

sheet, active DPTR is implied.

MOV DPCON,#55H

;Select shadow DPTR

;DPTR1 increment mode

;DPTR0 increment mode

;DPTR auto toggling ON

•

Only the MOVC/MOVX @DPTR instructions

automatically post-increment and post-decrement the

DPTR. Other MOVC/MOVX instructions, such as MOVC

PC or MOVC @Ri, do not cause the DPTR to automatically

post-increment and post-decrement.

MOV DPTR,#0D000H ;DPTR = D000H

MOVELOOP: CLR A

MOVC A,@A+DPTR

;Get data

;Post Inc DPTR

;Swap to Main DPTR(Data)

;Put ACC in XRAM

MOVX @DPTR,A

To illustrate the operation of DPCON, the following code copies

256 bytes of code memory at Address D000H into XRAM,

starting from Address 0000H.

;Increment main DPTR

;Swap Shadow DPTR(Code)

MOV A, DPL

JNZ MOVELOOP

Rev. A | Page 67 of 108

ADuC845/ADuC847/ADuC848

safe supply level is well established. The supply monitor is also

protected against spurious glitches triggering the interrupt

circuit.

POWER SUPPLY MONITOR

The power supply monitor, once enabled, monitors the DV_DD

and AV_DDsupplies on the parts. It indicates when any of the

supply pins drop below one of four user-selectable voltage trip

points from 2.63 V to 4.63 V. For correct operation of the power

supply monitor function, AV_DDmust be equal to or greater than

2.63 V. Monitor function is controlled via the PSMCON SFR. If

enabled via the IEIP2 SFR, the monitor interrupts the core by

using the PSMI bit in the PSMCON SFR. This bit is not cleared

until the failing power supply returns above the trip point for at

least 250 ms.

Note that the 5 V part has an internal POR trip level of 4.63 V,

which means that there are no usable DV_DDPSM trip levels on

the 5 V part. The 3 V part has a POR trip level of 2.63 V

following a reset and initialization sequence, allowing all

relevant PSM trip points to be used.

PSMCON—Power Supply Monitor Control Register

SFR Address:

Power-On Default:

Bit Addressable:

DFH

DEH

No

The monitor function allows the user to save working registers

to avoid possible data loss due to the low supply condition, and

also ensures that normal code execution does not resume until a

Table 43. PSMCON SFR Bit Designations

Bit No.

Name

Description

7

CMPD

DV_DDComparator Bit.

This read-only bit directly reflects the state of the DV_DDcomparator.

Read 1 indicates that the DV_DDsupply is above its selected trip point.

Read 0 indicates that the DV_DDsupply is below its selected trip point.

AV_DDComparator Bit.

This read-only bit directly reflects the state of the AV_DDcomparator.

Read 1 indicates that the AV_DDsupply is above its selected trip point.

Read 0 indicates that the AV_DDsupply is below its selected trip point.

Power Supply Monitor Interrupt Bit.

6

5

CMPA

PSMI

Set high by the MicroConverter if either CMPA or CMPD is low, indicating low analog or digital supply. The PSMI

bit can be used to interrupt the processor. Once CMPD and/or CMPA returns (and remains) high, a 250 ms

counter is started. When this counter times out, the PSMI interrupt is cleared. PSMI can also be written by the

user. However, if either comparator output is low, it is not possible for the user to clear PSMI.

4, 3

TPD1, TPD0

DV_DDTrip Point Selection Bits.

A 5 V part has no valid PSM trip points. If the DV_DDsupply falls below the 4.63 V point, the part resets (POR). For a

3 V part, all relevant PSM trip points are valid. The 3 V POR trip point is 2.63 V (fixed).

These bits select the DV_DDtrip point voltage as follows:

TPD1 TPD0

Selected DV_DDTrip Point (V)

0

1

0

1

0

1

4.63

3.08

2.93

2.63

2, 1

TPA1, TPA0

PSMEN

AV_DDTrip Point Selection Bits. These bits select the AV_DDtrip point voltage as follows:

TPA1 TPA0

Selected AV_DDTrip Point (V)

0

1

0

1

0

1

4.63

3.08

2.93

2.63

0

Power Supply Monitor Enable Bit.

Set to 1 by the user to enable the power supply monitor circuit.

Cleared to 0 by the user to disable the power supply monitor circuit.

Rev. A | Page 68 of 108

ADuC845/ADuC847/ADuC848

is clocked from the 32 kHz external crystal connected between

the XTAL1 and XTAL2 pins. The WDCOM SFR can be written

only by user software if the double write sequence described in

WDWR is initiated on every write access to the WDCON SFR.

WATCHDOG TIMER

The watchdog timer generates a device reset or interrupt within a

reasonable amount of time if the ADuC845/ADuC847/

ADuC848 enters an erroneous state, possibly due to a program-

ming error or electrical noise. The watchdog function can be

disabled by clearing the WDE (watchdog enable) bit in the

watchdog control (WDCON) SFR. When enabled, the watchdog

circuit generates a system reset or interrupt (WDS) if the user

program fails to set the WDE bit within a predetermined amount

of time (see the PRE3…0 bits in Table 44). The watchdog timer

WDCON—Watchdog Control Register

SFR Address:

Power-On Default:

Bit Addressable:

C0H

10H

Yes

Table 44. WDCON SFR Bit Designations

Bit No.

Name

Description

7, 6, 5, 4

PRE3, PRE2, PRE1, PRE0 Watchdog Timer Prescale Bits.

The watchdog timeout period is given by the equation

t_WD= (2^PREꢀ (2⁹/ f_XTAL)) (0 ≤ PRE ≤ 7; f_XTAL= 32.768 kHz)

PRE3

PRE2

PRE1

PRE0

Timeout Period (ms)

Action

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

15.6

31.2

62.5

125

250

500

1000

2000

0.0

Reset or interrupt

Immediate reset

Reserved. Not a valid selection.

PRE3–0 > 1000b

Watchdog Interrupt Response Enable Bit.

3

WDIR

If this bit is set by the user, the watchdog generates an interrupt response instead of a system reset

when the watchdog timeout period expires. This interrupt is not disabled by the CLR EA instruction,

and it is also a fixed, high priority interrupt. If the watchdog timer is not being used to monitor the

system, it can be used alternatively as a timer. The prescaler is used to set the timeout period in

which an interrupt is generated.

2

1

WDS

WDE

Watchdog Status Bit.

Set by the watchdog controller to indicate that a watchdog timeout has occurred.

Cleared by writing a 0 or by an external hardware reset. It is not cleared by a watchdog reset.

Watchdog Enable Bit.

Set by the user to enable the watchdog and clear its counters. If this bit is not set by the user within

the watchdog timeout period, the watchdog timer generates a reset or interrupt, depending on

WDIR.

Cleared under the following conditions: user writes 0; watchdog reset (WDIR = 0); hardware reset;

PSM interrupt.

0

WDWR

Watchdog Write Enable Bit.

Writing data to the WDCON SFR involves a double instruction sequence. Global interrupts must first

be disabled. The WDWR bit is set with the very next instruction, a write to the WDCON SFR. For

example:

CLR EA

SETB WDWR

;Disable Interrupts while configuring to WDT

;Allow Write to WDCON

MOV WDCON, #72H ;Enable WDT for 2.0s timeout

SETB EA ;Enable Interrupts again (if required)

Rev. A | Page 69 of 108

ADuC845/ADuC847/ADuC848

Because the TIC is clocked directly from a 32 kHz external

crystal on the parts, instructions that access the TIC registers

are also clocked at 32 kHz (not at the core frequency). The user

must ensure that sufficient time is given for these instructions

to execute.

TIME INTERVAL COUNTER (TIC)

A TIC is provided on-chip for counting longer intervals than

the standard 8051 compatible timers can count. The TIC is

capable of timeout intervals ranging from 1/128 second to 255

hours. Also, this counter is clocked by the external 32.768 kHz

crystal rather than by the core clock, and it can remain active in

power-down mode and time long power-down intervals. This

has obvious applications for remote battery-powered sensors

where regular widely spaced readings are required. Note that

instructions to the TIC SFRs are also clocked at 32.768 kHz, so

sufficient time must be allowed in user code for these instructions

to execute.

TCEN

32.768kHz EXTERNAL CRYSTAL

ITS0 ITS1

8-BIT

PRESCALER

HUNDREDTHS COUNTER

HTHSEC

INTERVAL

TIMEBASE

SELECTION

MUX

Six SFRs are associated with the time interval counter, TIMECON

being its control register. Depending on the configuration of the

IT0 and IT1 bits in TIMECON, the selected time counter register

overflow clocks the interval counter. When this counter is equal

to the time interval value loaded in the INTVAL SFR, the TII bit

(TIMECON.2) is set and generates an interrupt, if enabled. If

the part is in power-down mode, again with TIC interrupt

enabled, the TII bit wakes up the device and resumes code

execution by vectoring directly to the TIC interrupt service

vector address at 0053H. The TIC-related SFRs are described in

Table 45. Note also that the time based SFRs can be written

initially with the current time; the TIC can then be controlled

and accessed by user software. In effect, this facilitates the

implementation of a real-time clock. A basic block diagram of

the TIC is shown in Figure 47.

TIEN

SECOND COUNTER

SEC

MINUTE COUNTER

MIN

HOUR COUNTER

HOUR

8-BIT

INTERVAL COUNTER

INTERVAL TIMEOUT

TIME INTERVAL COUNTER INTERRUPT

EQUAL?

INTVAL SFR

Figure 47. TIC Simplified Block Diagram

Rev. A | Page 70 of 108

ADuC845/ADuC847/ADuC848

TIMECON—TIC Control Register

SFR Address:

Power-On Default:

Bit Addressable:

A1H

00H

No

Table 45. TIMECON SFR Bit Designations

Bit No.

Name

Description

7

6

----

TFH

Not Implemented. Write Don’t Care.

Twenty-Four Hour Select Bit.

Set by the user to enable the hour counter to count from 0 to 23.

Cleared by the user to enable the hour counter to count from 0 to 255.

Interval Timebase Selection Bits.

5, 4

ITS1, ITS0

ITS1 ITS0

Interval Timebase

1/128 Second

Seconds

Minutes

Hours

0

1

0

1

0

1

3

ST1

Single Time Interval Bit.

Set by the user to generate a single interval timeout. If set, a timeout clears the TIEN bit.

Cleared by the user to allow the interval counter to be automatically reloaded and start counting again at each

interval timeout.

2

1

0

TII

TIC Interrupt Bit.

Set when the 8-bit interval counter matches the value in the INTVAL SFR.

Cleared by user software.

Time Interval Enable Bit.

Set by the user to enable the 8-bit time interval counter.

Cleared by the user to disable the interval counter.

Time Clock Enable Bit.

TIEN

TCEN

Set by the user to enable the time clock to the time interval counters.

Cleared by the user to disable the clock to the time interval counters and reset the time interval SFRs to the last

value written to them by the user. The time registers (HTHSEC, SEC, MIN, and HOUR) can be written while TCEN is

low.

Rev. A | Page 71 of 108

ADuC845/ADuC847/ADuC848

INTVAL—User Timer Interval Select Register

Function:

User code writes the required time interval to this register. When the 8-bit interval counter is equal to the time interval

value loaded in the INTVAL SFR, the TII bit (TIMECON.2) is set and generates an interrupt, if enabled.

SFR Address:

A6H

Power-On Default:

Bit Addressable:

Valid Value:

00H

No

0 to 255 decimal

HTHSEC—Hundredths of Seconds Time Register

Function:

This register is incremented in 1/128-second intervals once TCEN in TIMECON is active. The HTHSEC SFR counts

from 0 to 127 before rolling over to increment the SEC time register.

SFR Address:

A2H

Power-On Default:

Bit Addressable:

Valid Value:

00H

No

0 to 127 decimal

SEC—Seconds Time Register

Function:

This register is incremented in 1-second intervals once TCEN in TIMECON is active. The SEC SFR counts from 0 to 59

before rolling over to increment the MIN time register.

SFR Address:

A3H

Power-On Default:

Bit Addressable:

Valid Value:

00H

No

0 to 59 decimal

MIN—Minutes Time Register

Function

This register is incremented in 1-minute intervals once TCEN in TIMECON is active. The MIN SFR counts from 0 to 59

before rolling over to increment the HOUR time register.

SFR Address:

A4H

Power-On Default:

Bit Addressable:

Valid Value:

00H

No

0 to 59 decimal

HOUR—Hours Time Register

Function:

This register is incremented in 1-hour intervals once TCEN in TIMECON is active. The HOUR SFR counts from 0 to 23

before rolling over to 0.

SFR Address:

A5H

Power-On Default:

Bit Addressable:

Valid Value:

00H

No

0 to 23 decimal

To enable the TIC as a real-time clock, the HOUR, MIN, SEC, and HTHSEC registers can be loaded with the current time. Once the

TCEN bit is high, the TIC starts. To use the TIC as a time interval counter, select the count interval—hundredths of seconds, seconds,

minutes, and hours via the ITS0 and ITS1 bits in the TIMECON SFR. Load the count required into the INTVAL SFR.

Note that INTVAL is only an 8-bit register, so user software must take into account any intervals longer than are possible with 8 bits.

Therefore, to count an interval of 20 seconds, use the following procedure:

MOV TIMECON, #0D0H ;Enable 24Hour mode, count seconds, Clear TCEN.

MOV INTVAL, #14H ;Load INTVAL with required count interval...in this case 14H = 20

MOV TIMECON, #0D3H ;Start TIC counting and enable the 8bit INTVAL counter.

Rev. A | Page 72 of 108

ADuC845/ADuC847/ADuC848

In general-purpose I/O port mode, Port 0 pins that have 1s

written to them via the Port 0 SFR are configured as open-drain

and, therefore, float. In this state, Port 0 pins can be used as high

impedance inputs. This is represented in Figure 48 by the NAND

gate whose output remains high as long as the control signal is

low, thereby disabling the top FET. External pull-up resistors

are, therefore, required when Port 0 pins are used as general-

purpose outputs. Port 0 pins with 0s written to them drive a

logic low output voltage (V_OL) and are capable of sinking 1.6 mA.

8052 COMPATIBLE ON-CHIP PERIPHERALS

This section gives a brief overview of the various secondary

peripheral circuits that are available to the user on-chip. These

features are mostly 8052 compatible (with a few additional

features) and are controlled via standard 8052 SFR bit definitions.

Parallel I/O

The ADuC845/ADuC847/ADuC848 use four input/output

ports to exchange data with external devices. In addition to

performing general-purpose I/O, some are capable of external

memory operations, while others are multiplexed with alternate

functions for the peripheral functions available on-chip. In

general, when a peripheral is enabled, that pin cannot be used as

a general-purpose I/O pin.

Port 1

Port 1 is also an 8-bit port directly controlled via the P1 SFR

(90H). Port 1 digital output capability is not supported on this

device. Port 1 pins can be configured as digital inputs or analog

inputs. By (power-on) default, these pins are configured as

analog inputs, that is, 1 is written to the corresponding Port 1

register bit. To configure any of these pins as digital inputs, the

user should write a 0 to these port bits to configure the corre-

sponding pin as a high impedance digital input. These pins also

have various secondary functions aside from their analog input

capability, as described in Table 46.

Port 0

Port 0 is an 8-bit open-drain bidirectional I/O port that is

directly controlled via the Port 0 SFR (80H). Port 0 is also the

multiplexed low-order address and data bus during accesses to

external data memory.

Figure 48 shows a typical bit latch and I/O buffer for a Port 0

pin. The bit latch (one bit in the port’s SFR) is represented as a

Type D flip-flop, which clocks in a value from the internal bus

in response to a write to latch signal from the CPU. The

Q output of the flip-flop is placed on the internal bus in

response to a read latch signal from the CPU. The level of the

port pin itself is placed on the internal bus in response to a read

pin signal from the CPU. Some instructions that read a port

activate the read latch signal, and others activate the read pin

signal. See the Read-Modify-Write Instructions section for

details.

Table 46. Port 1 Alternate Functions

Pin No. Alternate Function

P1.2

P1.3

P1.6

P1.7

REFIN2+ (second reference input, +’ve)

REFIN2− (second reference input, –‘ve)

IEXC1 (200 µA excitation current source)

IEXC2 (200 µA excitation current source)

READ

LATCH

INTERNAL

BUS

D

Q

WRITE

TO LATCH

ADDR/DATA

CONTROL

DV

DD

CL

LATCH

READ

P1.x

READ

LATCH

TO ADC

P0.x

INTERNAL

BUS

Figure 49. Port 1 Bit Latch and I/O Buffer

D

Q

Port 2

WRITE

TO LATCH

CL

Port 2 is a bidirectional port with internal pull-up resistors

directly controlled via the P2 SFR. Port 2 also emits the middle-

and high-order address bytes during accesses to the 24-bit

external data memory space.

LATCH

READ

Figure 48. Port 0 Bit Latch and I/O Buffer

In general-purpose I/O port mode, Port 2 pins that have 1s

written to them are pulled high by the internal pull-ups as

shown in Figure 50 and, in that state, can be used as inputs. As

inputs, Port 2 pins pulled externally low source current because

of the internal pull-up resistors. Port 2 pins with 0s written to

them drive a logic low output voltage (V_OL) and are capable of

sinking 1.6 mA.

As shown in Figure 48, the output drivers of Port 0 pins are

switchable to an internal ADDR and ADDR/DATA bus by an

internal control signal for use in external memory accesses.

During external memory accesses, the P0 SFR has 1s written to

it; therefore, all its bit latches become 1. When accessing

external memory, the control signal in Figure 48 goes high,

enabling push-pull operation of the output pin from the internal

address or data bus (ADDR/DATA line). Therefore, no external

pull-ups are required on Port 0 for it to access external memory.

Rev. A | Page 73 of 108

ADuC845/ADuC847/ADuC848

DV

DD

P2.5 and P2.6 can also be used as PWM outputs, while P2.7 can

act as an alternate PWM clock source. When selected as the

PWM outputs, they overwrite anything written to P2.5 or P2.6.

ALTERNATE

OUTPUT

FUNCTION

INTERNAL

PULL-UP

READ

LATCH

P3.x

Table 47. Port 2 Alternate Functions

Pin No. Alternate Function

INTERNAL

BUS

D

Q

WRITE

TO LATCH

CL

P2.0

P2.1

P2.2

P2.3

P2.4

P2.5

P2.6

P2.7

SCLOCK for SPI

MOSI for SPI

MISO for SPI

SS and T2 clock input

T2EX alternate control for T2

PWM0 output

LATCH

READ

ALTERNATE

INPUT

FUNCTION

Figure 51. Port 3 Bit Latch and I/O Buffer

PWM1 output

PWMCLK

Read-Modify-Write Instructions

Some 8051 instructions read the latch while others read the pin.

The instructions that read the latch rather than the pins are the

ones that read a value, possibly change it, and rewrite it to the

latch. These are called read-modify-write instructions, which

are listed in Table 49. When the destination operand is a port or

a port bit, these instructions read the latch rather than the pin.

ADDR

READ

LATCH

DV

DD

DV

DD

CONTROL

INTERNAL

PULL-UP

INTERNAL

BUS

D

Q

P2.x

WRITE

TO LATCH

Table 49. Read-Modify-Write Instructions

CL

LATCH

Instruction

Description

READ

ANL

ORL

XRL

Logical AND, for example, ANL P1, A

Logical OR, for example, ORL P2, A

Logical EX-OR, for example, XRL P3, A

Figure 50. Port 2 Bit Latch and I/O Buffer

Port 3

JBC

Jump if Bit = 1 and clear bit, for example, JBC

P1.1, LABEL

Complement bit, for example, CPL P3.0

Increment, for example, INC P2

Decrement, for example, DEC P2

Decrement and jump if not zero, for example,

DJNZ P3, LABEL

Port 3 is a bidirectional port with internal pull-ups directly

controlled via the P3 SFR (B0H). Port 3 pins that have 1s

written to them are pulled high by the internal pull-ups and, in

that state, can be used as inputs. As inputs, Port 3 pins pulled

externally low source current because of the internal pull-ups.

CPL

INC

DEC

DJNZ

MOV PX.Y, C¹

CLR PX.Y¹

Move Carry to Bit Y of Port X

Clear Bit Y of Port X

Set Bit Y of Port X

Port 3 pins with 0s written to them drive a logic low output

voltage (V_OL) and are capable of sinking 4 mA. Port 3 pins also

have various secondary functions as described in Table 48. The

alternate functions of Port 3 pins can be activated only if the

corresponding bit latch in the P3 SFR contains a 1. Otherwise,

the port pin remains at 0.

SETB PX.Y¹

___________________________________________

¹These instructions read the port byte (all 8 bits), modify the addressed bit,

and write the new byte back to the latch.

Read-modify-write instructions are directed to the latch rather

than to the pin to avoid a possible misinterpretation of the

voltage level of a pin. For example, a port pin might be used to

drive the base of a transistor. When 1 is written to the bit, the

transistor is turned on. If the CPU reads the same port bit at the

pin rather than the latch, it reads the base voltage of the

transistor and interprets it as Logic 0. Reading the latch rather

than the pin returns the correct value of 1.

Table 48. Port 3 Alternate Functions

Pin No. Alternate Function

P3.0

P3.1

P3.2

P3.3

P3.4

P3.5

P3.6

P3.7

RxD (UART input pin, or serial data I/O in Mode 0)

TxD (UART output pin, or serial clock output in Mode 0)

INT0 (External Interrupt 0)

INT1 (External Interrupt 1)

T0 (Timer/Counter 0 external input)

T1 (Timer/Counter 1 external input)

WR (external data memory write strobe)

RD (external data memory read strobe)

Rev. A | Page 74 of 108

ADuC845/ADuC847/ADuC848

When functioning as a counter, the TLx register is incremented

by a 1-to-0 transition at its corresponding external input pin:

T0, T1, or T2. When the samples show a high in one cycle and a

low in the next cycle, the count is incremented. Because it takes

two machine cycles (two core clock periods) to recognize a

1-to-0 transition, the maximum count rate is half the core clock

frequency.

TIMERS/COUNTERS

The ADuC845/ADuC847/ADuC848 have three 16-bit timer/

counters: Timer 0, Timer 1, and Timer 2. The timer/counter

hardware is included on-chip to relieve the processor core of the

overhead inherent in implementing timer/counter functionality

in software. Each timer/counter consists of two 8-bit registers:

THx and TLx (x = 0, 1, or 2). All three can be configured to

operate either as timers or as event counters.

There are no restrictions on the duty cycle of the external input

signal, but, to ensure that a given level is sampled at least once

before it changes, it must be held for a minimum of one full

machine cycle. User configuration and control of all timer

operating modes is achieved via three SFRs:

When functioning as a timer, the TLx register is incremented

every machine cycle. Thus, one can think of it as counting

machine cycles. Because a machine cycle on a single-cycle core

consists of one core clock period, the maximum count rate is

the core clock frequency.

TMOD, TCON—Control and Configuration for Timers 0 and 1.

T2CON—Control and Configuration for Timer 2.

TMOD—Timer/Counter 0 and 1 Mode Register

SFR Address:

Power-On Default:

Bit Addressable:

89H

00H

No

Table 50. TMOD SFR Bit Designation

Bit No.

Name

Description

7

Gate

Timer 1 Gating Control.

Set by software to enable Timer/Counter 1 only while the INT1 pin is high and the TR1 control is set.

Cleared by software to enable Timer 1 whenever the TR1control bit is set.

Timer 1 Timer or Counter Select Bit.

6

C/T

Set by software to select counter operation (input from T1 pin).

Cleared by software to select the timer operation (input from internal system clock).

Timer 1 Mode Select bits

5, 4

M1, M0

M1

M0

Description

0

1

0

1

0

TH1 operates as an 8-bit timer/counter. TL1 serves as 5-bit prescaler.

16-Bit Timer/Counter. TH1 and TL1 are cascaded; there is no prescaler.

8-Bit Autoreload Timer/Counter. TH1 holds a value that is to be reloaded into TL1 each time it

overflows.

1

Timer/Counter 1 Stopped.

3

Gate

C/T

Timer 0 Gating Control.

Set by software to enable Timer/Counter 0 only while the INT0 pin is high and the TR0 control bit is set.

Cleared by software to enable Timer 0 whenever the TR0 control bit is set.

Timer 0 Timer or Counter Select Bit.

2

Set by software to the select counter operation (input from T0 pin).

Cleared by software to the select timer operation (input from internal system clock).

Timer 0 Mode Select Bits

1, 0

M1, M0

M1

0

M0

0

1

Description

TH0 operates as an 8-bit timer/counter. TL0 serves as a 5-bit prescaler.

16-Bit Timer/Counter. TH0 and TL0 are cascaded; there is no prescaler.

1

0

8-Bit Autoreload Timer/Counter. TH0 holds a value that is to be reloaded into TL0 each time it

overflows.

1

TL0 is an 8-bit timer/counter controlled by the standard Timer 0 control bits.

TH0 is an 8-bit timer only, controlled by Timer 1 control bits.

Rev. A | Page 75 of 108

ADuC845/ADuC847/ADuC848

TCON—Timer/Counter 0 and 1 Control Register

SFR Address:

Power-On Default:

Bit Addressable:

88H

00H

Yes

Table 51. TCON SFR Bit Designations

Bit No.

Name

Description

7

TF1

Timer 1 Overflow Flag.

Set by hardware on a Timer/Counter 1 overflow.

Cleared by hardware when the program counter (PC) vectors to the interrupt service routine.

Timer 1 Run Control Bit.

Set by the user to turn on Timer/Counter 1.

Cleared by the user to turn off Timer/Counter 1.

Timer 0 Overflow Flag.

Set by hardware on a Timer/Counter 0 overflow.

Cleared by hardware when the PC vectors to the interrupt service routine.

Timer 0 Run Control Bit.

Set by the user to turn on Timer/Counter 0.

Cleared by the user to turn off Timer/Counter 0.

External Interrupt 1 (INT1) Flag.

6

5

4

3

TR1

TF0

TR0

IE1¹

Set by hardware by a falling edge or by a zero level applied to the external interrupt pin, INT1, depending on the

state of Bit IT1.

Cleared by hardware when the PC vectors to the interrupt service routine only if the interrupt was transition-

activated. If level-activated, the external requesting source controls the request flag rather than the on-chip

hardware.

2

1

IT1¹

IE0¹

External Interrupt 1 (IE1) Trigger Type.

Set by software to specify edge-sensitive detection, that is, 1-to-0 transition.

Cleared by software to specify level-sensitive detection, that is, zero level.

External Interrupt 0 (INT0) Flag.

Set by hardware by a falling edge or by a zero level being applied to the external interrupt pin, INT0, depending on

the statue of Bit IT0.

Cleared by hardware when the PC vectors to the interrupt service routine only if the interrupt was transition-

activated. If level-activated, the external requesting source controls the request flag rather than the on-chip

hardware.

0

IT0¹

External Interrupt 0 (IE0) Trigger Type.

Set by software to specify edge-sensitive detection, that is, 1-to-0 transition.

Cleared by software to specify level-sensitive detection, that is, zero level.

___________________________________________

1

INT0

INT1

interrupt pins.

These bits are not used to control Timer/Counters 0 and 1, but are used instead to control and monitor the external

and

Timer/Counter 0 and 1 Data Registers

Each timer consists of two 8-bit registers. These can be used as independent registers or combined into a single 16-bit register, depending

on the timers’ mode configuration.

TH0 and TL0—Timer 0 high and low bytes.

SFR Address:

Power-On Default:

8CH and 8AH, respectively.

00H and 00H, respectively.

TH1 and TL1—Timer 1 high and low bytes.

SFR Address:

Power-On Default:

8DH and 8BH, respectively.

00H and 00H, respectively

Rev. A | Page 76 of 108

ADuC845/ADuC847/ADuC848

Timer/Counter 0 and 1 Operating Modes

Mode 2 (8-Bit Timer/Counter with Autoreload)

This section describes the operating modes for Timer/Counters

0 and 1. Unless otherwise noted, these modes of operation are

the same for both Timer 0 and Timer 1.

Mode 2 configures the timer register as an 8-bit counter (TL0)

with automatic reload as shown in Figure 54. Overflow from

TL0 not only sets TF0, but also reloads TL0 with the contents of

TH0, which is preset by software. The reload leaves TH0

unchanged.

Mode 0 (13-Bit Timer/Counter)

Mode 0 configures an 8-bit timer/counter. Figure 52 shows

Mode 0 operation. Note that the divide-by-12 prescaler is not

present on the single-cycle core.

CORE

CLK*

C/T = 0

INTERRUPT

TL0

TF0

(8 BITS)

CORE

CLK*

C/T = 1

P3.4/T0

C/T = 0

INTERRUPT

CONTROL

TR0

TL0

TH0

TF0

(5 BITS) (8 BITS)

C/T = 1

P3.4/T0

RELOAD

GATE

TH0

CONTROL

(8 BITS)

P3.2/INT0

TR0

*

THE CORE CLOCK IS THE OUTPUT OF THE PLL (SEE THE ON-CHIP PLL SECTION)

GATE

Figure 54. Timer/Counter 0, Mode 2

P3.2/INT0

Mode 3 (Two 8-Bit Timer/Counters)

*

THE CORE CLOCK IS THE OUTPUT OF THE PLL (SEE THE ON-CHIP PLL SECTION)

Mode 3 has different effects on Timer 0 and Timer 1. Timer 1 in

Mode 3 simply holds its count. The effect is the same as setting

TR1 = 0. Timer 0 in Mode 3 establishes TL0 and TH0 as two

separate counters. This configuration is shown in Figure 55. TL0

Figure 52. Timer/Counter 0, Mode 0

In this mode, the timer register is configured as a 13-bit register.

As the count rolls over from all 1s to all 0s, it sets the timer

overflow flag, TF0. TF0 can then be used to request an interrupt.

The counted input is enabled to the timer when TR0 = 1 and

uses the Timer 0 control bits C/ , Gate, TR0,

, and TF0.

T

INT0

TH0 is locked into a timer function (counting machine cycles)

and takes over the use of TR1 and TF1 from Timer 1. Therefore,

TH0 then controls the Timer 1 interrupt. Mode 3 is provided

for applications requiring an extra 8-bit timer or counter.

either Gate = 0 or

= 1. Setting Gate = 1 allows the timer to

INT0

be controlled by external input

to facilitate pulse-width

INT0

measurements. TR0 is a control bit in the special function

register TCON; Gate is in TMOD. The 13-bit register consists of

all 8 bits of TH0 and the lower 5 bits of TL0. The upper 3 bits of

TL0 are indeterminate and should be ignored. Setting the run

flag (TR0) does not clear the registers.

When Timer 0 is in Mode 3, Timer 1 can be turned on and off

by switching it out of and into its own Mode 3, or it can still be

used by the serial interface as a baud rate generator. In fact, it

can be used in any application not requiring an interrupt from

Timer 1 itself.

Mode 1 (16-Bit Timer/Counter)

Mode 1 is the same as Mode 0 except that the Mode 1 timer

register runs with all 16 bits. Mode 1 is shown in Figure 53.

CORE

CLK/12

CORE

CLK*

C/T = 0

C/T = 1

INTERRUPT

TL0

(8 BITS)

TF0

CORE

CLK*

C/T = 0

INTERRUPT

P3.4/T0

TL0

TH0

TF0

(8 BITS) (8 BITS)

CONTROL

TR0

C/T = 1

P3.4/T0

CONTROL

GATE

TR0

P3.2/INT0

GATE

INTERRUPT

P3.2/INT0

TH0

(8 BITS)

CORE

CLK/12

TF1

*

THE CORE CLOCK IS THE OUTPUT OF THE PLL (SEE THE ON-CHIP PLL SECTION)

TR1

Figure 53. Timer/Counter 0, Mode 1

*

THE CORE CLOCK IS THE OUTPUT OF THE PLL (SEE THE ON-CHIP PLL SECTION)

Figure 55. Timer/Counter 0, Mode 3

Rev. A | Page 77 of 108

ADuC845/ADuC847/ADuC848

T2CON—Timer/Counter 2 Control Register

SFR Address:

Power-On Default:

Bit Addressable:

C8H

00H

Yes

Table 52. T2CON SFR Bit Designations

Bit No.

Name Description

7

TF2

Timer 2 Overflow Flag.

Set by hardware on a Timer 2 overflow. TF2 cannot be set when either RCLK = 1 or TCLK = 1.

Cleared by user software.

6

5

4

3

EXF2

RCLK

TCLK

Timer 2 External Flag.

Set by hardware when either a capture or reload is caused by a negative transition on T2EX and EXEN2 = 1.

Cleared by user software.

Receive Clock Enable Bit.

Set by the user to enable the serial port to use Timer 2 overflow pulses for its receive clock in serial port Modes 1 and 3.

Cleared by the user to enable Timer 1 overflow to be used for the receive clock.

Transmit Clock Enable Bit.

Set by the user to enable the serial port to use Timer 2 overflow pulses for its transmit clock in serial port Modes 1 and 3.

Cleared by the user to enable Timer 1 overflow to be used for the transmit clock.

EXEN2 Timer 2 External Enable Flag.

Set by the user to enable a capture or reload to occur as a result of a negative transition on T2EX if Timer 2 is not being

used to clock the serial port.

Cleared by the user for Timer 2 to ignore events at T2EX.

Timer 2 Start/Stop Control Bit.

Set by the user to start Timer 2.

2

1

0

TR2

Cleared by the user to stop Timer 2.

CNT2

CAP2

Timer 2 Timer or Counter Function Select Bit.

Set by the user to select the counter function (input from external T2 pin).

Cleared by the user to select the timer function (input from on-chip core clock).

Timer 2 Capture/Reload Select Bit.

Set by the user to enable captures on negative transitions at T2EX if EXEN2 = 1.

Cleared by the user to enable autoreloads with Timer 2 overflows or negative transitions at T2EX when EXEN2 = 1.

When either RCLK = 1 or TCLK = 1, this bit is ignored and the timer is forced to autoreload on Timer 2 overflow.

Timer/Counter 2 Data Registers

Timer/Counter 2 also has two pairs of 8-bit data registers

associated with it. These are used as both timer data registers

and as timer capture/reload registers.

TH2 and TL2—Timer 2 data high byte and low byte.

SFR Address:

Power-On Default:

CDH and CCH respectively.

00H and 00H, respectively.

RCAP2H and RCAP2L—Timer 2 capture/reload byte and low

byte.

SFR Address:

Power-On Default:

CBH and CAH, respectively.

00H and 00H, respectively.

Rev. A | Page 78 of 108

ADuC845/ADuC847/ADuC848

Timer/Counter 2 Operating Modes

16-Bit Capture Mode

The following sections describe the operating modes for

Timer/Counter 2. The operating modes are selected by bits in

the T2CON SFR as shown in Table 53.

Capture mode has two options that are selected by Bit EXEN2

in T2CON. If EXEN2 = 0, Timer 2 is a 16-bit timer or counter

that, upon overflowing, sets bit TF2, the Timer 2 overflow bit,

which can be used to generate an interrupt. If EXEN2 = 1,

Timer 2 still performs the above, but a l-to-0 transition on

external input T2EX causes the current value in the Timer 2

registers, TL2 and TH2, to be captured into registers RCAP2L

and RCAP2H, respectively. In addition, the transition at T2EX

causes bit EXF2 in T2CON to be set, and EXF2, like TF2, can

generate an interrupt. Capture mode is shown in Figure 57. The

baud rate generator mode is selected by RCLK = 1 and/or

TCLK = 1.

Table 53. T2CON Operating Modes

RCLK (or) TCLK

CAP2

TR2

Mode

0

1

X

0

1

X

1

0

16-Bit Autoreload

16-Bit Capture

Baud Rate

Off

16-Bit Autoreload Mode

Autoreload mode has two options that are selected by bit

EXEN2 in T2CON. If EXEN2 = 0, when Timer 2 rolls over, it

not only sets TF2 but also causes the Timer 2 registers to be

reloaded with the 16-bit value in registers RCAP2L and

RCAP2H, which are preset by software. If EXEN2 = 1, Timer 2

still performs the above, but with the added feature that a 1-to-0

transition at external input T2EX also triggers the 16-bit reload

and sets EXF2. Autoreload mode is shown in Figure 56.

In either case, if Timer 2 is used to generate the baud rate, the

TF2 interrupt flag does not occur. Therefore, Timer 2 interrupts

do not occur, so they do not have to be disabled. In this mode,

the EXF2 flag can, however, still cause interrupts, which can be

used as a third external interrupt. Baud rate generation is

described as part of the UART serial port operation in the

following section.

CORE

CLK*

C/T2 = 0

C/T2 = 1

TL2

(8 BITS)

TH2

(8 BITS)

T2

CONTROL

RELOAD

TR2

TRANSITION

DETECTOR

RCAP2L

RCAP2H

TF2

TIMER

INTERRUPT

T2EX

EXF2

CONTROL

EXEN2

*THE CORE CLOCK IS THE OUTPUT OF THE PLL (SEE THE ON-CHIP PLL SECTION)

Figure 56. Timer/Counter 2, 16-Bit Autoreload Mode

CORE

CLK*

C/T2 = 0

C/T2 = 1

TL2

(8 BITS)

TH2

(8 BITS)

TF2

T2

CONTROL

TR2

TIMER

INTERRUPT

CAPTURE

TRANSITION

DETECTOR

RCAP2L

RCAP2H

T2EX

EXF2

CONTROL

EXEN2

THE CORE CLOCK IS THE OUTPUT OF THE PLL (SEE THE ON-CHIP PLL SECTION)

*

Figure 57. Timer/Counter 2, 16-Bit Capture Mode

Rev. A | Page 79 of 108

ADuC845/ADuC847/ADuC848

SBUF SFR

UART SERIAL INTERFACE

Both the serial port receive and transmit registers are accessed

through the SBUF SFR (SFR address = 99H). Writing to SBUF

loads the transmit register, and reading SBUF accesses a

physically separate receive register.

The serial port is full duplex, meaning that it can transmit and

receive simultaneously. It is also receive buffered, meaning that

it can begin receiving a second byte before a previously received

byte is read from the receive register. However, if the first byte is

still not read by the time reception of the second byte is complete,

the first byte is lost. The physical interface to the serial data

network is via Pins RxD(P3.0) and TxD(P3.1), while the SFR

interface to the UART comprises SBUF and SCON, as described

below.

SCON UART—Serial Port Control Register

SFR Address:

Power-On Default:

Bit Addressable:

98H

00H

Yes

Table 54. SCON SFR Bit Designations

Bit No.

Name

Description

7, 6

SM0, SM1

UART Serial Mode Select Bits. These bits select the serial port operating mode as follows:

SM0

SM1

Selected Operating Mode.

0

1

0

1

0

1

Mode 0: Shift register, fixed baud rate (Core_Clk/2).

Mode 1: 8-bit UART, variable baud rate.

Mode 2: 9-bit UART, fixed baud rate (Core_Clk/32) or (Core_Clk/16).

Mode 3: 9-bit UART, variable baud rate.

5

SM2

Multiprocessor Communication Enable Bit.

Enables multiprocessor communication in Modes 2 and 3.

In Mode 0, SM2 should be cleared.

In Mode 1, if SM2 is set, RI is not activated if a valid stop bit was not received. If SM2 is cleared, RI is set as soon as

the byte of data is received.

In Modes 2 or 3, if SM2 is set, RI is not activated if the received ninth data bit in RB8 is 0.

If SM2 is cleared, RI is set as soon as the byte of data is received.

Serial Port Receive Enable Bit.

Set by user software to enable serial port reception.

Serial Port Transmit (Bit 9).

4

3

REN

TB8

The data loaded into TB8 is the ninth data bit transmitted in Modes 2 and 3. Cleared by user software to disable

serial port reception.

2

1

RB8

TI

Serial Port Receiver Bit 9.

The ninth data bit received in Modes 2 and 3 is latched into RB8. For Mode 1, the stop bit is latched into RB8.

Serial Port Transmit Interrupt Flag.

Set by hardware at the end of the eighth bit in Mode 0, or at the beginning of the stop bit in Modes 1, 2, and 3.

TI must be cleared by user software.

0

RI

Serial Port Receive Interrupt Flag.

Set by hardware at the end of the eighth bit in Mode 0, or halfway through the stop bit in Modes 1, 2, and 3.

RI must be cleared by software.

SBUF—UART Serial Port Data Register

SFR Address:

Power-On Default:

Bit Addressable:

99H

00H

No

Rev. A | Page 80 of 108

ADuC845/ADuC847/ADuC848

Mode 0 (8-Bit Shift Register Mode)

All of the following conditions must be met at the time the final

shift pulse is generated:

Mode 0 is selected by clearing both the SM0 and SM1 bits in the

SFR SCON. Serial data enters and exits through RxD. TxD

outputs the shift clock. Eight data bits are transmitted or

received. Transmission is initiated by any instruction that writes

to SBUF. The data is shifted out of the RxD line. The 8 bits are

transmitted with the least significant bit (LSB) first.

•

RI = 0

Either SM2 = 0 or SM2 = 1

Received stop bit = 1

If any of these conditions is not met, the received frame is

irretrievably lost, and RI is not set.

Reception is initiated when the receive enable bit (REN) is 1

and the receive interrupt bit (RI) is 0. When RI is cleared, the

data is clocked into the RxD line, and the clock pulses are

output from the TxD line as shown in Figure 58.

Mode 2 (9-Bit UART with Fixed Baud Rate)

Mode 2 is selected by setting SM0 and clearing SM1. In this

mode, the UART operates in 9-bit mode with a fixed baud rate.

The baud rate is fixed at Core_Clk/64 by default, although by

setting the SMOD bit in PCON, the frequency can be doubled

to Core_Clk/32. Eleven bits are transmitted or received: a start

bit (0), 8 data bits, a programmable 9th bit, and a stop bit (1).

The 9th bit is most often used as a parity bit, although it can be

used for anything, including a ninth data bit if required.

RxD

(DATA OUT)

DATA BIT 0

DATA BIT 1

DATA BIT 6

DATA BIT 7

TxD

(SHIFT CLOCK)

Figure 58. 8-Bit Shift Register Mode

Mode 1 (8-Bit UART, Variable Baud Rate)

Mode 1 is selected by clearing SM0 and setting SM1. Each data

byte (LSB first) is preceded by a start bit (0) and followed by a

stop bit (1). Therefore, 10 bits are transmitted on TxD or are

received on RxD. The baud rate is set by the Timer 1 or Timer 2

overflow rate, or a combination of the two (one for transmission

and the other for reception).

To transmit, the 8 data bits must be written into SBUF. The

ninth bit must be written to TB8 in SCON. When transmission

is initiated, the 8 data bits (from SBUF) are loaded into the

transmit shift register (LSB first). The contents of TB8 are

loaded into the 9th bit position of the transmit shift register.

The transmission starts at the next valid baud rate clock. The TI

flag is set as soon as the stop bit appears on TxD.

Transmission is initiated by writing to SBUF. The write to SBUF

signal also loads a 1 (stop bit) into the 9th bit position of the

transmit shift register. The data is output bit-by-bit until the

stop bit appears on TxD and the transmit interrupt flag (TI) is

automatically set as shown in Figure 59.

Reception for Mode 2 is similar to that of Mode 1. The 8 data

bytes are input at RxD (LSB first) and loaded onto the receive

shift register. When all 8 bits have been clocked in, the following

events occur:

STOP BIT

START

BIT

D0 D1 D2 D3 D4

D5 D6

D7

TxD

•

The 8 bits in the receive shift register are latched into SBUF.

The 9th data bit is latched into RB8 in SCON.

The receiver interrupt flag (RI) is set.

TI

(SCON.1)

SET INTERRUPT

I.E., READY FOR MORE DATA

Figure 59. 8-Bit Variable Baud Rate

All of the following conditions must be met at the time the final

shift pulse is generated:

Reception is initiated when a 1-to-0 transition is detected on

RxD. Assuming that a valid start bit is detected, character

reception continues. The start bit is skipped and the 8 data bits

are clocked into the serial port shift register. When all 8 bits

have been clocked in, the following events occur:

•

RI = 0

Either SM2 = 0 or SM2 = 1

Received stop bit = 1

•

The 8 bits in the receive shift register are latched into SBUF.

The 9th bit (stop bit) is clocked into RB8 in SCON.

The receiver interrupt flag (RI) is set.

If any of these conditions is not met, the received frame is

irretrievably lost, and RI is not set.

Rev. A | Page 81 of 108

ADuC845/ADuC847/ADuC848

Mode 3 (9-Bit UART with Variable Baud Rate)

The Timer 1 interrupt should be disabled in this application.

The timer itself can be configured for either timer or counter

operation, and in any of its three running modes. In the most

typical application, it is configured for timer operation in

autoreload mode (high nibble of TMOD = 0010 binary). In that

case, the baud rate is given by the formula

Mode 3 is selected by setting both SM0 and SM1. In this mode,

the 8051 UART serial port operates in 9-bit mode with a variable

baud rate determined by either Timer 1 or Timer 2. The opera-

tion of the 9-bit UART is the same as for Mode 2, but the baud

rate can be varied as for Mode 1.

2^SMODCore Clock Frequency

Modes 1 and 3 Baud Rate =

×

In all four modes, transmission is initiated by any instruction

that uses SBUF as a destination register. Reception is initiated in

Mode 0 when RI = 0 and REN = 1. Reception is initiated in the

other modes by the incoming start bit if REN = 1.

32

(256 −TH1)

Timer 2 Generated Baud Rates

Baud rates can also be generated by using Timer 2. Using Timer 2

is similar to using Timer 1 in that the timer must overflow 16

times before a bit is transmitted or received. Because Timer 2

has a 16-bit autoreload mode, a wider range of baud rates is

possible.

UART Serial Port Baud Rate Generation

Mode 0 Baud Rate Generation

The baud rate in Mode 0 is fixed:

Core Clock Frequency

⎛

⎜

⎞

⎟

1

Mode 0 Baud Rate =

Modes 1 and 3 Baud Rate =

× Timer 2 Overflow Rate

12

16

⎝

⎠

Therefore, when Timer 2 is used to generate baud rates, the

timer increments every two clock cycles rather than every core

machine cycle as before. It increments six times faster than

Timer 1, and, therefore, baud rates six times faster are possible.

Because Timer 2 has 16-bit autoreload capability, very low baud

rates are still possible.

Mode 2 Baud Rate Generation

The baud rate in Mode 2 depends on the value of the SMOD bit

in the PCON SFR. If SMOD = 0, the baud rate is 1/32 of the

core clock. If SMOD = 1, the baud rate is 1/16 of the core clock:

2^SMOD

Mode 2 Baud Rate =

× Core Clock Frequency

32

Timer 2 is selected as the baud rate generator by setting the

TCLK and/or RCLK in T2CON. The baud rates for transmit

and receive can be simultaneously different. Setting RCLK

and/or TCLK puts Timer 2 into its baud rate generator mode as

shown in Figure 60.

Modes 1 and 3 Baud Rate Generation

The baud rates in Modes 1 and 3 are determined by the overflow

rate in Timer 1 or Timer 2, or in both (one for transmit and the

other for receive).

In this case, the baud rate is given by the formula

Timer 1 Generated Baud Rates

Modes 1 and 3 Baud Rate =

When Timer 1 is used as the baud rate generator, the baud rates

in Modes 1 and 3 are determined by the Timer 1 overflow rate

and the value of SMOD as follows:

Core Clock Frequency

(

16×

[

65536 −

(

RCAP2H : RCAP2L

)])

2^SMOD

Modes 1 and 3 Baud Rate =

× Timer 1 Overflow Rate

32

TIMER 1

OVERFLOW

2

0

1

SMOD

CONTROL

C/T2 = 0

CORE

CLK*

TIMER 2

OVERFLOW

1

0

TL2

(8 BITS)

TH2

(8 BITS)

RCLK

16

C/T2 = 1

T2

RX

CLOCK

TR2

TCLK

16

NOTE: AVAILABILITY OF ADDITIONAL

EXTERNAL INTERRUPT

RELOAD

TX

CLOCK

RCAP2H

RCAP2L

TIMER 2

INTERRUPT

T2EX

EXF 2

CONTROL

TRANSITION

DETECTOR

EXEN2

*THE CORE CLOCK IS THE OUTPUT OF THE PLL (SEE THE ON-CHIP PLL SECTION)

Figure 60. Timer 2, UART Baud Rates

Rev. A | Page 82 of 108

ADuC845/ADuC847/ADuC848

Timer 3 Generated Baud Rates

The appropriate value to write to the DIV2-1-0 bits can be

calculated using the following formula where f_COREis defined in

PLLCON SFR. Note that the DIV value must be rounded down.

The high integer dividers in a UART block mean that high

speed baud rates are not always possible. Also, generating baud

rates requires the exclusive use of a timer, rendering it unusable

for other applications when the UART is required. To address

this problem, the ADuC845/ADuC847/ADuC848 have a

dedicated baud rate timer (Timer 3) specifically for generating

highly accurate baud rates. Timer 3 can be used instead of

Timer 1 or Timer 2 for generating very accurate high speed

UART baud rates including 115200 and 230400. Timer 3 also

allows a much wider range of baud rates to be obtained. In fact,

every desired bit rate from 12 bps to 393216 bps can be

generated to within an error of 0.8%. Timer 3 also frees up the

other three timers, allowing them to be used for different

applications. A block diagram of Timer 3 is shown in Figure 61.

⎛

⎞

Core Clock Frequency

16× Baud Rate

log (2)

⎜

⎟

log

⎝

⎠

DIV =

T3FD is the fractional divider ratio required to achieve the

required baud rate. The appropriate value for T3FD can be

calculated with the following formula:

2×Core Clock Frequency

T3FD =

− 64

2

^{DIV −1}× Baud Rate

Note that T3FD should be rounded to the nearest integer. Once

the values for DIV and T3FD are calculated, the actual baud

rate can be calculated with the following formula:

CORE

CLK

TIMER 1/TIMER 2

2×Core Clock Frequency

Actual Baud Rate =

Tx CLOCK

FRACTIONAL

DIVIDER

÷ (1 + T3FD/64)

2

^{DIV −1}×(T3FD + 64)

TIMER 1/TIMER 2

Rx CLOCK

1

0

For example, to get a baud rate of 9600 while operating at a core

clock frequency of 1.5725 MHz, that is, CD = 3,

÷

2^DIV

Rx CLOCK

Tx CLOCK

1

0

DIV = log(1572500/(16 × 9600))/log2 = 3.35 = 3

÷

16

T3EN

T3 Rx/Tx

CLOCK

Note that the DIV result is rounded down.

T3FD = (2 × 1572500)/(2³⁻¹× 9600) − 64 = 18 = 12H

Figure 61. Timer 3, UART Baud Rate

Two SFRs (T3CON and T3FD) are used to control Timer 3.

T3CON is the baud rate control SFR, allowing Timer 3 to be

used to set up the UART baud rate, and to set up the binary

divider (DIV).

Therefore, the actual baud rate is 9588 bps, which gives an error

of 0.12%.

The T3CON and T3FD registers are used to control Timer 3.

T3CON – Timer 3 Control Register

SFR Address:

Power-On Default:

Bit Addressable:

9EH

00H

No

Table 55. T3CON SFR Bit Designations

Bit No.

Name

Description

7

T3BAUDEN

T3UARTBAUD Enable.

Set to enable Timer 3 to generate the baud rate. When set, PCON.7, T2CON.4, and T2CON.5 are

ignored. Cleared to let the baud rate be generated as per a standard 8052.

6

5

4

3

Not Implemented. Write Don’t Care.

Binary Divider

2, 1, 0

DIV2, DIV1, DIV0

DIV2 DIV1

DIV0

0

1

0

1

0

1

0

1

0

1

0

1

0

Binary Divider 0. See Table 57.

Binary Divider 1. See Table 57.

Binary Divider 2. See Table 57.

Binary Divider 3. See Table 57.

Binary Divider 4. See Table 57.

Binary Divider 5. See Table 57.

Binary Divider 6. See Table 57.

Rev. A | Page 83 of 108

ADuC845/ADuC847/ADuC848

T3FD—Timer 3 Fractional Divider Register

See Table 57 for values.

SFR Address:

Power-On Default:

Bit Addressable:

9DH

00H

No

Table 56. T3FD SFR Bit Designations

Bit No.

Name

Description

7

6

5

4

3

2

1

0

----

Not Implemented. Write Don’t Care.

Timer 3 Fractional Divider Bit 5.

Timer 3 Fractional Divider Bit 4.

Timer 3 Fractional Divider Bit 3.

Timer 3 Fractional Divider Bit 2.

Timer 3 Fractional Divider Bit 1.

Timer 3 Fractional Divider Bit 0.

T3FD.5

T3FD.4

T3FD.3

T3FD.2

T3FD.1

T3FD.0

Table 57. Common Baud Rates Using Timer 3 with a 12.58 MHz PLL Clock

Ideal Baud

CD

DIV

T3CON

T3FD

% Error

230400

0

1

81H

2DH

0.18

115200

0

1

2

1

82H

81H

2DH

0.18

57600

0

1

2

3

2

1

83H

82H

81H

2DH

0.18

38400

0

1

2

3

4

3

2

1

84H

83H

82H

81H

12H

0.12

19200

0

1

2

3

4

5

4

3

2

1

85H

84H

83H

82H

81H

12H

0.12

9600

0

1

2

3

4

5

6

5

4

3

2

1

86H

85H

84H

83H

82H

81H

12H

0.12

Rev. A | Page 84 of 108

ADuC845/ADuC847/ADuC848

INTERRUPT SYSTEM

The ADuC845/ADuC847/ADuC848 provide nine interrupt sources with two priority levels. The control and configuration of the

interrupt system is carried out through three interrupt-related SFRs:

IE

Interrupt Enable Register

IP

IEIP2

Interrupt Priority Register

Secondary Interrupt Enable Register

IE—Interrupt Enable Register

SFR Address:

Power-On Default:

Bit Addressable:

A8H

00H

Yes

Table 58. IE SFR Bit Designations

Bit No.

Name

Description

7

EA

Set by the user to enable all interrupt sources.

Cleared by the user to disable all interrupt sources.

Set by the user to enable the ADC interrupt.

6

5

4

3

2

EADC

ET2

ES

Cleared by the user to disable the ADC interrupt.

Set by the user to enable the Timer 2 interrupt.

Cleared by the user to disable the Timer 2 interrupt.

Set by the user to enable the UART serial port interrupt.

Cleared by the user to disable the UART serial port interrupt.

Set by the user to enable the Timer 1 interrupt.

Cleared by the user to disable the Timer 1 interrupt.

Set by the user to enable External Interrupt 1 (INT0).

Cleared by the user to disable External Interrupt 1 (INT0).

Set by the user to enable the Timer 0 interrupt.

Cleared by the user to disable the Timer 0 interrupt.

Set by the user to enable External Interrupt 0 (INT0).

Cleared by the user to disable External Interrupt 0 (INT0).

ET1

EX1

1

0

ET0

EX0

IP—Interrupt Priority Register

SFR Address:

Power-On Default:

Bit Addressable:

B8H

00H

Yes

Table 59. IP SFR Bit Designations

Bit No.

Name

Description

7

6

5

4

3

2

1

0

-----

PADC

PT2

PS

PT1

PX1

PT0

PX0

Not Implemented. Write Don’t Care.

ADC Interrupt Priority (1 = High; 0 = Low).

Timer 2 Interrupt Priority (1 = High; 0 = Low).

UART Serial Port Interrupt Priority (1 = High; 0 = Low).

Timer 1 Interrupt Priority (1 = High; 0 = Low).

INT0 (External Interrupt 1) priority (1 = High; 0 = Low).

Timer 0 Interrupt Priority (1 = High; 0 = Low).

INT0 (External Interrupt 0) Priority (1 = High; 0 = Low).

Rev. A | Page 85 of 108

ADuC845/ADuC847/ADuC848

IEIP2—Secondary Interrupt Enable Register

SFR Address:

Power-On Default:

Bit Addressable:

A9H

A0H

No

Table 60. IEIP2 Bit Designations

Bit No.

Name Description

7

6

5

4

3

2

----

PTI

PPSM

PSI

----

Not Implemented. Write Don’t Care.

Time Interval Counter Interrupt Priority Setting (1 = High, 0 = Low).

Power Supply Monitor Interrupt Priority Setting (1 = High, 0 = Low).

SPI/I²C Interrupt Priority Setting (1 = High, 0 = Low).

This bit must contain 0.

Set by the user to enable the time interval counter interrupt.

Cleared by the user to disable the time interval counter interrupt.

ETI

1

0

EPSMI Set by the user to enable the power supply monitor interrupt.

Cleared by the user to disable the power supply monitor interrupt.

ESI

Set by the user to enable the SPI/I²C serial port interrupt.

Cleared by the user to disable the SPI/I²C serial port interrupt.

INTERRUPT PRIORITY

INTERRUPT VECTORS

The interrupt enable registers are written by the user to enable

individual interrupt sources; the interrupt priority registers

allow the user to select one of two priority levels for each

interrupt. A high priority interrupt can interrupt the service

routine of a low priority interrupt, and if two interrupts of

different priorities occur at the same time, the higher level

interrupt is serviced first. An interrupt cannot be interrupted by

another interrupt of the same priority level. If two interrupts of

the same priority level occur simultaneously, the polling sequence,

as shown in Table 61, is observed.

When an interrupt occurs, the program counter is pushed onto

the stack, and the corresponding interrupt vector address is

loaded into the program counter. The interrupt vector addresses

are shown in Table 62.

Table 62. Interrupt Vector Addresses

Source

Vector Address

IE0

0003H

TF0

000BH

IE1

0013H

TF1

001BH

Table 61. Priority within Interrupt Level

RI + TI

0023H

Source

Priority

Description

TF2 + EXF2

002BH

PSMI

WDS

IE0

RDY0/RDY1

TF0

1 (Highest)

2

3

4

5

Power Supply Monitor Interrupt

Watchdog Timer Interrupt

External Interrupt 0

ADC Interrupt

Timer/Counter 0 Interrupt

External Interrupt 1

RDY0/RDY1 (ADuC845 only)

0033H

003BH

0043H

0053H

ISPI/I2CI

PSMI

TII

WDS

005BH

IE1

TF1

ISPI/I2CI

RI/TI

TF2/EXF2

TII

6

7

8

9

Timer/Counter 1 Interrupt

SPI/I²C Interrupt

UART Serial Port Interrupt

Timer/Counter 2 Interrupt

Timer Interval Counter Interrupt

11 (Lowest)

Rev. A | Page 86 of 108

ADuC845/ADuC847/ADuC848

HARDWARE DESIGN CONSIDERATIONS

This section outlines some of the key hardware design

considerations that must be addressed when integrating the

ADuC845/ADuC847/ADuC848 into any hardware system.

In either implementation, Port 0 (P0) serves as a multiplexed

address/data bus. It emits the low byte of the data pointer (DPL)

as an address, which is latched by ALE prior to data being placed

on the bus by the parts (write operation) or the external data

memory (read operation). Port 2 (P2) provides the data pointer

page byte (DPP) to be latched by ALE, followed by the data

pointer high byte (DPH). If no latch is connected to P2, DPP is

ignored by the SRAM, and the 8051 standard of 64-kbyte external

data memory access is maintained.

EXTERNAL MEMORY INTERFACE

In addition to their internal program and data memories, the

parts can access up to 16 Mbytes of external data memory

(SRAM). No external program memory access is available.

To begin executing code, tie the

(external access) pin high.

EA

The following example shows the code used to write data to

external data memory.

When

is high (pulled up to V_DD—see Figure 69), user

EA

program execution starts at Address 0 in the internal 62-kbyte

Flash/EE code space. When executing from internal code space,

accesses to the program space above F7FFH (62 kbytes) are read

as NOP instructions.

MOV DPP, #10h ;Set addr to 100000h

MOV DPH, #00h

MOV DPL, #00h

MOV A,

#'B' ;Write Char ‘B’ (42h)

Note that a second very important function of the

described in the Single-Pin Emulation Mode section under the

Other Hardware Considerations section.

pin is

EA

MOVX @DPTR,A ;Move to DPP:DPH:DPL addr

POWER SUPPLIES

Figure 62 shows a hardware configuration for accessing up to

64 kbytes of external data memory. This interface is standard to

any 8051 compatible MCU.

The parts’ operational power supply voltage range is 2.7 V to

5.25 V. Although the guaranteed data sheet specifications are

given only for power supplies within 2.7 V to 3.6 V and 4.75 V

to 5.25 V ( 5% of the nominal 5 V level), the chip functions

equally well at any power supply level between 2.7 V and 5.25 V.

SRAM

ADuC845/

ADuC847/

ADuC848

D0–D7

(DATA)

P0

Separate analog and digital power supply pins (AV_DDand DV_DD

respectively) allow AV_DDto be kept relatively free of the noisy

digital signals often present on a system DV_DDline. In this mode,

,

LATCH

A0–A7

ALE

the part can also operate with split supplies, that is, using different

voltage supply levels for each supply. For example, the system

can be designed to operate with a DV_DDvoltage level of 3 V and

the AV_DDlevel can be at 5 V, or vice versa, if required. A typical

split-supply configuration is shown in Figure 64.

A8–A15

P2

RD

OE

WR

WE

Figure 62. External Data Memory Interface (64-kbyte Address Space)

DIGITAL SUPPLY

ANALOG SUPPLY

10µF

If access to more than 64 kbytes of RAM is desired, a feature

unique to the MicroConverter allows addressing up to 16 Mbytes

of external RAM simply by adding another latch as shown in

Figure 63.

10µF

+

–

+

–

22

36

51

AV

4

DD

DV

DD

0.1µF

ADuC845/

ADuC847/

ADuC848

0.1µF

SRAM

ADuC845/

23

37

38

50

5

6

ADuC847/

ADuC848

D0–D7

(DATA)

DGND

P0

AGND

LATCH

A0–A7

ALE

Figure 64. External Dual-Supply Connections

(56-Lead CSP Pin Numbering)

A8–A15

P2

LATCH

A16–A23

RD

OE

WR

WE

Figure 63. External Data Memory Interface (16-Mbtye Address Space)

Rev. A | Page 87 of 108

ADuC845/ADuC847/ADuC848

POWER CONSUMPTION

As an alternative to providing two separate power supplies,

AV_DDcan be kept quiet by placing a small series resistor and/or

ferrite bead between it and DV_DD, and then decoupling AV_DD

separately to ground. An example of this configuration is shown

in Figure 65. In this configuration, other analog circuitry (such

as op amps and voltage reference) can be powered from the

AV_DDsupply line as well.

The DV_DDpower supply current consumption is specified in

normal and power-down modes. The AV_DDpower supply

current is specified with the analog peripherals disabled. The

normal mode power consumption represents the current drawn

from DV_DDby the digital core. The other on-chip peripherals

(such as the watchdog timer and power supply monitor)

consume negligible current and are therefore included with the

normal operating current. The user must add any currents

sourced by the parallel and serial I/O pins, and those sourced by

the DAC to determine the total current needed at the ADuC845/

ADuC847/ADuC848 DV_DDand AV_DDsupply pins. Also, current

drawn from the DV_DDsupply increases by approximately 5 mA

during Flash/EE erase and program cycles.

DIGITAL SUPPLY

1.6

Ω

10µF

BEAD

10µF

+

–

22

36

51

AV

4

DD

DV

DD

0.1µF

ADuC845/

ADuC847/

ADuC848

0.1µF

23

37

38

50

5

6

DGND

POWER-SAVING MODES

AGND

Setting the power-down mode bit, PCON.1, in the PCON SFR

described in Table 6, allows the chip to be switched from

normal mode into full power-down mode.

Figure 65. External Single-Supply Connections (56-Lead CSP Pin Numbering)

Notice that in both Figure 64 and Figure 65 a large value (10 µF)

reservoir capacitor sits on DV_DDand a separate 10 µF capacitor

sits on AV_DD. Also, local decoupling capacitors (0.1 µF) are

located at each V_DDpin of the chip. As per standard design

practice, be sure to include all of these capacitors and ensure

that the smaller capacitors are closer than the 10 µF capacitors

to each V_DDpin with lead lengths as short as possible. Connect

the ground terminal of each of these capacitors directly to the

underlying ground plane. Finally, note that, at all times, the

analog and digital ground pins on the part must be referenced

to the same system ground reference point. It is recommended

that the CSP paddle be soldered to ensure mechanical stability

but be floated with respect to system V_DDs or grounds.

In power-down mode, both the PLL and the clock to the core

are stopped. The on-chip oscillator can be halted or can

continue to oscillate, depending on the state of the oscillator

power-down bit (OSC_PD) in the PLLCON SFR. The TIC,

driven directly from the oscillator, can also be enabled during

power-down. However, all other on-chip peripherals are shut

down. Port pins retain their logic levels in this mode, but the

DAC output goes to a high impedance state (three-state) while

ALE and

outputs are held low. There are five ways to

PSEN

terminate power-down mode:

•

Asserting the RESET Pin

Returns to normal mode. All registers are set to their reset

default value and program execution starts at the reset

vector once the RESET pin is de-asserted.

POWER-ON RESET OPERATION

An internal power-on reset (POR) is implemented on the

ADuC845/ADuC847/ADuC848. For DV_DDbelow 2.63 V, the

internal POR holds the part in reset. As DV_DDrises above 2.63 V,

an internal timer times out for typically 128 ms before the part

is released from reset. The user must ensure that the power

supply has at least reached a stable 2.7 V minimum level by this

time. Likewise on power-down, the internal POR holds the part

in reset until the power supply drops below 1 V. Figure 66

illustrates the operation of the internal POR.

•

Cycling Power

All registers are set to their default state and program exe-

cution starts at the reset vector approximately 128 ms later.

Time Interval Counter (TIC) Interrupt

If the OSC_PD bit in the PLLCON SFR is clear, the 32 kHz

oscillator remains powered up even in power-down mode.

If the time interval counter (wake-up/RTC timer) is

enabled, a TIC interrupt wakes the part from power-down

mode. The CPU services the TIC interrupt. The RETI at

the end of the TIC ISR returns the core to the next

instruction after that one that enabled power-down.

2.63V TYP

DV

DD

128ms TYP

1.0V TYP

INTERNAL

CORE RESET

Figure 66. ADuC845/ADuC847/ADuC848 Internal Power-On Reset Operation

Rev. A | Page 88 of 108

ADuC845/ADuC847/ADuC848

In these cases, tie the AGND and DGND pins of the part to the

analog ground plane, as shown in Figure 67b. In systems with

only one ground plane, ensure that the digital and analog

components are physically separated onto separate halves of the

board such that digital return currents do not flow near analog

circuitry and vice versa. The parts can then be placed between

the digital and analog sections, as shown in Figure 67c.

•

SPI Interrupt

If the SERIPD bit in the PCON SFR is set, an SPI interrupt,

if enabled, wakes up the part from power-down mode. The

CPU services the SPI interrupt. The RETI at the end of the

ISR returns the core to the next instruction after the one

that enabled power-down.

Interrupt

INT0

In all of these scenarios, and in more complicated real-life

applications, keep in mind the flow of current from the supplies

and back to ground. Make sure that the return paths for all

currents are as close as possible to the paths the currents took to

reach their destinations. For example, do not power components

on the analog side of Figure 67b with DV_DDsince that would

force return currents from DV_DDto flow through AGND. Also,

try to avoid digital currents flowing under analog circuitry,

which could happen if the user placed a noisy digital chip on

the left half of the board in Figure 67c. Whenever possible,

avoid large discontinuities in the ground plane(s) (such as are

formed by a long trace on the same layer), since they force

return signals to travel a longer path. Make all connections

directly to the ground plane, with little or no trace separating

the pin from its via to ground.

If the INT0PD bit in the PCON SFR is set, an external

interrupt 0, if enabled, wakes up the part from power-

down. The CPU services the interrupt. The RETI at the end

of the ISR returns the core to the next instruction after the

one that enabled power-down.

Wake-Up from Power-Down Latency

Even with the 32 kHz crystal enabled during power-down, the

PLL takes some time to lock after a wake-up from power-down.

Typically, the PLL takes about 1 ms to lock. During this time,

code executes, but not at the specified frequency. Some opera-

tions, for example, UART communications, require an accurate

clock to achieve the specified 50 Hz/60 Hz rejection from the

ADCs. Therefore, it is advisable to wait until the PLL has locked

before proceeding with normal code execution. The following

code can be used to wait for the PLL to lock:

WAITFORLOCK: MOV A, PLLCON

JNB ACC.6, WAITFORLOCK

PLACE ANALOG

COMPONENTS

HERE

PLACE DIGITAL

COMPONENTS

HERE

a.

b.

c.

If the crystal is powered down during power-down, an additional

delay is associated with the startup of the crystal oscillator

before the PLL can lock. Typically taking about 150 ms, 32 kHz

crystals are inherently slow to oscillate. During this time before

lock, code executes, but the exact frequency of the clock cannot

be guaranteed. For any timing-sensitive operations, it is

recommended to wait for lock by using the lock bit in PLLCON

as shown previously.

AGND

DGND

PLACE ANALOG

COMPONENTS

HERE

PLACE DIGITAL

COMPONENTS

HERE

An alternative way of saving power in power-down mode

is to slow down the core clock by using the CD bits in the

PLLCON register.

AGND

DGND

GROUNDING AND BOARD LAYOUT

RECOMMENDATIONS

PLACE ANALOG

COMPONENTS

HERE

PLACE DIGITAL

COMPONENTS

HERE

As with all high resolution data converters, special attention

must be paid to grounding and PC board layout of ADuC845/

ADuC847/ADuC848-based designs in order to achieve

optimum performance from the ADCs and DAC.

GND

Figure 67. System Grounding Schemes

Although the parts have separate pins for analog and digital

ground (AGND and DGND), the user must not tie these to

separate ground planes unless the two ground planes are

connected together very close to the part as shown in the

simplified example in Figure 67a. In systems where digital and

analog ground planes are connected together somewhere else

(at the system’s power supply, for example), they cannot be

connected again near the part since a ground loop would result.

If the user plans to connect fast logic signals (rise/fall time < 5 ns)

to any of the ADuC845/ADuC847/ADuC848’s digital inputs,

add a series resistor to each relevant line to keep rise and fall

times longer than 5 ns at the parts input pins. A value of 100 Ω

or 200 Ω is usually sufficient to prevent high speed signals from

coupling capacitively into the part and affecting the accuracy of

ADC conversions.

Rev. A | Page 89 of 108

ADuC845/ADuC847/ADuC848

When using the LFCSP package, it is recommended that the

paddle underneath the chip be soldered to the board to provide

maximum mechanical stability. However, it is recommended

that this paddle not be grounded but left floating. All results and

specifications contained in this data sheet are taken or recorded

with the paddle floating.

ADuC845/ADuC847/ADuC848

XTAL1

XTAL2

32

33

12pF

32.768kHz

TO INTERNAL PLL

12pF

System Self-Identification

Figure 68. Crystal Connectivity to ADuC845/ADuC847/ADuC848

In some hardware designs, it may be an advantage for the

software to be able to identify the host MicroConverter.

As shown in the typical external crystal connection diagram in

Figure 68, two internal 12 pF capacitors are provided on-chip.

These are connected internally, directly to the XTAL1 and XTAL2

pins. The total input capacitance at both pins is detailed in the

Specifications table. Note that the total capacitance required for

a particular crystal must be in accordance with the crystal

manufacturer. However, in most cases, no additional external

capacitance is required above that already supplied on-chip.

The CHIPID SFR is a read-only register located at SFR address

C2H. The upper nibble of this SFR designates the MicroConverter

within the Σ-∆ ADC family. User software can read this SFR to

identify the host MicroConverter and therefore execute slightly

different code if required. The CHIPID SFR reads as follows for

the Σ-∆ ADC family of MicroConverter products. Note that the

ADuC845/ADuC847/ADuC848 are treated as one part as far as

the CHIPID is concerned.

OTHER HARDWARE CONSIDERATIONS

In-Circuit Serial Download Access

Table 63. CHIPID Values for Σ-∆ MicroConverter Products

Nearly all ADuC845/ADuC847/ADuC848 designs can take

advantage of the in-circuit reprogrammability of the chip. This

is accomplished by a connection to the parts” UART, which

requires an external RS-232 chip for level translation if down-

loading code from a PC. Basic configuration of an RS-232

connection is shown in Figure 69 with a simple ADM3202-

based circuit. If users would rather not include an RS-232 chip

on the target board, refer to Application Note uC006,

“A 4-Wire UART-to-PC Interface” available at

Part

CHIPID

ADuC816

ADuC824

ADuC836

ADuC834

1xH

0xH

3xH

2xH

ADuC845/ADuC847/ADuC848

AxH

Clock Oscillator

As described earlier, the core clock frequency for the ADuC845/

ADuC847/ADuC848 is generated from an on-chip PLL that

locks onto a multiple (384 times) of 32.768 kHz. The latter is

generated from an internal clock oscillator. To use the internal

clock oscillator, connect a 32.768 kHz parallel resonant crystal

between XTAL1 and XTAL2 as shown in Figure 68.

www.analog.com/microconverter, for a simple (and zero-cost-

per-board) method of gaining in-circuit serial download access

to the part.

Rev. A | Page 90 of 108

ADuC845/ADuC847/ADuC848

DOWNLOAD/DEBUG

ENABLE JUMPER

(NORMALLY OPEN)

1kΩ

DV

DD

1kΩ

2-PIN HEADER FOR

EMULATION ACCESS

(NORMALLY OPEN)

44 43

11 P1.6/I

EXC

1/AIN7

200mA/400mA

EXCITATION

CURRENT

AV

DD

ADuC845/ADuC847/ADuC848

CSP PACKAGE

AV

4

5

DD

0.1µF

AGND

XTAL2 35

XTAL1

6

RTD

34

REFIN–

REFIN+

P1.0/AIN1

P1.1/AIN2

7

32.768kHz

8

R

REF

5.6kV

56

1

DV

17 18 19 22 36 51 23 37 38 50

DD

RESET ACTIVE HIGH.

(NORMALLY OPEN)

0.1µF

DV

DD

DV

DD

RS232 INTERFACE*

STANDARD D-TYPE

SERIAL COMMS

CONNECTOR TO

PC HOST

ADM3202

C1+

V

CC

0.1µF

V+

GND

1

2

3

4

5

6

7

8

9

C1–

C2+

C2–

V–

T1OUT

R1IN

R1OUT

T1IN

T2OUT

R2IN

T2IN

R2OUT

*EXTERNAL UART TRANSCEIVER INTEGRATED IN SYSTEM OR AS PART

OF AN EXTERNAL DONGLE AS DESCRIBED IN APPLICATION NOTE uC006.

Figure 69. UART Connectivity in Typical System

download mode and fail to begin user code execution. To

prevent this, ensure that no external signals are capable of

In addition to the basic UART connections, users also need a

way to trigger the chip into download mode. This is accomplished

via a 1 kΩ pull-down resistor that can be jumpered onto the

pulling the

pin low, except for the external

jumper

PSEN

itself or the method of download entry in use during a reset or

power-cycle condition.

pin, as shown in Figure 69. To get the parts into download

PSEN

mode, connect this jumper and power-cycle the device (or

manually reset the device, if a manual reset button is available),

and it is ready to receive a new program serially. With the

jumper removed, the device powers on in normal mode (and

runs the program) whenever power is cycled or RESET is

Embedded Serial Port Debugger

From a hardware perspective, entry to serial port debug mode is

identical to the serial download entry sequence described

previously. In fact, both serial download and serial port debug

modes are essentially one mode of operation used in two

different ways.

toggled. Note that

is normally an output and that it is

PSEN

sampled as an input only on the falling edge of RESET, that is, at

power-on or upon an external manual reset. Note also that if

Note that the serial port debugger is fully contained on the

device, unlike ROM monitor type debuggers, and, therefore, no

external memory is needed to enable in-system debug sessions.

any external circuitry unintentionally pulls

low during

PSEN

power-on or reset events, it could cause the chip to enter

Rev. A | Page 91 of 108

ADuC845/ADuC847/ADuC848

Single-Pin Emulation Mode

Here, the on-chip excitation current sources are enabled to

excite the sensor. The excitation current flows directly through

the RTD generating a voltage across the RTD proportional to its

resistance. This differential voltage is routed directly to one set

of the positive and negative inputs of the ADC (AIN1, AIN2,

respectively in this case). The same current that excited the

RTD also flows through a series resistance, R_REF, generating a

ratiometric voltage reference, V_REF. The ratiometric voltage

reference ensures that variations in the excitation current do not

affect the measurement system since the input voltage from the

RTD and reference voltage across R_REFvary ratiometrically with

the excitation current. Resistor R_REFmust, however, have a low

temperature coefficient to avoid errors in the reference voltage

overtemperature. R_REFmust also be large enough to generate at

least a 1 V voltage reference.

Built into the ADuC845/ADuC847/ADuC848 is a dedicated

controller for single-pin in-circuit emulation (ICE). In this mode,

emulation access is gained by connection to a single pin, the

pin. Normally on the 8051 standard, this pin is hardwired either

high or low to select execution from internal or external program

memory space. Note that external program memory or execu-

tion from external program memory is not allowed on the

devices. To enable single-pin emulation mode, users need to pull

EA

the

pin high through a 1 kΩ resistor as shown in Figure 69.

EA

The emulator then connects to the 2-pin header also shown in

Figure 69. To be compatible with the standard connector that

comes with the single-pin emulator available from Accutron

Limited (www.accutron.com), use a 2-pin 0.1-inch pitch

Friction Lock header from Molex (www.molex.com) such as

part number 22-27-2021. Be sure to observe the polarity of this

header. As shown in Figure 69, when the Friction Lock tab is at

the right, the ground pin should be the lower of the two pins

when viewed from the top.

The preceding example shows just a single differential ADC

connection using a single reference input pair. The ADuC845/

ADuC847/ADuC848 have the capability of connecting to five

differential inputs directly or ten single-ended inputs (LFCSP

package only) as well as having a second reference input. This

arrangement means that different sensors with different

reference ranges can be connected to the part with the need for

external multiplexing circuitry. This arrangement is shown in

Figure 70. The bridge sensor shown can be a load cell or a

pressure sensor. The RTD is shown using a reference voltage

derived from the R_REFresistor via the REFIN inputs, and the

bridge sensor is shown using a divided down AV_DDreference via

the REFIN2 inputs.

Typical System Configuration

A typical ADuC845/ADuC847/ADuC848 configuration is

shown in Figure 69. Figure 69 also includes connections for a

typical analog measurement application of the parts, namely an

interface to an resistive temperature device (RTD). The

arrangement shown is commonly referred to as a 4-wire RTD

configuration.

Rev. A | Page 92 of 108

ADuC845/ADuC847/ADuC848

DOWNLOAD/DEBUG

ENABLE JUMPER

(NORMALLY OPEN)

1kΩ

DV

DD

1kΩ

2-PIN HEADER FOR

EMULATION ACCESS

(NORMALLY OPEN)

44 43

11 P1.6/I

EXC

1/AIN7

200mA/400mA

EXCITATION

CURRENT

AV

DD

ADuC845/ADuC847/ADuC848

CSP PACKAGE

AV

4

5

DGND

DV

DD

0.1µF

AGND

DD

XTAL2 35

XTAL1

AGND

6

7

RTD

34

REFIN–

8

REFIN+

R

REF

5.6kV

56

1

P1.0/AIN1

P1.1/AIN2

P1.2/AIN3/REFIN2+

AIN9

AV

DD

R

2

15

16

3

R

AIN10

P1.3/AIN4/REFIN2–

DV

17 18 19 22 36 51 23 37 38 50

DD

RESET ACTIVE HIGH.

(NORMALLY OPEN)

0.1µF

DV

DD

DV

DD

RS232

CONNECTION

Figure 70. Dual Reference Typical Connectivity

Rev. A | Page 93 of 108

ADuC845/ADuC847/ADuC848

QuickStart DEVELOPMENT SYSTEM

The QuickStart Development System is an entry-level, low cost

development tool suite supporting the ADuC8xx MicroConverter

product family. The system consists of the following PC-based

(Windows® compatible) hardware and software development

tools:

QuickStart-PLUS DEVELOPMENT SYSTEM

The QuickStart-PLUS development system offers users

enhanced nonintrusive debug and emulation tools. The system

consists of the following PC-based (Windows compatible)

hardware and software development tools:

Hardware:

Evaluation board and serial port

programming cable.

Serial download software.

Hardware:

Software:

Prototype Board, Accutron NonIntrusive

Single-Pin Emulator.

ASPIRE Integrated Development

Environment. Features full C and Assembly

emulation using the Accutron single-pin

emulator.

Software:

Miscellaneous: CD-ROM documentation and prototype

evaluation board.

A brief description of some of the software tools and

components in the QuickStart system follows.

Miscellaneous: CD-ROM documentation.

Download—In-Circuit Serial Downloader

The serial downloader is a Windows application that allows the

user to serially download an assembled program (Intel® hexa-

decimal format file) to the on-chip program flash memory via

the serial COM port on a standard PC. Application Note uC004

details this serial download protocol and is available from

www.analog.com/microconverter.

ASPIRE—IDE

The ASPIRE® integrated development environment is a

Windows application that allows the user to compile, edit, and

debug code in the same environment. The ASPIRE software

allows users to debug code execution on silicon using the

MicroConverter UART serial port. The debugger provides

access to all on-chip peripherals during a typical debug session

as well as single-step, animate (automatic single stepping), and

break-point code execution control.

Note that the ASPIRE IDE is also included as part of the

QuickStart-PLUS system. As part of the QuickStart-PLUS

system the ASPIRE IDE also supports mixed level and C source

debugging. This is not available in the QuickStart system where

the program is limited to assembly only.

Rev. A | Page 94 of 108

ADuC845/ADuC847/ADuC848

TIMING SPECIFICATIONS

AC inputs during testing are driven at DV_DD– 0.5 V for Logic 1 and 0.45 V for Logic 0. Timing measurements are made at V_IHmin for

Logic 1 and V_ILmax for Logic 0 as shown in Figure 71.

For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs. A port pin begins to float when a

100 mV change from the loaded V_OH/V_OLlevel occurs as shown in Figure 71.

C_LOADfor all outputs = 80 pF, unless otherwise noted.

AV_DD= 2.7 V to 3.6 V or 4.75 V to 5.25 V, DV_DD= 2.7 V to 3.6 V or 4.75 V to 5.25 V; all specifications T_MINto T_MAX, unless otherwise noted.

Table 64. CLOCK INPUT (External Clock Driven XTAL1) Parameter

32.768 kHz External Crystal

Min

Typ

30.52

6.26

9

Max

Unit

µs

ns

t_CK

XTAL1 Period

t_CKL

t_CKH

t_CKR

XTAL1 Width Low

XTAL1 Width High

XTAL1 Rise Time

XTAL1 Fall Time

t_CKF

9

ns

MHz

µs

1/t_CORE

t_CORE

t_CYC

Core Clock Frequency¹

Core Clock Period²

Machine Cycle Time³

0.098

10.2

1.57

0.636

12.58

0.08

µs

¹ADuC845/ADuC847/ADuC848 internal PLL locks onto a multiple (512 times) of the 32.768 kHz external crystal frequency to provide a stable 12.58 MHz internal clock

for the system. The core can operate at this frequency or at a binary submultiple called Core_Clk, selected via the PLLCON SFR.

²This number is measured at the default Core_Clk operating frequency of 1.57 MHz.

³ADuC845/ADuC847/ADuC848 machine cycle time is nominally defined as 1/Core_Clk.

DV – 0.5V

DD

V

– 0.1V

+ 0.1V

V

– 0.1V

LOAD

0.2DV + 0.9V

DD

TIMING

REFERENCE

POINTS

V

LOAD

TEST POINTS

LOAD

0.2DV – 0.1V

DD

V

– 0.1V

LOAD

0.45V

Figure 71. Timing Waveform Characteristics

Rev. A | Page 95 of 108

ADuC845/ADuC847/ADuC848

Table 65. EXTERNAL DATA MEMORY READ CYCLE Parameter

12.58 MHz Core Clock

6.29 MHz Core Clock

Max

Min

60

Max

Min

125

120

290

Unit

ns

t_RLRH

t_AVLL

t_LLAX

t_RLDV

t_RHDX

t_RHDZ

t_LLDV

t_AVDV

t_LLWL

t_AVWL

t_RLAZ

t_WHLH

RD Pulse Width

Address Valid after ALE Low

Address Hold after ALE Low

RD Low to Valid Data In

Data and Address Hold after RD

Data Float after RD

60

145

48

100

0

150

170

230

625

350

470

ALE Low to Valid Data In

Address to Valid Data In

ALE Low to RD or WR Low

Address Valid to RD or WR Low

RD Low to Address Float

RD or WR High to ALE High

130

190

255

375

15

35

60

120

ALE (O)

t_WHLH

PSEN (O)

t_LLDV

t_LLWL

t_RLRH

RD (O)

t_AVWL

t_LLAX

t_RLDV

t_RHDZ

t_RHDX

t_AVLL

t_RLAZ

A0ٛ

A7 (OUT)

t_AVDV

DATA (IN)

PORT 0 (I/O)

A16

ٛ

A23

A8 A15

PORT 2 (O)

Figure 72. External Data Memory Read Cycle

Rev. A | Page 96 of 108

ADuC845/ADuC847/ADuC848

Table 66. EXTERNAL DATA MEMORY WRITE CYCLE Parameter

12.58 MHz Core Clock

6.29 MHz Core Clock

Min

65

Max

Min

130

120

135

Max

Unit

ns

t_WLWH

t_AVLL

t_LLAX

WR Pulse Width

Address Valid after ALE Low

Address Hold after ALE Low

ALE Low to RD or WR Low

Address Valid to RD or WR Low

Data Valid to WR Transition

Data Setup before WR

60

65

ns

t_LLWL

130

260

t_AVWL

t_QVWX

t_QVWH

t_WHQX

t_WHLH

190

60

375

120

250

755

125

ns

120

380

60

ns

Data and Address Hold after WR

RD or WR High to ALE High

ns

ALE (O)

t_WHLH

PSEN (O)

t_LLWL

t_WLWH

WR (O)

t_AVWL

t_LLAX

t_QVWX

t_WHQX

t_AVLL

t_QVWH

DATA

A0ٛA7

A16ٛ

A23

V8 A15

PORT 2 (O)

Figure 73. External Data Memory Write Cycle

Rev. A | Page 97 of 108

ADuC845/ADuC847/ADuC848

Table 67. I²C COMPATIBLE INTERFACE TIMING Parameter

Parameter

Min

1.3

0.6

100

Max

Unit

µs

ns

t_L

t_H

SCLOCK Low Pulse Width

SCLOCK High Pulse Width

Start Condition Hold Time

Data Setup Time

Data Hold Time

Setup Time for Repeated Start

Stop Condition Setup Time

Bus Free Time between a Stop Condition and a Start Condition

Rise Time of Both SCLOCK and SDATA

Fall Time of Both SCLOCK and SDATA

Pulse Width of Spike Suppressed

t_SHD

t_DSU

t_DHD

t_RSU

t_PSU

t_BUF

t_R

0.9

0.6

1.3

300

50

t_F

1

t_SUP

____________________________________________

¹Input filtering on both the SCLOCK and SDATA inputs suppresses noise spikes less than 50 ns.

t_BUF

t_SUP

t_R

SDATA (I/O)

MSB

LSB

ACK

MSB

t_DSU

t_F

t_DHD

t_R

t_RSU

t_H

t_PSU

SCLK (I)

t_SHD

1

2-7

8

9

1

t_SUP

t_L

S(R)

PS

t_F

STOP

START

REPEATED

START

CONDITION CONDITION

Figure 74. I²C Compatible Interface Timing

Rev. A | Page 98 of 108

ADuC845/ADuC847/ADuC848

Table 68. SPI MASTER MODE TIMING (CPHA = 1) Parameter

Min

Typ

635

Max

Unit

ns

t_SL

t_SH

SCLOCK Low Pulse Width¹

SCLOCK High Pulse Width¹

Data Output Valid after SCLOCK Edge

Data Input Setup Time before SCLOCK Edge

Data Input Hold Time after SCLOCK Edge

Data Output Fall Time

Data Output Rise Time

SCLOCK Rise Time

SCLOCK Fall Time

t_DAV

t_DSU

t_DHD

t_DF

t_DR

t_SR

50

100

10

25

t_SF

ns

____________________________________________

¹Characterized under the following conditions:

a. Core clock divider bits CD2, CD1, and CD0 in PLLCON SFR set to 0, 1, and 1, respectively, that is, core clock frequency = 1.57 MHz.

b. SPI bit-rate selection bits SPR1 and SPR0 in SPICON SFR set to 0 and 0, respectively.

SCLOCK

(CPOL = 0)

t_SH

t_SL

t_SR

t_SF

SCLOCK

(CPOL = 1)

t_DAV

t_DF

t_DR

MOSI

MISO

MSB

BITS 6–1

LSB

LSB IN

MSB IN

BITS 6–1

t_DSU

t_DHD

Figure 75. SPI Master Mode Timing (CHPA = 1)

Rev. A | Page 99 of 108

ADuC845/ADuC847/ADuC848

Table 69. SPI MASTER MODE TIMING (CPHA = 0) Parameter

Min

Typ

635

Max

Unit

ns

t_SL

t_SH

SCLOCK Low Pulse Width¹

SCLOCK High Pulse Width¹

t_DAV

t_DOSU

t_DSU

t_DHD

t_DF

t_DR

t_SR

t_SF

Data Output Valid after SCLOCK Edge

Data Output Setup before SCLOCK Edge

Data Input Setup Time before SCLOCK Edge

Data Input Hold Time after SCLOCK Edge

Data Output Fall Time

Data Output Rise Time

SCLOCK Rise Time

SCLOCK Fall Time

50

150

100

10

25

¹Characterized under the following conditions:

a. Core clock divider bits CD2, CD1, and CD0 in PLLCON SFR set to 0, 1, and 1, respectively, that is, core clock frequency = 1.57 MHz.

b. SPI bit-rate selection bits SPR1 and SPR0 in SPICON SFR set to 0 and 0, respectively.

SCLOCK

(CPOL = 0)

t_SH

t_SL

t_SR

t_SF

SCLOCK

(CPOL = 1)

t_DAV

t_DOSU

t_DF

t_DR

MOSI

MISO

MSB

BITS 6–1

LSB

LSB IN

MSB IN

BITS 6–1

t_DSUt_DHD

Figure 76. SPI Master Mode Timing (CHPA = 0)

Rev. A | Page 100 of 108

ADuC845/ADuC847/ADuC848

Table 70. SPI SLAVE MODE TIMING (CPHA = 1) Parameter

Min

Typ

Max

Unit

ns

t_SS

SS to SCLOCK Edge

0

t_SL

t_SH

SCLOCK Low Pulse Width

SCLOCK High Pulse Width

Data Output Valid after SCLOCK Edge

Data Input Setup Time before SCLOCK Edge

Data Input Hold Time after SCLOCK Edge

Data Output Fall Time

330

t_DAV

t_DSU

t_DHD

t_DF

t_DR

t_SR

50

100

10

25

Data Output Rise Time

SCLOCK Rise Time

t_SF

SCLOCK Fall Time

t_SFS

SS High after SCLOCK Edge

0

SS

t_SFS

t_SS

SCLOCK

(CPOL = 0)

t_SH

t_SL

t_SR

t_SF

SCLOCK

(CPOL = 1)

t_DAV

t_DF

t_DR

MISO

BITS 6–1

LSB

MSB

MOSI

MSB IN

LSB IN

t_DSU

t_DHD

Figure 77. SPI Slave Mode Timing (CHPA = 1)

Rev. A | Page 101 of 108

ADuC845/ADuC847/ADuC848

Table 71. SPI SLAVE MODE TIMING (CPHA = 0) Parameter

Min

Typ

Max

Unit

ns

t_SS

SS to SCLOCK Edge

0

t_SL

t_SH

t_DAV

t_DSU

t_DHD

t_DF

SCLOCK Low Pulse Width

SCLOCK High Pulse Width

Data Output Valid after SCLOCK Edge

Data Input Setup Time before SCLOCK Edge

Data Input Hold Time after SCLOCK Edge

Data Output Fall Time

330

50

100

10

25

20

t_DR

Data Output Rise Time

t_SR

SCLOCK Rise Time

t_SF

SCLOCK Fall Time

t_DOSS

t_SFS

Data Output Valid after SS Edge

SS High after SCLOCK Edge

SS

t_SFS

t_SS

SCLOCK

(CPOL = 0)

t_SH

t_SL

t_SF

t_SR

SCLOCK

(CPOL = 1)

t_DAV

t_DOSS

t_DF

t_DR

MISO

MOSI

BITS 6–1

MSB

LSB

BITS 6–1

LSB IN

MSB IN

t_DSU

t_DHD

Figure 78. SPI Slave Mode Timing (CHPA = 0)

Rev. A | Page 102 of 108

ADuC845/ADuC847/ADuC848

Table 72. UART Timing (Shift Register Mode) Parameter

12.58 MHz Core_Clk

Variable Core_Clk

Min

Typ

Max

Min

Typ

Max

Unit

ns

TXLXL

Serial Port Clock Cycle Time

Output Data Setup to Clock

Input Data Setup to Clock

Input Data Hold after Clock

Output Data Hold after Clock

954

12t_core

TQVXH

TDVXH

TXHDX

TXHQX

662

292

0

ns

22

ns

t_XLXL

TxD

(OUTPUT CLOCK)

SET RI

OR

t_QVXH

SET TI

t_XHQX

RxD

(OUTPUT DATA)

LSB

BIT 1

BIT 6

t_DVXH

t_XHDX

RxD

(INPUT DATA)

LSB

BIT 1

BIT 6

MSB

Figure 79. UART Timing in Shift Register Mode

Rev. A | Page 103 of 108

ADuC845/ADuC847/ADuC848

OUTLINE DIMENSIONS

14.15

1.03

0.88

0.73

13.90 SQ

13.65

2.45

MAX

39

27

SEATING

PLANE

40

26

10.20

10.00 SQ

9.80

TOP VIEW

(PINS DOWN)

7.80

REF

10°

6°

2°

2.10

2.00

1.95

0.23

0.11

VIEW A

PIN 1

7°

0°

52

14

0.25

MAX

1

13

0.13 MIN

COPLANARITY

0.65 BSC

0.38

0.22

VIEW A

ROTATED 90° CCW

COMPLIANT TO JEDEC STANDARDS MO-112-AC-1

Figure 80. 52-Lead Metric Quad Flat Package [MQFP]

(S-52)

Dimensions shown in millimeters

0.30

0.23

0.18

8.00

BSC SQ

0.60 MAX

PIN 1

INDICATOR

43

42

56

1

PIN 1

INDICATOR

6.25

6.10

5.95

7.75

BSC SQ

BOTTOM

VIEW

SQ

TOP

VIEW

0.50

0.40

0.30

29

28

14

15

0.25 MIN

6.50

REF

0.80 MAX

0.65 TYP

1.00

0.85

0.80

12° MAX

0.05 MAX

0.02 NOM

COPLANARITY

0.08

0.50 BSC

0.20 REF

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MO-220-VLLD-2

Figure 81. 56-Lead Frame Chip Scale Package [LFCSP]

(CP-56)

Dimensions shown in millimeters

Rev. A | Page 104 of 108

ADuC845/ADuC847/ADuC848

ORDERING GUIDE

Model¹

Temperature Range

−40°C to +125°C

−40°C to +85°C

Package Description

Package Option

ADuC845BS62-5

ADuC845BS62-3

ADuC845BS8-5

ADuC845BS8-3

ADuC845BCP62-5

ADuC845BCP62-3

ADuC845BCP8-5

ADuC845BCP8-3

52-Lead Plastic Quad Flatpack, 62-kbyte, 5 V

52-Lead Plastic Quad Flatpack, 62-kbyte, 3 V

52-Lead Plastic Quad Flatpack, 8-kbyte, 5 V

52-Lead Plastic Quad Flatpack, 8-kbyte, 3 V

56-Lead Chip Scale Package, 62-kbyte, 5 V

56-Lead Chip Scale Package, 62-kbyte, 3 V

56-Lead Chip Scale Package, 8-kbyte, 5 V

56-Lead Chip Scale Package, 8-kbyte, 3 V

S-52

CP-56

ADuC847BS62-5

ADuC847BS62-3

ADuC847BS32-5

ADuC847BS32-3

ADuC847BS8-5

ADuC847BS8-3

ADuC847BCP62-5

ADuC847BCP62-3

ADuC847BCP8-5

ADuC847BCP8-3

−40°C to +125°C

−40°C to +85°C

52-Lead Plastic Quad Flatpack, 62-kbyte, 5 V

52-Lead Plastic Quad Flatpack, 62-kbyte, 3 V

52-Lead Plastic Quad Flatpack, 32-kbyte, 5 V

52-Lead Plastic Quad Flatpack, 32-kbyte, 3 V

52-Lead Plastic Quad Flatpack, 8-kbyte, 5 V

52-Lead Plastic Quad Flatpack, 8-kbyte, 3 V

56-Lead Chip Scale Package, 62-kbyte, 5 V

56-Lead Chip Scale Package, 62-kbyte, 3 V

56-Lead Chip Scale Package, 8-kbyte, 5 V

56-Lead Chip Scale Package, 8-kbyte, 3 V

S-52

CP-56

ADuC848BS62-5

ADuC848BS62-3

ADuC848BS32-5

ADuC848BS32-3

ADuC848BS8-5

ADuC848BS8-3

ADuC848BCP62-5

ADuC848BCP62-3

ADuC848BCP8-5

ADuC848BCP8-3

−40°C to +125°C

−40°C to +85°C

52-Lead Plastic Quad Flatpack, 62-kbyte, 5 V

52-Lead Plastic Quad Flatpack, 62-kbyte, 3 V

52-Lead Plastic Quad Flatpack, 32-kbyte, 5 V

52-Lead Plastic Quad Flatpack, 32-kbyte, 3 V

52-Lead Plastic Quad Flatpack, 8-kbyte, 5 V

52-Lead Plastic Quad Flatpack, 8-kbyte, 3 V

56-Lead Chip Scale Package, 62-kbyte, 5 V

56-Lead Chip Scale Package, 62-kbyte, 3 V

56-Lead Chip Scale Package, 8-kbyte, 5 V

56-Lead Chip Scale Package, 8-kbyte, 3 V

S-52

CP-56

EVAL-ADuC845QS

EVAL-ADuC845QSP²

EVAL-ADuC847QS

EVAL-ADuC847QSP²

QuickStart Development System

QuickStart-PLUS Development System

QuickStart Development System

QuickStart-PLUS Development System

¹The -3 and -5 in the Model column indicate the DV_DDoperating voltage.

²The QuickStart Plus system can only be ordered directly from Accutron. It can be purchased from the website www.accutron.com.

Rev. A | Page 105 of 108

ADuC845/ADuC847/ADuC848

NOTES

Rev. A | Page 106 of 108

ADuC845/ADuC847/ADuC848

NOTES

Rev. A | Page 107 of 108

ADuC845/ADuC847/ADuC848

NOTES

Purchase of licensed I²C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I²C Patent

Rights to use these components in an I²C system, provided that the system conforms to the I²C Standard Specification as defined by Philips.

©

registered trademarks are the property of their respective owners.

D04741–0–6/04(A)

Rev. A | Page 108 of 108


型号：	ADUC848BS8-5
厂家：	ADI
描述：	MicroConverter Multichannel 24-/16-Bit ADCs with Embedded 62 kB Flash and Single-Cycle MCU 微转换器多通道24位/ 16位ADC，内置62 KB的闪存和单周期MCU 转换器闪存
文件：	总108页 (文件大小：1108K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADUC848BS8-5 [ADI]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB