ADUCM320BBCZ [ADI]
ADUCM320BBCZ;
ADI 
Precision Analog Microcontroller, 14-Bit Analog
Input/Output with MDIO Interface, ARM Cortex-M3
Data Sheet
ADuCM320
On-chip peripherals
MDIO slave up to 4 MHz
2 × I2C, 2 × SPI, UART
Multiple general-purpose input/output (GPIO) pins: 3.6 V
compliant
7 × 1.2 V compatible when used for MDIO
32-element programmable logic array (PLA)
3 general-purpose timers
Wake-up timer
Watchdog timer
16-bit pulse width modulator (PWM)
Power
Supply range: 2.9 V to 3.6 V, and 1.8 V to 2.5 V for IDACs
Flexible operating modes for low power applications
Packages and temperature range
6 mm × 6mm, 96-ball CSP_BGA package
Fully specified for −40°C to +105°C ambient operation
Tools
FEATURES
Analog input/output
Multichannel, 14-bit, 1 MSPS analog-to-digital
converter (ADC)
Up to 16 ADC input channels
0 V to VREF analog input range
Fully differential and single-ended modes
AVDD and IOVDD monitors
12-bit voltage output digital-to-analog converters (VDACs)
8 VDACs with a range of 0 V to 2.5 V or AVDD outputs
12-bit current output DACs (IDACs)
4 IDACS with a range of 0 mA to 150 mA outputs
Voltage comparator
Microcontroller
ARM® Cortex®-M3 processor, 32-bit RISC architecture
Serial wire port supports code download and debug
Clocking options
80 MHz phase-locked loop (PLL) with programmable
divider
Trimmed on-chip oscillator ( 3%)
External 16 MHz crystal option
External clock source up to 80 MHz
Memory
Low cost QuickStart™ development system
Full third party support
APPLICATIONS
Optical networking
2 × 128 kB independent Flash/EE memories
10,000 cycle Flash/EE endurance
20-year Flash/EE retention
32 kB SRAM
Software triggered in-circuit reprogrammability via
management data input/output (MDIO)
Rev. C
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ADUCM320* PRODUCT PAGE QUICK LINKS
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EVALUATION KITS
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• ADuCM320 Evaluation Board
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DOCUMENTATION
Application Notes
DISCUSSIONS
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• AN-1310: Flash Programming via MDIO—Protocol Type 8
• AN-1322: ADuCM320 Code Execution Speed
Data Sheet
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• ADuCM320: Precision Analog Microcontroller, 14-Bit
Analog I/O with MDIO Interface, ARM Cortex-M3 Data
Sheet
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User Guides
• UG-498: ADuCM320 Hardware Reference Manual
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ADuCM320
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Absolute Maximum Ratings ..................................................... 21
ESD Caution................................................................................ 21
Pin Configuration and Function Descriptions........................... 22
Typical Performance Characteristics ........................................... 27
Recommended Circuit and Component Values ........................ 28
Packaging and Ordering Information ......................................... 30
Outline Dimensions................................................................... 30
Ordering Guide .......................................................................... 30
Applications....................................................................................... 1
Revision History ............................................................................... 2
Functional Block Diagram .............................................................. 3
General Description......................................................................... 4
Specifications..................................................................................... 5
Microcontroller Electrical Specifications.................................. 5
Timing Specifications ................................................................ 15
REVISION HISTORY
10/15—Rev. B to Rev. C
Change to Features Section ............................................................. 1
Added Table 2; Renumbered Sequentially .................................. 10
Changes to Table 7 and Figure 5................................................... 18
Changes to Table 8 and Figure 6................................................... 19
Change to Table 10 ......................................................................... 21
Changes to Figure 14...................................................................... 27
Changes to Ordering Guide .......................................................... 30
3/15—Rev. A to Rev. B
Changes to Table 1............................................................................ 7
Changes to tSHD and tPSU Parameters, Table 3 .............................. 10
11/14—Rev. 0 to Rev. A
Changes to Figure 1.......................................................................... 3
Changes to General Description .................................................... 4
Changes to Table 1 ............................................................................ 5
Added Timing Specifications Section.......................................... 10
Added Figure 2; Renumbered Sequentially ................................ 10
Added Figure 3................................................................................ 11
Added Figure 4................................................................................ 12
Added Figure 5................................................................................ 13
Added Figure 6 and Figure 7......................................................... 14
Changes to Absolute Maximum Ratings Section....................... 15
Changes to Pin C3 and Pin A11 Descriptions............................ 17
Changes to Ordering Guide .......................................................... 24
6/14—Revision 0: Initial Version
Rev. C | Page 2 of 30
Data Sheet
ADuCM320
FUNCTIONAL BLOCK DIAGRAM
BUF_VREF2V5
XTALO XTALI ECLKIN
2.5V BAND GAP
1.8 V LDO
DGNDx
AVDDx
AGNDx
CLOCK SYSTEM
32.768kHz
16MHz OSC
80MHz PLL
AIN0
AIN5
14-BIT
SAR ADC
MUX
IOVDDx
IOGNDx
AIN6
AIN15
ARM
CORTEX M3
PROCESSOR
INTERNAL
CHANNELS:
TEMPERATURE,
GPIO PORTS
UART
AV , IOV
DD
DD
GENERAL
PURPOSE
I/O PORTS
2 × SPI
2
2 × I C
COMPA-
RATOR
EXT IRQS
MDIO
PLA
MEMORY
2 × 128kB FLASH
32kB SRAM
VDAC0
VDAC
VDAC
IDAC
IDAC
DMA
NVIC
3 × GP TIMER
WD TIMER
WAKE-UP TIMER
PWM
VDAC7
IDAC0
IDAC3
PWM0 TO
PWM6
ADuCM320
RESET SYSTEM
RESET
SWDIO
SWCLK
SERIAL WIRE
PGND
PVDDx
Figure 1.
Rev. C | Page 3 of 30
ADuCM320
Data Sheet
GENERAL DESCRIPTION
The ADuCM320 is a fully integrated single package device that
incorporates high performance analog peripherals together
with digital peripherals controlled by an 80 MHz ARM Cortex-
M3 processor and integral flash for code and data.
optionally be divided down to reduce current consumption.
Additional low power modes can be set via software. In normal
operating mode, the ADuCM320 digital core consumes about
300 µA per MHz.
The ADC on the ADuCM320 provides 14-bit, 1 MSPS data
acquisition on up to 16 input pins that can be programmed for
single-ended or differential operation. The voltage at the IDAC
output pins can also be measured by the ADC, which is useful for
controlling the power consumption of the current DACs.
Additionally, chip temperature and supply voltages can be
measured.
The device includes an MDIO interface capable of operating at
up to 4 MHz. The capability to simultaneously execute from
one flash block and write/erase the other flash block makes the
ADuCM320 ideal for 10G, 40G, and 100G optical applications.
User programming is eased by incorporating PHYADR and
DEVADD hardware comparators. In addition, the nonerasable
kernel code plus flags in user flash provide assistance by
allowing user code to robustly switch between the two blocks
of user flash code and data spaces.
The ADC input voltage is 0 V to VREF. A sequencer is provided,
which allows a user to select a set of ADC channels to be measured
in sequence without software involvement during the sequence.
The sequence can optionally repeat automatically at a user
selectable rate.
The ADuCM320 integrates a range of on-chip peripherals that
can be configured under software control, as required in the appli-
cation. These peripherals include 1 × UART, 2 × I2C, and 2 × SPI
serial input/output communication controllers, GPIO, 32-
element programmable logic array, 3 general-purpose timers,
plus a wake-up timer and system watchdog timer. A 16-bit
PWM with seven output channels is also provided.
Up to eight VDACs are provided with output ranges that are
programmable to one of two voltage ranges.
Four IDAC sources are provided. The output currents are
programmable with ranges of 0 mA to 150 mA. A low drift
band gap reference and voltage comparator completes the
analog input peripheral set.
GPIO pins on the device power up in high impedance input
mode. In output mode, the software chooses between open-
drain mode and push-pull mode. The pull-up resistors can be
disabled and enabled in software. In GPIO output mode, the
inputs can remain enabled to monitor the pins. The GPIO pins
can also be programmed to handle digital or analog peripheral
signals, in which case the pin characteristics are matched to the
specific requirement.
The ADuCM320 can be configured so that the digital and analog
outputs will retain their output voltages and currents through
a watchdog or software reset sequence. Thus, a product can
remain functional even while the ADuCM320 is resetting itself.
The ADuCM320 has a low power ARM Cortex-M3 processor
and a 32-bit RISC machine that offers up to 100 MIPS peak
performance. Also integrated on chip are 2 × 128 kB Flash/EE
memory and 32 kB of SRAM. The flash comprises two separate
128 kB blocks supporting execution from one flash block and
simultaneous writing/erasing of the other flash block.
A large support ecosystem is available for the ARM Cortex-M3
processor to ease product development of the ADuCM320.
Access is via the ARM serial wire debug port (SW-DP). On-
chip factory firmware supports in-circuit serial download via
MDIO. These features are incorporated into a low cost
QuickStart development system supporting this precision
analog microcontroller family.
The ADuCM320 operates from an on-chip oscillator or a
16 MHz external crystal and a PLL at 80 MHz. This clock can
Rev. C | Page 4 of 30
Data Sheet
ADuCM320
SPECIFICATIONS
MICROCONTROLLER ELECTRICAL SPECIFICATIONS
AVDD = IOVDD = VDD1 = 2.9 V to 3.6 V (see Figure 14) maximum difference between supplies = 0.3 V, V REF = 2.5 V internal reference,
CORE = 80 MHz, TA = −40°C to +85°C, unless otherwise noted. PVDDx for IDACs = 1.8 V to 2.5 V. Power-up sequence must be VDD1,
f
IOVDDx, AVDDx, and then PVDDx, but no delays in the sequence are required.
Table 1.
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
ADC BASIC SPECIFICATIONS
Single-ended mode, unless
otherwise stated
ADC Power-Up Time
Data Rate
DC Accuracy1
Resolution1
Integral Nonlinearity
5
µs
fSAMPLE
1
MSPS
Bits
Bits
LSB
14
16
1 LSB = 2.5 V/214
Number of data bits
2.5 V internal reference; 1 LSB =
2.5 V/214
INL
1.75
1.75
0.75
0.75
3
LSB
LSB
LSB
LSB
2.5 V external reference; 1 LSB =
2.5 V/214
2.5 V internal reference; 1 LSB =
2.5 V/214
Differential Nonlinearity
DNL
−0.99
+1
2.5 V external reference; 1 LSB =
2.5 V/214
DC Code Distribution
ADC ENDPOINT ERRORS
Offset Error
ADC input 1.25 V; 1 LSB = 2.5 V/214
Input Buffer Off
Drift1
Input Buffer On
Drift1
200
−250
1
µV
µV/°C
µV
µV/°C
LSB
−2.25
−2.6
+1.2
+2
Using 2.5 V external reference
Using 2.5 V external reference
Matching compared to AIN8
Match
Full-Scale Error
Input Buffer Off
Gain Drift1
400
µV
µV/°C
−4
+2
+3
Full-scale error drift minus offset
error drift
Input Buffer On
Gain Drift1
−350
1
µV
µV/°C
−4.5
Full-scale error drift minus offset
error drift
Match
LSB
ADC DYNAMIC PERFORMANCE
fIN = 665.25 Hz sine wave, fSAMPLE =
100 kSPS; input filter = 15 Ω, 2 nF
Signal-to-Noise Ratio
SNR
THD
Includes distortion and noise
components
Input Buffer
Disabled
Enabled
Total Harmonic Distortion
Input Buffer
80
74
dB
dB
Disabled
Enabled
Peak Harmonic or Spurious Noise
Channel-to-Channel Crosstalk
ADC INPUT
−86
−83
−88
−90
dB
dB
dB
dB
Measured on adjacent channels
Input buffer not enabled
Input Voltage Ranges
Single-Ended Mode1
Differential Mode1
Compliance1
AGND4
−VREF
AGND4
0.9
VREF
+VREF
AVDD4
1.6
V
V
Voltage between differential pins
Common Mode1
Rev. C | Page 5 of 30
ADuCM320
Data Sheet
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
Leakage Current
AIN0 to AIN4, AIN6 to AIN15
±1.5
±±0
±ꢀ
nA
AIN5
nA
Pin shared with comparator
At 1 MSPS; buffer off
Input Current
μA/V
μA/V
μA/V
±6
≤800 kSPS; buffer off
±4
500 kSPS; buffer off;
ADCCNVC[±5:16] = 0x1E
Input Capacitance
ADC INPUT BUFFER±
Voltage Compliance1
Input Current
±0
pF
During ADC acquisition
When enabled by software
Reduced accuracy below 0.15 V
VIN = 0.15 V to ±.5 V, ADC converting
0.15
±.5
V
±100
±.51
nA
V
ON-CHIP VOLTAGE REFERENCE
0.47 μF from VREF_1V± to AGND4;
reference is measured with all
ADCs, VDACs, and IDACs enabled
Accuracy
±5
+4
mV
TA = ±5°C
Reference Temperature Coefficient1
Power Supply Rejection Ratio
Internal VREF Power-On Time
EXTERNAL REFERENCE INPUT
Range1
−34
1.8
−15
60
ppm/°C
dB
PSRR
50
ms
±.5
V
ADC
Input Current
±00
μA
BUFFERED REFFERNCE OUTPUT
Output Voltage
±.504
±8
V
Accuracy
Reference Temperature Coefficient1
mV
μV/°C
TA = ±5°C, load = 1.± mA
−55
−5
+40
1.±
100 nF from BUF_VREF±V5 to
AGND4
Output Impedance
Load Current1
10
Ω
TA = ±5°C
mA
VDAC CHANNEL SPECIFICATIONS
DC Accuracy1
Resolution1
Relative Accuracy4
Differential Nonlinearity4
RL = 5 kΩ, CL = 100 pF3
1 LSB = ±.5 V/±1±
1±
1±
Bits
Bits
LSB
LSB
Number of data bits
1 LSB = ±.5 V/±1±
INL
±4
±3
DNL
−0.ꢀꢀ
+1
Guaranteed monotonic, 1 LSB =
±.5 V/±1±
Offset Error
±15
mV
±.5 V internal reference, DAC
Output Code 0
Drift
Gain Error5
±13
±0.3
±0.4
6.5
μV/°C
%
±0.85
±1
0 V to internal VREF range
0 V to AVDD range
%
Drift
ppm/°C
%
Excluding reference drift
% of full scale on DAC0
Mismatch
0.1
Analog Outputs
Output Voltage Range 11
0.15
0.15
±.5
V
Output Voltage Range ±1
Output Impedance
DAC AC Characteristics
Output Settling Time
Glitch Energy
AVDDx− 0.15
V
±
Ω
10
μs
Settled to ±1 LSB
±±0
nV-sec
1 LSB change when the maximum
number of bits changes
simultaneously in the
DACxDAT register
IDAC CHANNEL SPECIFICATIONS
Resolution1
14
Bits
Combination of overlapping
11 bits and 5 bits
Full-Scale Output1
Supply Voltage Each Channel1
150
mA
V
1.8
±.5
Separate PVDDx supply for each
channel
Output Compliance Range
IDAC0, IDAC1
0.4
0.4
PVDDx − 400 mV
PVDDx − ±50 mV
V
V
See Figure 11
See Figure 11
IDAC±, IDAC3
Rev. C | Page 6 of 30
Data Sheet
ADuCM320
Parameter
Symbol
Min
Typ
Max
0.75
Unit
Test Conditions/Comments
Full-Scale Error
IDAC0, IDAC1
IDAC set to 85% of full scale
25°C to 105°C range
%
%
%
3.5
0.75
−40°C to +105°C range
−40°C to +105°C range
IDAC2, IDAC3
Full-Scale Error Drift
IDAC0, IDAC1
Internal VREF
−40°C to +85°C
25°C to 85°C
IDAC2, IDAC3
Integral Nonlinearity
Differential Nonlinearity
25
5
2
µA/°C
µA/°C
µA/°C
LSB
Internal VREF
1 LSB = 150 mA/211
Guaranteed 11-bit monotonic,
1 LSB = 150 mA/211
INL
DNL
3
6
+1.5
−0.99
−220
LSB
Zero-Scale Error
Zero-Scale Error Drift
IDAC0, IDAC1
IDAC2, IDAC3
Noise Current
Pull-Down Current
Settling Time
To 0.1%
50
µA
300
800
nA/°C
nA/°C
µA
2
IDACxCON[5:2] = 0
When enabled
IDACxCON[5:2] = 0
4 mA change from midscale
4 mA change from midscale
Pull-down enabled
Junction temperature
IDACxCON[5:2] = 0
−165
−100
µA
100
50
20
µs
µs
µs
°C
To 1%
Full Scale to 0 mA
Overheat Shutdown
PVDD ACPSRR
100 Hz
1 kHz
10 kHz
135
51
45
25
10
dB
dB
dB
dB
100 kHz
COMPARATOR
Input
Offset Voltage
Bias Current
Voltage Range1
Capacitance
Hysteresis1
10
1
mV
nA
V
pF
mV
µs
AGNDx
8.5
AVDDx – 1.2
15
7
7
When enabled in software
AFECOMP[2:1] = 0
Response Time
TEMPERATURE SENSOR
Indicates die temperature, see
Figure 9
Resolution
Accuracy1
0.5
°C
V
When precision calibrated by the
user6
ADC measured voltage for
temperature sensor channel without
calibration, T = 25°C
1.34
1.5
1.43
2.9
POWER-ON RESET
External Reset Minimum Pulse Width1
POR
2.85
V
µs
Minimum pulse width required on
external reset pin to trigger a reset
sequence
WATCHDOG TIMER
Timeout Period
FLASH/EE MEMORY
Endurance1
WDT
32
sec
Default at power-up
TJ = 85°C
10,000
20
Cycles
Years
Data Retention1
Rev. C | Page 7 of 30
ADuCM320
Data Sheet
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
DIGITAL INPUTS
Input Leakage Current
Logic 1 GPIO
1
10
nA
nA
VIH = VDD, pull-up resistor disabled
VIL = 0 V, pull-up resistor disabled
Logic 0 GPIO
PRTADDRx
Input Leakage Current
16
10
µA
V
VIN = 0 to 1.8 V, due to weak pull-
up resistors to 1.8 V
External resistor 91 kΩ 1% to
ground, range for CFP MSA high1
Input Voltage
0.84
1.5
Input Capacitance, All Pins Except MCK,
MDIO, PRTADDRx, and XTALx
pF
Input Capacitance
MCK, PRTADDRx
MDIO
6.5
8.5
pF
pF
Pin Capacitance
XTALI
XTALO
5
5
pF
pF
LOGIC INPUTS
GPIO Input Voltage
Low
VINL
VINH
0.25 × IOVDDx
V
V
High
0.58 × IOVDDx
MDIO
PRTADDRx Input Voltage
Low
High
VINL
VINH
0.36
0.36
V
V
0.84
0.84
MCK, MDIO Input Voltage
Setup time ≥10 ns; hold time
≥10 ns; MCK/MDIO
Low
High
VINL
VINH
V
V
XTALI Input Voltage
Low
High
VINL
VINH
1.1
1.7
V
V
Pull-Up Current
Pull-Down Current
LOGIC OUTPUTS
30
30
120
100
µA
µA
VIN = 0 V, see Figure 10
VIN = 3.3 V, see Figure 10
All digital outputs excluding
XTALO
GPIO Output Voltage7
High
Low
VOH
VOL
IOVDDx − 0.4
V
V
ISOURCE = 2 mA
ISINK = 2 mA
0.4
GPIO Short-Circuit Current1
11
mA
See Figure 13
MDIO
Output Voltage
High
Low
VOH
VOL
1.0
V
V
ISOURCE = 4 mA
ISINK = 4 mA
0.2
Delay Time
100
ns
MCK to MDIO out
OSCILLATORS
Internal System Oscillator
Accuracy
16
0.5
MHz
%
3
System PLL
External Crystal Oscillator
80
16
MHz
MHz
Main system clock
Can be selected in place of
internal oscillator
32 kHz Internal Oscillator
Accuracy
External Clock
32.768
5
kHz
%
MHz
Use for watchdog
20
80
0.05
Can be selected in place of PLL
Processor clock = 80 MHz
START-UP TIME
At Power-On
After Other Reset
From All Power-Down Modes
40
1.5
1.25
ms
ms
µs
POR to first user code execution
Reset to first user code execution
Rev. C | Page 8 of 30
Data Sheet
ADuCM320
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
PROGRAMMABLE LOGIC ARRAY
Propagation Delay
Pin
PLA
17
ns
ns
From input pin to output pin
Per PLA cell
Element
1.5
EXTERNAL INTERRUPTS
Pulse Width1
Level Triggered
7
1
ns
ns
Edge Triggered
POWER REQUIREMENTS8
Power Supply Voltage Range
AVDDx to AGNDx and IOVDDx
to DGNDx1
2.9
3.3
3.6
V
Analog Power Supply Currents
AVDDx Current
6.3
4
mA
mA
mA
Analog peripherals in idle mode
All GPIO pull-up resistors enabled
Digital Power Supply Current
IOVDDx Current in Normal Mode
VDDx Current
Normal Mode9
29
CD = 0 (80 MHz clock) executing
typical code
20
10
16
8
mA
mA
mA
mA
mA
CD = 1 executing typical code
CD = 7 executing typical code
CORE_SLEEP Mode9
SYS_SLEEP Mode9
Hibernate Mode9
Additional Power Supply Currents
ADC
6.6
4.1
mA
mA
mA
μA
Continuously converting at 100 kSPS
Both buffers enabled
ADC Input Buffer
IDAC
4.0
16.5
340
Excluding load current
DAC
Per powered up DAC, excluding
load current
Total Supply Current
35
40
45
mA
VDD1, IOVDDx, AVDDx connected
together; condition when entering
user code: peripheral clocks on,
peripherals idle, no load currents
Thermal Performance
Impedance Junction to Ambient
45
°C/W
JEDEC 2S2P
1 These numbers are not production tested but are guaranteed by design and/or characterization data at production release.
2 Enabling the input buffer changes the ADC input characteristics as described in this subsection.
3 The data in this section also applies for a load of RL = 1 kΩ and CL = 100 pF to GND but only for 0 V to 2.5 V. However, this is not production tested.
4 DAC linearity is calculated using a reduced code range of 100 to 3900.
5 DAC gain error is calculated using a reduced code range of 100 to an internal 2.5 V VREF
.
6 Due to self heating, internal temperature measurements cannot be used to predict external temperatures. This value is only relevant after user calibration and only for
internal and external conditions identical to those at calibration.
7 The average current from all GPIO pins must not exceed 3 mA per pin.
8 Power figures exclude any load currents to external circuits.
9 See the ADuCM320 reference manual, How to Set up and Use the ADuCM320.
Rev. C | Page 9 of 30
ADuCM320
Data Sheet
AVDD = IOVDD = VDD1 = 2.9 V to 3.6 V maximum difference between supplies = 0.3 V, VREF = 2.5 V internal reference, fCORE = 80 MHz,
TA = −40°C to +105°C, unless otherwise noted. PVDDx for IDACs = 1.8 V to 2.5 V. Power-up sequence must be VDD1, IOVDDx, AVDDx, and
then PVDDx, but no delays in the sequence are required.
Table 2.
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
ADC BASIC SPECIFICATIONS
Single-ended mode, unless
otherwise stated
ADC Power-Up Time
Data Rate
DC Accuracy1
Resolution1
Integral Nonlinearity
5
µs
fSAMPLE
1
MSPS
Bits
Bits
LSB
14
16
1 LSB = 2.5 V/214
Number of data bits
2.5 V internal reference; 1 LSB =
2.5 V/214
INL
1.75
1.75
0.75
0.75
3
LSB
LSB
LSB
LSB
2.5 V external reference; 1 LSB =
2.5 V/214
2.5 V internal reference; 1 LSB =
2.5 V/214
Differential Nonlinearity
DNL
−0.99
+1.5
2.5 V external reference; 1 LSB =
2.5 V/214
DC Code Distribution
ADC ENDPOINT ERRORS
Offset Error
ADC input 1.25 V; 1 LSB = 2.5 V/214
Input Buffer Off
Drift1
200
−250
1
µV
µV/°C
µV
µV/°C
LSB
−2.25
−3
+1.2
+2
Using 2.5 V external reference
Input Buffer On
Drift1
Match
Using 2.5 V external reference
Matching compared to AIN8
Full-Scale Error
Input Buffer Off
Gain Drift1
400
µV
µV/°C
−4.3
−4.5
+2
+3
Full-scale error drift minus offset
error drift
Input Buffer On
Gain Drift1
−350
1
µV
µV/°C
Full-scale error drift minus offset
error drift
Match
LSB
ADC DYNAMIC PERFORMANCE
fIN = 665.25 Hz sine wave, fSAMPLE =
100 kSPS; input filter = 15 Ω, 2 nF
Signal-to-Noise Ratio
SNR
THD
Includes distortion and noise
components
Input Buffer
Disabled
Enabled
Total Harmonic Distortion
Input Buffer
80
74
dB
dB
Disabled
Enabled
−86
−83
−88
−90
dB
dB
dB
dB
Peak Harmonic or Spurious Noise
Channel-to-Channel Crosstalk
ADC INPUT
Measured on adjacent channels
Input buffer not enabled
Input Voltage Ranges
Single-Ended Mode1
Differential Mode1
Compliance1
AGND4
−VREF
AGND4
0.9
VREF
+VREF
AVDD4
1.6
V
V
Voltage between differential pins
Common Mode1
Rev. C | Page 10 of 30
Data Sheet
ADuCM320
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
Leakage Current
AIN0 to AIN4, AIN6 to AIN15
±1.5
±±0
±ꢀ
nA
AIN5
nA
Pin shared with comparator
At 1 MSPS; buffer off
Input Current
μA/V
μA/V
μA/V
±6
≤800 kSPS; buffer off
±4
500 kSPS; buffer off;
ADCCNVC[±5:16] = 0x1E
Input Capacitance
ADC INPUT BUFFER±
Voltage Compliance1
Input Current
±0
pF
During ADC acquisition
When enabled by software
Reduced accuracy below 0.15 V
VIN = 0.15 V to ±.5 V, ADC converting
0.15
±.5
V
±100
±.51
nA
V
ON-CHIP VOLTAGE REFERENCE
0.47 μF from VREF_1V± to AGND4;
reference is measured with all
ADCs, VDACs, and IDACs enabled
Accuracy
±5
+4
mV
TA = ±5°C
Reference Temperature Coefficient1
Power Supply Rejection Ratio
Internal VREF Power-On Time
EXTERNAL REFERENCE INPUT
Range1
−34
1.8
−15
60
ppm/°C
dB
PSRR
50
ms
±.5
V
ADC
Input Current
±00
μA
BUFFERED REFFERNCE OUTPUT
Output Voltage
±.504
±8
V
Accuracy
Reference Temperature Coefficient1
mV
μV/°C
TA = ±5°C, load = 1.± mA
−55
−5
+40
1.±
100 nF from BUF_VREF±V5 to
AGND4
Output Impedance
Load Current1
10
Ω
TA = ±5°C
mA
VDAC CHANNEL SPECIFICATIONS
DC Accuracy1
Resolution1
Relative Accuracy4
Differential Nonlinearity4
RL = 5 kΩ, CL = 100 pF3
1 LSB = ±.5 V/±1±
1±
1±
Bits
Bits
LSB
LSB
Number of data bits
1 LSB = ±.5 V/±1±
INL
±4
±3
DNL
−0.ꢀꢀ
+1
Guaranteed monotonic, 1 LSB =
±.5 V/±1±
Offset Error
±15
mV
±.5 V internal reference, DAC
Output Code 0
Drift
Gain Error5
±13
±0.3
±0.4
6.5
μV/°C
%
±0.85
±1
0 V to internal VREF range
0 V to AVDD range
%
Drift
ppm/°C
%
Excluding reference drift
% of full scale on DAC0
Mismatch
0.1
Analog Outputs
Output Voltage Range 11
0.15
0.15
±.5
V
Output Voltage Range ±1
Output Impedance
DAC AC Characteristics
Output Settling Time
Glitch Energy
AVDDx− 0.15
V
±
Ω
10
μs
Settled to ±1 LSB
±±0
nV-sec
1 LSB change when the maximum
number of bits changes
simultaneously in the
DACxDAT register
IDAC CHANNEL SPECIFICATIONS
Resolution1
14
Bits
Combination of overlapping
11 bits and 5 bits
Full-Scale Output1
Supply Voltage Each Channel1
150
mA
V
1.8
±.5
Separate PVDDx supply for each
channel
Output Compliance Range
IDAC0, IDAC1
0.4
0.4
PVDDx − 400 mV
PVDDx − ±50 mV
V
V
See Figure 11
See Figure 11
IDAC±, IDAC3
Rev. C | Page 11 of 30
ADuCM320
Data Sheet
Parameter
Symbol
Min
Typ
Max
0.75
Unit
Test Conditions/Comments
Full-Scale Error
IDAC0, IDAC1
IDAC set to 85% of full scale
25°C to 105°C range
%
%
%
3.5
0.75
IDAC2, IDAC3
Full-Scale Error Drift
IDAC0, IDAC1
Internal VREF
−40°C to 105°C
25°C to 105°C
IDAC2, IDAC3
Integral Nonlinearity
Differential Nonlinearity
25
5
2
µA/°C
µA/°C
µA/°C
LSB
Internal VREF
1 LSB = 150 mA/211
Guaranteed 11-bit monotonic,
1 LSB = 150 mA/211
INL
DNL
3
6
+1.5
−0.99
−220
LSB
Zero-Scale Error
Zero-Scale Error Drift
IDAC0, IDAC1
IDAC2, IDAC3
Noise Current
Pull-Down Current
Settling Time
To 0.1%
50
µA
300
800
nA/°C
nA/°C
µA
2
IDACxCON[5:2] = 0
When enabled
IDACxCON[5:2] = 0
4 mA change from midscale
4 mA change from midscale
Pull-down enabled
Junction temperature
IDACxCON[5:2] = 0
−165
−100
µA
100
50
20
µs
µs
µs
°C
To 1%
Full Scale to 0 mA
Overheat Shutdown
PVDD ACPSRR
100 Hz
1 kHz
10 kHz
135
51
45
25
10
dB
dB
dB
dB
100 kHz
COMPARATOR
Input
Offset Voltage
Bias Current
Voltage Range1
Capacitance
Hysteresis1
10
1
mV
nA
V
pF
mV
µs
AGNDx
8.5
AVDDx – 1.2
15
7
7
When enabled in software
AFECOMP[2:1] = 0
Response Time
TEMPERATURE SENSOR
Indicates die temperature, see
Figure 9
Resolution
Accuracy1
0.5
°C
V
When precision calibrated by the
user6
ADC measured voltage for
temperature sensor channel without
calibration, T = 25°C
1.34
1.5
1.43
2.9
POWER-ON RESET
External Reset Minimum Pulse Width1
POR
2.85
V
µs
Minimum pulse width required on
external reset pin to trigger a reset
sequence
WATCHDOG TIMER
Timeout Period
FLASH/EE MEMORY
Endurance1
WDT
32
sec
Default at power-up
TJ = 85°C
10,000
20
Cycles
Years
Data Retention1
Rev. C | Page 12 of 30
Data Sheet
ADuCM320
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
DIGITAL INPUTS
Input Leakage Current
Logic 1 GPIO
1
10
nA
nA
VIH = VDD, pull-up resistor disabled
VIL = 0 V, pull-up resistor disabled
Logic 0 GPIO
PRTADDRx
Input Leakage Current
16
10
µA
V
VIN = 0 to 1.8 V, due to weak pull-
up resistors to 1.8 V
External resistor 91 kΩ 1% to
ground, range for CFP MSA high1
Input Voltage
0.84
1.5
Input Capacitance, All Pins Except MCK,
MDIO, PRTADDRx, and XTALx
pF
Input Capacitance
MCK, PRTADDRx
MDIO
6.5
8.5
pF
pF
Pin Capacitance
XTALI
XTALO
5
5
pF
pF
LOGIC INPUTS
GPIO Input Voltage
Low
VINL
VINH
0.25 × IOVDDx
V
V
High
0.58 × IOVDDx
MDIO
PRTADDRx Input Voltage
Low
High
VINL
VINH
0.36
0.36
V
V
0.84
0.84
MCK, MDIO Input Voltage
Setup time ≥10 ns; hold time
≥10 ns; MCK/MDIO
Low
High
VINL
VINH
V
V
XTALI Input Voltage
Low
High
VINL
VINH
1.1
1.7
V
V
Pull-Up Current
Pull-Down Current
LOGIC OUTPUTS
30
30
120
100
µA
µA
VIN = 0 V, see Figure 10
VIN = 3.3 V, see Figure 10
All digital outputs excluding
XTALO
GPIO Output Voltage7
High
Low
VOH
VOL
IOVDDx − 0.4
V
V
ISOURCE = 2 mA
ISINK = 2 mA
0.4
GPIO Short-Circuit Current1
11
mA
See Figure 13
MDIO
Output Voltage
High
Low
VOH
VOL
1.0
V
V
ISOURCE = 4 mA
ISINK = 4 mA
0.2
Delay Time
100
ns
MCK to MDIO out
OSCILLATORS
Internal System Oscillator
Accuracy
16
0.5
MHz
%
3
System PLL
External Crystal Oscillator
80
16
MHz
MHz
Main system clock
Can be selected in place of
internal oscillator
32 kHz Internal Oscillator
Accuracy
32.768
5
kHz
%
Use for watchdog
20
80
External Clock
0.05
MHz
Can be selected in place of PLL
Processor clock = 80 MHz
START-UP TIME
At Power-On
After Other Reset
From All Power-Down Modes
40
1.5
1.25
ms
ms
µs
POR to first user code execution
Reset to first user code execution
Rev. C | Page 13 of 30
ADuCM320
Data Sheet
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
PROGRAMMABLE LOGIC ARRAY
Propagation Delay
Pin
PLA
17
ns
ns
From input pin to output pin
Per PLA cell
Element
1.5
EXTERNAL INTERRUPTS
Pulse Width1
Level Triggered
7
1
ns
ns
Edge Triggered
POWER REQUIREMENTS8
Power Supply Voltage Range
AVDDx to AGNDx and IOVDDx
to DGNDx1
2.9
3.3
3.6
V
Analog Power Supply Currents
AVDDx Current
6.3
4
mA
mA
mA
Analog peripherals in idle mode
All GPIO pull-up resistors enabled
Digital Power Supply Current
IOVDDx Current in Normal Mode
VDDx Current
Normal Mode9
29
CD = 0 (80 MHz clock) executing
typical code
20
10
16
8
mA
mA
mA
mA
mA
CD = 1 executing typical code
CD = 7 executing typical code
CORE_SLEEP Mode9
SYS_SLEEP Mode9
Hibernate Mode9
6.6
Additional Power Supply Currents
ADC
4.1
mA
Continuously converting at
100 kSPS
ADC Input Buffer
4.0
mA
mA
μA
Both buffers enabled
Excluding load current
IDAC
DAC
16.5
340
Per powered up DAC, excluding
load current
Total Supply Current
35
40
45
mA
VDD1, IOVDDx, AVDDx connected
together; condition when entering
user code: peripheral clocks on,
peripherals idle, no load currents
Thermal Performance
Impedance Junction to Ambient
45
°C/W
JEDEC 2S2P
1 These numbers are not production tested but are guaranteed by design and/or characterization data at production release.
2 Enabling the input buffer changes the ADC input characteristics as described in this subsection.
3 The data in this section also applies for a load of RL = 1 kΩ and CL = 100 pF to GND but only for 0 V to 2.5 V. However, this is not production tested.
4 DAC linearity is calculated using a reduced code range of 100 to 3900.
5 DAC gain error is calculated using a reduced code range of 100 to an internal 2.5 V VREF
.
6 Due to self heating, internal temperature measurements cannot be used to predict external temperatures. This value is only relevant after user calibration and only for
internal and external conditions identical to those at calibration.
7 The average current from all GPIO pins must not exceed 3 mA per pin.
8 Power figures exclude any load currents to external circuits.
9 See the ADuCM320 reference manual, How to Set up and Use the ADuCM320
Rev. C | Page 14 of 30
Data Sheet
ADuCM320
TIMING SPECIFICATIONS
I2C Timing
Table 3. I2C Timing in Standard Mode (100 kHz)
Slave
Typ
Parameter
Description
Min
4.7
4.0
4.0
250
0
4.7
4.0
4.7
Max
Unit
µs
ns
µs
ns
µs
µs
µs
µs
µs
ns
µs
µs
tL
tH
SCL low pulse width
SCL high pulse width
Start condition hold time
Data setup time
Data hold time (SDA held internally for 300 ns after falling edge of SCL)
Setup time for repeated start
Stop condition setup time
Bus-free time between a stop condition and a start condition
Rise time for both SLC and SDA
Fall time for both SLC and SDA
Data valid time
tSHD
tDSU
tDHD
tRSU
tPSU
tBUF
tR
tF
tVD;DAT
tVD;ACK
3.45
1
15
300
3.45
3.45
Data valid acknowledge time
Table 4. I2C Timing in Fast Mode (400 kHz)
Slave
Typ
Parameter
Description
Min
1.3
0.6
0.3
100
0
0.6
0.3
1.3
20
Max
Unit
µs
ns
µs
ns
µs
µs
µs
µs
ns
ns
µs
µs
tL
tH
SCL low pulse width
SCL high pulse width
Start condition hold time
Data setup time
Data hold time (SDA held internally for 300 ns after falling edge of SCL)
Setup time for repeated start
Stop condition setup time
Bus-free time between a stop condition and a start condition
Rise time for both SCL and SDA
Fall time for both SCL and SDA
Data valid time
tSHD
tDSU
tDHD
tRSU
tPSU
tBUF
tR
tF
tVD;DAT
tVD;ACK
300
300
0.9
15
Data valid acknowledge time
0.9
tBUF
tR
SDA (I/O)
MSB
LSB
ACK
MSB
tDSU
tDSU
tDHD
tRSU
tF
tDHD
tPSU
tR
tVD; DAT
tH
tSHD
tVD; ACK
1
2–7
8
9
1
SCL (I)
tL
P
S
S(R)
tF
STOP
START
REPEATED
START
CONDITION CONDITION
Figure 2. I2C Compatible Interface Timing
Rev. C | Page 15 of 30
ADuCM320
Data Sheet
SPI Timing
Table 5. SPI Master Mode Timing (Phase Mode = 1)
Parameter
Description
Min
Typ
Max
Unit
ns
tSL
SCLK low pulse width
(SPIDIV + 1) × tHCLK/2
tSH
SCLK high pulse width
Data output valid after SCLK edge
Data input setup time before SCLK edge
Data input hold time after SCLK edge
Data output fall time
(SPIDIV + 1) × tHCLK/2
3
½ SCLK
SCLK
SCLK
25
ns
ns
ns
ns
ns
ns
ns
tDAV
tDSU
tDHD
tDF
tDR
tSR
0
Data output rise time
SCLK rise time
25
tSF
SCLK fall time
20
ns
SCLK
(POLARITY = 0)
tSH
tSL
tSR
tSF
SCLK
(POLARITY = 1)
tDAV
tDF
tDR
MOSI
MISO
MSB
BITS 6 TO 1
LSB
MSB IN
BITS 6 TO 1
LSB IN
tDSU
tDHD
Figure 3. SPI Master Mode Timing (Phase Mode = 1)
Rev. C | Page 16 of 30
Data Sheet
ADuCM320
Table 6. SPI Master Mode Timing (Phase Mode = 0)
Parameter
Description
Min
Typ
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSL
tSH
SCLK low pulse width
SCLK high pulse width
(SPIDIV + 1) × tHCLK/2
(SPIDIV + 1) × tHCLK/2
3
½ SCLK
SCLK
SCLK
25
25
20
tDAV
tDOSU
tDSU
tDHD
tDF
tDR
tSR
tSF
Data output valid after SCLK edge
Data output setup before SCLK edge
Data input setup time before SCLK edge
Data input hold time after SCLK edge
Data output fall time
Data output rise time
SCLK rise time
SCLK fall time
0
20
SCLK
(POLARITY = 0)
tSH
tSL
tSR
tSF
SCLK
(POLARITY = 1)
tDAV
tDOSU
tDF
tDR
MOSI
MISO
MSB
BITS 6 TO 1
LSB
MSB IN
BITS 6 TO 1
LSB IN
tDSU
tDHD
Figure 4. SPI Master Mode Timing (Phase Mode = 0)
Rev. C | Page 17 of 30
ADuCM320
Data Sheet
Table 7. SPI Slave Mode Timing (Phase Mode = 1)
Parameter
Description
Min
Typ
Max
Unit
tCS
CS to SCLK edge
10
ns
tCS
M
CS
SCLKx
ns
high time between active periods
tSL
tSH
SCLK low pulse width
SCLK high pulse width
Data output valid after SCLK edge
Data input setup time before SCLK edge
Data input hold time after SCLK edge
Data output fall time
Data output rise time
SCLK rise time
SCLK fall time
CS high after SCLK edge
(SPIDIV + 1) × tHCLK
(SPIDIV + 1) × tHCLK
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tDAV
tDSU
tDHD
tDF
tDR
tSR
10
10
25
25
1
1
20
tSF
tSFS
tCSM
CS
tSFS
tCS
SCLK
(POLARITY = 0)
tSH
tSL
tSR
tSF
SCLK
(POLARITY = 1)
tDAV
tDF
tDR
MISO
MOSI
MSB
BITS 6 TO 1
LSB
MSB IN
BITS 6 TO 1
LSB IN
tDSU
tDHD
Figure 5. SPI Slave Mode Timing (Phase Mode = 1)
Rev. C | Page 18 of 30
Data Sheet
ADuCM320
Table 8. SPI Slave Mode Timing (Phase Mode = 0)
Parameter
Description
Min
Typ
Max
Unit
tCS
CS to SCLK edge
10
ns
tCS
M
CS
SCLKx
ns
high time between active periods
tSL
tSH
tDAV
tDSU
tDHD
tDF
tDR
tSR
tSF
tDOCS
tSFS
SCLK low pulse width
SCLK high pulse width
Data output valid after SCLK edge
Data input setup time before SCLK edge
Data input hold time after SCLK edge
Data output fall time
Data output rise time
SCLK rise time
SCLK fall time
Data output valid after CS edge
CS high after SCLK edge
(SPIDIV + 1) × tHCLK
(SPIDIV + 1) × tHCLK
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
10
25
25
1
1
20
10
tCSM
CS
tCS
tSFS
SCLK
(POLARITY = 0)
tSH
tSL
tSF
tSR
SCLK
(POLARITY = 1)
tDAV
tDOCS
tDF
tDR
MISO
MOSI
MSB
BITS 6 TO 1
LSB
MSB IN
BITS 6 TO 1
LSB IN
tDSU
tDHD
Figure 6. SPI Slave Mode Timing (Phase Mode = 0)
Rev. C | Page 19 of 30
ADuCM320
Data Sheet
Table 9. MDIO vs MDC Timing
Parameter
Description
Min
10
10
Typ
Max
Unit
ns
ns
tSETUP
tHOLD
tDELAY
MDIO setup before MCK edge
MDIO valid after MCK edge
Data output after MCK edge
100
ns
MCK
VIH
VIL
CFP
INPUT
MDIO
VIH
VIL
CFP
INPUT
MDIO
VOH
VOL
CFP
OUTPUT
tSETUP tHOLD
tDELAY
Figure 7. MDIO Timing
Rev. C | Page 20 of 30
Data Sheet
ADuCM320
ABSOLUTE MAXIMUM RATINGS
All requirements applicable to each pin must be met. Where
multiple limits apply to a pin each one must be met individually.
The limits apply according to the functionality of the pins at the
time. Pins that can be either analog or digital, that is, that have
two types indicated in the pin descriptions, must meet the limits
for both types. For pin types, see Table 11.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
When powered up, it is required that all ground pins plus
ADC_REFN be connected together to a node referred to as
GND in Table 10. The limits that are listed must be reduced by
any difference between any GNDs. Also, it is required that
AVDD3 is connected to AVDD4 and that IOVDD1 to IOVDD3
are connected together.
ESD CAUTION
Table 10. Absolute Maximum Ratings
Parameter
Rating
Any Pin to GND
Any PVDDx Pin to GND
MDIO1, MCK, and PRTADDR0-4 in
MDIO Mode to GND
−0.3 V to +3.9 V
−0.3 V to +2.8 V
−0.3 V to +2.1 V
Between Any of AVDDx, IOVDDx, and −0.3 V to +0.3 V
VDD1 Pins
Any Type I Pin to GND2
−0.3 V to IOVDDx + 0.3 V
−0.3 V to AVDDx + 0.3 V
−0.3 V to PVDDx + 0.3 V
Any Type AI or AO Pin to GND3
Any IDACx, CDAMPx, IDACTST, IREF
to GND
ADC_REFP to GND
−0.3 V to AVDDx + 0.3 V
0 mA to 30 mA
−30 mA to 0 mA
1 W
Total Positive GPIO Pin Currents
Total Negative GPIO Pin Currents
Maximum Power Dissipation
Operating Ambient Temperature
Range
−40°C to +105°C
Storage Temperature Range
Operating Junction Temperature
Range
−65°C to +160°C
−40°C to +120°C
ESD HBM
ESD FICDM
2 kV
1 kV
1 Note this pin is always in MDIO mode.
2 This limit does not apply if no current can be drawn by external circuits on
IOVDDx because then IOVDD follows to a suitable level.
3 This limit does not apply if no current can be drawn by external circuits on
AVDDx because then AVDD follows to a suitable level.
Rev. C | Page 21 of 30
ADuCM320
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
9
10
11
IDAC_
TST
A
B
C
D
E
F
PVDD2
IDAC2
PGND
IDAC3
PVDD3
PVDD1
IDAC1
IREF
IDAC0
PVDD0
P1.2/
PWM0/
PLAI[6]
P3.3/
PRTADDR3/
PLAI[15]
P1.1/SOUT/
PLACLK1/
PLAI[5]
P1.0/SIN/
ECLKIN/
PLAI[4]
RESET
IOVDD1
IOGND1
CDAMP0 CDAMP2
PGND
CDAMP3
CDAMP1
P2.2/
P1.4/
PWM2/
SCLK1/
PLAO[10]
P1.5/
PWM3/
MISO1/
PLAO[11]
P1.6/
PWM4/
MOSI1/
PLAO[12]
P2.0/IRQ2/
P1.7/IRQ1/
PWM5/
P0.0/
SCLK0/
PLAI[0]
P1.3/
PWM1/
PLAI[7]
P3.4/
PRTADDR4/
PLAO[26]
IRQ4/POR/
PWMTRIP/
P2.3/BM
CLKOUT/
PLACLK2/
CS1/
PLAI[10]
PLAI[8]
PLAO[13]
P2.4/IRQ5/
ADCCONV/
PWM6/
P0.1/
MISO0/
PLAI[1]
P0.2/
MOSI0/
PLAI[2]
P3.2/
PRTADDR2/
PLAI[14]
DGND2
SWDIO
IOVDD2
IOGND2
VREF_1V2
AVDD4
PLAO[18]
P0.3/
P0.4/
SCL0/
PLAO[2]
P0.5/
SDA0/
PLAO[3]
IRQ0/CS0/
PLACLK0/
PLAI[3]
SWCLK
ADuCM320
P2.6/
IRQ7/
PLAO[20] PLAO[5]
P0.7/
SDA1/
P0.6/
SCL1/
PLAO[4]
AVDD_
REG1
AVDD_
REG0
TOP VIEW
(Not to Scale)
P2.7/
IRQ8/
PLAO[21]
P3.1/
PRTADDR1/
PLAI[13]
P3.0/
PRTADDR0/
PLAI[12]
AIN15/
P4.7
AIN13/
P4.5
G
P3.5/
MCK/
AIN14/
P4.6
AIN12/
P4.4
XTALO
XTALI
AGND4
MDIO
H
J
PLAO[27]
AIN11/
BUF_
VREF2V5
VDAC7/
P5.2
VDAC4
AIN2
AIN3
AIN4
IOVDD3
IOGND3
DGND1
AGND1
VDAC1
AIN0
VDD1
AIN1
AIN7
AIN6
AIN5
AIN10
VDAC6/
P5.1
AIN9/
P4.3
ADC_
REFP
VDAC3/
P5.0
DVDD_
2V5
K
L
AGND2
AGND3
VDAC2/
P3.7/
PLAO[29]
VDAC0/
P5.3
AIN8/
P4.2
ADC_
REFN
DVDD_1V8
VDAC5
AVDD3
Figure 8. Pin Configuration
Table 11. Pin Function Descriptions
Pin
No.
Mnemonic
RESET
Type1
Description
B2
I
Reset Input (Active Low). An internal pull-up resistor is included.
Digital I/O Port 0.0 (P0.0).
C2
P0.0/SCLK0/PLAI[0]
I/O
SPI0 Clock (SCLK0).
Input to PLA Element 0 (PLAI[0]).
Digital I/O Port 0.1 (P0.1).
SPI0 Master In, Slave Out (MISO0).
Input to PLA Element 1 (PLAI[1]).
Digital I/O Port 0.2 (P0.2).
SPI0 Master Out, Slave In (MOSI0).
Input to PLA Element 2 (PLAI[2]).
Digital I/O Port 0.3 (P0.3).
D2
D1
E3
P0.1/MISO0/PLAI[1]
P0.2/MOSI0/PLAI[2]
I/O
I/O
I/O
P0.3/IRQ0/CS0/PLACLK0/PLAI[3]
External Interrupt 0 (IRQ0).
SPI0 Chip Select 0 (CS0). When using SPI0, configure this pin as CS0.
PLA Clock 0 (PLACLK0).
Input to PLA Element 3 (PLAI[3]).
Digital I/O Port 0.4 (P0.4).
E2
E1
P0.4/SCL0/PLAO[2]
P0.5/SDA0/PLAO[3]
I/O
I/O
I2C0 Serial Clock (SCL0).
Output of PLA Element 2 (PLAO[2]).
Digital I/O Port 0.5 (P0.5).
I2C0 Serial Data (SDA0).
Output of PLA Element 3 (PLAO[3]).
Rev. C | Page 22 of 30
Data Sheet
ADuCM320
Pin
No.
Mnemonic
Type1
Description
F3
P0.6/SCL1/PLAO[4]
I/O
Digital I/O Port 0.6 (P0.6).
I2C1 Serial Clock (SCL1).
Output of PLA Element 4 (PLAO[4]).
Digital I/O Port 0.7 (P0.7).
I2C1 Serial Data (SDA1).
Output of PLA Element 5 (PLAO[5]).
Digital I/O Port 1.0 (P1.0).
UART Input (SIN).
F2
B9
P0.7/SDA1/PLAO[5]
I/O
I/O
P1.0/SIN/ECLKIN/PLAI[4]
External Input Clock (ECLKIN).
Input to PLA Element 4 (PLAI[4]).
Digital I/O Port 1.1 (P1.1).
UART Output (SOUT)
B10
P1.1/SOUT/PLACLK1/PLAI[5]
I/O
PLA Clock 1(PLACLK1).
Input to PLA Element 5 (PLAI[5]).
Digital I/O Port 1.2 (P1.2).
PWM Output 0 (PWM0).
Input to PLA Element 6 (PLAI[6]).
Digital I/O Port 1.3 (P1.3).
PWM Output 1 (PWM1).
Input to PLA Element 7 (PLAI[7]).
Digital I/O Port 1.4 (P1.4).
PWM Output 2 (PWM2).
B11
C6
P1.2/PWM0/PLAI[6]
I/O
I/O
I/O
P1.3/PWM1/PLAI[7]
C7
P1.4/PWM2/SCLK1/PLAO[10]
SPI1 Clock (SCLK1).
Output of PLA Element 10 (PLAO[10]).
Digital I/O Port 1.5 (P1.5).
PWM Output 3 (PWM3).
SPI1 Master In, Slave Out (MISO1).
Output of PLA Element 11 (PLAO[11]).
Digital I/O Port 1.6 (P1.6).
PWM Output 4 (PWM4).
SPI1 Master Out, Slave Input (MOSI1).
Output of PLA Element 12 (PLAO[12]).
Digital I/O Port 1.7 (P1.7).
External Interrupt 1 (IRQ1).
PWM Output 5 (PWM5).
C8
P1.5/PWM3/MISO1/PLAO[11]
P1.6/PWM4/MOSI1/PLAO[12]
P1.7/IRQ1/PWM5/CS1/PLAO[13]
I/O
I/O
I/O
C9
C10
SPI1 Chip Select 1 (CS1). When using SPI1, configure this pin as CS1.
Output of PLA Element 13 (PLAO[13]).
Digital I/O Port 2.0 (P2.0).
External Interrupt 2 (IRQ2).
PWM Trip (PWMTRIP).
PLA Input Clock 2 (PLACLK2).
Input to PLA Element 8 (PLAI[8]).
Digital I/O Port 2.2 (P2.2).
C5
C4
P2.0/IRQ2/PWMTRIP/PLACLK2/PLAI[8] I/O
P2.2/IRQ4/POR/CLKOUT/PLAI[10]
I/O
I/O
External Interrupt 4 (IRQ4).
Reset Output (POR). This pin function is an output and it is the default for Pin C4.
Clock Output (CLKOUT).
Input to PLA Element 10 (PLAI[10]).
Digital I/O Port 2.3 (P2.3).
C3
P2.3/BM
Boot Mode (BM). This pin determines the start-up sequence after every reset.
Pull-up is enabled at power-up.
Rev. C | Page 23 of 30
ADuCM320
Data Sheet
Pin
No.
Mnemonic
P2.4/IRQ5/ADCCONV/PWM6/PLAO[18] I/O
Type1
Description
D9
Digital I/O Port 2.4 (P2.4).
External Interrupt 5 (IRQ5).
External Input to Start ADC Conversions (ADCCONV).
PWM Output 6 (PWM6).
Output of PLA Element 18 (PLAO[18]).
Digital I/O Port 2.6 (P2.6).
External Interrupt 7 (IRQ7).
Output of PLA Element 20 (PLAO[20]).
Digital I/O Port 2.7 (P2.7).
External Interrupt 8 (IRQ8).
F1
G1
G3
P2.6/IRQ7/PLAO[20]
P2.7/IRQ8/PLAO[21]
P3.0/PRTADDR0/PLAI[12]
I/O
I/O
I/O
Output of PLA Element 21 (PLAO[21]).
Digital I/O Port 3.0 (P3.0).
MDIO Port Address Bit 0 (PRTADDR0). See the digital inputs parameter in Table 1
for details.
Input to PLA Element 12 (PLAI[12]).
Digital I/O Port 3.1 (P3.1).
MDIO Port Address Bit 1 (PRTADDR1). See the digital inputs parameter in Table 1
for details.
Input to PLA Element 13 (PLAI[13]).
Digital I/O Port 3.2 (P3.2).
MDIO Port Address Bit 2 (PRTADDR2). See the digital inputs parameter in Table 1
for details.
Input to PLA Element 14 (PLAI[14]).
Digital I/O Port 3.3 (P3.3).
MDIO Port Address Bit 3 (PRTADDR3). See the digital inputs parameter in Table 1
for details.
Output of PLA Element 15 (PLAI[15]).
Digital I/O Port 3.4 (P3.4).
MDIO Port Address Bit 4 (PRTADDR4). See the digital inputs parameter in Table 1
for details.
G2
D3
B3
P3.1/PRTADDR1/PLAI[13]
P3.2/PRTADDR2/PLAI[14]
P3.3/PRTADDR3/PLAI[15]
P3.4/PRTADDR4/PLAO[26]
P3.5/MCK/PLAO[27]
I/O
I/O
I/O
I/O
I/O
C11
H1
Output of PLA Element 26 (PLAO[26]).
Digital I/O Port 3.5 (P3.5).
MDIO Clock (MCK) See the digital inputs parameter in Table 1 for more details.
Output of PLA Element 27 (PLAO[27]).
H3
E9
E10
F11
MDIO
I/O
I
I/O
S
MDIO Data.
Serial Wire Debug Clock.
Serial Wire Bidirectional Data.
1.2 V Reference. This pin cannot be used to source current externally. Connect
VREF_1V2 to AGNDx via a 470 nF capacitor.
SWCLK
SWDIO
VREF_1V2
A11
IREF
AI
IDAC Reference Current. This pin generates the reference current for the IDACs
and is set by an external resistor, REXT. Connect REXT from IREF to AGND4.
J6
AIN0
AI
Analog Input 0.
J7
AIN1
AI
Analog Input 1.
J8
AIN2
AI
Analog Input 2.
K8
L8
L9
K9
J9
AIN3
AIN4
AIN5
AIN6
AI
AI
AI
AI
Analog Input 3.
Analog Input 4.
Analog Input 5. AIN5 can be the −ve input for the comparator.
Analog Input 6. AIN6 is also the +ve input for the comparator.
Analog Input 7.
AIN7
AI
L10
AIN8/P4.2
AI/I/O
Analog Input 8 (AIN8).
Digital I/O Port 4.2 (P4.2).
Analog Input 9 (AIN9).
Digital I/O Port 4.3 (P4.3).
Analog Input 10.
K10
J10
AIN9/P4.3
AIN10
AI/I/O
AI
Rev. C | Page 24 of 30
Data Sheet
ADuCM320
Pin
No.
Mnemonic
Type1
Description
J11
AIN11/BUF_VREF2V5
AI/AO
Analog Input 11 (AIN11).
Buffered 2.5 V Bias (BUF_VREF2V5). The maximum load = 1.2 mA. Connect
BUF_VREF2V5 to AGNDx via a 100 nF capacitor.
H10
G10
H9
AIN12/P4.4
AIN13/P4.5
AIN14/P4.6
AIN15/P4.7
VDAC0/P5.3
AI/I/O
AI/I/O
AI/I/O
AI/I/O
Analog Input 12 (AIN12).
Digital I/O Port 4.4 (P4.4).
Analog Input 13 (AIN13).
Digital I/O Port 4.5 (P4.5).
Analog Input 14 (AIN14).
Digital I/O Port 4.6 (P4.6).
Analog Input 15 (AIN15).
Digital I/O Port 4.7 (P4.7).
G9
L5
AO/I/O Voltage DAC0 Output (VDAC0).
Digital I/O Port 5.3 (P5.3).
K5
L4
VDAC1
VDAC2/P3.7/PLAO[29]
AO
Voltage DAC1 Output.
AO/I/O Voltage DAC2 Output (VDAC2).
Digital I/O Port 3.7 (P3.7).
Output of PLA Element 29 (PLAO[29]).
AO/I/O Voltage DAC3 Output (VDAC3).
Digital I/O Port 5.0 (P5.0).
K4
VDAC3/P5.0
J4
L3
K3
VDAC4
VDAC5
VDAC6/P5.1
AO
AO
Voltage DAC4 Output (VDAC4).
Voltage DAC5 Output (VDAC5).
AO/I/O Voltage DAC6 Output (VDAC6).
Digital I/O Port 5.1 (P5.1).
J3
VDAC7/P5.2
AO/I/O Voltage DAC7 Output (VDAC7).
Digital I/O Port 5.2 (P5.2).
A2
A3
B4
A10
A9
B8
A5
A4
B5
A7
A8
B7
B6
A6
A1
L2
IDAC0
AO
S
AI
AO
S
AI
AO
S
AI
AO
S
AI
IDAC0. 0 mA to 150 mA full-scale output.
Power for IDAC0.
Damping Capacitor 0. Connect damping capacitor from this pin to PVDD0.
IDAC1. 0 mA to 150 mA full-scale output.
Power for IDAC1.
Damping Capacitor 1. Connect damping capacitor from this pin to PVDD1.
IDAC2. 0 mA to 150 mA full-scale output.
Power for IDAC2.
Damping Capacitor 2. Connect damping capacitor from this pin to PVDD2.
IDA3C. 0 mA to 150 mA full-scale output.
Power for IDAC3.
PVDD0
CDAMP0
IDAC1
PVDD1
CDAMP1
IDAC2
PVDD2
CDAMP2
IDAC3
PVDD3
CDAMP3
PGND
Damping Capacitor 3. Connect damping capacitor from this pin to PVDD3.
Power Supply Ground for IDACs.
Power Supply Ground for IDACs.
S
S
PGND
IDAC_TST
DVDD_1V8
AI/AO
AO
Pin for IDAC Test Purposes. Leave IDAC_TST unconnected.
1.8 V Digital Supply. A 470 nF capacitor to DGND1 must be connected to this pin
to stabilize the internal 1.8 V regulator that supplies flash memory and the ARM
Cortex-M3 processor.
K2
DVDD_2V5
AO
2.5 V Digital Supply. A 470 nF capacitor to IOGND3 must be connected to this
pin to stabilize the internal 2.5 V regulator that supplies the analog digital
control.
F9
AVDD_REG0
AVDD_REG1
AO
AO
Analog Regulator 0 Supply. A 470 nF capacitor to AGND4 must be connected to
this pin to stabilize the internal 2.5 V regulator that supplies the ADC.
Analog Regulator 1 Supply. Output of 2.5 V on-chip LDO regulator. A 470 nF
capacitor to AGND4 must be connected to this pin. This regulator supplies the
IDACs.
F10
L1
D10
B1
DGND1
DGND2
IOVDD1
S
S
S
Digital Ground 1 for DVDD_1V8.
Digital Ground 2. Connect to DGND1.
3.3 V GPIO Supply.
Rev. C | Page 25 of 30
ADuCM320
Data Sheet
Pin
No.
D11
J1
C1
E11
K1
J5
K7
L7
H11
K6
Mnemonic
IOVDD2
IOVDD3
IOGND1
IOGND2
IOGND3
AGND1
AGND2
AGND3
AGND4
VDD1
Type1
Description
S
S
S
S
S
S
S
S
S
S
S
S
3.3 V GPIO Supply and Interdie Communications.
3.3 V GPIO Supply.
Ground for IOVDD1.
Ground for IOVDD2.
Ground for IOVDD3 and Interdie Communications.
Analog Ground for VDD1.
ESD Ground for Pad Ring.
Ground for AVDD3.
Ground for AVDD4, AVDD_REG0, and AVDD_REG1.
3.3 V Supply for Digital Die.
VDAC and IDAC Supply (3.3 V).
ADC Supply (3.3 V).
Decoupling Capacitor Connection for ADC Reference Buffer. Connect this pin to
AGND4.
L6
G11
L11
AVDD3
AVDD4
ADC_REFN
AO/A
K11
ADC_REFP
AO/A
Decoupling Capacitor Connection for ADC Reference Buffer. Connect this pin to
a 4.7 µF capacitor to the ADC_REFN pin. ADC_REFP can be overdriven by an
external reference.
H2
J2
XTALO
XTALI
O
I
Output from the Crystal Oscillator Inverter. When not using an external crystal,
leave XTALO unconnected.
Input to the Crystal Oscillator Inverter and Input to the Internal Clock Generator
Circuits. When not using an external crystal, connect XTALI to DGND.
1 AI is analog input, AO is analog output, I is digital input, O is digital output, S is supply.
Rev. C | Page 26 of 30
Data Sheet
ADuCM320
TYPICAL PERFORMANCE CHARACTERISTICS
0
–10
–20
–30
–40
–50
–60
–70
50000
IDAC0
IDAC1
IDAC2
IDAC3
DEVICE 1
DEVICE 2
DEVICE 3
DEVICE 4
DEVICE 5
45000
40000
35000
30000
25000
100
1k
10k
100k
–60
–40
–20
0
20
40
60
80
100
120
FREQUENCY (Hz)
TEMPERATURE (°C)
Figure 9. Typical Temperature Measurement vs. Internal Temperature
(VDD = 3.3 V, 50 kSPS)
Figure 12. Typical PVDD AC PSRR vs. Frequency
90
MAX PULL UP
MIN PULL UP
80
3.0
2.5
2.0
1.5
1.0
0.5
0
MIN PULLDOWN
MAX PULLDOWN
70
60
50
40
30
20
10
0
V
V
V
V
MAX
MIN
OH
OH
OL
OL
MIN
MAX
–10
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0
2
4
6
8
10
12
14
16
PIN VOLTAGE (V)
LOAD CURRENT (mA)
Figure 10. Typical Pull-Up/Pull-Down Pin Current vs. Pin Voltage
(VDD = 3.3 V, 25°C)
Figure 13. Typical Output Voltage vs. Load Current
350
IDAC 2
IDAC 3
3.60
IDAC 0
300
IDAC 1
250
200
150
100
50
AFTER 50ms DVDD MUST
STAY ABOVE 2.85V INCLUDING
NOISE EXCURSIONS
2.90
2.85
50ms min
DVDD MUST BE ABOVE 2.9V
FOR AT LEAST 50ms TO
COMPLETE POR
0
0
25
50
75
100
125
150
TIME (Not to Scale)
IDAC OUTPUT CURRENT (mA)
Figure 11. Typical IDAC Headroom vs. IDAC Output Current
Figure 14. VDD1 Power-On Requirements
Rev. C | Page 27 of 30
ADuCM320
Data Sheet
RECOMMENDED CIRCUIT AND COMPONENT VALUES
Figure 15 shows a typical connection diagram for the ADuCM320.
The IDAC output filters depend on a 10 nF capacitor being
placed between the CDAMPx and PVDDx.
Supplies and regulators must be adequately decoupled with
capacitors connected between the AVDDx, PVDDx, DVDD_x,
AVDD_REGx, IOVDDx, and VDD1 balls and their associated
GND balls (AGNDx, PGND, IOGNDx, and DGNDx). Table 11
indicates which ground balls are paired with which supply balls.
The ADC reference requires a 4.7 μF capacitor placed between
ADC_REFP and ADC_REFN and located as near as possible to
each ball. ADC_REFN must be connected directly to AGND4.
The ADuCM320 contains four internal regulators. These
regulators require external decoupling capacitors. The
DVDD_1V8 and DVDD_2V5 balls each require a 470 nF
capacitor to DGND1 and IOGND3, respectively. AVDD_REG0
and AVDD_REG1 each require a decoupling capacitor to
AGND4.
There are four digital supply balls, IOVDD1, IOVDD2, IOVDD3,
and VDD1. Decouple these balls with a 100 nF capacitor placed
as near as possible to each of the four balls and their associated
GND balls (IOGNDx and AGND1, respectively). In addition,
place a 10 μF capacitor conveniently near to these balls.
Similarly, the analog supply pins, AVDD3 and AVDD4, each
require a 100 nF capacitor placed as near as possible to each ball
and its associated AGNDx ball, and place a 10 μF capacitor
conveniently near to these balls.
To generate an accurate and low drift reference current, connect
the IREF ball to AGND4 via a low ppm 3.16 kΩ resistor.
Take care in the layout to ensure that currents flowing from the
ground end of each decoupling capacitor to its associated
ground ball share as little track as possible with other ground
currents on the printed circuit board.
The IDACs source their output currents from the PVDDx
supply balls. Each PVDDx supply ball must have a 100 nF
capacitor near to each ball and their associated GND balls
(PGND). In addition, place at least one 10 μF capacitor at the
source of the PVDDx supply.
Rev. C | Page 28 of 30
Data Sheet
ADuCM320
DVDD
VDD1
0.47µF 0.47µF
DGND
K2
L1
D10
J1
C1
E11
K1
B1
D11
K6
L2
VDD1
10kΩ
RESET
B2
RESET
12pF
12pF
J2
XTALI
H2
XTALO
VDD1
10kΩ
PVDD
A3
A9
PVDD0
PVDD1
P2.3/BM C3
ADuCM320
A4 PVDD2
A8 PVDD3
B4 CDAMP0
B8 CDAMP1
B5 CDAMP2
P1.0/SIN/ECLKIN/PLAI[4] B9
SWCLK
E9
10nF
10nF
10nF
B10
P1.1/SOUT
10nF
SWDIO E10
B7 CDAMP3
A6 PGND
B6 PGND
J5
L6
G11
F11
A11
K11 L11
F9
F10
K7
H11
L7
AVDD
0.47µF 3.16kΩ 4.7µF
0.47µF 0.47µF
RESET
GND
RESET
AGND
DGND
SWDIO
TX
SWCLK
RX
NC
VDD1
DVDD
1.6Ω
0.1µF
10µF
0.1µF
DGND DGND1
AVDD
AGND1
V
DVDD
10µF
ADP7102ARDZ3.3
IN
1.6Ω
VIN VOUT
SENSE0
0.1µF
10µF
10µF
0.1µF
0.1µF
10kΩ
EN
PG
GND
DGND
AGND AGND
PVDD
+2.5V
ADP1741ACPZ
VIN VOUT
EN
10µF
PGND
30kΩ
10kΩ
10µF
ADJ
EP
SS
GND
10µF
PGND
PGND
Figure 15. Recommended Circuit and Component Values
Rev. C | Page 29 of 30
ADuCM320
Data Sheet
PACKAGING AND ORDERING INFORMATION
OUTLINE DIMENSIONS
6.10
6.00 SQ
5.90
A1 BALL
CORNER
A1 BALL
CORNER
11 10
7 4 2 1
6
9 8 5 3
A
B
C
D
E
F
5.00 REF
SQ
G
H
J
0.50
BSC
K
L
BOTTOM VIEW
DETAIL A
0.50
TOP VIEW
REF
0.93
0.86
0.79
DETAIL A
1.200
1.083
1.000
0.223 NOM
0.173 MIN
0.35
0.30
0.25
COPLANARITY
0.08
SEATING
PLANE
BALL DIAMETER
COMPLIANT TO JEDEC STANDARDS MO-195-AC
WITH THE EXCEPTION TO BALL COUNT.
Figure 16. 96-Ball Chip Scale Package Ball Grid Array [CSP_BGA]
(BC-96-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range Package Description
−40°C to +105°C
Package Option Ordering Quantity
ADuCM320BBCZ
ADuCM320BBCZ-RL −40°C to +105°C
EV-ADuCM320QSPZ
96-Ball Chip Scale Package Ball Grid Array [CSP_BGA] BC-96-2
96-Ball Chip Scale Package Ball Grid Array [CSP_BGA] BC-96-2
Evaluation Board with QuickStart Development System
429
2,500
1
1 Z = RoHS Compliant Part.
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
©2014–2015 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D12272-0-10/15(C)
www.analog.com/ADuCM320
Rev. C | Page 30 of 30
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