ADUCM420BCBZ-RL7_技术文档

Precision Analog Microcontroller, 12-Bit Analog

Input/Output with MDIO Interface, Arm Cortex-M33

Data Sheet

ADuCM420

Package and temperature range

3.46 mm × 3.46 mm 64-ball WLCSP

Fully specified for −40°C to +105°C operation

Tools

Low cost quick start development system

Full third-party support

FEATURES

Analog input/output

Multichannel, 12-bit, 2 MSPS ADC

Up to 12 external channels

On-chip die temperature monitor

3 power monitor channels

Single-ended mode

0 V to VREF analog input range

Input buffers

12-bit voltage output DACs

8× 0 V to 2.5 V, 1 kΩ load

4× 0 V to 2.5 V, 2.5 kΩ load

APPLICATIONS

Optical networking 100 Gbps/200 Gbps/400 Gbps and

higher frequency modules

GENERAL DESCRIPTION

The ADuCM420 is a fully integrated, single package device that

On-chip low drift voltage reference, 1.25 V or 2.5 V

Buffered 1.25 V or 2.5 V output

4 voltage comparators

incorporates high performance analog peripherals together

with digital peripherals (controlled by a 160 MHz Arm®

Cortex™-M33 processor) and integrated flash for code and data.

Microcontroller

The analog-to-digital converter (ADC) on the ADuCM420

provides 12-bit, 2 MSPS data acquisition using up to 12 input

pins for single-ended mode. Additionally, the die temperature and

supply voltages can be measured.

32-bit Arm Cortex-M33 core, 32-bit RISC architecture, FPU

Serial wire port supports code download and debug

Clocking options

16 MHz on-chip oscillator

160 MHz PLL output with programmable divider

External clock source

Memory

2× 256 kB independent Flash/EE memories with ECC

10,000-cycle Flash/EE endurance

20-year Flash/EE retention

64 kB SRAM with ECC

Software triggered, in circuit reprogrammability via MDIO or I²C

On-chip peripherals

2× UART, 2× SPI, 3× I²C serial input/output

Multilevel voltage (3.3 V, 1.8 V, 1.2 V) GPIOs

MDIO slave up to 10 MHz

The ADC input voltage is 0 V to VREF. A sequencer is

provided that allows a user to select a set of ADC channels to be

measured in sequence without software involvement during the

sequence. The sequence can optionally repeat automatically at a

user-selectable rate.

Up to 12 channels of 12-bit digital-to-analog converters

(DACs) are provided with output buffers supported.

The ADuCM420 can be configured so that the digital and analog

outputs retain their output voltages through a watchdog or

software reset sequence. Therefore, a product can remain

functional even while the ADuCM420 is resetting itself.

5 general-purpose timers

Wake-up timer (WUTs)

Watchdog timers (WDTs)

32-element PLA

The ADuCM420 has a low power Arm Cortex-M33 processor

and a 32-bit reduced instruction set computer (RISC) machine

that offers up to 240 MIPS peak performance with a floating-

point unit (FPU). Also integrated on chip are 2× 256 kB

Flash/EE memories and 64 kB of static random access memory

(SRAM), both with with single-error correction (SEC) and

double error detection (DED) error checking and correction

(ECC). The flash comprises two separate 256 kB blocks

supporting execution from one flash block and simultaneous

writing and/or erasing of the other flash block.

16-bit PWM

All GPIOs support external interrupt, 5 can support wake-up

Power

Multiple supplies: 3.3 V for voltage DACs and ADCs, and

3.3 V, 1.8 V, or 1.2 V for digital inputs/outputs

Flexible operating modes for low power applications

Continued on Page 3

Rev. 0

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rights of third parties that may result from its use. Specifications subject to change without notice.

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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Technical Support

www.analog.com

ADuCM420

Data Sheet

TABLE OF CONTENTS

Features.............................................................................................. 1

Typical Performance Characteristics .......................................... 15

Pin Configuration and Function Descriptions .......................... 16

Theory of Operation ...................................................................... 21

Applications Information ............................................................. 22

Power Supplies ........................................................................... 22

Power-Up Requirements .......................................................... 22

Recommended Circuit and Component Values ................... 23

Outline Dimensions....................................................................... 25

Ordering Guide .......................................................................... 25

Applications ...................................................................................... 1

General Description......................................................................... 1

Revision History ............................................................................... 2

Functional Block Diagram .............................................................. 4

Specifications .................................................................................... 5

Timing Specifications .................................................................. 9

Absolute Maximum Ratings ......................................................... 14

Thermal Resistance.................................................................... 14

Electrostatic Discharge (ESD) Ratings.................................... 14

ESD Caution................................................................................ 14

REVISION HISTORY

1/2021—Revision 0: Initial Version

Rev. 0| Page 2 of 25

Data Sheet

ADuCM420

The ADuCM420 operates from an on-chip oscillator and has a

phase-locked loop (PLL) of 160 MHz. This clock can optionally

be divided down to reduce current consumption. Additional

low power modes can be set via the ADuCM420 software.

The GPIO pins (Px.x) power up in high impedance input

mode. In output mode, the software chooses between open-

drain mode and push/pull mode. The pull-up and pull-down

resistors can be disabled and enabled in the software. The GPIO

pins can be configured with different voltage levels according to

the IOVDDx pin, such as 3.3 V, 1.8 V, and 1.2 V. In GPIO

output mode, the inputs can remain enabled to monitor the

GPIO pins. The GPIO pins can also be programmed to handle

digital or analog peripheral signals, in which case, the pin

characteristics are matched to the specific requirement.

The device includes a management data input/output (MDIO)

interface capable of operating up to 10 MHz. User programming

is eased by incorporating physical address (PHYADR) and device

address (DEVADD) hardware comparators. The nonerasable

kernel code combined with flags in user flash allow user code to

reliably switch between the two hardware independent flash

blocks.

A large support ecosystem is available for the Arm Cortex-M33

processor to ease product development of the ADuCM420.

Access is via the Arm serial wire debug port. On-chip factory

firmware supports in-circuit serial download via MDIO or I²C.

These features are incorporated into a low cost quick start

development system supporting this precision analog

microcontroller

The ADuCM420 integrates a range of on-chip peripherals that

can be configured under software control, as required in the

application. These peripherals include 2× universal asynchronous

receiver transmitter (UART), 3× I²C, and 2× serial peripheral

interface (SPI) serial input/output communication controllers,

general-purpose inputs/outputs (GPIOs), a 32-element

programmable logic array (PLA), five general-purpose timers, a

wake-up timer (WUT), and a system watchdog timer (WDT).

A 16-bit pulse-width modulation (PWM) with eight output

channels is also provided.

Note that throughout this data sheet, multifunction pins, such

as AIN4/VDAC0, are referred to either by the entire pin name

or by a single function of the pin, for example, AIN4, when

only that function is relevant.

.

Rev. 0| Page 3 of 25

ADuCM420

Data Sheet

FUNCTIONAL BLOCK DIAGRAM

1

VDAC0

VDAC1

VDAC10 VDAC11

AIN0

AIN1

AIN2

AIN3

ADuCM420

1

AIN4

AIN7

AIN8/COM0P

COMP

GP TIMER

WATCHDOG

TIMER

AIN9/COM0N

2

12-BIT

SAR ADC

AT 2MSPS

GPIO

PLA

GPIOs

VDAC8

WAKE-UP TIMER

BUF

PLAOx

PLAIx

AIN8

2 × 256kB FLASH/EE

WITH ECC

AIN10/COM1P

COMP

64kB SRAM

WITH ECC

VDAC9

4

MDIO

SPI

CACHE

AIN14

CONTROLLER

5

SPIs

AVDD/2

IOVDD/2

AGND

DMA

AIN12/COM2P

COMP

SDAx,

SCLx

AIN13/COM2N

16MHz

OSC

32kHz

6

7

WIC

NVIC

2

PLL

ALP

I C

OSC

POR

0.9V

TEMPERATURE

SENSOR

VDAC10

Arm Cortex-M33

WITH DSP

UP TO 160MHz

HP

REF

SOUTx,

SINx

UART

PWM

8

9

REF

1

COMP

AIN14/COM3P

BUF

2.5V

ALDO

DLP

VDAC11

10

11

12

SERIAL WIRE DEBUG

REF

DLDO

1

BUF0_VREF

AVDD_REG

DVDD_REG

SERIAL WIRE

3

EMULATION

1

THIS IS A PARTIAL FUNCTION OF A MULTIFUNCTION PIN. FOR EXAMPLE, VDAC0 AND AIN4 ARE SEPARATE FUNCTIONS

ON THE SAME PIN, AIN4/VDAC0.

2

GPIOs REFER TO Px.x.

3

4

SERIAL WIRE EMULATION REFERS TO SWDIO, SWCLK, AND SWO.

MDIO REFERS TO PRTADDRx, MDIO, AND MCK.

SPIs REFER TO SCLKx, CSx, MOSIx, SRDYx, AND MISOx.

NVIC IS NESTED VECTORED INTERRUPT CONTROLLER.

WAKE-UP INTERRUPT CONTROLLER.

5

6

7

8

HP REF IS HIGH POWER REFERENCE.

9

ALP REF IS ANALOG LOW POWER REFERENCE.

ALDO IS ANALOG LOW DROPOUT REGULATOR.

10

11

DLP REF IS DIGITAL LOW POWER REFERENCE.

DLDO IS DIGITAL LOW DROPOUT REGULATOR.

12

Figure 1.

Rev. 0| Page 4 of 25

Data Sheet

ADuCM420

SPECIFICATIONS

AVDD = IOVDD0 = 2.85 V to 3.6 V, IOVDD1 = 1.2 V or 1.8 V, DVDD = 1.8 V to 3.6 V, VREF = 2.5 V for the internal reference, the

core frequency (f_CORE) = 160 MHz, and T_A= −40°C to +105°C, unless otherwise noted. HCLK is the high speed system clock.

Table 1.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

ADC CHANNEL SPECIFICATIONS

ADC Power-Up Time

Single-ended mode only

5

μs

Data Rate (f_ADC

Resolution

Integral Nonlinearity

Differential Nonlinearity

DC Code Distribution¹

)

2

MSPS

Bits

LSB

12

2.5 V internal reference

1

0.ꢀ

2

0.ꢁ

Minimum and maximum range from mean

ADC codes for 1000 samples

2

LSB

ꢂV

ADC input 1.25 V, single ended; f_ADC= 1 MSPS

ENDPOINT ERRORS

Offset Error

−ꢁ20

400

+720

External channels

Offset Error Drift

Offset Error Drift Matching

4

1

ꢂV/°C

Matching compared to AIN0; for voltage

input channels

Full-Scale Error

Gain Error Drift

Gain Error Drift Matching

−1500

500

5

0.5

+1000

ꢂV

ppm/°C

External channels

Matching compared to AIN0; for voltage

input channels

DYNAMIC PERFORMANCE

Signal-to-Noise Ratio (SNR)

Input frequency (f_IN) = 500 Hz sine wave,

sampling frequency (f_SAMPLE) = 1 MSPS internally

Includes distortion and noise components;

voltage input

73

dB

Total Harmonic Distortion (THD)

Peak Harmonic or Spurious Noise

Channel to Channel Crosstalk

ANALOG INPUT

−85

−82

−ꢁꢀ

dB

Measured on adjacent channels

Input Voltage Ranges

Single-Ended Mode

0

2.5

V

Leakage Current

Input Current

5

50

230

30

nA

pF

Input voltage to AINx = 0.15 V to 2.5 V

At 100 kHz sample rate from 0.15 V to 2.5 V

2 MSPS ADC sample rate

420

Input Capacitance

During ADC acquisition

ON-CHIP VOLTAGE REFERENCE

4.7 μF decoupling capacitor between

ADCREFP and ADCREFN

Output Voltage

2.5

V

Accuracy

Reference Temperature Coefficient

5

30

20

mV

ppm/°C

T_A= 25°C

T_A= −40°C to +25°C range

T_A= 25°C to 105°C range

10

Power Supply Rejection Ratio (PSRR)

DC

AC

70

ꢀ0

dB

AVDD change effects, 2.85 V to 3.ꢀ V

Tested with AVDD noise of 1 kHz, 10 kHz,

100 kHz, and 1 MHz

Output Impedance

2

Ω

Do not use as external reference source;

T_A= 25°C

EXTERNAL REFERENCE INPUT

Input Voltage Range

Input Impedance

2.5

5

V

kΩ

Only supports 2.5 V external reference input

Do not use as external reference source

Rev. 0| Page 5 of 25

ADuCM420

Data Sheet

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

BUFFERED VREF OUTPUT (BUF0_VREF)

Output Voltage

1 μF capacitor required on output

1.25 or

2.5

V

Accuracy

Reference Temperature Coefficient

ꢀ

30

20

mV

T_A= 25°C, load capacitance (C_L) = 4 mA

T_A= −40°C to +25°C range

T_A= 25°C to 105°C range

10

2.5

ppm/°C

mV/mA

Ω

mA

dB

Load Regulation

Output Impedance

Load Current

PSRR

4

70

VOLTAGE DAC (VDAC) CHANNEL

SPECIFICATIONS

VDAC Channel 0 to Channel 7: buffer on,

load resistance (R_L) = 1 kΩ, C_L= 100 pF,

DACCONx, Bit ꢁ = 0 (normal drive, unless

otherwise stated); VDAC Channel 8 to

Channel 11: buffer on, R_L= 2.5 kΩ, C_L= 100 pF

DC Accuracy

Resolution

12

−2

−0.ꢁ

−13.5

−15

Bits

LSB

mV

Relative Accuracy²

Differential Nonlinearity¹

Calculated Offset Error

Actual Offset Error

1.5

0.5

5

+2

+3

+0.ꢁ

+15.5

+15

Guaranteed monotonic

2.5 V internal reference

Measured at Code 0

VDAC Channel 0 to Channel 7: DACCONx,

Bit ꢁ = 1; R_L= 250 Ω; C_L= 100 pF

Gain Error

−0.7

0.2

+0.5

% of FS³

VDAC Channel 0 to Channel 7: DACCONx,

Bit ꢁ = 1; R_L= 250 Ω; C_L= 100 pF

Offset Error Drift

Gain Error Drift

Short-Circuit Current

10

15

32

μV/°C

ppm/°C

mA

VDAC Channel 0 to Channel 7

VDAC Channel 8 to Channel 11

15

mA

VDAC OUTPUTS

Output Range¹

0

2.5

V

VDAC Channel 0 to Channel 7

VDAC Channel 8 to Channel 11

Lower of 2.5

or AVDD − 0.7

Output Impedance

1

Ω

VDAC AC CHARACTERISTICS

Slew Rate

Voltage Output Settling Time

Digital to Analog Glitch Energy

2.5

10

20

V/ꢂs

ꢂs

nV-sec

1 LSB change at major carry (where

maximum number of bits simultaneously

changes in the DACDATx register)

COMPARATOR INPUT

Offset Voltage

15

mV

The offset voltage is dependent on the

comparator being enabled with its input

pins connected to external biasing circuits; if

the comparator is left powered down or if

the inputs to the comparator are left

floating, over time the offset error may

increase

Bias Current

−30

740

+3

10

50

+43

ꢁ40

nA

Noninverting (positive) input

Inverting (negative) input, hysteresis disabled

Inverting (negative) input, hysteresis = 10 mV

Inverting (negative) input, hysteresis = 210 mV

840

Rev. 0| Page ꢀ of 25

Data Sheet

ADuCM420

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

Voltage Range

0.5

AVDD − 1.2

V

Negative input range (reference node of the

comparator)

AGND

0

AVDD

2.0

V

Positive input range to comparator

Differential input range; positive input −

negative input voltage

Capacitance

Hysteresis

Hysteresis Voltage Accuracy

7

50

10

pF

mV

% of target

hysteresis

10

210

35

1ꢀ configurable options⁴

10 mV to 35 mV settings

5

15

% of target

hysteresis

ꢂs

50 mV to 210 mV settings

Response Time

POWER-ON RESET (POR)

POR Trip Level (DVDD)

Refers to voltage at DVDD pin

Power-on level (see Figure 17)

Power-down level (brownout)

1.ꢀ

1.ꢀ2

1.77

1.7

V

ms

1.ꢀꢀ

32

Timeout from POR

FLASH MEMORY

Endurance

10,000

10

20

Cycles

Years

MHz

%

Data Retention

Junction temperature (T_J) = 125°C

T_J= 85°C

INTERNAL HIGH POWER OSCILLATOR

Accuracy

1ꢀ

3

TEMPERATURE SENSOR

Voltage Output at 25°C

Voltage Temperature Coefficient

Accuracy with No Calibration

INTERNAL LOW POWER OSCILLATOR

Accuracy

Indicates die temperature

0.13ꢀ25

0.45ꢀ8

2

32

7

V

mV/°C

°C

−3

+4.4

+10

kHz

%

−10

3.3 V GPIO

Logic Inputs

IOVDD0 = 3.3 V

IOVDD0 × 0.3

Input Low Voltage (V_INL

)

0.ꢁꢁ

V

Input High Voltage (V_INH

)

2

V

Pull-Up Current

Pull-Down Current

Internal Pull-Up or Pull-Down

Disabled

120

115

−32

1ꢀ0

1ꢀ3

+1

210

+ꢀ5

ꢂA

nA

Input voltage (V_IN) = 0 V

V_IN= 3.3 V

Logic Outputs

Output High Voltage (V_OH)

Output Low Voltage (V_OL)

2.4

V

Source current (I_SOURCE) = 12 mA

0.4

10

Sink current (I_SINK) = 12 mA for SCL0 and

SDA0 (I²C0); and for SCL2 and SDA2 (I²C2),

I

_SINK= 20 mA

Input Capacitor

Short-Circuit Current

1.8 V GPIO

pF

mA

13

IOVDD1 = 1.8 V

Logic Inputs

V_INL

0.54

V

V_INH

1.2ꢀ

150

170

V

Pull-Up Current

Pull-Down Current

Internal Pull-Up or Pull-Down

Disabled

1ꢁ4

217

+25

240

270

+2000

ꢂA

nA

V_IN= 0 V

V_IN= 1.8 V

IOVDD1 power source

−520

Rev. 0| Page 7 of 25

ADuCM420

Data Sheet

Parameter

Logic Outputs

V_OH

Min

Typ

Max

Unit

Test Conditions/Comments

1.4

V

pF

mA

I_SOURCE= 12 mA

I_SINK= 12 mA

V_OL

0.3ꢀ

10

Input Capacitor

Short-Circuit Current

1.2 V GPIO

Logic Inputs

V_INL

17

IOVDD1 = 1.2 V

0.3ꢀ

V

V_INH

0.84

55

V

Pull-Up Current

Pull-Down Current

Internal Pull-Up or Pull-Down

Disabled

7ꢀ

82

+20

100

110

+1510

ꢂA

nA

V_IN= 0 V

V_IN= 1.2 V

IOVDD1 power source

−450

Logic Outputs

V_OH

V_OL

1.0

V

pF

mA

I_SOURCE= ꢀ mA

I_SINK= ꢀ mA

0.18

10

Input Capacitor

Short-Circuit Current

MDIO

7

Logic Inputs

V_INL

V_INH

Logic Output

V_OH

0.3ꢀ

V

0.84

1.0

V

I_SOURCE= 4 mA

I_SINK= 4 mA

V_OL

0.2

10

V

pF

mA

Input Capacitor

Short-Circuit Current

7

MICROCONTROLLER UNIT (MCU)

CLOCK RATE

Using PLL Output

1ꢀ0

1ꢀ3

MHz

ꢂs

EXTERNAL RESET

Minimum Pulse Duration

PROCESSOR START-UP TIME

At Power-On

10

Pin voltage must stay low for this period

32

1

ms

Includes kernel execution time

After Reset Event

After Processor Power-Down

Core Sleep Mode (Mode 1)

System Sleep Mode (Mode 2)

Hibernate Mode (Mode 3)

POWER REQUIREMENTS

Power Supply Voltage Range

AVDD to AGND

30

85

3

HCLK cycles Fixed number of HCLK periods

ꢂs

HCLK = 1ꢀ0 MHz from PLL

HCLK = 1ꢀ MHz from internal oscillator

2.85

1.7

3.3

1.8 or

3.3

3.ꢀ

V

DVDD to DGND

IOVDD0 to IOGND

IOVDD1 to IOGND

2.85

1.08

3.3

1.2 or

1.8

3.ꢀ

1.ꢁ8

V

If unused, can be tied to DVDD_REG or to

DGND

Analog Power Supply Currents

AVDD Current

ꢁ00

1050

ꢂA

Analog peripherals in idle mode

Digital Power Supply Current

Current in Normal Mode

IOVDD0

175

20

200

ꢀ0

ꢂA

IOVDD1

Rev. 0| Page 8 of 25

Data Sheet

ADuCM420

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

DVDD Current

Active Mode

Executing typical code

1ꢀ

4.8

11

4.3

2.4ꢀ

2.44

mA

HCLK = 1ꢀ0 MHz clock

HCLK = 1ꢀ MHz from internal oscillator

HCLK = 1ꢀ0 MHz clock

Core Sleep Mode (Mode 1)

HCLK = 1ꢀ MHz from internal oscillator

System Sleep Mode (Mode 2)

Hibernate Mode (Mode 1)

Additional Power Supply Currents

ADC

1ꢁ

20

HCLK = 1ꢀ0 MHz clock

2.8

330

18.8

3.4

350

mA

ꢂA

mA

Continuously converting at 2 MSPS

Per powered up DAC, excluding load current

Active mode with PLL clock of 1ꢀ0 MHz and

ADC enabled

DAC

Total Supply Current

¹These numbers are not production tested but are guaranteed by design and/or characterization data at production release.

²VDAC linearity specifications generated using reduced DAC code range of 82 to 40ꢁ5. For VDAC Channel 8 to Channel 11, end code of 40ꢁ5 only used when AVDD −

0.7 V > 2.5 V.

³FS is full scale.

⁴These options include 10 mV, 25 mV, 35 mV, 50 mV, ꢀ0 mV, 75 mV, 100 mV, 110 mV, 125 mV, 135 mV, 150 mV, 1ꢀ0 mV, 175 mV, 185 mV, 200 mV, and 210 mV.

TIMING SPECIFICATIONS

I²C Timing

Table 2. I²C Timing in Standard Mode (100 kHz)—Slave/Master

Parameter

Description

Min

4.7

4.0

250

0

Typ

Max

Unit

ꢂs

ns

t_L

t_H

t_SHD

t_DSU

t_DHD

SCLx low pulse width

SCLx high pulse width

Start condition hold time

Data setup time

Data hold time (SDAx held internally after falling edge of SCLx, duration set via

TCTL register, THDATIN bits)

3.45

ꢂs

t_RSU

t_PSU

t_BUF

t_R

Setup time for repeated start

Stop condition setup time

Bus free time between a stop condition and a start condition

Rise time for both SCLx and SDAx

Fall time for both SCLx and SDAx

Data valid time

4.7

4.0

4.7

ꢂs

ns

ꢂs

pF

1

t_F

15

300

3.45

400

t_{VD; DAT}

t_VD;ACK

C_B

Data valid acknowledge time

Capacitive load for each bus line (not shown in Figure 2)

Table 3. I²C Timing in Fast Mode (400 kHz)—Slave/Master

Parameter Description

Min Typ Max Unit

t_L

t_H

t_SHD

t_DSU

t_DHD

SCLx low pulse width

SCLx high pulse width

Start condition hold time

Data setup time

Data hold time (SDAx held internally after falling edge of SCLx, duration set via TCTL register,

THDATIN bits)

1.3

0.ꢀ

100

0

ꢂs

ns

ꢂs

t_RSU

t_PSU

t_BUF

t_R

Setup time for repeated start

Stop condition setup time

Bus free time between a stop condition and a start condition

Rise time for both SCLx and SDAx

Fall time for both SCLx and SDAx

Data valid time

Data valid acknowledge time

Capacitive load for each bus line (not shown in Figure 2)

Rev. 0| Page ꢁ of 25

0.ꢀ

1.3

20

ꢂs

ns

ꢂs

pF

300

0.ꢁ

400

t_F

15

t_{VD; DAT}

t_{VD; ACK}

C_B

ADuCM420

Data Sheet

I²C GPIOs (P0.7 to P0.4 and P1.3 to P1.2) drive strength set to 20 mA.

Table 4. I²C Timing in Fast Mode Plus (1 MHz)—Slave/Master

Parameter Description

Min Typ Max Unit

t_L

t_H

t_SHD

t_DSU

t_DHD

SCLx low pulse width

SCLx high pulse width

Start condition hold time

Data setup time

Data hold time (SDAx held internally after falling edge of SCLx, duration set via TCTL register,

THDATIN bits)

0.5

0.2ꢀ

50

ꢂs

ns

ꢂs

0

t_RSU

t_PSU

t_BUF

t_R

Setup time for repeated start

Stop condition setup time

Bus free time between a stop condition and a start condition

Rise time for both SCLx and SDAx

Fall time for both SCLx and SDAx

Data valid time

0.2ꢀ

0.5

ꢂs

ns

120

t_F

t_{VD; DAT}

t_{VD; ACK}

C_B

0.45 ꢂs

Data valid acknowledge time

Capacitive load for each bus line (not shown in Figure 2)

550

pF

I²C GPIOs (P0.7 to P0.4 and P1.3 to P1.2) drive strength set to 20 mA.

Table 5. I²C Timing in High Speed Mode (3.4 MHz)—Slave Only

Parameter

Description

Min

1ꢀ0

ꢀ0

1ꢀ0

10

Typ

Max

Unit

ns

t_L

t_H

t_SHD

t_DSU

t_DHD

SCLx low pulse width

SCLx high pulse width

Start condition hold time

Data setup time

Data hold time (SDAx held internally after falling edge of SCLx, duration set via

TCTL register, THDATIN bits)

0

ns

t_RSU

t_PSU

t_BUF

t_R

Setup time for repeated start

Stop condition setup time

Bus free time between a stop condition and a start condition

Rise time for both SCLx and SDAx

Up to C_B= 100 pF

1ꢀ0

200

10

ns

40

Up to C_B= 400 pF

Fall time for both SCLx and SDAx

Up to C_B= 400 pF

80

40

80

400

ns

pF

t_F

10

C_B

Capacitive load for each bus line (not shown in Figure 2)

t_BUF

t_R

SDAx (I/O)

MSB

LSB

ACK

MSB

t_DSU

t_DHD

t_RSU

t_F

t_DHD

t_PSU

t_{VD; DAT}

t_R

t_H

t_SHD

t_{VD; ACK}

1

2–7

8

9

1

SCLx (I)

t_L

P

S

S(R)

t_F

STOP

START

REPEATED

START

CONDITION CONDITION

Figure 2. I²C-Compatible Interface Timing

Rev. 0| Page 10 of 25

Data Sheet

ADuCM420

SPI Timing Specifications: Slave Mode

SPI GPIOs (P0.3 to P0.0, P1.7 to P1.4) drive strength set to 12 mA, IOVDD1 ≥ 1.2 V, and 40 MHz SPI clock. See Figure 3 and Figure 4.

Table 6. SPI Slave Mode Timing

Parameter

Symbol

Min

Typ

Max

Unit

TIMING REQUIREMENTS

CSx

t_CS

25

ns

to SCLKx Edge

CSx

t_CS

Minimum Valid

Inactive Period

M

SCLKx Low Pulse Width

SCLKx High Pulse Width

Data Input Setup Time Before SCLKx Edge

Data Input Hold Time After SCLKx Edge

SCLKx Rise Time

t_SL

t_SH

t_DSU

t_DHD

t_SR

10

ns

5

SCLKx Fall Time

t_SF

SWITCHING CHARACTERISTICS

Data Output Valid After SCLKx Edge

t_DAV

t_DOCS

t_SFS

10

15

ns

CSx

Data Output Valid After

Edge

CSx

8.75

High After SCLKx Edge

t_CSM

CSx

t_CS

t_SFS

SCLKx

(POLARITY = 0)

t_SH

t_SL

t_SR

t_SF

SCLKx

(POLARITY = 1)

t_DAV

t_DOCS

t_DF

t_DR

MSB

MISOx

MOSIx

Figure 3. SPI Slave Mode Timing (Serial Clock Phase Mode, CTL Register, Bit 2, CPHA = 0)

t_CSM

CSx

t_CS

t_SFS

SCLKx

(POLARITY = 0)

t_SH

t_SL

SCLKx

(POLARITY = 1)

t_DAV

t_DOCS

t_DF

t_DR

BIT 6 TO BIT 1

MISOx

MSB

LSB

MOSIx

MSB IN

t_DSU

BIT 6 TO BIT 1

LSB IN

t_DHD

Figure 4. SPI Slave Mode Timing (CPHA = 1)

Rev. 0| Page 11 of 25

ADuCM420

Data Sheet

SPI Timing Specifications: Master Mode

SCLKx = 40 MHz, SPI SPI GPIOs (P0.3 to P0.0, P1.7 to P1.4) pin drive strength set to 12 mA. IOVDD1 ≥ 1.2 V. DIV is the SPI clock

divider, in the SPI baud rate selection register (see the ADuCM420 hardware reference manual for more information). t_HCLKis the time

period of HCLK set up by the user.

Table 7. SPI Master Mode Timing (CPHA = 0 and 1)

Parameter

Description

Min

Typ

Max

Unit

ns

t_SL

t_SH

SCLKx low pulse width

SCLKx high pulse width

Data output valid after SCLKx edge

Data input setup time before SCLKx edge

Data input hold time after SCLKx edge

Data output fall time

Data output rise time

SCLKx rise time

SCLKx fall time

(DIV + 1) × t_HCLK/2

t_DAV

t_DSU

t_DHD

t_DF

t_DR

t_SR

0

5

t_SF

ns

SCLKx

(POLARITY = 0)

t_SH

t_SL

t_SR

t_SF

SCLKx

(POLARITY = 1)

t_DAV

t_DF

t_DR

MOSIx

MISOx

MSB

BIT 6 TO BIT 1

LSB

MSB IN

BIT 6 TO BIT 1

LSB IN

t_DSU

t_DHD

Figure 5. SPI Master Mode Timing (CPHA = 1)

SCLKx

(POLARITY = 0)

t_SH

t_SL

t_SR

t_SF

SCLKx

(POLARITY = 1)

t_DAV

t_DF

t_DR

MOSIx

MISOx

MSB

BIT 6 TO BIT 1

LSB

MSB IN

BIT 6 TO BIT 1

LSB IN

t_DSU

t_DHD

Figure 6. SPI Master Mode Timing (CPHA = 0)

Rev. 0| Page 12 of 25

Data Sheet

ADuCM420

Table 8. MDIO vs. Management Data Clock (MDC) Timing

Parameter¹

Description

Min

Typ

Max

10

4

Unit

MHz

ns

Maximum MCK Clock Speed

Push/pull mode

Open-drain mode, pull-up resistance (R_PULLUP) = 312 Ω

MDIO setup before MCK edge (push/pull mode)

Open-drain mode, R_PULLUP= 312 Ω

MDIO valid after MCK edge (push/pull mode)

Open-drain mode, R_PULLUP= 312 Ω

Data output after MCK edge (push/pull mode)

Open-drain mode, R_PULLUP= 312 Ω

t_SETUP

t_HOLD

t_DELAY

5

10

7

10

ns

2ꢀ

100

¹In Figure 7, CFP is C formfactor pluggable. V_IHis the voltage input high level, and V_ILis voltage input low level.

MCK

V

IH

IL

CFP

INPUT

MDIO

V

IH

IL

CFP

INPUT

MDIO

V

OH

OL

CFP

OUTPUT

t_SETUPt_HOLD

t_DELAY

Figure 7. MDIO Timing

Rev. 0| Page 13 of 25

ADuCM420

Data Sheet

ABSOLUTE MAXIMUM RATINGS

THERMAL RESISTANCE

Table 9.

Thermal performance is directly linked to printed circuit board

(PCB) design and operating environment. Careful attention to

PCB thermal design is required.

Parameter

Rating

AVDD to AGND

IOVDD0 to IOGND

IOVDD1 to IOGND

DVDD to DGND

AVDD to IOVDD0

Analog Input Voltage to AGND

(AVDD Range = 2.85 V to 3.ꢀ V)

Digital Input Voltage to IOGND

−0.3 V to +3.ꢀ3 V

−0.3 V to +1.ꢁ8 V

−0.3 V to +3.ꢀ3 V

IOVDD0 0.3 V

−0.3 V to AVDD + 0.3 V,

must be ≤3.ꢀ3 V

−0.3 V to IOVDD0 + 0.3 V,

must be ≤3.ꢀ3 V

θ_JAis the natural convection junction to ambient thermal

resistance measured in a one cubic foot sealed enclosure. θ_JCis

the junction to case thermal resistance.

Table 10. Thermal Resistance

Package Type

1

θ_JA

θ_JC

Unit

CB-ꢀ4-2

34

0.1ꢀ

°C/W

Digital Input Voltage to IOGND (P1.0 −0.3 V to IOVDD1 + 0.3 V,

to P1.7 and P0.0 to P0.3 Only)¹

AGND to DGND

must be ≤1.ꢁ8 V

−0.3 V to +0.3 V

0 mA to 40 mA

−40 mA to 0 mA

¹JEDEC 2S2P.

ELECTROSTATIC DISCHARGE (ESD) RATINGS

IOGND to DGND

Total Positive GPIO Pins Current

Total Negative GPIO Pins Current

Temperature Ranges

Storage

Operating

Reflow Profiles

The following ESD information is provided for handling of

ESD sensitive devices in an ESD protected area only.

Human body model (HBM) per ANSI/ESDA/JEDEC JS-001.

Field induced charged device model (FICDM) per

ANSI/ESDA/JEDEC JS-002.

−ꢀ5°C to +150°C

−40°C to +105°C

ESD Ratings for ADuCM420

SnPb Assemblies (10 sec to 30 sec) 240°C

Pb-Free Assemblies (20 sec to

40 sec)

Junction Temperature

2ꢀ0°C

Table 11. ADuCM420, 64-Ball WLCSP

ESD Model

Withstand Threshold (kV)

Class

2

C2A

150°C

HBM

3

¹When IOVDD1 is the selected power rail.

FICDM

0.5

Stresses at or above those listed under Absolute Maximum

Ratings may cause permanent damage to the product. This is a

stress rating only; functional operation of the product at these

or any other conditions above those indicated in the

operational section of this specification is not implied.

Operation beyond the maximum operating conditions for

extended periods may affect product reliability.

ESD CAUTION

Rev. 0| Page 14 of 25

Data Sheet

ADuCM420

TYPICAL PERFORMANCE CHARACTERISTICS

2.510

16

14

12

10

8

DEVICE 1

DEVICE 2

DEVICE 3

2.508

2.506

2.504

2.502

2.500

2.498

2.496

2.494

2.492

2.490

6

4

DEVICE 5, AIN0

DEVICE 5, AIN1

DEVICE 5, AIN2

DEVICE 5, AIN3

DEVICE 5, AIN4

DEVICE 5, AIN7

DEVICE 5, AIN8

DEVICE 5, AIN9

DEVICE 5, AIN10

DEVICE 5, AIN12

DEVICE 5, AIN13

DEVICE 5, AIN14

2

DEVICE 6, AIN0

DEVICE 6, AIN1

DEVICE 6, AIN2

DEVICE 6, AIN3

DEVICE 6, AIN4

0

DEVICE 6, AIN7

DEVICE 6, AIN8

–2

0.1

0.5

0.9

1.3

1.7

2.1

2.5

2.9

3.3

3.7

4.0

0.30

0.60

0.90

1.20

1.35

1.65

1.95

2.25

2.50

VOLTAGE ON AINx (V)

LOAD CURRENT (mA)

Figure 11. Input Current vs. Voltage on AINx, f_SAMPLE= 100 kSPS

Figure 8. BUF0_VREF Load Regulation, 2.5 V Output Setting

3

1.258

DEVICE 1

DEVICE 2

DEVICE 3

1.256

1.254

1.252

1.250

1.248

1.246

1.244

1.242

1.240

2

1

0

–1

–2

–40 –30 –20 –10

0

10 20 30 40 50 60 70 80 90 100

TEMPERATURE (°C)

0.1

0.5

0.9

1.3

1.7

2.1

2.5

2.9

3.3

3.7

4.0

LOAD CURRENT (mA)

Figure 12. Temperature Sensor Accuracy, No Calibration, 240 Devices

Figure 9. BUF0_VREF Load Regulation, 1.25 V Output Setting

2.504

2.503

2.502

2.501

2.500

2.499

2.498

2.497

2.496

2.495

2.494

350

300

250

200

150

100

50

DEVICE 5, AIN8

DEVICE 5, AIN9

DEVICE 5, AIN10

DEVICE 5, AIN12

DEVICE 5, AIN13

DEVICE 5, AIN14

DEVICE 5, AIN0

DEVICE 5, AIN1

DEVICE 5, AIN2

DEVICE 5, AIN3

DEVICE 5, AIN4

DEVICE 5, AIN7

DEVICE 6, AIN0

DEVICE 6, AIN1

DEVICE 6, AIN2

DEVICE 6, AIN3

DEVICE 6, AIN4

DEVICE 6, AIN7

DEVICE 6, AIN8

0

–40 –30 –20 –10

0

10 20 30 40 50 60 70 80 90 100

TEMPERATURE (°C)

0.30

0.60

0.90

1.20

1.35

1.65

1.95

2.25

2.50

VOLTAGE ON AINx (V)

Figure 10. Input Current vs. Voltage on AINx, f_SAMPLE= 2 MSPS

Figure 13. Reference Voltage Drift vs. Temperature, 250 Devices

Rev. 0| Page 15 of 25

ADuCM420

Data Sheet

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

2

3

4

5

6

7

8

P2.1/DM/

IRQ2/

ECLKIN/

COMPDIN3/

PLAI9

P2.0/

ADCCONV/

COMPDIN2/

PLAI8

IOGND

SWDIO

VDAC7

VDAC6

VDAC5

VDAC3

A

B

C

D

E

F

P0.3/IRQ0/

P0.2/MOSI0/

PLACLK1/

PLAI2

P2.3/

BM

PLAI10

CS0/

PLACLK0/

PLAI3

SWCLK

RESET

VDAC1

VREF

AIN2

AVDD

P2.2/

POR/

CLKOUT/

SWO

P0.0/SCLK0/

COMOUT0/

PLAI0

P1.0/SIN1/

COMOUT2/

PLAI4

P0.1/MISO0/

COMOUT1/

PLAI1

AIN14/

COM3P/

BUF0_VREF

AIN4/

VDAC0

IOVDD1

DVDD_REG

IOVDD0

P1.2/

SCL1/

PWM0/

PLAI6

P1.3/

SDA1/

PWM1/

PLAI7

P1.1/

SOUT1/

COMOUT3/

PLAI5

AIN10/

COM1P

AIN0

DGND

AIN3

P1.4/

P1.7/

SCLK1/

PWM2/

PLAO10

AIN12/

COM2P

VDAC8/

P5.0

IRQ1/CS1/

PWM5/

PLAO13

AGND

AVDD_REG

ADCREFP

IOGND

P1.5/

P1.6/

P0.7/IRQ4/

SDA2/

COMPDIN1/

PLAO5

P3.2/

AIN8/

COM0P

VDAC9/

P5.1

MISO1/

PWM3/

PLAO11

MOSI1/

PWM4/

PLAO12

PRTADDR2/

PWMTRIP/

PLAI14

ADCREFN

P0.6/IRQ3/

SCL2/

P3.1/

P0.4/SCL0/

SIN0/

P0.5/SDA0/

SOUT0/

PRTADDR1/

PWMSYNC/

PLAI13

VDAC11/

P5.3

AIN7/

AIN9/

G

H

AIN1

COMPDIN0/

PLAO4

VDAC2

COM0N

PLAO2

PLAO3

P3.5/

MCK/

SRDY1/

PLAO27

P3.0/

PRTADDR0/

SRDY0/

P3.6/

MDIO

VDAC10/

P5.2

AIN13/

COM2N

IOGND

DVDD

VDAC4

PLAI12

Figure 14. Pin Configuration

Table 12. Pin Function Descriptions

Pin No. Mnemonic

Type¹

Description

A1

A2

IOGND

S

I/O

Ground for Digital Inputs/Outputs.

Digital Input/Output Port 2.0 (P2.0).

P2.0/ADCCONV/COMPDIN2/PLAI8

External Input to Start ADC Conversions (ADCCONV).

Comparator 2 Digital Input for Three-State (COMPDIN2).

Input to PLA Element 8 (PLAI8).

Digital I/O Port 2.1 (P2.1).

A3

P2.1/DM/IRQ2/ECLKIN/COMPDIN3/PLAIꢁ I/O

Download Mode Selection (DM).

External Interrupt 2 (IRQ2).

External Input Clock (ECLKIN).

Comparator 3 Digital Input for Three-State (COMPDIN3).

Input to PLA Element ꢁ (PLAIꢁ).

Serial Wire Bidirectional Data.

Voltage DAC 7 Output.

Voltage DAC ꢀ Output.

A4

A5

Aꢀ

A7

A8

SWDIO

VDAC7

VDACꢀ

VDAC5

VDAC3

I/O

AO

Voltage DAC 5 Output.

Voltage DAC 3 Output.

Rev. 0 | Page 1ꢀ of 25

Data Sheet

ADuCM420

Pin No. Mnemonic

Type¹

Description

B1

P0.3/IRQ0/CS0/PLACLK0/PLAI3

I/O

Digital Input/Output Port 0.3 (P0.3).

External Interrupt 0 (IRQ0).

SPI Channel 0 (SPI0) Chip Select (CS0).

PLA Clock 0 (PLACLK0).

Input to PLA Element 3 (PLAI3).

Ball B1 is a multilevel voltage input/output with 3.3 V, 1.8 V, or 1.2 V

support. Note that 3.3 V is the default.

B2

B3

P0.2/MOSI0/PLACLK1/PLAI2

I/O

Digital Input/Output Port 0.2 (P0.2).

SPI0 Master Output, Slave Input (MOSI0).

PLA Clock 1 (PLACLK1).

Input to PLA Element 2 (PLAI2).

Ball B2 is a multilevel voltage input/output with 3.3 V, 1.8 V, or 1.2 V

support. Note that 3.3 V is the default.

P2.3/BM/PLAI10

Digital Input/Output Port 2.3 (P2.3). An internal pull-up resistor is enabled

at power-up on P2.3.

Boot Mode (BM). This pin determines the start-up sequence after every reset.

Input to PLA Element 10 (PLAI10).

B4

B5

Bꢀ

B7

B8

C1

C2

SWCLK

RESET

I

Serial Wire Debug Clock.

Reset Input (Active Low). An internal pull-up resistor is included with this pin.

Voltage DAC 1 Output.

0.ꢁ2 V Reference with 100 nF Capacitor.

3.3 V Analog Power Supply.

1.2 V or 1.8 V GPIO Supply.

Digital Input/Output Port 0.1 (P0.1).

SPI0 Master Input, Slave Output (MISO0).

Comparator 1 Output (COMOUT1)

VDAC1

VREF

AVDD

IOVDD1

AO

AO/AI

S

I/O

P0.1/MISO0/COMOUT1/PLAI1

Input to PLA Element 1 (PLAI1).

Ball C2 is a multilevel voltage input/output with 3.3 V, 1.8 V, or 1.2 V

support. Note that 3.3 V is the default.

C3

C4

P0.0/SCLK0/COMOUT0/PLAI0

P1.0/SIN1/COMOUT2/PLAI4

I/O

Digital Input/Output Port 0.0 (P0.0).

SPI0 Clock (SCLK0).

Comparator 0 Output (COMOUT0).

Input to PLA Element 0 (PLAI0).

Ball C3 is a multilevel voltage input/output with 3.3 V, 1.8 V, or 1.2 V

support. Note that 3.3 V is the default.

Digital Input/Output Port 1.0 (P1.0).

UART Input 1 (SIN1).

Comparator 2 Output (COMOUT2).

Input to PLA Element 4 (PLAI4).

Ball C4 is a multilevel voltage input/output with 3.3 V, 1.8 V, or 1.2 V

support. Note that 3.3 V is the default.

C5

Cꢀ

P2.2/POR/CLKOUT/SWO

I/O

Digital Input/Output Port 2.2 (P2.2).

Reset Output (POR). This pin function is an output, and it is the default.

Clock Output (CLKOUT).

SWD Output (SWO).

Analog Input 14 (AIN14).

AIN14/COM3P/BUF0_VREF

AI/AO

Comparator 3 Emitter Voltage (V_E) Positive (COM3P).

Buffered Reference Voltage source (BUF0_VREF).

Analog Input 2.

C7

C8

AIN2

AIN4/VDAC0

AI

Analog Input 4 (AIN4).

Voltage DAC 0 Output (VDAC0).

D1

D2

DVDD_REG

DGND

AO

S

0.ꢁ V Digital Regulator Supply with 0.47 ꢂF Decoupling Capacitor. Do not

use DVDD_REG to power external circuits.

Digital Ground.

Rev. 0| Page 17 of 25

ADuCM420

Data Sheet

Pin No. Mnemonic

Type¹

Description

D3

D4

D5

P1.2/SCL1/PWM0/PLAIꢀ

I/O

Digital Input/Output Port 1.2 (P1.2).

I²C Channel 1 (I²C1) Serial Clock (SCL1).

PWM Output 0 (PWM0).

Input to PLA Element ꢀ (PLAIꢀ).

Ball D3 is a multilevel voltage input/output with 3.3 V, 1.8 V, or 1.2 V

support. Note that 3.3 V is the default.

Digital Input/Output Port 1.3 (P1.3).

I²C1 Serial Data (SDA1).

PWM Output 1 (PWM1).

Input to PLA Element 7 (PLAI7).

Ball D4 is a multilevel voltage input/output with 3.3 V, 1.8 V, or 1.2 V

support. Note that 3.3 V is the default.

P1.3/SDA1/PWM1/PLAI7

I/O

P1.1/SOUT1/COMOUT3/PLAI5

Digital Input/Output Port 1.1 (P1.1).

UART Output 1 (SOUT1).

Comparator 3 Output (COMOUT3)

Input to PLA Element 5 (PLAI5).

Ball D5 is a multilevel voltage input/output with 3.3 V, 1.8 V, or 1.2 V

support. Note that 3.3 V is the default.

Dꢀ

D7

D8

AIN3

AIN0

AIN10/COM1P

AI

Analog Input 3.

Analog Input 0.

Analog Input 10 (AIN10).

Comparator 1 V_EPositive (COM1P).

3.3 V GPIO Supply.

Ground for Digital Inputs/Outputs.

Digital Input/Output Port 1.4 (P1.4).

SPI Channel 1 (SPI1) Clock (SCLK1).

PWM Output 2 (PWM2).

E1

E2

E3

IOVDD0

IOGND

P1.4/SCLK1/PWM2/PLAO10

S

I/O

Output of PLA Element 10 (PLAO10).

Ball E3 is a multilevel voltage input/output with 3.3 V, 1.8 V, or 1.2 V

support. Note that 3.3 V is the default.

E4

P1.7/IRQ1/CS1/PWM5/PLAO13

I/O

Digital Input/Output Port 1.7 (P1.7).

External Interrupt 1 (IRQ1).

SPI1 Chip Select (CS1).

PWM Output 5 (PWM5).

Output of PLA Element 13 (PLAO13).

Ball E4 is a multilevel voltage input/output with 3.3 V, 1.8 V, or 1.2 V

support. Note that 3.3 V is the default.

E5

Eꢀ

VDAC8/P5.0

AO/I/O Voltage DAC 8 Output (VDAC8).

Digital Input/Output Port 5.0 (P5.0).

AIN12/COM2P

AI

Analog Input 12 (AIN12).

Comparator 2 V_EPositive (COM2P).

Analog Ground.

E7

E8

AGND

AVDD_REG

S

AO

2.5 V Analog Regulator Supply with 0.47 ꢂF Decoupling Capacitor. Do not

use AVDD_REG to power external circuits.

F1

P1.5/MISO1/PWM3/PLAO11

I/O

Digital Input/Output Port 1.5 (P1.5).

SPI1 Master Input, Slave Output (MISO1).

PWM Output 3 (PWM3).

Output of PLA Element 11 (PLAO11).

Ball F1 is a multilevel voltage input/output with 3.3 V, 1.8 V, or 1.2 V

support. Note that 3.3 V is the default.

Rev. 0 | Page 18 of 25

Data Sheet

ADuCM420

Pin No. Mnemonic

Type¹

Description

F2

P1.ꢀ/MOSI1/PWM4/PLAO12

I/O

Digital Input/Output Port 1.ꢀ (P1.ꢀ).

SPI1 Master Output, Slave Input (MOSI1).

PWM Output 4 (PWM4).

Output of PLA Element 12 (PLAO12).

Ball F2 is a multilevel voltage input/output with 3.3 V, 1.8 V, or 1.2 V

support. Note that 3.3 V is the default.

F3

F4

P0.7/IRQ4/SDA2/COMPDIN1/PLAO5

P3.2/PRTADDR2/PWMTRIP/PLAI14

I/O

Digital Input/Output Port 0.7 (P0.7).

External Interrupt 4 (IRQ4).

I²C Channel 2 (I²C2) Serial Data (SDA2).

Comparator 1 Digital Input for Three-State (COMPDIN1).

Output of PLA Element 5 (PLAO5).

Digital Input/Output Port 3.2 (P3.2).

MDIO Port Address Bit 2 (PRTADDR2).

PWM Trip (PWMTRIP).

Input to PLA Element 14 (PLAI14).

F5

Fꢀ

VDACꢁ/P5.1

AIN8/COM0P

AO/I/O Voltage DAC ꢁ Output (VDACꢁ).

Digital Input/Output Port 5.1 (P5.1).

AI

Analog Input 8 (AIN8).

Comparator 0 V_EPositive (COM0P).

F7

F8

ADCREFN

ADCREFP

AO/AI

Decoupling Capacitor Connection for ADC. Connect this pin to AGND.

Decoupling Capacitor Connection for ADC Reference Buffer with 4.7 ꢂF

Decoupling Capacitor.

G1

G2

G3

P0.4/SCL0/SIN0/PLAO2

I/O

Digital Input/Output Port 0.4 (P0.4).

I²C Channel 0 (I²C0) Serial Clock (SCL0).

UART 0 Input (SIN0).

Output of PLA Element 2 (PLAO2).

Digital Input/Output Port 0.5 (P0.5).

I²C0 Serial Data (SDA0).

P0.5/SDA0/SOUT0/PLAO3

P0.ꢀ/IRQ3/SCL2/COMPDIN0/PLAO4

UART Output 0 (SOUT0).

Output of PLA Element 3 (PLAO3).

Digital Input/Output Port 0.ꢀ (P0.ꢀ).

External Interrupt 3 (IRQ3).

I²C2 Serial Clock (SCL2).

Comparator 0 Digital Input for Three-State (COMPDIN0).

Output of PLA Element 4 (PLAO4).

Digital Input/Output Port 3.1 (P3.1).

MDIO Port Address Bit 1 (PRTADDR1).

PWM Synchronization (PWMSYNC).

Input to PLA Element 13 (PLAI13).

G4

P3.1/PRTADDR1/PWMSYNC/PLAI13

I/O

G5

Gꢀ

VDAC11/P5.3

AIN7/VDAC2

AO/I/O Voltage DAC 11 Output (VDAC11).

Digital Input/Output Port 5.1 (P5.3).

AI

Analog Input 7 (AIN7).

Voltage DAC 2 Output (VDAC2).

Analog Input 1.

Analog Input ꢁ (AINꢁ).

G7

G8

AIN1

AINꢁ/COM0N

AI

Comparator 0 V_ENegative (COM0N).

Ground for Digital Inputs/Outputs.

1.8 V or 3.3 V Digital Power Supply.

Digital Input/Output Port 3.ꢀ (P3.ꢀ).

MDIO Slave Data (MDIO).

H1

H2

H3

IOGND

DVDD

P3.ꢀ/MDIO

S

I/O

H4

P3.5/MCK/SRDY1/PLAO27

I/O

Digital Input/Output Port 3.5 (P3.5).

MDIO Slave Clock (MCK).

SPI1 Ready (SRDY1).

Output of PLA Element 27 (PLAO27).

Rev. 0| Page 1ꢁ of 25

ADuCM420

Data Sheet

Pin No. Mnemonic

Type¹

Description

H5

P3.0/PRTADDR0/SRDY0/PLAI12

I/O

Digital Input/Output Port 3.0 (P3.0).

MDIO Port Address Bit 0 (PRTADDR0).

SPI0 Ready (SRDY0).

Input to PLA Element 12 (PLAI12).

Hꢀ

VDAC10/P5.2

AO/I/O Voltage DAC 10 Output (VDAC10).

Digital Input/Output Port 5.2 (P5.2).

H7

H8

VDAC4

AIN13/COM2N

AO

AI

Voltage DAC 4 Output.

Analog Input 13 (AIN13).

Comparator 2 V_ENegative (COM2N).

¹S is supply, I/O is input/output, AO is analog output, I is digital input, and AI is analog input.

Rev. 0 | Page 20 of 25

Data Sheet

ADuCM420

THEORY OF OPERATION

The ADuCM420 is an on-chip system. The ADuCM420 is

mixed-signal microcontroller based on the Arm Cortex-M33

processor.

to, all register details and information about the various

features and operation of the power management unit, the Arm

Cortex-M33 processor, the ADC circuit, the flash controller,

and the SPI, I²C, and UART interfaces.

See the ADuCM420 hardware reference manual for full details

on the operation of the ADuCM420, including, but not limited

Rev. 0| Page 21 of 25

ADuCM420

Data Sheet

APPLICATIONS INFORMATION

Note that the analog and digital ground pins on the ADuCM420

must be referenced to the same system ground reference point

at all times.

POWER SUPPLIES

The ADuCM420 operational power supply voltage is 2.85 V to

3.6 V for AVDD and IOVDD0, 1.2 V or 1.8 V for IOVDD1,

and 1.8 V to 3.6 V for DVDD. Separate analog (AVDD) and

digital power supply pins (IOVDD1 and DVDD) allow AVDD

to be kept relatively free of noisy digital signals often present in

the system DVDD line. In this mode, the ADuCM420 can also

operate with split supplies. That is, the device can use different

voltage levels for each supply as long as the minimum and

maximum specifications defined in Table 1 and Table 9 for

each supply are adhered to. A typical split supply configuration

is shown in Figure 15.

POWER-UP REQUIREMENTS

Figure 17 and Figure 18 show the power-up requirements for

DVDD and AVDD. Figure 19 shows the power-up requirement

for IOVDD0 if no external pull-up is applied to the

P2.3/BM/PLAI10 pin.

3.6

AFTER 50ms DVDD MUST

STAY ABOVE 1.7V INCLUDING

NOISE EXCURSIONS

DIGITAL SUPPLY

ANALOG SUPPLY

3.3V

10µF

1.8

1.7

ADuCM420

AVDD

DVDD

0.1µF

10µF

0.1µF

IOVDD0

50ms MIN

DVDD MUST BE ABOVE

1.8V FOR AT LEAST 50ms

TO COMPLETE POR

1

GND

REF

1.6

AGND

IOVDD1

DGND

1.8V

TIME (Not to Scale)

1

GND

IS A COMMON GROUND BETWEEN AGND AND DGND.

REF

Figure 17. DVDD Power-Up Requirements

Figure 15. External Multiple Supply Connections

25ms

DVDD

As an alternative to providing two separate power supplies, the

user can reduce noise on AVDD by placing a small series

resistor and/or ferrite bead between AVDD and DVDD and

then decoupling AVDD separately to ground. An example of

this configuration is shown in Figure 16. With this configuration,

other analog circuitry (such as op amps and voltage reference)

can be powered from the AVDD supply line as well.

AVDD

2.85V

1.6V

AFTER DVDD RISES

ABOVE 1.6V

(POR THRESHOLD),

AVDD MUST REACH

2.85V (min.) WITHIN 25ms.

OTHERWISE, RESET ADC

BEAD

1.6V

1

3.3V

AND VDACs IN SOFTWARE .

10µF

ADuCM420

AVDD

DVDD

0.1µF

10µF

0.1µF

TIME

DETAILS IN HARDWARE REFERENCE MANUAL.

IOVDD0

1

0.1µF

1

GND

REF

LDO

1.8V

Figure 18. AVDD Power-Up Requirements

AGND

IOVDD1

DGND

25ms

DVDD

IOVDD0

1

GND

IS A COMMON GROUND BETWEEN AGND AND DGND.

2.85V

1.6V

REF

Figure 16. External Single-Supply Connections

In both Figure 15 and Figure 16, a large value (10 μF) reservoir

capacitor is connected to DVDD, and a separate 10 μF capacitor is

connected to AVDD. In addition, local small value (0.1 μF)

capacitors are located at each AVDD, IOVDD0, IOVDD1, and

DVDD pin of the chip. As per standard design practice, include

all of these capacitors and ensure that the smaller capacitors are

close to each supply pin with trace lengths as short as possible.

Connect the ground terminal of each of these capacitors

directly to the underlying ground plane.

TIME

Figure 19. IOVDD0 Power-Up Requirement, No External Pull-Up

Rev. 0 | Page 22 of 25

Data Sheet

ADuCM420

Similarly, the analog supply pin (AVDD) requires a 0.1 μF

RECOMMENDED CIRCUIT AND COMPONENT

VALUES

capacitor placed as near as possible to each ball and its

associated AGND ball. Also, place a 10 ꢀF capacitor near these

balls.

Figure 20 shows a typical connection diagram for the ADuCM420.

Adequately decouple the supplies and regulators with

capacitors connected between the AVDD_REG, DVDD_REG,

and IOVDDx balls and their associated ground balls (AGND

and DGND). Table 12 indicates which ground balls are paired

with which supply balls.

The ADC reference requires a 4.7 ꢀF capacitor be placed

between ADCREFP and ADCREFN and located as near as

possible to each ball. ADCREFN must be connected directly to

AGND. The ADuCM420 contains two internal regulators.

These regulators require external decoupling capacitors. The

DVDD_REG and AVDD_REG balls each require a 0.47 μF

capacitor to DGND and AGND, respectively. Take care in the

layout to ensure that currents flowing from the ground end of

each decoupling capacitor to its associated ground ball share as

little track as possible with other ground currents on the PCB.

There are three digital supply balls, IOVDD0, IOVDD1, and

DVDD. Decouple these balls with a 0.1 μF capacitor placed as

near as possible to each of the three balls and their associated

ground balls (IOGND and DGND). In addition, place a 10 ꢀF

capacitor near these balls.

For DVDD, to improve noise reduction, place a ferrite bead in

series with a 10 ꢀF capacitor to DGND.

Rev. 0| Page 23 of 25

ADuCM420

Data Sheet

0.47µF

IOVDD0

10kΩ

RESET

IOVDD0

10kΩ

ADuCM420

P2.3/BM/PLAI10

P1.0/SIN1/COMOUT2/PLAI4

SWCLK

P1.1/SOUT1/COMOUT3/PLAI5

SWDIO

0.47µF

0.1µF

4.7µF

RESET

GND

RESET

SWDIO

Tx

SWCLK

Rx

NC

IOVDD0

AVDD

LT3022EMSE

VIN

IN

OUT

IOVDD1

0.1µF

10µF

10kΩ

0.1µF

10µF

0.1µF

10µF

PGND

AVDD

ADJ/SENSE

AGND

10µF

ADP7104ARDZ-3.3

AVDD

VIN

VOUT

PG

10kΩ

10µF

0.1µF

10µF

0.1µF

10µF

EN/UVLO

SENSE/ADJ

GND

Figure 20. Recommended Circuit and Component Values (ADuCM420, LT3022EMSE, and ADP7104ARDZ-3.3)

Rev. 0 | Page 24 of 25

Data Sheet

ADuCM420

OUTLINE DIMENSIONS

3.50

3.46 SQ

3.42

8

7

6

5

4

3

2

1

A

BALL A1

IDENTIFIER

B

C

D

E

F

2.80

REF

G

H

0.40

BSC

TOP VIEW

(BALL SIDE DOWN)

BOTTOM VIEW

(BALL SIDE UP)

0.330

0.300

0.270

2.80 REF

0.560

0.500

0.440

SIDE VIEW

COPLANARITY

0.05

0.300

0.260

0.220

SEATING

PLANE

0.230

0.200

0.170

Figure 21. 64-Ball Wafer Level Chip Scale Package [WLCSP]

(CB-64-2)

Dimensions shown in millimeters

ORDERING GUIDE

Model¹

Temperature Range

Package Description

Package Option

CB-ꢀ4-2

ADUCM420BCBZ-RL

ADUCM420BCBZ-RL7

EVAL-ADuCM420QSP1Z

−40°C to +105°C

ꢀ4-Ball Wafer Level Chip Scale Package [WLCSP]

WLCSP Evaluation Board and Quick Start Development System

¹Z = RoHS Compliant Part.

I²C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).

registered trademarks are the property of their respective owners.

D25843-1/21(0)

Rev. 0 | Page 25 of 25


型号：	ADUCM420BCBZ-RL7
厂家：	ADI
描述：	Precision Analog Microcontroller, 12-Bit Analog Input/Output with MDIO Interface, Arm Cortex-M33 微控制器
文件：	总25页 (文件大小：335K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADUCM420BCBZ-RL7 [ADI]

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