ADUM1402WSRWZ35-RL [ADI]
Interface Circuit, CMOS, PDSO16;
| 型号： | ADUM1402WSRWZ35-RL |
| 厂家： | 
ADI |
| 描述： | Interface Circuit, CMOS, PDSO16 光电二极管 |
| 文件： | 总31页 (文件大小：623K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Quad-Channel Digital Isolators
Data Sheet
ADuM1400/ADuM1401/ADuM1402
FEATURES
GENERAL DESCRIPTION
Qualified for automotive applications
Low power operation
5 V operation
The ADuM1400/ADuM1401/ADuM14021 are quad-channel
digital isolators based on Analog Devices, Inc., iCoupler®
technology. Combining high speed CMOS and monolithic air
core transformer technology, these isolation components provide
outstanding performance characteristics superior to alternatives,
such as optocoupler devices.
1.0 mA per channel maximum at 0 Mbps to 2 Mbps
3.5 mA per channel maximum at 10 Mbps
31 mA per channel maximum at 90 Mbps
3 V operation
0.7 mA per channel maximum at 0 Mbps to 2 Mbps
2.1 mA per channel maximum at 10 Mbps
20 mA per channel maximum at 90 Mbps
Bidirectional communication
By avoiding the use of LEDs and photodiodes, iCoupler devices
remove the design difficulties commonly associated with opto-
couplers. The typical optocoupler concerns regarding uncertain
current transfer ratios, nonlinear transfer functions, and
temperature and lifetime effects are eliminated with the simple
iCoupler digital interfaces and stable performance characteristics.
3 V/5 V level translation
High temperature operation: 125°C
High data rate: dc to 90 Mbps (NRZ)
Precise timing characteristics
2 ns maximum pulse width distortion
2 ns maximum channel-to-channel matching
High common-mode transient immunity: >25 kV/μs
Output enable function
16-lead SOIC wide body package
RoHS-compliant models available
Safety and regulatory approvals
UL recognition: 2500 V rms for 1 minute per UL 1577
CSA Component Acceptance Notice 5A
VDE Certificate of Conformity
The need for external drivers and other discrete components is
eliminated with these iCoupler products. Furthermore, iCoupler
devices consume one tenth to one sixth of the power of
optocouplers at comparable signal data rates.
The ADuM1400/ADuM1401/ADuM1402 isolators provide four
independent isolation channels in a variety of channel configu-
rations and data rates (see the Ordering Guide). All models
operate with the supply voltage on either side ranging from
2.7 V to 5.5 V, providing compatibility with lower voltage
systems as well as enabling a voltage translation functionality
across the isolation barrier. In addition, the ADuM1400/
ADuM1401/ADuM1402 provide low pulse width distortion
(<2 ns for CRW grade) and tight channel-to-channel matching
(<2 ns for CRW grade). Unlike other optocoupler alternatives, the
ADuM1400/ADuM1401/ADuM1402 isolators have a patented
refresh feature that ensures dc correctness in the absence of input
logic transitions and when power is not applied to one of the
supplies.
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
V
IORM = 560 V peak
TÜV approval: IEC/EN/UL/CSA 61010-1
APPLICATIONS
General-purpose multichannel isolation
SPI interface/data converter isolation
RS-232/RS-422/RS-485 transceivers
Industrial field bus isolation
1 Protected by U.S. Patents 5,952,849; 6,873,065; 6,903,578; and 7,075,329.
Automotive systems
FUNCTIONAL BLOCK DIAGRAMS
1
2
3
16
15
14
V
V
1
2
3
16
15
14
1
2
3
16
15
14
V
V
V
V
DD2
DD1
DD2
DD1
DD2
DD1
GND
V
GND
GND
V
GND
GND
V
GND
2
1
2
1
2
1
ENCODE
ENCODE
ENCODE
ENCODE
DECODE
DECODE
DECODE
DECODE
V
ENCODE
ENCODE
ENCODE
DECODE
DECODE
DECODE
DECODE
ENCODE
V
ENCODE
ENCODE
DECODE
DECODE
DECODE
DECODE
ENCODE
ENCODE
V
IA
IB
OA
IA
IB
OA
IA
IB
OA
V
4
5
13
12
V
V
V
4
5
13
12
4
5
13
12
V
V
OB
OB
OB
V
V
V
V
V
V
V
V
IC
ID
OC
IC
OC
OC
IC
6
7
8
11
10
9
V
6
7
8
11
10
9
6
7
8
11
10
9
V
V
V
OD
OD
ID
OD
ID
NC
GND
V
V
V
V
V
E2
E1
E2
E1
E2
GND
GND
GND
GND
GND
2
1
2
1
2
1
Figure 1. ADuM1400
Figure 2. ADuM1401
Figure 3. ADuM1402
Rev. L
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Tel: 781.329.4700 ©2003–2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
ADuM1400/ADuM1401/ADuM1402
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
DIN V VDE V 0884-10 (VDE V 0884-10) Insulation
Characteristics ............................................................................ 20
Recommended Operating Conditions .................................... 20
Absolute Maximum Ratings ......................................................... 21
ESD Caution................................................................................ 21
Pin Configurations and Function Descriptions......................... 22
Typical Performance Characteristics ........................................... 25
Applications Information .............................................................. 27
PC Board Layout ........................................................................ 27
Propagation Delay-Related Parameters................................... 27
DC Correctness and Magnetic Field Immunity..................... 27
Power Consumption .................................................................. 28
Insulation Lifetime..................................................................... 29
Outline Dimensions....................................................................... 30
Ordering Guide .......................................................................... 30
Automotive Products................................................................. 31
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagrams............................................................. 1
Revision History ............................................................................... 3
Specifications..................................................................................... 4
Electrical Characteristics—5 V, 105°C Operation ................... 4
Electrical Characteristics—3 V, 105°C Operation ................... 6
Electrical Characteristics—Mixed 5 V/3 V or 3 V/5 V, 105°C
Operation....................................................................................... 8
Electrical Characteristics—5 V, 125°C Operation ................. 11
Electrical Characteristics—3 V, 125°C Operation ................. 13
Electrical Characteristics—Mixed 5 V/3 V, 125°C Operation
....................................................................................................... 15
Electrical Characteristics—Mixed 3 V/5 V, 125°C Operation
....................................................................................................... 17
Package Characteristics ............................................................. 19
Regulatory Information............................................................. 19
Insulation and Safety Related Specifications .......................... 19
Rev. L | Page 2 of 31
Data Sheet
ADuM1400/ADuM1401/ADuM1402
REVISION HISTORY
12/2016—Rev. K to Rev. L
6/2007—Rev. D to Rev. E
Changes to Table 1 ............................................................................4
Changes to Table 2 ............................................................................6
Changes to Table 3 ............................................................................9
Changes to Table 4 ..........................................................................11
Changes to Table 5 ..........................................................................13
Changes to Table 6 ..........................................................................15
Changes to Table 7 ..........................................................................17
Changes to Table 9 and Table 10 ...................................................19
Changes to Ordering Guide...........................................................30
Updated VDE Certification Throughout.......................................1
Changes to Features and Note 1......................................................1
Changes to Figure 1, Figure 2, and Figure 3..................................1
Changes to Regulatory Information Section...............................10
Changes to Table 7 ..........................................................................11
Added Table 10................................................................................12
Added Insulation Lifetime Section...............................................20
Updated Outline Dimensions........................................................21
Changes to Ordering Guide...........................................................21
7/2015—Rev. J to Rev. K
Changes to Table 9 and Table 10 ...................................................19
2/2006—Rev. C to Rev. D
Updated Format ................................................................. Universal
Added TÜV Approval ....................................................... Universal
4/2015—Rev. I to Rev. J
Changed ADuM140x to ADuM1400/ADuM1401/
ADuM1402..................................................................... Throughout
Changes to Table 10 ........................................................................19
5/2005—Rev. B to Rev. C
Changes to Format............................................................. Universal
Changes to Figure 2 ..........................................................................1
Changes to Table 3 ............................................................................8
Changes to Table 6 ..........................................................................12
Changes to Ordering Guide...........................................................21
4/2014—Rev. H to Rev. I
Change to Table 9 ............................................................................19
3/2012—Rev. G to Rev. H
6/2004—Rev. A to Rev. B
Created Hyperlink for Safety and Regulatory Approvals
Entry in Features Section .................................................................1
Change to PC Board Layout Section ............................................27
Updated Outline Dimensions........................................................30
Moved Automotive Products Section...........................................31
Changes to Format............................................................. Universal
Changes to Features..........................................................................1
Changes to Electrical Characteristics—5 V Operation................3
Changes to Electrical Characteristics—3 V Operation................5
Changes to Electrical Characteristics—Mixed 5 V/3 V or
3 V/5 V Operation ............................................................................7
Changes to DIN EN 60747-5-2 (VDE 0884 Part 2) Insulation
Characteristics Title........................................................................11
Changes to the Ordering Guide ....................................................19
5/2008—Rev. F to Rev. G
Added ADuM1400W, ADuM1401W, and ADuM1402W
Parts......................................................................................Universal
Added Table 4 ..................................................................................11
Added Table 5 ..................................................................................13
Added Table 6 ..................................................................................15
Added Table 7 ..................................................................................17
Changes to Table 12 ........................................................................20
Changes to Table 13 ........................................................................21
Added Automotive Products Section ...........................................29
Changes to Ordering Guide...........................................................30
5/2004—Rev. 0 to Rev. A
Updated Format ................................................................. Universal
Changes to the Features....................................................................1
Changes to Table 7 and Table 8 .....................................................14
Changes to Table 9 ..........................................................................15
Changes to the DC Correctness and Magnetic Field Immunity
Section ..............................................................................................20
Changes to the Power Consumption Section..............................21
Changes to the Ordering Guide ....................................................22
11/2007—Rev. E to Rev. F
Changes to Note 1 .............................................................................1
Added ADuM140xARW Change vs. Temperature Parameter ...4
Added ADuM140xARW Change vs. Temperature Parameter ...5
Added ADuM140xARW Change vs. Temperature Parameter ...8
Changes to Figure 17 ......................................................................18
9/2003—Revision 0: Initial Version
Rev. L | Page 3 of 31
ADuM1400/ADuM1401/ADuM1402
Data Sheet
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—5 V, 105°C OPERATION1
4.5 V ≤ VDD1 ≤ 5.5 V, 4.5 V ≤ VDD2 ≤ 5.5 V; all minimum/maximum specifications apply over the entire recommended operation range,
unless otherwise noted; all typical specifications are at TA = 25°C, VDD1 = VDD2 = 5 V. These specifications do not apply to ADuM1400W,
ADuM1401W, and ADuM1402W automotive grade versions.
Table 1.
Parameter
Symbol
Min
Typ Max Unit
Test Conditions
DC SPECIFICATIONS
Input Supply Current per Channel, Quiescent
Output Supply Current per Channel, Quiescent
ADuM1400 Total Supply Current, Four Channels2
DC to 2 Mbps
IDDI (Q)
IDDO (Q)
0.50 0.53 mA
0.19 0.21 mA
VDD1 Supply Current
VDD2 Supply Current
IDD1 (Q)
IDD2 (Q)
2.2
0.9
2.8 mA
1.4 mA
DC to 1 MHz logic signal freq.
DC to 1 MHz logic signal freq.
10 Mbps (BRW and CRW Grades Only)
VDD1 Supply Current
VDD2 Supply Current
IDD1 (10)
IDD2 (10)
8.6
2.6
10.6 mA
3.5 mA
5 MHz logic signal freq.
5 MHz logic signal freq.
90 Mbps (CRW Grade Only)
VDD1 Supply Current
VDD2 Supply Current
IDD1 (90)
IDD2 (90)
70
18
100 mA
45 MHz logic signal freq.
45 MHz logic signal freq.
25
mA
ADuM1401 Total Supply Current, Four Channels2
DC to 2 Mbps
VDD1 Supply Current
VDD2 Supply Current
IDD1 (Q)
IDD2 (Q)
1.8
1.2
2.4 mA
1.8 mA
DC to 1 MHz logic signal freq.
DC to 1 MHz logic signal freq.
10 Mbps (BRW and CRW Grades Only)
VDD1 Supply Current
VDD2 Supply Current
IDD1 (10)
IDD2 (10)
7.1
4.1
9.0 mA
5.0 mA
5 MHz logic signal freq.
5 MHz logic signal freq.
90 Mbps (CRW Grade Only)
VDD1 Supply Current
VDD2 Supply Current
IDD1 (90)
IDD2 (90)
57
31
82
43
mA
mA
45 MHz logic signal freq.
45 MHz logic signal freq.
ADuM1402 Total Supply Current, Four Channels2
DC to 2 Mbps
VDD1 or VDD2 Supply Current
10 Mbps (BRW and CRW Grades Only)
VDD1 or VDD2 Supply Current
90 Mbps (CRW Grade Only)
VDD1 or VDD2 Supply Current
For All Models
IDD1 (Q), IDD2 (Q)
IDD1 (10), IDD2 (10)
IDD1 (90), IDD2 (90)
1.5
5.6
44
2.1 mA
7.0 mA
DC to 1 MHz logic signal freq.
5 MHz logic signal freq.
62
mA
45 MHz logic signal freq.
Input Currents
IIA, IIB, IIC,
IID, IE1, IE2
VIH, VEH
VIL, VEL
VOAH, VOBH
VOCH, VODH
−10
2.0
+0.01 +10 µA
V
0 V ≤ VIA, VIB, VIC, VID ≤ VDD1 or VDD2
0 V ≤ VE1, VE2 ≤ VDD1 or VDD2
,
Logic High Input Threshold
Logic Low Input Threshold
Logic High Output Voltages
0.8
V
V
V
V
V
V
,
(VDD1 or VDD2) − 0.1 5.0
(VDD1 or VDD2) − 0.4 4.8
0.0
IOx = −20 µA, VIx = VIxH
IOx = −3.2 mA, VIx = VIxH
IOx = 20 µA, VIx = VIxL
IOx = 400 µA, VIx = VIxL
IOx = 3.2 mA, VIx = VIxL
Logic Low Output Voltages
VOAL, VOBL,
VOCL, VODL
0.1
0.04 0.1
0.2
0.4
SWITCHING SPECIFICATIONS
ADuM1400ARW/ADuM1401ARW/ADuM1402ARW
Minimum Pulse Width3
PW
1000 ns
Mbps
100 ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
Maximum Data Rate4
1
50
Propagation Delay5
tPHL, tPLH
65
Rev. L | Page 4 of 31
Data Sheet
ADuM1400/ADuM1401/ADuM1402
Parameter
Symbol
Min
Typ Max Unit
Test Conditions
5
Pulse Width Distortion, |tPLH − tPHL
|
PWD
40
ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
Change vs. Temperature
Propagation Delay Skew6
Channel-to-Channel Matching7
11
ps/°C
ns
ns
tPSK
tPSKCD/tPSKOD
50
50
ADuM1400BRW/ADuM1401BRW/ADuM1402BRW
Minimum Pulse Width3
PW
100 ns
Mbps
ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
Maximum Data Rate4
10
20
Propagation Delay5
Pulse Width Distortion, |tPLH − tPHL
tPHL, tPLH
PWD
32
5
50
3
5
|
ns
Change vs. Temperature
Propagation Delay Skew6
Channel-to-Channel Matching, Codirectional
Channels7
ps/°C
ns
ns
tPSK
tPSKCD
15
3
Channel-to-Channel Matching, Opposing-
Directional Channels7
tPSKOD
6
ns
CL = 15 pF, CMOS signal levels
ADuM1400CRW/ADuM1401CRW/ADuM1402CRW
Minimum Pulse Width3
PW
8.3
120
27
0.5
3
11.1 ns
Mbps
ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
Maximum Data Rate4
90
18
Propagation Delay5
Pulse Width Distortion, |tPLH − tPHL
tPHL, tPLH
PWD
32
2
5
|
ns
Change vs. Temperature
Propagation Delay Skew6
Channel-to-Channel Matching, Codirectional
Channels7
ps/°C
ns
ns
tPSK
tPSKCD
10
2
Channel-to-Channel Matching, Opposing-
Directional Channels7
tPSKOD
5
ns
CL = 15 pF, CMOS signal levels
For All Models
Output Disable Propagation Delay (High/Low
to High Impedance)
Output Enable Propagation Delay (High
Impedance to High/Low)
Output Rise/Fall Time (10% to 90%)
Common-Mode Transient Immunity at Logic
High Output8
tPHZ, tPLH
tPZH, tPZL
6
6
8
8
ns
ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
VIx = VDD1 or VDD2, VCM = 1000 V,
transient magnitude = 800 V
VIx = 0 V, VCM = 1000 V,
tR/tF
|CMH|
2.5
35
ns
kV/µs
25
25
Common-Mode Transient Immunity at Logic
Low Output8
|CML|
35
kV/µs
transient magnitude = 800 V
Refresh Rate
fr
1.2
0.19
0.05
Mbps
mA/Mbps
mA/Mbps
Input Dynamic Supply Current per Channel9
IDDI (D)
Output Dynamic Supply Current per Channel9 IDDO (D)
1 All voltages are relative to their respective ground.
2 The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load
present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section.
See Figure 8 through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11 through
Figure 15 for total VDD1 and VDD2 supply currents as a function of data rate for ADuM1400/ADuM1401/ADuM1402 channel configurations.
3 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
4 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
5 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is
measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
6 tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load
within the recommended operating conditions.
7 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
8 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate
that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
magnitude is the range over which the common mode is slewed.
9 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for information
on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current
for a given data rate.
Rev. L | Page 5 of 31
ADuM1400/ADuM1401/ADuM1402
Data Sheet
ELECTRICAL CHARACTERISTICS—3 V, 105°C OPERATION1
2.7 V ≤ VDD1 ≤ 3.6 V, 2.7 V ≤ VDD2 ≤ 3.6 V; all minimum/maximum specifications apply over the entire recommended operation range,
unless otherwise noted; all typical specifications are at TA = 25°C, VDD1 = VDD2 = 3.0 V. These specifications do not apply to ADuM1400W,
ADuM1401W, and ADuM1402W automotive grade versions.
Table 2.
Parameter
Symbol
Min
Typ
Max Unit Test Conditions
DC SPECIFICATIONS
Input Supply Current per Channel, Quiescent
Output Supply Current per Channel, Quiescent
ADuM1400 Total Supply Current, Four Channels2
DC to 2 Mbps
IDDI (Q)
IDDO (Q)
0.26 0.31 mA
0.11 0.14 mA
VDD1 Supply Current
VDD2 Supply Current
IDD1 (Q)
IDD2 (Q)
1.2
0.5
1.9
0.9
mA
mA
DC to 1 MHz logic signal freq.
DC to 1 MHz logic signal freq.
10 Mbps (BRW and CRW Grades Only)
VDD1 Supply Current
VDD2 Supply Current
IDD1 (10)
IDD2 (10)
4.5
1.4
6.5
2.0
mA
mA
5 MHz logic signal freq.
5 MHz logic signal freq.
90 Mbps (CRW Grade Only)
VDD1 Supply Current
VDD2 Supply Current
IDD1 (90)
IDD2 (90)
37
11
65
15
mA
mA
45 MHz logic signal freq.
45 MHz logic signal freq.
ADuM1401 Total Supply Current, Four Channels2
DC to 2 Mbps
VDD1 Supply Current
VDD2 Supply Current
IDD1 (Q)
IDD2 (Q)
1.0
0.7
1.6
1.2
mA
mA
DC to 1 MHz logic signal freq.
DC to 1 MHz logic signal freq.
10 Mbps (BRW and CRW Grades Only)
VDD1 Supply Current
VDD2 Supply Current
IDD1 (10)
IDD2 (10)
3.7
2.2
5.4
3.0
mA
mA
5 MHz logic signal freq.
5 MHz logic signal freq.
90 Mbps (CRW Grade Only)
VDD1 Supply Current
VDD2 Supply Current
IDD1 (90)
IDD2 (90)
30
18
52
27
mA
mA
45 MHz logic signal freq.
45 MHz logic signal freq.
ADuM1402 Total Supply Current, Four Channels2
DC to 2 Mbps
VDD1 or VDD2 Supply Current
10 Mbps (BRW and CRW Grades Only)
VDD1 or VDD2 Supply Current
90 Mbps (CRW Grade Only)
VDD1 or VDD2 Supply Current
For All Models
IDD1 (Q), IDD2 (Q)
IDD1 (10), IDD2 (10)
IDD1 (90), IDD2 (90)
0.9
3.0
24
1.5
4.2
39
mA
mA
mA
DC to 1 MHz logic signal freq.
5 MHz logic signal freq.
45 MHz logic signal freq.
Input Currents
IIA, IIB, IIC,
IID, IE1, IE2
VIH, VEH
VIL, VEL
VOAH, VOBH
VOCH, VODH
−10
1.6
+0.01 +10 µA
V
0 V ≤ VIA, VIB, VIC, VID ≤ VDD1 or VDD2
0 V ≤ VE1, VE2 ≤ VDD1 or VDD2
,
Logic High Input Threshold
Logic Low Input Threshold
Logic High Output Voltages
0.4
V
V
V
V
V
V
,
(VDD1 or VDD2) − 0.1 3.0
(VDD1 or VDD2) − 0.4 2.8
0.0
IOx = −20 µA, VIx = VIxH
IOx = −3.2 mA, VIx = VIxH
IOx = 20 µA, VIx = VIxL
IOx = 400 µA, VIx = VIxL
IOx = 3.2 mA, VIx = VIxL
Logic Low Output Voltages
VOAL, VOBL
VOCL, VODL
,
0.1
0.04 0.1
0.2
0.4
SWITCHING SPECIFICATIONS
ADuM1400ARW/ADuM1401ARW/ADuM1402ARW
Minimum Pulse Width3
PW
1000 ns
CL = 15 pF, CMOS signal levels
Maximum Data Rate4
1
50
Mbps CL = 15 pF, CMOS signal levels
100 ns
Propagation Delay5
Pulse Width Distortion, |tPLH − tPHL
tPHL, tPLH
PWD
75
11
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
5
|
40
ns
Change vs. Temperature
ps/°C CL = 15 pF, CMOS signal levels
Propagation Delay Skew6
tPSK
tPSKCD/tPSKOD
50
50
ns
ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching7
Rev. L | Page 6 of 31
Data Sheet
ADuM1400/ADuM1401/ADuM1402
Parameter
Symbol
Min
Typ
Max Unit Test Conditions
ADuM1400BRW/ADuM1401BRW/ADuM1402BRW
Minimum Pulse Width3
PW
100 ns
CL = 15 pF, CMOS signal levels
Maximum Data Rate4
10
20
Mbps CL = 15 pF, CMOS signal levels
Propagation Delay5
Pulse Width Distortion, |tPLH − tPHL
tPHL, tPLH
PWD
38
5
50
3
ns
ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
5
|
Change vs. Temperature
Propagation Delay Skew6
Channel-to-Channel Matching, Codirectional
Channels7
ps/°C CL = 15 pF, CMOS signal levels
tPSK
tPSKCD
22
3
ns
ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching, Opposing-
Directional Channels7
tPSKOD
6
ns
CL = 15 pF, CMOS signal levels
ADuM1400CRW/ADuM1401CRW/ADuM1402CRW
Minimum Pulse Width3
PW
8.3
120
34
0.5
3
11.1 ns
CL = 15 pF, CMOS signal levels
Maximum Data Rate4
90
20
Mbps CL = 15 pF, CMOS signal levels
Propagation Delay5
Pulse Width Distortion, |tPLH − tPHL
tPHL, tPLH
PWD
45
2
ns
ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
5
|
Change vs. Temperature
Propagation Delay Skew6
Channel-to-Channel Matching, Codirectional
Channels7
ps/°C CL = 15 pF, CMOS signal levels
tPSK
tPSKCD
16
2
ns
ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching, Opposing-
Directional Channels7
tPSKOD
5
ns
CL = 15 pF, CMOS signal levels
For All Models
Output Disable Propagation Delay (High/Low to tPHZ, tPLH
High Impedance)
6
6
8
8
ns
ns
ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
Output Enable Propagation Delay (High
Impedance to High/Low)
tPZH, tPZL
Output Rise/Fall Time (10% to 90%)
tR/tF
3
Common-Mode Transient Immunity at Logic
High Output8
Common-Mode Transient Immunity at Logic
Low Output8
|CMH|
25
25
35
kV/µs VIx = VDD1 or VDD2, VCM = 1000 V,
transient magnitude = 800 V
kV/µs VIx = 0 V, VCM = 1000 V,
transient magnitude = 800 V
|CML|
35
Refresh Rate
Input Dynamic Supply Current per Channel9
fr
1.1
0.10
Mbps
mA/
IDDI (D)
Mbps
mA/
Output Dynamic Supply Current per Channel9
IDDO (D)
0.03
Mbps
1 All voltages are relative to their respective ground.
2 The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load
present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section.
See Figure 8 through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11 through
Figure 15 for total VDD1 and VDD2 supply currents as a function of data rate for ADuM1400/ADuM1401/ADuM1402 channel configurations.
3 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
4 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
5 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is
measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
6 tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load
within the recommended operating conditions.
7 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
8 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate
that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
magnitude is the range over which the common mode is slewed.
9 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for information
on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current
for a given data rate.
Rev. L | Page 7 of 31
ADuM1400/ADuM1401/ADuM1402
Data Sheet
ELECTRICAL CHARACTERISTICS—MIXED 5 V/3 V OR 3 V/5 V, 105°C OPERATION1
5 V/3 V operation: 4.5 V ≤ VDD1 ≤ 5.5 V, 2.7 V ≤ VDD2 ≤ 3.6 V; 3 V/5 V operation: 2.7 V ≤ VDD1 ≤ 3.6 V, 4.5 V ≤ VDD2 ≤ 5.5 V; all
minimum/maximum specifications apply over the entire recommended operation range, unless otherwise noted; all typical specifications
are at TA = 25°C; VDD1 = 3.0 V, VDD2 = 5 V or VDD1 = 5 V, VDD2 = 3. 0 V. These specifications do not apply to ADuM1400W, ADuM1401W,
and ADuM1402W automotive grade versions.
Table 3.
Parameter
Symbol
Min
Typ
Max Unit
Test Conditions
DC SPECIFICATIONS
Input Supply Current per Channel, Quiescent
5 V/3 V Operation
IDDI (Q)
0.50
0.26
0.53 mA
0.31 mA
3 V/5 V Operation
Output Supply Current per Channel, Quiescent
5 V/3 V Operation
3 V/5 V Operation
IDDO (Q)
0.11
0.19
0.14 mA
0.21 mA
ADuM1400 Total Supply Current, Four Channels2
DC to 2 Mbps
VDD1 Supply Current
5 V/3 V Operation
3 V/5 V Operation
IDD1 (Q)
2.2
1.2
2.8
1.9
mA
mA
DC to 1 MHz logic signal freq.
DC to 1 MHz logic signal freq.
VDD2 Supply Current
5 V/3 V Operation
3 V/5 V Operation
IDD2 (Q)
0.5
0.9
0.9
1.4
mA
mA
DC to 1 MHz logic signal freq.
DC to 1 MHz logic signal freq.
10 Mbps (BRW and CRW Grades Only)
VDD1 Supply Current
5 V/3 V Operation
IDD1 (10)
8.6
4.5
10.6 mA
5 MHz logic signal freq.
5 MHz logic signal freq.
3 V/5 V Operation
6.5
mA
VDD2 Supply Current
5 V/3 V Operation
3 V/5 V Operation
IDD2 (10)
1.4
2.6
2.0
3.5
mA
mA
5 MHz logic signal freq.
5 MHz logic signal freq.
90 Mbps (CRW Grade Only)
VDD1 Supply Current
5 V/3 V Operation
IDD1 (90)
70
37
100 mA
45 MHz logic signal freq.
45 MHz logic signal freq.
3 V/5 V Operation
65
mA
VDD2 Supply Current
5 V/3 V Operation
3 V/5 V Operation
IDD2 (90)
11
18
15
25
mA
mA
45 MHz logic signal freq.
45 MHz logic signal freq.
ADuM1401 Total Supply Current, Four Channels2
DC to 2 Mbps
VDD1 Supply Current
5 V/3 V Operation
3 V/5 V Operation
IDD1 (Q)
1.8
1.0
2.4
1.6
mA
mA
DC to 1 MHz logic signal freq.
DC to 1 MHz logic signal freq.
VDD2 Supply Current
5 V/3 V Operation
3 V/5 V Operation
IDD2 (Q)
0.7
1.2
1.2
1.8
mA
mA
DC to 1 MHz logic signal freq.
DC to 1 MHz logic signal freq.
10 Mbps (BRW and CRW Grades Only)
VDD1 Supply Current
5 V/3 V Operation
IDD1 (10)
7.1
3.7
9.0
5.4
mA
mA
5 MHz logic signal freq.
5 MHz logic signal freq.
3 V/5 V Operation
VDD2 Supply Current
5 V/3 V Operation
3 V/5 V Operation
IDD2 (10)
2.2
4.1
3.0
5.0
mA
mA
5 MHz logic signal freq.
5 MHz logic signal freq.
Rev. L | Page 8 of 31
Data Sheet
ADuM1400/ADuM1401/ADuM1402
Parameter
Symbol
Min
Typ
Max Unit
Test Conditions
90 Mbps (CRW Grade Only)
VDD1 Supply Current
5 V/3 V Operation
3 V/5 V Operation
IDD1 (90)
57
30
82
52
mA
mA
45 MHz logic signal freq.
45 MHz logic signal freq.
VDD2 Supply Current
5 V/3 V Operation
3 V/5 V Operation
IDD2 (90)
18
31
27
43
mA
mA
45 MHz logic signal freq.
45 MHz logic signal freq.
ADuM1402 Total Supply Current, Four Channels2
DC to 2 Mbps
VDD1 Supply Current
5 V/3 V Operation
3 V/5 V Operation
IDD1 (Q)
1.5
0.9
2.1
1.5
mA
mA
DC to 1 MHz logic signal freq.
DC to 1 MHz logic signal freq.
VDD2 Supply Current
5 V/3 V Operation
3 V/5 V Operation
IDD2 (Q)
0.9
1.5
1.5
2.1
mA
mA
DC to 1 MHz logic signal freq.
DC to 1 MHz logic signal freq.
10 Mbps (BRW and CRW Grades Only)
VDD1 Supply Current
5 V/3 V Operation
IDD1 (10)
5.6
3.0
7.0
4.2
mA
mA
5 MHz logic signal freq.
5 MHz logic signal freq.
3 V/5 V Operation
VDD2 Supply Current
5 V/3 V Operation
3 V/5 V Operation
IDD2 (10)
3.0
5.6
4.2
7.0
mA
mA
5 MHz logic signal freq.
5 MHz logic signal freq.
90 Mbps (CRW Grade Only)
VDD1 Supply Current
5 V/3 V Operation
IDD1 (90)
44
24
62
39
mA
mA
45 MHz logic signal freq.
45 MHz logic signal freq.
3 V/5 V Operation
VDD2 Supply Current
5 V/3 V Operation
3 V/5 V Operation
IDD2 (90)
24
44
39
62
mA
mA
45 MHz logic signal freq.
45 MHz logic signal freq.
For All Models
Input Currents
IIA, IIB, IIC,
IID, IE1, IE2
−10
+0.01
+10 µA
0 V ≤ VIA, VIB, VIC, VID ≤ VDD1 or VDD2
0 V ≤ VE1, VE2 ≤ VDD1 or VDD2
,
Logic High Input Threshold
5 V/3 V Operation
3 V/5 V Operation
VIH, VEH
2.0
1.6
V
V
Logic Low Input Threshold
5 V/3 V Operation
3 V/5 V Operation
VIL, VEL
0.8
0.4
V
V
V
V
V
V
V
Logic High Output Voltages
VOAH, VOBH
,
(VDD1 or VDD2) − 0.1 (VDD1 or VDD2
(VDD1 or VDD2) − 0.4 (VDD1 or VDD2) − 0.2
)
IOx = −20 µA, VIx = VIxH
IOx = −3.2 mA, VIx = VIxH
IOx = 20 µA, VIx = VIxL
IOx = 400 µA, VIx = VIxL
IOx = 3.2 mA, VIx = VIxL
VOCH, VODH
Logic Low Output Voltages
VOAL, VOBL
VOCL, VODL
,
0.0
0.04
0.2
0.1
0.1
0.4
SWITCHING SPECIFICATIONS
ADuM1400ARW/ADuM1401ARW/ADuM1402ARW
Minimum Pulse Width3
PW
1000 ns
Mbps
100 ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
Maximum Data Rate4
1
50
Propagation Delay5
Pulse Width Distortion, |tPLH − tPHL
Change vs. Temperature
tPHL, tPLH
PWD
70
11
5
|
40
ns
ps/°C
ns
ns
Propagation Delay Skew6
Channel-to-Channel Matching7
tPSK
tPSKCD/tPSKOD
50
50
ADuM1400BRW/ADuM1401BRW/ADuM1402BRW
Minimum Pulse Width3
Maximum Data Rate4
PW
100 ns
Mbps
50 ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
10
15
Propagation Delay5
tPHL, tPLH
35
Rev. L | Page 9 of 31
ADuM1400/ADuM1401/ADuM1402
Data Sheet
Parameter
Pulse Width Distortion, |tPLH − tPHL
Symbol
Min
Typ
Max Unit
Test Conditions
5
|
PWD
3
ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
Change vs. Temperature
Propagation Delay Skew6
Channel-to-Channel Matching, Codirectional
Channels7
5
ps/°C
ns
ns
tPSK
tPSKCD
22
3
Channel-to-Channel Matching, Opposing-
Directional Channels7
tPSKOD
6
ns
CL = 15 pF, CMOS signal levels
ADuM1400CRW/ADuM1401CRW/ADuM1402CRW
Minimum Pulse Width3
Maximum Data Rate4
PW
8.3
120
30
0.5
3
11.1 ns
Mbps
ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
90
20
Propagation Delay5
Pulse Width Distortion, |tPLH − tPHL
tPHL, tPLH
PWD
40
2
5
|
ns
Change vs. Temperature
Propagation Delay Skew6
Channel-to-Channel Matching, Codirectional
Channels7
ps/°C
ns
ns
tPSK
tPSKCD
14
2
Channel-to-Channel Matching, Opposing-
Directional Channels7
tPSKOD
5
ns
CL = 15 pF, CMOS signal levels
For All Models
Output Disable Propagation Delay (High/Low tPHZ, tPLH
to High Impedance)
6
6
8
8
ns
ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
Output Enable Propagation Delay (High
Impedance to High/Low)
tPZH, tPZL
Output Rise/Fall Time (10% to 90%)
5 V/3 V Operation
tR/tF
3.0
2.5
35
ns
ns
kV/µs
3 V/5 V Operation
Common-Mode Transient Immunity at Logic
High Output8
Common-Mode Transient Immunity at Logic
Low Output8
|CMH|
|CML|
fr
25
25
VIx = VDD1 or VDD2, VCM = 1000 V,
transient magnitude = 800 V
VIx = 0 V, VCM = 1000 V,
35
kV/µs
transient magnitude = 800 V
Refresh Rate
5 V/3 V Operation
3 V/5 V Operation
1.2
1.1
Mbps
Mbps
Input Dynamic Supply Current per Channel9
IDDI (D)
5 V/3 V Operation
3 V/5 V Operation
0.19
0.10
mA/Mbps
mA/Mbps
Output Dynamic Supply Current per Channel9
IDDO (D)
5 V/3 V Operation
3 V/5 V Operation
0.03
0.05
mA/Mbps
mA/Mbps
1 All voltages are relative to their respective ground.
2 The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load
present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section.
See Figure 8 through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11 through
Figure 15 for total VDD1 and VDD2 supply currents as a function of data rate for ADuM1400/ADuM1401/ADuM1402 channel configurations.
3 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
4 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
5 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is
measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
6 tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load
within the recommended operating conditions.
7 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
8 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate
that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
magnitude is the range over which the common mode is slewed.
9 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for information
on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current
for a given data rate.
Rev. L | Page 10 of 31
Data Sheet
ADuM1400/ADuM1401/ADuM1402
ELECTRICAL CHARACTERISTICS—5 V, 125°C OPERATION1
4.5 V ≤ VDD1 ≤ 5.5 V, 4.5 V ≤ VDD2 ≤ 5.5 V; all minimum/maximum specifications apply over the entire recommended operation range,
unless otherwise noted; all typical specifications are at TA = 25°C, VDD1 = VDD2 = 5 V. These specifications apply to ADuM1400W,
ADuM1401W, and ADuM1402W automotive grade versions.
Table 4.
Parameter
Symbol
Min
Typ
Max Unit
Test Conditions
DC SPECIFICATIONS
Input Supply Current per Channel, Quiescent
Output Supply Current per Channel, Quiescent
ADuM1400W, Total Supply Current, Four Channels2
DC to 2 Mbps
IDDI (Q)
IDDO (Q)
0.50 0.53 mA
0.19 0.21 mA
VDD1 Supply Current
VDD2 Supply Current
IDD1 (Q)
IDD2 (Q)
2.2
0.9
2.8
1.4
mA
mA
DC to 1 MHz logic signal freq.
DC to 1 MHz logic signal freq.
10 Mbps (TRWZ Grade Only)
VDD1 Supply Current
VDD2 Supply Current
IDD1 (10)
IDD2 (10)
8.6
2.6
10.6 mA
5 MHz logic signal freq.
5 MHz logic signal freq.
3.5
mA
ADuM1401W, Total Supply Current, Four Channels2
DC to 2 Mbps
VDD1 Supply Current
VDD2 Supply Current
IDD1 (Q)
IDD2 (Q)
1.8
1.2
2.4
1.8
mA
mA
DC to 1 MHz logic signal freq.
DC to 1 MHz logic signal freq.
10 Mbps (TRWZ Grade Only)
VDD1 Supply Current
VDD2 Supply Current
IDD1 (10)
IDD2 (10)
7.1
4.1
9.0
5.0
mA
mA
5 MHz logic signal freq.
5 MHz logic signal freq.
ADuM1402W, Total Supply Current, Four Channels2
DC to 2 Mbps
VDD1 or VDD2 Supply Current
10 Mbps (TRWZ Grade Only)
VDD1 or VDD2 Supply Current
For All Models
IDD1 (Q), IDD2 (Q)
IDD1 (10), IDD2 (10)
1.5
5.6
2.1
7.0
mA
mA
DC to 1 MHz logic signal freq.
5 MHz logic signal freq.
Input Currents
IIA, IIB, IIC,
IID, IE1, IE2
VIH, VEH
VIL, VEL
VOAH, VOBH
VOCH, VODH
−10
2.0
+0.01 +10 µA
V
0 V ≤ VIA, VIB, VIC, VID ≤ VDD1 or VDD2
0 V ≤ VE1, VE2 ≤ VDD1 or VDD2
,
Logic High Input Threshold
Logic Low Input Threshold
Logic High Output Voltages
0.8
V
V
V
V
V
V
,
(VDD1 or VDD2) − 0.1 5.0
(VDD1 or VDD2) − 0.4 4.8
0.0
IOx = −20 µA, VIx = VIxH
IOx = −3.2 mA, VIx = VIxH
IOx = 20 µA, VIx = VIxL
IOx = 400 µA, VIx = VIxL
IOx = 3.2 mA, VIx = VIxL
Logic Low Output Voltages
VOAL, VOBL
VOCL, VODL
,
0.1
0.04 0.1
0.2
0.4
SWITCHING SPECIFICATIONS
ADuM1400WSRWZ/ADuM1401WSRWZ/
ADuM1402WSRWZ
Minimum Pulse Width3
Maximum Data Rate4
PW
1000 ns
Mbps
100 ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
1
50
Propagation Delay5
tPHL, tPLH
PWD
tPSK
65
5
Pulse Width Distortion, |tPLH − tPHL
|
40
50
50
ns
ns
ns
Propagation Delay Skew6
Channel-to-Channel Matching7
tPSKCD/tPSKOD
Rev. L | Page 11 of 31
ADuM1400/ADuM1401/ADuM1402
Data Sheet
Parameter
Symbol
Min
Typ
Max Unit
Test Conditions
ADuM1400WTRWZ/ADuM1401WTRWZ/
ADuM1402WTRWZ
Minimum Pulse Width3
Maximum Data Rate4
PW
100 ns
Mbps
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
10
18
Propagation Delay5
tPHL, tPLH
PWD
27
5
34
3
ns
ns
5
Pulse Width Distortion, |tPLH − tPHL
Change vs. Temperature
Propagation Delay Skew6
Channel-to-Channel Matching, Codirectional
Channels7
|
ps/°C
ns
ns
tPSK
tPSKCD
15
3
Channel-to-Channel Matching, Opposing-
Directional Channels7
tPSKOD
6
ns
CL = 15 pF, CMOS signal levels
For All Models
Output Disable Propagation Delay (High/Low
to High Impedance)
Output Enable Propagation Delay (High
Impedance to High/Low)
Output Rise/Fall Time (10% to 90%)
Common-Mode Transient Immunity at Logic
High Output8
tPHZ, tPLH
tPZH, tPZL
6
6
8
8
ns
ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
VIx = VDD1/VDD2, VCM = 1000 V,
transient magnitude = 800 V
VIx = 0 V, VCM = 1000 V,
tR/tF
|CMH|
2.5
35
ns
kV/µs
25
25
Common-Mode Transient Immunity at Logic
Low Output8
|CML|
35
kV/µs
transient magnitude = 800 V
Refresh Rate
fr
1.2
0.19
0.05
Mbps
mA/Mbps
mA/Mbps
Input Dynamic Supply Current per Channel9
IDDI (D)
Output Dynamic Supply Current per Channel9 IDDO (D)
1 All voltages are relative to their respective ground.
2 The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load
present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section.
See Figure 8 through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11 through
Figure 15 for total VDD1 and VDD2 supply currents as a function of data rate for ADuM1400W/ADuM1401W/ADuM1402W channel configurations.
3 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
4 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
5 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is
measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
6 tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load
within the recommended operating conditions.
7 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
8 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate
that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
magnitude is the range over which the common mode is slewed.
9 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for information
on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current
for a given data rate.
Rev. L | Page 12 of 31
Data Sheet
ADuM1400/ADuM1401/ADuM1402
ELECTRICAL CHARACTERISTICS—3 V, 125°C OPERATION1
3.0 V ≤ VDD1 ≤ 3.6 V, 3.0 V ≤ VDD2 ≤ 3.6 V; all minimum/maximum specifications apply over the entire recommended operation range,
unless otherwise noted; all typical specifications are at TA = 25°C, VDD1 = VDD2 = 3.0 V. These specifications apply to ADuM1400W,
ADuM1401W, and ADuM1402W automotive grade versions.
Table 5.
Parameter
Symbol
Min
Typ
Max Unit
Test Conditions
DC SPECIFICATIONS
Input Supply Current per Channel,
Quiescent
Output Supply Current per Channel,
Quiescent
IDDI (Q)
0.26
0.11
0.31 mA
0.14 mA
IDDO (Q)
ADuM1400W, Total Supply Current, Four
Channels2
DC to 2 Mbps
VDD1 Supply Current
VDD2 Supply Current
10 Mbps (TRWZ Grade Only)
VDD1 Supply Current
VDD2 Supply Current
IDD1 (Q)
IDD2 (Q)
1.2
0.5
1.9
0.9
mA
mA
DC to 1 MHz logic signal freq.
DC to 1 MHz logic signal freq.
IDD1 (10)
IDD2 (10)
4.5
1.4
6.5
2.0
mA
mA
5 MHz logic signal freq.
5 MHz logic signal freq.
ADuM1401W, Total Supply Current, Four
Channels2
DC to 2 Mbps
VDD1 Supply Current
VDD2 Supply Current
10 Mbps (TRWZ Grade Only)
VDD1 Supply Current
VDD2 Supply Current
IDD1 (Q)
IDD2 (Q)
1.0
0.7
1.6
1.2
mA
mA
DC to 1 MHz logic signal freq.
DC to 1 MHz logic signal freq.
IDD1 (10)
IDD2 (10)
3.7
2.2
5.4
3.0
mA
mA
5 MHz logic signal freq.
5 MHz logic signal freq.
ADuM1402W, Total Supply Current, Four
Channels2
DC to 2 Mbps
VDD1 or VDD2 Supply Current
10 Mbps (TRWZ Grade Only)
VDD1 or VDD2 Supply Current
For All Models
IDD1 (Q), IDD2 (Q)
IDD1 (10), IDD2 (10)
0.9
1.5
mA
mA
µA
DC to 1 MHz logic signal freq.
5 MHz logic signal freq.
3.0
4.2
Input Currents
IIA, IIB, IIC,
IID, IE1, IE2
VIH, VEH
VIL, VEL
−10
1.6
+0.01
+10
0 V ≤ VIA, VIB, VIC, VID ≤ VDD1 or VDD2
0 V ≤ VE1, VE2 ≤ VDD1 or VDD2
,
Logic High Input Threshold
Logic Low Input Threshold
Logic High Output Voltages
V
V
V
V
V
V
V
0.4
VOAH, VOBH
,
(VDD1 or VDD2) − 0.1
(VDD1 or VDD2) − 0.4
3.0
2.8
0.0
0.04
0.2
IOx = −20 µA, VIx = VIxH
IOx = −3.2 mA, VIx = VIxH
IOx = 20 µA, VIx = VIxL
IOx = 400 µA, VIx = VIxL
IOx = 3.2 mA, VIx = VIxL
VOCH, VODH
Logic Low Output Voltages
VOAL, VOBL
,
0.1
0.1
0.4
VOCL, VODL
SWITCHING SPECIFICATIONS
ADuM1400WSRWZ/ADuM1401WSRWZ/
ADuM1402WSRWZ
Minimum Pulse Width3
Maximum Data Rate4
PW
1000 ns
Mbps
ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
1
50
Propagation Delay5
tPHL, tPLH
PWD
tPSK
75
100
40
5
Pulse Width Distortion, |tPLH − tPHL
|
ns
ns
ns
Propagation Delay Skew6
50
50
Channel-to-Channel Matching7
tPSKCD/tPSKOD
Rev. L | Page 13 of 31
ADuM1400/ADuM1401/ADuM1402
Data Sheet
Parameter
Symbol
Min
Typ
Max Unit
Test Conditions
ADuM1400WTRWZ/ADuM1401WTRWZ/
ADuM1402WTRWZ
Minimum Pulse Width3
Maximum Data Rate4
PW
100
ns
Mbps
ns
ns
ps/°C
ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
10
20
Propagation Delay5
tPHL, tPLH
PWD
34
5
45
3
5
Pulse Width Distortion, |tPLH − tPHL
Change vs. Temperature
Propagation Delay Skew6
Channel-to-Channel Matching,
Codirectional Channels7
|
tPSK
tPSKCD
22
3
ns
Channel-to-Channel Matching,
tPSKOD
6
ns
CL = 15 pF, CMOS signal levels
Opposing-Directional Channels7
For All Models
Output Disable Propagation Delay
(High/Low to High Impedance)
Output Enable Propagation Delay (High tPZH, tPZL
Impedance to High/Low)
tPHZ, tPLH
6
6
8
8
ns
ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
Output Rise/Fall Time (10% to 90%)
tR/tF
3
ns
Common-Mode Transient Immunity at
Logic High Output8
Common-Mode Transient Immunity at
Logic Low Output8
|CMH|
25
25
35
kV/µs
VIx = VDD1/VDD2, VCM = 1000 V,
transient magnitude = 800 V
VIx = 0 V, VCM = 1000 V,
|CML|
35
kV/µs
transient magnitude = 800 V
Refresh Rate
fr
1.1
Mbps
Input Dynamic Supply Current per
Channel9
IDDI (D)
0.10
mA/Mbps
Output Dynamic Supply Current per
Channel9
IDDO (D)
0.03
mA/Mbps
1 All voltages are relative to their respective ground.
2 The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load
present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section.
See Figure 8 through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11 through
Figure 15 for total VDD1 and VDD2 supply currents as a function of data rate for ADuM1400W/ADuM1401W/ADuM1402W channel configurations.
3 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
4 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
5 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is
measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
6 tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load
within the recommended operating conditions.
7 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
8 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate
that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
magnitude is the range over which the common mode is slewed.
9 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for information
on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current
for a given data rate.
Rev. L | Page 14 of 31
Data Sheet
ADuM1400/ADuM1401/ADuM1402
ELECTRICAL CHARACTERISTICS—MIXED 5 V/3 V, 125°C OPERATION1
4.5 V ≤ VDD1 ≤ 5.5 V, 3.0 V ≤ VDD2 ≤ 3.6 V; all minimum/maximum specifications apply over the entire recommended operation range,
unless otherwise noted; all typical specifications are at TA = 25°C; VDD1 = 5 V, VDD2 = 3.0 V. These specifications apply to ADuM1400W,
ADuM1401W, and ADuM1402W automotive grade versions.
Table 6.
Parameter
Symbol
Min
Typ
Max Unit
Test Conditions
DC SPECIFICATIONS
Input Supply Current per Channel, Quiescent
Output Supply Current per Channel, Quiescent
ADuM1400W, Total Supply Current, Four Channels2
DC to 2 Mbps
IDDI (Q)
IDDO (Q)
0.50
0.11
0.53 mA
0.14 mA
VDD1 Supply Current
VDD2 Supply Current
IDD1 (Q)
IDD2 (Q)
2.2
0.5
2.8
0.9
mA
mA
DC to 1 MHz logic signal freq.
DC to 1 MHz logic signal freq.
10 Mbps (TRWZ Grade Only)
VDD1 Supply Current
VDD2 Supply Current
IDD1 (10)
IDD2 (10)
8.6
1.4
10.6 mA
5 MHz logic signal freq.
5 MHz logic signal freq.
2.0
mA
ADuM1401W, Total Supply Current, Four Channels2
DC to 2 Mbps
VDD1 Supply Current
VDD2 Supply Current
IDD1 (Q)
IDD2 (Q)
1.8
0.7
2.4
1.2
mA
mA
DC to 1 MHz logic signal freq.
DC to 1 MHz logic signal freq.
10 Mbps (TRWZ Grade Only)
VDD1 Supply Current
VDD2 Supply Current
IDD1 (10)
IDD2 (10)
7.1
2.2
9.0
3.0
mA
mA
5 MHz logic signal freq.
5 MHz logic signal freq.
ADuM1402W, Total Supply Current, Four Channels2
DC to 2 Mbps
VDD1 Supply Current
VDD2 Supply Current
IDD1 (Q)
IDD2 (Q)
1.5
0.9
2.1
1.5
mA
mA
DC to 1 MHz logic signal freq.
DC to 1 MHz logic signal freq.
10 Mbps (TRWZ Grade Only)
VDD1 Supply Current
VDD2 Supply Current
IDD1 (10)
IDD2 (10)
5.6
3.0
7.0
4.2
mA
mA
5 MHz logic signal freq.
5 MHz logic signal freq.
For All Models
Input Currents
IIA, IIB, IIC,
IID, IE1, IE2
−10
+0.01
+10 µA
0 V ≤ VIA, VIB, VIC, VID ≤ VDD1
or VDD2, 0 V ≤ VE1, VE2 ≤ VDD1
or VDD2
Logic High Input Threshold
5 V/3 V Operation
3 V/5 V Operation
VIH, VEH
2.0
1.6
V
V
Logic Low Input Threshold
5 V/3 V Operation
3 V/5 V Operation
VIL, VEL
0.8
0.4
V
V
V
V
V
V
V
Logic High Output Voltages
VOAH, VOBH
,
(VDD1 or VDD2) − 0.1 VDD1 or VDD2
(VDD1 or VDD2) − 0.4 VDD1, VDD2 − 0.2
IOx = −20 µA, VIx = VIxH
IOx = −3.2 mA, VIx = VIxH
IOx = 20 µA, VIx = VIxL
IOx = 400 µA, VIx = VIxL
IOx = 3.2 mA, VIx = VIxL
VOCH, VODH
VOAL, VOBL
VOCL, VODL
Logic Low Output Voltages
,
0.0
0.04
0.2
0.1
0.1
0.4
SWITCHING SPECIFICATIONS
ADuM1400WSRWZ/ADuM1401WSRWZ/
ADuM1402WSRWZ
Minimum Pulse Width3
Maximum Data Rate4
PW
1000 ns
Mbps
100 ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
1
50
Propagation Delay5
tPHL, tPLH
PWD
tPSK
70
5
Pulse Width Distortion, |tPLH − tPHL
|
40
50
50
ns
ns
ns
Propagation Delay Skew6
Channel-to-Channel Matching7
tPSKCD/tPSKOD
Rev. L | Page 15 of 31
ADuM1400/ADuM1401/ADuM1402
Data Sheet
Parameter
Symbol
Min
Typ
Max Unit
Test Conditions
ADuM1400WTRWZ/ADuM1401WTRWZ/
ADuM1402WTRWZ
Minimum Pulse Width3
Maximum Data Rate4
PW
100 ns
Mbps
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
10
20
Propagation Delay5
tPHL, tPLH
PWD
30
5
40
3
ns
ns
5
Pulse Width Distortion, |tPLH − tPHL
Change vs. Temperature
Propagation Delay Skew6
Channel-to-Channel Matching, Codirectional
Channels7
|
ps/°C
ns
ns
tPSK
tPSKCD
22
3
Channel-to-Channel Matching, Opposing-
Directional Channels7
tPSKOD
6
ns
CL = 15 pF, CMOS signal levels
For All Models
Output Disable Propagation Delay (High/Low
to High Impedance)
Output Enable Propagation Delay (High
Impedance to High/Low)
Output Rise/Fall Time (10% to 90%)
Common-Mode Transient Immunity at Logic
High Output8
tPHZ, tPLH
tPZH, tPZL
6
6
8
8
ns
ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
VIx = VDD1/VDD2, VCM = 1000 V,
transient magnitude = 800 V
VIx = 0 V, VCM = 1000 V,
tR/tF
|CMH|
3.0
35
ns
kV/µs
25
25
Common-Mode Transient Immunity at Logic
Low Output8
|CML|
35
kV/µs
transient magnitude = 800 V
Refresh Rate
fr
1.2
Mbps
Input Dynamic Supply Current per Channel9
Output Dynamic Supply Current per Channel9
IDDI (D)
IDDO (D)
0.19
0.03
mA/Mbps
mA/Mbps
1 All voltages are relative to their respective ground.
2 The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load
present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section.
See Figure 8 through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11 through
Figure 15 for total VDD1 and VDD2 supply currents as a function of data rate for ADuM1400W/ADuM1401W/ADuM1402W channel configurations.
3 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
4 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
5 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is
measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
6 tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load
within the recommended operating conditions.
7 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
8 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate
that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
magnitude is the range over which the common mode is slewed.
9 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for information
on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current
for a given data rate.
Rev. L | Page 16 of 31
Data Sheet
ADuM1400/ADuM1401/ADuM1402
ELECTRICAL CHARACTERISTICS—MIXED 3 V/5 V, 125°C OPERATION1
3.0 V ≤ VDD1 ≤ 3.6 V, 4.5 V ≤ VDD2 ≤ 5.5 V; all minimum/maximum specifications apply over the entire recommended operation range,
unless otherwise noted; all typical specifications are at TA = 25°C; VDD1 = 3.0 V, VDD2 = 5 V. These specifications apply to ADuM1400W,
ADuM1401W, and ADuM1402W automotive grade versions.
Table 7.
Parameter
Symbol
Min
Typ
Max Unit
Test Conditions
DC SPECIFICATIONS
Input Supply Current per Channel, Quiescent
Output Supply Current per Channel, Quiescent IDDO (Q)
IDDI (Q)
0.26
0.19
0.31 mA
0.21 mA
ADuM1400W, Total Supply Current, Four
Channels2
DC to 2 Mbps
VDD1 Supply Current
VDD2 Supply Current
IDD1 (Q)
IDD2 (Q)
1.2
0.9
1.9
1.4
mA
mA
DC to 1 MHz logic signal freq.
DC to 1 MHz logic signal freq.
10 Mbps (TRWZ Grade Only)
VDD1 Supply Current
VDD2 Supply Current
IDD1 (10)
IDD2 (10)
4.5
2.6
6.5
3.5
mA
mA
5 MHz logic signal freq.
5 MHz logic signal freq.
ADuM1401W, Total Supply Current, Four
Channels2
DC to 2 Mbps
VDD1 Supply Current
VDD2 Supply Current
10 Mbps (TRWZ Grade Only)
VDD1 Supply Current
VDD2 Supply Current
IDD1 (Q)
IDD2 (Q)
1.0
1.2
1.6
1.8
mA
mA
DC to 1 MHz logic signal freq.
DC to 1 MHz logic signal freq.
IDD1 (10)
IDD2 (10)
3.7
4.1
5.4
5.0
mA
mA
5 MHz logic signal freq.
5 MHz logic signal freq.
ADuM1402W, Total Supply Current, Four
Channels2
DC to 2 Mbps
VDD1 Supply Current
VDD2 Supply Current
10 Mbps (TRWZ Grade Only)
VDD1 Supply Current
VDD2 Supply Current
For All Models
IDD1 (Q)
IDD2 (Q)
0.9
1.5
1.5
2.1
mA
mA
DC to 1 MHz logic signal freq.
DC to 1 MHz logic signal freq.
IDD1 (10)
IDD2 (10)
3.0
5.6
4.2
7.0
mA
mA
5 MHz logic signal freq.
5 MHz logic signal freq.
Input Currents
IIA, IIB, IIC,
IID, IE1, IE2
VIH, VEH
VIL, VEL
VOAH, VOBH
VOCH, VODH
VOAL, VOBL
VOCL, VODL
−10
1.6
+0.01
+10
0.4
µA
0 V ≤ VIA, VIB, VIC, VID ≤ VDD1 or
VDD2, 0 V ≤ VE1, VE2 ≤ VDD1 or VDD2
Logic High Input Threshold
Logic Low Input Threshold
Logic High Output Voltages
V
V
V
V
V
V
V
,
(VDD1 or VDD2) − 0.1 VDD1, VDD2
(VDD1 or VDD2) − 0.4 VDD1, VDD2 − 0.2
IOx = −20 µA, VIx = VIxH
IOx = −3.2 mA, VIx = VIxH
IOx = 20 µA, VIx = VIxL
IOx = 400 µA, VIx = VIxL
IOx = 3.2 mA, VIx = VIxL
Logic Low Output Voltages
,
0.0
0.04
0.2
0.1
0.1
0.4
SWITCHING SPECIFICATIONS
ADuM1400WSRWZ/ADuM1401WSRWZ/
ADuM1402WSRWZ
Minimum Pulse Width3
Maximum Data Rate4
PW
1000 ns
Mbps
ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
1
50
Propagation Delay5
tPHL, tPLH
PWD
tPSK
70
100
40
5
Pulse Width Distortion, |tPLH − tPHL
|
ns
ns
ns
Propagation Delay Skew6
50
50
Channel-to-Channel Matching7
tPSKCD/tPSKOD
Rev. L | Page 17 of 31
ADuM1400/ADuM1401/ADuM1402
Data Sheet
Parameter
Symbol
Min
Typ
Max Unit
Test Conditions
ADuM1400WTRWZ/ADuM1401WTRWZ/
ADuM1402WTRWZ
Minimum Pulse Width3
Maximum Data Rate4
PW
100
ns
Mbps
ns
ns
ps/°C
ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
10
20
Propagation Delay5
tPHL, tPLH
PWD
30
5
40
3
5
Pulse Width Distortion, |tPLH − tPHL
Change vs. Temperature
Propagation Delay Skew6
Channel-to-Channel Matching,
Codirectional Channels7
|
tPSK
tPSKCD
22
3
ns
Channel-to-Channel Matching, Opposing-
Directional Channels7
tPSKOD
6
ns
CL = 15 pF, CMOS signal levels
For All Models
Output Disable Propagation Delay
(High/Low to High Impedance)
Output Enable Propagation Delay (High
Impedance to High/Low)
Output Rise/Fall Time (10% to 90%)
Common-Mode Transient Immunity at
Logic High Output8
tPHZ, tPLH
tPZH, tPZL
6
6
8
8
ns
ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
VIx = VDD1/VDD2, VCM = 1000 V,
transient magnitude = 800 V
VIx = 0 V, VCM = 1000 V,
tR/tF
|CMH|
2.5
35
ns
kV/µs
25
25
Common-Mode Transient Immunity at
Logic Low Output8
|CML|
35
kV/µs
transient magnitude = 800 V
Refresh Rate
fr
1.1
Mbps
Input Dynamic Supply Current per Channel9
Output Dynamic Supply Current per Channel9
IDDI (D)
IDDO (D)
0.10
0.05
mA/Mbps
mA/Mbps
1 All voltages are relative to their respective ground.
2 The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load
present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section.
See Figure 8 through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11 through
Figure 15 for total VDD1 and VDD2 supply currents as a function of data rate for ADuM1400W/ADuM1401W/ADuM1402W channel configurations.
3 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
4 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
5 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is
measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
6 tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load
within the recommended operating conditions.
7 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
8 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate
that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
magnitude is the range over which the common mode is slewed.
9 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for information
on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current
for a given data rate.
Rev. L | Page 18 of 31
Data Sheet
ADuM1400/ADuM1401/ADuM1402
PACKAGE CHARACTERISTICS
Table 8.
Parameter
Symbol
RI-O
CI-O
CI
θJCI
Min
Typ
1012
2.2
4.0
33
Max
Unit
Ω
pF
pF
°C/W
°C/W
Test Conditions
Resistance (Input to Output)1
Capacitance (Input to Output)1
Input Capacitance2
f = 1 MHz
IC Junction to Case Thermal Resistance, Side 1
IC Junction to Case Thermal Resistance, Side 2
Thermocouple located at
center of package underside
θJCO
28
1 Device is considered a 2-terminal device; Pin 1, Pin 2, Pin 3, Pin 4, Pin 5, Pin 6, Pin 7, and Pin 8 are shorted together and Pin 9, Pin 10, Pin 11, Pin 12, Pin 13, Pin 14,
Pin 15, and Pin 16 are shorted together.
2 Input capacitance is from any input data pin to ground.
REGULATORY INFORMATION
The ADuM1400/ADuM1401/ADuM1402 are approved by the organizations listed in Table 9. Refer to Table 14 and the Insulation Lifetime
section for details regarding recommended maximum working voltages for specific cross-isolation waveforms and insulation levels.
Table 9.
UL
CSA
VDE
CQC
TÜV
Recognized Under
UL 1577 Component CSA Component
Approved under
Certified according to
DIN V VDE V 0884-10
(VDE V 0884-10):2006-122
Approved under
CQC11-471543-2012
Approved according to
IEC 61010-1:2001 (2nd Edition),
EN 61010-1:2001 (2nd Edition),
UL 61010-1:2004, and
Recognition
Acceptance Notice 5A
Program1
CSA C22.2.61010.1:2005
Single Protection,
2500 V rms Isolation CSA 60950-1-03 and
Voltage
Basic insulation per
Reinforced insulation,
560 V peak
Basic Insulation per
Reinforced insulation, 400 V rms
maximum working voltage
GB4943.1-2011, 415 V rms
(588 V peak) maximum
working voltage, tropical
climate, altitude ≤ 5000 m
IEC 60950-1, 780 V rms
(1103 V peak) maximum
working voltage
Reinforced insulation
per CSA 60950-1-03 and
IEC 60950-1, 390 V rms
(551 V peak) maximum
working voltage
File E214100
File 205078
File 2471900-4880-0001
File CQC14001114900
Certificate U8V 05 06 56232 002
1 In accordance with UL 1577, each ADuM1400/ADuM1401/ADuM1402 is proof tested by applying an insulation test voltage ≥3000 V rms for 1 sec (current leakage
detection limit = 5 µA).
2 In accordance with DIN V VDE V 0884-10, each ADuM1400/ADuM1401/ADuM1402 is proof tested by applying an insulation test voltage ≥1050 V peak for 1 sec (partial
discharge detection limit = 5 pC). The asterisk (*) marking branded on the component designates DIN V VDE V 0884-10 approval.
INSULATION AND SAFETY RELATED SPECIFICATIONS
Table 10.
Parameter
Symbol Value
Unit Conditions
Rated Dielectric Insulation Voltage
Minimum External Air Gap (Clearance)
2500
V rms 1-minute duration
L(I01)
L(I02)
L(PCB)
7.8 min
7.8 min
8.3 min
mm
mm
mm
Measured from input terminals to output terminals,
shortest distance through air
Minimum External Tracking (Creepage)
Measured from input terminals to output terminals,
shortest distance path along body
Measured from input terminals to output terminals,
shortest distance through air, and line of sight, in the
PCB mounting plane
Minimum Clearance in the Plane of the Printed
Circuit Board (PCB Clearance)
Minimum Internal Gap (Internal Clearance)
Tracking Resistance (Comparative Tracking Index)
Isolation Group
0.017 min mm
Insulation distance through insulation
DIN IEC 112/VDE 0303 Part 1
Material Group (DIN VDE 0110, 1/89, Table 1)
CTI
>400
II
V
Rev. L | Page 19 of 31
ADuM1400/ADuM1401/ADuM1402
Data Sheet
DIN V VDE V 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS
These isolators are suitable for reinforced electrical isolation only within the safety limit data. Maintenance of the safety data is ensured by
protective circuits. The asterisk (*) marking on packages denotes DIN V VDE V 0884-10 approval.
Table 11.
Description
Conditions
Symbol Characteristic Unit
Installation Classification per DIN VDE 0110
For Rated Mains Voltage ≤ 150 V rms
For Rated Mains Voltage ≤ 300 V rms
For Rated Mains Voltage ≤ 400 V rms
Climatic Classification
Pollution Degree per DIN VDE 0110, Table 1
Maximum Working Insulation Voltage
Input to Output Test Voltage, Method B1
I to IV
I to III
I to II
40/105/21
2
VIORM
VPR
560
1050
V peak
V peak
VIORM × 1.875 = VPR, 100% production test, tm = 1 sec,
partial discharge < 5 pC
Input to Output Test Voltage, Method A
After Environmental Tests Subgroup 1
After Input and/or Safety Test Subgroup 2
and Subgroup 3
Highest Allowable Overvoltage
Safety Limiting Values
VIORM × 1.6 = VPR, tm = 60 sec, partial discharge < 5 pC
VPR
896
672
V peak
V peak
VIORM × 1.2 = VPR, tm = 60 sec, partial discharge < 5 pC
Transient overvoltage, tTR = 10 seconds
Maximum value allowed in the event of a failure
(see Figure 4)
VTR
4000
V peak
Case Temperature
Side 1 Current
Side 2 Current
TS
IS1
IS2
RS
150
265
335
>109
°C
mA
mA
Ω
Insulation Resistance at TS
VIO = 500 V
350
RECOMMENDED OPERATING CONDITIONS
300
Table 12.
Parameter
Rating
250
Operating Temperature (TA)1
Operating Temperature (TA)2
−40°C to +105°C
−40°C to +125°C
2.7 V to 5.5 V
3.0 V to 5.5 V
1.0 ms
SIDE #2
200
1, 3
Supply Voltages (VDD1, VDD2
Supply Voltages (VDD1, VDD2
)
)
150
2, 3
SIDE #1
Input Signal Rise and Fall Times
100
50
0
1 Does not apply to ADuM1400W, ADuM1401W, and ADuM1402W automotive
grade versions.
2 Applies to ADuM1400W, ADuM1401W, and ADuM1402W automotive grade
versions.
0
50
100
150
200
3 All voltages are relative to their respective ground. See the DC Correctness
and Magnetic Field Immunity section for information on immunity to
external magnetic fields.
CASE TEMPERATURE (°C)
Figure 4. Thermal Derating Curve, Dependence of Safety Limiting Values
with Case Temperature per DIN V VDE V 0884-10
Rev. L | Page 20 of 31
Data Sheet
ADuM1400/ADuM1401/ADuM1402
ABSOLUTE MAXIMUM RATINGS
Ambient temperature = 25°C, unless otherwise noted.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Table 13.
Parameter
Rating
Storage Temperature (TST)
Ambient Operating Temperature (TA)1
−65°C to +150°C
−40°C to +105°C
−40°C to +125°C
−0.5 V to +7.0 V
−0.5 V to VDDI + 0.5 V
−0.5 V to VDDO + 0.5 V
Ambient Operating Temperature (TA)2
3
Supply Voltages (VDD1, VDD2
)
Input Voltage (VIA, VIB, VIC, VID, VE1, VE2)3, 4
Output Voltage (VOA, VOB, VOC, VOD)3, 4
Average Output Current per Pin5
Side 1 (IO1)
ESD CAUTION
−18 mA to +18 mA
−22 mA to +22 mA
−100 kV/µs to +100 kV/µs
Side 2 (IO2)
Common-Mode Transients6
1 Does not apply to ADuM1400W, ADuM1401W, and ADuM1402W automotive
grade versions.
2 Applies to ADuM1400W, ADuM1401W, and ADuM1402W automotive grade
versions.
3 All voltages are relative to their respective ground.
4 VDDI and VDDO refer to the supply voltages on the input and output sides of a
given channel, respectively. See the PC Board Layout section.
5 See Figure 4 for maximum rated current values for various temperatures.
6 This refers to common-mode transients across the insulation barrier.
Common-mode transients exceeding the Absolute Maximum Ratings
may cause latch-up or permanent damage.
Table 14. Maximum Continuous Working Voltage1
Parameter
Max
Unit
Constraint
AC Voltage, Bipolar Waveform
AC Voltage, Unipolar Waveform
Basic Insulation
Reinforced Insulation
DC Voltage
565
V peak
50-year minimum lifetime
1131
560
V peak
V peak
Maximum approved working voltage per IEC 60950-1
Maximum approved working voltage per IEC 60950-1 and VDE V 0884-10
Basic Insulation
Reinforced Insulation
1131
560
V peak
V peak
Maximum approved working voltage per IEC 60950-1
Maximum approved working voltage per IEC 60950-1 and VDE V 0884-10
1 Refers to continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for more details.
Table 15. Truth Table (Positive Logic)
VIx Input1 VEx Input1, 2 VDDI State1 VDDO State1 VOx Output1
Notes
H
L
X
X
X
X
H or NC
H or NC
L
H or NC
L
X
Powered
Powered
Powered
Unpowered Powered
Unpowered Powered
Powered
Powered
Powered
H
L
Z
H
Z
Outputs return to the input state within 1 µs of VDDI power restoration.
Powered
Unpowered Indeterminate Outputs return to the input state within 1 µs of VDDO power restoration
if the VEx state is H or NC. Outputs return to a high impedance state
within 8 ns of VDDO power restoration if the VEx state is L.
1 VIx and VOx refer to the input and output signals of a given channel (A, B, C, or D). VEx refers to the output enable signal on the same side as the VOx outputs. VDDI and
DDO refer to the supply voltages on the input and output sides of the given channel, respectively.
2 In noisy environments, connecting VEx to an external logic high or low is recommended.
V
Rev. L | Page 21 of 31
ADuM1400/ADuM1401/ADuM1402
Data Sheet
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
V
1
2
3
4
5
6
7
8
16
V
DD2
DD1
*GND
15 GND *
1
IA
IB
IC
ID
2
V
V
V
V
14
13
12
11
10
9
V
V
V
V
V
OA
OB
OC
OD
E2
ADuM1400
TOP VIEW
(Not to Scale)
NC
*GND
GND *
1
2
NC = NO CONNECT
*PIN 2 AND PIN 8 ARE INTERNALLY CONNECTED, AND CONNECTING
BOTH TO GND IS RECOMMENDED. PIN 9 AND PIN 15 ARE INTERNALLY
1
CONNECTED, AND CONNECTING BOTH TO GND IS RECOMMENDED.
2
Figure 5. ADuM1400 Pin Configuration
Table 16. ADuM1400 Pin Function Descriptions
Pin No. Mnemonic Description
1
2
3
4
5
6
7
8
9
10
VDD1
GND1
VIA
VIB
VIC
VID
NC
GND1
GND2
VE2
Supply Voltage for Isolator Side 1.
Ground 1. Ground reference for Isolator Side 1.
Logic Input A.
Logic Input B.
Logic Input C.
Logic Input D.
No Connect.
Ground 1. Ground reference for Isolator Side 1.
Ground 2. Ground reference for Isolator Side 2.
Output Enable 2. Active high logic input. VOA, VOB, VOC, and VOD outputs are enabled when VE2 is high or disconnected.
VOA, VOB, VOC, and VOD outputs are disabled when VE2 is low. In noisy environments, connecting VE2 to an external logic
high or low is recommended.
11
12
13
14
15
16
VOD
VOC
VOB
VOA
GND2
VDD2
Logic Output D.
Logic Output C.
Logic Output B.
Logic Output A.
Ground 2. Ground reference for Isolator Side 2.
Supply Voltage for Isolator Side 2.
Rev. L | Page 22 of 31
Data Sheet
ADuM1400/ADuM1401/ADuM1402
V
1
2
3
4
5
6
7
8
16
V
DD2
DD1
*GND
15 GND *
1
IA
IB
IC
2
V
V
V
14
13
12
11
10
9
V
V
V
V
V
OA
OB
OC
ID
ADuM1401
TOP VIEW
(Not to Scale)
V
OD
V
E1
E2
*GND
GND *
2
1
*PIN 2 AND PIN 8 ARE INTERNALLY CONNECTED, AND CONNECTING
BOTH TO GND IS RECOMMENDED. PIN 9 AND PIN 15 ARE INTERNALLY
1
CONNECTED, AND CONNECTING BOTH TO GND IS RECOMMENDED.
2
Figure 6. ADuM1401 Pin Configuration
Table 17. ADuM1401 Pin Function Descriptions
Pin No. Mnemonic Description
1
2
3
4
5
6
7
VDD1
GND1
VIA
VIB
VIC
Supply Voltage for Isolator Side 1.
Ground 1. Ground reference for Isolator Side 1.
Logic Input A.
Logic Input B.
Logic Input C.
VOD
VE1
Logic Output D.
Output Enable 1. Active high logic input. VOD output is enabled when VE1 is high or disconnected. VOD is disabled
when VE1 is low. In noisy environments, connecting VE1 to an external logic high or low is recommended.
8
9
10
GND1
GND2
VE2
Ground 1. Ground reference for Isolator Side 1.
Ground 2. Ground reference for Isolator Side 2.
Output Enable 2. Active high logic input. VOA, VOB, and VOC outputs are enabled when VE2 is high or disconnected. VOA,
VOB, and VOC outputs are disabled when VE2 is low. In noisy environments, connecting VE2 to an external logic high or
low is recommended.
11
12
13
14
15
16
VID
VOC
VOB
VOA
GND2
VDD2
Logic Input D.
Logic Output C.
Logic Output B.
Logic Output A.
Ground 2. Ground reference for Isolator Side 2.
Supply Voltage for Isolator Side 2.
Rev. L | Page 23 of 31
ADuM1400/ADuM1401/ADuM1402
Data Sheet
V
1
2
3
4
5
6
7
8
16
V
DD2
DD1
*GND
15 GND *
1
IA
IB
2
V
V
14
13
12
11
10
9
V
V
V
V
V
OA
OB
IC
ADuM1402
TOP VIEW
(Not to Scale)
V
V
OC
OD
ID
V
E1
E2
*GND
GND *
2
1
*PIN 2 AND PIN 8 ARE INTERNALLY CONNECTED, AND CONNECTING
BOTH TO GND IS RECOMMENDED. PIN 9 AND PIN 15 ARE INTERNALLY
1
CONNECTED, AND CONNECTING BOTH TO GND IS RECOMMENDED.
2
Figure 7. ADuM1402 Pin Configuration
Table 18. ADuM1402 Pin Function Descriptions
Pin No. Mnemonic Description
1
2
3
4
5
6
7
VDD1
GND1
VIA
Supply Voltage for Isolator Side 1.
Ground 1. Ground reference for Isolator Side 1.
Logic Input A.
Logic Input B.
Logic Output C.
VIB
VOC
VOD
VE1
Logic Output D.
Output Enable 1. Active high logic input. VOC and VOD outputs are enabled when VE1 is high or disconnected. VOC and
VOD outputs are disabled when VE1 is low. In noisy environments, connecting VE1 to an external logic high or low is
recommended.
8
9
10
GND1
GND2
VE2
Ground 1. Ground reference for Isolator Side 1.
Ground 2. Ground reference for Isolator Side 2.
Output Enable 2. Active high logic input. VOA and VOB outputs are enabled when VE2 is high or disconnected. VOA and
VOB outputs are disabled when VE2 is low. In noisy environments, connecting VE2 to an external logic high or low is
recommended.
11
12
13
14
15
16
VID
VIC
VOB
VOA
GND2
VDD2
Logic Input D.
Logic Input C.
Logic Output B.
Logic Output A.
Ground 2. Ground reference for Isolator Side 2.
Supply Voltage for Isolator Side 2.
Rev. L | Page 24 of 31
Data Sheet
ADuM1400/ADuM1401/ADuM1402
TYPICAL PERFORMANCE CHARACTERISTICS
20
80
70
60
50
40
30
20
10
0
15
10
5V
5V
3V
3V
5
0
0
20
40
60
80
100
0
20
40
60
80
100
DATA RATE (Mbps)
DATA RATE (Mbps)
Figure 8. Typical Input Supply Current per Channel vs. Data Rate
for 5 V and 3 V Operation
Figure 11. Typical ADuM1400 VDD1 Supply Current vs. Data Rate
for 5 V and 3 V Operation
6
5
4
3
25
20
15
10
5V
5V
2
3V
3V
5
1
0
0
0
20
40
60
80
100
0
20
40
60
80
100
DATA RATE (Mbps)
DATA RATE (Mbps)
Figure 12. Typical ADuM1400 VDD2 Supply Current vs. Data Rate
for 5 V and 3 V Operation
Figure 9. Typical Output Supply Current per Channel vs. Data Rate
for 5 V and 3 V Operation (No Output Load)
35
30
25
20
15
10
8
6
4
5V
5V
10
3V
3V
2
5
0
0
0
20
40
60
80
100
0
20
40
60
80
100
DATA RATE (Mbps)
DATA RATE (Mbps)
Figure 13. Typical ADuM1401 VDD1 Supply Current vs. Data Rate
for 5 V and 3 V Operation
Figure 10. Typical Output Supply Current per Channel vs. Data Rate
for 5 V and 3 V Operation (15 pF Output Load)
Rev. L | Page 25 of 31
ADuM1400/ADuM1401/ADuM1402
Data Sheet
40
35
30
25
20
40
35
30
25
3V
5V
15
10
3V
5V
5
0
0
20
40
60
80
100
–50
–25
0
25
50
75
100
DATA RATE (Mbps)
TEMPERATURE (°C)
Figure 14. Typical ADuM1401 VDD2 Supply Current vs. Data Rate
for 5 V and 3 V Operation
Figure 16. Propagation Delay vs. Temperature, C Grade
50
45
40
35
30
25
20
5V
15
3V
10
5
0
0
20
40
60
80
100
DATA RATE (Mbps)
Figure 15. Typical ADuM1402 VDD1 or VDD2 Supply Current vs. Data Rate
for 5 V and 3 V Operation
Rev. L | Page 26 of 31
Data Sheet
ADuM1400/ADuM1401/ADuM1402
APPLICATIONS INFORMATION
PC BOARD LAYOUT
DC CORRECTNESS AND MAGNETIC FIELD
IMMUNITY
The ADuM1400/ADuM1401/ADuM1402 digital isolators
require no external interface circuitry for the logic interfaces.
Power supply bypassing is strongly recommended at the input
and output supply pins (see Figure 17). Bypass capacitors are
most conveniently connected between Pin 1 and Pin 2 for VDD1
and between Pin 15 and Pin 16 for VDD2. The capacitor value
should be between 0.01 µF and 0.1 µF. The total lead length
between both ends of the capacitor and the input power supply
pin should not exceed 20 mm. Bypassing between Pin 1 and Pin
8 and between Pin 9 and Pin 16 should also be considered,
unless the ground pair on each package side is connected close
to the package.
Positive and negative logic transitions at the isolator input
cause narrow (~1 ns) pulses to be sent to the decoder via the
transformer. The decoder is bistable and is, therefore, either set
or reset by the pulses, indicating input logic transitions. In the
absence of logic transitions at the input for more than ~1 µs, a
periodic set of refresh pulses indicative of the correct input state
are sent to ensure dc correctness at the output. If the decoder
receives no internal pulses of more than about 5 µs, the input
side is assumed to be unpowered or nonfunctional, in which
case the isolator output is forced to a default state (see Table 15)
by the watchdog timer circuit.
V
GND
V
V
DD2
DD1
The limitation on the magnetic field immunity of the ADuM1400/
ADuM1401/ADuM1402 is set by the condition in which induced
voltage in the receiving coil of the transformer is sufficiently large
enough to either falsely set or reset the decoder. The following
analysis defines the conditions under which this may occur. The
3 V operating condition of the ADuM1400/ADuM1401/
ADuM1402 is examined because it represents the most susceptible
mode of operation.
GND
1
2
V
IA
IB
OA
V
V
OB
V
V
/V
V
V
V
V
IC OC
OC/ IC
V
V
ID/ OD
OD/ ID
NC/V
E1
E2
GND
GND
2
1
Figure 17. Recommended Printed Circuit Board Layout
In applications involving high common-mode transients, care
should be taken to ensure that board coupling across the isolation
barrier is minimized. Furthermore, the board layout should be
designed such that any coupling that does occur equally affects
all pins on a given component side. Failure to ensure this could
cause voltage differentials between pins exceeding the Absolute
Maximum Ratings of the device, thereby leading to latch-up or
permanent damage.
The pulses at the transformer output have an amplitude greater
than 1.0 V. The decoder has a sensing threshold at about 0.5 V, thus
establishing a 0.5 V margin in which induced voltages can be
tolerated. The voltage induced across the receiving coil is given by
2
V = (−dβ/dt)∑∏rn ; n = 1, 2, … , N
where:
β is magnetic flux density (gauss).
N is the number of turns in the receiving coil.
rn is the radius of the nth turn in the receiving coil (cm).
See the AN-1109 Application Note for board layout guidelines.
PROPAGATION DELAY-RELATED PARAMETERS
Propagation delay is a parameter that describes the time it takes
a logic signal to propagate through a component. The propagation
delay to a Logic 0 output may differ from the propagation delay
to a Logic 1 output.
Given the geometry of the receiving coil in the ADuM1400/
ADuM1401/ADuM1402 and an imposed requirement that the
induced voltage be 50% at most of the 0.5 V margin at the
decoder, a maximum allowable magnetic field is calculated as
shown in Figure 19.
INPUT (V
)
50%
Ix
100
tPLH
tPHL
OUTPUT (V
)
50%
Ox
10
1
Figure 18. Propagation Delay Parameters
Pulse width distortion is the maximum difference between
these two propagation delay values and is an indication of how
accurately the timing of the input signal is preserved.
0.1
Channel-to-channel matching refers to the maximum amount
the propagation delay differs between channels within a single
ADuM1400/ADuM1401/ADuM1402 component.
0.01
0.001
Propagation delay skew refers to the maximum amount the
propagation delay differs between multiple ADuM1400/
ADuM1401/ADuM1402 components operating under the same
conditions.
1k
10k
100k
1M
10M
100M
MAGNETIC FIELD FREQUENCY (Hz)
Figure 19. Maximum Allowable External Magnetic Flux Density
Rev. L | Page 27 of 31
ADuM1400/ADuM1401/ADuM1402
Data Sheet
For example, at a magnetic field frequency of 1 MHz, the
maximum allowable magnetic field of 0.2 kgauss induces a
voltage of 0.25 V at the receiving coil. This is about 50% of the
sensing threshold and does not cause a faulty output transition.
Similarly, if such an event occurs during a transmitted pulse
(and has the worst-case polarity), it reduces the received pulse
from >1.0 V to 0.75 V—still well above the 0.5 V sensing
threshold of the decoder.
POWER CONSUMPTION
The supply current at a given channel of the ADuM1400/
ADuM1401/ADuM1402 isolator is a function of the supply
voltage, the data rate of the channel, and the output load of the
channel.
For each input channel, the supply current is given by
IDDI = IDDI (Q)
f ≤ 0.5 fr
f > 0.5 fr
The preceding magnetic flux density values correspond to
specific current magnitudes at given distances from the
ADuM1400/ADuM1401/ADuM1402 transformers. Figure 20
expresses these allowable current magnitudes as a function of
frequency for selected distances. As shown, the ADuM1400/
ADuM1401/ADuM1402 are extremely immune and can be
affected only by extremely large currents operated at high
frequency very close to the component. For the 1 MHz example
noted, one would have to place a 0.5 kA current 5 mm away
from the ADuM1400/ADuM1401/ADuM1402 to affect the
operation of the component.
IDDI = IDDI (D) × (2f − fr) + IDDI (Q)
For each output channel, the supply current is given by
DDO = IDDO (Q) f ≤ 0.5 fr
DDO = (IDDO (D) + (0.5 × 10−3) × CL × VDDO) × (2f − fr) + IDDO (Q)
f > 0.5 fr
I
I
where:
DDI (D), IDDO (D) are the input and output dynamic supply currents
I
per channel (mA/Mbps).
CL is the output load capacitance (pF).
VDDO is the output supply voltage (V).
1000
f is the input logic signal frequency (MHz); it is half of the input
data rate expressed in units of Mbps.
fr is the input stage refresh rate (Mbps).
DISTANCE = 1m
100
I
DDI (Q), IDDO (Q) are the specified input and output quiescent
supply currents (mA).
10
DISTANCE = 100mm
To calculate the total VDD1 and VDD2 supply current, the supply
currents for each input and output channel corresponding to
1
V
DD1 and VDD2 are calculated and totaled. Figure 8 and Figure 9
DISTANCE = 5mm
provide per-channel supply currents as a function of data rate
for an unloaded output condition. Figure 10 provides per-
channel supply current as a function of data rate for a 15 pF
output condition. Figure 11 through Figure 15 provide total
0.1
0.01
1k
10k
100k
1M
10M
100M
V
DD1 and VDD2 supply current as a function of data rate for
MAGNETIC FIELD FREQUENCY (Hz)
ADuM1400/ADuM1401/ADuM1402 channel configurations.
Figure 20. Maximum Allowable Current for Various
Current-to-ADuM1400/ADuM1401/ADuM1402 Spacings
Note that at combinations of strong magnetic field and high
frequency, any loops formed by printed circuit board traces
could induce error voltages sufficiently large enough to trigger
the thresholds of succeeding circuitry. Care should be taken in
the layout of such traces to avoid this possibility.
Rev. L | Page 28 of 31
Data Sheet
ADuM1400/ADuM1401/ADuM1402
In the case of unipolar ac or dc voltage, the stress on the insulation
is significantly lower, which allows operation at higher working
voltages while still achieving a 50-year service life. The working
voltages listed in Table 14 can be applied while maintaining the
50-year minimum lifetime, provided the voltage conforms to either
the unipolar ac or dc voltage cases. Any cross-insulation voltage
waveform that does not conform to Figure 22 or Figure 23 should
be treated as a bipolar ac waveform, and its peak voltage should
be limited to the 50-year lifetime voltage value listed in Table 14.
INSULATION LIFETIME
All insulation structures eventually break down when subjected
to voltage stress over a sufficiently long period. The rate of
insulation degradation is dependent on the characteristics of
the voltage waveform applied across the insulation. In addition
to the testing performed by the regulatory agencies, Analog
Devices carries out an extensive set of evaluations to determine
the lifetime of the insulation structure within the ADuM1400/
ADuM1401/ADuM1402.
Note that the voltage presented in Figure 22 is shown as sinusoidal
for illustration purposes only. It is meant to represent any voltage
waveform varying between 0 V and some limiting value. The
limiting value can be positive or negative, but the voltage cannot
cross 0 V.
Analog Devices performs accelerated life testing using voltage
levels higher than the rated continuous working voltage. Accel-
eration factors for several operating conditions are determined.
These factors allow calculation of the time to failure at the actual
working voltage. The values shown in Table 14 summarize the
peak voltage for 50 years of service life for a bipolar ac operating
condition and the maximum CSA/VDE approved working
voltages. In many cases, the approved working voltage is higher
than a 50-year service life voltage. Operation at these high working
voltages can lead to shortened insulation life in some cases.
RATED PEAK VOLTAGE
0V
Figure 21. Bipolar AC Waveform
RATED PEAK VOLTAGE
The insulation lifetime of the ADuM1400/ADuM1401/
ADuM1402 depends on the voltage waveform type imposed
across the isolation barrier. The iCoupler insulation structure
degrades at different rates depending on whether the waveform
is bipolar ac, unipolar ac, or dc. Figure 21, Figure 22, and Figure 23
illustrate these different isolation voltage waveforms, respectively.
0V
Figure 22. Unipolar AC Waveform
RATED PEAK VOLTAGE
0V
Bipolar ac voltage is the most stringent environment. The goal
of a 50-year operating lifetime under the ac bipolar condition
determines the Analog Devices recommended maximum
working voltage.
Figure 23. DC Waveform
Rev. L | Page 29 of 31
ADuM1400/ADuM1401/ADuM1402
OUTLINE DIMENSIONS
Data Sheet
10.50 (0.4134)
10.10 (0.3976)
16
9
8
7.60 (0.2992)
7.40 (0.2913)
1
10.65 (0.4193)
10.00 (0.3937)
0.75 (0.0295)
0.25 (0.0098)
1.27 (0.0500)
BSC
45°
2.65 (0.1043)
2.35 (0.0925)
0.30 (0.0118)
0.10 (0.0039)
8°
0°
COPLANARITY
0.10
SEATING
PLANE
0.51 (0.0201)
0.31 (0.0122)
1.27 (0.0500)
0.40 (0.0157)
0.33 (0.0130)
0.20 (0.0079)
COMPLIANT TO JEDEC STANDARDS MS-013-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 24. 16-Lead Standard Small Outline Package [SOIC_W]
Wide Body (RW-16)
Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Number
Number
Maximum Maximum
Maximum
of Inputs, of Inputs, Data Rate Propagation
Pulse Width
Temperature
Delay, 5 V (ns) Distortion (ns) Range
Package
Description
Package
Option
Model1, 2, 3, 4
VDD1 Side VDD2 Side
(Mbps)
1
ADuM1400ARW
ADuM1400BRW
ADuM1400CRW
ADuM1400ARWZ
ADuM1400BRWZ
ADuM1400CRWZ
ADuM1400WSRWZ
ADuM1400WTRWZ
ADuM1401ARW
ADuM1401BRW
ADuM1401CRW
ADuM1401ARWZ
ADuM1401BRWZ
ADuM1401CRWZ
ADuM1401WSRWZ
ADuM1401WTRWZ
ADuM1402ARW
ADuM1402BRW
ADuM1402CRW
ADuM1402ARWZ
ADuM1402BRWZ
ADuM1402CRWZ
ADuM1402WSRWZ
ADuM1402WTRWZ
EVAL-ADuMQSEBZ
4
4
4
4
4
4
4
4
3
3
3
3
3
3
3
3
2
2
2
2
2
2
2
2
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
100
50
32
100
50
32
40
3
2
40
3
2
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +125°C
−40°C to +125°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +125°C
−40°C to +125°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +125°C
−40°C to +125°C
16-Lead SOIC_W RW-16
16-Lead SOIC_W RW-16
16-Lead SOIC_W RW-16
16-Lead SOIC_W RW-16
16-Lead SOIC_W RW-16
16-Lead SOIC_W RW-16
16-Lead SOIC_W RW-16
16-Lead SOIC_W RW-16
16-Lead SOIC_W RW-16
16-Lead SOIC_W RW-16
16-Lead SOIC_W RW-16
16-Lead SOIC_W RW-16
16-Lead SOIC_W RW-16
16-Lead SOIC_W RW-16
16-Lead SOIC_W RW-16
16-Lead SOIC_W RW-16
16-Lead SOIC_W RW-16
16-Lead SOIC_W RW-16
16-Lead SOIC_W RW-16
16-Lead SOIC_W RW-16
16-Lead SOIC_W RW-16
16-Lead SOIC_W RW-16
16-Lead SOIC_W RW-16
16-Lead SOIC_W RW-16
Evaluation Board
10
90
1
10
90
1
10
1
10
90
1
10
90
1
10
1
10
90
1
10
90
1
100
34
40
3
100
50
32
100
50
32
40
3
2
40
3
2
100
34
40
3
100
50
32
100
50
32
40
3
2
40
3
2
100
34
40
3
10
1 Z = RoHS Compliant Part.
2 W = Qualified for Automotive Applications.
3 Tape and reel are available. The addition of an -RL suffix designates a 13” (1,000 units) tape and reel option.
4 No tape and reel option is available for the ADuM1400CRW or ADuM1402BRW models.
Rev. L | Page 30 of 31
Data Sheet
ADuM1400/ADuM1401/ADuM1402
AUTOMOTIVE PRODUCTS
The ADuM1400W/ADuM1401W/ADuM1402W models are available with controlled manufacturing to support the quality and reliability
requirements of automotive applications. Note that these automotive models may have specifications that differ from the commercial
models; therefore, designers should review the Specifications section of this data sheet carefully. Only the automotive grade products
shown are available for use in automotive applications. Contact your local Analog Devices account representative for specific product
ordering information and to obtain the specific Automotive Reliability reports for these models.
©2003–2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D03786-0-12/16(L)
Rev. L | Page 31 of 31
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