ADUM140E1BRWZ_技术文档

3.75 kV rms Quad Digital Isolators

ADuM140D/ADuM140E

Data Sheet

FEATURES

FUNCTIONAL BLOCK DIAGRAMS

High common-mode transient immunity: 100 kV/μs

High robustness to radiated and conducted noise

Low propagation delay: 13 ns maximum for 5 V operation

150 Mbps minimum data rate

3.75 kV rms withstand voltage rating

Safety and regulatory approvals (pending)

UL recognition (pending)

3750 V rms for 1 minute per UL 1577

CSA component acceptance notice 5A

VDE certificate of conformity

ADuM140D

1

2

3

16

15

14

V

DD2

DD1

GND

2

1

IA

IB

ENCODE

DECODE

V

OA

OB

OC

4

5

13

12

V

IC

ID

V

11 OD

6

7

8

NIC

10

9

DISABLE

1

GND

1

2

NIC = NO INTERNAL CONNECTION. LEAVE THIS PIN FLOATING.

Figure 1. ADuM140D Functional Block Diagram

DIN V VDE V 0884-10 (VDE V 0884-10):2006-12

V

_IORM= 848 V peak

ADuM140E

1

2

3

16

15

14

V

DD2

DD1

CQC11-471543-2012

Backward compatibility

GND

V

GND

1

2

V

ENCODE

DECODE

IA

IB

IC

ID

OA

ADuM140E1 pin compatible with ADuM1400

Low dynamic power consumption

1.8 V to 5 V level translation

High temperature operation: 125°C

Failsafe high or low options

V

4

5

13

12

OB

V

OC

V

6

7

8

11

10

9

OD

V

NIC

GND

E2

GND

16-lead, RoHS-compliant, SOIC package

1

2

NIC = NO INTERNAL CONNECTION. LEAVE THIS PIN FLOATING.

APPLICATIONS

Figure 2. ADuM140E Functional Block Diagram

General-purpose multichannel isolation

SPI interface/data converter isolation

Industrial field bus isolation

GENERAL DESCRIPTION

The ADuM140D/ADuM140E¹are quad-channel digital isolators

based on Analog Devices, Inc., iCoupler® technology. Combining

high speed, complementary metal-oxide semiconductor (CMOS)

and monolithic air core transformer technology, these isolation

components provide outstanding performance characteristics

superior to alternatives such as optocoupler devices and other

integrated couplers. The maximum propagation delay is 13 ns

with a pulse width distortion of less than 3 ns at 5 V operation.

Channel matching is tight at 3.0 ns maximum.

voltage rating of 3.75 kV rms (see the Ordering Guide). The

devices operate with the supply voltage on either side ranging

from 1.8 V to 5 V, providing compatibility with lower voltage

systems as well as enabling voltage translation functionality

across the isolation barrier.

Unlike other optocoupler alternatives, dc correctness is ensured

in the absence of input logic transitions. Two different fail-safe

options are available, in which the outputs transition to a

predetermined state when the input power supply is not applied

or the inputs are disabled. The ADuM140E1 is pin compatible

with the ADuM1400.

The ADuM140D/ADuM140E data channels are independent

and are available in a variety of configurations with a withstand

¹Protected by U.S. Patents 5,952,849; 6,873,065; 6,903,578; and 7,075,329. Other patents are pending.

Rev. 0 Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Technical Support

www.analog.com

ADuM140D/ADuM140E

Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Recommended Operating Conditions .................................... 10

Absolute Maximum Ratings ......................................................... 11

ESD Caution................................................................................ 11

Pin Configurations and Function Descriptions......................... 13

Typical Performance Characteristics ........................................... 14

Applications Information .............................................................. 15

Overview ..................................................................................... 15

PCB Layout ................................................................................. 15

Propagation Delay Related Parameters ................................... 16

Jitter Measurement..................................................................... 16

Insulation Lifetime..................................................................... 16

Outline Dimensions....................................................................... 18

Ordering Guide .......................................................................... 18

Applications....................................................................................... 1

Functional Block Diagrams............................................................. 1

General Description......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Electrical Characteristics—5 V Operation................................ 3

Electrical Characteristics—3.3 V Operation ............................ 4

Electrical Characteristics—2.5 V Operation ............................ 5

Electrical Characteristics—1.8 V Operation ............................ 7

Insulation and Safety Related Specifications ............................ 8

Package Characteristics ............................................................... 8

Regulatory Information............................................................... 9

DIN V VDE V 0884-10 (VDE V 0884-10) Insulation

Characteristics ............................................................................ 10

REVISION HISTORY

4/15—Revision 0: Initial Version

Rev. 0 | Page 2 of 18

Data Sheet

ADuM140D/ADuM140E

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS—5 V OPERATION

All typical specifications are at T_A= 25°C, V_DD1= V_DD2= 5 V. Minimum/maximum specifications apply over the entire recommended

operation range of 4.5 V ≤ V_DD1≤ 5.5 V, 4.5 V ≤ V_DD2≤ 5.5 V, and −40°C ≤ T_A≤ +125°C, unless otherwise noted. Switching specifications

are tested with C_L= 15 pF and CMOS signal levels, unless otherwise noted. Supply currents are specified with 50% duty cycle signals.

Table 1.

Parameter

Symbol Min

Typ

Max

Unit

Test Conditions/Comments

SWITCHING SPECIFICATIONS

Pulse Width

Data Rate

Propagation Delay

Pulse Width Distortion

Change vs. Temperature

Propagation Delay Skew

PW

6.6

150

ns

Mbps

ns

ps/°C

ns

Within pulse width distortion (PWD) limit

Within PWD limit

50% input to 50% output

t_PHL, t_PLH4.8

PWD

7.2

0.5

1.5

13

3

|t_PLH− t_PHL|

t_PSK

6.1

Between any two units at the

same temperature, voltage, and load

Channel Matching

Codirectional

Opposing Direction

Jitter

t_PSKCD

t_PSKOD

0.5

490

3.0

ns

ps p-p

See the Jitter Measurement section

DC SPECIFICATIONS

Input Threshold

Logic High

V_IH

V_IL

0.7 × V_DDx

V

Logic Low

0.3 × V_DDx

Output Voltage

Logic High

2

V_OH

V_OL

V_DDx− 0.1 V_DDx

V_DDx− 0.4 V_DDx− 0.2

V

I_Ox¹= −20 µA, V_Ix= V_IxH

2

I_Ox¹= −4 mA, V_Ix= V_IxH

3

Logic Low

0.0

0.2

0.1

0.4

I_Ox¹= 20 µA, V_Ix= V_IxL

3

I_Ox¹= 4 mA, V_Ix= V_IxL

Input Current per Channel

V_E2Enable Input Pull-Up Current

DISABLE₁Input Pull-Down Current

Tristate Output Current per Channel

Supply Current per Channel

Quiescent Input

Quiescent Output

Quiescent Input

Quiescent Output

Dynamic Input

I_I

−10

+0.01

−3

9

+10

µA

0 V ≤ V_Ix≤ V_DDx

V_E2= 0 V

DISABLE₁= V_DDx

0 V ≤ V_Ox≤ V_DDx

I_PU

I_PD

I_OZ

15

+10

−10

+0.01

I_{DDI (Q)}

0.3

0.5

3.0

0.5

0.01

0.02

0.55

0.68

5.0

mA

V_I⁴= 0 (E0, D0), 1 (E1, D1)⁵

V_I⁴= 1 (E0, D0), 0 (E1, D1)⁵

I_{DDO (Q)}

I_{DDI (Q)}

I_{DDO (Q)}

I_{DDI (D)}

I_{DDO (D)}

UVLO

V_DDxUV+

V_DDxUV−

V_DDxUVH

0.73

mA/Mbps Inputs switching, 50% duty cycle

Dynamic Output

Undervoltage Lockout

Positive V_DDxThreshold

Negative V_DDxThreshold

V_DDxHysteresis

1.6

1.5

0.1

V

Rev. 0 | Page 3 of 18

ADuM140D/ADuM140E

Data Sheet

Parameter

Symbol Min

Typ

Max

Unit

Test Conditions/Comments

AC SPECIFICATIONS

Output Rise/Fall Time

t_R/t_F

2.5

100

ns

kV/µs

10% to 90%

V_Ix= V_DDx, V_CM= 1000 V,

transient magnitude = 800 V

V_Ix= 0 V, V_CM= 1000 V,

Common-Mode Transient Immunity⁶|CM_H|

75

|CM_L|

100

kV/µs

transient magnitude = 800 V

¹I_Oxis the Channel x output current, where x = A, B, C, or D.

²V_IxHis the input side logic high.

³V_IxLis the input side logic low.

⁴V_Iis the voltage input.

⁵E0 is the ADuM140E0 model, D0 is the ADuM140D0 model, E1 is the ADuM140E1 model, and D1 is the ADuM140D1 model. See the Ordering Guide section.

⁶|CM_H| is the maximum common-mode voltage slew rate that can be sustained while maintaining the voltage output (V_O) > 0.8 V_DDx. |CM_L| is the maximum common-

mode voltage slew rate that can be sustained while maintaining V_O> 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode

voltage edges.

Table 2. Total Supply Current vs. Data Throughput

1 Mbps

Typ

25 Mbps

Typ

100 Mbps

Typ

Parameter

Symbol

Min

Max

Min

Max

Min

Max

Unit

SUPPLY CURRENT

Supply Current Side 1

Supply Current Side 2

I_DD1

I_DD2

6.8

2.1

10

3.7

7.8

3.9

12

5.7

11.8

9.2

17.4

13

mA

ELECTRICAL CHARACTERISTICS—3.3 V OPERATION

All typical specifications are at T_A= 25°C, V_DD1= V_DD2= 3.3 V. Minimum/maximum specifications apply over the entire recommended

operation range: 3.0 V ≤ V_DD1≤ 3.6 V, 3.0 V ≤ V_DD2≤ 3.6 V, and −40°C ≤ T_A≤ +125°C, unless otherwise noted. Switching specifications

are tested with C_L= 15 pF and CMOS signal levels, unless otherwise noted. Supply currents are specified with 50% duty cycle signals.

Table 3.

Parameter

Symbol Min

Typ

Max

Unit

Test Conditions/Comments

SWITCHING SPECIFICATIONS

Pulse Width

Data Rate

Propagation Delay

Pulse Width Distortion

Change vs. Temperature

Propagation Delay Skew

PW

6.6

150

4.8

ns

Mbps

ns

ps/°C

ns

Within PWD limit

50% input to 50% output

|t_PLH− t_PHL|

t_PHL, t_PLH

PWD

6.8

0.7

1.5

14

3

t_PSK

7.5

Between any two units at the same

temperature, voltage, and load

Channel Matching

Codirectional

Opposing Direction

Jitter

t_PSKCD

t_PSKOD

0.7

580

3.0

ns

ps p-p

See the Jitter Measurement section

DC SPECIFICATIONS

Input Threshold

Logic High

V_IH

V_IL

0.7 × V_DDx

V

Logic Low

0.3 × V_DDx

Output Voltage

Logic High

2

V_OH

V_OL

V_DDx− 0.1 V_DDx

V_DDx− 0.4 V_DDx− 0.2

V

I_Ox¹= −20 µA, V_Ix= V_IxH

2

I_Ox¹= −2 mA, V_Ix= V_IxH

3

Logic Low

0.0

0.2

0.1

0.4

I_Ox¹= 20 µA, V_Ix= V_IxL

3

I_Ox¹= 2 mA, V_Ix= V_IxL

Input Current per Channel

I_I

−10

+0.01

−3

9

+10

µA

0 V ≤ V_Ix≤ V_DDx

V_E2= 0 V

DISABLE₁= V_DDx

0 V ≤ V_Ox≤ V_DDx

V_E2Enable Input Pull-Up Current

DISABLE₁Input Pull-Down Current

Tristate Output Current per Channel

I_PU

I_PD

I_OZ

15

+10

−10

+0.01

Rev. 0 | Page 4 of 18

Data Sheet

ADuM140D/ADuM140E

Parameter

Symbol Min

Typ

Max

Unit

Test Conditions/Comments

Supply Current per Channel

Quiescent Input

Quiescent Output

Quiescent Input

Quiescent Output

Dynamic Input

Dynamic Output

Undervoltage Lockout

Positive V_DDxThreshold

Negative V_DDxThreshold

V_DDxHysteresis

I_{DDI (Q)}

0.3

0.5

3.0

0.5

0.01

0.53

0.67

4.9

mA

V_I⁴= 0 (E0, D0), 1 (E1, D1)⁵

V_I⁴= 1 (E0, D0), 0 (E1, D1)⁵

I_{DDO (Q)}

I_{DDI (Q)}

I_{DDO (Q)}

I_{DDI (D)}

I_{DDO (D)}

UVLO

V_DDxUV+

V_DDxUV−

V_DDxUVH

0.7

mA/Mbps Inputs switching, 50% duty cycle

1.6

1.5

0.1

V

AC SPECIFICATIONS

Output Rise/Fall Time

t_R/t_F

2.5

100

ns

kV/µs

10% to 90%

V_Ix= V_DDx, V_CM= 1000 V,

transient magnitude = 800 V

V_Ix= 0 V, V_CM= 1000 V,

Common-Mode Transient Immunity⁶|CM_H|

75

|CM_L|

100

kV/µs

transient magnitude = 800 V

¹I_Oxis the Channel x output current, where x = A, B, C, or D.

²V_IxHis the input side logic high.

³V_IxLis the input side logic low.

⁴V_Iis the voltage input.

⁵E0 is the ADuM140E0 model, D0 is the ADuM140D0 model, E1 is the ADuM140E1 model, and D1 is the ADuM140D1 model. See the Ordering Guide section.

⁶|CM_H| is the maximum common-mode voltage slew rate that can be sustained while maintaining the voltage output (V_O) > 0.8 V_DDx. |CM_L| is the maximum common-

mode voltage slew rate that can be sustained while maintaining V_O> 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode

voltage edges.

Table 4. Total Supply Current vs. Data Throughput

1 Mbps

Typ

25 Mbps

Typ

100 Mbps

Typ

Parameter

Symbol

Min

Max

Min

Max

Min

Max

Unit

SUPPLY CURRENT

Supply Current Side 1

Supply Current Side 2

I_DD1

I_DD2

6.6

2.0

9.8

3.7

7.4

3.5

11.2

5.5

10.7

8.2

15.9

11.6

mA

ELECTRICAL CHARACTERISTICS—2.5 V OPERATION

All typical specifications are at T_A= 25°C, V_DD1= V_DD2= 2.5 V. Minimum/maximum specifications apply over the entire recommended

operation range: 2.25 V ≤ V_DD1≤ 2.75 V, 2.25 V ≤ V_DD2≤ 2.75 V, −40°C ≤ T_A≤ +125°C, unless otherwise noted. Switching specifications

are tested with C_L= 15 pF and CMOS signal levels, unless otherwise noted. Supply currents are specified with 50% duty cycle signals.

Table 5.

Parameter

Symbol Min

Typ

Max

Unit

Test Conditions/Comments

SWITCHING SPECIFICATIONS

Pulse Width

Data Rate

Propagation Delay

Pulse Width Distortion

Change vs. Temperature

Propagation Delay Skew

PW

6.6

150

5.0

ns

Mbps

ns

ps/°C

ns

Within PWD limit

50% input to 50% output

|t_PLH− t_PHL|

t_PHL, t_PLH

PWD

7.0

0.7

1.5

14

3

t_PSK

6.8

Between any two units at the

same temperature, voltage, load

Channel Matching

Codirectional

Opposing Direction

Jitter

t_PSKCD

t_PSKOD

0.7

800

3.0

ns

ps p-p

See the Jitter Measurement section

Rev. 0 | Page 5 of 18

ADuM140D/ADuM140E

Data Sheet

Parameter

Symbol Min

Typ

Max

Unit

Test Conditions/Comments

DC SPECIFICATIONS

Input Threshold

Logic High

V_IH

V_IL

0.7 × V_DDx

V

Logic Low

0.3 × V_DDx

Output Voltage

Logic High

2

V_OH

V_OL

V_DDx− 0.1

V_DDx− 0.4 V_DDx− 0.2

V_DDx

V

I_Ox¹= −20 µA, V_Ix= V_IxH

2

I_Ox¹= −2 mA, V_Ix= V_IxH

3

Logic Low

0.0

0.2

0.1

0.4

I_Ox¹= 20 µA, V_Ix= V_IxL

3

I_Ox¹= 2 mA, V_Ix= V_IxL

Input Current per Channel

V_E2Enable Input Pull-Up Current

DISABLE₁Input Pull-Down Current

Tristate Output Current per Channel

Supply Current per Channel

Quiescent Input

Quiescent Output

Quiescent Input

Quiescent Output

Dynamic Input

I_I

−10

+0.01

−3

9

+10

µA

0 V ≤ V_Ix≤ V_DDx

V_E2= 0 V

DISABLE₁= V_DDx

0 V ≤ V_Ox≤ V_DDx

I_PU

I_PD

I_OZ

15

+10

−10

+0.01

I_{DDI (Q)}

I_{DDO (Q)}

I_{DDI (Q)}

I_{DDO (Q)}

I_{DDI (D)}

I_{DDO (D)}

0.3

0.5

3.0

0.5

0.01

0.5

0.66

4.9

mA

V_I⁴= 0 (E0, D0), 1 (E1, D1)⁵

V_I⁴= 1 (E0, D0), 0 (E1, D1)⁵

0.69

mA/Mbps Inputs switching, 50% duty cycle

Dynamic Output

Undervoltage Lockout

Positive V_DDxThreshold

Negative V_DDxThreshold

V_DDxHysteresis

V_DDxUV+

V_DDxUV−

V_DDxUVH

1.6

1.5

0.1

V

AC SPECIFICATIONS

Output Rise/Fall Time

Common-Mode Transient Immunity⁶

t_R/t_F

|CM_H|

2.5

100

ns

kV/µs

10% to 90%

V_Ix= V_DDx, V_CM= 1000 V,

transient magnitude = 800 V

V_Ix= 0 V, V_CM= 1000 V,

75

|CM_L|

100

kV/µs

transient magnitude = 800 V

¹I_Oxis the Channel x output current, where x = A, B, C, or D.

²V_IxHis the input side logic high.

³V_IxLis the input side logic low.

⁴V_Iis the voltage input.

⁵E0 is the ADuM140E0 model, D0 is the ADuM140D0 model, E1 is the ADuM140E1 model, and D1 is the ADuM140D1 model. See the Ordering Guide section.

⁶|CM_H| is the maximum common-mode voltage slew rate that can be sustained while maintaining the voltage output (V_O) > 0.8 V_DDx. |CM_L| is the maximum common-

mode voltage slew rate that can be sustained while maintaining V_O> 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode

voltage edges.

Table 6. Total Supply Current vs. Data Throughput

1 Mbps

Typ

25 Mbps

Typ

100 Mbps

Typ

Parameter

Symbol

Min

Max

Min

Max

Min

Max

Unit

SUPPLY CURRENT

Supply Current Side 1

Supply Current Side 2

I_DD1

I_DD2

6.5

2.0

9.8

3.6

7.3

3.3

11.1

5.2

10.4

7.3

15.5

10.2

mA

Rev. 0 | Page 6 of 18

Data Sheet

ADuM140D/ADuM140E

ELECTRICAL CHARACTERISTICS—1.8 V OPERATION

All typical specifications are at T_A= 25°C, V_DD1= V_DD2= 1.8 V. Minimum/maximum specifications apply over the entire recommended

operation range: 1.7 V ≤ V_DD1≤ 1.9 V, 1.7 V ≤ V_DD2≤ 1.9 V, and −40°C ≤ T_A≤ +125°C, unless otherwise noted. Switching specifications

are tested with C_L= 15 pF and CMOS signal levels, unless otherwise noted. Supply currents are specified with 50% duty cycle signals.

Table 7.

Parameter

Symbol Min

Typ

Max

Unit

Test Conditions/Comments

SWITCHING SPECIFICATIONS

Pulse Width

Data Rate

Propagation Delay

Pulse Width Distortion

Change vs. Temperature

Propagation Delay Skew

PW

6.6

150

5.8

ns

Mbps

ns

ps/°C

ns

Within PWD limit

50% input to 50% output

|t_PLH− t_PHL|

t_PHL, t_PLH

PWD

8.7

0.7

1.5

15

3

t_PSK

7.0

Between any two units at the same

temperature, voltage, and load

Channel Matching

Codirectional

Opposing Direction

Jitter

t_PSKCD

t_PSKOD

0.7

470

3.0

ns

ps p-p

See the Jitter Measurement section

DC SPECIFICATIONS

Input Threshold

Logic High

Logic Low

Output Voltage

Logic High

V_IH

V_IL

0.7 × V_DDx

V_DDx− 0.1

V

0.3 × V_DDx

2

V_OH

V_OL

V_DDx

V

I_Ox¹= −20 µA, V_Ix= V_IxH

2

V_DDx− 0.4 V_DDx− 0.2

I_Ox¹= −2 mA, V_Ix= V_IxH

3

Logic Low

0.0

0.2

0.1

0.4

I_Ox¹= 20 µA, V_Ix= V_IxL

3

I_Ox¹= 2 mA, V_Ix= V_IxL

Input Current per Channel

V_E2Enable Input Pull-Up Current

DISABLE₁Input Pull-Down Current

Tristate Output Current per Channel

Supply Current per Channel

Quiescent Input

Quiescent Output

Quiescent Input

Quiescent Output

Dynamic Input

I_I

−10

+0.01

−3

9

+10

µA

0 V ≤ V_Ix≤ V_DDx

V_E2= 0 V

DISABLE₁= V_DDx

0 V ≤ V_Ox≤ V_DDx

I_PU

I_PD

I_OZ

15

+10

−10

+0.01

I_{DDI (Q)}

0.3

0.5

3.0

0.5

0.01

0.48

0.66

4.9

mA

V_I⁴= 0 (E0, D0), 1 (E1, D1)⁵

V_I⁴= 1 (E0, D0), 0 (E1, D1)⁵

I_{DDO (Q)}

I_{DDI (Q)}

I_{DDO (Q)}

I_{DDI (D)}

I_{DDO (D)}

UVLO

V_DDxUV+

V_DDxUV−

V_DDxUVH

0.69

mA/Mbps Inputs switching, 50% duty cycle

Dynamic Output

Undervoltage Lockout

Positive V_DDxThreshold

Negative V_DDxThreshold

V_DDxHysteresis

1.6

1.5

0.1

V

AC SPECIFICATIONS

Output Rise/Fall Time

t_R/t_F

2.5

100

ns

kV/µs

10% to 90%

V_Ix= V_DDx, V_CM= 1000 V,

transient magnitude = 800 V

V_Ix= 0 V, V_CM= 1000 V,

Common-Mode Transient Immunity⁶|CM_H|

75

|CM_L|

100

kV/µs

transient magnitude = 800 V

¹I_Oxis the Channel x output current, where x = A, B, C, or D.

²V_IxHis the input side logic high.

³V_IxLis the input side logic low.

⁴V_Iis the voltage input.

⁵E0 is the ADuM140E0 model, D0 is the ADuM140D0 model, E1 is the ADuM140E1 model, and D1 is the ADuM140D1 model. See the Ordering Guide section.

⁶|CM_H| is the maximum common-mode voltage slew rate that can be sustained while maintaining the voltage output (V_O) > 0.8 V_DDx. |CM_L| is the maximum common-

mode voltage slew rate that can be sustained while maintaining V_O> 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode

voltage edges.

Rev. 0 | Page 7 of 18

ADuM140D/ADuM140E

Data Sheet

Table 8. Total Supply Current vs. Data Throughput

1 Mbps

Typ

25 Mbps

Typ

100 Mbps

Typ

Parameter

Symbol

Min

Max

Min

Max

Min

Max

Unit

SUPPLY CURRENT

Supply Current Side 1

Supply Current Side 2

I_DD1

I_DD2

6.4

1.9

9.8

3.5

7.2

3.1

11

5.0

10.2

6.8

15.2

10

mA

INSULATION AND SAFETY RELATED SPECIFICATIONS

For additional information, see www.analog.com/icouplersafety.

Table 9.

Parameter

Symbol Value Unit

Test Conditions/Comments

Rated Dielectric Insulation Voltage

Minimum External Air Gap (Clearance)

3750

7.8

V rms

1-minute duration

L (I01)

L (I02)

L (PCB)

mm min Measured from input terminals to output terminals,

shortest distance through air

mm min Measured from input terminals to output terminals,

shortest distance path along body

mm min Measured from input terminals to output terminals,

shortest distance through air, line of sight, in the PCB

mounting plane

Minimum External Tracking (Creepage)

7.8

8.1

Minimum Clearance in the Plane of the Printed

Circuit Board (PCB Clearance)

Minimum Internal Gap (Internal Clearance)

Tracking Resistance (Comparative Tracking Index)

Material Group

25.5

>400

II

μm min

V

Insulation distance through insulation

DIN IEC 112/VDE 0303 Part 1

Material Group (DIN VDE 0110, 1/89, Table 1)

CTI

PACKAGE CHARACTERISTICS

Table 10.

Parameter

Symbol Min Typ Max Unit Test Conditions/Comments

Resistance (Input to Output)¹

Capacitance (Input to Output)¹

Input Capacitance²

R_I-O

C_I-O

C_I

10¹³

2.2

4.0

45

Ω

pF

f = 1 MHz

IC Junction to Ambient Thermal Resistance

θ_JA

°C/W Thermocouple located at center of package underside

¹The device is considered a 2-terminal device: Pin 1 through Pin 8 are shorted together, and Pin 9 through Pin 16 are shorted together.

²Input capacitance is from any input data pin to ground.

Rev. 0 | Page 8 of 18

Data Sheet

ADuM140D/ADuM140E

REGULATORY INFORMATION

See Table 15 and the Insulation Lifetime section for details regarding recommended maximum working voltages for specific cross-

isolation waveforms and insulation levels.

Table 11.

UL (Pending)

CSA (Pending)

VDE (Pending)

CQC (Pending)

Recognized under 1577

Component Recognition

Program¹

Approved under CSA Component Acceptance

Notice 5A

Certified according to

Certified by

DIN V VDE V 0884-10 (VDE CQC11-471543-2012

V 0884-10):2006-12²

Single Protection, 3750 V rms Basic insulation per CSA 60950-1-07+A1+A2 and

Reinforced insulation,

849 V peak

Basic insulation per

GB4943.1-2011

Isolation Voltage

IEC 60950-1, Second Edition +A1+A2, 800 V rms

(1131 V peak)

Reinforced insulation per CSA 60950-1-07+A1+A2

and IEC 60950-1 Second Edition +A1+A2, 400 V rms

(565 V peak) maximum working voltage

Reinforced insulation (2MOPP) per IEC 60601-1

Edition 3.1, 250 V rms (353 V peak) maximum

Working voltage

800 V rms (1131 V peak),

tropical climate, altitude

≤5000 meters

Reinforced insulation per CSA 61010-1-12 and

IEC 61010-1 Third Edition (Pollution Degree 2,

Material Group III, Overvoltage Category II, and

Overvoltage Category III): 300 V rms (424 V peak)

maximum working voltage

File E214100

File 205078

File 2471900-4880-0001

File (pending)

¹In accordance with UL 1577, each ADuM140D/ADuM140E is proof tested by applying an insulation test voltage ≥ 4500 V rms for 1 sec.

²In accordance with DIN V VDE V 0884-10, each ADuM140D/ADuM140E is proof tested by applying an insulation test voltage ≥ 1018 V peak for 1 sec (partial discharge

detection limit = 5 pC). The * marking branded on the component designates DIN V VDE V 0884-10 approval.

Rev. 0 | Page 9 of 18

ADuM140D/ADuM140E

Data Sheet

DIN V VDE V 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS

These isolators are suitable for reinforced electrical isolation only within the safety limit data. Protective circuits ensure the maintenance

of the safety data. The * marking on packages denotes DIN V VDE V 0884-10 approval.

Table 12.

Description

Test Conditions/Comments

Symbol

Characteristic Unit

Installation Classification per DIN VDE 0110

For Rated Mains Voltage ≤ 150 V rms

For Rated Mains Voltage ≤ 300 V rms

For Rated Mains Voltage ≤ 400 V rms

Climatic Classification

Pollution Degree per DIN VDE 0110, Table 1

Maximum Working Insulation Voltage

Input to Output Test Voltage, Method B1

I to IV

I to III

40/125/21

2

V_IORM

V_{pd (m)}

848

1592

V peak

V_IORM× 1.875 = V_{pd (m)}, 100% production test,

t

_ini= t_m= 1 sec, partial discharge < 5 pC

Input to Output Test Voltage, Method A

After Environmental Tests Subgroup 1

V_{pd (m)}

V_IORM× 1.5 = V_{pd (m)}, t_ini= 60 sec, t_m= 10 sec,

partial discharge < 5 pC

V_IORM× 1.2 = V_{pd (m)}, t_ini= 60 sec, t_m= 10 sec,

partial discharge < 5 pC

1274

1019

V peak

After Input and/or Safety Test Subgroup 2

and Subgroup 3

Highest Allowable Overvoltage

Surge Isolation Voltage

V_IOTM

V_IOSM

5303

8000

V peak

V peak = 12.8 kV, 1.2 µs rise time, 50 µs,

50% fall time

Safety Limiting Values

Maximum value allowed in the event of a

failure (see Figure 3)

Maximum Junction Temperature

Total Power Dissipation at 25°C

Insulation Resistance at T_S

T_S

P_S

R_S

150

2.78

>10⁹

°C

W

Ω

V_IO= 500 V

3.0

2.5

2.0

1.5

1.0

0.5

0

RECOMMENDED OPERATING CONDITIONS

Table 13.

Parameter

Symbol

T_A

V_DD1, V_DD2

Rating

Operating Temperature

Supply Voltages

Input Signal Rise and Fall Times

−40°C to +125°C

1.7 V to 5.5 V

1.0 ms

0

50

100

150

200

AMBIENT TEMPERATURE (°C)

Figure 3. Thermal Derating Curve, Dependence of Safety Limiting Values

with Ambient Temperature per DIN V VDE V 0884-10

Rev. 0 | Page 10 of 18

Data Sheet

ADuM140D/ADuM140E

ABSOLUTE MAXIMUM RATINGS

T_A= 25°C, unless otherwise noted.

Table 15. Maximum Continuous Working Voltage¹

Parameter

Rating

Constraint

Table 14.

Parameter

AC Voltage

Bipolar Waveform

Basic Insulation

Rating

Storage Temperature (T_ST) Range

Ambient Operating Temperature

(T_A) Range

Supply Voltages (V_DD1, V_DD2

Input Voltages (V_IA, V_IB, V_IC, V_ID, V_E2,

DISABLE₁)

Output Voltages (V_OA, V_OB, V_OC, V_OD)

Average Output Current per Pin³

Side 1 Output Current (I_O1)

−65°C to +150°C

−40°C to +125°C

849 V peak

790 V peak

50-year minimum

insulation lifetime

50-year minimum

insulation lifetime

Reinforced Insulation

)

−0.5 V to +7.0 V

−0.5 V to V_DDI¹+ 0.5 V

Unipolar Waveform

Basic Insulation

1698 V peak 50-year minimum

insulation lifetime

849 V peak

−0.5 V to V_DDO²+ 0.5 V

Reinforced Insulation

50-year minimum

insulation lifetime

−10 mA to +10 mA

Side 2 Output Current (I_O2)

Common-Mode Transients⁴

−10 mA to +10 mA

−150 kV/μs to +150 kV/μs

DC Voltage

Basic Insulation

1118 V peak Lifetime limited by

package creepage

maximum

¹V_DDIis the input side supply voltage.

²V_DDOis the output side supply voltage.

approved working

voltage per IEC

60950-1

³See Figure 3 for the maximum rated current values for various temperatures.

⁴Refers to the common-mode transients across the insulation barrier.

Common-mode transients exceeding the absolute maximum ratings may

cause latch-up or permanent damage.

Reinforced Insulation

559 V peak

Lifetime limited by

package creepage

maximum

Stresses at or above those listed under Absolute Maximum

Ratings may cause permanent damage to the product. This is a

stress rating only; functional operation of the product at these

or any other conditions above those indicated in the operational

section of this specification is not implied. Operation beyond

the maximum operating conditions for extended periods may

affect product reliability.

approved working

voltage per IEC

60950-1

¹Refers to the continuous voltage magnitude imposed across the isolation

barrier. See the Insulation Lifetime section for more details.

ESD CAUTION

Rev. 0 | Page 11 of 18

ADuM140D/ADuM140E

Data Sheet

Truth Tables

Table 16. ADuM140D Truth Table (Positive Logic)

Default Low (D0),³

V_OxOutput^{1, 2}

Default High (D1),³

V_OxOutput^{1, 2}

Test Conditions/

Comments

V_IxInput^{1, 2}V_DISABLE1Input^{1, 2}

V_DDIState²

Powered

V_DDOState²

Powered

L

H

X

L or NC

H

L

H

L

H

Normal operation

Inputs disabled,

fail-safe output

Fail-safe output

X⁴

Unpowered

Powered

Unpowered

L

H

Indeterminate

¹H means high, L means low, X means don’t care, and NC means not connected.

²V_Ixand V_Oxrefer to the input and output signals of a given channel (A, B, C, or D). V_DISABLE1refers to the input disable signal on the same side as the V_Ixinputs. V_DDIand

V_DDOrefer to the supply voltages on the input and output sides of the given channel, respectively.

³D0 is the ADuM140D0 model and D1 is the ADuM140D1 model. See the Ordering Guide section.

⁴Input pins (V_Ix, DISABLE₁, and V_E2) on the same side as an unpowered supply must be in a low state to avoid powering the device through its ESD protection circuitry.

Table 17. ADuM140E Truth Table (Positive Logic)

Default Low (E0),³Default High (E1),³Test Conditions/

V_IxInput^{1, 2}V_ExInput^{1, 2}

V_DDIState²

Powered

V_DDOState²

Powered

Unpowered

V_OxOutput^{1, 2}

Comments

L

H or NC

L

H

Z

L

H

Z

H

Normal operation

Outputs disabled

Fail-safe output

Outputs disabled

H

X

L

X⁴

H or NC

L⁴

X⁴

Unpowered

Powered

Z

Indeterminate

¹H means high, L means low, X means don’t care, and NC means not connected, and Z means high impedance.

²V_Ixand V_Oxrefer to the input and output signals of a given channel (A, B, C, or D). V_DISABLE1refers to the input disable signal on the same side as the V_Ixinputs. V_DDIand

V

_DDOrefer to the supply voltages on the input and output sides of the given channel, respectively.

³E0 is the ADuM140E0 model and E1 is the ADuM140E1 model. See the Ordering Guide section.

⁴Input pins (V_Ix, DISABLE₁, and V_E2) on the same side as an unpowered supply must be in a low state to avoid powering the device through its ESD protection circuitry.

Rev. 0 | Page 12 of 18

Data Sheet

ADuM140D/ADuM140E

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

V

1

2

3

4

5

6

7

8

16

V

1

2

3

4

5

6

7

8

16

V

DD1

DD2

DD1

DD2

GND

15 GND

GND

15 GND

1

IA

IB

IC

ID

2

1

IA

IB

IC

ID

2

V

14

13

12

11

10

9

V

14

13

12

11

10

9

V

OA

OB

OC

OD

OA

OB

OC

OD

E2

ADuM140D

ADuM140E

TOP VIEW

(Not to Scale)

DISABLE

GND

NC

GND

1

GND

2

1

NIC = NO INTERNAL CONNECTION.

LEAVE THIS PIN FLOATING.

NIC = NO INTERNAL CONNECTION.

LEAVE THIS PIN FLOATING.

Figure 5. ADuM140E Pin Configuration

Figure 4. ADuM140D Pin Configuration

Reference the AN-1109 Application Note for specific layout guidelines.

Table 18. Pin Function Descriptions

Pin No.

ADuM140D

ADuM140E

Mnemonic Description

1

2, 8

3

4

5

1

2, 8

3

4

5

V_DD1

GND₁

V_IA

V_IB

V_IC

Supply Voltage for Isolator Side 1.

Ground 1. Ground reference for Isolator Side 1.

Logic Input A.

Logic Input B.

Logic Input C.

Logic Input D.

6

V_ID

7

Not applicable DISABLE₁

Input Disable 1. This pin disables the isolator inputs. Outputs take on the logic state

determined by the fail-safe option shown in the Ordering Guide.

9, 15

10

9, 15

7

GND₂

NIC

Ground 2. Ground reference for Isolator Side 2.

No Internal Connection. Leave this pin floating.

Not applicable

10

V_E2

Output Enable 2. Active high logic input. When V_E2is high or disconnected, the V_OA, V_OB,

V_OC, and V_ODoutputs are enabled. When V_E2is low, the V_OA, V_OB, V_OC, and V_ODoutputs are

disabled to the high-Z state.

11

12

13

14

16

11

12

13

14

16

VOD

V_OC

V_OB

V_OA

V_DD2

Logic Output D.

Logic Output C.

Logic Output B.

Logic Output A.

Supply Voltage for Isolator Side 2.

Rev. 0 | Page 13 of 18

ADuM140D/ADuM140E

Data Sheet

TYPICAL PERFORMANCE CHARACTERISTICS

14

12

10

8

16

V

= V

= 5V

V

= V

= 5V

DD1

DD2

DD1

DD2

= 3.3V

= 2.5V

= 1.8V

= 3.3V

= 2.5V

= 1.8V

14

12

10

8

6

4

2

0

–40

0

–20

0

20

40

60

80

100

120

140

0

20

40

60

80

100

120

140

160

TEMPERATURE (°C)

DATA RATE (Mbps)

Figure 8. Propagation Delay, T_PLHvs. Temperature at Various Voltages

Figure 6. I_DD1Supply Current vs. Data Rate at Various Voltages

14

16

V

= V

= 5V

V

= V

= 5V

DD1

DD2

DD1

DD2

= 3.3V

= 2.5V

= 1.8V

= 3.3V

= 2.5V

= 1.8V

14

12

10

8

12

10

8

6

4

2

0

–40

0

–20

0

20

40

60

80

100

120

140

0

20

40

60

80

100

120

140

160

TEMPERATURE (°C)

DATA RATE (Mbps)

Figure 9. Propagation Delay, T_PHLvs. Temperature at Various Voltages

Figure 7. I_DD2Supply Current vs. Data Rate at Various Voltages

Rev. 0 | Page 14 of 18

Data Sheet

ADuM140D/ADuM140E

APPLICATIONS INFORMATION

OVERVIEW

PCB LAYOUT

The ADuM140D/ADuM140E use a high frequency carrier to

transmit data across the isolation barrier using iCoupler chip

scale transformer coils separated by layers of polyimide isolation.

Using an on-off keying (OOK) technique and the differential

architecture shown in Figure 11 and Figure 12, the ADuM140D/

ADuM140E have very low propagation delay and high speed.

Internal regulators and input/output design techniques allow

logic and supply voltages over a wide range from 1.7 V to 5.5 V,

offering voltage translation of 1.8 V, 2.5 V, 3.3 V, and 5 V logic.

The architecture is designed for high common-mode transient

immunity and high immunity to electrical noise and magnetic

interference. Radiated emissions are minimized with a spread

spectrum OOK carrier and other techniques.

The ADuM140D/ADuM140E digital isolators require no external

interface circuitry for the logic interfaces. Power supply bypassing

is strongly recommended at the input and output supply pins

(see Figure 10). Bypass capacitors are most conveniently connected

between Pin 1 and Pin 2 for V_DD1and between Pin 15 and Pin 16

for V_DD2. The recommended bypass capacitor value is between

0.01 μF and 0.1 μF. The total lead length between both ends of

the capacitor and the input power supply pin must not exceed

10 mm. Bypassing between Pin 1 and Pin 8 and between Pin 9

and Pin 16 must also be considered, unless the ground pair on

each package side is connected close to the package.

V

DD2

DD1

GND

1

IA

IB

IC

ID

2

V

OA

OB

OC

OD

Figure 11 illustrates the waveforms for models of the ADuM140D/

ADuM140E with the condition of the fail-safe output state equal

to low, where the carrier waveform is off when the input state is

low. If the input side is off or not operating, the fail-safe output state

of low sets the output to low. For the ADuM140D/ADuM140E

with a fail-safe output state of high, Figure 12 illustrates the

conditions where the carrier waveform is off when the input

state is high. When the input side is off or not operating, the

fail-safe output state of high sets the output to high. See the

Ordering Guide for the model numbers that have the fail-safe

output state of low or the fail-safe output state of high.

DISABLE /N/A

NIC/V

E2

1

GND

2

1

NIC = NO INTERNAL CONNECTION. LEAVE THIS PIN FLOATING.

N/A = NOT APPLICABLE.

Figure 10. Recommended Printed Circuit Board Layout

In applications involving high common-mode transients, ensure

that board coupling across the isolation barrier is minimized.

Furthermore, design the board layout such that any coupling

that does occur equally affects all pins on a given component

side. Failure to ensure this can cause voltage differentials between

pins exceeding the Absolute Maximum Ratings of the device,

thereby leading to latch-up or permanent damage.

See the AN-1109 Application Note for board layout guidelines.

REGULATOR

TRANSMITTER

RECEIVER

V

OUT

IN

GND

2

1

Figure 11. Operational Block Diagram of a Single Channel with a Low Fail-Safe Output State

REGULATOR

TRANSMITTER

RECEIVER

V

OUT

IN

GND

2

1

Figure 12. Operational Block Diagram of a Single Channel with a High Fail-Safe Output State

Rev. 0 | Page 15 of 18

ADuM140D/ADuM140E

Data Sheet

PROPAGATION DELAY RELATED PARAMETERS

INSULATION LIFETIME

Propagation delay is a parameter that describes the time it takes

a logic signal to propagate through a component. The propagation

delay to a Logic 0 output may differ from the propagation delay

to a Logic 1 output.

All insulation structures eventually break down when subjected

to voltage stress over a sufficiently long period. The rate of

insulation degradation is dependent on the characteristics of the

voltage waveform applied across the insulation as well as on the

materials and material interfaces.

INPUT (V

)

50%

Ix

The two types of insulation degradation of primary interest are

breakdown along surfaces exposed to the air and insulation

wear out. Surface breakdown is the phenomenon of surface

tracking, and the primary determinant of surface creepage

requirements in system level standards. Insulation wear out is the

phenomenon where charge injection or displacement currents

inside the insulation material cause long-term insulation

degradation.

t_PLH

t_PHL

OUTPUT (V

)

50%

Ox

Figure 13. Propagation Delay Parameters

Pulse width distortion is the maximum difference between these

two propagation delay values and is an indication of how

accurately the timing of the input signal is preserved.

Channel matching is the maximum amount the propagation delay

differs between channels within a single ADuM140D/

ADuM140E component.

Surface Tracking

Surface tracking is addressed in electrical safety standards by

setting a minimum surface creepage based on the working voltage,

the environmental conditions, and the properties of the insulation

material. Safety agencies perform characterization testing on the

surface insulation of components that allows the components to be

categorized in different material groups. Lower material group

ratings are more resistant to surface tracking and, therefore, can

provide adequate lifetime with smaller creepage. The minimum

creepage for a given working voltage and material group is in each

system level standard and is based on the total rms voltage

across the isolation, pollution degree, and material group.

The material group and creepage for the ADuM140D/ADuM140E

isolators are presented in Table 9.

Propagation delay skew is the maximum amount the

propagation delay differs between multiple ADuM140D/

ADuM140E components operating under the same conditions

JITTER MEASUREMENT

Figure 14 shows the eye diagram for the ADuM140D/ADuM140E.

The measurement was taken using an Agilent 81110A pulse

pattern generator at 150 Mbps with pseudorandom bit sequences

(PRBS) 2(n − 1), n = 14, for 5 V supplies. Jitter was measured

with the Tektronix Model 5104B oscilloscope, 1 GHz, 10 GS/sec

with the DPOJET jitter and eye diagram analysis tools. The result

shows a typical measurement on the ADuM140D/ADuM140E

with 490 ps p-p jitter.

Insulation Wear Out

The lifetime of insulation caused by wear out is determined by

its thickness, material properties, and the voltage stress applied.

It is important to verify that the product lifetime is adequate at

the application working voltage. The working voltage supported

by an isolator for wear out may not be the same as the working

voltage supported for tracking. It is the working voltage

5

4

3

2

1

0

applicable to tracking that is specified in most standards.

Testing and modeling have shown that the primary driver of long-

term degradation is displacement current in the polyimide

insulation causing incremental damage. The stress on the

insulation can be broken down into broad categories, such as:

dc stress, which causes very little wear out because there is no

displacement current, and an ac component time varying

voltage stress, which causes wear out.

–10

–5

0

5

10

TIME (ns)

Figure 14. ADuM140D/ADuM140E Eye Diagram

The ratings in certification documents are usually based on

60 Hz sinusoidal stress because this reflects isolation from line

voltage. However, many practical applications have combinations

of 60 Hz ac and dc across the barrier as shown in Equation 1.

Because only the ac portion of the stress causes wear out, the

equation can be rearranged to solve for the ac rms voltage, as is

shown in Equation 2. For insulation wear out with the

polyimide materials used in these products, the ac rms voltage

determines the product lifetime.

Rev. 0 | Page 16 of 18

Data Sheet

ADuM140D/ADuM140E

2

The working voltage across the barrier from Equation 1 is

V

_RMS V_{AC RMS}²V_DC

(1)

(2)

2

V

_RMS V_{AC RMS}²V_DC

V_RMS 240² 400²

_RMS= 466 V

or

2

V_{AC RMS} V_RMS²V_DC

V

where:

V_{AC RMS}is the time varying portion of the working voltage.

V_DCis the dc offset of the working voltage.

V_RMSis the total rms working voltage.

This is the working voltage used together with the material

group and pollution degree when looking up the creepage

required by a system standard.

Calculation and Use of Parameters Example

To determine if the lifetime is adequate, obtain the time varying

portion of the working voltage. To obtain the ac rms voltage,

use Equation 2.

The following example frequently arises in power conversion

applications. Assume that the line voltage on one side of the

isolation is 240 V_{AC RMS}and a 400 V_DCbus voltage is present on

the other side of the isolation barrier. The isolator material is

polyimide. To establish the critical voltages in determining the

creepage, clearance and lifetime of a device, see Figure 15 and

the following equations.

2

V_{AC RMS} V_RMS²V_DC

V

_{AC RMS} 466² 400²

_{AC RMS}= 240 V rms

V

In this case, the ac rms voltage is simply the line voltage of

240 V rms. This calculation is more relevant when the waveform is

not sinusoidal. The value is compared to the limits for working

voltage in Table 15 for the expected lifetime, less than a 60 Hz

sine wave, and it is well within the limit for a 50-year service life.

V

AC RMS

V

DC

PEAK

RMS

Note that the dc working voltage limit in Table 15 is set by the

creepage of the package as specified in IEC 60664-1. This value

can differ for specific system level standards.

TIME

Figure 15. Critical Voltage Example

Rev. 0 | Page 17 of 18

ADuM140D/ADuM140E

OUTLINE DIMENSIONS

Data Sheet

10.50 (0.4134)

10.10 (0.3976)

16

1

9

8

7.60 (0.2992)

7.40 (0.2913)

10.65 (0.4193)

10.00 (0.3937)

0.75 (0.0295)

0.25 (0.0098)

1.27 (0.0500)

BSC

45°

2.65 (0.1043)

2.35 (0.0925)

0.30 (0.0118)

0.10 (0.0039)

8°

0°

COPLANARITY

0.10

SEATING

PLANE

0.51 (0.0201)

0.31 (0.0122)

1.27 (0.0500)

0.40 (0.0157)

0.33 (0.0130)

0.20 (0.0079)

COMPLIANT TO JEDEC STANDARDS MS-013-AA

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS

(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

Figure 16. 16-Lead Standard Small Outline Package [SOIC_W]

Wide Body

(RW-16)

Dimensions shown in millimeters and (inches)

ORDERING GUIDE

No. of

Inputs, Inputs, Voltage

No. of

Withstand

Fail-Safe

Output

State

Temperature

Range

V_DD1

Side

V_DD2

Side

Rating

(kV rms)

Input

Output Package

Package

Option

Model¹

Disable Enable Description

ADuM140D1BRWZ

−40°C to +125°C

4

0

3.75

High

Low

High

Low

Yes

No

Yes

16-Lead SOIC_W RW-16

ADuM140D1BRWZ-RL −40°C to +125°C

ADuM140D0BRWZ −40°C to +125°C

ADuM140D0BRWZ-RL −40°C to +125°C

ADuM140E1BRWZ −40°C to +125°C

ADuM140E1BRWZ-RL −40°C to +125°C

ADuM140E0BRWZ −40°C to +125°C

ADuM140E0BRWZ-RL −40°C to +125°C

¹Z = RoHS Compliant Part.

registered trademarks are the property of their respective owners.

D13119-0-4/15(0)

Rev. 0 | Page 18 of 18


型号：	ADUM140E1BRWZ
厂家：	ADI
描述：	Robust, Quad Channel Isolator W/ Output Enable & 0 Reverse Channels 光电二极管
文件：	总18页 (文件大小：409K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADUM140E1BRWZ [ADI]

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ADUM1410_07

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