ADUM1440ARSZ_技术文档

Micropower

Quad-Channel Digital Isolators

ADuM1440/ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447

Data Sheet

FEATURES

FUNCTIONAL BLOCK DIAGRAMS

Ultralow power operation

3.3 V operation (typical)

V

1

2

3

16

15

14

V

DD1

ADuM144x

QSOP

DD2

GND

1

2

V

ENCODE

DECODE

V

IA

OA

OB

5.6 μA per channel quiescent current, refresh enabled

0.3 μA per channel quiescent current, refresh disabled

148 μA/Mbps per channel typical dynamic current

2.5 V operation (typical)

3.1 μA per channel quiescent current, refresh enabled

0.1 μA per channel quiescent current, refresh disabled

117 μA/Mbps per channel typical dynamic current

Small, 16-lead QSOP and 20-Lead SSOP

Bidirectional communication

Up to 2 Mbps data rate (NRZ)

High temperature operation: 125°C

High common-mode transient immunity: >25 kV/μs

Safety and regulatory approvals

4

5

13

12

IB

V

/V

IC OC

/V

OC IC

6

7

8

11

10

9

V

/V

ID OD

/V

OD ID

EN

2

1

GND

2

Figure 1.

1

20

V

DD1

ADuM144x

DD2

2

3

19

18

GND

2

1

V

ENCODE

DECODE

V

IA

OA

4

5

17

16

IB

OB

V

/V

IC OC

OC IC

6

7

15

14

13

12

11

V

/V

ID OD

OD ID

EN

2

1

UL 1577 component recognition program

2500 V rms for 1 minute per UL 1577 QSOP package

3750V rms for 1 minute per UL 1577 SSOP package

CSA Component Acceptance Notice 5A

VDE certificate of conformity

8

NIC

GND

9

10

GND

1

2

Figure 2.

freeing almost 70% of board space compared to isolators packages

in wide body SOIC packages.

DIN V VDE V 0884-10 (VDE V 0884-10):2006-12

V

_IORM= 565 V_PEAKQSOP package

_IORM= 849 V_PEAKSSOP package

The devices withstand high isolation voltages and meet regulatory

requirements, such as UL and CSA standards. In addition to the

space savings, the ADuM1440/ADuM1441/ADuM1442/

ADuM1445/ADuM1446/ADuM1447 operate with supplies as

low as 2.25 V.

IECEx and ATEX intrinsic safety

Sira 0518 II 1G Ex ia IIC Ga

APPLICATIONS

General-purpose, low power multichannel isolation

1 MHz, low power peripheral interface (SPI)

4 mA to 20 mA loop process controls

Despite the low power consumption, all models of the ADuM1440/

ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447

provide low, pulse width distortion at <8 ns. In addition, every

model has an input glitch filter to protect against extraneous

noise disturbances.

GENERAL DESCRIPTION

The ADuM1440/ADuM1441/ADuM1442/ADuM1445/

ADuM1446/ADuM1447¹are micropower, 4-channel digital

isolators based on the Analog Devices, Inc., iCoupler® technology.

Combining high speed, complementary metal oxide semiconductor

(CMOS) and monolithic air core transformer technologies,

these isolation components provide outstanding performance

characteristics superior to the alternatives, such as optocoupler

devices. As shown in Figure 3, in standard operating mode,

when EN_x= 0 (internal refresh enabled), the current per channel is

less than 10 μA. When EN_x= 1 (internal refresh disabled), the

current per channel drops to less than 1 μA.

1000

100

10

EN = 0

x

EN = 1

x

1

0.1

The ADuM1440/ADuM1441/ADuM1442/ADuM1445/

1

10

100

1000

10000

ADuM1446/ADuM1447 family of quad 2.5 kV digital isolation

devices are packaged in a small 16-lead QSOP and 20-lead SSOP,

¹Protected by U.S. Patents 5,952,849, 6,873,065, 7,075,329, 6,262,600. Other patents pending.

DATA RATE (kbps)

Figure 3. Typical Total Supply Current per Channel (V_DDx= 3.3 V)

Rev. E

Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Technical Support

www.analog.com

ADuM1440/ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447

TABLE OF CONTENTS

Data Sheet

Features .............................................................................................. 1

Applications....................................................................................... 1

General Description......................................................................... 1

Functional Block Diagrams............................................................. 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Electrical Characteristics—3.3 V Operation ............................ 3

Electrical Characteristics—2.5 V Operation ............................ 5

Intrinsic Safety............................................................................ 11

Absolute Maximum Ratings ......................................................... 13

ESD Caution................................................................................ 13

Pin Configurations and Function Descriptions......................... 14

Typical Performance Characteristics ........................................... 17

Applications Information.............................................................. 20

PCB Layout ................................................................................. 20

Propagation Delay-Related Parameters................................... 20

DC Correctness............................................................................ 20

Magnetic Field Immunity............................................................. 21

Power Consumption .................................................................. 22

Insulation Lifetime..................................................................... 22

Outline Dimensions....................................................................... 24

Ordering Guide .......................................................................... 25

Electrical Characteristics—V_DD1= 3.3 V, V_DD2= 2.5 V

Operation....................................................................................... 7

Electrical Characteristics—V_DD1= 2.5 V, V_DD2= 3.3 V

Operation....................................................................................... 8

Package Characteristics ............................................................... 9

Regulatory Information............................................................... 9

Insulation and Safety Related Specifications .......................... 10

DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 Insulation

Characteristics ............................................................................ 10

REVISION HISTORY

3/2014—Rev. 0 to Rev. A

Added SSOP Package.........................................................Universal

Changes to Features Section, Added Figure 2,

1/2017—Rev. D to Rev. E

Changes to Features Section............................................................ 1

Changes to Table 12.......................................................................... 9

Added Intrinsic Safety Section, Table 16; Renumbered Sequentially,

and Table 17..................................................................................... 11

Renumbered Sequentially ................................................................1

Changes to Output Voltage Logic High Parameter, Table 3 ........4

Added Table 15, Renumbered Sequentially; Changes to

Figure 4 ............................................................................................ 11

Change to Supply Voltages (V_DD1, V_DD2) Parameter, Table 17........ 12

Added Figure 6; Changes to Table 20 .......................................... 13

Added Figure 8; Changes to Table 21 .......................................... 14

Added Figure 10, Changes to Table 22 ........................................ 15

Added Figure 30 ............................................................................. 19

Changes to Power Consumption Section; Added Table 23 ...... 21

Added Figure 27 ............................................................................. 23

Changes to Ordering Guide.......................................................... 24

4/2015—Rev. C to Rev. D

Change to General Description Section........................................ 1

4/2015—Rev. B to Rev. C

Changes to Regulatory Information Section ................................ 9

3/2015—Rev. A to Rev. B

Changes to Features Section and Figure 3..................................... 1

Changes to Table 12.......................................................................... 9

Changes to Table 13 and Table 14 ................................................ 10

Updated Outline Dimensions....................................................... 23

Changes to Ordering Guide .......................................................... 24

10/2013—Revision 0: Initial Version

Rev. E | Page 2 of 25

Data Sheet

ADuM1440/ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS—3.3 V OPERATION

All typical specifications are at T_A= 25°C, V_DD1= V_DD2= 3.3 V. Minimum/maximum specifications apply over the entire recommended

operating range of 3.0 V ≤ V_DD1≤ 3.6 V, 3.0 V ≤ V_DD2≤ 3.6 V, and −40°C ≤ T_A≤ +125°C, unless otherwise noted. Switching specifications

are tested with C_L= 15 pF, and CMOS signal levels, unless otherwise noted.

Table 1.

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions/Comments

SWITCHING SPECIFICATIONS

Data Rate

2

180

Mbps

ns

ps/°C

ns

Within pulse-width distortion (PWD) limit

50% input to 50% output

Propagation Delay

Change vs. Temperature

Minimum Pulse Width

Pulse-Width Distortion

Propagation Delay Skew¹

Channel Matching

Codirectional

t_PHL, t_PLH

80

200

PW

PWD

t_PSK

500

Within PWD limit

|t_PLH− t_PHL|

8

10

t_PSKCD

t_PSKOD

10

15

ns

Opposing Direction

¹t_PSKis the magnitude of the worst-case difference in t_PHLand t_PLHthat is measured between units at the same operating temperature, supply voltages, and output load within the

recommended operating conditions.

Table 2.

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions/Comments

2 Mbps, no load

SUPPLY CURRENT

ADuM1440/ADuM1445

I_DD1

I_DD2

I_DD1

I_DD2

I_DD1

I_DD2

732

492

672

552

612

1000

750

900

µA

EN_X= 0 V, V_IH=V_DD, V_IL= 0V

EN_X= 0 V, V_IH= V_DD, V_IL= 0 V

ADuM1441/ADuM1446

ADuM1442/ADuM1447

Rev. E | Page 3 of 25

ADuM1440/ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447

Data Sheet

Table 3. For All Models

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions/Comments

DC SPECIFICATIONS

Input Threshold

Logic High

1

V_IH

V_IL

0.7 V_DDx

V

1

Logic Low

0.3 V_DDx

Output Voltages

Logic High

V_OH

V_OL

I_I

V_DDx¹− 0.1

V_DDx¹− 0.4

3.3

3.1

0.0

0.2

V

I_OUTx= −20 µA, V_Ix= V_IxH

I_OUTx= −4 mA, V_Ix= V_IxH

I_OUTx= 20 µA, V_Ix= V_IxL

I_OUTx= 4 mA, V_Ix= V_IxL

Logic Low

0.1

0.4

+1

1

Input Current per Channel

Input Switching Thresholds

Positive Threshold Voltage

Negative Going Threshold

Input Hysteresis

Undervoltage Lockout, V_DD1or V_DD2

Supply Current per Channel

Quiescent Current

−1

+0.01

µA

0 V ≤ V_Ix≤ V_DDx

V_T+

V_T−

ΔV_T

UVLO

1.8

1.2

0.6

1.5

V

Input Supply

Output Supply

Input (Refresh Off)

Output (Refresh Off)

Dynamic Supply Current

Input

I_{DDI (Q)}

I_{DDO (Q)}

I_{DDI (Q)}

I_{DDO (Q)}

4.8

0.8

0.12

0.13

10

3.3

µA

EN_Xlow

EN_Xhigh

I_{DDI (D)}

I_{DDO (D)}

88

60

µA/Mbps

Output

AC SPECIFICATIONS

Output Rise Time/Fall Time

Common-Mode Transient Immunity²

t_R/t_F

|CM|

2

40

ns

kV/µs

10% to 90%

V_Ix= V_DDx¹, V_CM= 1000 V,

25

transient magnitude = 800 V

Refresh Rate

f_r

14

kbps

¹V_DDx= V_DD1or V_DD2

.

²|CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining V_OUT> 0.8 V_DDx. The common-mode voltage slew rates apply to both rising and

falling common-mode voltage edges.

Rev. E | Page 4 of 25

Data Sheet

ADuM1440/ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447

ELECTRICAL CHARACTERISTICS—2.5 V OPERATION

All typical specifications are at T_A= 25°C, V_DD1= V_DD2= 2.5 V. Minimum/maximum specifications apply over the entire recommended

operating range of 2.25 V ≤ V_DD1≤ 2.75 V, 2.25 V ≤ V_DD2≤ 2.75 V, and −40°C ≤ T_A≤ +125°C, unless otherwise noted. Switching

specifications are tested with C_L= 15 pF, and CMOS signal levels, unless otherwise noted.

Table 4.

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions/Comments

SWITCHING SPECIFICATIONS

Data Rate

2

180

Mbps

ns

ps/°C

ns

Within PWD limit

50% input to 50% output

Propagation Delay

Change vs. Temperature

Pulse-Width Distortion

Minimum Pulse Width

Propagation Delay Skew¹

Channel Matching

Codirectional

t_PHL, t_PLH

112

280

PWD

PW

t_PSK

12

10

|t_PLH− t_PHL

|

500

Within PWD limit

t_PSKCD

t_PSKOD

10

30

ns

Opposing Direction

¹t_PSKis the magnitude of the worst-case difference in t_PHLor t_PLHthat is measured between units at the same operating temperature, supply voltages, and output load within the

recommended operating conditions.

Table 5.

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions/Comments

2 Mbps, no load

SUPPLY CURRENT

ADuM1440/ADuM1445

I_DD1

I_DD2

I_DD1

I_DD2

I_DD1

I_DD2

623

337

552

409

480

800

500

750

µA

EN_X= 0 V, V_IH= V_DD, V_IL= 0 V

ADuM1441/ADuM1446

ADuM1442/ADuM1447

Rev. E | Page 5 of 25

ADuM1440/ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447

Data Sheet

Table 6. For All Models

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions/Comments

DC SPECIFICATIONS

Input Threshold

Logic High

1

V_IH

V_IL

0.7 V_DDx

V

1

Logic Low

0.3 V_DDx

Output Voltages

Logic High

V_OH

V_OL

I_I

V_DDx¹− 0.1

V_DDx¹− 0.4

2.5

2.35

0.0

0.1

+0.01

V

I_Ox= −20 µA, V_Ix= V_IxH

I_Ox= −4 mA, V_Ix= V_IxH

I_Ox= 20 µA, V_Ix= V_IxL

I_Ox= 4 mA, V_Ix= V_IxL

Logic Low

0.1

0.4

+1

1

Input Current per Channel

Input Switching Thresholds

Positive Threshold Voltage

Negative Going Threshold

Input Hysteresis

Undervoltage Lockout, V_DD1or V_DD2

Supply Current per Channel

Quiescent Current

−1

µA

0 V ≤ V_Ix≤ V_DDx

V_T+

V_T−

ΔV_T

UVLO

1.5

1.0

0.5

1.5

V

Input Supply

Output Supply

Input (Refresh Off)

Output (Refresh Off)

Dynamic Supply Current

Input

I_{DDI (Q)}

I_{DDO (Q)}

I_{DDI (Q)}

I_{DDO (Q)}

2.6

0.5

0.05

3.3

1.8

µA

EN_Xlow

EN_Xhigh

I_{DDI (D)}

I_{DDO (D)}

76

41

µA/Mbps

Output

AC SPECIFICATIONS

Output Rise Time/Fall Time

Common-Mode Transient Immunity²

t_R/t_F

|CM|

2

40

ns

kV/µs

10% to 90%

V_Ix= V_DDx¹, V_CM= 1000 V,

25

transient magnitude = 800 V

Refresh Rate

f_r

14

kbps

¹V_DDx= V_DD1or V_DD2

.

²|CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining V_OUT> 0.8 V_DDx. The common-mode voltage slew rates apply to both rising and

falling common-mode voltage edges.

Rev. E | Page 6 of 25

Data Sheet

ADuM1440/ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447

ELECTRICAL CHARACTERISTICS—V_DD1= 3.3 V, V_DD2= 2.5 V OPERATION

All typical specifications are at T_A= 25°C, V_DD1= 3.3 V, and.V_DD2= 2.5 V. Minimum/maximum specifications apply over the entire

recommended operating range of 3.0 V ≤ V_DD1≤ 3.6 V, 2.25 V ≤ V_DD2≤ 2.75 V, and −40°C ≤ T_A≤ +125°C, unless otherwise noted.

Switching specifications are tested with C_L= 15 pF, and CMOS signal levels, unless otherwise noted.

For dc specifications and ac specifications, see Table 3 for Side 1 and see Table 6 for Side 2.

Table 7.

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions/Comments

SWITCHING SPECIFICATIONS

Data Rate

2

Mbps

Within PWD limit

Propagation Delay

Side 1 to Side 2

Side 2 to Side 1

Change vs. Temperature

Pulse-Width Distortion

Pulse Width

Propagation Delay Skew¹

Channel Matching

Codirectional

t_PHL, t_PLH

84

120

280

180

ns

ps/°C

ns

50% input to 50% output

PWD

PW

t_PSK

12

10

|t_PLH− t_PHL

|

500

Within PWD limit

ns

t_PSKCD

t_PSKOD

10

60

ns

Opposing Direction

¹t_PSKis the magnitude of the worst-case difference in t_PHLor t_PLHthat is measured between units at the same operating temperature, supply voltages, and output load within the

recommended operating conditions.

Table 8.

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions/Comments

2 Mbps, no load

SUPPLY CURRENT

ADuM1440/ADuM1445

I_DD1

I_DD2

I_DD1

I_DD2

I_DD1

I_DD2

732

337

672

409

612

480

1000

750

900

750

900

750

µA

EN_X= 0 V, V_IH= V_DD, V_IL= 0 V

ADuM1441/ADuM1446

ADuM1442/ADuM1447

Rev. E | Page 7 of 25

ADuM1440/ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447

Data Sheet

ELECTRICAL CHARACTERISTICS—V_DD1= 2.5 V, V_DD2= 3.3 V OPERATION

All typical specifications are at T_A= 25°C, V_DD1= 2.5, and V_DD2= 3.3 V. Minimum/maximum specifications apply over the entire

recommended operating range of 2.25 V ≤ V_DD1≤ 2.75 V, 3.0 V ≤ V_DD2≤ 3.6 V, and −40°C ≤ T_A≤ +125°C, unless otherwise noted.

Switching specifications are tested with C_L= 15 pF, and CMOS signal levels, unless otherwise noted.

For dc specifications and ac specifications, see Table 6 for Side 1 and see Table 3 for Side 2.

Table 9.

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions/Comments

SWITCHING SPECIFICATIONS

Data Rate

2

Mbps

Within PWD limit

Propagation Delay

Side 1 to Side 2

Side 2 to Side 1

t_PHL,t_PLH

120

84

180

ns

50% input to 50% output

Change vs. Temperature

Pulse-Width Distortion

Pulse Width

Propagation Delay Skew¹

Channel Matching

Codirectional

200

ps/°C

ns

PWD

PW

t_PSK

12

10

|t_PLH− t_PHL

Within PWD limit

|

500

ns

t_PSKCD

t_PSKOD

10

60

ns

Opposing Direction

¹t_PSKis the magnitude of the worst-case difference in t_PHLor t_PLHthat is measured between units at the same operating temperature, supply voltages, and output load within the

recommended operating conditions.

Table 10.

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions/Comments

2 Mbps, no load

SUPPLY CURRENT

ADuM1440/ADuM1445

I_DD1

I_DD2

I_DD1

I_DD2

I_DD1

I_DD2

623

492

552

480

612

1000

750

900

750

900

µA

EN_X= 0 V, V_IH= V_DD, V_IL= 0 V

ADuM1441/ADuM1446

ADuM1442/ADuM1447

Rev. E | Page 8 of 25

Data Sheet

ADuM1440/ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447

PACKAGE CHARACTERISTICS

Table 11.

Parameter

Symbol

R_I-O

C_I-O

C_I

θ_JA

Min Typ

Max

Unit Test Conditions/Comments

Resistance (Input-to-Output)¹

Capacitance (Input-to-Output)¹

Input Capacitance²

10¹³

2

4.0

76

Ω

pF

f = 1 MHz

IC Junction-to-Ambient Thermal

Resistance (QSOP)

°C/W Thermocouple located at center of package underside

IC Junction-to-Ambient Thermal

Resistance (SSOP)

θ_JA

50.5

°C/W Thermocouple located at center of package underside

¹The device is considered a 2-terminal device: Pin 1 through Pin 8 are shorted together, and Pin 9 through Pin 16 are shorted together.

²Input capacitance is from any input data pin to ground.

REGULATORY INFORMATION

See Table 20 and the Insulation Lifetime section for the recommended maximum working voltages for specific cross-isolation waveforms

and insulation levels.

Table 12. Safety Certifications

UL

CSA

VDE

CSA/Sira

Recognized Under UL

1577 Component

Approved under CSA

Component Acceptance

Notice 5A

Certified according to

DIN V VDE V 0884-10

Certified for use in intrinsic

safety (IS) to IS applications

Recognition Program¹

(VDE V 0884-10):2006-12²under ATEX and IECEx

Single Protection

CSA 60950-1-07+A1+A2 and

IEC 60950-1 second edition

+A1+A2

QSOP package:

reinforced insulation,

565 V_PEAKQSOP package

ATEX: EN 60079-0:2012+A11:2013

and EN 60079-11:2012

2500 V RMS Isolation

Voltage (RQ-16 Only) insulation, 310 V rms

maximum working voltage

QSOP package: basic

SSOP package:

reinforced insulation,

849 V_PEAKSSOP package

IECEx: IEC 60079-0:2011 Edition 6

and IEC 60079-11:2011 Edition 6

3750 V RMS Isolation

Voltage (RS-20 Only)

SSOP package: basic insulation

at 510 V rms (721 V_PEAK

II 1G Ex ia IIC Ga

)

maximum working voltage and

IEC 60601-1 Edition 3.1 250 V

(1 means of patient protection

(MOPP)); reinforced insulation at

255 V rms (360 V_PEAK) maximum

working voltage

File E214100

File 205078

File 2471900-4880-0001 File 70013932

¹In accordance with UL 1577, each ADuM1440/ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447 is proof tested by applying an insulation test voltage and

measuring leakage during final production testing. QSOP package devices are tested at ≥3000 V rms for 1 sec with a current leakage detection limit = 5 μA. SSOP

package devices are tested at ≥4500 V rms for 1 sec with a current leakage detection limit = 10 μA.

²In accordance with DIN V VDE V 0884-10, each ADuM1440/ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447 is proof tested by applying an insulation test

voltage ≥1059 V_PEAKfor 1 second (partial discharge detection limit = 5 pC). The asterisk (*) marked on the component designates DIN V VDE V 0884-10 approval.

Rev. E | Page 9 of 25

ADuM1440/ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447

Data Sheet

INSULATION AND SAFETY RELATED SPECIFICATIONS

Table 13.

Parameter

Symbol Value Unit

Test Conditions/Comments

Rated Dielectric Insulation Voltage (RQ-16)

Rated Dielectric Insulation Voltage (RS-20)

Minimum External Tracking and Air Gap, RQ-16 (Creepage

and Clearance)

2500

3750

3.1

V rms

1-minute duration

L(I02)

L(I01)

L(I02)

mm min Measured from input terminals to output

terminals, shortest distance path along

package body

mm min Measured from input terminals to output

terminals, shortest distance through air, line

of sight, in the PCB mounting plane

mm min Measured from input terminals to output

terminals, shortest distance path along

package body

mm min Measured from input terminals to output

terminals, shortest distance through air, line

of sight, in the PCB mounting plane

Minimum Clearance in the Plane of the Printed Circuit

Board, RQ-16 (PCB Clearance)

3.8

5.1

Minimum External Tracking and Air Gap, RS-20 (Creepage

and Clearance)

Minimum Clearance in the Plane of the Printed Circuit

Board, RS-20 (PCB Clearance)

Minimum Internal Gap (Internal Clearance)

Tracking Resistance (Comparative Tracking Index)

Isolation Group

0.017 mm min Insulation distance through insulation

CTI

>400

II

V

DIN IEC 112/VDE 0303 Part 1

Material Group (DIN VDE 0110, 1/89, Table 1)

DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 INSULATION CHARACTERISTICS

These isolators are suitable for reinforced electrical isolation within the safety limit data only. Maintenance of the safety data is ensured by

protective circuits. The asterisk (*) marked on packages denotes DIN V VDE V 0884-10 approval.

Table 14. 16-Lead QSOP (RQ-16)

Description

Test Conditions/Comments

Symbol Characteristic

Unit

Installation Classification per DIN VDE 0110

For Rated Mains Voltage ≤ 150 V rms

For Rated Mains Voltage ≤ 300 V rms

For Rated Mains Voltage ≤ 400 V rms

Climatic Classification

Pollution Degree per DIN VDE 0110, Table 1

Maximum Working Insulation Voltage

Input-to-Output Test Voltage, Method b1

I to IV

I to III

I to II

40/105/21

2

V_IORM

V_pd(m)

565

1059

V_PEAK

V_IORM× 1.875 = V_pd(m), 100% production test,

t

_ini= t_m= 1 sec, partial discharge < 5 pC

Input-to-Output Test Voltage, Method a

After Environmental Tests Subgroup 1

V_IORM× 1.5 = V_pd(m), t_ini= 60 sec, t_m= 10 sec,

partial discharge < 5 pC

V_IORM× 1.2 = V_pd(m), t_ini= 60 sec, t_m= 10 sec,

partial discharge < 5 pC

V_pd(m)

847

678

V_PEAK

After Input and/or Safety Test Subgroup 2

and Subgroup 3

Highest Allowable Overvoltage

Surge Isolation Voltage

V_IOTM

V_IOSM

4000

6250

V_PEAK

V_PEAK= 10 kV, 1.2 µs rise time, 50 µs, 50% fall time

Safety Limiting Values

Maximum value allowed in the event of a failure

(see Figure 4)

Case Temperature

Total Power Dissipation at 25°C

Insulation Resistance at T_S

T_S

I_S1

R_S

150

1.64

>10⁹

°C

W

Ω

V_IO= 500 V

Rev. E | Page 10 of 25

Data Sheet

ADuM1440/ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447

Table 15. 20-Lead SSOP (RS-20)

Description

Conditions

Symbol Characteristic Unit

Installation Classification per DIN VDE 0110

For Rated Mains Voltage ≤ 150 V rms

For Rated Mains Voltage ≤ 300 V rms

For Rated Mains Voltage ≤ 400 V rms

Climatic Classification

Pollution Degree per DIN VDE 0110, Table 1

Maximum Working Insulation Voltage

Input-to-Output Test Voltage, Method b1

I to IV

I to III

40/105/21

2

V_IORM

V_pd(m)

849

1592

V_PEAK

V_IORM× 1.875 = V_pd(m), 100% production test, t_ini= t_m

1 sec, partial discharge < 5 pC

=

Input-to-Output Test Voltage, Method a

After Environmental Tests Subgroup 1

V_IORM× 1.5 = V_pd(m), t_ini= 60 sec, t_m= 10 sec, partial

discharge < 5 pC

V_IORM× 1.2 = V_pd(m),t_ini= 60 sec, t_m= 10 sec, partial

discharge < 5 pC

V_pd(m)

1273

1018

V_PEAK

After Input and/or Safety Test Subgroup 2

and Subgroup 3

Highest Allowable Overvoltage

Surge Isolation Voltage

V_IOTM

V_IOSM

6000

V_PEAK

V_PEAK= 10 kV, 1.2 µs rise time, 50µs, 50% fall time

Safety Limiting Values

Maximum value allowed in the event of a failure

(see Figure 4)

Case Temperature

Total Power Dissipation at 25°C

T_S

I_S1

R_S

150

2.5

°C

W

Insulation Resistance at T_S

V_IO= 500 V

>10⁹

Ω

INTRINSIC SAFETY

The ADuM1440/ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447 support intrinsic safety for IS to IS applications under

IEC 60079-11, and carry ATEX and IECEx certifications. These devices do not currently support IS to non IS galvanic isolation

applications due to the minimum insulation requirements of IEC60079-11.

Product Conformity Certificate

Sira 16ATEX2265U and IECEx SIR 16.0091U

Special Conditions for Safe Use

These components are certified to comply with IEC 60079-11:2011. When one of these components is used in equipment, the component

is to be fitted on a PCB inside a suitable enclosure and recertified as equipment. The creepage and clearance distances across the isolating

component have been evaluated, but the distances to other circuitry remain the responsibility of the user of the certified equipment.

This assembly is an isolating component between separate intrinsically safe circuits. It is recommended that the assembly be connected to

suitably certified intrinsically safe circuits considering the entity parameters in Table 16.

Table 16. IS Entity Parameters

Package Type

16-Lead QSOP

20-Lead SSOP

Entity Parameters Side 1¹

Entity Parameters Side 2

U_i= 42 V, I_i= 275 mA, P_i= 1.3W, L_i= 0, C_i= 4pF

U_i= 42 V, I_i= 275 mA, P_i= 1.3W. L_i= 0, C_i= 4pF

¹L_iis defined as input inductance, C_iis input capacitance, P_iis input power, U_iis input voltage, and I_iis input current.

The components (for example, digital isolators) being certified have the following safety ratings listed in Table 17. The temperature class is

determined based on Table 17.

Table 17. Temperature Class Information

Maximum Component

Temperature (°C)

Package Type

16-Lead QSOP

20-Lead SSOP

Maximum Power Side 1 (W) Maximum Power Side 2 (W)

Ambient Temperature (°C)

−40°C to +85°C

1.3

189.8

218

Rev. E | Page 11 of 25

ADuM1440/ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447

Data Sheet

3.0

Recommended Operating Conditions

SSOP20

Table 18.

2.5

Parameter

Symbol

T_A

V_DD1, V_DD2

Value

Operating Temperature

Supply Voltages¹

Input Signal Rise and Fall Times

−40°C to +125°C

2.25 V to 3.6 V

1.0 ms

2.0

1.5

1.0

0.5

0

QSOP16

¹All voltages are relative to their respective grounds. See the DC Correctness

section for information on immunity to external magnetic fields.

0

50

100

150

200

AMBIENT TEMPERATURE (°C)

Figure 4. Thermal Derating Curve, Dependence of Safety-Limiting Values

with Case Temperature per DIN V VDE V 0884-10

Rev. E | Page 12 of 25

Data Sheet

ADuM1440/ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447

ABSOLUTE MAXIMUM RATINGS

T_A= 25°C, unless otherwise noted.

Table 20. Maximum Continuous Working Voltage¹

Parameter

Value

Constraint

Table 19.

Parameter

AC Voltage

Rating

60 Hz Bipolar Waveform

60 Hz Unipolar Waveform

Basic Insulation

DC Voltage

565 V_PEAK50-year minimum lifetime

975 V_PEAK50-year minimum lifetime

Supply Voltages (V_DD1, V_DD2

)

−0.5 V to +5 V

−0.5 V to V_DDI+ 0.5 V

−0.5 V to V_DD2+ 0.5 V

Input Voltages (V_IA, V_IB

Output Voltages (V_OA, V_OB

Average Output Current per Pin¹

Side 1 (I_O1

Side 2 (I_O2

Common-Mode Transients²

)

Basic Insulation

)

−10 mA to +10 mA

−100 kV/µs to +100 kV/µs

−65°C to +150°C

¹Refers to continuous voltage magnitude imposed across the isolation

barrier. See the Insulation Lifetime section for more details.

ESD CAUTION

Storage Temperature (T_ST) Range

Ambient Operating Temperature

(T_A) Range

−40°C to +125°C

¹See Figure 4 for maximum safety power values for various temperatures.

²Refers to common-mode transients across the insulation barrier. Common-mode

transients exceeding the absolute maximum ratings can cause latch-up or

permanent damage.

Stresses at or above those listed under Absolute Maximum

Ratings may cause permanent damage to the product. This is a

stress rating only; functional operation of the product at these

or any other conditions above those indicated in the operational

section of this specification is not implied. Operation beyond

the maximum operating conditions for extended periods may

affect product reliability.

Table 21. Truth Table (Positive Logic) for all Models

V_IxInput^{1, 2}

V_DDIState³

Powered

Unpowered

V_DDOState⁴

Powered

EN_xInput¹

V_OxOutput¹

Description

H

L

H

L

H

L

H

L

H

L⁵

Normal operation; data is high and refresh is enabled.

Normal operation; data is low and refresh is enabled.

Output is high, and refresh is disabled.

Output is low, and refresh is disabled.

Input unpowered. Outputs are in the default state, high for

ADuM1440, ADuM1441, and ADuM1442, and low ADuM1445,

ADuM1446, and ADuM1447. Outputs return to input state

within 150 µs of V_DDIpower restoration. See the pin function

descriptions (Table 22 through Table 24) for more details.

L

Default

L

Unpowered

Powered

H

X

Hold

Z

Input unpowered. Outputs are the last state before input

power is shut down.

X

Unpowered

Output unpowered. Output pins are in high impedance state.

Outputs return to input state within 34 µs of V_DDOpower

restoration. See the pin function descriptions (Table 22 through

Table 24) for more details.

¹H = high, L = low, X = don’t care, and Z = high impedance.

²V_Ixand V_Oxrefer to the input and output signals of a given channel (A, B, C, or D).

³V_DDIrefers to the power supply on the input side of a given channel (A, B, C, or D).

⁴V_DDOrefers to the power supply on the output side of a given channel (A, B, C, or D).

⁵Low input must follow a falling edge; otherwise, it can be in the default low state.

Rev. E | Page 13 of 25

ADuM1440/ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

Data Sheet

V

1

20

19

18

17

16

15

V

DD2

V

1

2

3

4

5

6

7

8

16

V

DD2

DD1

1

DD1

2

GND

2

1

2

GND

15 GND

1

V

3

V

14

13

12

11

V

IA

IB

IC

ID

OA

OB

OC

OD

IA

IB

IC

ID

OA

OB

OC

OD

ADuM1440/

ADuM1445

4

ADuM1440/

ADuM1445

TOP VIEW

5

(Not to Scale)

6

TOP VIEW

(Not to Scale)

EN

7

14 EN

2

EN

10 EN

1

2

9 GND

2

NIC

8

13 NIC

12 NIC

11 GND

GND

1

NIC

1

9

1

2

PIN 2 AND PIN 8 ARE INTERNALLY CONNECTED. CONNECTING BOTH

GND

10

1

TO GND IS RECOMMENDED.

1

PIN 9 AND PIN 15 ARE INTERNALLY CONNECTED. CONNECTING

NIC = NOT INTERNALLY CONNECTED.

PIN 2 AND PIN 10 ARE INTERNALLY CONNECTED.

BOTH TO GND IS RECOMMENDED.

2

1

2

CONNECTING BOTH TO GND IS RECOMMENDED.

1

PIN 11 AND PIN 19 ARE INTERNALLY CONNECTED.

CONNECTING BOTH TO GND IS RECOMMENDED.

2

Figure 6. ADuM1440/ADuM1445 SSOP Pin Configuration

Figure 5. ADuM1440/ADuM1445 QSOP Pin Configuration

Table 22. ADuM1440/ADuM1445 Pin Function Descriptions¹

QSOP

SSOP

Pin No.

Pin No.²

Mnemonic

Description

1

V_DD1

Supply Voltage for Isolator Side 1 (2.25 V to 3.6 V). Connect a ceramic bypass capacitor in the 0.01

µF to 0.1 µF range between V_DD1(Pin 1) and GND₁(Pin 2).

2, 8

2, 10

GND₁

Ground 1. Ground reference for Isolator Side 1. Pin 2 and Pin 8 are internally connected, and connecting

both to GND₁is recommended.

3

4

5

6

7

3

4

5

3

7

V_IA

V_IB

V_IC

V_ID

EN₁

Logic Input A.

Logic Input B.

Logic Input C.

Logic Input D.

Refresh/Watchdog Enable 1. Connecting Pin 7 to GND₁enables input/output refresh and

watchdog functionality for Side 1, supporting standard iCoupler operation. Tying Pin 7 to V_DD1

disables refresh and watchdog functionality for lowest power operation, see the Applications

Information section for a detailed description of this mode. EN₁and EN₂must be set to the same

logic state.

9, 15

10

11, 19

14

GND₂

EN₂

Ground 2. Ground reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected, and

connecting both to GND₂is recommended.

Refresh/Watchdog Enable 2. Connecting Pin 10 to GND₂enables input/output refresh and

watchdog functionality for Side 2, supporting standard iCoupler operation. Tying Pin 10 to V_DD2

disables refresh and watchdog functionality for lowest power operation, see the Applications

Information section for a detailed description of this mode. EN₁and EN₂must be set to the same

logic state.

11

12

13

14

16

15

16

17

18

20

V_OD

V_OC

V_OB

V_OA

V_DD2

Logic Output D.

Logic Output C.

Logic Output B.

Logic Output A.

Supply Voltage for Isolator Side 2 (2.25 V to 3.6 V). Connect a ceramic bypass capacitor in the 0.01

µF to 0.1 µF range between V_DD2(Pin 16) and GND₂(Pin 15).

N/A

8, 9, 12, 13

NC

No Connect. Do not connect to this pin.

¹Reference the AN-1109 Application Note for specific layout guidelines.

²N/A = not applicable.

Rev. E | Page 14 of 25

Data Sheet

ADuM1440/ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447

V

1

2

20

2

19 GND

2

V

1

2

3

4

5

6

7

8

16

V

DD1

1

DD2

DD1

DD2

1

2

GND

15 GND

1

2

V

3

18

17

16

15

V

14

13

12

11

V

IA

IB

IC

OA

OB

OC

ID

IA

IB

IC

OA

OB

OC

ID

ADuM1441/

ADuM1446

4

ADuM1441/

ADuM1446

TOP VIEW

5

(Not to Scale)

V

6

TOP VIEW

V

OD

(Not to Scale)

EN

7

14 EN

2

EN

10 EN

1

2

NIC

8

13 NIC

12 NIC

11 GND

2

9 GND

2

GND

1

NIC

1

9

1

2

PIN 2 AND PIN 8 ARE INTERNALLY CONNECTED. CONNECTING BOTH

TO GND IS RECOMMENDED.

GND

10

1

PIN 9 AND PIN 15 ARE INTERNALLY CONNECTED. CONNECTING

NIC = NOT INTERNALLY CONNECTED.

BOTH TO GND IS RECOMMENDED.

2

1

2

PIN 2 AND PIN 10 ARE INTERNALLY CONNECTED.

CONNECTING BOTH TO GND IS RECOMMENDED.

1

PIN 11 AND PIN 19 ARE INTERNALLY CONNECTED.

CONNECTING BOTH TO GND IS RECOMMENDED.

2

Figure 8. ADuM1441/ADuM1446 SSOP Pin Configuration

Figure 7. ADuM1441/ADuM1446 QSOP Pin Configuration

Table 23. ADuM1441/ADuM1446 Pin Function Descriptions¹

QSOP SSOP

Pin No. ²Pin No.

Mnemonic Description

1

V_DD1

Supply Voltage for Isolator Side 1 (2.25 V to 3.6 V). Connect a ceramic bypass capacitor in the 0.01

µF to 0.1 µF range between V_DD1(Pin 1) and GND₁(Pin 2).

2, 8

2, 10

GND₁

Ground 1. Ground reference for Isolator Side 1. Pin 2 and Pin 8 are internally connected, and connecting

both to GND₁is recommended.

3

4

5

6

7

3

4

5

3

7

V_IA

V_IB

V_IC

V_OD

EN₁

Logic Input A.

Logic Input B.

Logic Input C.

Logic Output D.

Refresh/Watchdog Enable 1. Connecting Pin 7 to GND₁enables input/output refresh and

watchdog functionality for Side 1, supporting standard iCoupler operation. Tying Pin 7 to V_DD1

disables refresh and watchdog functionality for lowest power operation, see the Applications

Information section for a detailed description of this mode. EN₁and EN₂must be set to the same

logic state.

9, 15

10

11, 19

14

GND₂

EN₂

Ground 2. Ground reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected, and

connecting both to GND₂is recommended.

Refresh/Watchdog Enable 2. Connecting Pin 10 to GND₂enables input/output refresh and

watchdog functionality for Side 2, supporting standard iCoupler operation. Tying Pin 10 to V_DD2

disables refresh and watchdog functionality for lowest power operation, see the Applications

Information section for a detailed description of this mode. EN₁and EN₂must be set to the same

logic state.

11

12

13

14

16

15

16

17

18

20

V_ID

Logic Input D.

Logic Output C.

Logic Output B.

Logic Output A.

V_OC

V_OB

V_OA

V_DD2

Supply Voltage for Isolator Side 2 (2.25 V to 3.6 V). Connect a ceramic bypass capacitor in the 0.01

µF to 0.1 µF range between V_DD2(Pin 16) and GND₂(Pin 15).

N/A

8, 9, 12, 13

NC

No Connect. Do not connect to this pin.

¹Reference the AN-1109 Application Note for specific layout guidelines.

²N/A = not applicable.

Rev. E | Page 15 of 25

ADuM1440/ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447

Data Sheet

V

1

2

20

V

DD2

V

1

2

3

4

5

6

7

8

16

V

DD2

DD1

1

DD1

1

2

GND

19 GND

GND

15 GND

1

2

1

2

V

3

18

17

16

15

V

14

13

12

11

V

IA

IB

OA

OB

IC

IA

OA

OB

IC

ADuM1442/

ADuM1447

4

IB

ADuM1442/

ADuM1447

TOP VIEW

V

5

V

OC

OD

OC

OD

(Not to Scale)

V

6

V

TOP VIEW

ID

(Not to Scale)

EN

7

14 EN

2

EN

10 EN

2

1

2

9 GND

2

NIC

8

13 NIC

12 NIC

11 GND

GND

1

9

1

2

PIN 2 AND PIN 8 ARE INTERNALLY CONNECTED. CONNECTING BOTH

TO GND IS RECOMMENDED.

1

2

GND

10

1

2

1

PIN 9 AND PIN 15 ARE INTERNALLY CONNECTED. CONNECTING

NIC = NOT INTERNALLY CONNECTED.

PIN 2 AND PIN 10 ARE INTERNALLY CONNECTED.

CONNECTING BOTH TO GND IS RECOMMENDED.

PIN 11 AND PIN 19 ARE INTERNALLY CONNECTED.

BOTH TO GND IS RECOMMENDED.

2

1

2

1

CONNECTING BOTH TO GND IS RECOMMENDED.

2

Figure 9. ADuM1442/ADuM1447 QSOP Pin Configuration

Figure 10. ADuM1442/ADuM1447 SSOP Pin Configuration

Table 24. ADuM1442/ADuM1447 Pin Function Descriptions¹

QSOP SSOP

Pin No. ²Pin No.

Mnemonic

Description

1

V_DD1

Supply Voltage for Isolator Side 1 (2.25 V to 3.6 V). Connect a ceramic bypass capacitor in the 0.01

µF to 0.1 µF range between V_DD1(Pin 1) and GND₁(Pin 2).

2, 8

2, 10

GND₁

Ground 1. Ground reference for Isolator Side 1. Pin 2 and Pin 8 are internally connected, and connecting

both to GND₁is recommended.

3

4

5

6

7

3

4

5

3

7

V_IA

V_IB

V_OC

V_OD

EN₁

Logic Input A.

Logic Input B.

Logic Output C.

Logic Output D.

Refresh/Watchdog Enable 1. Connecting Pin 7 to GND₁enables input/output refresh and

watchdog functionality for Side 1, supporting standard iCoupler operation. Tying Pin 7 to V_DD1

disables refresh and watchdog functionality for lowest power operation, see the Applications

Information section for detailed description of this mode. EN₁and EN₂must be set to the same

logic state.

9, 15

10

11, 19

14

GND₂

EN₂

Ground 2. Ground reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected, and

connecting both to GND₂is recommended.

Refresh/Watchdog Enable 2. Connecting Pin 10 to GND₂enables input/output refresh and

watchdog functionality for Side 2, supporting standard iCoupler operation. Tying Pin 10 to V_DD2

disables refresh and watchdog functionality for lowest power operation, see the Applications

Information section for a detailed description of this mode. EN₁and EN₂must be set to the same

logic state.

11

12

13

14

16

15

16

17

18

20

V_ID

V_IC

V_OB

V_OA

V_DD2

Logic Input D.

Logic Input C.

Logic Output B.

Logic Output A.

Supply Voltage for Isolator Side 2 (2.25 V to 3.6 V). Connect a ceramic bypass capacitor in the 0.01

µF to 0.1 µF range between V_DD2(Pin 16) and GND₂(Pin 15).

N/A

8, 9, 12, 13

NC

No Connect. Do not connect to this pin.

¹Reference the AN-1109 Application Note for specific layout guidelines.

²N/A = not applicable.

Rev. E | Page 16 of 25

Data Sheet

ADuM1440/ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447

TYPICAL PERFORMANCE CHARACTERISTICS

350

140

120

100

80

300

15

4

2

0

10

250

5

0

20

40

0

20

40

200

150

100

50

60

40

20

V

INPUT CURRENT

V

OUTPUT CURRENT

DDx

0

500

1000

DATA RATE (kbps)

1500

2000

0

500

1000

DATA RATE (kbps)

1500

2000

Figure 11. Current Consumption per Input vs. Data Rate for 2.5 V,

EN_x= Low Operation

Figure 14. Current Consumption per Output vs. Data Rate for 3.3 V,

EN_x= Low Operation

90

80

160

140

1.0

4

2

0

70

60

50

40

30

20

10

0

120

100

80

60

40

20

0

0.5

0

5

10

0

20

40

V

INPUT CURRENT

V

OUTPUT CURRENT

DDx

0

500

1000

DATA RATE (kbps)

1500

2000

0

500

1000

DATA RATE (kbps)

1500

2000

Figure 12. Current Consumption per Output vs. Data Rate for 2.5 V,

EN_x= Low Operation

Figure 15. Current Consumption per Input vs. Data Rate for 2.5 V,

EN_x= High Operation

400

90

80

350

15

1.0

10

70

300

0.5

5

60

0

250

0

20

40

0

5

10

50

40

30

20

10

0

200

150

100

50

V

OUTPUT CURRENT

V

INPUT CURRENT

DDx

0

500

1000

DATA RATE (kbps)

1500

2000

0

500

1000

DATA RATE (kbps)

1500

2000

Figure 13. Current Consumption per Input vs. Data Rate for 3.3 V,

EN_x= Low Operation

Figure 16. Current Consumption per Output vs. Data Rate for 2.5 V,

EN_x= High Operation

Rev. E | Page 17 of 25

ADuM1440/ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447

Data Sheet

200

180

160

140

120

100

80

300

250

200

150

100

50

FALLING

RISING

1.0

0.5

0

5

10

60

40

20

V

INPUT CURRENT

DDx

0

500

1000

DATA RATE (kbps)

1500

2000

0

0.5

1.0

1.5

2.0

2.5

3.0

DATA INPUT VOLTAGE (V)

Figure 17. Current Consumption per Input vs. Data Rate for V_DDX= 3.3 V,

EN_x= High Operation

Figure 20. I_DDxCurrent per Input vs. Data Input Voltage for V_DDx= 2.5 V

140

10

9

1.0

120

8

0.5

100

7

0

5

10

6

80

60

40

20

0

5

4

3

2

1

OUTPUT

V

OUTPUT CURRENT

DDx

INPUT

0

–40

0

500

1000

DATA RATE (kbps)

1500

2000

–20

0

20

40

60

80

100

120

140

TEMPERATURE (°C)

Figure 18. Current Consumption per Output vs. Data Rate for V_DDx= 3.3 V,

EN_x= High Operation

Figure 21. Typical Input and Output Supply Current per Channel vs.

Temperature for V_DDx= 2.5 V, Data Rate = 100 kbps

600

10

9

FALLING

RISING

500

400

300

200

100

0

8

7

6

5

4

3

2

1

OUTPUT

INPUT

0

–40

0

1

2

3

4

–20

0

20

40

60

80

100

120

140

DATA INPUT VOLTAGE (V)

TEMPERATURE (°C)

SFigure 19. Typical I_DDxCurrent per Input vs.

Data Input Voltage for V_DDx= 3.3 V

Figure 22. Typical Input and Output Supply Current per Channel vs.

Temperature for V_DDx= 3.3 V, Data Rate = 100 kbps

Rev. E | Page 18 of 25

Data Sheet

ADuM1440/ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447

100

90

80

70

60

50

40

30

20

10

0

120

100

80

60

40

20

OUTPUT

INPUT

0

2.0

2.5

3.0

3.5

4.0

–40

–20

0

20

40

60

80

100

120

140

TRANSMITTER V

(V)

TEMPERATURE (°C)

DDx

Figure 23. Typical Input and Output Supply Current per Channel vs.

Temperature for V_DDx= 2.5 V, Data Rate = 1000 kbps

Figure 26. Typical Glitch Filter Operation Threshold

100

90

80

70

60

50

40

30

20

140

120

100

80

60

40

20

10

V

= 2.5V

= 3.3V

DDx

OUTPUT

INPUT

0

–40

0

–40

–20

0

20

40

60

80

100

120

140

–20

0

20

40

60

80

100

120

140

TEMPERATURE (°C)

Figure 24. Typical Input and Output Supply Current per Channel vs.

Temperature for V_DDx= 3.3 V, Data Rate = 1000 kbps

Figure 27. Typical Refresh Period vs. Temperature for

3.3 V and 2.5 V Operation

140

120

100

80

120

100

80

60

40

20

0

60

40

20

V

= 2.5V

= 3.3V

DDx

0

–40

–20

0

20

40

60

80

100

120

140

2.0

2.5

3.0

3.5

4.0

TEMPERATURE (°C)

V

VOLTAGE (V)

DDx

Figure 25. Typical Propagation Delay vs. Temperature for

V_DDx= 3.3 V or V_DDx= 2.5 V

Figure 28. Typical Refresh Period vs. V_DDXVoltage

Rev. E | Page 19 of 25

ADuM1440/ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447

APPLICATIONS INFORMATION

Data Sheet

PCB LAYOUT

INPUT (V )

Ix

50%

The ADuM1440/ADuM1441/ADuM1442/ADuM1445/

t_PLH

t_PHL

ADuM1446/ADuM1447 digital isolators require no external

interface circuitry for the logic interfaces. Power supply bypassing

is strongly recommended at both input and output supply pins:

OUTPUT (V

)

50%

Ox

Figure 31. Propagation Delay Parameters

V

_DD1and V_DD2(see Figure 29). Choose a capacitor value between

Pulse width distortion is the maximum difference between

these two propagation delay values and an indication of how

accurately the timing of the input signal is preserved.

0.01 µF and 0.1 µF. The total lead length between both ends of the

capacitor and the input power supply pin must not exceed 20 mm.

Using proper PCB design choices, the ADuM1440/ADuM1441/

ADuM1442/ADuM1445/ADuM1446/ADuM1447 readily meets

CISPR 22 Class A (and FCC Class A) emissions standards, as

well as the more stringent CISPR 22 Class B (and FCC Class B)

standards in an unshielded environment. Refer to the AN-1109

Application Note, Recommendations for Control of Radiated

Emissions with iCoupler Devices, for PCB-related EMI mitigation

techniques, including board layout and stack-up issues.

Channel-to-channel matching is the maximum amount of time

the propagation delay differs between channels within a single

ADuM1440/ADuM1441/ADuM1442/ADuM1445/ADuM1446/

ADuM1447 component.

Propagation delay skew is the maximum amount of time the

propagation delay differs between multiple ADuM1440/

ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447

components operating under the same conditions.

V

DD2

DD1

GND

V

GND

1

2

In edge-based systems, it is critical to reject pulses that are too

short to be handled by the encode and decode circuits. The

ADuM1440/ADuM1441/ADuM1442/ADuM1445/ADuM1446/

ADuM1447 implement a glitch filter to reject pulses less than

the glitch filter operating threshold. This threshold depends on

the operating voltage, as shown in Figure 26. Any pulse shorter

than the glitch filter does not pass to the output. When the refresh

circuit is enabled, pulses that match the glitch filter width have a

small probability of being stretched until corrected by the next

refresh cycle, or by the next valid data through that channel. To

avoid issues with pulse stretching, observe the minimum pulse

width requirements listed in the switching specifications.

V

IA

IB

OA

V

OB

V

IC/ OC

OC/ IC

V

ID/ OD

OD/ ID

EN

1

EN

2

GND

1

GND

2

Figure 29. Recommended Printed Circuit Board Layout, QSOP

V

DD2

DD1

GND

V

GND

1

2

V

IA

IB

OA

V

OB

V

IC/ OC

OC/ IC

V

ID/ OD

OD/ ID

NC/CTRL

EN

CTRL

NC/EN

NC

1

2

NC

GND

2

1

DC CORRECTNESS

Standard Operating Mode

Figure 30. Recommended Printed Circuit Board Layout, SSOP

For applications involving high common-mode transients, it is

important to minimize board coupling across the isolation barrier.

Furthermore, design the board layout so that any coupling that

does occur equally affects all pins on a given component side.

Failure to ensure this can cause voltage differentials between

pins exceeding the absolute maximum ratings of the device,

thereby leading to latch-up or permanent damage.

Positive and negative logic transitions at the isolator input cause

narrow (~1 ns) pulses to be sent to the decoder using the

transformer. The decoder is bistable and is, therefore, either set

or reset by the pulses, indicating input logic transitions. When

refresh and watchdog functions are enabled by pulling EN₁and

EN₂low, in the absence of logic transitions at the input for more

than ~140 µs, a periodic set of refresh pulses indicative of the

correct input state is sent to ensure dc correctness at the output. If

the decoder receives no internal pulses of more than approximately

200 µs, the input side is assumed unpowered or nonfunctional,

in which case, the isolator watchdog circuit forces the output to

a default state. The default state is either high as in the ADuM1440,

ADuM1441, and ADuM1442 versions, or low as in the ADuM1445,

ADuM1446, and ADuM1447 versions.

PROPAGATION DELAY-RELATED PARAMETERS

These products are optimized for minimum power consumption

by eliminating as many internal bias currents as possible. As a

result, the timing characteristics are more sensitive to operating

voltage and temperature than in standard iCoupler products.

Refer to Figure 21 through Figure 28 for the expected variation

of these parameters.

Propagation delay is a parameter defined as the time it takes a

logic signal to propagate through a component. The input-to-

output propagation delay time for a high-to-low transition can

differ from the propagation delay time of a low-to-high transition.

Rev. E | Page 20 of 25

Data Sheet

ADuM1440/ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447

Low Power Operating Mode

The pulses at the transformer output have an amplitude greater

than 1.0 V. The decoder has a sensing threshold at about 0.5 V, thus

establishing a 0.5 V margin in which induced voltages can be

The ADuM1440/ADuM1441/ADuM1442/ADuM1445/

ADuM1446/ADuM1447 allow the refresh and watchdog

functions to be disabled by pulling EN₁and EN₂to logic high for

the lowest power consumption. These control pins must be set to

the same value on each side of the component for proper operation.

tolerated. The voltage induced across the receiving coil is given by

2

V = (−dβ/dt) ∑ π r_n; n = 1, 2, … , N

where:

In this mode, the current consumption of the chip drops to the

microamp range. However, be careful when using this mode

because dc correctness is no longer guaranteed at startup. For

example, if the following sequence of events occurs:

β is magnetic flux density (gauss).

r_nis the radius of the n^thturn in the receiving coil (cm).

N is the number of turns in the receiving coil.

Given the geometry of the receiving coil in the ADuM1440/

ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447

and an imposed requirement that the induced voltage be, at most,

50% of the 0.5 V margin at the decoder, a maximum allowable

magnetic field at a given frequency can be calculated. The result

is shown in Figure 32.

1. Power is applied to Side 1

2. A high level is asserted on the V_IAinput

3. Power is applied to Side 2

The high on V_IAis not automatically transferred to the Side 2

V_OA, and there can be a level mismatch that is not corrected until a

transition occurs at V_IA. After power is stable on each side and a

transition occurs on the input of the channel, that channel’s input

and output state is correctly matched. This contingency can be

addressed in several ways, such as sending dummy data, or toggling

refresh on for a short period to force synchronization after turn on.

1000

100

10

Recommended Input Voltage for Low Power Operation

1

The ADuM1440/ADuM1441/ADuM1442/ADuM1445/

ADuM1446/ADuM1447 implement Schmitt trigger input buffers

so that the devices operate cleanly in low data rate or noisy

environments. Schmitt triggers allow a small amount of shoot

through current when their input voltage is not approximate to

either V_DDxor GND_xlevels. This is because the two transistors are

both slightly on when input voltages are in the middle of the supply

range. For many digital devices, this leakage is not a large portion

of the total supply current and may not be noticed; however, in

the ultralow power ADuM1440/ADuM1441/ADuM1442/

ADuM1445/ADuM1446/ADuM1447, this leakage can be larger

than the total operating current of the device and cannot be

ignored.

0.1

0.01

0.001

1k

10k

100k

1M

10M

100M

MAGNETIC FIELD FREQUENCY (Hz)

Figure 32. Maximum Allowable External Magnetic Flux Density

For example, at a magnetic field frequency of 1 MHz, the

maximum allowable magnetic field of 0.5 kgauss induces a

voltage of 0.25 V at the receiving coil. This is about 50% of the

sensing threshold and does not cause a faulty output transition.

Similarly, if such an event occurred during a transmitted pulse

(and was of the worst-case polarity), it would reduce the received

pulse from >1.0 V to 0.75 V, still well above the 0.5 V sensing

threshold of the decoder.

To achieve optimum power consumption with the ADuM1440/

ADuM1441/ADuM1442/ADuM1445/ADuM1446/ ADuM1447,

always drive the inputs as near to V_DDxor GND_xlevels as possible.

Figure 19 and Figure 20 illustrate the shoot through leakage of

an input; therefore, whereas the logic thresholds of the input are

standard CMOS levels, optimum power performance is achieved

when the input logic levels are driven within 0.5 V of either

The preceding magnetic flux density values correspond to specific

current magnitudes at given distances from the ADuM1440/

ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447

transformers. Figure 33 shows these allowable current magnitudes

as a function of frequency for selected distances. As shown, the

ADuM1440/ADuM1441/ADuM1442/ADuM1445/ADuM1446/

ADuM1447 are extremely immune and can be affected only by

extremely large currents operating at a high frequency very near

to the component. For the 1 MHz example noted previously, a

1.2 kA current would have to be placed 5 mm away from the

ADuM1440/ADuM1441/ADuM1442/ADuM1445/ADuM1446/

ADuM1447 to affect the operation of the component.

V_DDxor GND_xlevels.

MAGNETIC FIELD IMMUNITY

The magnetic field immunity of the ADuM1440/ADuM1441/

ADuM1442/ADuM1445/ADuM1446/ADuM1447 is determined

by the changing magnetic field, which induces a voltage in the

receiving coil of the transformer large enough to either falsely

set or reset the decoder. The following analysis defines the

conditions under which this can occur. The 3.3 V operating

condition of the ADuM1440/ADuM1441/ADuM1442/

ADuM1445/ADuM1446/ADuM1447 is examined because it

represents the most typical mode of operation.

Rev. E | Page 21 of 25

ADuM1440/ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447

Data Sheet

1000

The ADuM1440/ADuM1441/ADuM1442/ADuM1445/

ADuM1446/ADuM1447 devices are intended to operate at an

ultralow current. This is achieved by operating the part at a low

average data rate, either by bursting data at high speed at a low

duty factor or by running low bit rates. If data is burst at high

data rates, the part sits quiescent for the majority of the time, at

low data rates, the power consumption approaches the

100

10

1

quiescent power consumption. Table 25 shows the typical

current for an input and output channel pair as well as the total

power dissipated for that channel. The total power is summed

across both sides of the device, so the power is being drawn

from two different supplies. However, it shows how the power

depends on the V_DDvalues and the state of the refresh.

0.1

0.01

DISTANCE = 5mm

DISTANCE = 100mm

DISTANCE = 1m

1k

10k

100k

1M

10M

100M

MAGNETIC FIELD FREQUENCY (Hz)

Figure 33. Maximum Allowable Current for Various Current-to-ADuM1440/

ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447 Spacings

Table 25. Typical Total Power Dissipation Per Channel

Typical Input

Channel

Typical Output

Channel

Note that at combinations of strong magnetic field and high

frequency, any loops formed by PCB traces can induce error

voltages sufficiently large enough to trigger the thresholds of

succeeding circuitry. Take care in the layout of such traces to

avoid this possibility.

State of

Refresh

V_DDI

I_DDI(Q)

V_DDO

I_DDO(Q)

Power/Ch

7.8 µW

Enabled

2.5 V

3.3 V

2.5 V

3.3 V

2.6 µA

4.8 µA

2.5 V

3.3 V

0.5 µA

0.8 µA

0.05 µA

0.13 µA

18.5 µW

0.3 µW

Disabled

0.05 µA 2.5 V

0.12 µA 3.3 V

POWER CONSUMPTION

0.8 µW

The supply current at a given channel of the ADuM1440/

ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447

isolator is a function of the supply voltage, the data rate of the

channel, and the output load of the channel.

INSULATION LIFETIME

All insulation structures eventually break down when subjected

to voltage stress over a sufficiently long period. The rate of

insulation degradation is dependent on the characteristics of the

voltage waveform applied across the insulation. In addition to

the testing performed by the regulatory agencies, Analog Devices

carries out an extensive set of evaluations to determine the

lifetime of the insulation structure within the ADuM1440/

ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447.

For each input channel, the supply current is given by

I

_DDI= I_{DDI (Q)}

f ≤ 0.5 f_r

f > 0.5 f_r

I_DDI= I_{DDI (D)}× (2f − f_r) + I_{DDI (Q)}

For each output channel, the supply current is given by

_DDO= I_{DDO (Q)}f ≤ 0.5 f_r

_DDO= (I_{DDO (D)}+ (0.5 × 10⁻³) × C_L× V_DDO) × (2f − f_r) + I_{DDO (Q)}

f > 0.5 f_r

I

Analog Devices performs accelerated life testing using voltage levels

higher than the rated continuous working voltage. Acceleration

factors for several operating conditions are determined. These

factors allow calculation of the time to failure at the actual

working voltage. The values shown in Table 20 summarize the

peak voltage for 50 years of service life for a bipolar ac operating

condition and the maximum CSA approved working voltages.

In many cases, the approved working voltage is higher than the

50-year service life voltage. Operation at these high working

voltages can lead to shortened insulation life, in some cases.

where:

_{DDI (D)}, I_{DDO (D)}are the input and output dynamic supply currents

per channel (mA/Mbps).

_{DDI (Q)}, I_{DDO (Q)}are the specified input and output quiescent

I

supply currents (mA).

f is the input logic signal frequency (MHz); it is half the input

data rate, expressed in units of Mbps.

f_ris the input stage refresh rate (Mbps).

C_Lis the output load capacitance (pF).

The insulation lifetime of the ADuM1440/ADuM1441/

ADuM1442/ADuM1445/ADuM1446/ADuM1447 depends on

the voltage waveform type imposed across the isolation barrier.

The iCoupler insulation structure degrades at different rates

depending on whether the waveform is bipolar ac, unipolar ac,

or dc. Figure 34, Figure 35, and Figure 36 illustrate these

different isolation voltage waveforms.

V_DDOis the output supply voltage (V).

To calculate the total V_DD1and V_DD2supply current, the supply

currents for each input and output channel corresponding to

V

_DD1and V_DD2are calculated and totaled. Figure 11 through

Figure 18 show per channel supply currents as a function of

data rate for an unloaded output condition.

Bipolar ac voltage is the most stringent environment. The goal

of a 50-year operating lifetime under the ac bipolar condition

determines the Analog Devices recommended maximum

working voltage.

Rev. E | Page 22 of 25

Data Sheet

ADuM1440/ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447

In the case of unipolar ac or dc voltage, the stress on the insulation

is significantly lower. This allows operation at higher working

voltages while still achieving a 50-year service life. The working

voltages listed in Table 20 can be applied while maintaining the

50-year minimum lifetime provided the voltage conforms to

either the unipolar ac or dc voltage case. Treat any cross-insulation

voltage waveform that does not conform to Figure 35 or Figure 36

as a bipolar ac waveform, and limit its peak voltage to the 50-year

lifetime voltage value listed in Table 20.

RATED PEAK VOLTAGE

0V

Figure 34. Bipolar AC Waveform

RATED PEAK VOLTAGE

0V

Figure 35. Unipolar AC Waveform

Note that the voltage presented in Figure 35 is shown as sinusoidal

for illustration purposes only. It is meant to represent any voltage

waveform varying between 0 V and some limiting value. The

limiting value can be positive or negative, but the voltage cannot

cross 0 V.

RATED PEAK VOLTAGE

0V

Figure 36. DC Waveform

Rev. E | Page 23 of 25

ADuM1440/ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447

Data Sheet

OUTLINE DIMENSIONS

0.197 (5.00)

0.193 (4.90)

0.189 (4.80)

16

1

9

8

0.158 (4.01)

0.154 (3.91)

0.150 (3.81)

0.244 (6.20)

0.236 (5.99)

0.228 (5.79)

0.010 (0.25)

0.006 (0.15)

0.020 (0.51)

0.010 (0.25)

0.069 (1.75)

0.053 (1.35)

0.065 (1.65)

0.049 (1.25)

0.010 (0.25)

0.004 (0.10)

0.041 (1.04)

REF

SEATING

PLANE

8°

0°

0.025 (0.64)

BSC

0.050 (1.27)

0.016 (0.41)

COPLANARITY

0.004 (0.10)

0.012 (0.30)

0.008 (0.20)

COMPLIANT TO JEDEC STANDARDS MO-137-AB

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS

(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

Figure 37. 16-Lead Shrink Small Outline Package [QSOP]

(RQ-16)

Dimensions shown in inches and (millimeters)

7.50

7.20

6.90

11

20

5.60

5.30

5.00

8.20

7.80

7.40

1

10

0.25

0.09

1.85

1.75

1.65

2.00 MAX

8°

4°

0°

0.95

0.75

0.55

0.38

0.22

0.05 MIN

SEATING

PLANE

COPLANARITY

0.10

0.65 BSC

COMPLIANT TO JEDEC STANDARDS MO-150-AE

Figure 38. 20-Lead Shrink Small Outline Package [SSOP]

(RS-20)

Dimensions shown in millimeters

Rev. E | Page 24 of 25

Data Sheet

ADuM1440/ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447

ORDERING GUIDE

Number

Maximum Default Maximum

of Inputs, of Inputs, Data Rate Output Propagation

Temperature

Delay, 3.3 V (ns) Range

Package

Description

Package

Option

Model^{1, 2}

V_DD1Side

V_DD2Side

(Mbps)

State

High

Low

ADuM1440ARQZ

ADuM1441ARQZ

ADuM1442ARQZ

ADuM1445ARQZ

ADuM1446ARQZ

ADuM1447ARQZ

ADuM1440ARSZ

ADuM1441ARSZ

ADuM1442ARSZ

ADuM1445ARSZ

ADuM1446ARSZ

ADuM1447ARSZ

EVAL-ADUM1441EBZ

4

3

2

4

3

2

4

3

2

4

3

2

0

1

2

0

1

2

0

1

2

0

1

2

180

−40°C to +125°C 16-Lead QSOP RQ-16

Low

High

Low

−40°C to +125°C 20-Lead SSOP

RS-20

Evaluation

Board

¹Z = RoHS Compliant Part.

²Tape and reel is available. The addition of the –RL7 suffix indicates that the product is shipped on 7” tape and reel.

registered trademarks are the property of their respective owners.

D11845-0-1/17(E)

Rev. E | Page 25 of 25


型号：	ADUM1440ARSZ
厂家：	ADI
描述：	Micropower Quad-Channel Digital Isolator, Default High (4/0 Channel Directionality) 光电二极管接口集成电路
文件：	总25页 (文件大小：458K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADUM1440ARSZ [ADI]

相关型号：

ADUM1440ARSZ-RL7

ADUM1441

ADuM1441ARQZ

ADUM1441ARQZ-RL7

ADUM1442

ADuM1442ARQZ

ADUM1442ARQZ-RL7

ADUM1442ARSZ

ADUM1442ARSZ-RL7

ADUM1445

ADuM1445ARQZ

ADUM1445ARQZ-RL7