ADUM4138 [ADI]
High Voltage, Isolated IGBT Gate Driver with Isolated Flyback Controller;
| 型号： | ADUM4138 |
| 厂家： | 
ADI |
| 描述： | High Voltage, Isolated IGBT Gate Driver with Isolated Flyback Controller 栅 双极性晶体管 |
| 文件： | 总24页 (文件大小：579K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
High Voltage, Isolated IGBT Gate Driver
with Isolated Flyback Controller
ADuM4138
Data Sheet
and low voltage domains of the chip. Information on the status
of the chip can be read back from the dedicated outputs.
FEATURES
6 A (typical) peak drive output capability
Internal turn off NFET, on resistance: <1 Ω
Internal turn on PFET, on resistance: <1.2 Ω
2 overcurrent protection methods
Desaturation detection
Split emitter overcurrent detection
Miller clamp output with gate sense input
Isolated fault output
The ADuM4138 includes an isolated flyback controller,
allowing simple secondary voltage generation.
Overcurrent detection is integrated in the ADuM4138 to
protect the IGBT in case of desaturation and/or overcurrent
events. The overcurrent detection is coupled with a high speed,
two-level turn off function in case of faults.
The ADuM4138 provides a Miller clamp control signal for a
metal-oxide semiconductor field effect transistor (MOSFET) to
provide IGBT turn off, with a single rail supply when the Miller
clamp voltage threshold drops below 2 V (typical) above GND2.
Operation with unipolar secondary supplies is possible with or
Isolated temperature sensor readback
Propagation delay
Rising: 95 ns typical
Falling: 100 ns typical
Minimum pulse width: 74 ns
without the Miller clamp operation.
Operating junction temperature range: −40°C to +150°C
V
DD1 and VDD2 UVLO
A low gate voltage detection circuit can trigger a fault if the gate
voltage does not rise above the internal threshold within the
time allowed after turn on (12.8 µs typical). The low voltage
detection circuit detects IGBT device failures that exhibit gate
shorts or other causes of weak drive.
Minimum external tracking (creepage): 8.3 mm (pending)
Safety and regulatory approvals
5000 V rms for 1 minute per UL 1577
CSA Component Acceptance Notice 5A
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
Two temperature sensor pins, TS1 and TS2, allow isolated
monitoring of system temperatures at the IGBTs. The secondary
undervoltage lockout (UVLO) is set to 11.2 V (typical) in
accordance with common IGBT threshold levels.
V
IORM = 849 VPEAK (reinforced/basic)
Qualified for automotive applications
APPLICATIONS
MOSFET and IGBT gate drivers
Photovoltaic (PV) inverters
Motor drives
A serial peripheral interface (SPI) bus on the primary side of
the device provides in field programming of temperature
sensing diode gains and offsets to the ADuM4138. Values are
stored on an electrically erasable programmable read-only
memory (EEPROM) located on the secondary side of the device.
In addition, programming is available for specific VDD2 voltages,
temperature sensing reporting frequencies, and overcurrent
blanking times.
Power supplies
GENERAL DESCRIPTION
The ADuM4138 is a single-channel gate driver optimized for
driving insulated gate bipolar transistors (IGBTs). Analog
Devices, Inc., iCoupler® technology provides isolation between
the input signal and the output gate drive.
The ADuM4138 provides isolated fault reporting for overcurrent
events, remote temperature overheating events, UVLO, thermal
shutdown (TSD), and desaturation detection.
The Analog Devices chip scale transformers also provide isolated
communication of control information between the high voltage
Protected by U.S. Patents 5,952,849; 6,873,065; and 7,075,329. Other patents pending.
Rev. A
Document Feedback
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rightsof third parties that may result fromits use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2018–2019 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
ADuM4138
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Theory of Operation ...................................................................... 13
Applications Information .............................................................. 14
PCB Layout ................................................................................. 14
Isolated Flyback Controller....................................................... 14
SPI and EEPROM Operation.................................................... 14
User Register Map...................................................................... 15
User Register Bits ....................................................................... 15
Configuration Register Bits....................................................... 15
Control Register Bits.................................................................. 17
Propagation Delay Related Parameters ................................... 18
Protection Features .................................................................... 18
Power Dissipation....................................................................... 22
Insulation Lifetime..................................................................... 22
DC Correctness and Magnetic Field Immunity..................... 23
Typical Application Circuit....................................................... 23
Outline Dimensions....................................................................... 24
Ordering Guide .......................................................................... 24
Automotive Products................................................................. 24
Applications....................................................................................... 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Functional Block Diagram .............................................................. 3
Specifications..................................................................................... 4
Electrical Characteristics............................................................. 4
SPI Timing Specifications ........................................................... 7
Package Characteristics ............................................................... 7
Regulatory Information (Pending) ............................................ 8
Insulation and Safety-Related Specifications............................ 8
DIN V VDE V 0884-10 (VDE V 0884-10) Insulation
Characteristics (Pending)............................................................ 9
Recommended Operating Conditions ...................................... 9
Absolute Maximum Ratings.......................................................... 10
Thermal Resistance .................................................................... 10
ESD Caution................................................................................ 10
Pin Configuration and Function Descriptions........................... 11
Typical Performance Characteristics ........................................... 12
REVISION HISTORY
8/2019—Rev. 0 to Rev. A
Changes to Figure 1.......................................................................... 3
Change to Overcurrent Detection Section.................................. 18
Changes to Figure 18...................................................................... 19
Changes to Figure 20...................................................................... 20
Changes to Figure 24...................................................................... 21
Changes to Figure 30...................................................................... 23
12/2018—Revision 0: Initial Version
Rev. A | Page 2 of 24
Data Sheet
ADuM4138
FUNCTIONAL BLOCK DIAGRAM
V
DD2
FLYBACK
CONTROLLER
LOGIC
28
27
ADuM4138
V
DD2
ENCODE
UVLO2
DECODE
VDD2_REF
GND
2
I
DESAT
25
DESAT
DESAT_ERROR
SW
1
FLYBACK
CONTROLLER
LOGIC
V
UVLO1
I_SENSE
Δt = tdDst
UVLO2
I
HYSTERESIS
9V
2
3
I
SENSE
DRIVE
FAULT
GND
1
OC_DET
V
I_SENSE
V
DECODE
ENCODE
ENCODE
24
23
OUT_ON
LOW_T_OP
V
DD1
V
PGOOD
V
DD1
HYSTERESIS
DRIVE
4
V
MILLER_THRESH
DD1
UVLO2
V
OUT_OFF
DRIVE
FAULT
INTERNAL
LDO
REGULATOR
5V
VDD2
UVLO2
TSD
DESAT_ERROR
OC_ERROR
OT_ERROR
VL_ERROR
V5_1
VI+
5
6
DECODE
UVLO1
INTERNAL
LDO
REGULATOR
5V
26 V5_2
FAULT
V5
FAULT
DRIVE
V
22
OC_DET
FAULT
OFF_SOFT
I
NF
VDD2
7
FAIL LATCH
FAULT
LOW_T_OP
ENCODE
DECODE
DECODE
= t
DALM
V
2LEV
DRIVE
VL_ERROR
Δt = t
DVL
21
GATE_SENSE
MILLER_THRESH
V5
TEMP_OUT_PWM
8
9
ENCODE
TEMP_OUT
PGOOD
V
VL
V
MILLER
OC_DET
20
19
MILLER_OUT
OC1
V5
DRIVE
FAULT
LOW_T_OP
I
PG
I
OC1
OC_ERROR
V
LOW_TEMP
Δt = t
dOC
I
OC2
HYSTERESIS
OT_ERROR
18
OC2
SCALING
BLOCK
V
= 2V
V
OC
DD1
Δt = t
dOT
V
UVLO1
OC_OFF
GAIN1
Δt = tV
DD1
I
V
T1
UVLO1
HYSTERESIS
V
17
16
OT
TS1
TS2
V
T_OFFSET1
GAIN2
I
T2
TEMP_OUT_PWM
10
11
12
13
MOSI
MISO
SPI
SAWTOOTH
V
T_OFFSET2
CS
TSD
INTERNAL
SCLK
TEMPERATURE
SENSOR
GAIN1
V
14
GND
T_OFFSET1
1
HYSTERESIS
EEPROM
15 GND
2
GAIN2
V
T_OFFSET2
NOTES
1. VL_ERROR IS THE VOLTAGE LOW ERROR INTERNAL CONNECTION.
2. TEMP_OUT_PWM IS THE TEMPERATURE SENSE INTERNAL CONNECTION.
3. OC_ERROR IS THE OVERCURRENT ERROR INTERNAL CONNECTION.
4. OC_DET IS THE OVERCURRENT DETECTION INTERNAL CONNECTION.
5. VDD2_REF IS THE REFERENCE VOLTAGE FOR V
.
DD2
6. DESAT_ERROR IS THE DESAT DETECTION ERROR INTERNAL CONNECTION.
7. MILLER_THRESH IS THE REFERENCE FOR THE MILLER THRESHOLD ACTIVATION.
8. OT_ERROR IS THE OVERTEMPERATURE ERROR INTERNAL CONNECTION.
9.
10. V
V
IS THE TEMPERATURE SENSE OFFSET VOLTAGE FOR THE TS1 PIN.
IS THE TEMPERATURE SENSE OFFSET VOLTAGE FOR TS2 PIN.
T_OFFSET1
T_OFFSET2
11. I IS THE INTERNAL CURRENT REFERENCE FOR TS1 PIN.
T1
12. I IS THE INTERNAL CURRENT REFERENCE FOR TS2 PIN.
T2
13. V
IS THE OVERCURRENT VOLTAGE OFFSET DUE TO TEMPERATURE RAMP.
OC_OFF
IS THE OVERCURRENT REFERENCE VOLTAGE.
14. V
OC
15. MILLER_THRESH IS THE ACTIVE MILLER CLAMP INTERNAL CONTROL CONNECTION.
16. I
17. I
IS THE OC1 INTERNAL PULL-UP CURRENT SOURCE.
IS THE OC2 INTERNAL PULL-UP CURRENT SOURCE.
OC1
OC2
18. V
19. V
20. V
21. V
IS THE PGOOD VOLTAGE REFERENCE.
PGOOD
IS THE V
UVLO REFERENCE.
IS THE LOW TEMPERATURE OPERATION REFERENCE.
UVLO1
DD1
LOW_TEMP
IS THE TARGET VOLTAGE REFERENCE FOR TWO LEVEL OPERATION.
2LEV
22. LOW_T_OP IS THE LOW TEMPERATURE OPERATION TRIGGER.
Figure 1.
Rev. A | Page 3 of 24
ADuM4138
Data Sheet
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
Low-side voltages referenced to GND1 and high-side voltages referenced to GND2. VDD1 = 12 V, VDD2 = 16 V, TA = −40°C to +125°C, unless
otherwise noted. All minimum and maximum specifications apply over the entire recommended operating junction temperature range,
unless otherwise noted. All typical specifications are at TA = 25°C, VDD1 = 12 V, and VDD2 = 16 V, unless otherwise noted.
Table 1.
Parameter
Symbol
Min
Typ
Max
Unit Test Conditions/Comments
DIGITAL CONVERTER SPECIFICATIONS
High-Side Power Supply
Input Voltage
VDD2
IDD2(Q)
12
25
18
V
mA
Operating without flyback
TS1 = TS2 = open, VI+ = 0 V,
Input Current, Quiescent for VDD2
14
5
V
DD2 = 25 V
V5_2 Regulated Output Voltage
Isolated Flyback
Soft Start
V5_2
4.9
5.1
50
V
tSS
VFB
44
VDD2
ms
V
Output Voltage
VDD2
−
VDD2
+
All FLYBACK_V codes
2.6%
15.6
180
2.5%
16.4
220
16
200
V
kHz
For FLYBACK_V code of 0111
Flyback Operating Frequency
Maximum
fSW
Duty Cycle
On Time
DMAX
tMAX_ON
83.5
4.2
86
4.8
90
5.4
%
µs
Flyback Switch RDSON
Negative Channel Field Effect
Transistor (NFET)
Positive Channel Field Effect
Transistor (PFET)
RDSON_SW_N
RDSON_SW_P
1.6
1.7
3.0
2.8
Ω
Ω
SW current (ISW) = 20 mA
ISW = 20 mA
Logic Supply
VDD1 Input Voltage
V5_1 Regulated Output Voltage
VDD1 Input Current
VDD1
VV5_1
IDD1
6.0
4.9
25
5.1
5.0
V
V
mA
5.0
4.0
No load
TS1 = TS2 = open, VI+ = 0 V,
TEMP_OUT and SW floating,
VDD1 = 25 V, VDD2 = 25 V
Logic Inputs (VI+, MOSI, SCLK, CS)
Input Current
Input Voltage
Logic High
II
0.1
1.0
0.9
µA
VIH
VIL
VHYST
2.5
V
V
V
Logic Low
Logic Input Hysteresis
Logic Output
MISO NFET RDSON
MISO PFET RDSON
MISO PFET High-Z Leakage
UVLO
1.10
RDSON_MISO_N
RDSON_MISO_P
IMISO_LK_P
9
12.5
16
22
20.0
Ω
Ω
µA
MISO current (IMISO) = 5 mA
IMISO = 5 mA
MISO = 5 V
Positive Going Threshold
VDD1
VDD2
VVDD1UV+
VVDD2UV+
4.25
11.6
4.5
11.8
V
V
Negative Going Threshold
VDD1
VDD2
VVDD1UV−
VVDD2UV−
4.0
11.0
4.13
11.2
V
V
Hysteresis
VDD1
VDD2
VVDD1UVH
VVDD2UVH
0.1
0.3
V
V
Rev. A | Page 4 of 24
Data Sheet
ADuM4138
Parameter
PGOOD
Symbol
VPGOOD_R
VPGOOD_F
Min
Typ
Max
Unit Test Conditions/Comments
Threshold Rising
12.4
17.3
11.77
16.64
13.0
18.2
12.3
17.2
14
13.45
18.8
12.75
17.76
24
V
For FLYBACK_V code of 0000
V
V
V
Ω
µA
For FLYBACK_V code of 1111
For FLYBACK_V code of 0000
For FLYBACK_V code of 1111
PGOOD current (IPGSW) =10 mA
PGOOD = 0 V, VDD1 = 12 V
Threshold Falling
Pull-Down NFET Resistance
Pull-Up Current Source
Filter Time
RPGOOD_PD
IPG
66
78
88
Active
Cleared
tPGOOD_FILT1
tPGOOD_FILT2
30
0.5
40
2.25
50
4
µs
µs
FAULT
Pull-Down NFET Resistance
Pull-Up Current Source
Hold Time
RNFLT_PD_FET
INF
16
28
Ω
FAULT current (IFT) = 10 mA
FAULT = 0 V, VDD1 = 12 V
66
78
88
µA
ms
tDALM
23.3
26.4
30.2
Low Gate Voltage
Reference Voltage
Detect Delay Time
Fault Delay Time
Overcurrent
VVL
tDVL
tDVL_FLT
9.6
10.3
530
10
12.8
735
10.4
15.6
940
V
µs
ns
Voltage
Temperature, Disabled
Temperature, Enabled
VOCD_TH
VOCD_TH_EN
2
2.69
1.75
V
V
V
T_RAMP_OP = 1
T_RAMP_OP = 0, TS1 = 1.55 V
T_RAMP_OP = 0, TS1 = 2.45 V
2.59
1.65
2.76
1.82
Hysteresis
Temperature, Disabled
Temperature, Enabled
VOCD_HYST
VOCD_HYST_EN
0.17
0.17
0.17
920
735
0.36
5
V
V
V
ns
ns
µs
µA
T_RAMP_OP = 1
T_RAMP_OP = 0, TS1 = 1.55 V
T_RAMP_OP = 0, TS1 = 2.45 V
OC_2LEV_OP = 0, OC_TIME_OP = 0
OC_2LEV_OP=1
tBLANK bits = 0001
VDD2 = 25 V, OC1 = OC2 = 0 V
Detect Delay Time
Fault Delay Time
Detect Blanking
tdOC
520
510
0.275
3.8
1340
960
0.47
6.2
tdOC_FLT
tBLANK
IOC
Pin Pull-Up Current Source
Desaturation (DESAT) Detect
Comparator Threshold
Rising
Falling
VDESAT_R
VDESAT_F
8.4
7.7
8.9
8.1
9.4
8.5
V
V
Hysteresis
VDESAT_H
IDESAT
tDESAT_DELAY
tDESAT_BLANK
RDSON_DESAT
0.85
490
825
450
14
V
Internal Current Source
Fault Delay Time
FAULT Pin Blank Time
DESAT Pin Pull-Down Resistance
TSD
365
620
300
570
1030
620
28
µA
ns
ns
Ω
DESAT = 0 V
DESAT current (ID) = 10 mA
Primary Side TSD
Positive Edge
Negative Edge
tTSD_POS1
tTSD_NEG1
154
135
°C
°C
Secondary Side TSD
Positive Edge
Negative Edge
tTSD_POS2
tTSD_NEG2
150
130
°C
°C
Isolated Temperature Sensor
Temperature Sense Bias Current Source
IT1
IT2
IT_MATCH
0.938
0.953
1.015
1.03
0.014
1.092
1.107
0.0415
mA
mA
mA
TS1 = 2.2 V
TS2 = 2.2 V
TSx = 2.2 V
Temperature Sense Current Matching
Rev. A | Page 5 of 24
ADuM4138
Data Sheet
Parameter
Symbol
Min
Typ
Max
Unit Test Conditions/Comments
Pulse-Width Modulation (PWM) Output
Frequency
fPWM
9.20
46
10
50
10.80
54
kHz
kHz
PWM_OSC = 0, TSx = 2.2 V
PWM_OSC = 1, TSx = 2.2 V
PWM Duty Cycle
TSx = 2.45 V
TSx = 2.25 V
TSx = 1.55 V
TSx = 2.45 V
7.50
26
90.2
7.5
26
90.1
10
28
92
10
28
92
11.3
29.5
93.3
11.5
29.6
93.3
%
%
%
%
%
%
PWM_OSC = 0
PWM_OSC = 0
PWM_OSC = 0
PWM_OSC = 1
PWM_OSC = 1
PWM_OSC = 1
TSx = 2.25 V
TSx = 1.55 V
Overtemperature
Detect Delay Time
Fault Delay Time
Detection Voltage
Rising
tDOT
tDOT_FLT
0.80
530
1
735
1.2
940
ms
ns
VOT_0_R
VOT_1_R
VOT_0_F
VOT_1_F
1.62
1.63
1.57
1.59
1.69
1.73
1.65
1.69
1.73
1.81
1.70
1.78
V
V
V
V
OT_FAULT_SEL = 0
OT_FAULT_SEL = 1
OT_FAULT_SEL = 0
OT_FAULT_SEL = 1
Falling
Low Temperature Threshold
Rising
Falling
VLOW_T_R
VLOW_T_F
2.35
2.31
2.4
2.36
2.45
2.41
V
V
TS1 pin voltage
TS1 pin voltage
TEMP_OUT Resistance
Pull-Down
Pull-Up
Miller Clamp Voltage Threshold
Internal Turn Off NFET
On Resistance
RTEMP_N
RTEMP_P
VMILLER
11.3
13.7
2
20
23
2.1
Ω
Ω
V
TEMP_OUT current (ITEMP_OUT) = 5 mA
ITEMP_OUT = 5 mA
Referenced to GND2
1.9
RDSON_N
0.5
1.8
1
4
Ω
Ω
VOUT_OFF current (IVOUT_OFF) = 0.5 A,
VDD1 = 6 V, VDD2 = 12 V
On Resistance 2 Level
Internal Turn On PFET
On Resistance
RDSON_N_2LEV
IVOUT_OFF = 0.1 A, VDD1 = 6 V, VDD2 = 12 V
RDSON_P
0.6
2.0
1.2
4
Ω
Ω
VOUT_ON current (IVOUT_ON) = 0.5 A,
V
DD1 = 6 V, VDD2 = 12 V
IVOUT_ON = 0.1 A, VDD1 = 6 V,
DD2 = 12 V
On Resistance 2 Level
RDSON_P_2LEV
V
Miller Pull-Down NFET
VOFF_SOFT RDSON
Peak Current
Two-Level Plateau Voltage
CURRENT LIMIT
RDSON_MILLER
RDSON_SOFT_OFF
IPEAKIP
4.2
15
6
10
36
Ω
Ω
A
V
Miller current (IMILLER) = 10 mA
VOFF_SOFT current (IOFF_SOFT) = 10 mA
VDD2 = 15 V, 2 Ω external resistance
V2LEV
11.30
11.90
12.50
Set Current
II_SENSE
VI_SENSE
tCL_BLANK
18
480
120
20
500
145
22
520
180
µA
mV
ns
ISENSE = 0.5 V
Rising edge
Internal Current-Limit Reference
Current-Limit Blanking Time
SWITCHING SPECIFICATIONS
Pulse Width1
PW
74
ns
No load, Miller clamp open
Propagation Delay
Rising2
Falling2
tDLH
tDHL
71
79
95
100
130
121
ns
ns
No load, Miller clamp open
No load, Miller clamp open
1 The minimum pulse width is the shortest pulse width at which the specified timing parameter is guaranteed.
2 tDLH propagation delay is measured from the time of the input rising logic high threshold, VIH, to the output rising 0% level of the VOUT_ON or VOUT_OFF signal. tDHL
propagation delay is measured from the input falling logic low threshold, VIL, to the output falling 90% threshold of the VOUT_ON or VOUT_OFF signal. See Figure 13 for
waveforms of propagation delay parameters.
Rev. A | Page 6 of 24
Data Sheet
ADuM4138
SPI TIMING SPECIFICATIONS
SPI timing specifications are guaranteed by design. All devices are production tested with 200 kHz SPI communication.
Table 2.
Parameter
Description
Min
8
1
1
5
Typ
Max
Unit
µs
µs
µs
µs
tS
Time to first clock edge
Set period
Hold period
Clock period
Release time
tDS
tDH
tCLK
tH
8
µs
tHIGH
tLOW
tOV
Clock time high
Clock time low
Output valid time
100
100
ns
ns
ns
240
SPI Timing Diagram
tDS
tHIGH
tLOW
tCLK
tH
tDH
tS
CS
SCLK DON’T CARE
DON’T CARE
DON’T CARE
MBZ RW0
A1
A0
MBZ MBZ MBZ MBZ
D23
D5
D4
D3
D1
D0
MOSI
MISO
DON’T CARE
HIGH-Z
tOV
0
RW0′ A1′
A0′
0
0
0
0
D23′
D5′
D4′
D3′
D1′
D0′
DON’T CARE
Figure 2. SPI Timing Diagram
PACKAGE CHARACTERISTICS
Table 3.
Parameter
Resistance (Input Side to High-Side Output)1
Capacitance (Input Side to High-Side Output)1
Input Capacitance
Symbol
Min
Typ
1012
2
Max
Unit
Ω
pF
RI-O
CI-O
CI
4
pF
1 The device is considered a two terminal device: Pin 1 through Pin 14 are shorted together, and Pin 15 through Pin 28 are shorted together.
Rev. A | Page 7 of 24
ADuM4138
Data Sheet
REGULATORY INFORMATION (PENDING)
Table 4.
UL (Pending)
CSA (Pending)
VDE (Pending)
CQC (Pending)
UL1577 Component
Recognition Program
Approved under CSA Component
Acceptance Notice 5A
DIN V VDE V 0884-10
(VDE V 0884-10):2006-12
Certified under
CQC11-471543-2012
Single Protection, 5000 V rms
Isolation Voltage
CSA 60950-1-07+A1+A2 and
IEC 60950-1, second edition, +A1+A2:
Reinforced insulation, 849 VPEAK
VIOTM = 8 kVPEAK
,
GB4943.1-2011
Basic insulation at 830 V rms
Basic insulation, 830 V rms
(1174 VPEAK
Reinforced insulation at 415 V rms
(587 VPEAK
)
(1174 VPEAK
Reinforced insulation,
415 V rms (587 VPEAK
)
)
)
IEC 60601-1 Edition 3.1:
Basic insulation (1 MOPP),
519 V rms (734 VPEAK
Reinforced insulation (2 MOPP),
261 V rms (369 VPEAK
)
)
CSA 61010-1-12 and IEC 61010-1
third edition
Basic insulation, 300 V rms mains,
830 V secondary (1174 VPEAK
)
Reinforced insulation, 300 V rms
mains, 415 V secondary (587 VPEAK
)
File E214100
File 205078
File 2471900-4880-0001
File (pending)
INSULATION AND SAFETY-RELATED SPECIFICATIONS
Table 5.
Parameter
Symbol
Value
5000
8.3
Unit
Test Conditions/Comments
Rated Dielectric Insulation Voltage
Minimum External Air Gap (Clearance)
V rms
1 minute duration
L (I01)
L (I02)
L (PCB)
mm min Measured from input terminals to output
terminals, shortest distance through air
mm min Measured from input terminals to output
terminals, shortest distance path along body
mm min Measured from input terminals to output
terminals, shortest distance through air,
Minimum External Tracking (Creepage)
8.3
8.7
Minimum Clearance in the Plane of the Printed
Circuit Board (PCB Clearance)
line of sight, in the PCB mounting plane
Minimum Internal Gap (Internal Clearance)
Tracking Resistance (Comparative Tracking Index)
Material Group
0.017
>400
II
mm min Insulation distance through insulation
CTI
V
DIN IEC 112/VDE 0303 Part 1
Material group (DIN VDE 0110, 1/89, Table 1)
Rev. A | Page 8 of 24
Data Sheet
ADuM4138
DIN V VDE V 0884-10 (VDE V 0884-10):2016-12 INSULATION CHARACTERISTICS (PENDING)
These isolators are suitable for reinforced isolation only within the safety limit data. Protective circuits ensure the maintenance of the
safety data. The asterisk (*) marking on the package denotes DIN V VDE V 0884-10 approval for a 560 VPEAK working voltage.
Table 6. VDE Characteristics
Description
Test Conditions/Comments
Symbol Characteristic Unit
Installation Classification per IEC 60664-1
For Rated Mains Voltage ≤ 150 V rms
For Rated Mains Voltage ≤ 300 V rms
For Rated Mains Voltage ≤ 600 V rms
Climatic Classification
Pollution Degree per DIN VDE 0110, Table 1
Maximum Working Insulation Voltage
Input to Output Test Voltage, Method B1
I to IV
I to IV
I to IV
40/125/21
2
VIORM
Vpd(m)
849
1592
VPEAK
VPEAK
VIORM × 1.875 = Vpd(m), 100% production test,
t
ini = tm = 1 sec, partial discharge < 5 pC
Input to Output Test Voltage, Method A
After Environmental Tests Subgroup 1
After Input and/or Safety Test
Subgroup 2 and Subgroup 3
VIORM × 1.5 = Vpd(m), tini = 60 sec, tm = 10 sec,
partial discharge < 5 pC
Vpd(m)
1274
1019
VPEAK
VPEAK
VIORM × 1.2 = Vpd(m), tini = 60 sec, tm = 10 sec,
partial discharge < 5 pC
Highest Allowable Overvoltage
Impulse
VIOTM
VIMPULSE
8000
8000
VPEAK
VPEAK
1.2 µs rise time, 50 µs, 50% fall time in air to the
preferred sequence
Surge Isolation Voltage Basic
Surge Isolation Voltage Reinforced
Safety Limiting Values
VPEAK = 12.8 kV, 1.2 µs rise time, 50 µs, 50% fall time
VPEAK = 12.8 kV, 1.2 µs rise time, 50 µs, 50% fall time
Maximum value allowed in the event of a
failure (see Figure 3)
VIOSM
VIOSM
9800
8000
VPEAK
VPEAK
Maximum Junction Temperature
Total Power Dissipation at TA = 25°C
Insulation Resistance at TS
TS
PS
RS
150
2.0
>109
°C
W
Ω
Voltage between the input and output (VIO) = 500 V
2.5
2.0
1.5
1.0
0.5
0
RECOMMENDED OPERATING CONDITIONS
Table 7.
Parameter
Value
Operating Junction Temperature Range −40°C to +150°C
Supply Voltages
VDD1 Referenced to GND1
VDD2 Referenced to GND2
6.0 V to 25 V
12 V to 25 V
0
50
100
150
200
AMBIENT TEMPERATURE (°C)
Figure 3. Thermal Derating Curve, Dependence of Safety Limiting Values on
Case Temperature, per DIN V VDE V 0884-10
Rev. A | Page 9 of 24
ADuM4138
Data Sheet
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 8.
Thermal performance is directly linked to PCB design and
operating environment. Careful attention to PCB thermal
design is required.
Parameter
Supply Voltages
VDD1
Rating
−0.2 V to +30 V
−0.2 V to +30 V
VDD2
θ
JA is the junction to ambient thermal resistance, and ΨJT is the
Primary Side Pins
VI+, MOSI, CS, SCLK
junction to top characterization parameter.
−0.2 V to +5.5 V
Table 9. Thermal Resistance
Package Type1
SW, ISENSE, FAULT, TEMP_OUT,
PGOOD, MISO
−0.2 V to V5_1 + 0.2 V
θJA
ΨJT
Unit
Secondary Side Pins
TS1, TS2
MILLER_OUT, VOFF_SOFT, VOUT_OFF
RN-28-1
62.4
2.97
°C/W
−0.2 V to V5_2 + 0.2 V
−0.2 V to + 30 V
1 4-layer PCB.
VOUT_ON, DESAT, GATE_SENSE,
OC1, OC2
Common-Mode Transients (|CM|)
Storage Temperature Range (TST)
−0.2 V to VDD2 + 0.2 V
ESD CAUTION
−150 kV/µs to +150 kV/µs
−55°C to +150°C
Operating Junction Temperature
Range
−40°C to +150°C
Electrostatic Discharge (ESD)
Human Body Model (HBM)
Charge Device Model (CDM)
1 kV
1.25 kV
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Table 10. Maximum Continuous Working Voltage1, 2, 3
Parameter
Rating
Constraint
AC Voltage
Bipolar Waveform
Basic Insulation
Reinforced Insulation
Unipolar Waveform
Basic Insulation
Reinforced Insulation
DC Voltage
849 VPEAK
707 VPEAK
Lifetime limited by insulation lifetime per VDE-0884-11
Lifetime limited by insulation lifetime per VDE-0884-11
1697 VPEAK
892 VPEAK
Lifetime limited by insulation lifetime per VDE-0884-11
Lifetime limited by package creepage per IEC 60664-1
Basic Insulation
Reinforced Insulation
1092 VPEAK
546 VPEAK
Lifetime limited by package creepage per IEC 60664-1
Lifetime limited by package creepage per IEC 60664-1
1 See the Insulation Lifetime section for details.
2 Other pollution degree and material group requirements yield a different limit.
3 Some system level standards allow components to use the printed wiring board (PWB) creepage values. The supported dc voltage may be higher for those standards.
Table 11. Truth Table (Positive Logic)
Pin
FAULT
High
High
Low
VI+ Input
VDD1 State
Powered
Powered
Powered
Unpowered
Powered
VDD2 State
Powered
Powered
Powered
Powered
Unpowered
GATE_SENSE Voltage (VGATE_SENSE)
Low
High
Low
High
Low
Low
High-Z
Don’t Care or Unknown
Don’t Care or Unknown
Don’t Care or Unknown
Don’t care or unknown
Low
Rev. A | Page 10 of 24
Data Sheet
ADuM4138
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
SW
V
DD2
I
GND
SENSE
2
3
GND
1
V5_2
4
V
DESAT
DD1
5
V5_1
VI+
V
V
V
OUT_ON
6
OUT_OFF
OFF_SOFT
ADuM4138
7
FAULT
TEMP_OUT
PGOOD
MOSI
TOP VIEW
8
GATE_SENSE
MILLER_OUT
OC1
(Not to Scale)
9
10
11
12
13
14
MISO
OC2
CS
TS1
TS2
SCLK
GND
2
GND
1
Figure 4. Pin Configuration
Table 12. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
2
3
4
5
SW
ISENSE
GND1
VDD1
V5_1
Switching Signal Pin for Isolated Flyback Converter. Connect this pin to the flyback transformer MOSFET.
Flyback Current Sense. Current sense node for flyback transistor.
Ground Reference for Primary Side. Decouple this pin to VDD1.
Input Supply Voltage Pin on Primary Side, 6 V to 25 V Referenced to GND1.
5 V Regulated Output. Connect this pin to a 1 µF external capacitor referenced to GND1. This pin controls the
logic levels for the input pins.
6
7
VI+
FAULT
Noninverting Input for Gate Drive. Connect this pin to the incoming PWM control signal.
Fault Reporting Pin. The FAULT pin goes low when an overcurrent event is detected by the overcurrent pin,
desaturation is detected, secondary UVLO occurs during thermal shutdown, during remote sensing
overtemperature, or during gate voltage low errors.
8
9
TEMP_OUT
PGOOD
Remote Temperature Sense Reporting Pin. This pin is 10 kHz or 50 kHz and is the 5% to 95% PWM output for
the diode temperature sensor.
Power Good Pin. The signal is high when the output voltage is within regulation. When not in use, leave this
pin open.
10
11
12
13
14
15
16
17
18
19
20
21
22
MOSI
MISO
CS
Master Out, Slave In Pin. This pin provides the MOSI connection for the SPI bus.
Master In, Slave Out Pin. This pin provides the MISO connection for the SPI bus.
Chip Select for SPI Bus. Logic is active low.
SCLK
GND1
GND2
TS2
TS1
OC2
OC1
Clock for SPI Bus. Connect this pin to the clock pin from the SPI master.
Ground Reference for Primary Side.
Secondary Ground Reference. Use this ground pin for the high current path.
Remote Temperature Sensor 2. Float or pull this pin high to V5_2 when not in use.
Remote Temperature Sensor 1. See the Applications Information section for more information if this pin is unused.
Split Emitter Overcurrent Detection 2. Connect this pin to GND2 when this pin is not in use.
Split Emitter Overcurrent Detection 1. Connect this pin to GND2 when this pin is not in use.
MILLER_OUT Output Signal to Control External MOSFET for Miller Clamping.
GATE_SENSE Miller Clamping Sense Pin. Connect this pin directly to the gate of the IGBT.
VOFF_SOFT
VOUT_OFF
VOUT_ON
Soft Shutdown Gate Connection. Connect this pin to the gate through the external series resistor. This pin
pulls the gate down during fault conditions.
Turns Off Current Path Connection. Connect this pin to the gate through the external series resistor. This pin
pulls the gate down during the low output command.
Turns On Current Path Connection. Connect this pin to the gate through the external series resistor. This pin
pulls the gate up during the high output command.
23
24
25
26
27
28
DESAT
V5_2
GND2
VDD2
Desaturation Detection Pin. Connect this pin to GND2 when not in use.
5 V Regulated Output on Secondary Side. Connect this pin to the 1 µF external capacitor referenced to GND2.
Ground Reference for Secondary Side.
Input Supply Voltage on Secondary Side, 15 V (Typical) Referenced to GND2.
Rev. A | Page 11 of 24
ADuM4138
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
T
T
VI+
1
DESAT
FAULT
1
3
GATE_SENSE
2
2
GATE_SENSE
CH1 5.00V CH2 5V
500ns/DIV 5.0GSPS
A
CH1
3.3V
CH1 5.0V
CH3 5.0V
CH2 5.0V 10µs/DIV 5.0GSPS
A
CH3
1.8V
200ps PER POINT
200ps PER POINT
Figure 5. Example Turn On Edge, VDD1 = 12 V, VDD2 = 16 V,
3 Ω Turn On, 100 nF Load
Figure 8. Example DESAT Fault, VDD1 = 12 V, VDD2 = 16 V, VI+ = 5 V,
2 Ω Turn Off, 100 nF Load
T
T
V
DD1
VI+
1
1
3
FAULT
V
DD2
GATE_SENSE
2
2
CH1 5.00V CH2 5V
500ns/DIV 5.0GSPS
A
CH1
3.3V
CH1 10.0V CH2 10.0V 5ms/DIV 5.0MSPS
CH3 5.0V 500ns PER POINT
A
CH1
5.4V
200ps PER POINT
Figure 6. Example Turn Off Edge, VDD1 = 12 V, VDD2 = 16 V,
2 Ω Turn Off, 100 nF Load
Figure 9. Typical Flyback Startup, VDD1 = 12 V
T
T
V
DD1
OC1
1
3
1
3
FAULT
FAULT
TEMP_OUT
4
2
V
DD2
GATE_SENSE
2
CH1 3.0V
CH3 5.0V
CH2 5.0V 5µs/DIV
5.0GSPS
200ps PER POINT
A
CH3
1.8V
CH1 10.0V CH2 10.0V 50µs/DIV 200MSPS
CH3 5.0V CH4 5.0V 5.0ns PER POINT
A
CH4
2.2V
Figure 7. Example Overcurrent Fault, VDD1 = 12 V, VDD2 = 16 V,
VI+ = 5 V, 2 Ω Turn Off, 100 nF Load
Figure 10. Example TEMP_OUT Reading, VDD1 = 12 V, VDD2 = 16 V
Rev. A | Page 12 of 24
Data Sheet
ADuM4138
THEORY OF OPERATION
Gate drivers are required in situations where fast rise times
of switching device gates are required. The gate signals for
enhancement power devices are referenced to a source or
emitter node. The gate driver must follow this source or emitter
node. As such, isolation is necessary between the controlling
signal and the output of the gate driver in topologies where the
source or emitter nodes swing, such as a half bridge. Gate switching
times are a function of the drive strength of the gate driver.
Buffer stages before a complementary metal-oxide semiconductor
(CMOS) output reduce the total delay time and increase the
final drive strength of the driver.
chip scale transformer coils separated by layers of polyimide
isolation. The ADuM4138 uses positive logic on/off keying
(OOK) encoding, in which a high signal is transmitted by the
presence of the carrier frequency across the iCoupler chip scale
transformer coils. Positive logic encoding ensures that a low
signal is seen on the output when the input side of the gate
driver is unpowered. A low state is the most common safe state
in enhancement mode power devices and can drive in situations
where shoot through conditions are present. The architecture of
the ADuM4138 is designed for high common-mode transient
immunity and high immunity to electrical noise and magnetic
interference. Radiated emissions are minimized with a spread
spectrum OOK carrier and differential coil layout. Figure 11
shows the OOK encoding used by the ADuM4138.
The ADuM4138 achieves isolation between the control side and
the output side of the gate driver using a high frequency carrier
that transmits data across the isolation barrier with iCoupler
REGULATOR
REGULATOR
RECEIVER
TRANSMITTER
V
V
OUT_ON
VI+
OUT_OFF
GND
GND
2
1
Figure 11. Operational Block Diagram of OOK Encoding
Rev. A | Page 13 of 24
ADuM4138
Data Sheet
APPLICATIONS INFORMATION
Peak current mode control is employed on the primary side of
the ADuM4138 through the ISENSE pin. Use the following
equation to set the current limit:
PCB LAYOUT
The ADuM4138 IGBT gate driver requires no external interface
circuitry for the logic interfaces. Power supply bypassing is
required at the VDD1 and VDD2 supply pins. Use a small ceramic
capacitor (>10 µF) from VDD1 to GND1. Add at least 30 µF to
60 µF capacitance on the output power supply pin (VDD2) to
provide the charge required to drive the gate capacitance at the
outputs. This capacitance can be provided by multiple parallel
capacitors. Avoid using vias on VDD2 on the bypass capacitor or
employing multiple vias to reduce the inductance in bypassing
because board vias can introduce parasitic inductance. The total
lead length between both ends of the smaller capacitor and the
input or output power supply pin must not exceed approximately
5 mm. For the 5 V regulators, place 1 µF capacitors as close as
possible to the ADuM4138.
I
PEAK (mA) = 100 mV/RS
where:
PEAK is the desired peak current limit in mA.
RS is the sense resistor used to set the peak current limit in Ω.
(1)
I
A typical application is shown in Figure 30. The recommended
current-limit resistance (RCL) value is 20 kΩ. In operation, the
equation for setting the peak current follows:
VI_SENSE = (II_SENSE) × (RCL) + (IPEAK) × (RS)
(2)
where:
V
I
R
I_SENSE = 500 mV (typical)
I_SENSE = 20 µA (typical)
CL = 20 kΩ (recommended)
ISOLATED FLYBACK CONTROLLER
SPI AND EEPROM OPERATION
SPI Programming
The ADuM4138 has an integrated isolated flyback controller
that delivers isolated power to the gate being driven. The
flyback controller provides a control signal to the flyback
MOSFET on the low side of the device. This MOSFET switches
the primary side of the flyback transformer. An external diode
rectifies the secondary voltage and regulates the internal
compensation on the secondary side. An inductive isolation
link transfers duty cycle information to the primary side.
The ADuM4138 contains an SPI bus for setting remote
temperature gains and offsets, PWM reporting frequency, high
temperature faults, and low temperature operation mode. The
SPI bus allows programming of the secondary side EEPROM,
allowing a permanent operation setting. The SPI interface can
operate in a daisy-chain mode to allow efficient use of the
microcontroller input and output pins. When the chip select
Startup includes a soft start, where the duty cycle is controlled to a
maximum value that increases with time. The primary side has
an oscillator that controls this timing. The secondary side also
has an oscillator, creating the 200 kHz (typical) ramp signal
used to create the PWM control. The handoff between the soft
start and secondary oscillator is controlled internally without
user intervention. An internal resistor network performs
feedback sensing on the VDD2 pin.
CS
(
) pin is brought low, programming of the EEPROM is
available. However, the gate drive output is disabled. The gate
CS
drive output is not available again until is brought back to high.
Programming is performed using the standard SPI convention of
clock polarity (CPOL) = 0 and clock phase (CPHA) = 1. The
SPI timing diagram shown in Figure 2 demonstrates a typical
read or write operation. Bit A1 and Bit A0 are the address bits. The
must be zero (MBZ) bits must be set to 0. Bits[D23:D0] are the
data bits, with MSB first. Bit RW0 sets whether the action is a
read (0) or a write (1).
The power good pin, PGOOD, is available for output on the
primary side, allowing the user to observe when the secondary
voltage is within regulation.
If VDD2 loses power during operation, a fault posts to the
primary side, and the flyback does not automatically attempt
recovery. The VDD1 power cycle initiates the flyback operation
again.
Rev. A | Page 14 of 24
Data Sheet
ADuM4138
USER REGISTER MAP
Figure 12 shows the user register map and binary addresses.
BIT
ADDRESS
00
NAME
USER
23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
OFFSET_2[5:0]
GAIN_2[5:0]
OFFSET_1[5:0]
GAIN_1[5:0]
RESERVED
01
10
CONFIG
CONTROL
RESERVED
Figure 12. User Register Map
Bit Name
Bits
Description
USER REGISTER BITS
OC_BLANK_OP 11
Overcurrent blanking operation select
Overcurrent blanking time
Enable soft shutdown with error
correcting code (ECC) fault
Flyback output voltage setting
Overcurrent temperature ramp enable
Table 13 lists the user register (Address 00) bits and bit
descriptions.
tBLANK[3:0]
[10:7]
ECC_OFF_OP
6
Table 13. User Register (Address 00) Bit Descriptions
FLYBACK_V[3:0] [5:2]
Bits
Bit Name
OFFSET_2[5:0] TS2 offset
GAIN_2[5:0] TS2 gain
OFFSET_1[5:0] TS1 offset
GAIN_1[5:0] TS1 gain
Description
T_RAMP_OP
PWM_OSC
1
0
[23:18]
[17:12]
[11:6]
[5:0]
Temperature reading output
oscillator select
OT_FAULT_OP Bit
Set the OT_FAULT_OP bit to 1 to disable a fault for over-
temperature. If this bit is set to 0, the ADuM4138 issues a fault
when the TS1 or TS2 pin detects an overtemperature event.
OFFSET_2[5:0] Bits
Use the OFFSET_2 bits of the EEPROM to adjust the internal
offset for the TS2 pin.
OT_FAULT_SEL Bit
GAIN_2[5:0] Bits
The OT_FAULT_SEL bit selects between two overtemperature
fault voltage thresholds. Set this bit to 0 to set the falling threshold
to 1.65 V (typical) and the rising threshold is 1.69 V (typical).
Set the OT_FAULT_SEL bit to 1 to set the falling threshold to
1.69 V (typical) and the rising threshold is 1.73 V (typical).
Use the GAIN_2 bits of the EEPROM to adjust the internal gain
for the TS2 pin.
OFFSET_1[5:0] Bits
Use the OFFSET_1 bits of the EEPROM to adjust the internal
offset for the TS1 pin.
OC_TIME_OP Bit
GAIN_1[5:0] Bits
Set the OC_TIME_OP bit to 1 to disable the two-level drive and
timer during an overcurrent event. During an overcurrent
event, the output immediately enters soft shutdown. If enabled,
overcurrent blanking is still available.
Use the GAIN_1 bits of the EEPROM to adjust the internal gain
for the TS1 pin.
CONFIGURATION REGISTER BITS
OC_2LEV_OP Bits
Table 14 lists the configuration (CONFIG) register (Address 01)
bits and bit descriptions.
Set the OC_2LEV_O bit to 1 to disable the two-level drive
during an overcurrent event before a fault registers. After the
overcurrent detection time completes, a fault registers and the
output shuts down using the soft shutdown. If this bit is set to 0
during an overcurrent event, but before tdOC, the two-level drive
level is output to the gate.
Table 14. CONFIG Register (Address 01) Bit Descriptions
Bit Name
Bits
Description
Reserved
[23:17] Reserved
OT_FAULT_OP
OT_FAULT_SEL
OC_TIME_OP
16
15
14
Overtemperature fault disable
Overtemperature fault select
Disable two-level drive and timer
during overcurrent event
OC_2LEV_OP
LOW_T_OP
13
12
Overcurrent two-level operation select
Low temperature operation select
Rev. A | Page 15 of 24
ADuM4138
Data Sheet
LOW_T_OP Bit
FLYBACK_V[3:0] Bits
Bit 12 of the CONFIG register can disable a special low
temperature operation. If the LOW_T_OP bit is set to 0 when
the TS1 pin rises above 2.4 V (typical), the gate voltage goes to
the two-level plateau voltage during an on command. Hysteresis
allows operation down to 2.36 V (typical) on TS1 before the low
temperature operation mode is left. If the LOW_T_OP bit is set
to 1, all nonfault gate signals are at the VDD2 output voltage on
an on signal.
The FLYBACK_V bits in the EEPROM can set the isolated
flyback output voltage. The default code is 0111 (16.00 V target).
Table 16 describes the output voltages available.
Table 16. EEPROM Register Map
FLYBACK_V[3:0]
VDD2 Voltage Setting (V)
0000
0001
0010
0011
0100
0101
0110
0111 (Default)
1000
1001
1010
1011
1100
1101
1110
1111
14.25
14.50
14.75
15.00
15.25
15.50
15.75
16.00
16.25
16.50
16.75
17.00
17.25
17.50
17.75
20.00
OC_BLANK_OP Bit
Set the OC_BLANK_OP bit to 1 to enable the two-level drive
during the current blanking time. When the OC_BLANK_OP
bit is set to 1, it enters the two-level drive in case of an
overcurrent event during the blanking time, tBLANK
.
tBLANK[3:0] Bits
During the initial turn on of a gate, a large amount of noise
caused by switching actions can exist. To account for this noise,
the overcurrent detection can be masked by setting different
tBLANK values. During the masking time, overcurrent events are
ignored.
Table 15. tBLANK Blanking Times
t
BLANK[3:0], Bits[10:7]
Blanking Time (µs) Typical
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0
T_RAMP_OP Bit
0.36
0.56
0.77
0.97
1.17
1.57
1.97
2.37
2.78
3.18
3.58
3.98
4.39
4.79
5.19
Set the T_RAMP_OP bit to 0 to allow the overcurrent reference
voltage to vary with temperature. The current reference varies by
10% across the TS1 voltages of 1.55 V to 2.45 V, as shown in
Figure 14. Set the T_RAMP_OP bit to 1 to have the overcurrent
reference voltage, VOCD_TH, set to 2 V (typical) regardless of the
sensed temperature.
PWM_OSC Bit
The PWM_OSC bit controls whether the reported TEMP_OUT
pin PWM frequency is 10 kHz or 50 kHz. When the PWM_OSC
bit is set to 0, the output frequency is 10 kHz (typical). When
the PWM_OSC bit is set to 1, the PWM output frequency is
50 kHz (typical).
ECC_OFF_OP Bit
If the ECC_OFF_OP bit is set to 1 when an ECC error is
detected, the ADuM4138 enters a soft shutdown and a fault
registers. This fault registers whether a single or double ECC
fault is detected. If this bit is set to 0, ECC faults are set in the
control register (Address 10), but the ADuM4138 continues to
operate without shutting down.
Rev. A | Page 16 of 24
Data Sheet
ADuM4138
ECC1_SNG_ERR Bit
CONTROL REGISTER BITS
When a single error is detected in the EEPROM stored data, the
ECC1_SNG_ERR bit is set to 1 when read. The error correcting
code employed by the ADuM4138 can detect and correct a
single error. The ECC2_SNG_ERR bit set to 1 indicates that a
single error is detected in the memory banks, representing trim
performed on the ADuM4138 by the user and configuration
(CONFIG) addresses. A value of 0 indicates no single bit error
was detected.
Table 17 lists the control register (Address 10) bits and bit
descriptions.
Table 17. Control Register (Address 10) Bit Descriptions
Field
Bit(s) Description
Reserved
ECC2_DBL_ERR
[23:6] Reserved.
5
4
3
2
Error Correcting Code Bank 2 double
error detected
Error Correcting Code Bank 2 single
error detected
Error Correcting Code Bank 1 double
error detected
ECC2_SNG_ERR
ECC1_DBL_ERR
ECC1_SNG_ERR
PROG_BUSY Bit
Set the PROG_BUSY bit high to program the EEPROM
memory. When this bit is set to 1, the EEPROM begins to
write to the memory. The hardware sets this bit back to 0 to
indicate that programming has occurred. The write sequence
takes 40 ms (maximum) to perform but can write faster than
40 ms (maximum). If a shorter wait time is required, the
PROG_BUSY bit can be read back multiple times during the
write time. If 0 is read back after the user sets this bit to 1, the
write completed.
Error Correcting Code Bank 1 single
error detected
PROG_BUSY
SIM_TRIM
1
0
Program/busy bit
Simulate trim
ECC2_DBL_ERR Bit
When two errors are detected in the EEPROM stored data, the
ECC2_DBL_ERR bit sets to 1 when read. Two errors are detectable.
Hwever, these errors cannot be fixed using the error correcting
code employed by the ADuM4138. The ECC2_DBL_ERR bit
set to 1 indicates when a double error is detected in the memory
banks, representing trim performed on the ADuM4138 outside
of the registers affected by user and configuration (CONFIG)
addresses. When this bit is set to 0, it indicates no error was
detected for bits greater than 1.
SIM_TRIM Bit
If the SIM_TRIM bit is set to 0, the user and configuration
(CONFIG) registers have no effect on the operation of the
ADuM4138. Use this bit to simulate trim settings but not to
write to the registers.
If SIM_TRIM is set high, address values can change the operation
of the gate driver to simulate what programming the values to
the EEPROM does across power ups. When SIM_TRIM is set
to 0, previous address values from the EEPROM are loaded, and
operation returns to what the power on state is.
ECC2_SNG_ERR Bit
When a single error is detected in the EEPROM stored data, the
ECC2_SNG_ERR bit sets to 1 when read. The error correcting
code employed by the ADuM4138 can detect and correct a
single error. The ECC2_SNG_ERR bit set to 1 indicates when a
single error is detected in the memory banks, representing trim
performed on the ADuM4138 outside of the registers affected
by user and configuration (CONFIG) addresses. When this bit
is set to 0, it indicates no single bit error was detected.
ECC1_DBL_ERR Bit
When two errors are detected in the EEPROM stored data,
the ECC1_DBL_ERR bit sets to 1 when read. Two errors are
detectable. However, these errors cannot be corrected using
the error correcting code employed by the ADuM4138. The
ECC2_DBL_ERR bit set to 1 indicates that a double error is
detected in the memory banks, representing trim performed
on the ADuM4138 by the user and configuration (CONFIG)
addresses. A value of 0 indicates no error was detected for bits
greater than 1.
Rev. A | Page 17 of 24
ADuM4138
Data Sheet
Overcurrent Detection
PROPAGATION DELAY RELATED PARAMETERS
The ADuM4138 operates with split emitter IGBTs or split
source MOSFETs. Using the lower current leg of the split leg
switches, an accurate measurement of current through the
IGBT or MOSFET can be made through a precision sense
resistor. In this way, fast reaction to overcurrent events results.
When an overcurrent event is detected, a high speed, two-level,
turn off initiates. If the overcurrent condition remains beyond
the two-level, detect delay time (tdOC), a fault reports to the
primary side of the ADuM4138. If the overcurrent condition is
removed before the turn off time, the VOUT_ON pin returns to a
high output state, and the fault timer is reset.
Propagation delay describes the time it takes a logic signal to
propagate through a component. The propagation delay to a
low output can differ from the propagation delay to a high
output. The ADuM4138 specifies tDLH (see Figure 13) as the
time between the rising input high logic threshold, VIH, to the
output rising 10% threshold. Likewise, the falling propagation
delay, tDHL, is defined as the time between the input falling logic
low threshold, VIL, and the output falling 90% threshold. The
rise and fall times are dependent on the loading conditions and
are not included in the propagation delay, which is the industry
standard for gate drivers.
Sense temperature on the TS1 pin can modify the overcurrent
threshold. If the T_RAMP_OP bit is set to 1, the overcurrent
threshold is set to 2 V (typical) across all operating conditions.
If the T_RAMP_OP bit is set to 0, the overcurrent voltage
temperature threshold, VOCD_TH_EN, is set to 2.69 V (typical) at TS1 =
1.55 V and goes to 1.75 V (typical) at TS1 = 2.45 V in a linear
fashion (see Figure 14).
90%
OUTPUT
10%
V
IH
INPUT
2.9
V
IL
tDHL
tDLH
2.7
2.5
2.3
2.1
1.9
1.7
1.5
tR
tF
Figure 13. Propagation Delay Parameters
Propagation delay skew refers to the maximum amount that
the propagation delay differs between multiple ADuM4138
components operating under the same temperature, input
voltage, and load conditions.
PROTECTION FEATURES
Primary Side UVLO
1.55
1.75
1.95
2.15
2.35
The ADuM4138 has UVLO on both the primary and secondary
sides. If the primary side voltage drops below 4.13 V (typical),
the transmission to the secondary side is stopped, effectively
bringing the output low. There can be current flowing from the
decoupling capacitor on the V5_1 pin due to the body diode of
the 5 V internal regulator. It is recommended that the VDD1 pin
to GND1 pin be supplied with a voltage 6 V or greater.
TS1 VOLTAGE (V)
Figure 14. Overcurrent Threshold Variation due to Sensed Temperature
ADuM4138
OC_DET
OC_ERROR
OC1
OC2
Δt = t
Fault Reporting
dOC
The ADuM4138 provides protections for faults that may occur
during the operation of an IGBT. The primary fault condition is
overcurrent as detected by the overcurrent detection pins, OC1
or OC2. If detected, the ADuM4138 shuts down the gate drive
V
= 2V
OC
V
OC_OFF
Figure 15. Split Emitter Overcurrent Detection Functional Block Diagram
FAULT
and asserts the
pin low. Faults initiate a soft shutdown
through the VOFF_SOFT pin. Faults can be initiated by the
secondary UVLO, TSD, desaturation detection, overcurrent,
gate low voltage detect, and remote overtemperature.
Rev. A | Page 18 of 24
Data Sheet
ADuM4138
High Speed, Two-Level, Turn Off
ADuM4138
If the OC1 or OC2 pin detects an overcurrent, the two-level
turn off circuitry drives the gate low. The internal MOSFET
drives the device gate low until the input voltage (GATE_SENSE)
reaches the 11.9 V (typical) voltage plateau. tdOCR is time the
output takes from detecting an overcurrent to driving the
overcurrent to the plateau voltage. After the detect time (tdOC),
a fault is registered and reported to the primary side (see Figure 16).
If during tdOC the overcurrent threshold (VOCD_TH), is no longer
violated, the internal positive metal-oxide conductor (PMOS)
returns the gate back to the VDD2 voltage and the two-level timer
is reset (see Figure 17).
V
DD2
DRIVE
FAULT
OC_DET
V
V
OUT_ON
LOW_T_OP
MILLER_THRESH
OUT_OFF
DRIVE
FAULT
V
FAULT
OFF_SOFT
OC_DET
V
DD2
FAULT
DRIVE
LOW_T_OP
tdOCR
GATE_SENSE
V
2LEV
tdOC
GATE_SENSE
V
2LEV
Figure 18. Gate Voltage Output Functional Block Diagram
Miller Clamp
The ADuM4138 has an integrated Miller clamp control signal
to reduce voltage spikes on the IGBT gate due to the Miller
capacitance during shutoff of the IGBT. When the input gate
signal calls for the IGBT to turn off (drive low), the external
Miller clamp MOSFET signal is initially off. When the voltage
on the GATE_SENSE pin crosses the 2 V (typical) internal
voltage reference, as referenced to GND2, the Miller clamp
latches on for the remainder of the off time of the IGBT,
creating a second low impedance current path for the gate
current to follow. The Miller clamp switch remains on until
the input drive signal changes from low to high. Figure 19
shows an example waveform of this timing, and Figure 20
shows the functional block diagram of the Miller clamp.
V
OCx
V
OCD_TH
FAULT
tREPORT
Figure 16. Two-Level Turn Off Fault Example (Not to Scale)
tdOCR
tdOC
VI+
V
DD2
GATE_SENSE
V
2LEV
V
DD2
V
GATE_SENSE
2V
GND
2
V
OCx
V
MILLER
CLAMP
SWITCH
OCD_TH
OFF
ON
OFF
LATCH ON
LATCH OFF
Figure 19. Miller Clamp Example Waveform of Timing
FAULT
Figure 17. Two-Level Timer Recovery Example (Not to Scale)
Rev. A | Page 19 of 24
ADuM4138
Data Sheet
Under normal operation, during IGBT off times, the voltage
across the IGBT (VCE) rises to the rail voltage supplied to the
system. In this instance, the blocking diode shuts off, protecting
the ADuM4138 from high voltages. During the off times, the
internal desaturation switch is on, accepting the current going
through the RBLANK resistor, which allows the CBLANK capacitor
to remain at a low voltage. For the first 450 ns (typical) of the
IGBT on time, the desaturation switch remains on, clamping
the DESAT pin voltage low. After the 450 ns (typical) delay
time, the DESAT pin releases, and the DESAT pin rises to
starting voltage (V3) = VCE + VF + VR_DESAT to dampen the
current at this time, usually around 100 Ω (see Figure 30).
Select a blocking diode with fast recovery and suitable
blocking voltage.
ADuM4138
GATE_SENSE
MILLER_OUT
MILLER_THRESH
V
MILLER
DRIVE
FAULT
Figure 20. Miller Clamp Functional Block Diagram
Desaturation Detection
The ADuM4138 enters a failure state and turns the IGBT off to
prevent desaturation from causing a short-circuit condition
across the IGBT, if the DESAT pin exceeds the DESAT threshold,
In the case of a desaturation event, VCE rises above the 9 V
threshold in the desaturation detection circuit. The voltage
on the DESAT pin rises with a resistor capacitor (RC) time
constant profile dependent on the CBLANK capacitor and the
V
DESAT_R, of 8.9 V (typical) while the high-side driver is on. At
FAULT
this time, the
pin is brought low. An internal current
source of 490 µA (typical) is provided, as well as the option to
boost the charging current using external current sources or
pull-up resistors. The ADuM4138 has a built in blanking time,
RBLANK resistor. The exact timing of this depends on V3, the
supply voltage (VDD2), the RBLANK resistor, and the CBLANK
capacitor values. Depending on the IGBT specifications, a
blanking time of around 2 µs is the typical design choice. When
the DESAT pin rises above the 9 V threshold, a fault registers,
and the gate output is driven low. The NFET soft shutdown
MOSFET brings the output low, which is 15 Ω (typical), to
perform a soft shutdown to reduce the chance of an overvoltage
spike on the IGBT during an abrupt turn off event. Within 825 ns
(typical), the fault communicates back to the primary side
t
BLANK, to prevent false triggering while the IGBT is first turning
on. The time between desaturation detection and reporting a
FAULT
desaturation fault to the
pin is less than 825 ns (typical).
t
DESAT_BLANK provides a 450 ns (typical) masking time that keeps
the internal switch that grounds the blanking capacitor tied low
for the initial portion of the IGBT on time, as shown in Figure 21.
DESAT
EVENT
FAULT
pin.
Thermal Shutdown
VI+
The ADuM4138 contains two thermal shutdowns (TSDs). If the
internal temperature of the secondary side of the ADuM4138
exceeds 150°C (typical), the ADuM4138 enters a TSD fault, and
the gate drive is disabled by means of a soft shutdown. When a
TSD occurs, the ADuM4138 does not leave TSD until the
internal temperature has dropped below 130°C (typical). After
reaching this temperature, the ADuM4138 exits shutdown. A
fault output is available on the primary side during a TSD event
V
GATE
tDESAT_BLANK = 450ns
DESAT
SWITCH
ON OFF
ON
OFF
ON
FAULT
on the secondary side by means of the
pin.
<50ns
If the primary die temperature exceeds 154°C (typical), the
primary side functions shut down, stopping the flyback switching
and shutting down the secondary side. The primary side leaves
TSD when the internal temperature has dropped below 135°C
(typical).
V
CE
9V
~2µs
RECOMMENDED
V
DD2
V
DESAT
9V
The main cause of overtemperature is driving too large a load
for a given ambient temperature. This type of temperature
overload typically affects the secondary side die because this
is where the main power dissipation for load driving occurs.
V
F
tREPORT < 825ns
FAULT
Figure 21. Desaturation Detection Timing Diagram
Rev. A | Page 20 of 24
Data Sheet
ADuM4138
Isolated Temperature Sensor
A low temperature operation mode is available if the voltage
sensed on the TS1 pin is greater than 2.4 V (typical), the
maximum gate voltage is set to the two-level plateau voltage
of 11.90 V (typical), see Figure 23. Hysteresis allows continued
low temperature operation until the TS1 pin voltage goes below
2.36 V (typical). Low temperature operation can be enabled
or disabled in the EEPROM settings in the LOW_T_OP bit,
Address 01, Bit 12. Basic operation is shown in Figure 23.
During the two-level drive, the RDSON resistances of the turn
on and turn off drivers increase to approximately 4 times the
normal turn on and turn off resistances.
The ADuM4138 allows simple isolated temperature detection.
Using an internal current source to bias an external temperature
sensing diode, the ADuM4138 encodes the forward-biased
voltage of the diode into a PWM signal, which is passed across
the isolation barrier from the secondary side to the primary side.
The PWM signal operates at 10 kHz or 50 kHz (programmed
in the EEPROM). A 10% (typical) PWM signal corresponds to a
voltage of 2.45 V, and a 92% (typical) PWM signal corresponds
to 1.55 V. Voltages between the minimum and maximum are
approximately linear and monotonically interpolated. The
ADuM4138 contains support for two remote temperature
sensing diode assemblies, which can both cause overheating
faults on the secondary side. Additionally, one temperature
sensor readback is available for reading on the primary side
through the isolated temperature reporting channel. The lower
voltage (higher temperature) of the two temperature sensor
pins, TS1 and TS2, reports on the TEMP_OUT pin. The gain
and offset of the PWM temperature sensor can be set in the
TEMP_OUT pin voltage mapping (see Figure 22).
GATE DRIVE LEVEL
V
DD2
11.90V
2.36V
2.4V
TS1 VOLTAGE
Figure 23. Low Temperature Operation
1.0
TS1
TS2
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
TSx PIN VOLTAGE (V)
Figure 22. TEMP_OUT Duty Cycle vs. Lower TSx Pin Voltage
ADuM4138
V
OC_OFF
LOW_T_OP
GAIN1
V
T_OFFSET1
EPROM
V
LOW_TEMP
GAIN2
HYSTERESIS
OT_ERROR
V
T_OFFSET2
I
I
T1
T2
GAIN1
Δt = t
dOT
TS1
TS2
V
T_OFFSET1
V
OT
V5
GAIN2
TEMP_OUT_PWM
TEMP_OUT
SAWTOOTH
V
T_OFFSET2
NOTES
1. V
IS THE LOW TEMPERATURE OPERATION COMPARATOR REFERENCE.
LOW_TEMP
2. V IS THE OVERTEMPERATURE ERROR COMPARATOR REFERENCE.
OT
Figure 24. Remote Temperature Sensing Block Diagram
Rev. A | Page 21 of 24
ADuM4138
Data Sheet
POWER DISSIPATION
INSULATION LIFETIME
When driving an IGBT gate, the driver must dissipate power.
This power can lead to TSD if the following considerations are
not made. The gate of an IGBT can be simulated roughly as a
capacitive load. Due to Miller capacitance and other nonlinearities,
All insulation structures eventually break down when subjected
to voltage stress over a sufficiently long period. The rate of
insulation degradation is dependent on the characteristics of the
voltage waveform applied across the insulation. In addition to
the testing performed by the regulatory agencies, Analog Devices
carries out an extensive set of evaluations to determine the
lifetime of the insulation structure within the ADuM4138.
it is common practice to take the stated input capacitance (CISS
of a given IGBT and multiply it by a factor of 5 to arrive at a
conservative estimate to approximate the load being driven.
)
With this value, the estimated total power dissipation (PDISS) in
the system due to switching action is given by the following
equation:
Analog Devices performs accelerated life testing using voltage
levels higher than the rated continuous working voltage.
Acceleration factors for several operating conditions are
determined. These factors allow calculation of the time to
failure at the actual working voltage.
P
DISS = CEST × (VDD2)2 × fS
where:
EST = CISS × 5.
DD2 is the voltage on the VDD2 pin.fS is the switching frequency
C
V
The values shown Table 10 summarize the peak voltage for
20 years of service life for a bipolar ac operating condition, and
the maximum CSA/VDE approved working voltages. In many
cases, the approved working voltage is higher than the 20 year
service life voltage. Operation at these high working voltages
can lead to shortened insulation life in some cases.
of IGBT.
This power dissipation is shared between the internal on
resistances of the internal gate driver switches and the external
gate resistances, RGON and RGOFF. The ratio of the internal gate
resistances to the total series resistance allows the calculation
of losses seen within the ADuM4138 chip.
The insulation lifetime of the ADuM4138 depends on the
voltage waveform type imposed across the isolation barrier.
The iCoupler insulation structure degrades at different rates
depending on whether the waveform is bipolar ac, unipolar ac,
or dc. Figure 25, Figure 26, and Figure 27 show these different
isolation voltage waveforms.
Take the power dissipation found inside the chip due to
switching, adding the quiescent power losses, and multiplying
it by the θJA gives the rise above ambient temperature that the
ADuM4138 experiences.
A bipolar ac voltage environment is the worst case for the
iCoupler products and is the 20 year operating lifetime that
Analog Devices recommends for maximum working voltage
(see Figure 25). In the case of unipolar ac or dc voltage, the stress
on the insulation is significantly lower, which allows operation at
higher working voltages while still achieving a 20 year service life.
Treat any cross insulation voltage waveform that does not conform
to Figure 26 or Figure 27 as a bipolar ac waveform, and limit its
peak voltage to the 20 year lifetime voltage value listed in Table 10.
P
DISS_ADUM4138 = PDISS × 0.5(RDSON_P ÷ (RGON + RDSON_P) +
(RDSON_N ÷ (RGOFF + RDSON_N)) + PQUIESCENT
where:
DISS_ADUM4138 is the power dissipation of the ADuM4138.
GON is the external series resistance in the on path.
P
R
P
P
GOFF is the external series resistance in the off path.
QUIESCENT is the quiescent power.
T
ADuM4138 = θJA × PDISS_ADuM4138 + TAMB
where:
The voltage presented in Figure 26 is shown as sinusoidal for
illustration purposes only. It is meant to represent any voltage
waveform varying between 0 V and some limiting value. The
limiting value can be positive or negative, but the voltage cannot
cross 0 V.
T
T
ADuM4138 is the junction temperature of the ADuM4138.
AMB is the ambient temperature.
For the ADuM4138 to remain within specification, TADuM4138
cannot exceed 150°C (typical). When TADuM4138 exceeds 150°C
(typical), the ADuM4138 enters TSD.
RATED PEAK VOLTAGE
0V
Figure 25. Bipolar AC Waveform
RATED PEAK VOLTAGE
0V
Figure 26. Unipolar AC Waveform
RATED PEAK VOLTAGE
0V
Figure 27. Unipolar DC Waveform
Rev. A | Page 22 of 24
Data Sheet
ADuM4138
1k
100
10
DC CORRECTNESS AND MAGNETIC FIELD
IMMUNITY
DISTANCE = 1m
The ADuM4138 is resistant to external magnetic fields. The
limitation on the ADuM4138 magnetic field immunity is set by
the condition in which the induced voltage in the transformer
receiving coil is sufficiently large to either falsely set or reset the
decoder. The following analysis defines the conditions under
which this can occur.
DISTANCE = 100mm
1
DISTANCE = 5mm
100
0.1
0.01
10
1
1k
10k
100k
1M
10M
100M
MAGNETIC FIELD FREQUENCY (Hz)
Figure 29. Maximum Allowable Current for Various Current to ADuM4138
Spacing
0.1
TYPICAL APPLICATION CIRCUIT
See Figure 30 for an example application of the IGBT drive.
0.01
0.001
1k
10k
100k
1M
10M
100M
MAGNETIC FIELD FREQUENCY (Hz)
Figure 28. Maximum Allowable External Magnetic Flux Density
V
DD2
V
DD2
R
BLANK
V
F
V
R_DESAT
R
ADuM4138
DESAT
SW
1
V
DD2
C
28
27
BLANK
R
SENSE
I
GND
2
3
4
5
6
7
SENSE
2
RCL
1µF
GND
1
V5_2
DESAT
OUT_ON
26
25
24
23
22
21
20
V
DD1
VDD1
1µF
V5_1
V
VI+
V
OUT_OFF
FAULT
TEMP_OUT
PGOOD
MOSI
V
OFF_SOFT
GATE_SENSE
MILLER_OUT
8
9
100Ω
10
11
OC1 19
MISO
OC2
TS1
TS2
18
17
16
15
100Ω
100Ω
12 CS
13
14
SCLK
GND
GND
1
2
Figure 30. IGBT Drive Example Application, Snubber Can Be Added to Flyback
Rev. A | Page 23 of 24
ADuM4138
Data Sheet
OUTLINE DIMENSIONS
10.45
10.15
28
15
7.60
7.40
10.55
10.05
14
1
PIN 1
INDICATOR
TOP VIEW
0.65 BSC
0.40
0.25
0.75
0.25
× 45°
2.40
2.25
2.65
2.35
END VIEW
SIDE VIEW
0.32
0.23
8°
0°
0.25
0.10
0.25 BSC
SEATING
PLANE
(GAUGE PLANE)
1.40
REF
1.27
0.40
COPLANARITY
0.10
Figure 31. 28-Lead Standard Small Outline, Wide Body with Finer Pitch [SOIC_W_FP]
(RN-28-1)
Dimensions shown in millimeters
ORDERING GUIDE
Package
Option
Model1, 2
Temperature Range
Package Description
ADuM4138WBRNZ
ADuM4138WBRNZ-RL
EVAL-ADuM4138EBZ
−40°C to +150°C
−40°C to +150°C
28-Lead Standard Small Outline, Wide Body with Finer Pitch [SOIC_W_FP]
28-Lead Standard Small Outline, Wide Body, with Finer Pitch [SOIC_W_FP]
Evaluation Board
RN-28-1
RN-28-1
1 Z = RoHS Compliant Part.
2 W = Qualified for Automotive Applications.
AUTOMOTIVE PRODUCTS
The ADuM4138W models are available with controlled manufacturing to support the quality and reliability requirements of automotive
applications. Note that these automotive models may have specifications that differ from the commercial models; therefore, designers
should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in
automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to
obtain the specific Automotive Reliability reports for these models.
©2018–2019 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D16036-0-8/19(A)
Rev. A | Page 24 of 24
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