ADUM4221CRIZ [ADI]
Isolated, Half Bridge Gate Driver with Adjustable Dead Time, 4 A Output;
| 型号： | ADUM4221CRIZ |
| 厂家： | 
ADI |
| 描述： | Isolated, Half Bridge Gate Driver with Adjustable Dead Time, 4 A Output 栅 |
| 文件： | 总19页 (文件大小：735K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Isolated, Half Bridge Gate Driver with
Adjustable Dead Time, 4 A Output
ADuM4221
Data Sheet
FEATURES
4 A peak current (<2 Ω RDSON_x
FUNCTIONAL BLOCK DIAGRAM
)
ADuM4221
2.5 V to 6.5 V logic input voltage
4.5 V to 35 V output supply voltage
UVLO VDD1 positive going threshold: 2.5 V maximum
Multiple UVLO options for VDDA and VDDB positive going
threshold
Grade A: 4.5 V maximum
Grade B: 7.5 V maximum
Grade C: 11.6 V maximum
Precise timing characteristics
V
V
16
15
14
1
2
3
4
5
6
7
8
DDA
OA
UVLO
TSD
IA
IB
V
V
DECODE
AND
ENCODE
LOGIC
GND
V
A
DD1
UVLO
GND
13 NC
12 NC
1
CONTROL
LOGIC
DISABLE
DT
UVLO
TSD
V
11
10
9
DDB
44 ns maximum propagation delay
Adjustable dead time
CMOS input logic levels
DECODE
AND
V
NC
OB
ENCODE
LOGIC
V
GND
DD1
B
High common-mode transient immunity: 150 kV/µs
High junction temperature operation: 125°C
Default low output
NC = NO CONNECT
Figure 1.
Safety and regulatory approvals (pending)
UL recognition per UL 1577
5700 V rms for 1 minute duration
CSA Component Acceptance Notice 5A (pending)
VDE certificate of conformity (pending)
DIN V VDE V 0884-11
GENERAL DESCRIPTION
The ADuM4221 is a 4 A isolated, half bridge gate driver that
employs the Analog Devices, Inc., iCoupler® technology to
provide independent and isolated high-side and low-side outputs.
The ADuM4221 provides 5700 V rms isolation in the increased
creepage wide body, 16-lead SOIC_IC package. Combining
high speed CMOS and monolithic transformer technology,
these isolation components provide outstanding performance
characteristics superior to the alternatives, such as the
combination of pulse transformers and gate drivers.
V
IORM = 849 V peak
Increased creepage wide body, 16-lead SOIC_IC
APPLICATIONS
Switching power supplies
Isolated IGBT/MOSFET gate drives
Industrial inverters
Gallium nitride (GaN)/silicon carbide (SiC) compatible
The isolators operate with a logic input voltage ranging from
2.5 V to 6.5 V, providing compatibility with lower voltage systems.
In comparison to gate drivers employing high voltage level
translation methodologies, the ADuM4221 offers the benefit of
true, galvanic isolation between the input and each output.
The ADuM4221 has a built in overlap protection and allows for
dead time adjustment. A single resistor between the dead time
pin (DT) and the GND1 pin sets the dead time on the secondary
side between the high-side and the low-side outputs.
An internal thermal shutdown (TSD) sets outputs low if the
internal temperature on the ADuM4221 exceeds the TSD
temperature. As a result, the ADuM4221 provides reliable
control over the switching characteristics of the insulated gate
bipolar transistor (IGBT)/metal-oxide semiconductor field
effect transistor (MOSFET) configurations over a wide range of
positive or negative switching voltages.
1 Protected by U.S. Patents 5,952,849; 6,873,065; 7,075,239. Other patents pending.
Rev. 0
Document Feedback
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rights of third parties that may result from its use. Specifications subject to change without notice.
No license is granted by implication or otherwise under any patent or patent rights of Analog
Devices. Trademarks and registeredtrademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Technical Support
©2020 Analog Devices, Inc. All rights reserved.
www.analog.com
ADuM4221
Data Sheet
TABLE OF CONTENTS
Features.............................................................................................. 1
Typical Performance Characteristics .............................................9
Theory of Operation ...................................................................... 13
Applications Information ............................................................. 14
PCB Layout ................................................................................. 14
Propagation Delay-Related Parameters.................................. 14
Peak Current Rating .................................................................. 14
Protection Features.................................................................... 14
Output Load Characteristics .................................................... 14
Adjustable Dead Time Control................................................ 15
Boot Strapped, Half Bridge Operation.................................... 16
Power Dissipation...................................................................... 17
DC Correctness and Magnetic Field Immunity .................... 17
Insulation Lifetime..................................................................... 18
Outline Dimensions....................................................................... 19
Ordering Guide .......................................................................... 19
Applications ...................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications .................................................................................... 3
Electrical Characteristics............................................................. 3
Package Characteristics ............................................................... 4
Regulatory Information............................................................... 5
Insulation and Safety Related Specifications............................ 5
DIN V VDE V 0884-11 (VDE V 0884-11) Insulation
Characteristics .............................................................................. 6
Recommended Operating Conditions ...................................... 6
Absolute Maximum Ratings ........................................................... 7
Thermal Resistance...................................................................... 7
ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions ............................ 8
REVISION HISTORY
7/2020—Revision 0: Initial Version
Rev. 0 | Page 2 of 19
Data Sheet
ADuM4221
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
Low-side voltages referenced to GND1, high-side voltages referenced to GNDA, GNDB, 2.5 V ≤ VDD1 ≤ 6.5 V, 4.5 V ≤ VDDA,VDDB ≤ 35 V,
and TJ = −40°C to +125°C, unless otherwise noted. All minimum and maximum specifications apply over the entire recommended
operating range, unless otherwise noted. All typical specifications are at TJ = 25°C, VDD1 = 5.0 V, and VDDA and VDDB = 15 V.
Table 1.
Parameter
Symbol
Min
Typ
Max
Unit Test Conditions
DC SPECIFICATIONS
Logic Input Voltage
Output Supply Voltage
Input Supply Current, Quiescent
Input A High or Input B High
Both Inputs Low
VDD1
VDDA, VDDB
IDD1 (Q)
2.5
4.5
6.5
35
V
V
7.2
1.4
10
2.4
mA
mA
Output Supply Current, Per Channel,
Quiescent
IDD2 (Q)
Output Channel
High
Low
Input Currents
Input Voltage
Input Threshold
Logic High
1.4
1.6
+0.01 +1
2.6
2.1
mA
mA
µA
IIA, IIB
−1
VIH
VIL
0.7 × VDD1
3.5
V
V
V
V
2.5 V ≤ VDD1 ≤ 5 V
VDD1 > 5 V
2.5 V ≤ VDD1 ≤ 5 V
VDD1 > 5 V
Logic Low
0.3 × VDD1
1.5
Undervoltage Lockout (UVLO)
VDD1 Positive Going Threshold
VDD1 Negative Going Threshold
VDD1 Hysteresis
VVDD1UV+
VVDD1UV−
VVDD1UVH
VVDDAUV+
VVDDBUV+
2.45
2.35
0.1
4.4
7.3
11.3
4.2
7.1
11.1
0.2
0.2
2.5
V
V
V
V
V
V
V
V
V
V
V
V
2.3
VDDA and VDDB Positive Going Threshold
,
,
4.5
7.5
11.6
Grade A
Grade B
Grade C
Grade A
Grade B
Grade C
Grade A
Grade B
Grade C
VDDA and VDDB Negative Going Threshold
VDDA and VDDB Hysteresis
VVDDAUV−
VVDDBUV−
4.1
6.9
10.8
VVDDAUVH
VVDDBUVH
,
0.2
TSD
Positive Edge
Hysteresis
Drive Strength
TTSD_POS
TTSD_HYST
155
30
°C
°C
Pull-Down Negative Metal Oxide
Semiconductor (NMOS) On Resistance
RDSON_N
RDSON_P
IPEAK
0.6
1.6
Ω
Tested at 250 mA, VDDx = 15 V
0.6
0.8
1.6
1.8
Ω
Ω
Tested at 1 A, VDDx = 15 V
Tested at 250 mA, VDDx = 15 V
Pull-Up Positive Metal Oxide
Semiconductor (PMOS) On Resistance
0.8
4
1.8
Ω
A
Tested at 1 A, VDDx = 15 V
VDDA,VDDB = 15 V, 2 Ω gate resistance
Peak Current
Rev. 0 | Page 3 of 19
ADuM4221
Data Sheet
Parameter
Symbol
Min
Typ
Max
Unit Test Conditions
SWITCHING SPECIFICATIONS
Pulse Width
50
ns
Load capacitance (CL) = 2.2 nF,
VDD1 = 5 V, VDDA and VDDB = 15 V,
external gate resistor (RG) = 5.1 Ω
CL = 2.2 nF, VDD1 = 5 V, VDDA and
VDDB = 15 V, and RG = 5.1Ω
Propagation Delay1
Rising Edge
Falling Edge
Time to Disable
Time to Enable
Delay Skew2
tDLH
tDHL
tDIS
tEN
tPSK
tPWD
19
21
21
19
25
30
25
25
33
44
44
33
22
16
ns
ns
ns
ns
ns
ns
CL = 2.2 nF, RG = 5.1 Ω
CL = 2.2 nF, VDD1 = 5 V, VDDA and
VDDB = 15 V, RG = 5.1 Ω
Pulse Width Distortion
5
Channel to Channel Matching3
Output Rise and Fall Time (10% to 90%)
Adjustable Dead Time
tPSKCD
tR/tF
DT
1.5
25
10
34
ns
ns
CL = 2.2 nF, VDD1 = 5 V, VDDA and
VDDB = 15 V, see Figure 19
CL = 2.2 nF, VDD1 = 5 V, VDDA and
VDDB = 15 V, RG = 5.1 Ω, see Figure 26
CL = 2.2 nF, VDD1 = 5 V, VDDA and
VDDB = 15 V, RG = 5.1 Ω
14
1809
742
48
2320
938
62
2831
1135
76
ns
ns
ns
Dead time resistor (RDT) = 500 kꢀ
RDT = 200 kꢀ
RDT = 10 kꢀ
1 tDLH propagation delay is measured from the time of the input rising logic high threshold, VIH, to the output rising 10% level of the VOx signal. tDHL propagation delay is
measured from the input falling logic low threshold, VIL, to the output falling 90% threshold of the VOx signal. See Figure 26 for the waveforms of the propagation delay
parameters.
2 tPSK is the magnitude of the worst case difference in tDLH and/or tDHL that is measured between units at the same operating temperature, supply voltages, and output
load within the recommended operating conditions. See Figure 26 for the waveforms of the propagation delay parameters.
3 Channel to channel matching is the absolute value of the difference in propagation delays between two channels on a single device.
PACKAGE CHARACTERISTICS
Table 2.
Parameter
Symbol Min Typ Max Unit Test Conditions/Comments
Resistance (Input to Output)1
Capacitance (Input to Output)1
Input Capacitance2
RI-O
CI-O
CI
1013
2.2
4.0
45
ꢀ
pF
pF
f = 1 MHz
IC Junction to Ambient Thermal Resistance θJA
°C/W Thermocouple located at center of package underside
1 The device is considered a 2-terminal device: Pin 1 through Pin 8 are shorted together, and Pin 9 through Pin 16 are shorted together.
2 Input capacitance is from any input data pin to ground.
Rev. 0 | Page 4 of 19
Data Sheet
ADuM4221
REGULATORY INFORMATION
The ADuM4221 is pending approval by the organizations listed in Table 3.
Table 3.
UL (Pending)
CSA (Pending)
VDE (Pending)
CQC (Pending)
Recognized Under 1577 Component
Recognition Program1
Approved under CSA Component
Acceptance Notice 5A
Certified according to DIN VDE V
0884-11 (VDE V 0884-11):2017-012
Certified by
CQC11-471543-2012
Single Protection, 5700 V rms
Isolation Voltage
IEC 62368, Third Edition
Basic insulation, 900 V peak,
VIOSM = 9850 V peak
GB4943.1-2011
Basic insulation at 830 V rms
(1173 V peak)
Reinforced insulation, 849 V peak, Basic insulation at
VIOSM = 8000 V peak
800 V rms (1131 V peak)
Reinforced insulation at 415 V rms
(586 V peak)
Reinforced insulation at
400 V rms (565 V peak)
IEC 60601-1, Edition 3.1
Reinforced insulation (2 MOPP),
250 V rms (353V peak)
CSA 61010-1-12 and IEC 61010-1,
Third Edition
Basic insulation at 300 V rms mains,
800 V secondary (1089 V peak)
Reinforced insulation at
300 V rms mains,
400 V secondary (565 V peak)
File E214100
File 205078
File 2471900-4880-0003
File (pending)
1 In accordance with UL 1577, each ADuM4221 is proof tested by applying an insulation test voltage ≥ 6840 V rms for 1 sec.
2 In accordance with DIN VDE V 0884-11, each ADuM4221 is proof tested by applying an insulation test voltage ≥ 1592 V peak for 1 sec (partial discharge detection limit =
5 pC). The * marking branded on the component designates DIN VDE V 0884-11 approval.
INSULATION AND SAFETY RELATED SPECIFICATIONS
Table 4.
Parameter
Symbol Value Unit
Test Conditions/Comments
Rated Dielectric Insulation Voltage
Minimum External Air Gap (Clearance)
5700
8.3
V rms
mm
1-minute duration
Measured from input terminals to output
terminals, shortest distance through air
Measured from input terminals to output
terminals, shortest distance path along body
Measured from input terminals to output
terminals, shortest distance through air,
line of sight, in the PCB mounting plane
L (I01)
L (I02)
L (PCB)
Minimum External Tracking (Creepage)
8.3
8.3
mm
mm
Minimum Clearance in the Plane of the Printed Circuit
Board, PCB (PCB Clearance)
Minimum Internal Gap (Internal Clearance)
Tracking Resistance (Comparative Tracking Index)
Material Group
25.5
>600
I
μm
V
Insulation distance through insulation
DIN IEC 112/VDE 0303 Part 1
Material Group (DIN VDE 0110, 1/89, Table 1)
CTI
Rev. 0 | Page 5 of 19
ADuM4221
Data Sheet
DIN V VDE V 0884-11 (VDE V 0884-11) INSULATION CHARACTERISTICS
This isolator is suitable for reinforced isolation only within the safety limit data. Protective circuits ensure maintenance of the safety data.
Table 5. VDE Characteristics
Description
Test Conditions/Comments
Symbol
Characteristic Unit
Installation Classification per DIN VDE 0110
For Rated Mains Voltage ≤ 150 V rms
For Rated Mains Voltage ≤ 300 V rms
For Rated Mains Voltage ≤ 600 V rms
Climatic Classification
Pollution Degree per DIN VDE 0110, Table 1
Maximum Repetitive Peak Isolation Voltage
Input to Output Test Voltage, Method B1
I to IV
I to IV
I to IV
40/105/21
2
VIORM
Vpd (m)
849
1592
V peak
V
IORM × 1.875 = Vpd (m), 100% production test,
V peak
tini = tm = 1 sec, partial discharge < 5 pC
Input to Output Test Voltage, Method A
After Environmental Tests Subgroup 1
Vpd (m)
V
IORM × 1.5 = Vpd (m), tini = 60 sec, tm = 10 sec,
1274
1019
8000
V peak
V peak
V peak
partial discharge < 5 pC
VIORM × 1.2 = Vpd (m), tini = 60 sec, tm = 10 sec,
partial discharge < 5 pC
After Input and/or Safety Test Subgroup 2
and Subgroup 3
Maximum Rated Transient Isolation Voltage
Surge Isolation Voltage
Basic
VIOTM
VIOSM
V peak = 12.8 kV, 1.2 µs rise time, 50 µs,
50% fall time
V peak = 12.8 kV, 1.2 µs rise time, 50 µs,
50% fall time
9850
8000
V peak
V peak
Reinforced
Safety Limiting Values
Maximum value allowed in the event of a
failure (see Figure 2)
Maximum Junction Temperature
Total Power Dissipation at 25°C
Insulation Resistance at TS
TS
PS
RS
150
2.77
>109
°C
W
Ω
VIO = 500 V
3.0
2.5
2.0
1.5
1.0
0.5
0
RECOMMENDED OPERATING CONDITIONS
Table 6.
Parameter
Value
TJ
−40°C to +125°C
Supply Voltages
1
VDD1
2.5 V to 6.5 V
4.5 V to 35 V
2
VDDA and VDDB
Common-Mode Transient Immunity
Static3
−150 kV/µs to +150 kV/µs
−150 kV/µs to +150 kV/µs
10 kΩ to 500 kΩ
Dynamic4
Dead Time Resistor Range
0
50
100
150
200
1 Referenced to GND1.
AMBIENT TEMPERATURE (°C)
2 Referenced to GNDA,GNDB.
Figure 2. Thermal Derating Curve, Dependence of Safety Limiting Values on
Case Temperature, per DIN V VDE V 0884-11
3 Static common-mode transient immunity is defined as the largest dv/dt
between GND1 and GNDA and GNDB with the inputs held either high or low
such that the output voltage remains either above 0.8 × VDDA and VDDB for
output high or 0.8 V for output low. Operation with transients above
recommended levels can cause momentary data upsets.
4 Dynamic common-mode transient immunity is defined as the largest dv/dt
between GND1 and GNDA and GNDB with the switching edge coincident with
the transient test pulse. Operation with transients above recommended
levels can cause momentary data upsets.
Rev. 0 | Page 6 of 19
Data Sheet
ADuM4221
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Table 7.
Parameter
Voltage Ranges
Supply
VDD1
VDDA and VDDB
Input1 (VIA, VIB, and DISABLE)
Output2
Rating
−0.2 V to +7 V
−0.3 V to +40 V
−0.3 V to +7 V
THERMAL RESISTANCE
Thermal performance is directly linked to the PCB design and
operating environment. Careful attention to PCB thermal
design is required.
VOA
VOB
−0.3 V to VDDA + 0.3 V
−0.3 V to VDDB + 0.3 V
−2 V to VDDA + 0.3 V
−2 V to VDDB + 0.3 V
VOA Transient for 200 ns
VOB Transient for 200 ns
Temperature Range
Storage (TST)
θJA is the junction to ambient thermal resistance, and ΨJT is the
junction to top characterization parameter.
Table 8. Thermal Resistance
−55°C to +150°C
−40°C to +125°C
−200 kV/µs to
+200 kV/µs
Package Type1
θJA
ΨJT
Unit
TJ
Common-Mode Transients3 (CMH, CML)
RI-16-2
45
16.67
°C/W
1 4-layer PCB.
1 Rating assumes VDD1 is above 2.5 V. VIA and VIB are rated up to 6.5 V when VDD1
is unpowered.
2 Referenced to GND2, maximum of 40 V.
ESD CAUTION
3 Refers to common-mode transients across the insulation barrier. Common-
mode transients exceeding the absolute maximum rating can cause latch-up
or permanent damage.
Table 9. Maximum Continuous Working Voltage1
Parameter
Rating
Unit
Constraint
AC Voltage
Bipolar Waveform
Basic Insulation
Reinforced Insulation 849
DC Voltage
900
V peak
V peak
20 year minimum insulation lifetime per VDE-0884-11
20 year minimum insulation lifetime per VDE-0884-11
Basic Insulation
1660
V peak
V peak
Lifetime limited by package creepage maximum approved working voltage per IEC 60664-1,
Pollution Degree 2, Material Group I
Lifetime limited by package creepage maximum approved working voltage per IEC 60664-1,
Pollution Degree 2, Material Group I
Reinforced Insulation
830
1 Refers to the continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for more details.
Rev. 0 | Page 7 of 19
ADuM4221
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
V
V
V
V
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
IA
DDA
IB
OA
V
GND
NC
NC
V
DD1
A
ADuM4221
GND
1
TOP VIEW
DISABLE
DT
(Not to Scale)
DDB
OB
NC
V
V
GND
B
DD1
NOTES
1. NC = NO CONNECT.
DO NOT CONNECT TO THESE PINS.
Figure 3. Pin Configuration
Table 10. Pin Function Descriptions
Pin No.1
Mnemonic Description
1
VIA
Logic Input A.
2
VIB
Logic Input B.
3, 8
4
5
VDD1
GND1
DISABLE
DT
Input Supply Voltage.
Ground Reference for Input Logic Signals.
Input Disable. The DISABLE pin disables the isolator inputs and refresh circuits.
Dead Time Control Input. The resistor connected from the DT pin to ground sets the dead time between the
output transitions.
6
7, 12, 13
9
NC
GNDB
VOB
VDDB
GNDA
VOA
No Connect. Do not connect to these pins.
Ground Reference for Output B.
Output B.
Output B Supply Voltage.
Ground Reference for Output A.
Output A.
10
11
14
15
16
VDDA
Output A Supply Voltage.
1 Pin 3 and Pin 8 are internally connected. Connecting both the VDD1 pins to the VDD1 input supply is recommended.
Table 11. Truth Table (Positive Logic with Dead Time)
DISABLE1 VIA Input1 VIB Input1
VDD1 State
VDDA and VDDB State VOA Output
VOB Output
Notes
Low
Low
Low
Low
Low
Low
High
High
Low
High
Low
High
Powered
Powered
Powered
Powered
Powered
Low
Low
High
Low
Low
Output transition begins
after dead time expires
Output transition begins
after dead time expires
Output transition begins
after dead time expires
Output transition begins
after dead time expires
Powered
Powered
Powered
High
Low
Low
High
X
X
X
X
X
Powered
Unpowered
Powered
Powered
Low
Low
Low
Low
Device is disabled
Output returns to input state
after VDD1 power restoration
X
X
X
Powered
Unpowered
Low
Low
Output remains low
1 X means don’t care.
Rev. 0 | Page 8 of 19
Data Sheet
ADuM4221
TYPICAL PERFORMANCE CHARACTERISTICS
V
IB
V
Ox
V
IA
2
1
3
V
Ix
V
OB
4
3
V
OA
1
CH1 2.00V
CH3 5.00V
CH2 2.00V
CH4 5.00V
M2.00µs
16.0000µs
MAX
A
CH1
2.84V
CH1 2.00V
CH3 5.00V
M40.0ns
A CH1
2.04V
T
T
159.800ns
VALUE MEAN MIN
962.2ns 961.6n 961.6n 962.2n 353.6p
34.27ns 34.21n 34.15n 34.27n 82.50p
STD DEV
3
3
4
4
Figure 7. Dead Time Operation Between Input and Output with 200 kΩ Dead
Time Resistor and One Input Held High
Figure 4. Output Waveform for 2 nF Load and 3.9 Ω Series Gate Resistor
with 15 V Output Supply
V
V
DD1
Ox
3
4
3
V
Ix
V
Ox
1
M400µs
4.00000µs
MAX
14.33µs 14.33µ 14.33µ 14.33µ 0.000
A
CH4
5.50V
CH3 2.00V
CH4 5.00V
T
CH1 2.00V
CH3 5.00V
M40.0ns
A CH1
2.04V
VALUE MEAN MIN
STD DEV
T
159.800ns
3
4
Figure 5. Output Waveform for 2 nF Load and 0 Ω Series Gate Resistor
with 15 V Output Supply
Figure 8. Typical VDD1 Delay to Output Waveform, VIx = VDD1
V
IB
V
IA
V
DD2
1, 2
V
V
OA
3
4
OB
V
Ox
3, 4
M400µs
4.00000µs
MAX
13.84µs 13.84µ 13.84µ 13.84µ 0.000
A
CH4
5.50V
CH1 2.00V
CH3 5.00V
CH2 2.00V
CH4 5.00V
M400ns
0.0000s
MAX
A CH1
2.84V
CH3 5.00V
CH4 5.00V
T
T
VALUE MEAN MIN
STD DEV
VALUE MEAN MIN
252.1ns 163.8n –37.90n 252.1n 120.6n
252.9ns 165.4n –22.80n 254.0n 121.5n
STD DEV
3
4
3
4
4
3
Figure 6. Dead Time Operation Between Input and Output with 50 kΩ
Dead Time Resistor
Figure 9. Typical VDD2 Delay to Output Waveform, VIx = VDD1
(VDD2 Refers to VDDA or VDDB
)
Rev. 0 | Page 9 of 19
ADuM4221
Data Sheet
6.0
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
V
V
= 3.3V
V
V
V
= 5V
= 10V
= 15V
DD1
DD1
DD2
DD2
DD2
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
= 5V
0
100 200 300 400 500 600 700 800 900 1000
FREQUENCY (kHz)
0
10
20
30
40
50
60
70
80
90
100
DUTY CYCLE (%)
Figure 10. VDD1 Current (IDD1) vs. Frequency for VDD1 = 3.3 V and VDD1 = 5 V,
50% Duty Cycle
Figure 13. IDD2 vs. Duty Cycle for VDD2 = 5 V, VDD2 = 10 V, and VDD2 = 15 V,
VDD1 = 5 V (VDD2 Refers to VDDA or VDDB
)
40
30
25
20
15
10
5
V
V
V
= 5V
= 10V
= 15V
RISE TIME
FALL TIME
DD2
DD2
DD2
35
30
25
20
15
10
5
0
0
–40
–20
0
20
40
60
80
100
120
0
100 200 300 400 500 600 700 800 900 1000
FREQUENCY (kHz)
TEMPERATURE (°C)
Figure 11. VDD2 Current (IDD2) vs. Frequency for VDD2 = 5 V, VDD2 = 10 V, and
Figure 14. Rise and Fall Time vs. Temperature with a 3.9 Ω Series Gate
Resistor for a 2 nF Load and a 15 V Output Supply
V
DD2 = 15 V, 50% Duty Cycle, 2 nF Load (VDD2 Refers to VDDA or VDDB)
30
10
V
V
= 2.5V
= 5V
RISE TIME
FALL TIME
DD1
DD1
9
8
7
6
5
4
3
2
1
0
25
20
15
10
5
0
5
10
15
20
25
30
35
0
10
20
30
40
50
60
70
80
90
100
OUTPUT SUPPLY VOLTAGE (V)
DUTY CYCLE (%)
Figure 12. IDD1 vs. Duty Cycle for VDD1 = 2.5 V and VDD1 = 5 V,
DD2 = 15 V (VDD2 Refers to VDDA or VDDB
Figure 15. Rise and Fall Time vs. Output Supply Voltage with a 3.9 Ω Series
Gate Resistor for a 2 nF Load
V
)
Rev. 0 | Page 10 of 19
Data Sheet
ADuM4221
15
12
9
40
RISING
CHANNEL TO CHANNEL RISING
CHANNEL TO CHANNEL FALLING
FALLING
35
30
25
20
15
10
5
6
3
0
0
–40
–20
0
20
40
60
80
100
120
4
8
12
16
20
24
28
32
36
TEMPERATURE (°C)
OUTPUT SUPPLY VOLTAGE (V)
Figure 16. Propagation Delay vs. Temperature
Figure 19. Channel to Channel Matching vs. Output Supply Voltage,
Rising and Falling
15
40
35
30
25
20
15
10
5
CHANNEL TO CHANNEL RISING
CHANNEL TO CHANNEL FALLING
12
9
6
3
RISING
FALLING
0
0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
–40
–20
0
20
40
60
80
100
120
INPUT SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
Figure 17. Propagation Delay vs. Input Supply Voltage, Rising and Falling,
VDD2 = 15 V (VDD2 Refers to VDDA or VDDB
Figure 20. Channel to Channel Matching vs. Temperature, Rising and
)
Falling, VDD2 = 15 V (VDD2 Refers to VDDA or VDDB)
8
7
6
5
4
3
2
1
0
40
35
30
25
20
15
10
5
SOURCE CURRENT
SINK CURRENT
RISING
FALLING
0
0
5
10
15
20
25
30
35
40
4
8
12
16
20
24
28
32
36
OUTPUT SUPPLY VOLTAGE (V)
OUTPUT SUPPLY VOLTAGE (V)
Figure 18. Propagation Delay vs. Output Supply Voltage, Rising and
Falling, VDD1 = 5 V
Figure 21. Peak Output Current vs. Output Supply Voltage with a 2.2 Ω
Series Gain Resistor
Rev. 0 | Page 11 of 19
ADuM4221
Data Sheet
1.0
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
NMOS
NMOS
PMOS
PMOS
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
4
8
12
16
20
24
28
32
36
–40
–20
0
20
40
60
80
100
120
OUTPUT SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
Figure 22. Output Resistance (RDS(ON)) vs. Output Supply Voltage for
NMOS and PMOS, VDD1 = 5 V
Figure 23. RDS(ON) vs. Temperature for NMOS and PMOS
Rev. 0 | Page 12 of 19
Data Sheet
ADuM4221
THEORY OF OPERATION
Gate drivers are required where fast rise times of switching
device gates are desired. The gate signal for most enhancement
type power devices is referred to a source or emitter node. The
gate driver must have the ability to follow this source or emitter
node, necessitating isolation between the controlling signal and
the output of the gate driver in topologies where the source or
emitter nodes swing, such as a half bridge. Gate switching times
are a function of the drive strength of the gate driver. Buffer
stages before a CMOS output reduce the total delay time and
increase the final drive strength of the driver.
The encoding scheme used by the ADuM4221 is a positive logic
on/off keying (OOK), a high signal transmitted by the presence of
the carrier frequency across the iCoupler chip scale transformer
coils. Positive logic encoding ensures that a low signal is seen on
the output when the input side of the gate driver is unpowered.
A low state is the most common safe state in enhancement
mode power devices, driving in situations where shoot through
conditions can exist. The architecture is designed for high
common-mode transient immunity and high immunity to
electrical noise and magnetic interference. Radiated emissions
are minimized with a spread spectrum OOK carrier and other
techniques such as differential coil layout. Figure 24 illustrates
the encoding used by the ADuM4221.
The ADuM4221 achieves isolation between the control side and
output side of the gate driver by means of a high frequency carrier
that transmits data across the isolation barrier using iCoupler chip
scale transformer coils separated by layers of polyimide isolation.
REGULATOR
REGULATOR
RECEIVER
TRANSMITTER
V
V
OUT
IN
GND
GND
2
1
Figure 24. Operational Block Diagram of OOK Encoding (VIN Is the Input Voltage, and VOUT Is the Output Voltage.)
Rev. 0 | Page 13 of 19
ADuM4221
Data Sheet
APPLICATIONS INFORMATION
Channel to channel matching is the maximum amount that the
propagation delay differs between channels within a single
component.
PCB LAYOUT
The ADuM4221 requires no external interface circuitry for the
logic interfaces. Power supply bypassing is required at the input
and output supply pins, as shown in Figure 25. Use a small ceramic
capacitor with a value between 0.01 μF and 0.1 μF to provide a
good high frequency bypass. On the output power supply pin,
Propagation delay skew is the maximum amount that the
propagation delay differs between multiple components
operating under the same conditions.
V
DDA or VDDB, it is also recommended to add a 10 μF capacitor
PEAK CURRENT RATING
to provide the charge required to drive the gate capacitance at
the ADuM4221 outputs. On the output supply pin, avoid the
use of vias with a bypass capacitor or use multiple vias to
reduce the inductance in the bypassing. The total lead length
between both ends of the smaller capacitor and the input or
output power supply pin must be as short as possible.
The ADuM4221 has two output channels, and each channel
connects to the gate of the power device through an external
series gate resistor. The output driver MOSFETs of the gate
driver IC can source or sink more than 6 A (per VOA and VOB). In
a practical application, to control the drive strength and to spread
the power dissipation of driving the gate to outside of the gate
driver IC, standard external series gate resistors are used. The
output current of the gate driver is shown in Figure 21 of the
Typical Performance Characteristics section.
V
V
V
DDA
IA
V
IB
OA
V
DD1
GND
A
GND
1
NC
NC
PROTECTION FEATURES
DISABLE
TSD
DT
NC
NC
V
DDB
V
If the internal temperature of the ADuM4221 exceeds 155°C
(typical), the device enters TSD. During the TSD time, the gate
drive is disabled. When TSD occurs, the device does not leave
TSD until the internal temperature drops below 125°C
(typical), at which time, the device exits shutdown.
OB
V
DD1
GND
B
Figure 25. Recommended PCB Layout
PROPAGATION DELAY-RELATED PARAMETERS
Propagation delay parameter describes the time it takes a logic
signal to propagate through a component. The propagation delay
to a logic low output can differ from the propagation delay to a
logic high output. The ADuM4221 specifies the rising edge
propagation delay (tDLH) as the time between the rising input high
logic threshold (VIH) to the output rising (tR) 10% threshold
(see Figure 26). Likewise, the falling edge propagation delay
(tDHL) is the time between the input falling logic low threshold
(VIL) and the output falling (tF) 90% threshold. The rise and fall
times are dependent on the loading conditions and are not
included in the propagation delay, which is the industry
standard for gate drivers.
UVLO
The ADuM4221 has UVLO protections for both the primary
and secondary side of the device. If either the primary or
secondary side voltages are below the falling edge UVLO, the
device outputs a low signal. After the ADuM4221 is powered
above the rising edge UVLO threshold, the device outputs the
signal found at the input. To account for small voltage source
ripple, hysteresis is built into the UVLO. The primary side
UVLO thresholds are common among all models.
OUTPUT LOAD CHARACTERISTICS
The output signals depend on the characteristics of the output
load, which is typically an N channel MOSFET. The driver output
response to an N channel MOSFET load with a gate voltage
(VGATE) can be modeled with a switch output resistance (RSW),
an inductance due to the PCB trace (LTRACE), a series gate resistor
(RGATE), and a gate to source capacitance (CGS), as shown in
Figure 27.
90%
OUTPUT
10%
V
IH
INPUT
R
R
SW
GATE
V
V
OA
V
IA
IL
V
ADuM4221
GATE
L
TRACE
C
tDHL
GS
tDLH
tF
tR
Figure 27. Resistor, Inductor, and Capacitor (RLC) Model of the Gate of an
N Channel MOSFET
Figure 26. Propagation Delay Parameters
Rev. 0 | Page 14 of 19
Data Sheet
ADuM4221
RSW is the switch resistance of the internal driver output, which
is approximately 2 Ω. RGATE is the intrinsic gate resistance of the
MOSFET and any external series resistance. A MOSFET that
requires a 4 A gate driver has a typical intrinsic gate resistance of
approximately 1 Ω and a CGS of between 2 nF and 10 nF. LTRACE
is the inductance of the PCB trace, typically a value of 5 nH or
less for a well designed layout with a short and wide connection
from the ADuM4221 output to the gate of the MOSFET. The
following equation defines the Q factor of the RLC circuit, which
indicates how the output responds to a step change. For a well
damped output, Q is less than 1.
between the DT pin and ground (see Figure 30). The relation
between RDT and the obtained dead time is shown in Figure 28.
2400
2100
1800
1500
1200
900
600
300
0
1
LTRACE
CGS
Q =
×
(RSW + RGATE
)
0
50
100 150 200 250 300 350 400 450 500
(kΩ)
Output ringing is reduced by adding a series gate resistance to
dampen the response. The waveforms in Figure 4 show a correctly
damped example with a 2 nF load and a 3.9 Ω external series gate
resistor. The waveforms in Figure 5 show an underdamped
example with a 2 nF load and a 0 Ω external series gate resistor.
R
DT
Figure 28. Dead Time vs. Dead Time Resistor
Use the following equation, to calculate the required amount of
dead time:
DT (ns) ≈ 5 × RDT (kΩ)
ADJUSTABLE DEAD TIME CONTROL
The VOx pin reacts to the VIx pin depending on the dead time
value set by the RDT resistor. The DT pin controls the edge
transitions between VOA and VOB. Dead time only affects the
rising edge transition of the gate drive signal, and dead time
operation is shown in Figure 29.
The ADuM4221 includes overlap protection such that the gate
driver outputs (VOA and VOB) cannot simultaneously go high even
if both inputs are high. Additionally, the ADuM4221 also has a
dead time control pin (DT) that can adjust the delay between the
output high-side and low-side transitions by using a single resistor
V
IH
V
IA
V
IL
V
IH
V
IB
V
IL
DT
DT
90%
V
V
OA
10%
90%
DT
DT
OB
10%
Figure 29. Dead Time Operation for Different Input Transitions
Rev. 0 | Page 15 of 19
ADuM4221
Data Sheet
the low-side switch is closed, bringing GNDA to GNDB (see
BOOT STRAPPED, HALF BRIDGE OPERATION
Figure 30). During the CA charging time, control the dv/dt of
the VDDA voltage to reduce the possibility of glitches on the
output. To control the dv/dt of the VDDA voltage, introduce a
series resistance (RBOOT) into the CA charging path.
The ADuM4221 is well suited for operating two output gate
signals referenced to separate grounds, as in the case for a half
bridge configuration. Because isolated auxiliary supplies are often
expensive, it is beneficial to reduce the amount of supplies.
Note that in Figure 30, DBOOT is the bootstrapped diode, CDD1
is the decoupling capacitor on the input side, and CB is the
decoupling capacitor for the driver low-side supply.
One method to reduce power supplies is to use a boot strapped
configuration for the high-side supply of the ADuM4221.
In this topology, the decoupling capacitor (CA) acts as the
energy storage for the high-side supply and is filled whenever
V
BUS
R
V
BOOT
V
V
IA
DDA
ADuM4221
1
16
15
14
13
12
11
10
9
D
BOOT
R
V
IB
GA
OA
ENCODE
DECODE
2
3
4
5
6
7
8
C
A
V
DD1
V
DD1
GND
NC
A
C
DD1
V
DD1
GND
1
DISABLE
DT
NC
V
DDB
DELAY
V
DDB
R
NC
GB
V
R
OB
DT
V
DD1
ENCODE
DECODE
C
B
V
DD1
GND
B
NC = NO CONNECT
Figure 30. Circuit of Bootstrapped Half Bridge Operation
Rev. 0 | Page 16 of 19
Data Sheet
ADuM4221
POWER DISSIPATION
DC CORRECTNESS AND MAGNETIC FIELD
IMMUNITY
When driving a MOSFET or IGBT gate, the driver must dissipate
power. This power is not insignificant and can lead to TSD if
considerations are not made. The gate of an IGBT can be
approximately simulated as a capacitive load. Due to Miller
capacitance and other nonlinearities, it is common practice to
take the stated input capacitance of a given MOSFET or IGBT,
CISS, and multiply this capacitance by a factor of 3 to 5 to arrive
at a conservative estimate of the approximate load being driven.
With this value, the estimated total power dissipation in the
system due to the switching action is given by
The ADuM4221 is resistant to external magnetic fields. The
limitation on the ADuM4221 magnetic field immunity is set by
the condition in which the induced voltage in the transformer
receiving coil is sufficiently large to either falsely set or reset
the decoder. The following analysis defines the conditions under
which falsely sets or resets of the decoder can occur (see Figure 31
and Figure 32).
100
DISS = CEST × (VDD2 − GND2)2 × fSW
where:
EST = CISS × 5.
SW is the switching frequency of the IGBT.
Alternately, use the gate charge as follows:
DISS = QG × (VDD2 − GND2) × fSW
10
1
P
C
f
0.1
P
0.01
where QG is the total gate charge of the device being driven.
This power dissipation is shared between the internal on
resistances of the internal gate driver switches and the external
gate resistances, RGON and RGOFF. The ratio of the internal gate
resistances to the total series resistance allows the calculation of
losses seen within the ADuM4221device.
0.001
1k
10k
100k
1M
10M
100M
MAGNETIC FIELD FREQUENCY (Hz)
Figure 31. Maximum Allowable External Magnetic Flux Density
1k
P
DISS_ADuM4221 = PDISS × 0.5(RDSON_P/(RGON + RDSON_P) +
DISTANCE = 1m
100
0.5(RDSON_N/(RGOFF + RDSON_N))
Take the power dissipation found inside the chip and multiply
it by θJA to see the rise above ambient temperature that the
ADuM4221 experiences, then multiplied this value by two
because there are two channels.
10
DISTANCE = 100mm
1
TADuM4221 = θJA × 2 × PDISS_ADuM4221 + TA
DISTANCE = 5mm
0.1
For the device to remain within specification, TADuM4221 must
not exceed 125°C. If TADuM4221 exceeds the TSD rising edge, the
device enters TSD, and the output remains low until the TSD
falling edge is crossed.
0.01
1k
10k
100k
1M
10M
100M
MAGNETIC FIELD FREQUENCY (Hz)
Figure 32. Maximum Allowable Current for Various Current to
ADuM4221 Spacings
Rev. 0 | Page 17 of 19
ADuM4221
Data Sheet
Analog Devices recommends for the maximum working
INSULATION LIFETIME
voltage. In the case of unipolar ac or dc voltage, the stress on
the insulation is significantly lower. Unipolar ac or dc voltage
operation allows operation at higher working voltages while
still achieving a 20 year service life. Any cross insulation voltage
waveform that does not conform to Figure 34 or Figure 35 must
be treated as a bipolar ac waveform, and its peak voltage must
be limited to the 20 year lifetime voltage value listed in Table 9.
All insulation structures eventually break down when subjected
to voltage stress over a sufficiently long period. The rate of
insulation degradation is dependent on the characteristics of
the voltage waveform applied across the insulation. In addition
to the testing performed by regulatory agencies, Analog Devices
carries out an extensive set of evaluations to determine the
lifetime of the insulation structure within the ADuM4221.
The voltage presented in Figure 34 is shown as sinusoidal for
illustration purposes only. This voltage is meant to represent
any voltage waveform varying between 0 V and some limiting
value. The limiting value can be positive or negative, but the
voltage cannot cross 0 V.
Analog Devices performs accelerated life testing using voltage
levels higher than the rated continuous working voltage.
Acceleration factors for several operating conditions are
determined. These factors allow calculation of the time to
failure at the actual working voltage.
RATED PEAK VOLTAGE
The values detailed in Table 9 summarize the peak voltage for
20 years of service life for a bipolar ac operating condition,
and the maximum CSA and VDE approved working voltages.
In many cases, the approved working voltage is higher than
the 20 year service life voltage. Operation at these high working
voltages can lead to shortened insulation life in some cases.
0V
Figure 33. Bipolar AC Waveform
RATED PEAK VOLTAGE
0V
The insulation lifetime of the ADuM4221 depends on the
voltage waveform type imposed across the isolation barrier.
The iCoupler insulation structure degrades at different rates
depending on whether the waveform is bipolar ac, unipolar ac,
or dc. Figure 33, Figure 34, and Figure 35 illustrate these
different isolation voltage waveforms.
Figure 34. Unipolar AC Waveform
RATED PEAK VOLTAGE
0V
Figure 35. DC Waveform
A bipolar ac voltage environment is the worst condition for
iCoupler products and is the 20 year operating lifetime that
Rev. 0 | Page 18 of 19
Data Sheet
ADuM4221
OUTLINE DIMENSIONS
12.95
12.80
12.65
16
9
8
7.60
7.50
7.40
10.55
10.30
10.05
1
PIN 1
INDICATOR
TOP VIEW
SIDE VIEW
0.76
0.25
45°
0.25 BSC
2.64
2.50
2.36
2.44
2.24
GAGE
0.33
0.23
PLANE
END VIEW
0.25
0.10
SEATING
PLANE
8°
0°
1.27 BSC
COPLANARITY
0.49
0.35
1.27
0.41
0.10
COMPLIANT TO JEDEC STANDARDS MS-013-AC
Figure 36. 16-Lead Standard Small Outline Package with Increased Creepage [SOIC_IC]
(RI-16-2)
Dimensions shown in millimeters
ORDERING GUIDE
Minimum
Inputs Output Voltage (V)
Adjustable
Dead Time
Yes
Yes
Temperature
Range
−40°C to +125°C
−40°C to +125°C
Package
Description
16-Lead SOIC_IC
16-Lead SOIC_IC,
13” Tape and Reel
Package Ordering
Model1
ADuM4221ARIZ
ADuM4221ARIZ-RL
Option
RI-16-2
RI-16-2
Quantity
1
1,000
VIA, VIB
VIA, VIB
4.5
4.5
ADuM4221BRIZ
ADuM4221BRIZ-RL
VIA, VIB
VIA, VIB
7.5
7.5
Yes
Yes
−40°C to +125°C
−40°C to +125°C
16-Lead SOIC_IC
16-Lead SOIC_IC,
13” Tape and Reel
RI-16-2
RI-16-2
1
1,000
ADuM4221CRIZ
ADuM4221CRIZ-RL
VIA, VIB
VIA, VIB
11.6
11.6
Yes
Yes
−40°C to +125°C
−40°C to +125°C
16-Lead SOIC_IC
16-Lead SOIC_IC,
13” Tape and Reel
RI-16-2
RI-16-2
1
1,000
EVAL-ADuM4221EBZ
Evaluation Board
1 Z = RoHS Compliant Part.
©2020 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D17219-7/20(0)
Rev. 0 | Page 19 of 19
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