ADUM5400ARWZ2_技术文档

Quad-Channel Isolator with

Integrated DC-to-DC Converter

ADuM5400

Preliminary Technical Data

FEATURES

FUNCTIONAL BLOCK DIAGRAMS

isoPower integrated, isolated dc-to-dc converter

Regulated 3.3 V or 5 V output

500 mW output power

Quad dc-to-25 Mbps (NRZ) signal isolation channels

Schmitt trigger inputs

16-lead SOIC package with >8 mm creepage

High temperature operation: 105°C

High common-mode transient immunity: >25 kV/μs

Safety and regulatory approvals (pending)

UL recognition

2500 V rms for 1 minute per UL1577

CSA Component Acceptance Notice #5A

VDE certificate of conformity

Figure 1.

DIN V VDE V 0884-10 (VDE V 0884-10):2006-12

V

_IORM= 560 V peak

APPLICATIONS

RS-232/RS-422/RS-485 transceiver

Industrial field bus isolation

Power supply startup bias and gate drive

Isolated sensor interface

Figure 2. ADuM5400

Industrial PLC

GENERAL DESCRIPTION

The ADuM5400¹device is a quad-channel digital isolators with

isoPower™, an integrated, isolated dc-to-dc converter. Based on

the Analog Devices, Inc., iCoupler® technology, the dc-to-dc

converter provides up to 500 mW of regulated, isolated power at

either 5.0 V from a 5.0 V input supply or 3.3 V from a 3.3 V supply.

This eliminates the need for a separate, isolated dc-to-dc

converter in low power, isolated designs. The iCoupler chip scale

transformer technology is used

to isolate the logic signals and the magnetic components of the

dc-to-dc converter. The result is a small form factor, total isolation

solution.

The ADuM5400 isolator provides four independent isolation

channels in a variety of channel configurations and data rates

(see the Ordering Guide for more information).

1

Protected by U.S. Patents 5,952,849; 6,873,065; and 7075 329 B2. Other

patents pending.

Rev. PrA

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

Preliminary Technical Data

ADuM5400

TABLE OF CONTENTS

Features .............................................................................................. 1

Pin Configurations and Function Descriptions......................... 10

Typical Performance Characteristics ........................................... 11

Terminology.................................................................................... 13

Applications Information.............................................................. 14

Theory of Operation.................................................................. 14

PC Board Layout ........................................................................ 14

Thermal Analysis ....................................................................... 14

Propagation Delay-Related Parameters................................... 15

EMI Considerations................................................................... 15

DC Correctness and Magnetic Field Immunity........................... 15

Power Consumption .................................................................. 16

Power Considerations................................................................ 17

Insulation Lifetime..................................................................... 17

Outline Dimensions....................................................................... 18

Ordering Guide .......................................................................... 18

Applications....................................................................................... 1

General Description......................................................................... 1

Functional Block Diagrams............................................................. 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Electrical Characteristics—5 V Primary Input Supply/

5 V Secondary Isolated Supply ................................................... 3

Electrical Characteristics—3.3 V Primary Input Supply/

3.3 V Secondary Isolated Supply ................................................ 5

Package Characteristics ............................................................... 7

Regulatory Approvals................................................................... 7

Insulation and Safety-Related Specifications............................ 7

DIN V VDE V 0884-10 (VDE V 0884-10)

Insulation Characteristics............................................................ 8

Recommended Operating Conditions ...................................... 8

Absolute Maximum Ratings............................................................ 9

ESD Caution.................................................................................. 9

REVISION HISTORY

Rev. PrA | Page 2 of 21

Preliminary Technical Data

SPECIFICATIONS

ADuM5400

ELECTRICAL CHARACTERISTICS—5 V PRIMARY INPUT SUPPLY/5 V SECONDARY ISOLATED SUPPLY

4.5 V ≤ V_DD1≤ 5.5 V, V_SEL= V_ISO; all voltages are relative to their respective ground. All minimum/maximum specifications apply over the

entire recommended operating range, unless otherwise noted. All typical specifications are at T_A= 25°C, V_DD1= 5.0 V, V_SEL= V_ISO= 5.0 V.

Table 1.

Parameter

Symbol

Min

Typ

Max

5.4

5

Unit

Test Conditions/Comments

DC-TO-DC CONVERTER POWER SUPPLY

Setpoint

Line Regulation

Load Regulation

Output Ripple

V_ISO

4.7

5.0

1

V

I_ISO= 0 mA

I_ISO= 50 mA, V_DD1= 4.5 V to 5.5 V

I_ISO= 10 mA to 90 mA

V_ISO(LINE)

V_ISO(LOAD)

V_ISO(RIP)

mV/V

%

mV p-p

75

20 MHz bandwidth, C_BO= 0.1 μF║10 μF,

I_ISO= 90 mA

Output Noise

V_ISO(N)

200

mV p-p

20 MHz bandwidth, C_BO= 0.1 μF║10 μF,

I_ISO= 90 mA

Switching Frequency

f_OSC

f_PWM

180

625

MHz

kHz

Pulse-Width Modulation Frequency

iCoupler DATA CHANNELS

DC to 2 Mbps Data Rate¹

Maximum Output Supply Current²

Efficiency at Maximum Output Supply

Current³

I_DD1Supply Current, No V_ISOLoad

25 Mbps Data Rate (CRWZ Grade Only)

I_DD1Supply Current, No V_ISOLoad

ADuM5400

I_ISO(MAX)

100

mA

%

f ≤ 1 MHz, V_ISO> 4.5 V

I_ISO= I_ISO(2,MAX), f ≤ 1 MHz

34

19

I_DD1(Q)

30

mA

I_ISO= 0 mA, f ≤ 1 MHz

I_DD1(D)

64

mA

I_ISO= 0 mA, C_L= 15 pF, f = 12.5 MHz

Available V_ISOSupply Current⁴

ADuM5400

I_DD1Supply Current, Full V_ISOLoad

I/O Input Currents

I_ISO(LOAD)

89

290

+0.01 +20

mA

μA

V

C_L= 15 pF, f = 12.5 MHz

C_L= 0 pF, f = 0 MHz, V_DD= 5 V, I_ISO= 100 mA

I_DD1(MAX)

I_IA, I_IB, I_IC, I_ID

V_IH

−20

0.7 × V_ISO,

0.7 × V_IDD1

Logic High Input Threshold

Logic Low Input Threshold

Logic High Output Voltages

V_IL

0.3 × V_ISO,

0.3 ×

V_IDD1

V

V_OAH, V_OBH

V_OCH, V_ODH

,

V_DD1− 0.3, 5.0

V_ISO− 0.3

V_DD1− 0.5, 4.8

V_ISO− 0.3

V

I

_Ox= −20 μA, V_Ix= V_IxH

_Ox= −4 mA, V_Ix= V_IxH

_Ox= 20 μA, V_Ix= V_IxL

Logic Low Output Voltages

V_OAL, V_OBL

V_OCL, V_ODL

,

0.0

0.1

0.4

0.0

I_Ox= 4 mA, V_Ix= V_IxL

AC SPECIFICATIONS

ADuM5400ARWZ

Minimum Pulse Width

Maximum Data Rate

Propagation Delay

Pulse Width Distortion, |t_PLH− t_PHL

Propagation Delay Skew

Channel-to-Channel Matching

ADuM5400CRWZ

PW

1000

ns

Mbps

ns

C_L= 15 pF, CMOS signal levels

1

t_PHL, t_PLH

PWD

t_PSK

55

100

40

50

|

t_PSKCD/t_PSKOD

50

ns

Minimum Pulse Width

Maximum Data Rate

Propagation Delay

Pulse Width Distortion, |t_PLH− t_PHL

Change vs. Temperature

Propagation Delay Skew

PW

40

ns

Mbps

ns

C_L= 15 pF, CMOS signal levels

25

t_PHL, t_PLH

PWD

45

60

6

|

ns

5

ps/°C

ns

t_PSK

t_PSKCD

15

6

Channel-to-Channel Matching,

Rev. PrA | Page 3 of 21

Preliminary Technical Data

ADuM5400

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions/Comments

Codirectional Channels

Channel-to-Channel Matching,

Opposing Directional Channels

Output Rise/Fall Time (10% to 90%)

Common-Mode Transient Immunity

at Logic High Output

Common-Mode Transient Immunity

at Logic Low Output

t_PSKOD

15

ns

C_L= 15 pF, CMOS signal levels

V_Ix= V_DDor V_ISO, V_CM= 1000 V,

transient magnitude = 800 V

t_R/t_F

|CM_H|

2.5

35

ns

kV/μs

25

|CM_L|

f_r

35

kV/μs

Mbps

V_Ix= 0 V, V = 1000 V,

transient magnitude = 800 V

Refresh Rate

1.0

¹The contributions of supply current values for all four channels are combined at identical data rates.

²The V_ISOsupply current is available for external use when all data rates are below 2 Mbps. At data rates above 2 Mbps, the data I/O channels draw additional current

proportional to the data rate. Additional supply current associated with an individual channel operating at a given data rate can be calculated as described in the

Power Consumption section. The dynamic I/O channel load must be treated as an external load and included in the V_ISOpower budget.

³The power demands of the quiescent operation of the data channels cannot be separated from the power supply section. Efficiency includes the quiescent power

consumed by the I/O channels as part of the internal power consumption.

⁴This current is available for driving external loads at the V_ISOpin. All channels are simultaneously driven at a maximum data rate of 25 Mbps with full capacitive load

representing the maximum dynamic load conditions. Refer to the Power Consumption section for calculation of available current at less than the maximum data rate.

Rev. PrA | Page 4 of 21

Preliminary Technical Data

ADuM5400

ELECTRICAL CHARACTERISTICS—3.3 V PRIMARY INPUT SUPPLY/3.3 V SECONDARY ISOLATED SUPPLY

3.0 V ≤ V_DD1≤ 3.6 V, V_SEL= GND_ISO; all voltages are relative to their respective ground. All minimum/maximum specifications apply over

the entire recommended operating range, unless otherwise noted. All typical specifications are at T_A= 25°C, V_DD1= 3.3 V, V_ISO= 3.3 V,

V_SEL= GND_ISO.

Table 2.

Parameter

DC-TO-DC CONVERTER POWER SUPPLY

Setpoint

Line Regulation

Load Regulation

Symbol

Min

Typ

Max

3.6

5

Unit

Test Conditions/Comments

V_ISO

3.0

3.3

1

V

I_ISO= 0 mA

I_ISO= 37.5 mA, V_DD1= 3.0 V to 3.6 V

I_ISO= 6 mA to 54 mA

V_ISO(LINE)

V_ISO(LOAD)

V_ISO(RIP)

mV/V

%

mV p-p

Output Ripple

50

20 MHz bandwidth, C_BO= 0.1 μF║10 μF,

I_ISO= 54 mA

Output Noise

V_ISO(N)

130

mV p-p

20 MHz bandwidth, C_BO= 0.1 μF║10 μF,

I_ISO= 54 mA

Switching Frequency

Pulse-Width Modulation Frequency

f_OSC

f_PWM

180

625

MHz

kHz

iCoupler DATA CHANNELS

DC to 2 Mbps Data Rate¹

Maximum Output Supply Current²

Efficiency at Maximum Output Supply

Current³

I_DD1Supply Current, No V_ISOLoad

25 Mbps Data Rate (CRWZ Grade Only)

I_DD1Supply Current, No V_ISOLoad

ADuM5400

I_ISO(MAX)

60

mA

%

f ≤ 1 MHz, V_ISO> 3.0 V

I_ISO= I_ISO(2,max), f ≤ 1 MHz

36

14

I_DD1(Q)

20

mA

I_ISO= 0 mA, f ≤ 1 MHz

I_DD1(D)

41

mA

I_ISO= 0 mA, C_L= 15 pF, f = 12.5 MHz

Available V_ISOSupply Current⁴

ADuM5400

I_DD1Supply Current, Full V_ISOLoad

I/O Input Currents

I_ISO(LOAD)

43

175

+0.01

mA

μA

V

C_L= 15 pF, f = 12.5 MHz

C_L= 0 pF, f = 0 MHz, V_DD= 3.3 V, I_ISO= 60 mA

I_DD1(MAX)

I_IA, I_IB, I_IC, I_ID

V_IH

−10

0.7 × V_ISO,

0.7 × V_IDD1

+10

Logic High Input Threshold

Logic Low Input Threshold

Logic High Output Voltages

V_IL

0.3 × V_ISO,

0.3 × V_IDD1

V

V_OAH, V_OBH

V_OCH, V_ODH

,

V_DD1− 0.2, 5.0

V_ISO− 0.2

V_DD1− 0.5, 4.8

V_1SO− 0.5

I

_Ox= −20 μA, V_Ix= V_IxH

_Ox= −4 mA, V_Ix= V_IxH

_Ox= 20 μA, V_Ix= V_IxL

Logic Low Output Voltages

V_OAL, V_OBL

V_OCL, V_ODL

,

0.0

0.1

0.4

0.0

I_Ox= 4 mA, V_Ix= V_IxL

AC SPECIFICATIONS

ADuM5400ARWZ

Minimum Pulse Width

Maximum Data Rate

Propagation Delay

Pulse Width Distortion, |t_PLH− t_PHL

Propagation Delay Skew

Channel-to-Channel Matching

ADuM5400CRWZ

PW

1000

ns

Mbps

ns

C_L= 15 pF, CMOS signal levels

1

t_PHL, t_PLH

PWD

t_PSK

60

100

40

50

|

t_PSKCD/t_PSKOD

50

ns

Minimum Pulse Width

Maximum Data Rate

Propagation Delay

Pulse Width Distortion, |t_PLH− t_PHL

Change vs. Temperature

Propagation Delay Skew

Channel-to-Channel Matching,

Codirectional Channels

PW

40

ns

Mbps

ns

C_L= 15 pF, CMOS signal levels

25

t_PHL, t_PLH

PWD

45

60

6

|

ns

5

ps/°C

ns

t_PSK

t_PSKCD

45

6

Rev. PrA | Page 5 of 21

Preliminary Technical Data

ADuM5400

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions/Comments

Channel-to-Channel Matching,

Opposing Directional Channels

t_PSKOD

15

ns

C_L= 15 pF, CMOS signal levels

Output Rise/Fall Time (10% to 90%)

Common-Mode Transient Immunity

at Logic High Output

Common-Mode Transient Immunity

at Logic Low Output

Refresh Rate

t_R/t_F

|CM_H|

2.5

35

ns

kV/μs

C_L= 15 pF, CMOS signal levels

V_Ix= V_DDor V_ISO, V_CM= 1000 V,

transient magnitude = 800 V

V_Ix= 0 V, V = 1000 V,

transient magnitude = 800 V

25

|CM_L|

f_r

35

kV/μs

Mbps

1.0

¹The contributions of supply current values for all four channels are combined at identical data rates.

²The V_ISOsupply current is available for external use when all data rates are below 2 Mbps. At data rates above 2 Mbps, the data I/O channels draw additional

current proportional to the data rate. Additional supply current associated with an individual channel operating at a given data rate can be calculated as

described in the Power Consumption section. The dynamic I/O channel load must be treated as an external load and included in the V_ISOpower budget.

³The power demands of the quiescent operation of the data channels cannot be separated from the power supply section. Efficiency includes the quiescent

power consumed by the I/O channels as part of the internal power consumption.

⁴This current is available for driving external loads at the V_ISOpin. All channels are simultaneously driven at a maximum data rate of 25 Mbps with full capacitive

load representing the maximum dynamic load conditions. Refer to the Power Consumption section for calculation of available current at less than the maximum

data rate.

Rev. PrA | Page 6 of 21

Preliminary Technical Data

ADuM5400

PACKAGE CHARACTERISTICS

Table 3.

Parameter

Symbol Min Typ Max Unit Test Conditions

Resistance (Input to Output)¹

Capacitance (Input to Output)¹

Input Capacitance²

R_I-O

C_I-O

C_I

10¹²

2.2

4.0

45

Ω

pF

f = 1 MHz

IC Junction to Ambient Thermal Resistance θ_JA

°C/W Thermocouple located at center of package underside,

test conducted on four-layer board with thin traces.³

¹The device is considered a 2-terminal device: Pin 1 to Pin 8 are shorted together; and Pin 9 to Pin 16 are shorted together.

²Input capacitance is from any input data pin to ground.

³See the Thermal Analysis section for thermal model definitions.

REGULATORY APPROVALS

Table 4.

UL (Pending)

CSA (Pending)

VDE (Pending)

Recognized under the UL1577 component

recognition program¹

Approved under CSA Component

Acceptance Notice #5A

Certified according to DIN V VDE V 0884-10 (VDE

V 0884-10):2006-12²

Reinforced insulation,

2500 V rms isolation voltage

Reinforced insulation per CSA 60950-1-03 Reinforced insulation, 560 V peak

and IEC 60950-1, 300 V rms (424 V peak)

maximum working voltage

File E214100

File 205078

File 2471900-4880-0001

¹In accordance with UL1577, each ADuM5400 is proof tested by applying an insulation test voltage of ≥3000 V rms for 1 sec (current leakage detection limit = 10 μA).

²In accordance with DIN V VDE V 0884-10, each of the ADuM5400 is proof tested by applying an insulation test voltage of ≥1050 V peak for 1 sec (partial discharge

detection limit = 5 pC). The asterisk (*) marking branded on the component designates DIN V VDE V 0884-10 approval.

INSULATION AND SAFETY-RELATED SPECIFICATIONS

Table 5.

Parameter

Symbol

Value

2500

>8.0

Unit

V rms

mm

Test Conditions/Comments

Rated Dielectric Insulation Voltage

Minimum External Air Gap (Clearance)

1 minute duration

Measured from input terminals to output terminals,

shortest distance through air

Measured from input terminals to output terminals,

shortest distance path along body

L(I01)

L(I02)

Minimum External Tracking (Creepage)

>8.0

mm

Minimum Internal Gap (Internal Clearance)

0.017 min mm

Distance through insulation

Tracking Resistance (Comparative Tracking Index) CTI

Isolation Group

>175

IIIa

V

DIN IEC 112/VDE 0303 Part 1

Material Group (DIN VDE 0110, 1/89, Table 1)

Rev. PrA | Page 7 of 21

Preliminary Technical Data

ADuM5400

DIN V VDE V 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS

These isolators are suitable for reinforced electrical isolation only within the safety limit data. Maintenance of the safety data is ensured by

protective circuits. The asterisk (*) marking on packages denotes DIN V VDE V 0884-10 approval.

Table 6.

Description

Conditions

Symbol Characteristic Unit

Installation Classification per DIN VDE 0110

For Rated Mains Voltage ≤ 150 V rms

For Rated Mains Voltage ≤ 300 V rms

For Rated Mains Voltage ≤ 400 V rms

Climatic Classification

Pollution Degree per DIN VDE 0110, Table 1

Maximum Working Insulation Voltage

Input-to-Output Test Voltage, Method B1

I to IV

I to III

I to II

40/105/21

2

V_IORM

V_PR

560

1050

V peak

V_IORM× 1.875 = V_PR, 100% production test, t_m= 1 sec,

partial discharge < 5 pC

Input-to-Output Test Voltage, Method A

After Environmental Tests Subgroup 1

After Input and/or Safety Test Subgroup 2 V_IORM× 1.2 = V_PR, t_m= 60 sec, partial discharge < 5 pC

and Subgroup 3

V_PR

V_IORM× 1.6 = V_PR, t_m= 60 sec, partial discharge < 5 pC

896

672

V peak

Highest Allowable Overvoltage

Safety Limiting Values

Transient overvoltage, t_TR= 10 sec

Maximum value allowed in the event of a failure

(see Figure 3)

V_TR

4000

V peak

Case Temperature

Side 1 Current

Side 2 Current

T_S

I_S1

I_S2

R_S

150

265

335

>10⁹

°C

mA

Ω

Insulation Resistance at T_S

V_IO= 500 V

600

500

400

300

200

100

0

50

100

150

200

AMBIENT TEMPERATURE (°C)

Figure 3. Thermal Derating Curve, Dependence of Safety Limiting Values on Case Temperature, per DIN EN 60747-5-2

RECOMMENDED OPERATING CONDITIONS

Table 7.

Parameter

Symbol

Min

Max

Unit

Operating Temperature

Supply Voltages¹

V_DD1@ V_SEL= 0 V

V_DD1@ V_SEL= 5 V

Minimum Load

T_A

−40

+105

°C

V_DD

I_ISO(MIN)

3.0

4.5

10

3.6

5.5

V

mA

¹All voltages are relative to their respective ground.

Rev. PrA | Page 8 of 21

Preliminary Technical Data

ADuM5400

ABSOLUTE MAXIMUM RATINGS

Ambient temperature = 25°C, unless otherwise noted.

Table 8.

Parameter

Storage Temperature (T_ST)

Ambient Operating Temperature (T_A)

Supply Voltages (V_DD, V_ISO

Input Voltage

(V_IA, V_IB, V_IC, V_ID, V_SEL

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Rating

−55°C to +150°C

−40°C to +105°C

−0.5 V to +7.0 V

−0.5 V to V_DDI+ 0.5 V

1

)

1, 2

)

Output Voltage

−0.5 V to V_DDO+ 0.5 V

(V_OA, V_OB, V_OC, V_OD)^{1, 2}

Average Output Current per Pin³

Side 1 (I_O1)

ESD CAUTION

−18 mA to +18 mA

Side 2 (I_OISO

)

−22 mA to +22 mA

−100 kV/μs to +100 kV/μs

Common-Mode Transients⁴

¹All voltages are relative to their respective ground.

²V_DDIand V_DDOrefer to the supply voltages on the input and output sides of

a given channel, respectively. See the PC Board Layout section.

³See Figure 3 for maximum rated current values for various temperatures.

⁴Refers to common-mode transients across the insulation barrier. Common-

mode transients exceeding the absolute maximum ratings may cause latch-up

or permanent damage.

Table 9. Maximum Continuous Working Voltage Supporting 50-Year Minimum Lifetime¹

Parameter

Max

Unit

Applicable Certification

AC Voltage, Bipolar Waveform

AC Voltage, Unipolar Waveform

Basic Insulation

Reinforced Insulation

DC Voltage

424

V peak

All certifications

600

560

V peak

Working voltage per IEC 60950-1

Working voltage per VDE V 0884-10

Basic Insulation

Reinforced Insulation

600

560

V peak

Working voltage per IEC 60950-1

Working voltage per VDE V 0884-10

¹Refers to the continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for more information.

Table 10. Truth Table (Positive Logic)

V_Ix

V_SEL

Input

V_DD1

State

V_DD1

Input (V)

V_ISO

State

V_ISO

Output (V)

V_Ox

Input¹

Output¹

Notes

High

Low

High

Low

High

Low

High

Low

High

Low

High

Powered

5.0

3.3

5.0

3.3

Powered

5.0

3.3

5.0

High

Low

High

Low

High

Low

High

Low

Normal operation, data is high

Normal operation, data is low

Normal operation, data is high

Normal operation, data is low

Configuration not recommended

¹V_Ixand V_Oxrefer to the input and output signals of a given channel (A, B, C, or D).

Rev. PrA | Page 9 of 21

Preliminary Technical Data

ADuM5400

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

Figure 4. ADuM5400 Pin Configuration

Table 11. ADuM5400 Pin Function Descriptions

Pin No. Mnemonic Description

1

V_DD1

Primary Supply Voltage, 3.0 V to 5.5 V.

2, 8

GND₁

Ground 1. Ground reference for isolator primary. Pin 2 and Pin 8 are internally connected, and it is recommended that both

pins be connected to a common ground.

3

V_IA

Logic Input A.

4

V_IB

Logic Input B.

5

V_IC

Logic Input C.

6

V_ID

Logic Input D.

7

NC

Make no connection to this pin.

9, 15

GND_ISO

Ground Reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected, and it is recommended that both pins be

connected to a common ground.

10

V_SEL

Output Voltage Selection. When V_SEL= V_ISO, the V_ISOsetpoint is 5.0 V. When V_SEL= GND_ISO, the V_ISOsetpoint is 3.3 V.

V_DD1and V_ISOvoltages must be in the same operating range to guarantee proper operation of the data channels.

11

12

13

14

16

V_OD

V_OC

V_OB

V_OA

V_ISO

Logic Output D.

Logic Output C.

Logic Output B.

Logic Output A.

Secondary Supply Voltage Output for External Loads, 3.3 V (V_SELLow) or 5.0 V (V_SELHigh). V_DD1and V_ISOvoltages must be

in the same operating range to guarantee proper operation of the data channels.

Rev. PrA | Page 10 of 21

Preliminary Technical Data

ADuM5400

TYPICAL PERFORMANCE CHARACTERISTICS

40

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

35

30

25

20

POWER

15

3.3V IN/3.3V OUT

5V IN/5V OUT

10

I

DD

5

0

0.02

0.04

0.06

0.08

0.10

0.12

3.0

3.5

4.0

4.5

5.0

5.5

6.0

6.5

OUTPUT CURRENT (A)

INPUT VOLTAGE (V)

Figure 5. Typical Power Supply Efficiency at 5 V/5 V and 3.3 V/3.3 V

Figure 8. Typical Short-Circuit Input Current and Power vs. V_DDSupply Voltage

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

10% LOAD

90% LOAD

V

= 5V, V

ISO

= 5V

= 3.3V

DD1

0.2

0.1

0

= 3.3V, V

ISO

(100µs/DIV)

0

0.02

0.04

0.06

(A)

0.08

0.10

0.12

I

ISO

Figure 6. Typical Total Power Dissipation vs. I_ISOwith Data Channels Idle

Figure 9. Typical V_ISOTransient Load Response, 5 V Output,

10% to 90% Load Step

0.12

0.10

0.08

0.06

0.04

10% LOAD

90% LOAD

3.3V IN/3.3V OUT

5V IN/5V OUT

0.02

0

(100µs/DIV)

0

0.05

0.10

0.15

0.20

0.25

0.30

0.35

INPUT CURRENT (A)

Figure 10. Typical Transient Load Response, 3 V Output,

10% to 90% Load Step

Figure 7. Typical Isolated Output Supply Current, I_ISO, as a Function of External

Load, No Dynamic Current Draw at 5 V/5 V and 3.3 V/3.3 V

Rev. PrA | Page 11 of 21

Preliminary Technical Data

ADuM5400

20

16

12

8

5V IN/5V OUT

3.3V IN/3.3V OUT

4

0

BW = 20MHz (400ns/DIV)

0

5

10

15

20

25

DATA RATE (Mbps)

Figure 11. Typical V_ISO= 5 V Output Voltage Ripple at 90% Load

Figure 14. Typical I_CHSupply Current per Reverse Data Channel

(15 pF Output Load)

5

4

3

5V

2

3.3V

1

0

5

10

15

20

25

BW = 20MHz (400ns/DIV)

DATA RATE (Mbps)

Figure 12. Typical V_ISO= 3.3 V Output Voltage Ripple at 90% Load

Figure 15. Typical I_ISO(D)Dynamic Supply Current per Input

20

3.0

5V IN/5V OUT

3.3V IN/3.3V OUT

2.5

2.0

1.5

1.0

0.5

0

16

12

8

5V

3.3V

4

0

5

10

15

20

25

0

5

10

15

20

25

DATA RATE (Mbps)

Figure 16. Typical I_ISO(D)Dynamic Supply Current per Output

(15 pF Output Load)

Figure 13. Typical I_CHSupply Current per Forward Data Channel

(15 pF Output Load)

Rev. PrA | Page 12 of 21

Preliminary Technical Data

TERMINOLOGY

ADuM5400

t_PLHPropagation Delay

_PLHpropagation delay is measured from the 50% level of the

rising edge of the V_Ixsignal to the 50% level of the rising edge of

I_DD1(Q)

t

I_DD1(Q)is the minimum operating current drawn at the V_DD1pin

when there is no external load at V_ISOand the I/O pins are oper-

ating below 2 Mbps, requiring no additional dynamic supply

current. I_DDIO(Q)reflects the minimum current operating

condition.

the V_Oxsignal.

Propagation Delay Skew (t_PSK

t

)

_PSKis the magnitude of the worst-case difference in t_PHLand/or

t_PLHthat is measured between units at the same operating

temperature, supply voltages, and output load within the

recommended operating conditions.

I_DD1(D)

I

_DD1(D)is the typical input supply current with all channels

simultaneously driven at maximum data rate of 25 Mbps with

full capacitive load representing the maximum dynamic load

conditions. Resistive loads on the outputs should be treated

separately from the dynamic load.

Channel-to-Channel Matching

Channel-to-channel matching is the absolute value of the

difference in propagation delays between the two channels

when operated with identical loads.

I_DD1(MAX)

I

_DD1(MAX)is the input current under full dynamic and V_ISOload

Minimum Pulse Width

The minimum pulse width is the shortest pulse width at which

the specified pulse width distortion is guaranteed.

conditions.

t

_PHLPropagation Delay

t_PHLpropagation delay is measured from the 50% level of the

Maximum Data Rate

falling edge of the V_Ixsignal to the 50% level of the falling edge

of the V_Oxsignal.

The maximum data rate is the fastest data rate at which the

specified pulse width distortion is guaranteed.

Rev. PrA | Page 13 of 21

Preliminary Technical Data

ADuM5400

APPLICATIONS INFORMATION

THEORY OF OPERATION

BYPASS < 2mm

V

DD1

ISO

The dc-to-dc converter section of the ADuM5400 works on

principles that are common to most modern power supplies. It

is a secondary side controller architecture with isolated pulse-

width modulation (PWM) feedback. V_DD1power is supplied to an

oscillating circuit that switches current into a chip-scale air core

transformer. Power transferred to the secondary side is rectified

and regulated to either 3.3 V or

GND

1

ISO

V

/V

V

/V

IA OA

OA IA

/V

IB OB

/V

OB IB

/V

IC OC

/V

OC IC

/V

IC OD

/V

OD ID

SEL

GND

ISO

1

Figure 17. Recommended Printed Circuit Board Layout

5 V. The secondary (V_ISO) side controller regulates the output by

creating a PWM control signal that is sent to the primary (V_DD1

side by a dedicated iCoupler data channel. The PWM modulates

the oscillator circuit to control the power being sent to the secon-

dary side. Feedback allows for significantly higher power and

efficiency.

)

In applications involving high common-mode transients, care

should be taken to ensure that board coupling across the isolation

barrier is minimized. Furthermore, the board layout should be

designed such that any coupling that does occur equally affects

all pins on a given component side. Failure to ensure this could

cause voltage differentials between pins, exceeding the Absolute

Maximum Ratings specified in Table 8, thereby leading to latch-up

and/or permanent damage.

The ADuM5400 implements under voltage lockout (UVLO) with

hysteresis on the V_DD1power input. This feature ensures that the

converter does not go into oscillation due to noisy input power or

slow power on ramp rates.

The ADuM5400 is a power device that dissipates about 1 W of

power when fully loaded and running at maximum speed. Because

it is not possible to apply a heat sink to an isolation device, the

devices primarily depend on heat dissipation into the PCB through

the GND pins. If the devices are used at high ambient

temperatures, care should be taken to provide a thermal path

from the GND pins to the PCB ground plane. The board layout in

Figure 17 shows enlarged pads for Pin 8 and Pin 9. Large

diameter vias should be implemented from the pad to the

ground, and power planes should be used to reduce inductance.

Multiple vias in the thermal pads can significantly reduce

temperatures inside the chip. The dimensions of the expanded

pads are left to the discretion of the designer and the available

board space.

A minimum load current of 10 mA is recommended to ensure

optimum load regulation. Smaller loads can generate excess noise

on chip due to short or erratic PWM pulses. Excess noise gener-

ated this way can cause data corruption, in some circumstances.

PC BOARD LAYOUT

The ADuM5400 digital isolator with 0.5 W isoPower integrated

dc-to-dc converters requires no external interface circuitry for

the logic interfaces. Power supply bypassing is required at the

input and output supply pins (Figure 17). Note that a low ESR

bypass capacitor is required between Pin 1 and Pin 2, as close to

the chip pads as possible.

The power supply section of the ADuM5400 uses a very high

oscillator frequency to efficiently pass power through its chip

scale transformers. In addition, normal operation of the data

section of the iCoupler introduces switching transients on the

power supply pins. Bypass capacitors are required for several

operating frequencies. Noise suppression requires a low

inductance, high frequency capacitor; ripple suppression and

proper regulation require a large value capacitor. These are most

conveniently connected between Pin 1 and Pin 2 for V_DD1and

between Pin 15 and Pin 16 for V_ISO. To suppress noise and reduce

ripple, a parallel combination of at least two capacitors is

required. The recommended capacitor values are 0.1 μF and 33

μF for V_DD1. The smaller capacitor must have a low ESR; for

example, use of a ceramic capacitor is advised.

THERMAL ANALYSIS

The ADuM5400 part consists of four internal die attached to a

split lead frame with two die attach paddles. For the purposes of

thermal analysis, the die are treated as a thermal unit, with the

highest junction temperature reflected in the θ_JAfrom Table 3.

The value of θ_JAis based on measurements taken with the parts

mounted on a JEDEC standard, four-layer board with fine width

traces and still air. Under normal operating conditions, the

ADuM5400 device operates at full load across the full temperature

range without derating the output current. However, following

the recommendations in the PC Board Layout section decreases

thermal resistance to the PCB, allowing increased thermal margins

in high ambient temperatures.

Note that the total lead length between the ends of the low ESR

capacitor and the input power supply pin must not exceed 2 mm.

Installing the bypass capacitor with traces more than 2 mm in

length may result in data corruption. A bypass between Pin 1 and

Pin 8 and between Pin 9 and Pin 16 should also be considered

unless both common ground pins are connected together close

to the package.

Rev. PrA | Page 14 of 21

Preliminary Technical Data

ADuM5400

The limitation on the ADuM5400 magnetic field immunity is set

by the condition in which induced voltage in the transformer

receiving coil is sufficiently large to either falsely set or reset the

decoder. The following analysis defines the conditions under

which this can occur.

PROPAGATION DELAY-RELATED PARAMETERS

Propagation delay is a parameter that describes the time it takes

a logic signal to propagate through a component (see Figure 18).

The propagation delay to a logic low output may differ from the

propagation delay to a logic high.

The 3.3 V operating condition of the ADuM5400 is examined

because it represents the most susceptible mode of operation.

INPUT (V

)

50%

Ix

The pulses at the transformer output have an amplitude of >1.0 V.

The decoder has a sensing threshold of about 0.5 V, thus estab-

lishing a 0.5 V margin in which induced voltages can be tolerated.

The voltage induced across the receiving coil is given by

t_PLH

t_PHL

OUTPUT (V

)

50%

Ox

Figure 18. Propagation Delay Parameters

2

Pulse width distortion is the maximum difference between

these two propagation delay values and is an indication of how

accurately the input signal timing is preserved.

V = (−dβ/dt)∑πr_n; n = 1, 2, … , N

where:

β is magnetic flux density (gauss).

N is the number of turns in the receiving coil.

r_nis the radius of the n^thturn in the receiving coil (cm).

Channel-to-channel matching refers to the maximum amount

the propagation delay differs between channels within a single

ADuM5400 component.

Given the geometry of the receiving coil in the ADuM5400, and

an imposed requirement that the induced voltage be, at most, 50%

of the 0.5 V margin at the decoder, a maximum allowable

magnetic field is calculated as shown in Figure 19.

Propagation delay skew refers to the maximum amount the

propagation delay differs between multiple ADuM540x

components operating under the same conditions.

100

EMI CONSIDERATIONS

The dc-to-dc converter section of the ADuM5400 component

must, of necessity, operate at very high frequency to allow

efficient power transfer through the small transformers. This

creates high frequency currents that can propagate in circuit board

ground and power planes, causing edge and dipole radiation.

Grounded enclosures are recommended for applications that use

these devices. If grounded enclosures are not possible, good RF

design practices should be followed in layout of the PCB. See

www.analog.com for the most current PCB layout

10

1

0.1

0.01

0.001

recommendations specifically for the ADuM5400.

DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY

1k

10k

100k

1M

10M

100M

Positive and negative logic transitions at the isolator input cause

narrow (~1 ns) pulses to be sent to the decoder via the transformer.

The decoder is bistable and is, therefore, either set or reset by

the pulses, indicating input logic transitions. In the absence of

logic transitions at the input for more than 1 μs, periodic sets of

refresh pulses indicative of the correct input state are sent to ensure

dc correctness at the output. If the decoder receives no internal

pulses of more than approximately 5 μs, the input side is assumed

to be unpowered or nonfunctional, in which case the isolator

output is forced to a default state (see Table 10) by the watchdog

timer circuit. This situation should occur in the ADuM5400

device only during power-up and power-down operations.

MAGNETIC FIELD FREQUENCY (Hz)

Figure 19. Maximum Allowable External Magnetic Flux Density

For example, at a magnetic field frequency of 1 MHz, the

maximum allowable magnetic field of 0.2 kgauss induces a

voltage of 0.25 V at the receiving coil. This is about 50% of the

sensing threshold and does not cause a faulty output transition.

Similarly, if such an event occurs during a transmitted pulse

(and is of the worst-case polarity), it reduces the received pulse

from >1.0 V to 0.75 V, which is still well above the 0.5 V sensing

threshold of the decoder.

Rev. PrA | Page 15 of 21

Preliminary Technical Data

ADuM5400

Dynamic I/O current is consumed only when operating a channel

at speeds higher than the refresh rate of f_r. The dynamic current

of each channel is determined by its data rate. Figure 13 shows the

current for a channel in the forward direction, meaning that the

input is on the V_DD1side of the part. Figure 14 shows the current

for a channel in the reverse direction, meaning that the input is on

the V_ISOside of the part. Both figures assume a typical 15 pF load.

The preceding magnetic flux density values correspond to specific

current magnitudes at given distances from the ADuM5400

transformers. Figure 20 expresses these allowable current

magnitudes as a function

of frequency for selected distances. As shown in Figure 20,

the ADuM5400 is extremely immune and can be affected only by

extremely large currents operated at high frequency very close to

the component. For the 1 MHz example, a 0.5 kA current would

need to be placed 5 mm away from the ADuM5400 to affect

component operation.

The following relationship allows the total I_DD1current to be

calculated:

I

_DD1= (I_ISO× V_ISO)/(E × V_DD1) + Σ I_CHn; n = 1 to 4

(1)

1k

where:

DISTANCE = 1m

I

_DD1is the total supply input current.

_CHnis the current drawn by a single channel determined from

100

Figure 13 or Figure 14, depending on channel direction.

_ISOis the current drawn by the secondary side external load.

I

10

E is the power supply efficiency at 100 mA load from Figure 5

DISTANCE = 100mm

at the V_ISOand V_DD1condition of interest.

1

DISTANCE = 5mm

The maximum external load can be calculated by subtracting

the dynamic output load from the maximum allowable load.

0.1

I

_ISO(LOAD)= I_ISO(MAX)− Σ I_ISO(D)n; n = 1 to 4

where:

_ISO(LOAD)is the current available to supply an external secondary

side load.

_ISO(MAX)is the maximum external secondary side load current

available at V_ISO

_ISO(D)nis the dynamic load current drawn from V_ISOby an input

or output channel, as shown in Figure 15 and Figure 16.

(2)

0.01

1k

10k

100k

1M

10M

100M

I

MAGNETIC FIELD FREQUENCY (Hz)

Figure 20. Maximum Allowable Current for Various Current-to- ADuM5400

Spacings

I

.

Note that in combinations of strong magnetic field and high

frequency, any loops formed by printed circuit board traces

could induce error voltages sufficiently large to trigger the

thresholds of succeeding circuitry. Care should be taken in

the layout of such traces to avoid this possibility.

I

The preceding analysis assumes a 15 pF capacitive load on each

data output. If the capacitive load is larger than 15 pF, the additional

current must be included in the analysis of I_DD1and I_ISO(LOAD)

.

POWER CONSUMPTION

The V_DD1power supply input provides power to the iCoupler

data channels, as well as to the power converter. For this reason,

the quiescent currents drawn by the data converter and the

primary and secondary I/O channels cannot be determined

separately. All of these quiescent power demands have been

combined into the I_DD1(Q)current, as shown in Figure 21. The

total I_DD1supply current is equal to the sum of the quiescent

operating current; the dynamic current, I_DD1(D), demanded by

the I/O channels; and any external I_ISOload.

I

ISO

DD1(Q)

E

CONVERTER

PRIMARY

CONVERTER

SECONDARY

I

DD1(D)

I

ISO(D)

DDP(D)

PRIMARY

DATA

I/O

SECONDARY

DATA

I/O

4CH

Figure 21. Power Consumption Within the ADuM5400

Rev. PrA | Page 16 of 21

Preliminary Technical Data

ADuM5400

for several operating conditions are determined, allowing calcu-

lation of the time to failure at the working voltage of interest. The

values shown in Table 9 summarize the peak voltages for 50 years

of service life in several operating conditions. In many cases, the

working voltage approved by agency testing is higher than the

50-year service life voltage. Operation at working voltages higher

than the service life voltage listed leads to premature insulation

failure.

POWER CONSIDERATIONS

The ADuM5400 power input, the data input channels on the

primary side, and the data input channels on the secondary side

are all protected from premature operation by UVLO circuitry.

Below the minimum operating voltage, the power converter holds

its oscillator inactive, and all input channel drivers and refresh

circuits are idle. Outputs are held in a low state. This is to prevent

transmission of undefined states during power-up and power-

down operations.

The insulation lifetime of the ADuM5400 depends on the voltage

waveform type imposed across the isolation barrier. The

iCoupler insulation structure degrades at different rates,

depending on whether the waveform is bipolar ac, unipolar ac, or

dc. Figure 22, Figure 23, and Figure 24 illustrate these different

isolation voltage waveforms.

During application of power to V_DD1, the primary side circuitry

is held idle until the UVLO preset voltage is reached. At that time,

the data channels are initialized to their default low output state

until they receive data pulses from the secondary side.

The primary side input channels sample the input and send a pulse

to the inactive secondary output. The secondary side converter

begins to accept power from the primary, and the V_ISOvoltage

starts to rise. When the secondary side UVLO is reached, the

secondary side outputs are initialized to their default low state

until data, either a transition or a dc refresh pulse, is received

from the corresponding primary side input. It can take up to

1 μs after the secondary side is initialized for the state of the

output to correlate with the primary side input.

Bipolar ac voltage is the most stringent environment. A 50-year

operating lifetime under the bipolar ac condition determines

the Analog Devices recommended maximum working voltage.

In the case of unipolar ac or dc voltage, the stress on the insulation

is significantly lower. This allows operation at higher working

voltages while still achieving a 50-year service life. The working

voltages listed in Table 9 can be applied while maintaining the

50-year minimum lifetime, provided the voltage conforms to either

the unipolar ac or dc voltage cases. Any cross-insulation voltage

waveform that does not conform to Figure 23 or Figure 24

should be treated as a bipolar ac waveform, and its peak voltage

should be limited to the 50-year lifetime voltage value listed in

Table 9.

Secondary side inputs sample their state and transmit it to the

primary side. Outputs are valid one propagation delay after the

secondary side becomes active.

Because the rate of charge of the secondary side is dependent

on loading conditions, input voltage, and output voltage level

selected, care should be taken in the design to allow the converter

to stabilize before valid data is required.

RATED PEAK VOLTAGE

0V

When power is removed from V_DD1, the primary side converter

and coupler shut down when the UVLO level is reached. The

secondary side stops receiving power and starts to discharge.

The outputs on the secondary side hold the last state that they

received from the primary until either the UVLO level is reached

and the outputs are placed in their default low state, or the outputs

detect a lack of activity from the inputs and the outputs are set

to their default value before the secondary power reaches UVLO.

Figure 22. Bipolar AC Waveform

RATED PEAK VOLTAGE

0V

Figure 23. DC Waveform

INSULATION LIFETIME

RATED PEAK VOLTAGE

All insulation structures eventually break down when subjected

to voltage stress over a sufficiently long period. The rate of insu-

lation degradation is dependent on the characteristics of the voltage

waveform applied across the insulation. Analog Devices conducts

an extensive set of evaluations to determine the lifetime of the

insulation structure within the ADuM5400.

0V

NOTES:

1. THE VOLTAGE IS SHOWN AS SINUSOIDAL FOR ILLUSTRATION

PURPOSES ONLY. IT IS MEANT TO REPRESENT ANY VOLTAGE

WAVEFORM VARYING BETWEEN 0 AND SOME LIMITING VALUE.

THE LIMITING VALUE CAN BE POSITIVE OR NEGATIVE, BUT THE

VOLTAGE CANNOT CROSS 0V.

Figure 24. Unipolar AC Waveform

Accelerated life testing is performed using voltage levels higher

than the rated continuous working voltage. Acceleration factors

Rev. PrA | Page 17 of 21

Preliminary Technical Data

ADuM5400

OUTLINE DIMENSIONS

10.50 (0.4134)

10.10 (0.3976)

16

1

9

8

7.60 (0.2992)

7.40 (0.2913)

10.65 (0.4193)

10.00 (0.3937)

0.75 (0.0295)

0.25 (0.

0098)

1.27 (0.0500)

BSC

45°

2.65 (0.1043)

2.35 (0.0925)

0.30 (0.0118)

0.10 (0.0039)

8°

0°

COPLANARITY

0.10

SEATING

PLANE

0.51 (0.0201)

0.31 (0.0122)

1.27 (0.0500)

0.40 (0.0157)

0.33 (0.0130)

0.20 (0.0079)

COMPLIANT TO JEDEC STANDARDS MS-013-AA

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS

(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

Figure 25. 16-Lead Standard Small Outline Package [SOIC_W]

Wide Body (RW-16)

Dimensiosn shown in millimeters and (inches)

ORDERING GUIDE

Number

Maximum Maximum

Maximum

of Inputs, of Inputs, Data Rate Propagation

Pulse Width

Temperature Package

Package

Model

V_DD1Side

V_ISOSide

(Mbps)

Delay, 5 V (ns) Distortion (ns) Range (°C)

Description Option

ADuM5400ARWZ^{1, 2}

4

0

1

100

40

−40 to +105

16-Lead

SOIC_W

RW-16

ADuM5400CRWZ^{1, 2}

4

0

25

60

6

−40 to +105

16-Lead

SOIC_W

RW-16

¹Tape and reel are available. The addition of an RL suffix designates a 13” (1,000 units) tape and reel option.

²Z = RoHS Compliant Part.

Rev. PrA | Page 18 of 21

Preliminary Technical Data

NOTES

ADuM5400

Rev. PrA | Page 19 of 21

Preliminary Technical Data

ADuM5400

NOTES

Rev. PrA | Page 20 of 21

Preliminary Technical Data

NOTES

ADuM5400

registered trademarks are the property of their respective owners.

PR06577-0-5/08(PrA)

Rev. PrA | Page 21 of 21


型号：	ADUM5400ARWZ2
厂家：	ADI
描述：	Quad-Channel Isolator with Integrated DC-to-DC Converter 四通道隔离器，集成DC- DC转换器转换器
文件：	总21页 (文件大小：381K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADUM5400ARWZ2 [ADI]

相关型号：

ADUM5400ARWZRL

ADUM5400CRWZ

ADUM5400CRWZ-RL

ADUM5400CRWZ1

ADUM5400CRWZ2

ADUM5400CRWZRL

ADUM5400_08

ADUM5400_VA

ADUM5401

ADuM5401ARWZ

ADUM5401ARWZ-RL

ADUM5401ARWZ1