ADUM6132 [ADI]
Isolated Half-Bridge Driver with Integrated Isolated High-Side Supply; 隔离半桥驱动器，集成隔离高端电源
| 型号： | ADUM6132 |
| 厂家： | 
ADI |
| 描述： | Isolated Half-Bridge Driver with Integrated Isolated High-Side Supply |
| 文件： | 总12页 (文件大小：264K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Isolated Half-Bridge Driver
with Integrated Isolated High-Side Supply
ADuM6132
PRELIMINARY TECHNICAL DATA
FEATURES
GENERAL DESCRIPTION
Integrated Isolated High Side Supply
250mW Isolated DC/DC converter
The ADuM61321 is an isolated half-bridge gate driver that employs
Analog Devices’ iCoupler® technology to provide an isolated high-
200mA Output Sink Current, 200mA Output Source Current
High common-mode transient immunity: > 25 kV/μs
High temperature operation: 105°C
Wide body SOIC 16-lead package
Safety and regulatory approvals (pending)
UL recognition
3750 V rms for 1 minute per UL 1577
CSA component acceptance notice #5A
CSA/IEC 60950-1, 400 VRMS
side driver with an integrated 300 mW high-side supply. This
supply, provided by an internal isolated DC/DC converter powers
not only the ADuM6132’s high-side output but also any external
buffer circuitry that would commonly be used with the
ADuM6132. This eliminates the cost, space, and performance
difficulties associated with external supply configurations such
as a bootstrap circuitry. The architecture isolates the high side
channel and high side power from the control and low side
interface circuitry. Care has been taken to ensure close matching
between the high and low side driver timing characteristics,
reduces the need for dead time margin.
VDE certificate of conformity
DIN V VDE 0884-10 (VDE V 0884-10):2006-12
VIORM = 560 V peak
In comparison to gate drivers employing high voltage level
translation methodologies, the ADuM6132 offers the benefit of
true, galvanic isolation. The differential voltage between high and
low side channels can be as high as 1131V in some configurations
(see Table 7).
APPLICATIONS
MOSFET/IGBT Gate Drive
Motor Drives
Solar Panel Inverters
Power Supplies
1 Protected by U.S. Patents 5,952,849; 6,873,065; and 7,075 329. Other patents
pending.
FUNCTIONAL BLOCK DIAGRAM
Figure 1. ADuM6132 Functional Block Diagram
Rev. PrG
March 19, 2008
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703
www.analog.com
© 2008 Analog Devices, Inc. All rights reserved.
ADuM6132
PRELIMINARY TECHNICAL DATA
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
All voltages are relative to their respective ground. 4.5 ≤ VDD = VDDL ≤ 5.5 V, 12.5 ≤ VDDB ≤ 17.0 V, VDDA = VISO. All min/max specifications
apply over the entire recommended operating range, unless otherwise noted. All typical specifications are at TA = 25°C, VDD = VDDL
=
5.0V, VDDB = 15 V, VDDA = VISO
.
Table 1.
Parameter
Symbol
Min
Typ
Max
Unit Test Conditions
DC SPECIFICATIONS
Isolated Power Supply
Input Current, Quiescent
Input Current, Loaded
250
350
mA
mA
mA
V
IISO=0, DC signal inputs
IDD
IDD
IISO(max)
VISO
(Q)
IISO = IISO(max,)
12.5 < VISO < 17.0
0 < IISO < 22
Maximum Output Current1
22
12.5
Output Voltage
15
17
Logic Supply
Input Current
IDDL
1.8
3.0
mA
Output Supplies, Channel A or Channel B2
Supply Current, Quiescent
Supply Current, fIN=20kHz
Supply Current, fIN=100kHz
Supply Current, fIN=1000kHz
Logic Inputs, Channel A or Channel B
Input Current
Logic High Input Voltage
Logic Low Input Voltage
Outputs, Channel A or Channel B
Channel A High Level Output Voltage
Channel B High Level Output Voltage
Low Level Output Voltages
High Level Output Current, Peak3
Low Level Output Current, Peak3
Undervoltage Lockout, VDDA or VDDB Supply
Positive going threshold
Negative going threshold
Hysteresis
1.0
1.1
1.3
4.5
2
mA
mA
mA
mA
IDDA , IDDB
(Q)
(Q)
2.1
2.3
5.5
CL = 200 pF
CL = 200 pF
CL = 200 pF
IDDA(20) IDDB(20)
,
IDDA(100) IDDB(100)
,
IDDA(1000) IDDB(1000)
,
IIA, IIB
VIAH, VIBH
VIAL, VIBL
−10
0.7 xVDDL
0.01
10
μA
V
V
0 ≤ VIA, VIB ≤ 5.5V
0.3 x VDDL
VOAH
VOBH
VOAL,VOBL
IOAH, IOBH
IOAL, IOBL
VDDA –0.1
VDDB –0.1
V
V
V
mA
mA
IOAH = -1 mA
IOBH = -1 mA
IOAL, IOBL = +1 mA
0.1
200
200
VDDAUV+, VDDBUV+
VDDAUV-, VDDBUV-
VDDBUVH, VDDBUVH
11.0
10.0
0.8
11.7
10.7
1.0
12.3
11.2
1.2
V
V
V
Undervoltage Lockout, VDDL Supply
Positive going threshold
Negative going threshold
Hysteresis
VDDLUV+
VDDLUV-
VDDLUVH
3.5
3.0
0.3
4.2
3.7
V
V
V
SWITCHING SPECIFICATIONS
Minimum Pulse Width4
Maximum Switching Frequency5
Propagation Delay6
PW
fIN
tPHL, tPLH
50
ns
KHz
ns
CL = 200 pF
CL = 200 pF
CL = 200 pF
1000
40
60
100
Change versus temperature
100
ps/°
C
Pulse-Width Distortion, |tPLH−tPHL
Channel-to-Channel Matching, Rising or
Falling Matching Edge Polarity7
|
PWD
tM2
10
20
ns
ns
CL = 200 pF
CL = 200 pF
Channel-to-Channel Matching, Rising vs.
tM1
20
ns
CL = 200 pF
Falling Opposite Edge Polarity8
Part-to-Part Matching9
Output Rise Time (10%−90%)
Output Fall Time (10%−90%)
60
15
15
ns
ns
ns
CL = 200 pF
CL = 200 pF
CL = 200 pF
tR
tF
Rev. PrG| Page 2 of 12
PRELIMINARY TECHNICAL DATA
ADuM6132
1 The maximum output current is the maximum isolated supply current that the ADuM6132 can provide. This current supports external loads as well as the needs of
the ADuM6132 Channel A output circuitry. This is achieved via external connection of VISO to VDDA and GNDISO to GNDA (Figure 3). The net current available to power
external loads is the ADuM6132 output current IISO less the Channel A supply current IDDA
.
2 IDDA is supplied by the output of the integrated isolated dc/dc power as described in Footnote 1 above. IDDB is supplied by external power connection to VDDB pin. See
Figure 3.
3 Duration less than 1 second. Average output current must conform to the limit shown under the Absolute Maximum Ratings.
4 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. Operation below the minimum pulse width is not
recommended.
5 The maximum switching frequency is the maximum signal frequency at which the specified timing parameters are guaranteed. Operation beyond the maximum
frequency is not recommended since high switching rates can cause droop in the output supply voltage.
6 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is
measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
7 “Channel-to-channel matching, rising or falling matching edge polarity” is the magnitude of the propagation delay difference between two channels of the same part
when both inputs are either both rising or falling edges. The loads on each channel are equal.
8 “Channel-to-channel matching, rising vs. falling opposite edge polarity” is the magnitude of the propagation delay difference between two channels of the same part
when one input is a rising edge and one input is a falling edge. The loads on each channel are equal.
9 Part-to-part matching is the magnitude of the propagation delay difference between the same channels of two different parts. This includes rising vs. rising, falling vs.
falling, or rising vs. falling edges. The supply voltages, temperatures, and loads of each part are equal.
Rev. PrG| Page 3 of 12
ADuM6132
PRELIMINARY TECHNICAL DATA
PACKAGE CHARACTERISTICS
Table 2.
Parameter
Symbol
RI-O
CI-O
Min
Typ
1012
2.0
Max
Unit
Ω
pF
Test Conditions
Resistance (Input Side- High Side Output)1
Capacitance (Input to High Side Output)1
Input Capacitance
CI
4.0
pF
IC Junction-to-Ambient Thermal Resistance
θJA
45
°C/W
4-layer PC board
1
The device is considered a two-terminal device: Pins 1-8 are shorted together, and Pins 9-16 are shorted together.
REGULATORY INFORMATION
The ADuM6132 will be approved by the organizations listed in Table 3.
Table 3.
UL (pending)
CSA (Pending)
VDE (Pending)
Recognized under 1577
Approved under CSA Component
Acceptance Notice #5A
Certified according to DIN V VDE V 0884-10
(VDE V 0884-10):2006-122
component recognition program1
Double/reinforced insulation,
3750 V rms isolation voltage
Basic insulation per CSA 60950-1-03 and IEC
60950-1, 800 V rms (1131 V peak) maximum
working voltage
Reinforced insulation, 560 V peak
Reinforced insulation per CSA 60950-1-03 and
IEC 60950-1, 400 V rms maximum working voltage
Complies with DIN EN 60747-5-2 (VDE 0884
Part 2): 2003-01, DIN EN 60950 (VDE 0805):
2001-12; EN 60950: 2000, DIN V VDE 0884-10
(VDE V 0884-10):2006-12
File E214100
File 205078
File 2471900-4880-0001
1 In accordance with UL1577, each ADuM6132 is proof tested by applying an insulation test voltage ≥ 4500 V rms for 1 second (current leakage detection limit = 10 μA).
2 In accordance with DIN V VDE V 0884-10, each ADuM6132 is proof tested by applying an insulation test voltage ≥1050 V peak for 1 sec (partial discharge detection
limit = 5 pC). The * marking branded on the component designates DIN V VDE V 0884-10 approval.
INSULATION AND SAFETY-RELATED SPECIFICATIONS
Table 4.
Parameter
Symbol Value
Unit
Conditions
Rated Dielectric Insulation Voltage
Minimum External Air Gap (Clearance)
3750
8.0 min
V rms
mm
1 minute duration
Measured from input terminals to output terminals, shortest
distance through air
L(I01)
Minimum External Tracking (Creepage) L(I02)
8.0 min
mm
Measured from input terminals to output terminals, shortest
distance path along body
Minimum Internal Gap (Internal
Clearance)
Tracking Resistance (Comparative
Tracking Index)
0.017 min
>175
mm
V
Insulation distance through insulation
CTI
DIN IEC 112/VDE 0303 Part 1
Isolation Group
IIIa
Material Group (DIN VDE 0110, 1/89, Table 1)
Rev. PrG| Page 4 of 12
PRELIMINARY TECHNICAL DATA
ADuM6132
DIN V VDE V 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS
The ADuM6132 is suitable for reinforced electrical isolation only within the safety limit data. Maintenance of the safety data is ensured by
protective circuits. The * marking on the package denotes DIN V VDE V 0884-10 approval.
Table 5.
Description
Conditions
Symbol Characteristic Unit
Installation Classification per DIN VDE 0110
For Rated Mains Voltage ≤ 150 V rms
For Rated Mains Voltage ≤ 300 V rms
For Rated Mains Voltage ≤ 400 V rms
Climatic Classification
Pollution Degree (DIN VDE 0110, Table 1)
Maximum Working Insulation Voltage
Input-to-Output Test Voltage, Method B1
I to IV
I to III
I to II
40/105/21
2
VIORM
VPR
560
1050
V peak
V peak
VIORM × 1.875 = VPR, 100% production test, tm = 1 sec,
partial discharge < 5 pC
Input-to-Output Test Voltage, Method A
After Environmental Tests Subgroup 1
After Input and/or Safety Test Subgroup 2
and Subgroup 3
VIORM × 1.6 = VPR, tm = 60 sec, partial discharge < 5 pC
VPR
896
672
V peak
V peak
VIORM × 1.2 = VPR, tm = 60 sec, partial discharge < 5 pC
Highest Allowable Overvoltage
Safety-Limiting Values
Transient overvoltage, tTR = 10 sec
Maximum value allowed in the event of a failure;
see
VTR
6000
V peak
Case Temperature
Side 1 Current
Side 2 Current
TS
IS1
IS2
RS
150
265
335
>109
°C
mA
mA
Ω
Insulation Resistance at TS
VIO = 500 V
RECOMMENDED OPERATING CONDITIONS
Table 6.
Parameter
Symbol
TA
VDD
Min
−40
4.5
Max
+105
5.5
Unit
°C
V
Operating Temperature
Input Supply Voltage1
Channel B Supply Voltage1
Input Signal Rise and Fall Times
Common-Mode Transient Immunity, Input-to-Output
VDDB
12.5
17
1
+50
V
ms
kV/μs
−50
1 All voltages are relative to their respective ground.
Rev. PrG| Page 5 of 12
ADuM6132
PRELIMINARY TECHNICAL DATA
ABSOLUTE MAXIMUM RATINGS
Table 6.
Parameter
Symbol
TST
TA
Min
−55
−40
Max
+150
+105
Unit
°C
°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Storage Temperature
Ambient Operating
Temperature
Input Supply Voltage1
VDD
VDDB
−0.5
−0.5
+7.0
+27
V
V
Channel B Supply
Voltage1
Input Voltage1
VIA, VIB
VOA, VOB
−0.5
−0.5
VDDI + 0.5
VISO + 0.5,
V
V
Output Voltage1
Ambient temperature = 25°C, unless otherwise noted.
V
DDB + 0.5
Output DC Current
Common-Mode
Transients2
IOA, IOB
−100 +100
−100 +100
mA
kV/μs
ESD CAUTION
1 All voltages are relative to their respective ground.
2 Refers to common-mode transients across any insulation barrier. Common-
mode transients exceeding the Absolute Maximum Ratings can cause latch-
up or permanent damage.
Table 7. Maximum Continuous Working Voltage1
Parameter
Max
Unit
Constraint
AC Voltage, Bipolar Waveform
AC Voltage, Unipolar Waveform
Basic Insulation
565
V peak
V peak
V peak
50-year minimum lifetime
1131
Maximum approved working voltage per IEC 60950-1
DC Voltage
Basic Insulation
1131
V peak
Maximum approved working voltage per IEC 60950-1
1 Refers to continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for more details
600
500
400
300
200
100
0
0
50
100
150
200
Ambient Tempearture (°C)
Figure 2 Thermal Derating Curve, Dependence of Safety Limiting Values on
Case Temperature, per DIN EN 60747-5-2
Rev. PrG| Page 6 of 12
PRELIMINARY TECHNICAL DATA
ADuM6132
PIN CONFIGURATIONS AND PIN FUNCTION DESCRIPTIONS
Figure 3. ADuM6132 Pin Configuration
Table 8. ADuM6132 Pin Function Descriptions
Pin
No.
Mnemonic
Function
1
2
3
4
VDD
Input supply voltage for isolated power supply, 4.5V to 5.5V
Ground reference for isolated power supply input and logic inputs
Input supply voltage for logic, 4.5V to 5.5V
Logic input A
GND
VDDL
VIA
5
VIB
Logic input B
6
VOB
Output B (non-isolated).
7
VDDB
Output B supply voltage input (non-isolated),
12.5V to 17V
8
9
GND
GNDISO
NC
NC
VOA
VDDA
GNDA
GNDISO
VISO
Ground reference for isolated power supply input and logic inputs
Ground reference for isolated power supply output
No Connect
No Connect
Output A (isolated)
Output A supply voltage input, must be connected externally to VISO (pin16)
Output A ground reference, must be connected externally to GNDISO (pin 15)
Ground reference for isolated power supply output
Isolated power supply voltage output
10
11
12
13
14
15
16
Table 9. ADuM6132 Truth Table (Positive Logic)
VIA
VIB
VDDL State
VDDB State
VOA
VOB
Notes
Input Input
Output Output
L
L
H
H
X
L
H
L
H
X
Powered
Powered
Powered
Powered
Powered
Powered
Powered
Powered
L
L
H
H
L
L
H
L
H
L
Unpowered Powered
VOA returns to input state within 1 μs
of VDD power restoration.
X
X
Powered Unpowered
L
L
Rev. PrG| Page 7 of 12
ADuM6132
PRELIMINARY TECHNICAL DATA
Figure 3. Typical Application Circuit
APPLICATION INFORMATION
PC BOARD LAYOUT
TYPICAL APPLICATION USAGE
The ADuM6132 digital isolator with integrated 250mW
isoPower DC/DC converter requires no external interface
circuitry for the logic interfaces. Power supply bypassing is
required at the input and output supply pins (Figure 4). The
power supply section of the ADuM6132 uses a very high
oscillator frequency to efficiently pass power through its chip
scale transformers. In addition, the normal operation of the
data section of the iCoupler introduces switching transients on
the power supply pins. Bypass capacitors are required for
several operating frequencies. Noise suppression requires a low
ESR high frequency capacitor, ripple suppression and proper
regulation require a large value capacitor in parallel, see Table
10. The total lead length between both ends of the capacitor and
the input power supply pin should not exceed 20 mm.
The architecture of the ADuM6132 is ideal for motor drive and
inverter applications where the low side channels are common
to the controller. This arrangement requires only two isolation
regions in a package. All of the isolated signals and Isolated
power are grouped on one side of the package so full package
creepage and clearance are maintained. The low side drive as
well as the control signals share a common reference and are
also grouped together.
In order to maximize the efficacy of external bypass capacitors,
the isoPower DC/DC converter is not internally tied to the data
channels, and should be treated as a completely independent
subsystem, except for a UVLO function (see Undervoltage
lockout). This means that power must be applied to VDD to
operate the DC/DC converter. Power must also be applied to
Supply
VDD
Pins
1,2
Bypass Capacitors
0.1μF, 10μF
0.1μF
0.1μF
0.1μF
VDDL and VDDB to operate the data input and the channel B
driver output. On the secondary side, the power generated at
the VISO pin must be applied as an input power supply to the
VDDB
VDDL
VDDA
VISO
7,8
2,3
13,14
15,16
VDDA pin. GNDISO and GNDA must be connected together.
The ADuM6132 is intended for driving low gate capacitance
transistors (200 pF typically). Most high voltage applications
involve larger transistors than this. To accommodate these
applications, users can implement a buffer configuration with
the ADuM6132 as shown in Figure 3. In many cases, this buffer
configuration is the least expensive option to drive high
capacitance devices and provides the greatest amount of design
flexibility. The precise buffer/high voltage transistor
0.1μF, 10μF
Table 10 Recommended Bypass Capacitors
In applications involving high common-mode transients, care
should be taken to ensure that board capacitive coupling across the
isolation barrier is minimized. Furthermore, the board layout
should be designed such that any coupling that does occur
equally affects all pins on a given component side. Failure to
ensure this could cause voltage differentials between pins
exceeding the device’s Absolute Maximum Ratings, specified in
Error! Reference source not found. leading to latch-up and/or
permanent damage.
combination can be selected to fit the needs of the application.
Figure 4. Recommended Printed Circuit Board Layout
The ADuM6132 is a power device that dissipates about 1W of
power when fully loaded and running at maximum speed.
Since it is not possible to apply a heat sink to an isolation
device, the device primarily depends on heat dissipation into
the PCB through the GND pins. If the device will be used at
high ambient temperatures, care should be taken to provide a
thermal path from the GND pins to the PCB ground plane.
Rev. PrG| Page 8 of 12
PRELIMINARY TECHNICAL DATA
ADuM6132
The board layout in Figure 4 shows enlarged pads for pins 8 and
9. Multiple vias should be implemented from the pad to the
ground plane. This will significantly reduce the temperatures
inside of the chip. The dimensions of the expanded pads are
left to discretion of the designer and the available board space.
Table 11. Undervoltage Lockout Functionality Table
VISO
-
User-provided
supplies
powered
supply
VDDL
Supply
VDDB
VDDA
Resultant
Effect
THERMAL ANALYSIS
Supply Supply
The ADuM6132 parts consist of several internal die, attached to
two lead frame paddles. For the purposes of thermal analysis it
is treated as a thermal unit with the highest junction
temperature reflected in the θJA from Error! Reference source
not found. The value of θJA is based on measurements taken
with the part mounted on a JEDEC standard 4 layer board with
fine width traces and still air. Under normal operating
conditions the ADuM6132 will operate at full load across the
full temperature range without derating the output current.
However, following the recommendations in the PC Board
Layout section will decrease the thermal resistance to the PCB
allowing increased thermal margin it high ambient
temperatures.
H
H
X
L
H
H
L
H
Normal operation.
Internal DC/DC converter active.
VOA/VOB output logic states
match VIA/VIB input logic states.
Internal DC/DC converter active
but VISO belpow UVLO threshold.
VOA output driven low.
L
V
OB output operates normally.
X
X
Internal DC/DC converter turned
off (VISO = 0).
VOA output driven low.
V
OB output drive low.
X
Internal DC/DC converter turned
off (VISO = 0).
VOA output driven low.
V
OB output drive low.
UNDERVOLTAGE LOCKOUT
Notes:
The ADuM6132 has undervoltage lockout (UVLO) circuits on
the VDDL, VDDA, and VDDB supplies. For each supply its respective
UVLO circuit monitors the supply voltage and takes a
predetermined action based on whether the supply voltage is
above or below a given threshold. These thresholds are
specified in Table 1.
L: denotes supply voltage < undervoltage lockout threshold
H: denotes supply voltage > undervoltage lockout threshold
X: denotes supply voltage level is irrelevant
When all three supplies are above their respective UVLO
thresholds the ADuM6132 operates normally. The internal
DC/DC converter is active and both outputs operate as
determined by their respective input logic signals. If either of
the user-provided supplies is below its UVLO threshold, the
ADuM6132 is put into a disabled mode. In this mode the
internal DC/DC converter is turned off and both outputs are
driven low. The VOB output is driven low by either the VDDL or
In the recommended configuration of Figure 3 only two
independent supplies are controlled by the user: VDDB and
VDDL/VDD (VDDL=VDD in Figure 3). VDDA is supplied by the
internal DC/DC converter via the VISO=VDDA external
connection. Nevertheless, the VDDA UVLO functionality is
included in the below table so that the user has an
understanding of the VOA output behavior as the internal
DC/DC converter powers on and off.
V
DDB UVLO circuit (whichever is below its threshold). The VOA
output is driven low as the internal DC/DC converter is turned
off. The VISO supply voltage is drops to zero. Since VDDA is
connected to VISO, it also is brought down to zero. Once VDDA is
below its UVLO threshold VOA is driven low by the VDDA UVLO
circuit.
PROPAGATION DELAY-RELATED PARAMETERS
Propagation delay is a parameter that describes the time it takes
a logic signal to propagate through a component. The propagation
delay to a logic low output may differ from the propagation
delay to a logic high.
INPUT (V
)
50%
IX
tPLH
tPHL
OUTPUT (V
)
50%
OX
Figure 5. Propagation Delay Parameters
Pulse width distortion is the maximum difference between
these two propagation delay values and is an indication of how
Rev. PrG| Page 9 of 12
ADuM6132
PRELIMINARY TECHNICAL DATA
accurately the input signal’s timing is preserved.
The preceding magnetic flux density values correspond to
specific current magnitudes at given distances away from the
ADuM6132 transformers. Figure 7 expresses these allowable
current magnitudes as a function of frequency for selected
distances. As shown in Figure 7, the ADuM6132 is extremely
immune and can be affected only by extremely large currents
operated at high frequency and very close to the component.
For the 1 MHz example, one would have to place a 0.5 kA
current 5 mm away from the ADuM6132 to affect the
component’s operation.
Channel-to-channel matching refers to the maximum amount
the propagation delay differs between channels within a single
ADuM6132 component.
MAGNETIC FIELD IMMUNITY
The ADuM6132 is extremely immune to external magnetic
fields. The limitation on the ADuM6132’s magnetic field
immunity is set by the condition in which induced voltage in
the transformer’s receiving coil is sufficiently large to either
falsely set or reset the decoder. The following analysis defines
the conditions under which this may occur.
1000
DISTANCE = 1m
100
The pulses at the transformer output have an amplitude greater
than 1.0 V. The decoder has a sensing threshold at about 0.5 V, thus
establishing a 0.5 V margin in which induced voltages can be
tolerated. The voltage induced across the receiving coil is given by
10
DISTANCE = 100mm
1
V = (−dβ / dt) Πr2 ;n =1, 2, ...N
∑
n
DISTANCE = 5mm
0.1
where:
β is the magnetic flux density (gauss).
0.01
N is the number of turns in the receiving coil.
rn is the radius of the nth turn in the receiving coil (cm).
1k
10k
100k
1M
10M
100M
MAGNETIC FIELD FREQUENCY (Hz)
Figure 7. Maximum Allowable Current for Various
Current-to-ADuM6132 Spacings
Given the geometry of the receiving coil in the ADuM6132 and
an imposed requirement that the induced voltage is at most
50% of the 0.5 V margin at the decoder, a maximum allowable
magnetic field is calculated, as shown in Figure 6.
Note that at combinations of strong magnetic fields and high
frequencies, any loops formed by printed circuit board traces
could induce sufficiently large error voltages to trigger the
threshold of succeeding circuitry. Care should be taken in the
layout of such traces to avoid this possibility.
100
10
INSULATION LIFETIME
All insulation structures eventually break down when subjected
to voltage stress over a sufficiently long period. The rate of
insulation degradation depends on the characteristics of the
voltage waveform applied across the insulation. In addition to
the testing performed by the regulatory agencies, Analog
Devices conducts an extensive set of evaluations to determine
the lifetime of the insulation structure within the ADuM5230.
1
0.1
0.01
0.001
Analog Devices performs accelerated life testing using voltage
levels higher than the rated continuous working voltage.
Acceleration factors for several operating conditions are
determined. These factors allow calculation of the time to
failure at the actual working voltage. Table 7 summarizes the
peak voltages for 50 years of service life for a bipolar ac
operating condition and the maximum Analog Devices
recommended working voltages. In many cases, the approved
working voltage is higher than the 50-year service life voltage.
Operation at these high working voltages can lead to shortened
insulation life in some cases.
1k
10k
100k
1M
10M
100M
MAGNETIC FIELD FREQUENCY (Hz)
Figure 6. Maximum Allowable External Magnetic Flux Density
For example, at a magnetic field frequency of 1 MHz, the
maximum allowable magnetic field of 0.2 kgauss induces a
voltage of 0.25 V at the receiving coil. This is about 50% of the
sensing threshold and does not cause a faulty output transition.
Similarly, if such an event occurs during a transmitted pulse
(with the worst-case polarity), it reduces the received pulse
from > 1.0 V to 0.75 V. Note that this is still well above the 0.5 V
sensing threshold of the decoder.
The insulation lifetime of the ADuM6132 depends on the
Rev. PrG| Page 10 of 12
PRELIMINARY TECHNICAL DATA
ADuM6132
voltage waveform type imposed across the isolation barrier.
The iCoupler insulation structure degrades at different rates
depending on whether the waveform is bipolar ac, unipolar ac,
or dc. Figure 8, Figure 9, and Figure 10 illustrate these different
isolation voltage waveforms.
RATED PEAK VOLTAGE
0V
Figure 8. Bipolar AC Waveform
Bipolar ac voltage is the most stringent environment. The goal
of a 50-year operating lifetime under the ac bipolar condition
determines the maximum working voltage recommended by
Analog Devices.
RATED PEAK VOLTAGE
0V
In the case of unipolar ac or dc voltage, the stress on the insu-
lation is significantly lower. This allows operation at higher
working voltages while still achieving a 50-year service life.
The working voltages listed in Table 7 can be applied while
maintaining the 50-year minimum lifetime provided the voltage
conforms to either the unipolar ac or dc voltage cases. Any cross
insulation voltage waveform that does not conform to Figure 9
or Figure 10 should be treated as a bipolar ac waveform and its
peak voltage should be limited to the 50-year lifetime voltage
value listed in Table 7. Note that the voltage presented in Figure 9 is
shown as sinusoidal for illustration purposes only. It is meant to
represent any voltage waveform varying between 0 V and some
limiting value. The limiting value can be positive or negative,
but the voltage cannot cross 0 V.
Figure 9. Unipolar AC Waveform
RATED PEAK VOLTAGE
0V
Figure 10. DC Waveform
Rev. PrG| Page 11 of 12
ADuM6132
PRELIMINARY TECHNICAL DATA
OUTLINE DIMENSIONS
10.50 (0.4134)
10.10 (0.3976)
16
1
9
8
7.60 (0.2992)
7.40 (0.2913)
10.65 (0.4193)
10.00 (0.3937)
1.27 (0.0500)
BSC
0.75 (0.0295)
0.25 (0.0098)
2.65 (0.1043)
2.35 (0.0925)
× 45°
0.30 (0.0118)
0.10 (0.0039)
8°
0°
0.51 (0.0201)
0.31 (0.0122)
SEATING
PLANE
COPLANARITY
0.10
1.27 (0.0500)
0.40 (0.0157)
0.33 (0.0130)
0.20 (0.0079)
COMPLIANT TO JEDEC STANDARDS MS-013AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
Figure 6. 16-Lead Standard Small Outline Package [SOIC]— Wide Body (RW-16).
Dimensions shown in millimeters (inches)
ORDERING GUIDE
No. of
Channels Current (A)
Output Peak Output
Package
Option
Model
Voltage (V) Temperature Range
Package Description
ADuM6132ARWZ1
ADuM6132ARWZ-RL1
2
2
0.2
0.2
15
15
−40°C to +105°C
−40°C to +105°C
16-Lead SOIC_W
16-Lead SOIC_W, 13-inch Tape
and Reel Option (1, 000 Units)
RW-16
RW-16
1 Z = Pb-free part.
©2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
PR07393-0-3/08(PrG)
Rev. PrG| Page 12 of 12
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