ADUM6421ABRNZ3-RL [ADI]
Quad-Channel Isolators with Integrated DC-to-DC Converter;
| 型号： | ADUM6421ABRNZ3-RL |
| 厂家： | 
ADI |
| 描述： | Quad-Channel Isolators with Integrated DC-to-DC Converter |
| 文件： | 总26页 (文件大小：533K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Quad-Channel Isolators with
Integrated DC-to-DC Converter
Data Sheet
ADuM6420A/ADuM6421A/ADuM6422A
FEATURES
FUNCTIONAL BLOCK DIAGRAM
isoPower integrated, isolated dc-to-dc converter
100 mA output supply
Meets CISPR 32/EN55032 Class B emission limits up to
5 Mbps at a full load on a 2-layer PCB
Quad dc to 100 Mbps signal isolation channels
28-lead, fine pitch, SOIC with 8.3 mm minimum creepage
High temperature operation: 125°C maximum
High common-mode transient immunity: 100 kV/μs
Safety and regulatory approvals (pending)
UL recognition (pending)
1
2
3
28
27
26
V
V
DD2
DD1
GND
GND
V
GND
GND
1
1
2
2
4
5
25
24
23
22
21
20
V
4-CHANNEL iCoupler CORE
LOW POWER ON-OFF KEYING
IA
IB
OA
V
V
OB
ADuM6420A/
ADuM6421A/
ADuM6422A
V
V
/V
V
V
/V
6
IC OC
OC IC
/V
7
/V
ID OD
OD ID
LOW RADIATED EMISSIONS DC TO DC
PCS
GND
1
8
GND
2
PDIS
9
V
SEL
5000 V rms for 1 minute per UL 1577
CSA Component Acceptance Notice 5A (pending)
VDE V 0884-11 certificate of conformity (pending)
GND
1
10
11
12
13
14
19 GND
ISO
V
OSC
18
RECT REG
V
DDP
ISO
V
IORM = 566 V peak
17 GND
GND
1
ISO
16
15
NIC
NIC
APPLICATIONS
GND
1
GND
ISO
RS-232 transceivers
Power supply start-up bias and gate drives
Isolated sensor interfaces
Industrial programmable logic controllers (PLCs)
NIC = NO INTERNAL CONNECTION. LEAVE THIS PIN FLOATING.
Figure 1.
GENERAL DESCRIPTION
The ADuM6420A/ADuM6421A/ADuM6422A1 are quad-channel
digital isolators with an isoPower®, integrated, isolated dc-to-dc
converter. Based on the Analog Devices, Inc., iCoupler®
technology, the dc-to-dc converter provides regulated, isolated
power that meets CISPR 32/EN 55032 Class B limits at a full
load on a 2-layer printed circuit board (PCB) with ferrites.
Popular voltage combinations and the associated output
current levels are listed in Table 1.
The ADuM6420A/ADuM6421A/ADuM6422A isolators
provide four independent isolation channels (see the Pin
Configurations and Function Descriptions for additional
information).
Table 1. ADuM6420A/ADuM6421A/ADuM6422A Output
Current Levels
ISO Current, IISO (mA)
VDDP (V)
VISO (V)
5
3.3
85°C
100
100
60
105°C
65
65
125°C
30
30
The ADuM6420A/ADuM6421A/ADuM6422A eliminate the
need for a separate, isolated dc-to-dc converter in 500 mW,
isolated designs. The iCoupler chip scale transformer technology
is used for isolated logic signals and for the magnetic components
of the dc-to-dc converter. The result is a small form factor, total
isolation solution.
5
5
3.3
3.3
60
20
1 Protected by U.S. Patents 5,952,849; 6,873,065; 6,903,578; and 7,075,329. Other patents are pending.
Rev. A
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2019–2020 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
ADuM6420A/ADuM6421A/ADuM6422A
Data Sheet
TABLE OF CONTENTS
Features.............................................................................................. 1
Insulation and Safety Related Specifications.......................... 11
DIN V VDE V 0884-11 Insulation Characteristics............... 12
Recommended Operating Conditions.................................... 12
Absolute Maximum Ratings......................................................... 13
ESD Caution ............................................................................... 13
Pin Configurations and Function Descriptions......................... 14
Truth Table ................................................................................. 17
Typical Performance Characteristics .......................................... 18
Terminology.................................................................................... 21
Theory of Operation ...................................................................... 22
Applications Information ............................................................. 23
PCB Layout ................................................................................. 23
Thermal Analysis ....................................................................... 24
Propagation Delay Related Parameters................................... 24
EMI Considerations................................................................... 24
Power Consumption.................................................................. 24
Insulation Lifetime..................................................................... 24
Outline Dimensions....................................................................... 26
Ordering Guide .......................................................................... 26
Applications ...................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications .................................................................................... 3
Electrical Characteristics—5 V Primary Input Supply/5 V
Secondary Isolated Supply .......................................................... 3
Electrical Characteristics—5 V Primary Input Supply/3.3 V
Secondary Isolated Supply .......................................................... 3
Electrical Characteristics—3.3 V Primary Input Supply/3.3 V
Secondary Isolated Supply .......................................................... 4
Electrical Characteristics—5.0 V Operation Digital Isolator
Channels Only .............................................................................. 4
Electrical Characteristics—3.3 V Operation Digital Isolator
Channels Only .............................................................................. 6
Electrical Characteristics—2.5 V Operation Digital Isolator
Channels Only .............................................................................. 8
Electrical Characteristics—1.8 V Operation Digital Isolator
Channels Only .............................................................................. 9
Package Characteristics ............................................................. 11
Regulatory Approvals ................................................................ 11
REVISION HISTORY
12/2020—Rev. 0 to Rev. A
Changes to Table 11 and Table 13 ..................................................8
Changes to Table 14..........................................................................9
Changes to Table 21....................................................................... 12
Changes to Table 23....................................................................... 13
Change to Table 24 ........................................................................ 14
Change to Table 25 ........................................................................ 15
Change to Table 26 ........................................................................ 16
Changes to Table 28....................................................................... 17
Changes to Figure 6, Figure 7, and Figure 8............................... 18
Changes to PCB Layout Section, Figure 22, and Figure 23...... 23
Change to Thermal Analysis Section .......................................... 24
Changes to Ordering Guide.......................................................... 26
Changes to Table 1 ........................................................................... 1
Changes to Electrical Characteristics—5 V Primary Input
Supply/5 V Secondary Isolated Supply Section............................ 3
Moved Electrical Characteristics—5 V Primary Input
Supply/3.3 V Secondary Isolated Supply Section and Table 6;
Renumbered Sequentially ............................................................... 3
Added Electrical Characteristics—3.3 V Primary Input
Supply/3.3 V Secondary Isolated Supply Section, Table 4,
Electrical Characteristics—5.0 V Operation Digital Isolator
Channels Only Section, and Table 5.............................................. 4
Changes to Table 7 ........................................................................... 5
Removed Table 7 and Table 8......................................................... 6
Changes to Table 8 ........................................................................... 6
Removed Table 9 .............................................................................. 7
Changes to Table 10......................................................................... 7
12/2019—Revision 0: Initial Version
Rev. A | Page 2 of 26
Data Sheet
ADuM6420A/ADuM6421A/ADuM6422A
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—5 V PRIMARY INPUT SUPPLY/5 V SECONDARY ISOLATED SUPPLY
All typical specifications are at TA = 25°C, VDDP = VISO = 5 V. Minimum and maximum specifications apply over the entire recommended
operation range, which is 4.5 V ≤ (VDDP, VISO) ≤ 5.5 V and −40°C ≤ TA ≤ +125°C, unless otherwise noted.
Table 2. DC-to-DC Converters Static Specifications
Parameter
Symbol
Min Typ Max
Unit
Test Conditions/Comments
DC-TO-DC CONVERTERS SUPPLY
Setpoint
Line Regulation
Load Regulation
Output Ripple
VISO
4.75 5.0
5.25
5
V
ISO current (IISO) = 10 mA
IISO = 50 mA, VDD1 = 4.5 V to 5.5 V
IISO = 10 mA to 90 mA
VISO (LINE)
VISO (LOAD)
VISO (RIP)
20
1
75
mV/V
%
mV p-p 20 MHz bandwidth, bulk output capacitance
(CBO) = 0.1 μF||10 μF, IISO = 90 mA
Output Noise
VISO (NOISE)
fOSC
fPWM
200
180
625
mV p-p CBO = 0.1 μF||10 μF, IISO = 90 mA
MHz
kHz
Switching Frequency
Pulse-Width Modulation (PWM) Frequency
Output Supply1
IISO (MAX)
100
50
mA
mA
%
4.5 V < VISO < 5.25 V
4.75 V < VISO < 5.25 V
IISO = 100 mA, TA = 25°C
1
Efficiency at IISO (MAX)
34
VDD1 Supply Current
No VISO Load
Full VISO Load
IDDP (Q)
IDDP (MAX)
14
310
25
mA
mA
Thermal Shutdown
Shutdown Temperature
Thermal Hysteresis
154
10
°C
°C
1 Maximum VISO output current is derated by 1.75 mA/°C for TA > 85°C.
ELECTRICAL CHARACTERISTICS—5 V PRIMARY INPUT SUPPLY/3.3 V SECONDARY ISOLATED SUPPLY
All typical specifications are at TA = 25°C, VDDP = 5.0 V, VISO = 3.3 V. Minimum and maximum specifications apply over the entire
recommended operation range, which is 4.5 V ≤ VDDP ≤ 5.5 V, 3.0 V ≤ VISO ≤ 3.6 V, and −40°C ≤ TA ≤ +125°C, unless otherwise noted.
Table 3. DC-to-DC Converters Static Specifications
Parameter
Symbol Min
Typ Max
Unit
Test Conditions/Comments
DC-TO-DC CONVERTERS SUPPLY
Setpoint
VISO
3.135 3.3
3.465
V
IISO = 10 mA
Line Regulation
Load Regulation
Output Ripple
Output Noise
Switching Frequency
Pulse-Width Modulation Frequency
Output Supply1
VISO (LINE)
VISO (LOAD)
VISO (RIP)
VISO (NOISE)
fOSC
20
1
50
130
180
625
mV/V
%
IISO = 50 mA, VDD1 = 3.0 V to 3.6 V
IISO = 10 mA to 90 mA
5
mV p-p 20 MHz bandwidth, CBO = 0.1 μF||10 μF, IISO = 90 mA
mV p-p CBO = 0.1 μF||10 μF, IISO = 90 mA
MHz
kHz
mA
mA
%
fPWM
IISO (MAX)
100
50
3.0 V < VISO < 3.4 V
3.135 V < VISO < 3.465 V
IISO = 100 mA
1
Efficiency at IISO (MAX)
34
VDDP Supply Current
No VISO Load
Full VISO Load
IDDP (Q)
IDDP (MAX)
14
250
20
mA
mA
Thermal Shutdown
Shutdown Temperature
Thermal Hysteresis
154
10
°C
°C
1 Maximum VISO output current is derated by 1.75 mA/°C for TA > 85ºC.
Rev. A | Page 3 of 26
ADuM6420A/ADuM6421A/ADuM6422A
Data Sheet
ELECTRICAL CHARACTERISTICS—3.3 V PRIMARY INPUT SUPPLY/3.3 V SECONDARY ISOLATED SUPPLY
All typical specifications are at TA = 25°C, VDDP = VISO = 3.3 V. Minimum and maximum specifications apply over the entire
recommended operation range, which is 3.0 V ≤ VDDP, VISO ≤ 3.6 V, and −40°C ≤ TA ≤ +125°C, unless otherwise noted.
Table 4. DC-to-DC Converters Static Specifications
Parameter
Symbol Min
Typ Max
Unit
Test Conditions/Comments
DC-TO-DC CONVERTERS SUPPLY
Setpoint
Line Regulation
Load Regulation
Output Ripple
VISO
3.135
3.3
20
1
3.465
5
V
IISO = 10 mA
IISO = 30 mA, VDD1 = 3.0 V to 3.6 V
IISO = 6 mA to54 mA
VISO (LINE)
VISO (LOAD)
VISO (RIP)
VISO (NOISE)
fOSC
mV/V
%
50
mV p-p 20 MHz bandwidth, CBO = 0.1 μF||10 μF, IISO = 60 mA
mV p-p CBO = 0.1 μF||10 μF, IISO = 60 mA
Output Noise
130
180
625
Switching Frequency
Pulse-Width Modulation Frequency
Output Supply1
MHz
kHz
mA
mA
%
fPWM
IISO (MAX)
60
30
3.0 V < VISO < 3.465 V
3.135 V < VISO < 3.465 V
IISO = 60 mA
1
Efficiency at IISO (MAX)
34
VDDP Supply Current
No VISO Load
Full VISO Load
IDDP (Q)
IDDP (MAX)
14
190
20
mA
mA
Thermal Shutdown
Shutdown Temperature
Thermal Hysteresis
154
10
°C
°C
1 Maximum VISO output current is derated by 2.0 mA/°C for TA > 105ºC.
ELECTRICAL CHARACTERISTICS—5.0 V OPERATION DIGITAL ISOLATOR CHANNELS ONLY
All typical specifications are at TA = 25°C, VDD1 = VDD2 = 5.0 V. Minimum and maximum specifications apply over the entire recommended
operation range: 4.5 V ≤ VDD1 , VDD2 ≤ 5.5 V, and −40°C ≤ TA ≤ +125°C, unless otherwise noted. Switching specifications are tested with
CL = 15 pF and CMOS signal levels, unless otherwise noted. Supply currents are specified with 50% duty cycle signals.
Table 5. Data Channel Supply Current Specifications
1 Mbps
10 Mbps
100 Mbps
Parameter
Symbol
Min Typ Max Min Typ Max Min Typ Max Unit Test Conditions/Comments
SUPPLY CURRENT
ADuM6420AXRNZ5
CL = 0 pF
IDD1
IDD2
IDD1
IDD2
IDD1
IDD2
IDD1
IDD2
IDD1
IDD2
IDD1
IDD2
4.9
1.5
4.9
1.5
4.2
2.3
4.2
2.3
3.3
3.0
3.3
3.0
8.7
2.5
8.7
2.5
8.4
4.5
8.4
4.5
6.0
6.0
6.0
6.0
5.5
2.3
5.5
2.3
4.5
2.8
4.5
2.8
3.9
4.0
3.9
4.0
9.5
3.6
9.5
3.6
8.5
5.7
8.5
5.7
6.2
6.5
6.2
6.5
8.0
8.0
8.0
9.3
8.0
8.8
8.0
9.4
8.3
9.5
8.3
9.5
12.2 mA
11.0 mA
12.2 mA
15.0 mA
12.0 mA
12.0 mA
12.0 mA
15.0 mA
12.0 mA
13.5 mA
12.0 mA
14.0 mA
ADuM6420AXRNZ3
ADuM6421AXRNZ5
ADuM6421AXRNZ3
ADuM6422AXRNZ5
ADuM6422AXRNZ3
Rev. A | Page 4 of 26
Data Sheet
ADuM6420A/ADuM6421A/ADuM6422A
Table 6. Switching Specifications
Parameter
Symbol Min Typ Max Unit
Test Conditions/Comments
SWITCHING SPECIFICATIONS
Pulse Width
Data Rate
Propagation Delay
Pulse Width Distortion
Change vs. Temperature
Propagation Delay Skew
PW
10
ns
Mbps
ns
ns
ps/°C
ns
Within pulse width distortion (PWD) limit
Within PWD limit
50% input to 50% output
100
15
5
tPHL, tPLH
PWD
7.0
10
1
1.5
|tPLH − tPHL|
tPSK
8.0
Between any two units at the same temperature, voltage, and
load
Channel Matching
Codirectional
Opposing Direction
Jitter
tPSKCD
tPSKOD
1
1
816
5.0
5.0
ns
ns
ps p-p
Table 7. Input and Output Characteristics
Parameter
Symbol Min
Typ
Max
Unit
Test Conditions/Comments
DC SPECIFICATIONS
Input Threshold
Logic High
VIH
VIL
0.7 × VDDx
V
V
Logic Low
0.3 × VDDx
Output Voltage
Logic High
2
VOH
VOL
VDDx − 0.2
VDDx − 0.5
VDDx
VDDx − 0.2
0.0
V
V
V
V
IOx1 = −20 μA, VIx = VIxH
IOx1 = −3.2 mA, VIx = VIxH
2
3
Logic Low
0.1
0.4
IOx1 = 20 μA, VIx = VIxL
3
0.0
IOx1 = 3.2 mA, VIx = VIxL
Undervoltage Lockout
Positive Going Threshold
Negative Going Threshold
Hysteresis
Input Currents per Channel
Quiescent Supply Current
ADuM6420A
UVLO
VUV+
VUV−
VUVH
II
VDD1, VDD2, and VDDP supply
1.6
1.5
0.1
+0.01
V
V
V
μA
−10
+10
0 V ≤ VIx ≤ VDDx
IDD1 (Q)
IDD2 (Q)
IDD1 (Q)
IDD2 (Q)
0.37
1.2
9.5
1.2
1.9
16
mA
mA
mA
mA
VIx = Logic 0
VIx = Logic 0
VIx = Logic 1
VIx = Logic 1
1.5
2.5
ADuM6421A
ADuM6422A
IDD1 (Q)
IDD2 (Q)
IDD1 (Q)
IDD2 (Q)
0.5
0.9
7.5
3.3
1.4
1.5
14
mA
mA
mA
mA
VIx = Logic 0
VIx = Logic 0
VIx = Logic 1
VIx = Logic 1
6.2
IDD1 (Q)
IDD2 (Q)
IDD1 (Q)
IDD2 (Q)
0.7
0.72
5.4
1.2
1.3
9.5
9.7
mA
mA
mA
mA
VIx = Logic 0
VIx = Logic 0
VIx = Logic 1
VIx = Logic 1
5.3
Dynamic Supply Current
Input
Output
IDDI (D)
IDDO (D)
0.01
0.02
mA/Mbps Inputs switching, 50% duty cycle
mA/Mbps Inputs switching, 50% duty cycle
Rev. A | Page 5 of 26
ADuM6420A/ADuM6421A/ADuM6422A
Data Sheet
Parameter
Symbol Min
Typ
Max
Unit
Test Conditions/Comments
AC SPECIFICATIONS
Output Rise Time/Fall Time
tR/tF
2.5
ns
10% to 90%
Common-Mode Transient
Immunity4
|CMH|
75
75
100
kV/μs
VIx = VDD1 or VISO, common-mode
voltage (VCM) = 1000 V, transient
magnitude = 800 V
VIx = 0 V, VCM = 1000 V, transient
magnitude = 800 V
|CML|
100
kV/μs
1 IOX is the Channel x output current, where x is A, B, C, or D.
2 VIXH is the input side logic high.
3 VIXL is the input side logic low.
4 |CMH| is the maximum common-mode voltage slew rate that can be sustained while maintaining the voltage output (VO) > 0.8 VDDx. |CML| is the maximum common-mode voltage
slew rate that can be sustained while maintaining VO > 0.8 V. The common-mode voltage slew rates apply to both the rising and falling common-mode voltage edges.
ELECTRICAL CHARACTERISTICS—3.3 V OPERATION DIGITAL ISOLATOR CHANNELS ONLY
All typical specifications are at TA = 25°C, VDD1 = VDD2 = 3.3 V. Minimum and maximum specifications apply over the entire recommended
operation range: 3.0 V ≤ VDD1 ≤ 3.6 V, 3.0 V ≤ VDD2 ≤ 3.6 V, and −40°C ≤ TA ≤ +125°C, unless otherwise noted. Switching specifications
are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted. Supply currents are specified with 50% duty cycle signals.
Table 8. Data Channel Supply Current Specifications
1 Mbps
10 Mbps
100 Mbps
Parameter
Symbol Min Typ Max Min Typ Max Min Typ Max Unit Test Conditions/Comments
SUPPLY CURRENT
CL = 0 pF
ADuM6420AXRNZ5 IDD1
4.8
1.4
4.8
1.4
4.0
2.1
4.0
2.1
3.1
3.0
3.1
3.0
8.5
2.5
8.5
2.5
8.3
4.4
8.3
4.4
6.0
6.0
6.0
6.0
4.9
2.1
4.9
2.1
4.3
2.7
4.3
2.7
3.6
3.7
3.6
3.7
9.0
3.4
9.0
3.4
8.4
5.6
8.4
5.6
6.2
6.2
6.0
6.2
7.0
7.5
7.0
7.5
7.1
8.0
7.1
8.0
7.4
8.5
7.4
8.5
11.0 mA
11 mA
IDD2
ADuM6420AXRNZ3 IDD1
11.0 mA
12.0 mA
11.6 mA
11.6 mA
11.6 mA
12.0 mA
11.0 mA
12.0 mA
11.0 mA
13.0 mA
IDD2
ADuM6421AXRNZ5 IDD1
IDD2
ADuM6421AXRNZ3 IDD1
IDD2
ADuM6422AXRNZ5 IDD1
IDD2
ADuM6422AXRNZ3 IDD1
IDD2
Table 9. Switching Specifications
Parameter
Symbol Min Typ Max Unit
Test Conditions/Comments
SWITCHING SPECIFICATIONS
Pulse Width
PW
10
ns
Within PWD limit
Data Rate
100
16
5.0
Mbps
ns
ns
ps/°C
ns
Within PWD limit
50% input to 50% output
|tPLH − tPHL|
Propagation Delay
Pulse Width Distortion
Change vs. Temperature
Propagation Delay Skew
tPHL, tPLH
PWD
7.0
10
1.0
1.5
tPSK
8.0
Between any two units at the same temperature, voltage, and
load
Channel Matching
Codirectional
Opposing Direction
Jitter
tPSKCD
tPSKOD
1.0
1.0
816
5.0
5.0
ns
ns
ps p-p
Rev. A | Page 6 of 26
Data Sheet
ADuM6420A/ADuM6421A/ADuM6422A
Table 10. Input and Output Characteristics
Parameter
Symbol Min
Typ
Max
Unit
Test Conditions/Comments
DC SPECIFICATIONS
Input Threshold
Logic High
VIH
VIL
0.7 × VDDx
V
V
Logic Low
0.3 × VDDx
Output Voltage
Logic High
2
VOH
VOL
VDDx − 0.2
VDDx − 0.5
VDDx
VDDx1 – 0.2
0.0
V
V
V
V
IOx1 = −20 μA, VIx = VIxH
IOx1 = −3.2 mA, VIx = VIxH
2
3
Logic Low
0.1
0.4
IOx1 = 20 μA, VIx = VIxL
3
0.0
IOx1 = 3.2 mA, VIx = VIxL
Undervoltage Lockout
Positive Going Threshold
UVLO
VUV+
VDD1, VDD2, and VDDP supply
1.6
V
Negative Going Threshold VUV−
1.5
V
Hysteresis
VUVH
II
0.1
+0.01
V
μA
Input Currents per Channel
Quiescent Supply Current
ADuM6420A
−10
+10
0 V ≤ VIx ≤ VDDx
IDD1 (Q)
IDD2 (Q)
IDD1 (Q)
IDD2 (Q)
0.34
1.1
9.5
1.2
1.8
16
mA
mA
mA
mA
VIx = Logic 0
VIx = Logic 0
VIx = Logic 1
VIx = Logic 1
1.5
2.4
ADuM6421A
ADuM6422A
IDD1 (Q)
IDD2 (Q)
IDD1 (Q)
IDD2 (Q)
0.48
0.8
7.4
1.1
1.5
13.5
6.2
mA
mA
mA
mA
VIx = Logic 0
VIx = Logic 0
VIx = Logic 1
VIx = Logic 1
3.2
IDD1 (Q)
IDD2 (Q)
IDD1 (Q)
IDD2 (Q)
0.65
0.7
5.3
1.2
1.2
9.5
9.6
mA
mA
mA
mA
VIx = Logic 0
VIx = Logic 0
VIx = Logic 1
VIx = Logic 1
5.4
Dynamic Supply Current
Dynamic Input
Dynamic Output
IDDI (D)
IDDO (D)
0.01
0.01
mA/Mbps
mA/Mbps
Inputs switching, 50% duty cycle
Inputs switching, 50% duty cycle
AC SPECIFICATIONS
Output Rise/Fall Time
tR/tF
2.5
ns
10% to 90%
Common-Mode Transient
Immunity4
|CMH|
75
75
100
kV/μs
VIx = VDD1 or VISO, VCM = 1000 V,
transient magnitude = 800 V
VIx = 0 V, VCM = 1000 V,
|CML|
100
kV/μs
transient magnitude = 800 V
1 IOX is the Channel x output current, where x is A, B, C, or D.
2 VIXH is the input side logic high.
3 VIXL is the input side logic low.
4 |CMH| is the maximum common-mode voltage slew rate that can be sustained while maintaining the voltage output (VO) > 0.8 VDDx. |CML| is the maximum common-mode voltage
slew rate that can be sustained while maintaining VO > 0.8 V. The common-mode voltage slew rates apply to both the rising and falling common-mode voltage edges.
Rev. A | Page 7 of 26
ADuM6420A/ADuM6421A/ADuM6422A
Data Sheet
ELECTRICAL CHARACTERISTICS—2.5 V OPERATION DIGITAL ISOLATOR CHANNELS ONLY
All typical specifications are at TA = 25°C, VDD1 = VDD2 = 2.5 V. Minimum and maximum specifications apply over the entire recommended
operation range: 2.25 V ≤ VDD1 ≤ 2.75 V, 2.25 V ≤ VDD2 ≤ 2.75 V, and −40°C ≤ TA ≤ +125°C, unless otherwise noted. Switching specifications are
tested with CL = 15 pF and CMOS signal levels, unless otherwise noted. Supply currents are specified with 50% duty cycle signals.
Table 11. Data Channel Supply Current Specifications
1 Mbps
10 Mbps
100 Mbps
Parameter
Symbol Min Typ Max Min Typ Max Min Typ Max Unit Test Conditions/Comments
SUPPLY CURRENT
CL = 0 pF
ADuM6420AXRNZ5/ IDD1
4.8
1.4
4.2
2.3
3.0
3.0
8.5
2.3
8.0
4.4
6.0
6.0
4.8
2.0
4.4
2.4
3.4
3.4
9.0
3.3
8.2
5.4
6.1
6.1
6.4
6.5
6.7
6.5
6.4
6.4
11.0 mA
9.5 mA
11.5 mA
10.0 mA
ADuM6420AXRNZ3
IDD2
ADuM6421AXRNZ5/ IDD1
ADuM6421AXRNZ53
IDD2
ADuM6422AXRNZ5/ IDD1
ADuM6422AXRNZ3
9.5
9.5
mA
mA
IDD2
Table 12. Switching Specifications
Parameter
Symbol Min Typ Max Unit
Test Conditions/Comments
SWITCHING SPECIFICATIONS
Pulse Width
PW
10
ns
Within PWD limit
Data Rate
100
16
5.0
Mbps
ns
ns
ps/°C
ns
Within PWD limit
50% input to 50% output
|tPLH − tPHL|
Propagation Delay
Pulse Width Distortion
Change vs. Temperature
Propagation Delay Skew
tPHL, tPLH
PWD
8.0
11
1.0
1.5
tPSK
8.0
Between any two units at the same temperature, voltage, and
load
Channel Matching
Codirectional
Opposing Direction
Jitter
tPSKCD
tPSKOD
1.0
1.0
816
5.0
5.0
ns
ns
ps p-p
Table 13. Input and Output Characteristics
Parameter
Symbol Min
Typ
Max
Unit
Test Conditions/Comments
DC SPECIFICATIONS
Input Threshold
Logic High
VIH
VIL
0.7 × VDDx
V
V
Logic Low
0.3 × VDDx
Output Voltage
Logic High
2
VOH
VOL
VDDx − 0.2
VDDx − 0.5
VDDx
VDDx − 0.2
0.0
V
V
V
V
IOx1 = −20 μA, VIx = VIxH
IOx1 = −3.2 mA, VIx = VIxH
2
3
Logic Low
0.1
0.4
IOx1 = 20 μA, VIx = VIxL
3
0.0
IOx1 = 3.2 mA, VIx = VIxL
Undervoltage Lockout
Positive Going Threshold
UVLO
VUV+
VDD1, VDD2, and VDDP supply
1.6
V
Negative Going Threshold VUV−
1.5
V
Hysteresis
VUVH
II
0.1
+0.01
V
μA
Input Currents per Channel
Quiescent Supply Current
ADuM6420A
−10
+10
0 V ≤ VIx ≤ VDDx
IDD1 (Q)
IDD2 (Q)
IDD1 (Q)
IDD2 (Q)
0.33
1.1
1.5
1.0
1.7
2.2
16
mA
mA
mA
mA
VIx = Logic 0
VIx = Logic 0
VIx = Logic 1
VIx = Logic 1
9.5
Rev. A | Page 8 of 26
Data Sheet
ADuM6420A/ADuM6421A/ADuM6422A
Parameter
Symbol Min
Typ
Max
Unit
Test Conditions/Comments
ADuM6421A
IDD1 (Q)
IDD2 (Q)
IDD1 (Q)
IDD2 (Q)
0.5
0.9
7.4
3.2
1.0
1.5
13.5
6.2
mA
mA
mA
mA
VIx = Logic 0
VIx = Logic 0
VIx = Logic 1
VIx = Logic 1
ADuM6422A
IDD1 (Q)
IDD2 (Q)
IDD1 (Q)
IDD2 (Q)
0.55
0.55
5.3
1.2
1.2
9.5
9.5
mA
mA
mA
mA
VIx = Logic 0
VIx = Logic 0
VIx = Logic 1
VIx = Logic 1
5.3
Dynamic Supply Current
Dynamic Input
Dynamic Output
IDDI (D)
IDDO (D)
0.01
0.01
mA/Mbps
mA/Mbps
Inputs switching, 50% duty cycle
Inputs switching, 50% duty cycle
AC SPECIFICATIONS
Output Rise/Fall Time
tR/tF
2.5
ns
10% to 90%
Common-Mode Transient
Immunity4
|CMH|
75
75
100
kV/μs
VIx = VDD1 or VISO, VCM = 1000 V,
transient magnitude = 800 V
VIx = 0 V, VCM = 1000 V,
|CML|
100
kV/μs
transient magnitude = 800 V
1 IOx is the Channel x output current, where x means A, B, C, or D.
2 VIxH is the input side logic high.
3 VIxL is the input side logic low.
4 |CMH| is the maximum common-mode voltage slew rate that can be sustained while maintaining the voltage output (VO) > 0.8 VDDx. |CML| is the maximum common-mode voltage
slew rate that can be sustained while maintaining VO > 0.8 V. The common-mode voltage slew rates apply to both the rising and falling common-mode voltage edges.
ELECTRICAL CHARACTERISTICS—1.8 V OPERATION DIGITAL ISOLATOR CHANNELS ONLY
All typical specifications are at TA = 25°C, VDD1 = VDD2 = 1.8 V. Minimum and maximum specifications apply over the entire recommended
operation range: 1.7 V ≤ VDD1 ≤ 1.9 V, 1.7 V ≤ VDD2 ≤ 1.9 V, and −40°C ≤ TA ≤ +125°C, unless otherwise noted. Switching specifications
are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted. Supply currents are specified with 50% duty cycle signals.
Table 14. Data Channel Supply Current Specifications
1 Mbps
10 Mbps
100 Mbps
Parameter
Symbol Min Typ Max Min Typ Max Min Typ Max Unit Test Conditions/Comments
SUPPLY CURRENT
CL = 0 pF
ADuM6420AXRNZ5/ IDD1
ADuM6420AXRNZ3
4.3
1.3
4.1
2.3
3.0
3.0
8.5
2.3
8.0
4.4
6.0
6.0
4.9
1.4
4.4
2.6
3.4
3.4
8.5
2.5
8.0
5.3
6.2
6.2
6.4
6.4
6.7
6.5
6.2
6.0
10.6 mA
9.0 mA
11.5 mA
IDD2
ADuM6421AXRNZ5/ IDD1
ADuM6421AXRNZ3
IDD2
9.5
9.0
9.0
mA
mA
mA
ADuM6422AXRNZ5/ IDD1
ADuM6422AXRNZ3
IDD2
Table 15. Switching Specifications
Parameter
Symbol Min Typ Max Unit
Test Conditions/Comments
SWITCHING SPECIFICATIONS
Pulse Width
PW
10
ns
Within PWD limit
Data Rate
100
17
5.0
Mbps
ns
ns
ps/°C
ns
Within PWD limit
50% input to 50% output
Propagation Delay
Pulse Width Distortion
Change vs. Temperature
Propagation Delay Skew
Channel Matching
Codirectional
tPHL, tPLH
PWD
8.0
12
1.0
1.5
|tPLH − tPHL
|
tPSK
8.0
Between any two units at the same temperature, voltage, and load
tPSKCD
tPSKOD
1.0
1.0
816
5.0
5.0
ns
ns
ps p-p
Opposing Direction
Jitter
Rev. A | Page 9 of 26
ADuM6420A/ADuM6421A/ADuM6422A
Data Sheet
Table 16. Input and Output Characteristics
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
DC SPECIFICATIONS
Input Threshold
Logic High
VIH
VIL
0.7 × VDDx
V
V
Logic Low
0.3 × VDDx
Output Voltages
Logic High
2
VOH
VOL
VDDx − 0.1
VDDx − 0.4
VDDx
VDDx − 0.2
0.0
V
V
V
V
IOx1 = −20 μA, VIx = VIxH
IOx1 = −3.2 mA, VIx = VIxH
2
3
Logic Low
0.1
0.4
IOx1 = 20 μA, VIx = VIxL
3
0.2
IOx1 = 3.2 mA, VIx = VIxL
Undervoltage Lockout
Positive Going Threshold
Negative Going Threshold
Hysteresis
Input Currents per Channel
Quiescent Supply Current
ADuM6420A
UVLO
VUV+
VUV−
VUVH
II
VDD1, VDD2, and VDDP supply
1.6
1.5
0.1
+0.01
V
V
V
μA
−10
+10
0 V ≤ VIx ≤ VDDx
IDD1 (Q)
IDD2 (Q
IDD1 (Q)
IDD2 (Q)
0.35
1.0
9.4
1.0
1.7
16
mA
mA
mA
mA
VIx = Logic 0
VIx = Logic 0
VIx = Logic 1
VIx = Logic 1
1.4
2.2
ADuM6421A
ADuM6422A
IDD1 (Q)
IDD2 (Q)
IDD1 (Q)
IDD2 (Q)
0.5
0.9
7.5
3.2
1.0
1.4
13.5
6.2
mA
mA
mA
mA
VIx = Logic 0
VIx = Logic 0
VIx = Logic 1
VIx = Logic 1
IDD1 (Q)
IDD2 (Q)
IDD1 (Q)
IDD2 (Q)
0.6
0.65
5.3
1.2
1.2
9.5
9.5
mA
mA
mA
mA
VIx = Logic 0
VIx = Logic 0
VIx = Logic 1
VIx = Logic 1
5.3
Dynamic Supply Current
Input
Output
IDDI (D)
IDDO (D)
0.01
0.01
mA/Mbps
mA/Mbps
Inputs switching, 50% duty cycle
Inputs switching, 50% duty cycle
AC SPECIFICATIONS
Output Rise/Fall Time
tR/tF
2.5
ns
10% to 90%
Common-Mode Transient
Immunity4
|CMH|
75
75
100
kV/μs
VIx = VDD1 or VISO, VCM = 1000 V,
transient magnitude = 800 V
VIx = 0 V, VCM = 1000 V,
|CML|
100
kV/μs
transient magnitude = 800 V
1 IOx is the Channel x output current, where x means A, B, C, or D.
2 VIxH is the input side logic high.
3 VIxL is the input side logic low.
4 |CMH| is the maximum common-mode voltage slew rate that can be sustained while maintaining the voltage output (VO) > 0.8 VDDx. |CML| is the maximum common-mode voltage
slew rate that can be sustained while maintaining VO > 0.8 V. The common-mode voltage slew rates apply to both the rising and falling common-mode voltage edges.
Rev. A | Page 10 of 26
Data Sheet
ADuM6420A/ADuM6421A/ADuM6422A
PACKAGE CHARACTERISTICS
Table 17. Thermal and Isolation Characteristics
Parameter
Symbol Min Typ Max Unit Test Conditions/Comments
Resistance (Input to Output)1
Capacitance (Input to Output)1
Input Capacitance2
RI-O
CI-O
CI
1013
2.2
4.0
45
Ω
pF
pF
Frequency = 1 MHz
IC Junction to Ambient Thermal Resistance
θJA
°C/W Thermocouple located at center of package underside,
test conducted on 4-layer board with thin traces3
1 The device is considered a 2-terminal device: Pin 1 to Pin 14 are shorted together, and Pin 15 to Pin 28 are shorted together.
2 Input capacitance is from any input data pin to ground.
3 See the Thermal Analysis section for thermal model definitions.
REGULATORY APPROVALS
Table 18.
UL (Pending)1
CSA (Pending)
VDE (Pending)2
CQC (Pending)
Recognized Under UL 1577
Component Recognition
Program1
Approved under CSA Component
Acceptance Notice 5A
DIN V VDE V 0884-11 (VDE V 0884-
11):2017-1
Certified under
CQC11-471543-2012
Single Protection, 5000 V rms CSA 60950-1-07+A1+A2 and
Reinforced insulation 566 V peak,
GB4943.1-2011:
Isolation Voltage
IEC 60950-1, second edition,
+A1+A2:
V
IOSM = 6000 V peak
Basic insulation at 815 V rms
(1173 V peak)
Basic insulation at 830 V rms
(1173 V peak)
Transient voltage, VIOTM
8000 V peak
=
Reinforced insulation at
415 V rms (586 V peak)
Reinforced insulation at 415 V rms
(586 V peak)
IEC 60601-1 Edition 3.1:
Basic insulation (1 means of patient
protection (1 MOPP)), 250 V rms
CSA 61010-1-12 and IEC 61010-1
third edition:
Basic insulation at 300 V rms mains,
815 V rms (1173 V peak) secondary
Reinforced insulation at 300 V rms
mains, 415 V rms (586 V peak)
File E214100
File 205078
File (pending)
File (pending)
1 In accordance with UL 1577, each ADuM6420A/ADuM6421A/ADuM6422A is proof tested by applying an insulation test voltage ≥ 6000 V rms for 1 sec.
2 In accordance with DIN V VDE V 0884-11, each ADuM6420A/ADuM6421A/ADuM6422A is proof tested by applying an insulation test voltage ≥1059 V peak for 1 sec
(partial discharge detection limit = 5 pC). The * marking branded on the component designates DIN V VDE V 0884-11 approval.
INSULATION AND SAFETY RELATED SPECIFICATIONS
Table 19. Critical Safety Related Dimensions and Material Properties
Parameter
Symbol Value
Unit
Test Conditions/Comments
Rated Dielectric Insulation Voltage
Minimum External Air Gap (Clearance)
5000
8.3
V rms
1-minute duration
L(I01)
L(I02)
mm min Measured from input terminals to output terminals,
shortest distance through air
mm min Measured from input terminals to output terminals,
shortest distance path along body
Minimum External Tracking (Creepage)
8.3
Minimum Clearance in the Plane of the PCB
L (PCB) 8.3
mm min Measured from input terminals to output terminals,
shortest distance through air, line of sight, in the PCB
mounting plane
Minimum Internal Gap (Internal Clearance)
Tracking Resistance (Comparative Tracking Index)
Isolation Group
25.5
>600
I
ꢀm min Minimum distance through insulation
CTI
V
DIN IEC 112/VDE 0303, Part 1
Material group (DIN VDE 0110, 1/89, Table 1)
Rev. A | Page 11 of 26
ADuM6420A/ADuM6421A/ADuM6422A
Data Sheet
DIN V VDE V 0884-11 INSULATION CHARACTERISTICS
The ADuM6420A/ADuM6421A/ADuM6422A are suitable for reinforced electrical isolation only within the safety limit data.
Maintenance of the safety data is ensured by the protective circuits. The asterisk (*) marking on packages denotes DIN V VDE V 0884-11
approval.
Table 20. VDE Characteristics
Description
Test Conditions/Comments
Symbol Characteristic Unit
Installation Classification per DIN VDE 0110
For Rated Mains Voltage ≤ 150 V rms
For Rated Mains Voltage ≤ 300 V rms
For Rated Mains Voltage ≤ 400 V rms
Climatic Classification
Pollution Degree per DIN VDE 0110, Table 1
Maximum Working Insulation Voltage
Input to Output Test Voltage, Method b1
I to IV
I to IV
I to IV
40/125/21
2
VIORM
VPR
566
1059
V peak
V peak
V
IORM × 1.875 = VPR, 100% production test, tm = 1 sec,
partial discharge < 5 pC
Input to Output Test Voltage, Method a
After Environmental Tests Subgroup 1
VPR
Vpd(m)
V
IORM × 1.5 = Vpd(m), tini = 60 sec, tm = 10 sec,
partial discharge < 5 pC
After Input and/or Safety Test Subgroup 2 VIORM × 1.2 = Vpd(m), tini = 60 sec, tm = 10 sec,
849
679
V peak
V peak
Vpd(m)
and Subgroup 3
partial discharge < 5 pC
Highest Allowable Overvoltage
Withstand Isolation Voltage
Surge Isolation Voltage Reinforced
Transient overvoltage, tTR = 10 sec
1-minute withstand rating
VIOTM
VISO
VIOSM
8000
5000
8000
V peak
V rms
V peak
V
IOSM(TEST) = 12.8 kV; 1.2 μs rise time; 50 μs, 50% fall
time
Safety Limiting Values
Maximum value allowed in the event of a failure
(see Figure 2)
Case Temperature
Total Power Dissipation at 25°C
Insulation Resistance at TS
TS
IS1
RS
150
2.78
>109
°C
W
Ω
VIO = 500 V
3.0
2.5
2.0
1.5
1.0
0.5
0
RECOMMENDED OPERATING CONDITIONS
Table 21.
Parameter
Min
Max
Unit
Operating Temperature (TA)1
Supply Voltages2
VDDP at VSEL = GNDISO
VDDP at VSEL = VISO
VDD1, VDD2
−40
+125
°C
3.0
4.5
1.7
5.5
5.5
5.5
V
V
V
1 Operation at >85°C requires reduction of the maximum load current.
2 Each voltage is relative to its respective ground.
0
50
100
150
200
AMBIENT TEMPERATURE (°C)
Figure 2. Thermal Derating Curve, Dependence of Safety Limiting Values on
Case Temperature, per DIN EN 60747-5-2
Rev. A | Page 12 of 26
Data Sheet
ADuM6420A/ADuM6421A/ADuM6422A
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the
operational section of this specification is not implied.
Operation beyond the maximum operating conditions for
extended periods may affect product reliability.
Table 22.
Parameter
Rating
Storage Temperature (TST)
Ambient Operating Temperature
Supply Voltages (VDD1, VDDP, VDD2, VISO
VISO Supply Current2
−55°C to +150°C
−40°C to +125°C
−0.5 V to +7.0 V
100 mA
−0.5 V to VDDI + 0.5 V
−0.5 V to VDDO + 0.5 V
−10 mA to +10 mA
1
)
Input Voltage (VIA, VIB, VIC, VID, VSEL, PDIS)1, 3
1, 3
Output Voltage (VOA, VOB, VOC, VOD
)
ESD CAUTION
Average Output Current Per Data
Output Pin4
Common-Mode Transients5
−200 kV/μs to
+200 kV/μs
1 All voltages are relative to their respective ground.
2 The VISO pin provides current for dc and dynamic loads on the VISO input and
output channels. This current must be included when determining the total
V
ISO supply current. For ambient temperatures between 85°C and 125°C, the
maximum allowed current is reduced.
3 VDDI and VDDO refer to the supply voltages on the input and output sides of a
given channel, respectively. See the PCB Layout section.
4 See Figure 2 for the maximum rated current values for various temperatures.
5 Common-mode transients refer to common-mode transients across the
insulation barrier. Common-mode transients exceeding the absolute
maximum ratings may cause latch-up or permanent damage.
Table 23. Maximum Continuous Working Voltage1
Parameter
Rating
Constraint
AC Voltage
Bipolar Waveform
Basic Insulation
Reinforced Insulation
Unipolar Waveform
Basic Insulation
Reinforced Insulation
DC Voltage
636 V peak
566 V peak
733 V peak
652 V peak
Basic Insulation
Reinforced Insulation
1158 V peak
579 V peak
Lifetime limited by package creepage per IEC 60664-1
Lifetime limited by package creepage per IEC 60664-1
1 Maximum continuous working voltage refers to the continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for more
information.
Rev. A | Page 13 of 26
ADuM6420A/ADuM6421A/ADuM6422A
Data Sheet
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
1
2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
V
DD2
DD1
GND
GND
GND
2
2
1
3
GND
1
4
V
V
V
V
V
V
V
V
IA
IB
IC
OA
OB
OC
OD
5
6
ADuM6420A
TOP VIEW
(Not to Scale)
7
ID
8
GND
GND
V
1
2
9
PDIS
SEL
10
11
12
13
14
GND
GND
1
ISO
ISO
ISO
V
V
ISO
DDP
GND
GND
NIC
1
NIC
GND
GND
1
NOTES
1. NIC = NOT INTERNALLY CONNECTED. THESE PINS ARE NOT CONNECTED INTERNALLY.
Figure 3. ADuM6420A Pin Configuration
Table 24. ADuM6420A Pin Function Descriptions
Pin No.
Mnemonic Description
1
VDD1
Power Supply for the Side 1 Logic Circuits of the Device. VDD1 requires a 100 nF bypass capacitor. VDD1 is
independent of VDDP and can operate with power supply voltages between 1.7 V and 5.5 V.
2, 3, 8, 10, 12, 14 GND1
Ground 1. Ground references for the primary isolator. Pin 2, Pin 3, Pin 8, Pin 10, Pin 12, and Pin 14 are
internally connected, and it is recommended to connect the GND1 pins to a common ground.
4
5
6
7
9
VIA
VIB
VIC
VID
Logic Input A.
Logic Input B.
Logic Input C.
Logic Input D.
PDIS
Power Disable. When PDIS is tied to GND1, the power converter is active. When a logic high voltage is
applied to PDIS, the power supply enters low power standby mode.
11
13, 16
15, 17, 19
VDDP
NIC
GNDISO
Primary Supply Voltage, 3.0 V to 5.5 V. VDDP requires 100 nF and 10 μF bypass capacitors to GND1.
Not Internally Connected. These pins are not connected internally.
Ground References for VISO on Side 2. It is recommended to connect the GNDISO pins together. The GNDISO
pins are internally isolated from GND2.
18
20
21, 26, 27
VISO
VSEL
GND2
Secondary Supply Voltage Output for External Loads. Connect to VDD2 to power the isolator channels.
Output Voltage Select Input. Connect VSEL to VISO for a 5 V output or to GNDISO for a 3.3 V output.
Ground References for VDD2 on Side 2. It is recommended that the GND2 pins be connected together. The
GND2 pins are internally isolated from GNDISO
.
22
23
24
25
28
VOD
VOC
VOB
VOA
VDD2
Logic Output D.
Logic Output C.
Logic Output B.
Logic Output A.
Power Supply for the Side 2 Logic Circuits of the Device. VDD2 requires a 100 nF bypass capacitor. VDD2 is
independent of VISO and can operate with power supply voltages between 1.7 V and 5.5 V.
Rev. A | Page 14 of 26
Data Sheet
ADuM6420A/ADuM6421A/ADuM6422A
1
2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
V
DD2
DD1
GND
GND
GND
2
2
1
3
GND
1
4
V
V
V
V
V
V
V
IA
IB
IC
OA
OB
OC
ID
5
6
ADuM6421A
TOP VIEW
(Not to Scale)
7
V
OD
8
GND
GND
V
1
2
9
PDIS
SEL
10
11
12
13
14
GND
GND
1
ISO
ISO
ISO
V
V
ISO
DDP
GND
GND
NIC
1
NIC
GND
GND
1
NOTES
1. NIC = NOT INTERNALLY CONNECTED. THESE PINS ARE NOT CONNECTED INTERNALLY.
Figure 4. ADuM6421A Pin Configuration
Table 25. ADuM6421A Pin Function Descriptions
Pin No.
Mnemonic Description
1
VDD1
Power Supply for the Side 1 Logic Circuits of the Device. VDD1 requires a 0.10 μF bypass capacitor to GND1.
VDD1 is independent of VDDP and can operate with power supply voltages between 1.7 V and 5.5 V.
2, 3, 8, 10, 12, 14 GND1
Ground 1. Ground references for the primary isolator. Pin 2, Pin 3, Pin 8, Pin 10, Pin 12, and Pin14 are
internally connected, and it is recommended to connect the GND1 pins to a common ground.
4
5
6
7
9
VIA
VIB
VIC
VOD
PDIS
Logic Input A.
Logic Input B.
Logic Input C.
Logic Output D.
Power Disable. When PDIS is tied to GND1, the power converter is active. When a logic high voltage is
applied to PDIS, the power supply enters low power standby mode.
11
13, 16
15, 17, 19
VDDP
NIC
GNDISO
DC-to-DC Converter Supply Voltage, 3.0 V to 5.5 V. VDDP requires 0.10 μF and 10 μF bypass capacitors to GND1.
Not Internally Connected. These pins are not connected internally.
Grounds for the Isolated DC-to-DC Converter. Connect the GNDISO pins together through one ferrite bead to
PCB ground. The GNDISO pins are internally isolated from GND2.
18
VISO
Secondary Supply Voltage Output for External Loads. VISO requires 0.10 μF and 10 μF capacitors to GNDISO
.
Connect VISO through a ferrite bead to external loads.
20
21, 26, 27
VSEL
GND2
Output Voltage Select Input. Connect VSEL to VISO for a 5 V output or to GNDISO for a 3.3 V output.
Ground References for VDD2 on Side 2. It is recommended that the GND2 pins be connected together. The
GND2 pins are internally isolated from GNDISO
.
22
23
24
25
28
VID
Logic Input D.
Logic Output C.
Logic Output B.
Logic Output A.
VOC
VOB
VOA
VDD2
Power Supply for the Side 2 Logic Circuits of the Device. VDD2 requires a 100 nF bypass capacitor. VDD2 is
independent of VISO and can operate with power supply voltages between 1.7 V and 5.5 V.
Rev. A | Page 15 of 26
ADuM6420A/ADuM6421A/ADuM6422A
Data Sheet
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
V
DD2
DD1
2
3
GND
GND
GND
2
2
1
1
GND
4
V
V
V
V
V
V
IA
OA
OB
IC
5
IB
6
V
V
OC
OD
ADuM6422A
TOP VIEW
(Not to Scale)
7
ID
8
GND
GND
V
1
2
9
PDIS
SEL
10
11
12
13
14
GND
GND
1
ISO
ISO
ISO
V
V
ISO
DDP
GND
GND
NIC
1
NIC
GND
GND
1
NOTES
1. NIC = NOT INTERNALLY CONNECTED. THESE PINS ARE NOT CONNECTED INTERNALLY.
Figure 5. ADuM6422A Pin Configuration
Table 26. ADuM6422A Pin Function Descriptions
Pin No.
Mnemonic Description
VDD1
Power Supply for the Side 1 Logic Circuits of the Device. VDD1 requires a 0.10 μF bypass capacitor to GND1.
DD1 is independent of VDDP and can operate with power supply voltages between 1.7 V and 5.5 V.
1
V
2, 3, 8, 10, 12, 14 GND1
Ground 1. Ground references for the primary isolator. Pin 2, Pin 3, Pin 8, Pin 10, Pin 12, and Pin 14 are
internally connected, and it is recommended to connect the GND1 pins to a common ground.
4
5
6
7
9
VIA
VIB
VOC
VOD
PDIS
Logic Input A.
Logic Input B.
Logic Output C.
Logic Output D.
Power Disable. When PDIS is tied to GND1, the power converter is active. When a logic high voltage is
applied to PDIS, the power supply enters a low power standby mode.
11
13, 16
15, 17, 19
VDDP
NIC
GNDISO
DC-to-DC Converter Supply Voltage, 3.0 V to 5.5 V. VDDP requires 0.10 μF and 10 μF bypass capacitors to GND1.
Not Internally Connected. These pins are not connected internally.
Grounds for the Isolated DC-to-DC Converter. Connect the GNDISO pins together through one ferrite bead to
PCB ground. The GNDISO pins are internally isolated from GND2.
18
VISO
Secondary Supply Voltage Output for External Loads. VISO requires 0.10 μF and 10 μF capacitors to GNDISO
.
Connect VISO through a ferrite bead to external loads.
20
21, 26, 27
VSEL
GND2
Output Voltage Select Input. Connect VSEL to VISO for a 5 V output or to GNDISO for a 3.3 V output.
Ground Reference for VDD2 on Side 2. It is recommended that the GND2 pins be connected together. The
GND2 pins are internally isolated from GNDISO
.
22
23
24
25
28
VID
VIC
VOB
VOA
VDD2
Logic Input D.
Logic Input C.
Logic Output B.
Logic Output A.
Power Supply for the Side 2 Logic Circuits of the Device. VDD2 requires a 100 nF bypass capacitor. VDD2 is
independent of VISO and can operate with power supply voltages between 1.7 V and 5.5 V.
Rev. A | Page 16 of 26
Data Sheet
ADuM6420A/ADuM6421A/ADuM6422A
TRUTH TABLE
Table 27. Data Section Truth Table (Positive Logic)
VDDI State1
Powered
Powered
Don’t care
VIx Input1 VDDO State1
VOx Output1
High
Low
High-Z
Notes
High
Low
Powered
Powered
Normal operation, data is high.
Normal operation, data is low.
Output is off.
Don’t care Unpowered
Unpowered Low
Unpowered High
Powered
Powered
Low
Indeterminate
Output default low.
If a high level is applied to an input when no supply is present, the
input can parasitically power the input side, causing unpredictable
operation.
1 VDDI and VDDO refer to the supply voltages on the input and output sides of the given channel, respectively. VIx and VOx refer to the input and output signals of a given
channel (Channel A, Channel B, Channel C, or Channel D).
Table 28. Power Section Truth Table (Positive Logic)
VDDP (V)
VSEL Input
PDIS Input
Low
VISO (V)
5
High
5
5
5
Don’t care
Low
High
Low
0
3.3
3.3
3.3
3.3
Low
High
Don’t care
Low
Low
High
3.3
Condition not supported
0
Rev. A | Page 17 of 26
ADuM6420A/ADuM6421A/ADuM6422A
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
35
3.0
2.5
2.0
1.5
1.0
0.5
0
POWER DISSIPATION
DDP
I
30
25
20
15
10
3.3V IN/3.3V OUT
5V IN/5V OUT
5V IN/3.3V OUT
5
0
0
0.02
0.04
0.06
0.08
0.10
3.5
4.0
4.5
5.0
5.5
I
OUTPUT CURRENT (A)
V
(V)
ISO
DDP
Figure 6. Power Supply Efficiency in Supported Power Configurations
Figure 9. Short-Circuit Input Current (IDDP) and Power Dissipation vs. VDDP
0.10
0.09
0.08
0.07
0.06
0.05
0.04
0.03
1000
V
AT 5V (mV)
ISO
PERCENT LOAD
500
0
–500
–1000
100
50
0
0.02
3.3V IN/3.3V OUT
5V IN/5V OUT
5V IN/3.3V OUT
0.01
0
0
0.05
0.10
0.15
0.20
0.25
0.30
0.35
1
2
3
4
5
6
INPUT CURRENT (A)
TIME (ms)
Figure 7. IISO Output Current vs. Input Current in Supported Power
Configurations
Figure 10. VISO Transient Load Response, 5 V Output,
10% to 90% Load Step
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
1000
500
V
AT 3.3V (mV)
ISO
PERCENT LOAD
0
–500
–1000
100
50
0
0.2
3.3V IN/3.3V OUT
5V IN/5V OUT
5V IN/3.3V OUT
0.1
0
0
0.02
0.04
0.06
0.08
0.10
–1
0
1
2
3
4
I
OUTPUT CURRENT (A)
ISO
TIME (ms)
Figure 11. VISO Transient Load Response, 5 V Input, 3.3 V Output,
10% to 90% Load Step
Figure 8. Total Power Dissipation vs. IISO Output Current in Supported Power
Configurations
Rev. A | Page 18 of 26
Data Sheet
ADuM6420A/ADuM6421A/ADuM6422A
3.32
3.30
3.28
3.26
3.24
3.22
3.20
3.18
5.10
5.08
5.06
5.04
5.02
5.00
4.98
4.96
–50
–25
0
25
50
75
100
125
0
0.02
0.04
0.06
0.08
0.10
TEMPERATURE (°C)
I
OUTPUT CURRENT (A)
ISO
Figure 15. VISO vs. Temperature, Input = 3.3 V, VISO = 3.3 V
Figure 12. VISO vs. IISO Output Current, Input = 5 V, VISO = 5 V
15
10
5
3.36
3.34
3.32
3.30
3.28
3.26
3.24
3.22
0
–5
–10
–15
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
0
0.02
0.04
0.06
0.08
0.10
TIME (µs)
I
OUTPUT CURRENT (A)
ISO
Figure 16. Output Voltage Ripple at 90% Load, VISO = 5 V
Figure 13. VISO vs. IISO Output Current, Input = 5 V, VISO = 3.3 V
15
10
5
5.10
5.08
5.06
5.04
5.02
5.00
4.98
4.96
0
–5
–10
–15
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
–50
–25
0
25
50
75
100
125
TIME (µs)
TEMPERATURE (°C)
Figure 17. Output Voltage Ripple at 90% Load, VISO = 3.3 V
Figure 14. VISO vs. Temperature, Input = 5 V, VISO = 5 V
Rev. A | Page 19 of 26
ADuM6420A/ADuM6421A/ADuM6422A
Data Sheet
5
4
7
V
V
AT 10% LOAD (V)
AT 90% LOAD (V)
V
V
AT 10% LOAD (V)
AT 90% LOAD (V)
ISO
ISO
ISO
ISO
6
5
3
4
2
3
2
1
1
0
0
–1
–1
0
1
2
3
4
0
1
2
3
4
TIME (ms)
TIME (ms)
Figure 19. 5 V Input to 3.3 V Output VISO Start-Up Transient at
10% and 90% Load
Figure 18. 5 V Input to 5 V Output VISO Start-Up Transient at
10% and 90% Load
Rev. A | Page 20 of 26
Data Sheet
ADuM6420A/ADuM6421A/ADuM6422A
TERMINOLOGY
Propagation Delay Skew, tPSK
IDD1
tPSK is the magnitude of the worst-case difference in tPHL and/or tPLH
I
DD1 is the supply current required for the primary side of the
that is measured between units at the same operating temperature,
supply voltages, and output load within the recommended
operating conditions.
digital isolator.
IDD2
I
DD2 is the supply current required for the secondary side of the
Channel to Channel Matching, tPSKCD/tPSKOD
digital isolator.
tPSKCD is the absolute value of the difference in propagation
delays between two codirectional channels when operated with
identical loads. tPSKOD is the absolute value of the difference in
propagation delays between two channels transmitting in
opposing directions.
IDDP
I
DDP is the supply current required for the primary side of the
isolated dc-to-dc converter.
IISO
I
ISO is the available isolated current supply available to an
Minimum Pulse Width
The minimum pulse width is the shortest pulse width at which
external load.
Propagation Delay, tPHL
the specified pulse width distortion is guaranteed.
tPHL is measured from the 50% level of the falling edge of the VIx
signal to the 50% level of the falling edge of the VOx signal.
Maximum Data Rate
The maximum data rate is the fastest data rate at which the
specified pulse width distortion is guaranteed.
Propagation Delay, tPLH
tPLH is measured from the 50% level of the rising edge of the VIx
signal to the 50% level of the rising edge of the VOx signal.
Rev. A | Page 21 of 26
ADuM6420A/ADuM6421A/ADuM6422A
Data Sheet
THEORY OF OPERATION
The dc-to-dc converter section of the ADuM6420A/ADuM6421A/
ADuM6422A works on principles that are common to most
modern power supplies. The ADuM6420A/ADuM6421A/
ADuM6422A have a split controller architecture with isolated
PWM feedback. VDDP power is supplied to an oscillating circuit
that switches current into a chip scale, air core transformer.
Power transferred to the secondary side is rectified and regulated
to a value of 3.3 V or 5 V, depending on the setting of the VSEL pin.
The secondary (VISO) side controller regulates the output by
creating a PWM control signal that is sent to the primary
(VDDP) side by a dedicated iCoupler data channel. The PWM
modulates the oscillator circuit to control the power being sent
to the secondary side. Feedback allows for significantly higher
power and efficiency.
The digital isolator channels use a high frequency carrier to
transmit data across the isolation barrier using iCoupler chip
scale transformer coils separated by layers of polyimide isolation.
Using an on/off keying technique and the differential architecture
shown in Figure 20, the digital isolator channels have low
propagation delay and high speed. Internal regulators and
input and output design techniques allow logic and supply
voltages over a wide range from 1.7 V to 5.5 V, offering voltage
translation of 1.8 V, 2.5 V, 3.3 V, and 5 V logic. The architecture is
designed for high common-mode transient immunity and high
immunity to electrical noise and magnetic interference. Radiated
emissions are minimized with a spread spectrum on/off keying
carrier and other techniques.
Figure 20 shows the waveforms of the digital isolator channels
that have the condition of the fail-safe output state equal to low,
where the carrier waveform is off when the input state is low. If
the input side is off or not operating, the low fail-safe output
state sets the output to low.
The ADuM6420A/ADuM6421A/ADuM6422A implement
undervoltage lockout (UVLO) with hysteresis on the primary
and the secondary side input and output pins as well as the
V
DDP power input. This feature ensures that the converter does
not enter oscillation due to noisy input power or slow power-
on ramp rates.
REGULATOR
REGULATOR
RECEIVER
TRANSMITTER
V
V
OUT
IN
GND
GND
2
1
Figure 20. Operational Block Diagram of a Single Channel with a Low Fail-Safe Output State, VIN Is the Input Voltage and VOUT Is the Output Voltage
Rev. A | Page 22 of 26
Data Sheet
ADuM6420A/ADuM6421A/ADuM6422A
APPLICATIONS INFORMATION
and 10 μF for VDD1. The smaller capacitor must have a low ESR.
For example, use of a ceramic capacitor is advised. The total
lead length between the ends of the low ESR capacitor and the
input power supply pin must not exceed 2 mm.
PCB LAYOUT
The ADuM6420A/ADuM6421A/ADuM6422A digital isolators
with an isoPower integrated dc-to-dc converter require no external
interface circuitry for the logic interfaces. Power supply
bypassing is required at the input and output supply pins (see
Figure 21, Figure 22, and Figure 23). For proper data channel
operation, low equivalent series resistance (ESR) bypass
capacitors of 0.01 μF to 0.1 μF are required between the VDD1
pin and GND1 pin as close to the chip pads as possible. Low
ESR bypass capacitors of 0.1 μF or 0.22 μF are required between
the VISO pin and GNDISO pin as close to the chip pads as possible
(see the CISO notes in Figure 22 and Figure 23). Installing the
bypass capacitor with traces more than 2 mm in length may
result in data corruption. The isoPower inputs require several
passive components to bypass the power effectively, as well as
set the output voltage.
To reduce the level of electromagnetic radiation, the impedance
to high frequency currents between the VISO and the GNDISO pins
and the PCB trace connections can be increased. Using this
method of electromagnetic interference (EMI) suppression
controls the radiating signal at the signal source by placing
surface-mount ferrite beads in series with the VISO and GNDISO
pins, as seen in Figure 23. The impedance of the ferrite bead
must be approximately 1.8 kΩ between the 100 MHz and
1 GHz frequency range to reduce the emissions at the 180 MHz
primary switching frequency and the 360 MHz secondary side,
rectifying frequency and harmonics. See Table 29 for examples
of appropriate surface-mount ferrite beads.
Table 29. Surface-Mount Ferrite Beads Example
Manufacturer
Part No.
Taiyo Yuden
Murata Electronics
BKH1005LM182-T
BLM15HD182SN1
ADuM6420A
ADuM6421A
ADuM6422A
BYPASS <2mm
0.1µF
0.1µF
V
V
DD2
DD1
GND
GND
V
GND
GND
2
2
1
1
V
OA
OB
IA
V
V
IB
V
V
/V
V
V
/V
OC IC
IC OC
Figure 21. VDD1 and VDDP Bias and Bypass Components
/V
/V
OD ID
ID OD
GND
2
V
GND
DD2
1
28
V
SEL
PDIS
GND
0.1µF
GND
2
27
GND
V
ISO
ISO
ISO
1
V
DDP
V
SEL
GND
20
19
18
17
GND
1
1
10µF 0.1µF
0.1µF
FERRITES 10µF
GND
NIC
ISO
GND
GND
ISO
FB1
V
ISO
V
OUT
ISO
C
C
= 0.1µF FOR V
= 5V
= 3.3V
GND
ISO
ISO
ISO
ISO
0.1µF
10µF
FB2
= 0.22µF FOR V
ISO
ISO GND
Figure 23. Recommended PCB Layout
In applications involving high common-mode transients, ensure
that board coupling across the isolation barrier is minimized.
Furthermore, design the board layout such that any coupling
that does occur equally affects all pins on a given component
side. Failure to ensure these steps can cause voltage differentials
between pins, exceeding the absolute maximum ratings specified
in Table 22, thereby leading to latch-up and/or permanent
damage.
C
C
= 0.1µF FOR V
= 0.22µF FOR V
= 5V
ISO
ISO
ISO
= 3.3V
ISO
Figure 22. VDD2 and VISO Bias and Bypass Components
The power supply section of the ADuM6420A/ADuM6421A/
ADuM6422A use a 180 MHz oscillator frequency to efficiently
pass power through the chip scale transformers. Bypass capacitors
are required for several operating frequencies. Noise suppression
requires a low inductance, high frequency capacitor. Ripple
suppression and proper regulation require a large value capacitor.
These capacitors are connected between the VDDP pin and
GND1 pin and between the VISO pin and GNDISO pin. To suppress
noise and reduce ripple, a parallel combination of at least two
capacitors is required. The required capacitor values are 0.1 μF
Rev. A | Page 23 of 26
ADuM6420A/ADuM6421A/ADuM6422A
Data Sheet
THERMAL ANALYSIS
EMI CONSIDERATIONS
The ADuM6420A/ADuM6421A/ADuM6422A consist of five
internal die attached to a split lead frame with two die attach
pads. For the purposes of thermal analysis, the die is treated as
a thermal unit, with the highest junction temperature reflected
in the θJA value from Table 17. The value of θJA is based on
measurements taken with the devices mounted on a JEDEC
standard, 4-layer board with fine width traces and still air.
Under normal operating conditions, the ADuM6420A/
ADuM6421A/ADuM6422A can operate at full load. However,
at temperatures above 85°C, derating the output current may be
needed, as shown in Figure 2.
The dc-to-dc converter section of the ADuM6420A/ADuM6421A/
ADuM6422A components must, of necessity, operate at a high
frequency to allow efficient power transfer through the small
transformers, which creates high frequency currents that can
propagate in circuit board ground and power planes, requiring
proper power supply bypassing at the input and output supply pins
(see Figure 23). Using proper layout and bypassing techniques,
the dc-to-dc converter is designed to provide regulated, isolated
power that is below CISPR 32/EN 55032 Class B limits up to 5
Mbps at full load on a 2-layer PCB with ferrites.
POWER CONSUMPTION
PROPAGATION DELAY RELATED PARAMETERS
The VDDP power supply input only provides power to the
converter. Power for the data channels is provided through
Propagation delay is a parameter that describes the time it takes
a logic signal to propagate through a component (see Figure 24).
The propagation delay to a logic low output may differ from the
propagation delay to a logic high.
VDD1 and VDD2. These power supplies can be connected to VDDP
and VISO if desired, or the supplies can receive power from an
independent source. Treat the converter as a standalone supply
to be utilized at the discretion of the designer.
INPUT (V
)
50%
Ix
The VDD1 or VDD2 supply current at a given channel of the
ADuM6420A/ADuM6421A/ADuM6422A isolators is a
function of the supply voltage, the data rate of the channel,
and the output load of the channel.
tPLH
tPHL
OUTPUT (V
)
50%
Ox
Figure 24. Propagation Delay Parameters
The VDD1 and VDD2 supply current and the total supply currents
as a function of data rate for each model of the ADuM6420A/
ADuM6421A/ADuM6422A for an unloaded output condition
are shown under typical supply and room temperature conditions
in the figures in the Typical Performance Characteristics section.
The total IISO output current as a function of input current for
the ADuM6420A/ADuM6421A/ADuM6422A is shown in
Figure 7. In addition, the total power dissipation as a function
of output current is shown in Figure 8.
Pulse width distortion is the maximum difference between
these two propagation delay values and is an indication of how
accurately the input signal timing is preserved.
Channel to channel matching refers to the maximum amount
the propagation delay differs between channels within a single
ADuM6420A/ADuM6421A/ADuM6422A component.
Propagation delay skew refers to the maximum amount the
propagation delay differs between multiple ADuM6420A/
ADuM6421A/ADuM6422A components operating under the
same conditions.
INSULATION LIFETIME
All insulation structures eventually break down when subjected
to voltage stress over a sufficiently long period. The rate of
insulation degradation is dependent on the characteristics of
the voltage waveform applied across the insulation as well as
on the materials and material interfaces.
The two types of insulation degradation of primary interest
are breakdown along surfaces exposed to the air and insulation
wear out. Surface breakdown is the phenomenon of surface
tracking and the primary determinant of surface creepage
requirements in system level standards. Insulation wear out
is the phenomenon where charge injection or displacement
currents inside the insulation material cause long-term
insulation degradation.
Rev. A | Page 24 of 26
Data Sheet
ADuM6420A/ADuM6421A/ADuM6422A
Surface Tracking
Calculation and Use of Parameters Example
Surface tracking is addressed in electrical safety standards by
setting a minimum surface creepage based on the working
voltage, the environmental conditions, and the properties of the
insulation material. Safety agencies perform characterization
testing on the surface insulation of components that allows
the components to be categorized in different material groups.
Lower material group ratings are more resistant to surface
tracking and, therefore, can provide adequate lifetime with
smaller creepage. The minimum creepage for a given working
voltage and material group is in each system level standard and
is based on the total rms voltage across the isolation, pollution
degree, and material group. The material group and creepage
for the digital isolator channels are presented in Table 19.
The following example frequently arises in power conversion
applications. Assume that the line voltage on one side of the
isolation is 240 V ac rms and a 400 V dc bus voltage is present
on the other side of the isolation barrier. The isolator material
is polyimide. To establish the critical voltages in determining
the creepage, clearance and lifetime of a device, see Figure 25
and the following equations.
V
AC RMS
V
V
V
DC
PEAK
RMS
Insulation Wear Out
The lifetime of insulation caused by wear out is determined by
its thickness, material properties, and the voltage stress applied.
It is important to verify that the product lifetime is adequate at
the application working voltage. The working voltage supported
by an isolator for wear out may not be the same as the working
voltage supported for tracking. The working voltage applicable
to tracking is specified in most standards.
TIME
Figure 25. Critical Voltage Example
The working voltage across the barrier from Equation 1 is
2
VRMS = VAC RMS2 +VDC
Testing and modeling show that the primary driver of long-
term degradation is displacement current in the polyimide
insulation causing incremental damage. The stress on the
insulation can be broken down into broad categories, such as
dc stress, which causes little wear out because there is no
displacement current, and an ac component time varying
voltage stress, which causes wear out.
VRMS = 2402 + 4002
VRMS = 466 V
This VRMS value is the working voltage used together with the
material group and pollution degree when looking up the
creepage required by a system standard.
The ratings in certification documents are usually based on
60 Hz sinusoidal stress because this reflects isolation from line
voltage. However, many practical applications have combinations
of 60 Hz ac and dc across the barrier as shown in Equation 1.
Because only the ac portion of the stress causes wear out, the
equation can be rearranged to solve for the ac rms voltage, as
shown in Equation 2. For insulation wear out with the polyimide
materials used in these products, the ac rms voltage determines
the product lifetime.
To determine if the lifetime is adequate, obtain the time varying
portion of the working voltage. To obtain the ac rms voltage,
use Equation 2.
2
VAC RMS = VRMS2 −VDC
VAC RMS
AC RMS = 240 V rms
=
4662 − 4002
V
In this case, the ac rms voltage is simply the line voltage of
240 V rms. This calculation is more relevant when the waveform
is not sinusoidal. The value is compared to the limits for working
voltage in Table 23 for the expected lifetime, which is less than
a 60 Hz sine wave, and it is well within the limit for a 50-year
service life.
2
VRMS = VAC RMS2 +VDC
(1)
or
2
VAC RMS = VRMS2 −VDC
(2)
where:
Note that the dc working voltage limit is set by the creepage of
the package as specified in IEC 60664-1. This value can differ
for specific system level standards.
V
V
V
RMS is the total rms working voltage.
AC RMS is the time varying portion of the working voltage.
DC is the dc offset of the working voltage.
Rev. A | Page 25 of 26
ADuM6420A/ADuM6421A/ADuM6422A
OUTLINE DIMENSIONS
Data Sheet
10.45
10.15
28
15
7.60
7.40
10.55
10.05
14
1
PIN 1
INDICATOR
TOP VIEW
0.65 BSC
0.40
0.25
0.75
0.25
× 45°
2.40
2.25
2.65
2.35
END VIEW
SIDE VIEW
0.32
0.23
8°
0°
0.25
0.10
0.25 BSC
SEATING
PLANE
(GAUGE PLANE)
1.40
REF
1.27
0.40
COPLANARITY
0.10
Figure 26. 28-Lead Standard Small Outline, Wide Body, with Finer Pitch [SOIC_W_FP]
(RN-28-1)
Dimensions shown in millimeters
ORDERING GUIDE
Number
Number
of Inputs, of Inputs, Standard or
Typical VDDP Temperature
Package
Package Description Option
Model1, 2, 3
VDD1 Side
VISO Side
SPI Isolator
Standard
Standard
Standard
Standard
Standard
Standard
Standard
Standard
Standard
Standard
Standard
Standard
Voltage (V)
Range (°C)
ADuM6420ABRNZ5
ADuM6420ABRNZ5-RL
ADuM6421ABRNZ5
ADuM6421ABRNZ5-RL
ADuM6422ABRNZ5
ADuM6422ABRNZ5-RL
ADuM6420ABRNZ3
ADuM6420ABRNZ3-RL
ADuM6421ABRNZ3
ADuM6421ABRNZ3-RL
ADuM6422ABRNZ3
ADuM6422ABRNZ3-RL
EVAL-ADuM6421ARNZ
EVAL-ADuM6421AURNZ
4
4
3
3
2
2
4
4
3
3
2
2
0
0
1
1
2
2
0
0
1
1
2
2
5.0
5.0
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
28-Lead SOIC_W_FP
28-Lead SOIC_W_FP
28-Lead SOIC_W_FP
28-Lead SOIC_W_FP
28-Lead SOIC_W_FP
28-Lead SOIC_W_FP
28-Lead SOIC_W_FP
28-Lead SOIC_W_FP
28-Lead SOIC_W_FP
28-Lead SOIC_W_FP
28-Lead SOIC_W_FP
28-Lead SOIC_W_FP
Evaluation Board2
RN-28-1
RN-28-1
RN-28-1
RN-28-1
RN-28-1
RN-28-1
RN-28-1
RN-28-1
RN-28-1
RN-28-1
RN-28-1
RN-28-1
5.0
5.0
5.0
5.0
3.3
3.3
3.3
3.3
3.3
3.3
Evaluation Board3
1 Z = RoHS Compliant Part.
2 The EVAL-ADuM6421ARNZ is packaged with the ADuM6421ABRNZ5 installed.
3 The EVAL-ADuM6421AURNZ is packaged without a device installed. The ADuM6420A, ADuM6421A, or ADuM6422A must be ordered separately and installed.
©2019–2020 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D21365-12/20(A)
Rev. A | Page 26 of 26
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