ADUM7702BRWZ-RL [ADI]
16-Bit, Isolated, Sigma-Delta Modulator;型号: | ADUM7702BRWZ-RL |
厂家: | ADI |
描述: | 16-Bit, Isolated, Sigma-Delta Modulator |
文件: | 总22页 (文件大小:493K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
16-Bit, Isolated,
Sigma-Delta Modulator
ADuM7702
Data Sheet
FEATURES
FUNCTIONAL BLOCK DIAGRAM
V
V
DD2
DD1
5 MHz to 21 MHz master clock input frequency
Offset drift vs. temperature: 0.25 µV/°C
SNR: 82 dB typical
ADuM7702
CLK
DECODER
CLK
ENCODER
MCLKIN
MDAT
16 bits, no missing codes
Full-scale analog input voltage range: 64 mV
ENOB: 13 bits typical
V
V
IN+
DATA
ENCODER
DATA
DECODER
GAIN
I
DD1: 10 mA maximum
Σ-Δ ADC
IN–
On-board digital isolator
Operating temperature range: −40°C to +125°C
High isolation common-mode transient immunity:
150 kV/µs minimum, VDD2 = 3.3 V
Wide-body SOICs
GND
GND
2
1
Figure 1.
16-lead SOIC_W
8-lead SOIC_IC with increased creepage
Safety and regulatory approvals
UL recognition
5700 V rms for 1 minute per UL 1577
CSA Component Acceptance Notice 5A
VDE Certificate of Conformity
DIN V VDE V 0884-10: VIORM = 1270 VPEAK
DIN V VDE V 0884-11: VIORM = 1060 VPEAK (pending)
APPLICATIONS
Shunt current monitoring
AC motor controls
Power and solar inverters
Wind turbine inverters
Analog-to-digital and optoisolator replacement
GENERAL DESCRIPTION
The ADuM7702 is a high performance, second-order, Σ-Δ
modulator that converts an analog input signal to a high speed,
single-bit data stream, with on-chip digital isolation based on
Analog Devices, Inc., iCoupler® technology. The device operates
from a 4.5 V to 5.5 V power supply range (VDD1) and accepts a
pseudo differential input signal of 50 mV ( 64 mV full-scale).
The pseudo differential input is ideally suited to shunt voltage
monitoring in high voltage applications where galvanic isolation
is required.
The analog input is continuously sampled by a high performance
analog modulator and converted to a ones density digital output
stream with a data rate of up to 21 MHz. The original information
can be reconstructed with an appropriate sinc3 digital filter to
achieve an 82 dB signal-to-noise ratio (SNR) at 78.1 kSPS with a
256 decimation rate and a 20 MHz master clock. The serial input
and output operates from a 5 V or a 3 V supply (VDD2).
The serial interface is digitally isolated. High speed complementary
metal-oxide semiconductor (CMOS) technology, combined with
monolithic transformer technology, results in on-chip isolation
providing outstanding performance characteristics, superior to
alternatives such as optocoupler devices. The ADuM7702 is
available in both a 16-lead SOIC_W and an 8-lead SOIC_IC
and has an operating temperature range of −40°C to +125°C.
Rev. 0
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Technical Support
©2020 Analog Devices, Inc. All rights reserved.
www.analog.com
ADuM7702
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Pin Configurations and Function Descriptions............................9
Typical Performance Characteristics ........................................... 11
Terminology.................................................................................... 14
Theory of Operation ...................................................................... 16
Circuit Information.................................................................... 16
Analog Input ............................................................................... 16
Applications Information.............................................................. 18
Current Sensing Applications................................................... 18
Voltage Sensing Applications.................................................... 18
Input Filter................................................................................... 18
Digital Filter ................................................................................ 19
Interfacing to ADSP-CM4xx .................................................... 20
Grounding and Layout .............................................................. 20
Insulation Lifetime..................................................................... 20
Outline Dimensions....................................................................... 21
Ordering Guide .......................................................................... 22
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Specifications .................................................................. 4
Package Characteristics ............................................................... 5
Insulation and Safety Related Specifications ............................ 5
Regulatory Information............................................................... 5
DIN V VDE V 0884-10 Insulation Characteristics...................... 6
DIN V VDE V 0884-11 Insulation Characteristics (Pending).... 7
Absolute Maximum Ratings............................................................ 8
Thermal Resistance ...................................................................... 8
Insulation Ratings......................................................................... 8
Electrostatic Discharge (ESD) Ratings ...................................... 8
ESD Caution.................................................................................. 8
REVISION HISTORY
7/2020—Revision 0: Initial Version
Rev. 0 | Page 2 of 22
Data Sheet
ADuM7702
SPECIFICATIONS
VDD1 = 4.5 V to 5.5 V, VDD2 = 3 V to 5.5 V, VIN+ = −50 mV to +50 mV, VIN− = 0 V, TA = −40°C to +125°C, and MCLKIN frequency (fMCLKIN) =
20 MHz, tested with a sinc3 filter, and a 256 decimation rate, unless otherwise noted.
Table 1.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
STATIC PERFORMANCE
Resolution
16
Bits
Filter output truncated to 16 bits
Integral Nonlinearity (INL)1
Differential Nonlinearity (DNL)1
Offset Error1
±2
±±
LSB
LSB
mV
mV
μV/°C
μV/°C
μV/V
% FSR
ppm/°C
μV/°C
ppm/V
±0.99
±0.13
±0.1±
±0.2ꢀ
±0.6
Guaranteed no missed codes to 16 bits
Initial at TA = 2ꢀ°C
±0.0ꢀ
±0.1
±0.1
±0.1
±2.ꢀ
Offset Drift vs. Temperature1
16-lead SOIC_W
±-lead SOIC_IC
Offset Drift vs. VDD1
Gain Error1
Gain Error Drift vs. Temperature1
±0.2
±31.3
±ꢁ
Initial at TA = 2ꢀ°C
±1ꢀ.6
±2
±ꢀ
Gain Error Drift vs. VDD1
ANALOG INPUT
Input Voltage Range
−6ꢁ
−ꢀ0
+6ꢁ
+ꢀ0
mV
mV
V
μA
μA
μA
pF
Full-scale range
For specified performance
Input Common-Mode Voltage Range
Dynamic Input Current
−0.2 to +0.±
±1
0.0ꢀ
±0.01
2ꢀ
±2
VIN+ = ±ꢀ0 mV, VIN− = 0 V
VIN+ = 0 V, VIN− = 0 V
DC Leakage Current
Input Capacitance
±0.ꢀ
VIN+ or VIN− left floating
VIN+ = 1 kHz
DYNAMIC SPECIFICATIONS
Signal-to-Noise-and-Distortion Ratio (SINAD)1
SNR1
77
7±.6
−7±
±2
±2
−±9
−97
dB
dB
dB
dB
Total Harmonic Distortion (THD)1
Peak Harmonic or Spurious-Free Dynamic
Range Noise (SFDR)1
Effective Number of Bits (ENOB)1
12.ꢀ
13
Bits
ISOLATION COMMON-MODE TRANSIENT
IMMUNITY (CMTI)1
Common-mode voltage (|VCM|) = 2 kV
Static and Dynamic
7ꢀ
1ꢀ0
1ꢀ0
kV/μs
kV/μs
VDD2 = ꢀ.ꢀ V
VDD2 = 3.3 V
LOGIC INPUTS
CMOS with Schmitt trigger
Input High Voltage (VIH)
Input Low Voltage (VIL)
Input Current (IIN)
Input Capacitance (CIN)
LOGIC OUTPUTS
0.7 × VDD2
V
V
μA
pF
0.3 × VDD2
±0.6
10
Output High Voltage (VOH
Output Low Voltage (VOL
)
VDD2 − 0.ꢁ VDD2 − 0.2
0.2
V
V
Output current (IOUT) = −ꢁ mA
IOUT = ꢁ mA
)
0.ꢁ
Rev. 0 | Page 3 of 22
ADuM7702
Data Sheet
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
POWER REQUIREMENTS
VIN+ > 64 mV
VDD1
VDD2
4.5
3
5.5
5.5
10
3
71.5
66
V
V
mA
mA
mW
mW
VDD1 Current (IDD1
VDD2 Current (IDD2
Power Dissipation
)
)
8.2
2
51
VDD2 = 4.5 V to 5.5 V
VDD2 = 3 V to 3.6 V
47.6
1 See the Terminology section.
TIMING SPECIFICATIONS
VDD1 = 4.5 V to 5.5 V, VDD2 = 3 V to 5.5 V, and TA = −40°C to +125°C, unless otherwise noted. Sample tested during initial release to
ensure compliance. It is recommended to read MDAT on the MCLKIN rising edge.
Table 2.
Limit at TMIN, TMAX
Parameter
fMCLKIN
tMCLKIN
Min
5
48
Typ
20
50
Max
21
200
16
Unit
MHz
ns
ns
ns
Description
Master clock input frequency
Master clock input period
Data access time after MCLKIN rising edge
Data hold time after MCLKIN rising edge
Master clock low time
1
t1
t2
1
5
t3
t4
0.4 × tMCLKIN
0.4 × tMCLKIN
ns
ns
Master clock high time
1 Defined as the time required from an 80% MCLKIN input level to when the output crosses 0.5 × VDD2 as shown in Figure 2. Measured with a 20 µA load and a 25 pF
load capacitance.
Timing Diagram
tMCLKIN
t4
MCLKIN
MDAT
80%
t1
t2
t3
0.5 × V
*
DD2
*SEE NOTE 1 OF TABLE 2 FOR FURTHER DETAILS
Figure 2. Data Timing Diagram
Rev. 0 | Page 4 of 22
Data Sheet
ADuM7702
PACKAGE CHARACTERISTICS
Table 3.
Parameter1
Resistance (Input to Output)
Capacitance (Input to Output)
Symbol
RI-O
CI-O
Min
Typ
1012
1
Max
Unit
Ω
pF
Test Conditions/Comments
Frequency = 1 MHz
1 The device is considered a 2-terminal device. For the 16-lead SOIC_W, Pin 1 to Pin 8 are shorted together and Pin 9 to Pin 16 are shorted together. For the 8-lead
SOIC_IC, Pin 1 to Pin 4 are shorted together and Pin 5 to Pin 8 are shorted together.
INSULATION AND SAFETY RELATED SPECIFICATIONS
Table 4.
Parameter
Symbol Value
Unit
Test Conditions/Comments
Input to Output Momentary Withstand Voltage
Minimum External Air Gap (Clearance)1, 2
16-Lead SOIC_W
VISO
5700 min
V rms
1 minute duration
L(I01)
L(I01)
7.8 min
8.1 min
mm
mm
Measured from input terminals to output terminals,
shortest distance through air
Measured from input terminals to output terminals,
shortest distance through air
8-Lead SOIC_IC
Minimum External Tracking (Creepage)1
16-Lead SOIC_W
L(I02)
L(I02)
7.8 min
8.1 min
mm
mm
Measured from input terminals to output terminals,
shortest distance path along body
Measured from input terminals to output terminals,
shortest distance path along body
8-Lead SOIC_IC
Minimum Internal Gap (Internal Clearance)
Tracking Resistance (Comparative Tracking Index)
Isolation Group
0.041 min mm
Distance through insulation
DIN IEC 112/VDE 0303 Part 1
Material Group (DIN VDE 0110, 1/89, Table I)
CTI
>600
I
V
1 In accordance with IEC 60950-1 guidelines for the measurement of creepage and clearance distances for a pollution degree of 2 and altitudes ≤ 2000 m.
2 Consideration must be given to pad layout to ensure the minimum required distance for clearance is maintained.
REGULATORY INFORMATION
Table 5.
UL
CSA
VDE
Recognized under 1577 Component
Recognition Program1
Approved under CSA Component Acceptance Notice 5A
Certified according to DIN V VDE V 0884-102,
reinforced insulation, VIORM = 1270 VPEAK
VIOSM = 8000 VPEAK
,
5700 V rms Isolation Voltage Single
Protection
Basic insulation per CSA 60950-1-07 and IEC 60950-1,
ADuM7702: 780 V rms (1102 VPEAK), ADuM7702-8:
830 V rms (1173 VPEAK) maximum working voltage3
Reinforced insulation per CSA 60950-1-07 and
IEC 60950-1. ADuM7702: 390 V rms (551 VPEAK),
ADuM7702-8: 415 V rms (586 VPEAK) maximum
working voltage3
Certified according to DIN V VDE V 0884-11,
reinforced insulation, VIORM = 1060 VPEAK
VIOSM = 8000 VPEAK (pending)
,
Reinforced insulation per IEC 60601-1,
261 V rms (369 VPEAK) maximum working voltage
1 In accordance with UL 1577, each ADuM7702 is proof tested by applying an insulation test voltage ≥ 6840 V rms for 1 sec (current leakage detection limit = 15 µA).
2 In accordance with DIN V VDE V 0884-10, each ADuM7702 is proof tested by applying an insulation test voltage ≥ 2344 VPEAK for 1 sec (partial discharge detection limit = 5 pC).
3 Rating is calculated for a pollution degree of 2 and a Material Group III. The ADuM7702 package material is rated by CSA to a CTI of >600 V and, therefore, Material Group I.
Rev. 0 | Page 5 of 22
ADuM7702
Data Sheet
DIN V VDE V 0884-10 INSULATION CHARACTERISTICS
This isolator is suitable for reinforced electrical isolation only within the safety limit data. Maintenance of the safety data is ensured by
means of protective circuits.
Table 6.
Description
Symbol
Characteristic Unit
INSTALLATION CLASSIFICATION PER DIN VDE 0110
For Rated Mains Voltage ≤300 V rms
For Rated Mains Voltage ≤450 V rms
I to IV
I to IV
I to IV
40/125/21
2
For Rated Mains Voltage ≤600 V rms
CLIMATIC CLASSIFICATION
POLLUTION DEGREE (DIN VDE 0110, TABLE 1)
MAXIMUM WORKING INSULATION VOLTAGE
INPUT TO OUTPUT TEST VOLTAGE, METHOD B1
VIORM × 1.875 = VPR, 100% Production Test, tm = 1 Second, Partial Discharge < 5 pC
INPUT TO OUTPUT TEST VOLTAGE, METHOD A
After Environmental Test Subgroup 1
VIORM
1270
VPEAK
VPEAK
VPD(M)
VPR(M)
2344
VIORM × 1.6 = VPR, tm = 60 sec, Partial Discharge < 5 pC
After Input and/or Safety Test Subgroup 2/Safety Test Subgroup 3
VIORM × 1.2 = VPR, tm = 60 sec, Partial Discharge < 5 pC
HIGHEST ALLOWABLE OVERVOLTAGE (TRANSIENT OVERVOLTAGE, tTR = 10 sec)
SURGE ISOLATION VOLTAGE
1.2 µs Rise Time, 50 µs, 50% Fall Time
SAFETY LIMITING VALUES (MAXIMUM VALUE ALLOWED IN THE EVENT OF A FAILURE)1
Case Temperature
2032
VPEAK
1524
8000
VPEAK
VPEAK
VIOTM
VIOSM
8000
150
VPEAK
°C
TS
Side 1 (PVDD1) and Side 2 (PVDD2) Power Dissipation
16-Lead SOIC_W
8-Lead SOIC_IC
PSO
1.43
1.19
>109
W
W
Ω
INSULATION RESISTANCE AT TS, VOLTAGE INPUT TO OUTPUT (VIO) = 500 V
RIO
1 See Figure 3.
2.0
16-LEAD SOIC_W
8-LEAD SOIC_IC
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
0
50
100
150
200
AMBIENT TEMPERATURE (°C)
Figure 3. Thermal Derating Curve, Dependence of Safety Limiting Values with Case Temperature per DIN V VDE V 0884-10
Rev. 0 | Page 6 of 22
Data Sheet
ADuM7702
DIN V VDE V 0884-11 INSULATION CHARACTERISTICS (PENDING)
This isolator is suitable for reinforced electrical isolation only within the safety limit data. Maintenance of the safety data is ensured by
means of protective circuits.
Table 7.
Description
Symbol
Characteristic Unit
INSTALLATION CLASSIFICATION PER DIN VDE 0110
For Rated Mains Voltage ≤300 V rms
For Rated Mains Voltage ≤450 V rms
I to IV
I to IV
I to IV
40/125/21
2
For Rated Mains Voltage ≤600 V rms
CLIMATIC CLASSIFICATION
POLLUTION DEGREE (DIN VDE 0110, TABLE 1)
MAXIMUM WORKING INSULATION VOLTAGE
INPUT TO OUTPUT TEST VOLTAGE, METHOD B1
VIORM × 1.875 = VPR, 100% Production Test, tm = 1 sec, Partial Discharge < 5 pC
INPUT TO OUTPUT TEST VOLTAGE, METHOD A
After Environmental Test Subgroup 1
VIORM
1060
VPEAK
VPEAK
VPD(M)
VPR(M)
1987
VIORM × 1.6 = VPR, tm = 60 sec, Partial Discharge < 5 pC
After Input and/or Safety Test Subgroup 2/Safety Test Subgroup 3
VIORM × 1.2 = VPR, tm = 60 sec, Partial Discharge < 5 pC
HIGHEST ALLOWABLE OVERVOLTAGE (TRANSIENT OVERVOLTAGE, tTR = 10 sec)
SURGE ISOLATION VOLTAGE
1.2 µs Rise Time, 50 µs, 50% Fall Time
SAFETY LIMITING VALUES (MAXIMUM VALUE ALLOWED IN THE EVENT OF A FAILURE)1
Case Temperature
1696
VPEAK
1272
8000
VPEAK
VPEAK
VIOTM
VIOSM
8000
150
VPEAK
°C
TS
Side 1 (PVDD1) and Side 2 (PVDD2) Power Dissipation
16-Lead SOIC_W
8-Lead SOIC_IC
PSO
1.43
1.19
>109
W
W
Ω
INSULATION RESISTANCE AT TS, VIO = 500 V
RIO
1 See Figure 4.
2.0
16-LEAD SOIC_W
8-LEAD SOIC_IC
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
0
50
100
150
200
AMBIENT TEMPERATURE (°C)
Figure 4. Thermal Derating Curve, Dependence of Safety Limiting Values with Case Temperature per DIN V VDE V 0884-11
Rev. 0 | Page 7 of 22
ADuM7702
Data Sheet
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted. All voltages are relative to
their respective GNDx.
INSULATION RATINGS
The maximum continuous working voltage refers to the
continuous voltage magnitude imposed across the isolation
barrier. See the Insulation Lifetime section for more details.
Table 8.
Parameter
Rating
VDD1 to GND1
VDD2 to GND2
−0.3 V to +6 V
−0.3 V to +6 V
−1 V to 4.3 V
−0.5 V to VDD2 + 0.5 V
−0.5 V to VDD2 + 0.5 V
10 mA
Table 10. Maximum Continuous Working Voltage
Insulation
Analog Input Voltage to GND1
Digital Input Voltage to GND2
Digital Output Voltage to GND2
Input Current to Any Pin Except Supplies1
Output Current from Any Pin Except
Supplies
Temperature
Operating Range
Storage Range
Junction
Parameter
Rating1
Lifetime Conditions
Basic Insulation
AC Voltage
Bipolar Waveform
1129 VPEAK
20 years to 1000 ppm
failure at 1129 VPEAK
(798 V rms, 50 Hz/
60 Hz sine wave)
10 mA
−40°C to +125°C
−65°C to +150°C
150°C
Reinforced Insulation
AC Voltage
Bipolar Waveform
1060 VPEAK
20 years to 1 ppm
failure at 1060 VPEAK
(750 V rms, 50 Hz/
60 Hz sine wave)
Pb-Free, Soldering
Reflow
1 Transient currents of up to 100 mA do not cause silicon controlled rectifier
(SCR) to latch up.
260°C
1 Insulation capability without regard to creepage limitations. Working
voltage may be limited by the PCB creepage when considering rms voltages
for components soldered to a PCB (assumes Material Group I up to 1270 V
rms), or package: RI-8-1 package creepage of 8.1 mm and RW-16 package
creepage of 7.8 mm, when considering rms voltages for Material Group I.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ELECTROSTATIC DISCHARGE (ESD) RATINGS
The following ESD information is provided for handling of
ESD-sensitive devices in an ESD protected area only.
Human body model (HBM) per ANSI/ESDA/JEDEC JS-001.
THERMAL RESISTANCE
Field induced charged device model (FICDM) per
ANSI/ESDA/JEDEC JS-002.
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Close attention to
PCB thermal design is required.
ESD Ratings for ADuM7702
Table 11. ADuM7702, 16-Lead SOIC_W and 8-Lead
SOIC_IC
ESD Model Withstand Threshold (V)
Table 9. Thermal Resistance
Package Type1
RI-8-1
θJA
ΨJC
Unit
°C/W
°C/W
2
3
Class
3A
C4
105
87.25
9.25
10.4
HBM1
FICDM2
3500
1500
RW-16
1 Thermal impedance simulated values are based on a JEDEC 2S2P thermal
test board. See JEDEC JESD-51.
1 JESD22-C101, RC network,1 Ω, and package capacitance.
2 ESDA/JEDEC JS-001-2011, RC network: 1.5 kΩ and 100 pF.
2 θJA was calculated using the total power and maximum junction
temperature.
3 ΨJC was calculated using the package center case temperature.
ESD CAUTION
Rev. 0 | Page 8 of 22
Data Sheet
ADuM7702
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
NIC
GND
2
1
IN+
IN–
V
V
NIC
V
2
DD2
ADuM7702
GND
NIC
NIC
V
MCLKIN
1
1
1
TOP VIEW
NIC
2
(Not to Scale)
MDAT
NIC
2
DD1
GND
2
GND
1
NOTES
1. NIC = NOT INTERNALLY CONNECTED. THESE PINS ARE NOT INTERNALLY CONNECTED.
1
CONNECT TO VDD , GND , OR LEAVE FLOATING.
1
1
2. NIC = NOT INTERNALLY CONNECTED. THESE PINS ARE NOT INTERNALLY CONNECTED.
2
CONNECT TO VDD , GND , OR LEAVE FLOATING.
2
2
Figure 5. 16-Lead SOIC_W Pin Configuration
Table 12. 16-Lead SOIC_W Pin Function Descriptions
Pin No.
Mnemonic Description
1, 5, 6
NIC1
Not Internally Connected. These pins are not internally connected. Connect these pins to VDD1, GND1, or leave
floating.
2
VIN+
Positive Analog Input.
3
VIN−
Negative Analog Input.
4, 8
7
GND1
VDD1
Ground 1. These pins are the ground reference points for all circuitry on the isolated side.
Supply Voltage, 4.5 V to 5.5 V. VDD1 is the supply voltage for the isolated side of the ADuM7702 and is relative to
GND1. Decouple VDD1 to GND1 with a 10 µF capacitor in parallel with a 100 nF capacitor as close to VDD1 as possible.
9, 16
10, 12, 15
GND2
NIC2
Ground 2. These pins are the ground reference points for all circuitry on the nonisolated side.
Not Internally Connected. These pins are not internally connected. Connect these pins to VDD2, GND2, or leave
floating.
11
13
14
MDAT
MCLKIN
VDD2
Serial Data Output. The single-bit modulator output is supplied to MDAT as a serial data stream. The bits are
clocked out on the rising edge of the MCLKIN input and are valid on the following MCLKIN rising edge.
Master Clock Logic Input. 5 MHz to 21 MHz frequency range. The bit stream from the modulator is propagated on
the rising edge of MCLKIN.
Supply Voltage, 3 V to 5.5 V. VDD2 is the supply voltage for the nonisolated side and is relative to GND2. Decouple
VDD2 to GND2 with a 10 µF capacitor in parallel with a 100 nF capacitor as close to VDD2 as possible.
Rev. 0 | Page 9 of 22
ADuM7702
Data Sheet
V
1
2
3
4
8
7
6
5
V
DD2
DD1
V
ADuM7702
MCLKIN
MDAT
IN+
TOP VIEW
V
IN–
(Not to Scale)
GND
GND
2
1
Figure 6. 8-Lead SOIC_IC Pin Configuration
Table 13. 8-Lead SOIC_IC Pin Function Descriptions
Pin No. Mnemonic Description
1
VDD1
Supply Voltage, 4.5 V to 5.5 V. VDD1 is the supply voltage for the isolated side of the ADuM7702 and is relative to GND1.
Decouple VDD1 to GND1 with a 10 µF capacitor in parallel with a 100 nF capacitor as close to VDD1 as possible.
2
3
4
5
6
VIN+
VIN−
GND1
GND2
MDAT
Positive Analog Input.
Negative Analog Input.
Ground 1. This pin is the ground reference point for all circuitry on the isolated side.
Ground 2. This pin is the ground reference point for all circuitry on the nonisolated side.
Serial Data Output. The single-bit modulator output is supplied to MDAT as a serial data stream. The bits are clocked
out on the rising edge of the MCLKIN input and are valid on the following MCLKIN rising edge.
7
8
MCLKIN
VDD2
Master Clock Logic Input. 5 MHz to 21 MHz frequency range. The bit stream from the modulator is propagated on
the rising edge of the MCLKIN.
Supply Voltage, 3 V to 5.5 V. This pin is the supply voltage for the nonisolated side and is relative to GND2. Decouple
this supply to GND2 with a 10 µF capacitor in parallel with a 100 nF capacitor as close to the pin as possible.
Rev. 0 | Page 10 of 22
Data Sheet
ADuM7702
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VDD1 = 5 V, V DD2 = 5 V, V IN+ = −50 mV to +50 m V, V IN− = 0 V, and fMCLKIN = 20 MHz, using a sinc3 filter with a
256 oversampling ratio (OSR), unless otherwise noted.
0
–20
0
fIN = 1kHz
SNR = 82.71dB
SINAD = 82.54dB
THD = –96.65dB
–20
–40
–40
–60
–60
–80
–80
–100
–120
–140
–160
–100
–120
–140
0
5000
10000
15000
20000
25000
30000
0
200
400
600
800
1000
SUPPLY RIPPLE FREQUENCY (kHz)
FREQUENCY (kHz)
Figure 10. Typical Fast Fourier Transform (FFT)
Figure 7. Power Supply Rejection Ratio (PSRR) vs. Supply Ripple Frequency
1.0
0.8
0
SHORTED V
200mV p-p SINE WAVE ON INPUTS
INPUTS
IN±
–20
–40
0.6
0.4
0.2
–60
0
–80
–0.2
–0.4
–0.6
–0.8
–1.0
–100
–120
–140
MCLKIN = 10MHz, SINC3 OSR = 256
MCLKIN = 20MHz, SINC3 OSR = 256
0
10000
20000
30000
CODE
40000
50000
60000
0.1
1
10
100
1000
COMMON-MODE RIPPLE FREQUENCY (kHz)
Figure 11. Typical DNL Error
Figure 8. Common-Mode Rejection Ration (CMRR) vs. Common-Mode Ripple
Frequency
2.0
1.5
88
SINAD 20MHz MCLKIN
SINAD 10MHz MCLKIN
86
84
82
80
78
76
74
72
70
68
1.0
0.5
0.0
–0.5
–1.0
–1.5
–2.0
0.1
1
10
0
10000
20000
30000
CODE
40000
50000
60000
ANALOG INPUT FREQUECNCY (kHz)
Figure 9. SINAD vs. Analog Input Frequency
Figure 12. Typical INL Error
Rev. 0 | Page 11 of 22
ADuM7702
Data Sheet
14
12
10
8
100
80
DEVICE 1
DEVICE 2
DEVICE 3
11.51
11.226
60
10.237
40
8.627
20
7.107
0
6
5.57
–20
–40
–60
–80
–100
4.145
4
2.81
1.752
0.616
2
1.139
0.384
0.016
0.008
0.006
0.198
0.004
0.041
0.11
0
–40 –25 –10
5
20
35
50
65
80
95 110 125
TEMPERATURE (°C)
CODE
Figure 13. Histogram of Codes at the Code Center
Figure 16. Offset vs. Temperature
100
100
DEVICE 1
DEVICE 2
DEVICE 3
SNR
SINAD
80
60
90
80
70
60
40
20
0
–20
–40
–60
–80
–100
–40 –25 –10
5
20
35
50
65
80
95 110 125
4.50
4.75
5.00
(V)
5.25
5.50
TEMPERATURE (°C)
V
DD1
Figure 17. Offset vs. VDD1
Figure 14. SNR and SINAD vs. Temperature
–60
–70
1.0
0.8
THD
SFDR
DEVICE 1
DEVICE 2
DEVICE 3
0.6
0.4
–80
0.2
–90
0
–0.2
–0.4
–0.6
–0.8
–1.0
–100
–110
–120
–40 –25 –10
5
20
35
50
65
80
95 110 125
–40 –25 –10
5
20
35
50
65
80
95 110 125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 18. Gain Error vs. Temperature
Figure 15. THD and SFDR vs. Temperature
Rev. 0 | Page 12 of 22
Data Sheet
ADuM7702
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
0.25
0.20
0.15
0.10
0.05
0
MCLKIN = 10MHz, –40°C
MCLKIN = 10MHz, +25°C
MCLKIN = 10MHz, +125°C
MCLKIN = 20MHz, –40°C
MCLKIN = 20MHz, +25°C
MCLKIN = 20MHz, +125°C
–0.05
–0.10
–0.15
–0.20
–0.25
4.50
3
3.5
4
4.5
5
5.5
4.75
5.00
(V)
5.25
5.50
V
(V)
V
DD2
DD1
Figure 22. IDD2 vs. VDD2 at Various Clock Rates and Temperatures
Figure 19. Gain Error vs. VDD1
5.0
16
T
T
T
T
T
= –40°C
= 0°C
= +25°C
= +85°C
= +125°C
A
A
A
A
A
MCLKIN = 10MHz, –40°C
DC INPUT
MCLKIN = 10MHz, +25°C
MCLKIN = 10MHz, +125°C
MCLKIN = 20MHz, –40°C
MCLKIN = 20MHz, +25°C
MCLKIN = 20MHz, +125°C
14
12
10
8
4.5
4.0
3.5
3.0
2.5
2.0
6
4
2
0
4.50
–50
–25
0
25
50
4.75
5.00
(V)
5.25
5.50
V
(mV)
V
IN+
DD1
Figure 23. IDD2 vs. VIN+, DC Input at Various Temperatures
Figure 20. IDD1 vs. VDD1 at Clock Rates and Various Temperatures
500
400
300
200
100
0
10.0
MLCKIN = 10MHz
DC INPUT
DC INPUT
MLCKIN = 20MHz
9.5
9.0
8.5
8.0
7.5
7.0
6.5
–100
–200
–300
T
T
T
T
T
= –40°C
= 0°C
= +25°C
= +85°C
= +125°C
A
A
A
A
A
6.0
5.5
5.0
10
30
50
–50
–25
0
25
50
V
(mV)
V
(mV)
IN+
IN+
Figure 21. IDD1 vs. VIN+, DC Input at Various Temperatures
Figure 24. VIN+ Current (IIN+) vs. VIN+, DC Input
Rev. 0 | Page 13 of 22
ADuM7702
Data Sheet
TERMINOLOGY
Signal-to-Noise-and-Distortion Ratio (SINAD)
Differential Nonlinearity (DNL)
SINAD is the measured ratio of signal to noise and distortion at
the output of the ADC. The signal is the rms value of the sine
wave, and noise is the rms sum of all nonfundamental signals
up to half the sampling frequency (fS/2), including harmonics,
but excluding dc.
DNL is the difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the analog-to-digital
converter (ADC).
Integral Nonlinearity (INL)
INL is the maximum deviation from a straight line passing
through the endpoints of the ADC transfer function. The
endpoints of the transfer function are specified negative full
scale, −50 mV (VIN+ − VIN−), Code 7168 for the 16-bit level, and
specified positive full scale, +50 mV (VIN+ − VIN−), Code 58,368
for the 16-bit level.
Signal-to-Noise Ratio (SNR)
SNR is the measured ratio of signal to noise at the output of the
ADC. The signal is the rms amplitude of the fundamental. Noise
is the sum of all nonfundamental signals up to half the sampling
frequency (fS/2), excluding dc.
The ratio is dependent on the number of quantization levels in the
digitization process, that is, the greater the number of levels, the
smaller the quantization noise. The theoretical SNR for an ideal
N-bit converter with a sine wave input is given by
Offset Error
Offset error is the deviation of the midscale code (32,768 for
the 16-bit level) from the ideal VIN+ − VIN− (that is, 0 V).
Offset Drift vs. Temperature
The offset drift is calculated using the box method, as shown
by the following equation:
SNR = (6.02N + 1.76) dB
Therefore, for a 12-bit converter, the SNR is 74 dB.
Isolation Common-Mode Transient Immunity (CMTI)
The isolation CMTI specifies the rate of the rise and fall of a
transient pulse applied across the isolation boundary, beyond
which clock or data is corrupted. Both the rate of change and
the absolute common-mode voltage of the pulse are recorded.
The ADuM7702 is tested under both static and dynamic CMTI
conditions. Static testing detects single-bit errors from the
device. Dynamic testing monitors the filtered data output for
variations in noise performance to a randomized application
of the CMTI pulse.
Offset Drift = ((VoltageMAX − VoltageMIN)/TΔ)
where:
VoltageMAX is the maximum offset error point recorded.
VoltageMIN is the minimum offset error point recorded.
TΔ is the difference in temperature between the maximum
and minimum operating range.
Gain Error
The gain error includes both positive full-scale gain error and
negative full-scale gain error. Positive full-scale gain error is the
deviation of the specified positive full-scale code (58,368 for the
16-bit level) from the ideal VIN+ − VIN− (50 mV) after the offset
error is adjusted out. Negative full-scale gain error is the deviation
of the specified negative full-scale code (7168 for the 16-bit level)
from the ideal VIN+ − VIN− (−50 mV) after the offset error is
adjusted out.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the harmonics to the
fundamental. It is defined as
V22 +V32 +V42 +V52 +V62
THD (dB) = 20log
V1
Gain Error Drift vs. Temperature
The gain error drift (GED) is calculated using the box method,
as shown by the following equation:
where:
V2, V3, V4, V5, and V6 are the rms amplitudes of the second
through the sixth harmonics.
V1 is the rms amplitude of the fundamental.
GED (ppm) = ((VoltageMAX − VoltageMIN)/(VoltageFS ×
TΔ)) × 106
Peak Harmonic or Spurious-Free Dynamic Range (SFDR) Noise
Peak harmonic or SFDR noise is defined as the ratio of the rms
value of the next largest component in the ADC output spectrum
(up to fS/2, excluding dc) to the rms value of the fundamental.
Normally, the value of this specification is determined by the
largest harmonic in the spectrum, but for ADCs where the
harmonics are buried in the noise floor, it is a noise peak.
where:
VoltageMAX is the maximum gain error point recorded.
VoltageMIN is the minimum gain error point recorded.
VoltageFS is the analog input range full scale.
TΔ is the difference in temperature between the maximum
and minimum operating range.
Rev. 0 | Page 14 of 22
Data Sheet
ADuM7702
Effective Number of Bits (ENOB)
ENOB is defined by
Common-Mode Rejection Ratio (CMRR)
CMRR is the ratio of the power in the ADC output at 50 mV
frequency, f, to the power of a +50 mV p-p sine wave applied to
the common-mode voltage of VIN+ and VIN− of frequency, fS, as
ENOB = (SINAD − 1.76)/6.02 bits
Noise Free Code Resolution
CMRR (dB) = 10 log(Pf/PfS)
Noise free code resolution represents the resolution in bits for
which there is no code flicker. The noise free code resolution for
an N-bit converter is defined as
Noise Free Code Resolution (Bits) = log2(2N/Peak-to-Peak Noise)
where:
Pf is the power at frequency, f, in the ADC output.
PfS is the power at frequency, fS, in the ADC output.
Power Supply Rejection Ratio (PSRR)
The peak-to-peak noise in LSBs is measured with VIN+ = VIN− = 0 V.
Variations in power supply affect the full-scale transition but
not the linearity of the converter. PSRR is the maximum change
in the specified full-scale ( 50 mV) transition point due to a
change in power supply voltage from the nominal value.
Rev. 0 | Page 15 of 22
ADuM7702
Data Sheet
THEORY OF OPERATION
A differential signal of 0 V ideally results in a stream of alternating
1s and 0s at the MDAT output pin. This output is high 50% of
the time and low 50% of the time. A differential input of 50 mV
produces a stream of 1s and 0s that are high 89.06% of the time.
A differential input of −50 mV produces a stream of 1s and 0s
that are high 10.94% of the time.
CIRCUIT INFORMATION
The ADuM7702 isolated Σ-Δ modulator converts an analog
input signal to a high speed (21 MHz maximum), single-bit data
stream. The time average single-bit data from the modulator is
directly proportional to the input signal. Figure 25 shows a
typical application circuit where the ADuM7702 provides
isolation between the analog input, a current sensing resistor
or shunt, and the digital output, which is then processed by a
digital filter to provide an N-bit word.
A differential input of 64 mV ideally results in a stream of all 1s.
A differential input of −64 mV ideally results in a stream of all
0s. The ADuM7702 absolute full-scale range is 64 mV, and the
specified performance range is 50 mV, as shown in Table 14.
ANALOG INPUT
Table 14. Analog Input Range
The pseudo differential analog input of the ADuM7702 is
implemented with a switched capacitor circuit. This circuit
implements a second-order modulator stage that digitizes the
input signal to a single-bit output stream. The sample clock
(MCLKIN) provides the clock signal for the conversion process
as well as the output data framing clock. This clock source is
externally supplied to the ADuM7702. The analog input signal
is continuously sampled by the modulator and compared to
an internal voltage reference. A digital stream that accurately
represents the analog input over time appears at the output of
the converter (see Figure 26).
Analog Input
Voltage Input (mV)
Positive Full-Scale (+FS) Value
Positive Specified Performance
Zero
+64
+50
0
Negative Specified Performance
Negative Full-Scale (−FS) Value
−50
−64
FLOATING
POWER SUPPLY
–400V
NONISOLATED
5V/3.3V
GATED
10µF 100nF
DRIVE
ADuM7702
V
V
V
DD
DD1
DD2
CIRCUIT
SINC3 FILTER*
MDAT
5.1V
220pF
10Ω
Σ-Δ
MOD/
CS
MDAT
ENCODER
DECODER
ENCODER
V
V
IN+
SCLK
R
SHUNT
10Ω
MCLKIN
MCLK
MOTOR
IN–
SDAT
220pF
FLOATING
POWER SUPPLY
100nF
10µF
DECODER
GND
2
GND
GND
1
GATED
DRIVE
CIRCUIT
*THIS FILTER IS IMPLEMENTED
WITH AN FPGA OR DSP
–400V
Figure 25. Typical Application Circuit
MODULATOR OUTPUT
+FS ANALOG INPUT
–FS ANALOG INPUT
ANALOG INPUT
Figure 26. Analog Input vs. Modulator Output
Rev. 0 | Page 16 of 22
Data Sheet
ADuM7702
To reconstruct the original information, this output must be
digitally filtered and decimated. A sinc3 filter is recommended
because this filter is one order higher than that of the ADuM7702
modulator, which is a second-order modulator. When a
256 decimation rate is used, the resulting 16-bit word rate is
78.1 kSPS, assuming a 20 MHz external clock frequency. See the
Digital Filter section for more detailed information on the sinc
filter implementation. Figure 27 shows the transfer function of
the ADuM7702 relative to the 16-bit output.
65535
58368
SPECIFIED RANGE
7168
0
–64mV
–50mV
ANALOG INPUT
+50mV +64mV
Figure 27. Filtered and Decimated 16-Bit Transfer Function
Rev. 0 | Page 17 of 22
ADuM7702
Data Sheet
APPLICATIONS INFORMATION
fIN = 1kHz
CURRENT SENSING APPLICATIONS
MCLKIN = 20MHz
V
V
= 5V
= 3.3V
DD1
DD2
13-BIT
ENOB
The ADuM7702 is ideally suited for current sensing applications
where the voltage across a shunt resistor (RSHUNT) is monitored.
The load current flowing through an external shunt resistor
produces a voltage at the input terminals of the ADuM7702.
The ADuM7702 provides isolation between the analog input
from the current sensing resistor and the digital outputs. By
selecting the appropriate shunt resistor value, a variety of current
ranges can be monitored.
T
= 25°C
A
12-BIT
ENOB
11-BIT
ENOB
Choosing RSHUNT
RSHUNT values used in conjunction with the ADuM7702 are
determined by the specific application requirements in terms
of voltage, current, and power. Small resistors minimize power
dissipation, whereas low inductance resistors prevent any
induced voltage spikes, and high tolerance devices reduce
current variations. The final values chosen are a compromise
between low power dissipation and accuracy. Higher value
resistors use the full performance input range of the ADC,
thus achieving maximum SNR performance. Low value resistors
dissipate less power but do not use the full performance input
range. The ADuM7702, however, delivers excellent performance,
even with lower input signal levels, allowing low value shunt
resistors to be used while maintaining system performance.
0
10
20
30
40
50
V
(mV)
IN+
Figure 28. SINAD vs. VIN+ AC Input Signal Amplitude
RSHUNT must dissipate the current2 × resistance (I2R) power
losses. If the power dissipation rating of the resistor is exceeded,
the value may drift, or the resistor may be damaged, resulting in
an open circuit. This open circuit may result in a differential
voltage across the terminals of the ADuM7702, in excess of the
absolute maximum ratings. If ISENSE has a large high frequency
component, choose a resistor with low inductance.
VOLTAGE SENSING APPLICATIONS
The ADuM7702 can also be used for isolated voltage monitoring.
For example, in motor control applications, the device can be
used to sense the bus voltage. In applications where the voltage
being monitored exceeds the specified analog input range of the
ADuM7702, a voltage divider network can be used to reduce
the voltage being monitored to the required range.
To choose a suitable shunt resistor, first determine the current
through the shunt. Calculate the shunt current for a 3-phase
induction motor by using the following equation:
I
RMS = PW/(1.73 × V × EF × PF)
where:
RMS is the motor phase current (A rms).
INPUT FILTER
I
In a typical use case for directly measuring the voltage across a
shunt resistor, the ADuM7702 can be connected directly across
the shunt resistor with a simple RC low-pass filter on each input.
PW is the motor power (W).
V is the motor supply voltage (V ac).
EF is the motor efficiency (%).
PF is the power efficiency (%).
The recommended circuit configuration for driving the differential
inputs to achieve best performance is shown in Figure 29. An
RC low-pass filter is placed on both the analog input pins.
Recommended values for the resistors and capacitors are 10 Ω and
220 pF, respectively. If possible, equalize the source impedance
on each analog input to minimize offset.
To determine the shunt peak sense current (ISENSE), consider the
motor phase current and any overload that may be possible in
the system. When the peak sense current is known, divide the
voltage range of the ADuM7702 ( 50 mV) by the peak sense
current to yield a maximum shunt value.
If the power dissipation in the shunt resistor is too large, the
shunt resistor can be reduced and less of the ADC input
range can be used. Figure 28 shows the SINAD performance
characteristics and the ENOB of resolution for the ADuM7702
for different input signal amplitudes. The performance of the
ADuM7702 at lower input signal ranges allows smaller shunt
values to be used while still maintaining a high level of
performance and overall system efficiency.
C
R
V
V
IN+
ADuM7702
R
IN–
C
Figure 29. RC Low-Pass Filter Input Network
Rev. 0 | Page 18 of 22
Data Sheet
ADuM7702
The input filter configuration for the ADuM7702 is not limited
to the low-pass structure shown in Figure 29. The differential RC
filter configuration shown in Figure 30 also achieves excellent
performance. Recommended values for the resistors and
capacitor are 22 Ω and 47 pF, respectively.
A sinc3 filter is recommended for the ADuM7702. This filter
can be implemented on a field programmable gate array
(FPGA) or a digital signal processor (DSP). Equation 1
describes the transfer function of a sinc filter.
N
1− Z−DR
1− Z−1
(
)
R
1
DR
V
(1)
H (Z) =
IN+
C
ADuM7702
R
V
IN–
where:
Z is the sample.
DR is the decimation rate.
Figure 30. Differential RC Filter Network
DIGITAL FILTER
N is the sinc filter order.
The output of the ADuM7702 is a continuous digital bit stream.
To reconstruct the original input signal information, this output
bit stream must be digitally filtered and decimated. A sinc filter
is recommended due to simplicity of the filter. A sinc3 filter is
recommended because the filter is one order higher than that of
the ADuM7702 modulator, which is a second-order modulator.
The type of filter selected, the decimation rate, and the modulator
clock used determines the overall system resolution and
throughput rate. The higher the decimation rate, the greater the
system accuracy, as shown in Figure 31. However, there is a
trade-off between accuracy and throughput rate and, therefore,
higher decimation rates result in lower throughput solutions.
Note that for a given bandwidth requirement, a higher MCLKIN
frequency can allow higher decimation rates to be used, resulting
in higher SNR performance.
The throughput rate of the sinc filter is determined by the
modulator clock and the decimation rate selected.
Throughput = MCLK/DR
(2)
(3)
where MCLK is the modulator clock frequency
As the decimation rate increases, the data output size from
the sinc filter increases. The output data size is expressed in
Equation 3. The 16 most significant bits are used to return a
16-bit result.
Data Size = N × log2 DR
For a sinc3 filter, the −3 dB filter response point can be derived
from the filter transfer function, Equation 1, and is 0.262 times
the throughput rate. The filter characteristics for a third-order
sinc filter are summarized in Table 15.
100
80
60
40
20
0
10
100
1000
DECIMATION RATE
Figure 31. SNR vs. Decimation Rate of Sinc3 Filter Order
Table 15. Sinc3 Filter Characteristics for a 20 MHz MCLKIN
Decimation Ratio (DR)
Throughput Rate (kHz)
Output Data Size (Bits)
Filter Response (kHz)
32
64
128
256
512
625
15
18
21
24
27
163.7
81.8
40.9
20.4
10.2
312.5
156.2
78.1
39.1
Rev. 0 | Page 19 of 22
ADuM7702
Data Sheet
Minimize series resistance in the analog inputs to avoid any
INTERFACING TO ADSP-CM4xx
distortion effects, especially at high temperatures. If possible,
equalize the source impedance on each analog input to minimize
offset. Check for mismatch and thermocouple effects on the analog
input PCB tracks to reduce offset drift.
The ADSP-CM4xx family of mixed-signal control processors
contains an on-chip sinc filter and clock generation modules for
direct connection to the ADuM7702 MCLKIN and MDAT pins.
The ADSP-CM4xx can process bit streams from four ADuM7702
devices using a pair of configurable sinc filters for each bit stream.
The primary sinc filter of each pair produces the filtered and
decimated output for the pair. The output can be decimated to
any integer rate between 8 times and 256 times lower than the
input rate. The four secondary sinc filters are low latency filters
with programmable positive and negative overrange detection
comparators that can detect system fault conditions
INSULATION LIFETIME
All insulation structures eventually break down when subjected
to voltage stress over a sufficiently long period. The rate of
insulation degradation is dependent on the characteristics of
the voltage waveform applied across the insulation. In addition
to the testing performed by the regulatory agencies, Analog
Devices carries out an extensive set of evaluations to determine
the lifetime of the insulation structure within the ADuM7702.
Figure 32 shows the typical interface between the ADuM7702
and the ADSP-CM4xx. Additional information on the
configuration of the sinc filter modules in the ADSP-CM4xx
can be found in the AN-1265 Application Note.
Analog Devices performs accelerated life testing using voltage
levels higher than the rated continuous working voltage.
Acceleration factors for several operating conditions are
determined. These factors allow calculation of the time to
failure at the actual working voltage. The values shown in Table 10
summarize the peak voltage for 37.5 years of (reinforced) service
life for a bipolar, ac operating condition and the maximum
VDE approved working voltages.
SINC PAIR n
PRIMARY
SINC0_D0
LIMIT
MDAT
SECONDARY
These tests subjected the ADuM7702 to continuous cross isolation
voltages. To accelerate the occurrence of failures, the selected
test voltages were values exceeding those of normal use. The
time to failure values of these units were recorded and used to
calculate the acceleration factors. These factors were then used to
calculate the time to failure under the normal operating
conditions. The values shown in Table 10 are the lesser of the
following two values:
CONTROL FOR GROUP n
SINC0_CLK0
MODULATOR CLOCK n
MCLKIN
ADSP-CM40xF*
ADuM7702*
*ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 32. Interfacing the ADuM7702 to the ADSP-CM4xx
GROUNDING AND LAYOUT
•
The value that ensures at least a 37.5 year lifetime of
continuous (reinforced) use.
The maximum VDE approved working voltage.
It is recommended to decouple the VDD1 supply with a 10 µF
capacitor in parallel with a 100 nF capacitor to GND1. Decouple
the VDD2 supply with a 10 µF capacitor in parallel with a 100 nF
capacitor to GND2. In applications involving high common-
mode transients, ensure that board coupling across the isolation
barrier is minimized. Furthermore, design the board layout so
that any coupling that occurs equally affects all pins on a given
component side. Failure to ensure equal coupling can cause
voltage differentials between pins to exceed the absolute maximum
ratings of the device, thereby leading to latch-up or permanent
damage. Place any decoupling used as close to the supply pins
(VDDx) as possible.
•
The lifetime of the ADuM7702 is guaranteed using a bipolar
ac waveform as shown in Figure 33.
RATED PEAK VOLTAGE
0V
Figure 33. Bipolar AC Waveform, 50 Hz or 60 Hz
Rev. 0 | Page 20 of 22
Data Sheet
ADuM7702
OUTLINE DIMENSIONS
10.50 (0.4134)
10.10 (0.3976)
16
1
9
8
7.60 (0.2992)
7.40 (0.2913)
10.65 (0.4193)
10.00 (0.3937)
0.75 (0.0295)
0.25 (0.0098)
1.27 (0.0500)
BSC
45°
2.65 (0.1043)
2.35 (0.0925)
0.30 (0.0118)
0.10 (0.0039)
8°
0°
COPLANARITY
0.10
SEATING
PLANE
0.51 (0.0201)
0.31 (0.0122)
1.27 (0.0500)
0.40 (0.0157)
0.33 (0.0130)
0.20 (0.0079)
COMPLIANT TO JEDEC STANDARDS MS-013-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 34. 16-Lead Standard Small Outline Package [SOIC_W]
Wide Body
(RW-16)
Dimensions shown in millimeters and (inches)
6.05
5.85
5.65
8
1
5
4
7.60
7.50
7.40
10.51
10.31
10.11
PIN 1
MARK
0.75
0.50 45°
0.25
2.45
2.35
2.25
2.65
2.50
2.35
1.04
BSC
8°
0°
0.30
0.33
0.27
0.20
SEATING
PLANE
0.20
0.10
COPLANARITY
0.10
0.51
0.41
0.31
1.27 BSC
0.75
0.58
0.40
Figure 35. 8-Lead Standard Small Outline Package, with Increased Creepage [SOIC_IC]
Wide Body
(RI-8-1)
Dimensions shown in millimeters
Rev. 0 | Page 21 of 22
ADuM7702
Data Sheet
ORDERING GUIDE
Package
Option
RW-16
RW-16
RW-16
RI-8-1
RI-8-1
RI-8-1
Model1, 2
ADuM7702BRWZ
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
16-Lead Standard Small Outline Package [SOIC_W]
16-Lead Standard Small Outline Package [SOIC_W]
16-Lead Standard Small Outline Package [SOIC_W]
8-Lead Standard Small Outline Package, with Increased Creepage [SOIC_IC]
8-Lead Standard Small Outline Package, with Increased Creepage [SOIC_IC]
8-Lead Standard Small Outline Package, with Increased Creepage [SOIC_IC]
Evaluation Board
ADuM7702BRWZ-RL
ADuM7702BRWZ-RL7
ADuM7702-8BRIZ
ADuM7702-8BRIZ-RL
ADuM7702-8BRIZ-RL7
EV-ADuM7702-8FMCZ
1 Z = RoHS-Compliant Part.
2 The EV-ADuM7702-8FMCZ is compatible with the EVAL-SDP-CH1Z (must be ordered separately) high speed controller board.
©2020 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D23727-7/20(0)
Rev. 0 | Page 22 of 22
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