ADV3219-EVALZ [ADI]
800 MHz, 2:1 Analog Multiplexers; 800兆赫， 2 ： 1模拟多路复用器
| 型号： | ADV3219-EVALZ |
| 厂家： | 
ADI |
| 描述： | 800 MHz, 2:1 Analog Multiplexers |
| 文件： | 总20页 (文件大小：1465K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
800 MHz, 2:1 Analog Multiplexers
ADV3219/ADV3220
FEATURES
FUNCTIONAL BLOCK DIAGRAM
ADV3219
(ADV3220)
Excellent ac performance
−3 dB bandwidth
800 MHz (200 mV p-p)
730 MHz (2 V p-p)
Slew rate: 2800 V/μs
Low power: 75 mW, VS = 5 V
Excellent video performance
>100 MHz, 0.1 dB gain flatness
0.02% differential gain/0.02° differential phase error
(RL = 150 Ω)
IN0 1
GND 2
IN1 3
V+ 4
8 SELECT
7 EN
G = +1
6 OUT
5 V–
(G = +2)
Figure 1.
Gain = +1 (ADV3219) or gain = +2 (ADV3220)
Low crosstalk of −82 dB @ 5 MHz and −60 dB @ 100 MHz
High impedance output disable allows connection of
multiple devices without loading the output bus
8-lead LFCSP
APPLICATIONS
Routing of high speed signals including
Video (NTSC, PAL, S, SECAM, YUV, and RGB)
Compressed video (MPEG, wavelet)
3-level digital video (HDB3)
Data communications
Telecommunications
GENERAL DESCRIPTION
The ADV3219/ADV3220 include an output buffer that can be
placed into a high impedance state to allow multiple outputs to
be connected together for cascading stages without the off channels
loading the output bus. The ADV3219 has a gain of +1, and the
ADV3220 has a gain of +2; they both operate on 5 V supplies
while consuming less than 7.5 mA of idle current.
The ADV3219 and ADV3220 are high speed, high slew rate,
buffered, 2:1 analog multiplexers. They offer a −3 dB signal
bandwidth greater than 800 MHz and channel switch times of
less than 20 ns with 1% settling. With −60 dB of crosstalk and
−82 dB isolation (at 100 MHz), the ADV3219 and ADV3220 are
useful in many high speed applications. The differential gain of
less than 0.02% and the differential phase of less than 0.02°,
together with 0.1 dB flatness beyond 100 MHz while driving a
75 Ω back terminated load, make the ADV3219 and ADV3220
ideal for all types of signal switching.
The ADV3219/ADV3220 are available in the 8-lead LFCSP
package over the extended industrial temperature range of
−40°C to +85°C.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks are theproperty of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2010 Analog Devices, Inc. All rights reserved.
ADV3219/ADV3220
TABLE OF CONTENTS
Features .............................................................................................. 1
Typical Performance Characteristics..............................................7
Circuit Diagrams ............................................................................ 15
Theory of Operation ...................................................................... 16
Applications Information.............................................................. 17
Circuit Layout............................................................................. 17
Termination................................................................................. 17
Capacitive Load .......................................................................... 17
Outline Dimensions....................................................................... 18
Ordering Guide .......................................................................... 18
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 5
Thermal Resistance ...................................................................... 5
Power Dissipation......................................................................... 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions............................. 6
REVISION HISTORY
4/10—Revision 0: Initial Version
Rev. 0 | Page 2 of 20
ADV3219/ADV3220
SPECIFICATIONS
VS = 5 V, TA = 25°C, RL = 150 Ω, CL = 4 pF, ADV3219 at G = +1, ADV3220 at G = +2, unless otherwise noted.
Table 1.
ADV3219
ADV3220
Min Typ
Parameter
Conditions
Min Typ
Max
Max Unit
DYNAMIC PERFORMANCE
−3 dB Bandwidth
200 mV p-p
2 V p-p
0.1 dB, 200 mV p-p
0.1 dB, 2 V p-p
2 V p-p
840
600
100
100
700
5
800
730
100
100
650
5
MHz
MHz
MHz
MHz
ps
Gain Flatness
Propagation Delay
Settling Time
Slew Rate
1%, 2 V step
2 V step, peak
ns
V/μs
2200
2800
NOISE/DISTORTION PERFORMANCE
Differential Gain Error
Differential Phase Error
Crosstalk
NTSC or PAL
NTSC or PAL
f = 100 MHz
f = 5 MHz
f = 100 MHz, one channel
f = 70 MHz, ADV3220, RL = 100 Ω
f = 70 MHz, ADV3220, RL = 100 Ω
f = 70 MHz, ADV3220, RL = 100 Ω
10 MHz to 100 MHz
0.02
0.02
−70
−90
−83
0.02
0.02
−60
−82
−82
47
34
20
17
%
Degrees
dB
dB
dB
dBm
dBm
dBm
nV/√Hz
Off Isolation, Input-Output
Input Second-Order Intercept
Input Third-Order Intercept
Output 1 dB Compression Point
Input Voltage Noise
16
DC PERFORMANCE
Gain Error
No load
RL = 150 Ω
Channel-to-channel, no load
1
1.1
1
1.1
%
%
%
0.75
1
0.75
1
Gain Matching
OUTPUT CHARACTERISTICS
Output Impedance
DC, enabled
Disabled
Disabled
Disabled
No load
0.02
0.04
Ω
1
1
MΩ
pF
μA
V
Output Disable Capacitance
Output Leakage Current
Output Voltage Range
1.0
2
3
3
1.2
2
3
2.9
2.8
2.9
2.75
Load
3
V
Short-circuit current
50
50
mA
INPUT CHARACTERISTICS
Input Offset Voltage
Input Offset Voltage Drift
Input Voltage Range
Worst case (all configurations)
5
10
21
12
5
10
1.5
1.5
0.6
10
6
21
12
mV
μV/°C
V
V
pF
No load
RL = 150 Ω
Any switch configuration
Output enabled
Output enabled
3
3
0.6
10
5
Input Capacitance
Input Resistance
Input Bias Current
1
1
MΩ
μA
SWITCHING CHARACTERISTICS
Enable On Time
Switching Time, 2 V Step
Switching Transient (Glitch)
15
20
70
15
20
100
ns
ns
mV p-p
50% SELECT to 1% settling
IN0 to IN1 switching
Rev. 0 | Page 3 of 20
ADV3219/ADV3220
ADV3219
ADV3220
Min Typ Max Unit
Parameter
Conditions
Min Typ
Max
POWER SUPPLIES
Supply Current
V+, output enabled, no load
V+, output disabled ( high)
EN
7
1.6
7
8
2.0
8
2.0
5.5
7.5
1.8
7.5
1.8
9
2.2
9
mA
mA
mA
mA
V
V−, output enabled, no load
V−, output disabled ( high)
EN
1.6
2.2
Supply Voltage Range
PSR
4.5
4.5
5.5
f = 100 kHz
f = 1 MHz
−72
−62
−69
−60
dB
dB
TEMPERATURE
Operating Temperature Range
Operating Junction-to-Ambient
Thermal Impedance, θJA
Still air
Still air
−40
+85
−40
+85
°C
°C/W
85
85
Table 2. Logic Levels
VIH
SELECT,
VIL
SELECT,
IIH
SELECT,
IIL
SELECT,
EN
EN
EN
2 μA maximum
EN
+2.0 V minimum
+0.8 V maximum
2 μA maximum
Rev. 0 | Page 4 of 20
ADV3219/ADV3220
ABSOLUTE MAXIMUM RATINGS
Table 3.
POWER DISSIPATION
The ADV3219/ADV3220 are operated with 5 V supplies and
can drive loads down to 150 ꢀ, resulting in a wide range of
possible power dissipations. For this reason, extra care must
be taken derating the operating conditions based on ambient
temperature.
Parameter
Rating
12 V
V− to V+
0 to V+
Supply Voltage (V+ − V−)
Analog Input Voltage
Digital Input Voltage
Output Voltage (Disabled Output)
Output Short-Circuit
Duration
Current
Temperature
Storage Temperature Range
Operating Temperature Range
Junction Temperature
(V+ − 1 V) to (V− + 1 V)
Packaged in an 8-lead LFCSP, the ADV3219 and ADV3220
junction-to-ambient thermal impedance (θJA) is 85°C/W. For long-
term reliability, the maximum allowed junction temperature of the
die, TJ, should not exceed 125°C. Temporarily exceeding this
limit can cause a shift in parametric performance due to a change
in stresses exerted on the die by the package. Figure 2 shows the
range of the allowed internal die power dissipations that meet
these conditions over the −40°C to +85°C ambient temperature
range. When using Figure 2, do not include the external load
power in the maximum power calculation, but do include the
load current through the die output transistors.
Momentary
50 mA
−65°C to +150°C
−40°C to +85°C
150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
1.5
T
= 125°C
J
1.2
0.9
0.6
0.3
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 4. Thermal Resistance
Package Type
8-Lead LFCSP
θJA
85
θJC
23
Unit
°C/W
15
25
35
45
55
65
75
85
AMBIENT TEMPERATURE (°C)
Figure 2. Maximum Die Power Dissipation vs. Ambient Temperature
ESD CAUTION
Rev. 0 | Page 5 of 20
ADV3219/ADV3220
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
IN0
GND
IN1
1
2
3
4
8
7
6
5
SELECT
ADV3219/
ADV3220
TOP VIEW
(Not to Scale)
EN
OUT
V–
V+
NOTES
1. CONNECT THE EXPOSED
PAD TO GROUND.
Figure 3. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
Mnemonic
Descriptions
1
IN0
Analog Input.
2
3
GND
IN1
Ground.
Analog Input.
4
5
6
7
V+
V−
OUT
EN
Positive Power Supply.
Negative Power Supply.
Analog Output.
Output Enable (Low True).
Logic Input for Analog Input Selection.
Exposed Pad. Connect the exposed pad to ground.
8
N/A1
SELECT
EP
1 N/A means not applicable.
Table 6. Truth Table
EN
SELECT
OUT
IN0
IN1
High-Z
High-Z
0
1
0
1
0
0
1
1
Rev. 0 | Page 6 of 20
ADV3219/ADV3220
TYPICAL PERFORMANCE CHARACTERISTICS
VS = 5 V, TA = 25°C, RL = 150 Ω, CL = 4 pF, ADV3219 at G = +1, ADV3220 at G = +2, unless otherwise noted.
4
3
4
3
2
2
1
1
4pF
0
0
0pF
2pF
4pF
–1
–2
–3
–4
–5
–6
–7
–8
–9
–10
–11
–12
–1
–2
–3
–4
–5
–6
–7
–8
–9
–10
–11
–12
2pF
0pF
10pF
10pF
1
10
100
FREQUENCY (MHz)
1k
10k
1
10
100
FREQUENCY (MHz)
1k
10k
10k
20
Figure 4. ADV3219 Small Signal Frequency Response with Capacitive Loads,
200 mV p-p Output
Figure 7. ADV3220 Small Signal Frequency Response with
Capacitive Loads, 200 mV p-p Output
4
3
2
4
3
2
1
2pF
4pF
1
0
–1
0
4pF
–1
–2
–2
–3
2pF
0pF
–3
–4
–4
–5
–5
–6
–6
–7
–7
–8
–8
0pF
–9
–9
–10
–11
–12
10pF
–10
–11
–12
10pF
1
10
100
FREQUENCY (MHz)
1k
10k
1
10
100
FREQUENCY (MHz)
1k
Figure 5. ADV3219 Large Signal Frequency Response with
Capacitive Loads, 2 V p-p Output
Figure 8. ADV3220 Large Signal Frequency Response with
Capacitive Loads, 2 V p-p Output
0.2
0.2
0pF
2pF
4pF
10pF
0pF
2pF
4pF
10pF
0.1
0
0.1
0
–0.1
–0.2
–0.1
–0.2
0
5
10
15
20
0
5
10
15
TIME (ns)
TIME (ns)
Figure 6. ADV3219 Small Signal Pulse Response vs. Capacitive Load,
200 mV p-p Output
Figure 9. ADV3220 Small Signal Pulse Response vs. Capacitive Load,
200 mV p-p Output
Rev. 0 | Page 7 of 20
ADV3219/ADV3220
2
2
1
0pF
2pF
4pF
10pF
0pF
2pF
4pF
10pF
1
0
0
–1
–2
–1
–2
0
5
10
15
20
0
5
10
15
20
TIME (ns)
TIME (ns)
Figure 10. ADV3219 Large Signal Pulse Response vs. Capacitive Load,
2 V p-p Output
Figure 13. ADV3220 Large Signal Pulse Response vs. Capacitive Load,
2 V p-p Output
3000
2000
1000
0
1.5
1.0
0.5
0
4000
3000
2000
1000
0
1.5
1.0
0.5
0
dv/dt
dv/dt
–1000
–2000
–3000
–4000
–1000
–2000
–3000
–0.5
–1.0
–1.5
–0.5
–1.0
–1.5
V
OUT
V
OUT
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
TIME (ns)
TIME (ns)
Figure 11. ADV3219 Large Signal Rising Slew Rate with 4 pF Load,
2 V p-p Output
Figure 14. ADV3220 Large Signal Rising Slew Rate with 4 pF Load,
2 V p-p Output
3000
1.5
1.0
0.5
0
4000
1.5
1.0
0.5
0
V
3000
2000
1000
0
OUT
2000
1000
0
V
OUT
dv/dt
dv/dt
–1000
–2000
–3000
–4000
–1000
–2000
–3000
–0.5
–1.0
–1.5
–0.5
–1.0
–1.5
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
TIME (ns)
TIME (ns)
Figure 12. ADV3219 Large Signal Falling Slew Rate with 4 pF Load,
2 V p-p Output
Figure 15. ADV3220 Large Signal Falling Slew Rate with 4 pF Load,
2 V p-p Output
Rev. 0 | Page 8 of 20
ADV3219/ADV3220
1.5
1.0
2.1
1.9
1.7
1.5
1.3
1.1
0.9
0.7
1.5
1.0
2.1
1.9
1.7
1.5
1.3
1.1
0.9
0.7
FALLING EDGE
FALLING EDGE
0.5
0.5
SELECT
SELECT
0
0
–0.5
–1.0
–1.5
–0.5
–1.0
–1.5
RISING EDGE
RISING EDGE
0
0
0
10
20
30
0
0
0
10
20
30
TIME (ns)
TIME (ns)
Figure 16. ADV3219 Switching Time
Figure 19. ADV3220 Switching Time
0.5
0.4
6
0.5
0.4
6
5
5
EN
EN
0.3
0.3
4
4
0.2
0.2
0.1
0.1
3
3
OUTPUT
OUTPUT
0
0
2
2
–0.1
–0.2
–0.3
–0.4
–0.5
–0.1
–0.2
–0.3
–0.4
–0.5
1
1
0
0
–1
50
–1
50
10
20
30
40
10
20
30
40
TIME (ns)
TIME (ns)
Figure 17. ADV3219 Enable Glitch
Figure 20. ADV3220 Enable Glitch
3
2
2.1
1.9
1.7
1.5
1.3
1.1
0.9
0.7
3
2
2.1
1.9
1.7
1.5
1.3
1.1
0.9
0.7
EN
EN
INPUT +1V
INPUT +0.5V
1
1
0
0
INPUT –1V
INPUT –0.5V
–1
–2
–3
–1
–2
–3
10
20
30
10
20
30
TIME (ns)
TIME (ns)
Figure 18. ADV3219 Enable On Timing
Figure 21. ADV3220 Enable On Timing
Rev. 0 | Page 9 of 20
ADV3219/ADV3220
1.5
2.1
1.9
1.7
1.5
1.3
1.1
0.9
0.7
1.5
1.0
2.1
1.9
1.7
1.5
1.3
1.1
0.9
0.7
INPUT +1V
1.0
INPUT +0.5V
0.5
0.5
EN
EN
0
0
–0.5
–0.5
–1.0
–1.5
INPUT –1V
–1.0
INPUT –0.5V
–1.5
0
0
0
10
20
30
40
0
0
0
10
20
30
40
TIME (ns)
TIME (ns)
Figure 22. ADV3219 Disable Timing
Figure 25. ADV3220 Disable Timing
100
80
6
100
80
6
5
5
60
60
4
4
40
40
20
20
3
3
OUTPUT
SELECT
OUTPUT
SELECT
0
0
2
2
–20
–40
–60
–80
–100
–20
–40
–60
–80
–100
1
1
0
0
–1
50
–1
50
10
20
30
40
10
20
30
40
TIME (ns)
TIME (ns)
Figure 23. ADV3219 Switching Glitch Rising Edge
Figure 26. ADV3220 Switching Glitch Rising Edge
100
80
6
100
80
6
SELECT
SELECT
5
5
60
60
4
4
40
40
20
20
3
3
OUTPUT
OUTPUT
0
0
2
2
–20
–40
–60
–80
–100
–20
–40
–60
–80
–100
1
1
0
0
–1
50
–1
50
10
20
30
40
10
20
30
40
TIME (ns)
TIME (ns)
Figure 24. ADV3219 Switching Glitch Falling Edge
Figure 27. ADV3220 Switching Glitch Falling Edge
Rev. 0 | Page 10 of 20
ADV3219/ADV3220
5
4
1.25
5
4
1.25
0.75
0.25
INPUT
INPUT
3
0.75
3
2
2
1
0.25
1
ERROR
ERROR
0
0
–1
–2
–3
–4
–5
–0.25
–0.75
–1.25
–1
–2
–3
–4
–5
–0.25
–0.75
–1.25
OUTPUT
OUTPUT
3
0
1
2
3
4
5
6
7
8
9
10
0
1
2
4
5
6
7
8
9
10
TIME (ns)
TIME (ns)
Figure 28. ADV3219 Settling Time 2 V Output Step
Figure 31. ADV3220 Settling Time 2 V Output Step
10
0
10
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–10
–20
–30
–40
–50
–60
–70
–80
–90
PSR (V–)
PSR (V–)
PSR (V+)
PSR (V+)
0.1
1
10
100
1k
10k
0.1
1
10
100
1k
10k
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 29. ADV3219 PSR
Figure 32. ADV3220 PSR
200
180
160
140
120
100
80
200
180
160
140
120
100
80
60
60
40
40
20
20
0
0
1k
10k
100k
1M
10M
100M
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 30. ADV3219 Noise vs. Frequency
Figure 33. ADV3220 Noise vs. Frequency
Rev. 0 | Page 11 of 20
ADV3219/ADV3220
–20
–20
–30
–30
–40
–40
–50
–50
–60
–60
–70
–70
–80
–80
–90
–90
–100
–110
–100
–110
1
10
100
1k
10k
1
10
100
1k
10k
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 34. ADV3219 Crosstalk vs. Frequency
Figure 37. ADV3220 Crosstalk vs. Frequency
–20
–30
–20
–30
–40
–40
–50
–50
–60
–60
–70
–70
–80
–80
–90
–90
–100
–110
–100
–110
1
10
100
1k
10k
1
10
100
1k
10k
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 35. ADV3219 Off Isolation vs. Frequency
Figure 38. ADV3220 Off Isolation vs. Frequency
1M
1M
100k
10k
1k
100k
10k
1k
100
10
100
10
1
1
10
100
1k
1
10
100
1k
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 36. ADV3219 Disabled Output Impedance vs. Frequency
Figure 39. ADV3219/ADV3220 Input Impedance vs. Frequency
Rev. 0 | Page 12 of 20
ADV3219/ADV3220
10k
1k
10k
1k
100
10
100
10
1
1
0.1
0.01
0.1
0.01
1
10
100
1k
1
10
100
1k
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 40. ADV3219 Enabled Output Impedance vs. Frequency
Figure 43. ADV3220 Enabled Output Impedance vs. Frequency
–10
–20
–30
–40
–50
–60
–70
5
4
5
INPUT
4
3
3
2
2
OUTPUT
1
1
0
0
–1
–2
–3
–4
–5
–1
–2
–3
–4
–5
1
10
100
1k
0
20
40
60
80
100
FREQUENCY (MHz)
TIME (ns)
Figure 41. ADV3219/ADV3220, S11 (Measured on Evaluation Board)
Figure 44. ADV3219 Overdrive Recovery
1M
100k
10k
1k
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
100
10
HD2 0dBm
HD3 0dBm
HD2 10dBm
HD3 10dBm
1
1
10
100
1k
10
100
1k
FREQUENCY (MHz)
INPUT FREQUENCY (MHz)
Figure 42. ADV3220 Disabled Output Impedance vs. Frequency
Figure 45. ADV3220 Harmonic Distortion, RL = 100 Ω, CL = 4 pF
Rev. 0 | Page 13 of 20
ADV3219/ADV3220
40
35
30
25
20
15
10
5
60
50
40
30
20
10
0
0
10
100
INPUT FREQUENCY (MHz)
1k
10
100
1k
INPUT FREQUENCY (MHz)
Figure 46. ADV3220 Input Third-Order Intercept, RL = 100 Ω,
CL = 4 pF, 0 dBm Input
Figure 48. ADV3220 Input Second-Order Intercept, RL = 100 Ω,
CL = 4 pF, 0 dBm Input
5
4
2.5
24
22
20
18
16
14
12
10
8
INPUT
2.0
3
1.5
2
1.0
OUTPUT
1
0.5
0
0
–1
–2
–3
–4
–5
–0.5
–1.0
–1.5
–2.0
–2.5
6
4
2
0
0
20
40
60
80
100
10
100
1k
TIME (ns)
INPUT FREQUENCY (MHz)
Figure 47. ADV3220 Overdrive Recovery
Figure 49. ADV3220 Output P1dB Gain Compression, RL = 100 Ω, CL = 4 pF
Rev. 0 | Page 14 of 20
ADV3219/ADV3220
CIRCUIT DIAGRAMS
V+
IN
OUT
0.6pF
1.0pF (ADV3219)
1.2pF (ADV3220)
V–
Figure 50. ADV3219/ADV3220 Analog Input
Figure 53. ADV3219/ADV3220 Disabled Output
V+
OUT
1kΩ
SELECT, EN
V–
Figure 54. ADV3219/ADV3220 Logic Input
Figure 51. ADV3219 Enabled Analog Output
V+
OUT
SELECT,
EN
1kΩ
INx, OUT
1kΩ
GND
V–
GND
Figure 55. ADV3219/ADV3220 ESD Schematic
Figure 52. ADV3220 Enabled Analog Output
Rev. 0 | Page 15 of 20
ADV3219/ADV3220
THEORY OF OPERATION
The ADV3219/ADV3220 are dual-supply, high performance 2:1
analog multiplexers, optimized for switching between multiple
video sources. High peak slew rates enable wide bandwidth oper-
ation for large input signals. Internal compensation provides for
high phase margin, allowing low overshoot and fast settling for
pulsed inputs. Low enabled and disabled power consumption make
the ADV3219 and ADV3220 ideal for constructing larger arrays.
When not in use, place the OUT pin in a low power, high
EN
provides a wideband high impedance on the OUT pin that is
useful when paralleling multiple ADV3219/ADV3220 devices
in a system to create larger switching arrays.
impedance disabled mode via the
logic input. This mode
Switching between the inputs is controlled with the SELECT
logic input, with IN0 selected when the SELECT line is a logical
low and IN1 selected when the select line is a logical high. When
The multiplexer is organized as two input transconductance
stages tied in parallel with a single output transimpedance stage
followed by a unity-gain buffer. Internal voltage feedback sets
the gain. The ADV3219 is configured as a gain of 1, whereas the
ADV3220 uses a resistive feedback network and ground buffer to
realize gain-of-2 operation (see Figure 56). The ground reference
for the ADV3220 is taken from the exposed pad of the package.
To minimize spurious signals on the output, tie the exposed pad
to a low inductance, quiet ground plane.
EN
is a logical low, the output is enabled and connected to one
of the two inputs depending on the state of the SELECT pin.
EN
When
is a logical high, the output is placed in a high
impedance mode.
When not in use, the output can be placed in a low power, high
EN
impedance disabled mode via the
logic input.
V+
IN0
×1
OUT
V–
V+
IN1
1kΩ
V–
V+
1kΩ
GND
V–
Figure 56. Conceptual Diagram of ADV3220
Rev. 0 | Page 16 of 20
ADV3219/ADV3220
APPLICATIONS INFORMATION
The ADV3219 and ADV3220 are very high speed muxes that
can be used to switch video or RF signals. The low output imped-
ance of the ADV3219/ADV3220 allows the output environment
to be optimized for use in 75 Ω or 50 Ω systems by choosing the
appropriate series termination resistor. For composite video
applications, the ADV3220 (gain of +2) is typically used to
provide compensation for the loss of the output termination.
TERMINATION
For a controlled impedance situation, termination resistors are
required at the inputs and output of the device. The input ter-
mination should be a shunt resistor to ground with a value
matching the characteristic impedance of the input trace. To
reduce reflections, place the input termination resistor as close
to the device input pin as possible. To minimize the input-to-
input crosstalk, it is important to use a low inductance shield
between input traces to isolate each input. Consideration of
ground current paths must be taken to minimize loop currents
in the shields to prevent them from providing a coupling medium
for crosstalk.
CIRCUIT LAYOUT
Use of proper high speed design techniques is important to
ensure optimum performance. Use a low inductance ground
plane for power supply bypassing and to provide high quality
return paths for the input and output signals. For best performance,
it is recommended that power supplies be bypassed with 0.1 μF
ceramic capacitors placed as close to the body of the device as
possible. To provide stored energy for lower frequency, high
current output driving, place 10 μF tantalum capacitors farther
from the device.
For proper matching, the output series termination resistor
should be the same value as the characteristic impedance of the
output trace and placed as close to the output of the device as
possible. This placement reduces the high frequency effect of
series parasitic inductance, which can affect gain flatness and
−3 dB bandwidth.
The input and output signal paths should be stripline or micro-
strip controlled impedance. Video systems typically use a 75 Ω
characteristic impedance, whereas RF systems typically use 50 Ω.
Various calculators are available to calculate the trace geometry
that is required to produce the proper characteristic impedance.
CAPACITIVE LOAD
A high frequency output generally has difficulty when driving a
capacitive load. The usual response is some peaking in the fre-
quency domain or some overshoot in the time domain. If these
effects become too large, oscillation can result.
The response of the device under various capacitive loads is
shown in Figure 4 to Figure 10 and in Figure 13. If a condition
arises wherein excessive load capacitance is encountered and
the overshoot is too great or the part oscillates, use a small series
resistor of a few tens of ohms to improve the performance.
Rev. 0 | Page 17 of 20
ADV3219/ADV3220
OUTLINE DIMENSIONS
2.54
2.44
2.34
3.10
3.00 SQ
2.90
0.50 BSC
8
5
PIN 1 INDEX
EXPOSED
PAD
1.80
1.70
1.60
AREA
0.50
0.40
0.30
4
1
PIN 1
INDICATOR
(R 0.15)
TOP VIEW
BOTTOM VIEW
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.80
0.75
0.70
0.05 MAX
0.02 NOM
COPLANARITY
0.08
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.30
0.25
0.20
0.203 REF
COMPLIANT TO JEDEC STANDARDS MO-229-WEED
Figure 57. 8-Lead Lead Frame Chip Scale Package [LFCSP_WD]
3 mm × 3 mm Body, Very Very Thin, Dual Lead
(CP-8-11)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
ADV3219ACPZ
ADV3219ACPZ-RL
ADV3219ACPZ-R7
ADV3220ACPZ
ADV3220ACPZ-RL
ADV3220ACPZ-R7
ADV3219-EVALZ
ADV3220-EVALZ
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
8-Lead LFCSP_WD
Package Option
CP-8-11
CP-8-11
Branding Code
F0H
F0H
F0H
F0J
F0J
F0J
8-Lead LFCSP_WD, 13”Tape and Reel
8-Lead LFCSP_WD, 7”Tape and Reel
8-Lead LFCSP_WD
8-Lead LFCSP_WD, 13”Tape and Reel
8-Lead LFCSP_WD, 7”Tape and Reel
Evaluation Board
CP-8-11
CP-8-11
CP-8-11
CP-8-11
Evaluation Board
1 Z = RoHS Compliant Part.
Rev. 0 | Page 18 of 20
ADV3219/ADV3220
NOTES
Rev. 0 | Page 19 of 20
ADV3219/ADV3220
NOTES
©2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D08649-0-4/10(0)
Rev. 0 | Page 20 of 20
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