ADV601LCJSTZRL_技术文档

Ultralow Cost

Video Codec

a

ADV601LC

GENERAL D ESCRIP TIO N

FEATURES

T he ADV601LC is an ultralow cost, single chip, dedicated

function, all digital CMOS VLSI device capable of supporting

visually loss-less to 350:1 real-time compression and decom-

pression of CCIR-601 digital video at very high image quality

levels. T he chip integrates glueless video and host interfaces

with on-chip SRAM to permit low part count, system level

implementations suitable for a broad range of applications. T he

ADV601LC is 100% bitstream compatible with the ADV601.

100% Bitstream Com patible w ith the ADV601

Precise Com pressed Bit Rate Control

Field Independent Com pression

8-Bit Video Interface Supports CCIR-656 and Multi-

plexed Philips Form ats

General Purpose 16- or 32-Bit Host Interface w ith

512 Deep 32-Bit FIFO

PERFORMANCE

T he ADV601LC is a video encoder/decoder optimized for real-

time compression and decompression of interlaced digital video.

All features of the ADV601LC are designed to yield high perfor-

mance at a breakthrough systems-level cost. Additionally, the

unique sub-band coding architecture of the ADV601LC offers

you many application-specific advantages. A review of the Gen-

eral T heory of Operation and Applying the ADV601LC sections

will help you get the most use out of the ADV601LC in any

given application.

Real-Tim e Com pression or Decom pression of CCIR-601

to Video:

720

؋

288 @ 50 Fields/ Sec — PAL

720

؋

243 @ 60 Fields/ Sec — NTSC

Com pression Ratios from Visually Loss-Less to 350:1

Visually Loss-Less Com pression At 4:1 on Natural

Im ages (Typical)

APPLICATIONS

PC Video Editing

T he ADV601LC accepts component digital video through the

Video Interface and outputs a compressed bit stream though the

Host Interface in Encode Mode. While in Decode Mode, the

ADV601LC accepts a compressed bit stream through the Host

Interface and outputs component digital video through the

Video Interface. T he host accesses all of the ADV601LC’s con-

trol and status registers using the Host Interface. Figure 1 sum-

marizes the basic function of the part.

Rem ote CCTV Surveillance

Digital Cam corders

Digital Video Tape

Wireless Video System s

TV Instant Replay

(continued on page 2)

FUNCTIO NAL BLO CK D IAGRAM

256K

؋

16-BIT DRAM

(FIELD STORE)

ADV601LC

ULTRALOW COST,

VIDEO CODEC

DRAM

MANAGER

WAVELET

FILTERS,

DECIMATOR, &

INTERPOLATOR

RUN

LENGTH

CODER

HOST

I/O PORT

& FIFO

DIGITAL

COMPONENT

VIDEO I/O

DIGITAL

VIDEO I/O

PORT

HUFFMAN

CODER

ADAPTIVE

QUANTIZER

HOST

BIN WIDTH CONTROL

SUB-BAND STATISTICS

ON-CHIP

TRANSFORM

BUFFER

REV. 0

Inform ation furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assum ed by Analog Devices for its

use, nor for any infringem ents of patents or other rights of third parties

which m ay result from its use. No license is granted by im plication or

otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.

Tel: 781/ 329-4700

Fax: 781/ 326-8703

World Wide Web Site: http:/ / w w w .analog.com

ADV601LC

TABLE O F CO NTENTS

GENERAL D ESCRIP TIO N (Continued from page 1)

T his data sheet gives an overview of the ADV601LC functional-

ity and provides details on designing the part into a system. T he

text of the data sheet is written for an audience with a general

knowledge of designing digital video systems. Where appropri-

ate, additional sources of reference material are noted through-

out the data sheet.

VIDEO INTERFACE

HOST INTERFACE

COMPRESSED

VIDEO OUT

(ENCODE)

DIGITAL VIDEO IN

(ENCODE)

ADV601LC

STATUS AND CONTROL

ULTRALOW

COST,

DIGITAL VIDEO OUT

(DECODE)

VIDEO CODEC

COMPRESSED VIDEO IN

(DECODE)

GENERAL DESCRIPT ION . . . . . . . . . . . . . . . . . . . . . . . . . 1

INT ERNAL ARCHIT ECT URE . . . . . . . . . . . . . . . . . . . . . 3

GENERAL T HEORY OF OPERAT ION . . . . . . . . . . . . . . . 3

References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

T HE WAVELET KERNEL . . . . . . . . . . . . . . . . . . . . . . . . . 4

T HE PROGRAMMABLE QUANT IZER . . . . . . . . . . . . . . . 7

THE RUN LENGTH CODER AND HUFFMAN CODER . . 8

Encoding vs. Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

PROGRAMMER’S MODEL . . . . . . . . . . . . . . . . . . . . . . . . 8

ADV601LC REGIST ER DESCRIPT IONS . . . . . . . . . . . . 10

PIN FUNCT ION DESCRIPT IONS . . . . . . . . . . . . . . . . . 16

Video Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Host Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

DRAM Manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Compressed Data-Stream Definition . . . . . . . . . . . . . . . . 22

APPLYING T HE ADV601LC . . . . . . . . . . . . . . . . . . . . . . 28

Using the ADV601LC in Computer Applications . . . . . . 28

Using the ADV601LC in Stand-Alone Applications . . . . 29

Connecting the ADV601LC to Popular Video Decoders

Figure 1. Functional Block Diagram

T he ADV601LC adheres to international standard CCIR-601

for studio quality digital video. T he codec also supports a range

of field sizes and rates providing high performance in computer,

PAL, NT SC, or still image environments. T he ADV601LC is

designed only for real-time interlaced video, full frames of video

are formed and processed as two independent fields of data.

T he ADV601LC supports the field rates and sizes in T able I.

Note that the maximum active field size is 768 by 288. T he

maximum pixel rate is 14.75 MHz.

T he ADV601LC has a generic 16-/32-bit host interface, which

includes a 512-position, 32-bit wide FIFO for compressed video.

With additional external hardware, the ADV601LC’s host inter-

face is suitable (when interfaced to other devices) for moving com-

pressed video over PCI, ISA, SCSI, SONET, 10 Base T, ARCnet,

HDSL, ADSL, and a broad range of digital interfaces. For a full

description of the Host Interface, see the Host Interface section.

and Encoders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

GET T ING T HE MOST OUT OF ADV601LC . . . . . . . . . 30

ADV601LC SPECIFICAT IONS . . . . . . . . . . . . . . . . . . . . 31

T EST CONDIT IONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

T IMING PARAMET ERS . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Clock Signal T iming . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

CCIR-656 Video Format T iming . . . . . . . . . . . . . . . . . . . 33

Multiplexed Philips Video T iming . . . . . . . . . . . . . . . . . . 35

Host Interface (Indirect Address, Indirect Register Data,

and Interrupt Mask/Status) Register T iming . . . . . . . . 38

Host Interface (Compressed Data) Register T iming . . . . 40

PINOUT S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

PIN CONFIGURAT ION . . . . . . . . . . . . . . . . . . . . . . . . . . 43

OUT LINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . 44

ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

The compressed data rate is determined by the input data rate

and the selected compression ratio. The ADV601LC can achieve a

near constant compressed bit rate by using the current field

statistics in the off-chip bin width calculator on the external

DSP or Host. T he process of calculating bin widths on a DSP

or Host can be “adaptive,” optimizing the compressed bit rate

in real time. T his feature provides a near constant bit rate out of

the host interface in spite of scene changes or other types of

source material changes that would otherwise create bit rate

burst conditions. For more information on the quantizer, see

the Programmable Quantizer section.

T he ADV601LC typically yields visually loss-less compression

on natural images at a 4:1 compression ratio. Desired image

quality levels can vary widely in different applications, so it is

advisable to evaluate image quality of known source material at

different compression ratios to find the best compression range

for the application. T he sub-band coding architecture of the

ADV601LC provides a number of options to stretch compres-

sion performance. T hese options are outlined on in the Apply-

ing the ADV601LC section.

Table I. AD V601LC Field Rates and Sizes

Active

Total

Standard

Nam e

Region

H orizontal

Region

H orizontal

Region

Vertical

Field Rate

(H z)

P ixel Rate

(MH z)²

Vertical¹

CCIR-601/525

CCIR-601/625

720

243

288

858

864

262.5

312.5

59.94

50.00

13.50

NOT ES

¹T he maximum active field size is 720 by 288.

²T he maximum pixel rate is 13.5 MHz.

REV. 0

–2–

ADV601LC

INTERNAL ARCH ITECTURE

H uffm an Coder

T he ADV601LC is composed of eight blocks. T hree of these

blocks are interface blocks and five are processing blocks. T he

interface blocks are the Digital Video I/O Port, the Host I/O

Port, and the external DRAM manager. T he processing blocks

are the Wavelet Kernel, the On-Chip T ransform Buffer, the

Programmable Quantizer, the Run Length Coder, and the

H uffman Coder.

Performs Huffman coder and decoder functions on quantized

run-length coded coefficient values. T he Huffman coder/de-

coder uses three ROM-coded Huffman tables that provide ex-

cellent performance for wavelet transformed video.

GENERAL TH EO RY O F O P ERATIO N

T he ADV601LC processor’s compression algorithm is based on

the bi-orthogonal (7, 9) wavelet transform, and implements field

independent sub-band coding. Sub-band coders transform two-

dimensional spatial video data into spatial frequency filtered

sub-bands. T he quantization and entropy encoding processes

provide the ADV601LC’s data compression.

D igital Video I/O P or t

Provides a real-time uncompressed video interface to support a

broad range of component digital video formats, including “D1.”

H ost I/O P or t and FIFO

Carries control, status, and compressed video to and from the

host processor. A 512 position by 32-bit FIFO buffers the com-

pressed video stream between the host and the Huffman Coder.

T he wavelet theory, on which the ADV601LC is based, is a new

mathematical apparatus first explicitly introduced by Morlet and

Grossman in their works on geophysics during the mid 80s.

T his theory became very popular in theoretical physics and

applied math. T he late 80s and 90s have seen a dramatic growth

in wavelet applications such as signal and image processing. For

more on wavelet theory by Morlet and Grossman, see Decompo-

sition of Hardy Functions into Square Integrable Wavelets of Con-

stant Shape (journal citation listed in References section).

D RAM Manager

Performs all tasks related to writing, reading, and refreshing the

external DRAM. T he external host buffer DRAM is used for

reordering and buffering quantizer input and output values.

Wavelet Ker nel (Filter s, D ecim ator , and Inter polator )

Gathers statistics on a per field basis and includes a block of

filters, interpolators, and decimators. T he kernel calculates

forward and backward bi-orthogonal, two-dimensional, sepa-

rable wavelet transforms on horizontal scanned video data. T his

block uses the internal transform buffer when performing wave-

let transforms calculated on an entire image’s data and so

eliminates any need for extremely fast external memories in

an ADV601LC-based design.

ENCODE

PATH

RUN LENGTH

WAVELET

KERNEL

FILTER BANK

ADAPTIVE

QUANTIZER

COMPRESSED

DATA

CODER &

HUFFMAN

CODER

DECODE

PATH

Figure 2. Encode and Decode Paths

Refer ences

O n-Chip Tr ansfor m Buffer

For more information on the terms, techniques and underlying

principles referred to in this data sheet, you may find the follow-

ing reference texts useful. A reference text for general digital

video principles is:

Provides an internal set of SRAM for use by the wavelet trans-

form kernel. Its function is to provide enough delay line storage

to support calculation of separable two dimensional wavelet

transforms for horizontally scanned images.

Jack, K., Video Demystified: A Handbook for the Digital Engineer

(High T ext Publications, 1993) ISBN 1-878707-09-4

P r ogr am m able Q uantizer

Quantizes wavelet coefficients. Quantize controls are calculated

by the external DSP or host processor during encode operations

and de-quantize controls are extracted from the compressed bit

stream during decode. Each quantizer Bin Width is computed

by the BW calculator software to maintain a constant com-

pressed bit rate or constant quality bit rate. A Bin Width is a per

block parameter the quantizer uses when determining the num-

ber of bits to allocate to each block (sub-band).

T hree reference texts for wavelet transform background infor-

mation are:

Vetterli, M., Kovacevic, J., Wavelets And Sub-band Coding

(Prentice Hall, 1995) ISBN 0-13-097080-8

Benedetto, J., Frazier, M., Wavelets: Mathematics And Applica-

tions (CRC Press, 1994) ISBN 0-8493-8271-8

Grossman, A., Morlet, J., Decomposition of Hardy Functions into

Square Integrable Wavelets of Constant Shape, Siam. J. Math.

Anal., Vol. 15, No. 4, pp 723-736, 1984

Run Length Coder

Performs run length coding on zero data and models nonzero

data, encoding or decoding for more efficient Huffman coding.

T his data coding is optimized across the sub-bands and varies

depending on the block being coded.

REV. 0

–3–

ADV601LC

TH E WAVELET KERNEL

Understanding the structure and function of the wavelet filters

and resultant product is the key to obtaining the highest perfor-

mance from the ADV601LC. Consider the following points:

T his block contains a set of filters and decimators that work on

the image in both horizontal and vertical directions. Figure 6

illustrates the filter tree structure. T he filters apply carefully

chosen wavelet basis functions that better correlate to the broad-

band nature of images than the sinusoidal waves used in Dis-

crete Cosine T ransform (DCT ) compression schemes (JPEG,

MPEG, and H261).

• T he data in all blocks (except N) for all components are high

pass filtered. T herefore, the mean pixel value in those blocks

is typically zero and a histogram of the pixel values in these

blocks will contain a single “hump” (Laplacian distribution).

• T he data in most blocks is more likely to contain zeros or

An advantage of wavelet-based compression is that the entire

image can be filtered without being broken into sub-blocks as

required in DCT compression schemes. T his full image filtering

eliminates the block artifacts seen in DCT compression and

offers more graceful image degradation at high compression

ratios. T he availability of full image sub-band data also makes

image processing, scaling, and a number of other system fea-

tures possible with little or no computational overhead.

strings of zeros than unfiltered image data.

• T he human visual system is less sensitive to higher frequency

blocks than low ones.

• Attenuation of the selected blocks in luminance or color com-

ponents results in control over sharpness, brightness, contrast

and saturation.

• High quality filtered/decimated images can be extracted/created

T he resultant filtered image is made up of components of the

original image as is shown in Figure 3 (a modified Mallat T ree).

Note that Figure 3 shows how a component of video would be

filtered, but in multiple component video luminance and color

components are filtered separately. In Figure 4 and Figure 5 an

actual image and the Mallat T ree (luminance only) equivalent is

shown. It is important to note that while the image has been

filtered or transformed into the frequency domain, no compres-

sion has occurred. With the image in its filtered state, it is now

ready for processing in the second block, the quantizer.

without computational overhead.

T hrough leverage of these key points, the ADV601LC not

only compresses video, but offers a host of application features.

Please see the Applying the ADV601LC section for details on

getting the most out of the ADV601LC’s sub-band coding

architecture in different applications.

N

L

I

M

K

F

E

H

J

C

G

A

D

B

BLOCK A IS HIGH PASS IN X AND DECIMATED BY TWO.

BLOCK H IS HIGH PASS IN X, HIGH PASS IN Y, AND DECIMATED BY 128.

BLOCK I IS HIGH PASS IN X, LOW PASS IN Y, AND DECIMATED BY 128.

BLOCK B IS HIGH PASS IN X, HIGH PASS IN Y, AND DECIMATED BY EIGHT. BLOCK J IS LOW PASS IN X, HIGH PASS IN Y, AND DECIMATED BY 128.

BLOCK C IS HIGH PASS IN X, LOW PASS IN Y, AND DECIMATED BY EIGHT.

BLOCK D IS LOW PASS IN X, HIGH PASS IN Y, AND DECIMATED BY EIGHT.

BLOCK K IS HIGH PASS IN X, HIGH PASS IN Y, AND DECIMATED BY 512.

BLOCK E IS HIGH PASS IN X, HIGH PASS IN Y, AND DECIMATED BY 32.

BLOCK F IS HIGH PASS IN X, LOW PASS IN Y, AND DECIMATED BY 32.

BLOCK G IS LOW PASS IN X, HIGH PASS IN Y, AND DECIMATED BY 32.

BLOCK L IS HIGH PASS IN X, LOW PASS IN Y, AND DECIMATED BY 512.

BLOCK M IS LOW PASS IN X, HIGH PASS IN Y, AND DECIMATED BY 512.

BLOCK N IS LOW PASS IN X, LOW PASS IN Y, AND DECIMATED BY 512.

Figure 3. Modified Mallat Diagram (Block Letters Correspond to Those in Filter Tree)

REV. 0

–4–

ADV601LC

Figure 4. Unfiltered Original Im age (Analog Devices Corporate Offices, Norwood, Massachusetts)

Figure 5. Modified Mallat Diagram of Im age

REV. 0

–5–

ADV601LC

X

Y

2

INDICATES

INDICATES DECIMATE BY TWO IN X

INDICATES DECIMATE BY TWO IN Y

LUMINANCE AND

COLOR COMPONENTS

(EACH SEPARATELY)

CORRESPONDING BLOCK

LETTER ON MALLAT

DIAGRAM

BLOCK

#

HIGH

PASS IN

X

LOW

PASS IN

X

STAGE 1

STAGE 2

X

2

X 2

HIGH

PASS IN

X

LOW

PASS IN

X

BLOCK

A

X

2

X 2

HIGH

PASS IN

Y

LOW

PASS IN

Y

HIGH

PASS IN

Y

LOW

PASS IN

Y

2

Y

HIGH

PASS IN

X

LOW

PASS IN

X

BLOCK

B

BLOCK

C

BLOCK

D

X

2

X 2

STAGE 3

STAGE 4

STAGE 5

HIGH

PASS IN

Y

LOW

PASS IN

Y

HIGH

PASS IN

Y

LOW

PASS IN

Y

2

Y

HIGH

PASS IN

X

LOW

PASS IN

X

BLOCK

E

BLOCK

F

BLOCK

G

X

2

X 2

HIGH

PASS IN

Y

LOW

PASS IN

Y

HIGH

PASS IN

Y

LOW

PASS IN

Y

2

Y

HIGH

PASS IN

X

LOW

PASS IN

X

BLOCK

H

BLOCK

I

BLOCK

J

X

2

X 2

HIGH

PASS IN

Y

LOW

PASS IN

Y

HIGH

PASS IN

Y

LOW

PASS IN

Y

2

Y

BLOCK

K

BLOCK

L

BLOCK

M

BLOCK

N

Figure 6. Wavelet Filter Tree Structure

REV. 0

–6–

ADV601LC

TH E P RO GRAMMABLE Q UANTIZER

QUANTIZER - ENCODE MODE

T his block quantizes the filtered image based on the response

profile of the human visual system. In general, the human eye

cannot resolve high frequencies in images to the same level of

accuracy as lower frequencies. T hrough intelligent “quantiza-

tion” of information contained within the filtered image, the

ADV601LC achieves compression without compromising the

visual quality of the image. Figure 7 shows the encode and de-

code data formats used by the quantizer.

9.7

WAVELET

DATA

15.17 DATA

15.0 BIN

NUMBER

SIGNED

TRNC

UNSIGNED

0.5

6.10 1/BW

1/BW

QUANTIZER - DECODE MODE

23.8 DEQUANTIZED

WAVELET DATA

SIGNED

Figure 8 shows how a typical quantization pattern applies over

Mallat block data. T he high frequency blocks receive much

larger quantization (appear darker) than the low frequency

blocks (appear lighter). Looking at this figure, one sees some key

point concerning quantization: (1) quantization relates directly

to frequency in Mallat block data and (2) levels of quantization

range widely from high to low frequency block. (Note that the

fill is based on a log formula.) T he relation between actual

ADV601LC bin width factors and the Mallat block fill pattern

in Figure 8 appears in T able II.

9.7

WAVELET

DATA

15.0 BIN

NUMBER

SIGNED

UNSIGNED

SAT

8.8 BW

BW

Figure 7. Program m able Quantizer Data Flow

Y COMPONENT

39 33

24

21

36

30

15

12

27

6

18

0

9

3

40

34

37 31

Cb COMPONENT

25

22

16

13

28

7

19

1

10

4

41

35

38 32

Cr COMPONENT

26

23

17

14

29

8

20

2

11

5

QUANTIZATION OF MALLAT BLOCKS

HIGH

LOW

Figure 8. Typical Quantization of Mallat Data Blocks (Graphed)

–7–

REV. 0

ADV601LC

Table II. AD V601LC Typical Quantization of Mallat D ata

Block D ata¹

TH E RUN LENGTH CO D ER AND H UFFMAN CO D ER

T his block contains two types of entropy coders that achieve

mathematically loss-less compression: run length and Huffman.

T he run-length coder looks for long strings of zeros and replaces

it with short hand symbols. T able III illustrates an example of

how compression is possible.

Mallat

Blocks

Bin Width

Factors

Reciprocal Bin

Width Factors

39

40

41

36

33

30

34

35

37

38

31

32

27

24

21

25

26

28

29

22

23

5

18

12

20

19

17

16

14

13

6

0x007F

0x009A

0x00BE

0x00E4

0x00E6

0x0114

0x0281

0x0301

0x0306

0x03A1

0x0A16

0x0C1A

0x0C2E

0x0E9D

0x1DDC

0x23D5

0x2410

0x2B46

0xA417

0xC62B

0x0810

0x06a6

0x0564

0x047e

0x0474

0x03b6

0x0199

0x0155

0x0153

0x011a

0x0066

0x0055

0x0054

0x0046

0x0022

0x001d

0x001c

0x0018

0x0006

0x0005

T he Huffman coder is a digital compressor/decompressor that

can be used for compressing any type of digital data. Essentially,

an ideal Huffman coder creates a table of the most commonly

occurring code sequences (typically zero and small values near

zero) and then replaces those codes with some shorthand. T he

ADV601LC employs three fixed Huffman tables; it does not

create tables.

T he filters and the quantizer increase the number of zeros and

strings of zeros, which improves the performance of the entropy

coders. T he higher the selected compression ratio, the more

zeros and small value sequences the quantizer needs to generate.

T he transformed image in Figure 5 shows that the filter bank

concentrates zeros and small values in the higher frequency

blocks.

Encoding vs. D ecoding

T he decoding of compressed video follows the exact path as

encoding but in reverse order. T here is no need to calculate Bin

Widths during decode because the Bin Width is stored in the

compressed image during encode.

P RO GRAMMER’S MO D EL

A host device configures the ADV601LC using the Host I/O

Port. T he host reads from status registers and writes to control

registers through the Host I/O Port.

Table IV. Register D escription Conventions

Register Nam e

Register T ype (Indirect or Direct, Read or Write) and Address

Register Functional Description T ext

9

3

11

10

8

7

5

4

0

Bit [# ] or

Bit Range

[High:Low]

Bit or Bit Field Name and Usage Description

0 Action or Indication When Bit Is Cleared (Equals 0)

1 Action or Indication When Bit Is Set (Equals 1)

2

1

NOT E

¹T he Mallat block numbers, Bin Width factors, and Reciprocal Bin Width

factors in T able II correspond to the shading percent fill) of Mallat blocks in

Figure 8.

Table III. Uncom pressed Versus Com pressed D ata Using Run-Length Coding

0000000000000000000000000000000000000000000000000000000000000000000(uncompressed)

57 Zeros (Compressed)

REV. 0

–8–

ADV601LC

DIRECT (EXTERNALLY ACCESSIBLE) REGISTERS

REGISTER

ADDRESS

RESET

VALUE

BYTE 3

BYTE 2

BYTE 1

BYTE 0

RESERVED

UNDEF

0x00

0x0

0x4

0x8

0xC

INDIRECT REGISTER ADDRESS

INDIRECT REGISTER DATA

COMPRESSED DATA

RESERVED

INTERRUPT MASK / STATUS

MODE CONTROL*

0x0980

0x88

0x0

0x1

0x2

0x3

0x4

0x5

0x6

RESERVED

FIFO CONTROL

INDIRECT (INTERNALLY INDEXED) REGISTERS

0x000

HSTART

HEND

{ACCESS THESE REGISTERS THROUGH THE

INDIRECT REGISTER ADDRESS AND

INDIRECT REGISTER DATA REGISTERS}

0x3FF

*NOTE:

YOU MUST WRITE 0X0880 TO THE MODE

CONTROL REGISTER ON CHIP RESET TO

SELECT THE CORRECT PIXEL MODE

0x000

VSTART

VEND

0x3FF

RESERVED

UNDEF

0x7 – 0x7F

0x80 – 0xA9

0xAA

RESERVED

SUM OF SQUARES [0 – 41]

SUM OF LUMA

SUM OF Cb

SUM OF Cr

0xAB

0xAC

0xAD

MIN LUMA

0xAE

MAX LUMA

MIN Cb

0xAF

0xB0

MAX Cb

0xB1

MIN Cr

0xB2

MAX Cr

0xB3 – 0xFF

0x100

RESERVED

RBW0

0x101

BW0

RBW41

BW41

UNDEF

0x152

0x153

Figure 9. Map of ADV601LC Direct and Indirect Registers

REV. 0

–9–

ADV601LC

AD V601LC REGISTER D ESCRIP TIO NS

Indir ect Addr ess Register

Direct (Write) Register Byte Offset 0x00.

T his register holds a 16-bit value (index) that selects the indirect register accessible to the host through the indirect data register. All

indirect write registers are 16 bits wide. T he address in this register is auto-incremented on each subsequent access of the indirect

data register. T his capability enhances I/O performance during modes of operation where the host is calculating Bin Width controls.

[15:0] Indirect Address Register, IAR[15:0]. Holds a 16-bit value (index) that selects the indirect register to read or write through

the indirect data register (undefined at reset)

[31:16] Reserved (undefined read/write zero)

Indir ect Register D ata

Direct (Read/Write) Register Byte Offset 0x04

T his register holds a 16-bit value read or written from or to the indirect register indexed by the Indirect Address Register.

[15:0] Indirect Register Data, IRD[15:0]. A 16-bit value read or written to the indexed indirect register. Undefined at reset.

[31:16] Reserved (undefined read/write zero)

Com pr essed D ata Register

Direct (Read/Write) Register Byte Offset 0x08

T his register holds a 32-bit sequence from the compressed video bit stream. T his register is buffered by a 512 position, 32-bit FIFO.

For Word (16-bit) accesses, access Word0 (Byte 0 and Byte 1) then Word1 (Byte 2 and Byte 3) for correct auto-increment. For a

description of the data sequence, see the Compressed Data Stream Definition section.

[31:0] Compressed Data Register, CD R[31:0]. 32-bit value containing compressed video stream data. At reset, contents undefined.

Inter r upt Mask / Status Register

Direct (Read/Write) Register Byte Offset 0x0C

T his 16-bit register contains interrupt mask and status bits that control the state of the ADV601LC’s HIRQ pin. With the seven

mask bits (IE_LCODE, IE_ST AT SR, IE_FIFOST P, IE_FIFOSRQ, IE_FIFOERR, IE_CCIRER, IE_MERR); select the conditions

that are ORed together to determine the output of the HIRQ pin.

Six of the status bits (LCODE, ST AT SR, FIFOST P, MERR, FIFOERR, CCIRER) indicate active interrupt conditions and are

sticky bits that stay set until read. Because sticky status bits are cleared when read, and these bits are set on the positive edge of the

condition coming true, they cannot be read or tested for stable level true conditions multiple times.

T he FIFOSRQ bit is not sticky. T his bit can be polled to monitor for a FIFOSRQ true condition. Note: Enable this monitoring by

using the FIFOSRQ bit and correctly programming DSL and ESL fields within the FIFO control registers.

[0]

[1]

[2]

CCIR-656 Error in CCIR-656 data stream, CCIRER. T his read only status bit indicates the following:

0

1

No CCIR-656 Error condition, reset value

Unrecoverable error in CCIR-656 data stream (missing sync codes)

Statistics Ready, STATSR. T his read only status bit indicates the following:

0

1

No Statistics Ready condition, reset value (ST AT S_R pin LO)

Statistics Ready for BW calculator (ST AT S_R pin HI)

Last Code Read, LCO D E. T his read only status bit indicates the last compressed data word for field will be

retrieved from the FIFO on the next read from the host bus.

0

1

No Last Code condition, reset value (LCODE pin LO)

Next read retrieves last word for field in FIFO (LCODE pin HI)

[3]

FIFO Service Request, FIFO SRQ. T his read only status bit indicates the following:

0

1

No FIFO Service Request condition, reset value (FIFO_SRQ pin LO)

FIFO is nearly full (encode) or nearly empty (decode) (FIFO_SRQ pin HI)

REV. 0

–10–

ADV601LC

[4]

FIFO Error, FIFO ERR. This condition indicates that the host has been unable to keep up with the ADV601LC’s compressed

data supply or demand requirements. If this condition occurs during encode, the data stream will not be corrupted until

MERR indicates that the DRAM is also overflowed. If this condition occurs during decode, the video output will be

corrupted. If the system overflows the FIFO (disregarding a FIFOST P condition) with too many writes in decode mode,

FIFOERR is asserted. T his read only status bit indicates the following:

0

1

No FIFO Error condition, reset value (FIFO_ERR pin LO)

FIFO overflow (encode) or underflow (decode) (FIFO_ERR pin HI)

[5]

[6]

FIFO Stop, FIFO STP . T his condition indicates that the FIFO is full in decode mode and empty in encode mode.

In decode mode only, FIFOST P status actually behaves more conservatively than this. In decode mode, even when

FIFOST P is indicated, there are still 32 empty Dwords available in the FIFO and 32 more Dword writes can safely

be performed. T his status bit indicates the following:

0

1

No FIFO Stop condition, reset value (FIFO_ST P pin LO)

FIFO empty (encode) or full (decode) (FIFO_ST P pin HI)

Memory Error, MERR. This condition indicates that an error has occurred at the DRAM memory interface. This condition can

be caused by a defective DRAM, the inability of the Host to keep up with the ADV601LC compressed data stream, or bit errors

in the data stream. Note that the ADV601LC recovers from this condition without host intervention.

0

1

No memory error condition, reset value

Memory error

[7]

[8]

Reserved (always read/write zero)

Interrupt Enable on CCIRER, IE_CCIRER. T his mask bit selects the following:

0

1

Disable CCIR-656 data error interrupt, reset value

Enable interrupt on error in CCIR-656 data

[9]

Interrupt Enable on ST AT R, IE_STATR. T his mask bit selects the following:

0

1

Disable Statistics Ready interrupt, reset value

Enable interrupt on Statistics Ready

[10]

[11]

[12]

[13]

[14]

[15]

Interrupt Enable on LCODE, IE_LCO D E. T his mask bit selects the following:

0

1

Disable Last Code Read interrupt, reset value

Enable interrupt on Last Code Read from FIFO

Interrupt Enable on FIFOSRQ, IE_FIFO SRQ. T his mask bit selects the following:

0

1

Disable FIFO Service Request interrupt, reset value

Enable interrupt on FIFO Service Request

Interrupt Enable on FIFOERR, IE_FIFO ERR. T his mask bit selects the following:

0

1

Disable FIFO Stop interrupt, reset value

Enable interrupt on FIFO Stop

Interrupt Enable on FIFOST P, IE_FIFO STP . T his mask bit selects the following:

0

1

Disable FIFO Error interrupt, reset value

Enable interrupt on FIFO Error

Interrupt Enable on MERR, IE_MERR. T his mask bit selects the following:

0

1

Disable memory error interrupt, reset value

Enable interrupt on memory error

Reserved (always read/write zero)

Mode Contr ol Register

Indirect (Write Only) Register Index 0x00

T his register holds configuration data for the ADV601LC’s video interface format and controls several other video interface features.

For more information on formats and modes, see the Video Interface section. Bits in this register have the following functions:

[3:0]

Video Interface Format, VIF[3:0]. T hese bits select the interface format. Valid settings include the following (all

other values are reserved):

0x0 CCIR-656, reset value

0x2 MLT PX (Philips)

[4]

VCLK Output Divided by two, VCLK2. T his bit controls the following:

0

1

Do not divide VCLK output (VCLKO = VCLK), reset value

Divide VCLK output by two (VCLKO = VCLK/2)

REV. 0

–11–

ADV601LC

[5]

[6]

[7]

Video Interface Master/Slave Mode Select, M/S. T his bit selects the following:

0

1

Slave mode video interface (External control of video timing, HSYNC-VSYNC-FIELD are inputs), reset value

Master mode video interface (ADV601LC controls video timing, HSYNC-VSYNC are outputs)

Video Interface 525/625 (NT SC/PAL) Mode Select, P /N. T his bit selects the following:

0

1

525 mode video interface, reset value

625 mode video interface

Video Interface Encode/Decode Mode Select, E/D. T his bit selects the following:

0

1

Decode mode video interface (compressed-to-raw)

Encode mode video interface (raw-to-compressed), reset value

[8]

[9]

Reserved (always write zero)

Video Interface Bipolar/Unipolar Color Component Select, BUC. T his bit selects the following:

0

1

Bipolar color component mode video interface, reset value

Unipolar color component mode video interface

[10]

[11]

Reserved (always write zero)

Video Interface Software Reset, SWR. T his bit has the following effects on ADV601LC operations:

0

1

Normal operation

Software Reset. This bit is set on hardware reset and must be cleared before the ADV601LC can begin processing. (reset value)

When this bit is set during encode, the ADV601LC completes processing the current field then suspends operation until the

SWR bit is cleared. When this bit is set during decode, the ADV601LC suspends operation immediately and does not resume

operation until the SWR bit is cleared. Note that this bit must be set whenever any other bit in the Mode register is changed.

[12]

[13]

HSYNC pin Polarity, P H SYNC. T his bit has the following effects on ADV601LC operations:

0

1

HSYNC is HI during blanking, reset value

HSYNC is LO during blanking (HI during active)

HIRQ pin Polarity, P H IRQ. T his bit has the following effects on ADV601LC operations:

0

1

HIRQ is active LO, reset value

HIRQ is active HI

[15:14] Reserved (always write zero)

FIFO Contr ol Register

Indirect (Read/Write) Register Index 0x01

T his register holds the service-request settings for the ADV601LC’s host interface FIFO, causing interrupts for the “nearly full” and

“nearly empty” levels. Because each register is four bits in size, and the FIFO is 512 positions, the 4-bit value must be multiplied by

32 (decimal) to determine the exact value for encode service level (nearly full) and decode service level (nearly empty). The ADV601LC

uses these setting to determine when to generate a FIFO Service Request related host interrupt (FIFOSRQ bit and FIFO_SRQ pin).

[3:0]

Encode Service Level, ESL[3:0]. T he value in this field determines when the FIFO is considered nearly full on encode; a condi-

tion that generates a FIFO service request condition in encode mode. Since this register is four bits (16 states), and the FIFO is

512 positions, the step size for each bit in this register is 32 positions. T he following table summarizes sample states of the

register and their meaning.

ESL Interrupt When . . .

0000 Disables service requests (FIFO_SRQ never goes HI during encode)

0001 FIFO has only 32 positions filled (FIFO_SRQ when >= 32 positions are filled)

1000 FIFO is 1/2 full, reset value

1111 FIFO has only 32 positions empty (480 positions filled)

[7:4]

Decode Service Level, DSL[7:4]. The value in this field determines when the FIFO is considered nearly empty in decode; a

condition that generates a FIFO service request in decode mode. Because this register is four bits (16 states), and the FIFO

is 512 positions, the step size for each bit in this register is 32 positions. T he following table summarizes sample states of the

register and their meaning.

DSL Interrupt When . . .

0000 Disables service requests (FIFO_SRQ never goes HI)

0001 FIFO has only 32 positions filled (480 positions empty)

1000 FIFO is 1/2 empty, reset value

1111 FIFO has only 32 positions empty (FIFO_SRQ when >= 32 positions are empty)

[15:8] Reserved (always write zero)

REV. 0

–12–

ADV601LC

VID EO AREA REGISTERS

T he area defined by the HST ART , HEND, VST ART and VEND registers is the active area that the wavelet kernel processes. Video

data outside the active video area is set to minimum luminance and zero chrominance (black) by the ADV601LC. T hese registers

allow cropping of the input video during compression (encode only), but do not change the image size. Figure 10 shows how the

video area registers work together.

HSTART

HEND

Some comments on how these registers work are as follows:

• T he vertical numbers include the blanking areas of the video.

0, 0

ZERO

VSTART

Specifically, a VST ART value of 21 will include the first line

of active video, and the first pixel in a line corresponds to a

value HST ART of 0 (for NT SC regular).

ZERO

ACTIVE VIDEO AREA

Note that the vertical coordinates start with 1, whereas the

horizontal coordinates start with 0.

• T he default cropping mode is set for the entire frame. Specifi-

cally, Field 2 starts at a VST ART value of 283 (for NT SC

regular).

VEND

ZERO

X, Y

MAX FOR SELECTED VIDEO MODE

Figure 10. Video Area and Video Area Registers

H START Register

Indirect (Write Only) Register Index 0x02

T his register holds the setting for the horizontal start of the ADV601LC’s active video area. T he value in this register is usually set to

zero, but in cases where you wish to crop incoming video it is possible to do so by changing HST .

[9:0]

Horizontal Start, H ST[9:0]. 10-bit value defining the start of the active video region. (0 at reset)

[15:10] Reserved (always write zero)

H END Register

Indirect (Write Only) Register Index 0x03

T his register holds the setting for the horizontal end of the ADV601LC’s active video area. If the value is larger than the max size of

the selected video mode, the ADV601LC uses the max size of the selected mode for HEND.

[9:0]

Horizontal End, H EN[9:0].10-bit value defining the end of the active video region. (0x3FF at reset this value is larger than

the max size of the largest video mode)

[15:10] Reserved (always write zero)

VSTART Register

Indirect (Write Only) Register Index 0x04

T his register holds the setting for the vertical start of the ADV601LC’s active video area. T he value in this register is usually set to

zero unless you want to crop the active video.

T o vertically crop video while encoding, program the VST ART and VEND registers with actual video line numbers, which differ for

each field. The VSTART and VEND contents must be updated on each field. Perform this updating as part of the field-by-field BW regis-

ter update process. To perform this dynamic update correctly, the update software must keep track of which field is being processed next.

[9:0]

Vertical Start, VST[9:0]. 10-bit value defining the starting line of the active video region, with line numbers from 1-to-625

in PAL and 1-to-525 in NT SC. (0 at reset)

[15:10] Reserved (always write zero)

VEND Register

Indirect (Write Only) Register Index 0x05

T his register holds the setting for the vertical end of the ADV601LC’s active video area. If the value is larger than the max size of the

selected video mode, the ADV601LC uses the max size of the selected mode for VEND.

To vertically crop video while encoding, program the VSTART and VEND registers with actual video line numbers, which differ for each

field. The VSTART and VEND contents must be updated on each field. Perform this updating as part of the field-by-field BW register

update process. To perform this dynamic update correctly, the update software must keep track of which field is being processed next.

[9:0]

Vertical End, VEN[9:0]. 10-bit value defining the ending line of the active video region, with line numbers from 1-to-625

in PAL and 1-to-525 in NT SC. (0x3FF at reset—this value is larger than the max size of the largest video mode)

[15:10] Reserved (always write zero)

REV. 0

–13–

ADV601LC

Sum of Squar es [0–41] Register s

Indirect (Read Only) Register Index 0x080 through 0x0A9

T he Sum of Squares [0–41] registers hold values that correspond to the summation of values (squared) in corresponding Mallat

blocks [0–41]. T hese registers let the Host or DSP read sum of squares statistics from the ADV601LC; using these values (with the

Sum of Value, MIN Value, and MAX Value) the host or DSP can then calculate the BW and RBW values. T he ADV601LC indi-

cates that the sum of squares statistics have been updated by setting (1) the ST AT R bit and asserting the ST AT _R pin. Read the

statistics at any time. T he Host reads these values through the Host Interface.

[15:0] Sum of Squares, STS[15:0]. 16-bit values [0-41] for corresponding Mallat blocks [0-41] (undefined at reset). Sum of Square

values are 16-bit codes that represent the Most Significant Bits of values ranging from 40 bits for small blocks to 48 bits for

large blocks. T he 16-bit codes have the following precision:

Blocks P r ecision Sum of Squar es P r ecision D escr iption

0–2

3–11

12–20 44.–28

21–29 42.–26

30–41 40.–24

48.–32

46.–30

48.-bits wide, left shift code by 32-bits, and zero fill

46.-bits wide, left shift code by 30-bits, and zero fill

44.-bits wide, left shift code by 28-bits, and zero fill

42.-bits wide, left shift code by 26-bits, and zero fill

40.-bits wide, left shift code by 24-bits, and zero fill

If the Sum of Squares code were 0x0025 for block 10, the actual value would be 0x000940000000; if using that same

code, 0x0025, for block 30, the actual value would be 0x0025000000.

[31:0] Reserved (always read zero)

Sum of Lum a Value Register

Indirect (Read Only) Register Index 0x0AA

T he Sum of Luma Value register lets the host or DSP read the sum of pixel values for the Luma component in block 39. T he Host

reads these values through the Host Interface.

[15:0] Sum of Luma, SL[15:0]. 16-bit component pixel values (undefined at reset)

[31:0] Reserved (always read zero)

Sum of Cb Value Register

Indirect (Read Only) Register Index 0x0AB

T he Sum of Cb Value register lets the host or DSP read the sum of pixel values for the Cb component in block 40. T he Host reads

these values through the Host Interface.

[15:0] Sum of Cb, SCB[15:0]. 16-bit component pixel values (undefined at reset)

[31:0] Reserved (always read zero)

Sum of Cr Value Register

Indirect (Read Only) Register Index 0x0AC

T he Sum of Cr Value register lets the host or DSP read the sum of pixel values for the Cr component in block 41. T he Host reads

these values through the Host Interface.

[15:0] Sum of Cr, SCR[15:0]. 16-bit component pixel values (undefined at reset)

[31:0] Reserved (always read zero)

MIN Lum a Value Register

Indirect (Read Only) Register Index 0x0AD

T he MIN Luma Value register lets the host or DSP read the minimum pixel value for the Luma component in the unprocessed data.

T he Host reads these values through the Host Interface.

[15:0] Minimum Luma, MNL[15:0]. 16-bit component pixel value (undefined at reset)

[31:0] Reserved (always read zero)

MAX Lum a Value Register

Indirect (Read Only) Register Index 0x0AE

T he MAX Luma Value register lets the host or DSP read the maximum pixel value for the Luma component in the unprocessed

data. T he Host reads these values through the Host Interface.

[15:0] Maximum Luma, MXL[15:0]. 16-bit component pixel value (undefined at reset)

[31:0] Reserved (always read zero)

REV. 0

–14–

ADV601LC

MIN Cb Value Register

Indirect (Read Only) Register Index 0x0AF

T he MIN Cb Value register lets the host or DSP read the minimum pixel value for the Cb component in the unprocessed data.

T he Host reads these values through the Host Interface.

[15:0] Minimum Cb, MNCB[15:0], 16-bit component pixel value (undefined at reset)

[31:0] Reserved (always read zero)

MAX Cb Value Register

Indirect (Read Only) Register Index 0x0B0

T he MAX Cb Value register lets the host or DSP read the maximum pixel value for the Cb component in the unprocessed data.

T he Host reads these values through the Host Interface.

[15:0] Maximum Cb, MXCB[15:0].16-bit component pixel value (undefined at reset)

[31:0] Reserved (always read zero)

MIN Cr Value Register

Indirect (Read Only) Register Index 0x0B1

T he MIN Cr Value register lets the host or DSP read the minimum pixel value for the Cr component in the unprocessed data.

T he Host reads these values through the Host Interface.

[15:0] Minimum Cr, MNCR[15:0]. 16-bit component pixel value (undefined at reset)

[31:0] Reserved (always read zero)

MAX Cr Value Register

Indirect (Read Only) Register Index 0x0B2

T he MAX Cr Value register lets the host or DSP read the maximum pixel value for the Cr component in the unprocessed data.

T he Host reads these values through the Host Interface.

[15:0] Maximum Cr, MXCR[15:0]. 16-bit component pixel value (undefined at reset)

[31:0] Reserved (always read zero)

Bin Width and Recipr ocal Bin Width Register s

Indirect (Read/Write) Register Index 0x0100-0x0153

T he RBW and BW values are calculated by the host or DSP from data in the Sum of Squares [0-41], Sum of Value, MIN Value, and

MAX Value registers; then are written to RBW and BW registers during encode mode to control the quantizer. T he Host writes

these values through the Host Interface.

T hese registers contain a 16-bit interleaved table of alternating RBW/BW (RBW-even addresses and BW-odd addresses) values

as indexed on writes by address register. Bin Widths are 8.8, unsigned, 16-bit, fixed-point values. Reciprocal Bin Widths are

6.10, unsigned, 16-bit, fixed-point values. Operation of this register is controlled by the host driver or the DSP (84 total entries)

(undefined at reset).

[15:0] Bin Width Values, BW[15:0]

[15:0] Reciprocal Bin Width Values, RBW[15:0]

REV. 0

–15–

ADV601LC

P IN FUNCTIO N D ESCRIP TIO NS

D escription

Clock P ins

Nam e

P ins

I/O

VCLK/XT AL

2

I

A single clock (VCLK) or crystal input (across VCLK and XT AL). An acceptable

50% duty cycle clock signal is 27 MHz (CCIR-601 NT SC/PAL).

If using a clock crystal, use a parallel resonant, microprocessor grade clock crystal. If

using a clock input, use a T T L level input, 50% duty cycle clock with 1 ns (or less)

jitter (measured rising edge to rising edge). Slowly varying, low jitter clocks are

acceptable; up to 5% frequency variation in 0.5 sec.

VCLKO

1

O

VCLK Output or VCLK Output divided by two. Select function using Mode

Control register.

Video Inter face P ins

Nam e

P ins

I/O

D escription

VSYNC

1

I or O

Vertical Sync or Vertical Blank. T his pin can be either an output (Master Mode) or

an input (Slave Mode). T he pin operates as follows:

•

Output (Master) HI during inactive lines of video and LO otherwise

Input (Slave) a HI on this input indicates inactive lines of video

HSYNC

1

I or O

Horizontal Sync or Horizontal Blank. T his pin can be either an output (Master

Mode) or an input (Slave Mode). T he pin operates as follows:

•

Output (Master) HI during inactive portion of video line and LO otherwise

Input (Slave) a HI on this input indicates inactive portion of video line

Note that the polarity of this signal is modified using the Mode Control register. For

detailed timing information, see the Video Interface section.

FIELD

ENC

1

I or O

Field # or Frame Sync. T his pin can be either an output (Master Mode) or an input

(Slave Mode). T he pin operates as follows:

•

Output (Master) HI during Field1 lines of video and LO otherwise

Input (Slave) a HI on this input indicates Field1 lines of video

O

Encode or Decode. T his output pin indicates the coding mode of the ADV601LC

and operates as follows:

•

LO Decode Mode (Video Interface is output)

HI Encode Mode (Video Interface is input)

Note that this pin can be used to control bus enable pins for devices connected to

the ADV601LC Video Interface.

VDAT A[7:0]

8

I/O

4:2:2 Video Data (8-bit digital component video data). T hese pins are inputs during

encode mode and outputs during decode mode. When outputs (decode) these pins

are compatible with 50 pF loads (rather than 30 pF as all other busses) to meet the

high performance and large number of typical loads on this bus.

T he performance of these pins varies with the Video Interface Mode set in the

Mode Control register, see the Video Interface section of this data sheet for pin

assignments in each mode.

Note that the Mode Control register also sets whether the color component is

treated as either signed or unsigned.

REV. 0

–16–

ADV601LC

D RAM Inter face P ins

Nam e

P ins

I/O

D escription

DDAT [15:0]

16

I/O

DRAM Data Bus. T he ADV601LC uses these pins for 16-bit data read/write

operations to the external 256K × 16-bit DRAM. (T he operation of the DRAM

interface is fully automatic and controlled by internal functionality of the

ADV601LC.) T hese pins are compatible with 30 pF loads.

DADR[8:0]

9

O

DRAM Address Bus. T he ADV601LC uses these pins to form the multiplexed

row/column address lines to the external DRAM. (T he operation of the DRAM

interface is fully automatic and controlled by internal functionality of the

ADV601LC.) T hese pins are compatible with 30 pF loads.

RAS

CAS

WE

1

O

DRAM Row Address Strobe. T his pin is compatible with 30 pF loads.

DRAM Column Address Strobe. T his pin is compatible with 30 pF loads.

DRAM Write Enable. T his pin is compatible with 30 pF loads.

Note that the ADV601LC does not have a DRAM OE pin. T ie the DRAM’s

OE pin to ground.

H ost Inter face P ins

Nam e

P ins

I/O

D escription

DAT A[31:0]

32

I/O

Host Data Bus. T hese pins make up a 32-bit wide host data bus. T he host

controls this asynchronous bus with the WR, RD, BE, and CS pins to commu-

nicate with the ADV601LC. T hese pins are compatible with 30 pF loads.

ADR[1:0]

2

I

H ost DWord Address Bus. T hese two address pins let you address the

ADV601LC’s four directly addressable host interface registers. For an illustra-

tion of how this addressing works, see the Control and Write Register Map

figure and Status and Read Register Map figure. T he ADR bits permit register

addressing as follows:

ADR1

ADR0

DWord

Address Byte Address

0

1

0

1

0

1

0

1

2

3

0x00

0x04

0x08

0x0C

BE0–BE3

2

I

H ost Word Enable pins. T hese two input pins select the words that the

ADV601LC’s direct and indirect registers access through the Host Interface;

BE0–BE1 access the least significant word, and BE2–BE3 access the most

significant word. For a 32-bit interface only, tie these pins to ground, making

all words available.

Some important notes for 16-bit interfaces are as follows:

•

When using these byte enable pins, the byte order is always the lowest byte

to the higher bytes.

T he ADV601LC advances to the next 32-bit compressed data FIFO location

after the BE2–BE3 pin is asserted then de-asserted (when accessing the Com-

pressed Data register); so the FIFO location only advances when and if the

host reads or writes the MSW of a FIFO location.

•

The ADV601LC advances to the next 16-bit indirect register after the BE0–BE1

pin is asserted then de-asserted; so the register selection only advances when

and if the host reads or writes the MSW of a 16-bit indirect register.

CS

1

I

Host Chip Select. T his pin operates as follows:

•

LO Qualifies Host Interface control signals

HI T hree-states DAT A[31:0] pins

WR

RD

1

I

Host Write. Host register writes occur on the rising edge of this signal.

Host Read. Host register reads occur on the low true level of this signal.

REV. 0

–17–

ADV601LC

H ost Inter face P ins (Continued)

Nam e

P ins

I/O

D escription

ACK

1

O

Host Acknowledge. T he ADV601LC acknowledges completion of a Host Interface

access by asserting this pin. Most Host Interface accesses (other than the com-

pressed data register access) result in ACK being held high for at least one wait

cycle, but some exceptions to that rule are as follows:

•

A full FIFO during decode operations causes the ADV601LC to de-assert

(drive HI) the ACK pin, holding off further writes of compressed data until

the FIFO has one available location.

An empty FIFO during encode operations causes the ADV601LC to de-assert

(drive HI) the ACK pin, holding off further reads until one location is filled.

FIFO_SRQ

1

O

FIFO Service Request. T his pin is an active high signal indicating that the FIFO

needs to be serviced by the host. (see FIFO Control register). T he state of this pin

also appears in the Interrupt Mask/Status register. Use the interrupt mask to assert a

Host interrupt (HIRQ pin) based on the state of the FIFO_SRQ pin. T his pin oper-

ates as follows:

•

LO No FIFO Service Request condition (FIFOSRQ bit LO)

HI FIFO needs service is nearly full (encode) or nearly empty (decode)

During encode, FIFO_SRQ is LO when the SWR bit is cleared (0) and goes HI

when the FIFO is nearly full (see FIFO Control register).

During decode, FIFO_SRQ is HI when the SWR bit is cleared (0), because FIFO

is empty, and goes LO when the FIFO is filled beyond the nearly empty condition

(see FIFO Control register).

ST AT S_R

1

O

Statistics Ready. T his pin indicates the Wavelet Statistics (contents of Sum of

Squares, Sum of Value, MIN Value, MAX Value registers) have been updated and

are ready for the Bin Width calculator to read them from the host interface. T he

frequency of this interrupt will be equal to the field rate. T he state of this pin also

appears in the Interrupt Mask/Status register. Use the interrupt mask to assert a

Host interrupt (HIRQ pin) based on the state of the ST AT S_R pin. T his pin oper-

ates as follows:

•

LO No Statistics Ready condition (ST AT SR bit LO)

HI Statistics Ready for BW calculator (ST AT SR bit HI)

LCODE

1

O

Last Compressed Data (for field). T his bit indicates the last compressed data word

for field will be retrieved from the FIFO on the next read from the host bus. T he

frequency of this interrupt is similar to the field rate, but varies depending on

compression and host response. T he state of this pin also appears in the Interrupt

Mask/Status register. Use the interrupt mask to assert a Host interrupt (HIRQ pin)

based on the state of the LCODE pin. T his pin operates as follows:

•

LO No Last Code condition (LCODE bit LO)

HI Last data word for field has been read from FIFO (LCODE bit HI)

HIRQ

1

O

I

Host Interrupt Request. T his pin indicates an interrupt request to the Host. T he

Interrupt Mask/Status register can select conditions for this interrupt based on any

or all of the following: FIFOST P, FIFOSRQ, FIFOERR, LCODE, ST AT R or

CCIR-656 unrecoverable error. Note that the polarity of the HIRQ pin can be

modified using the Mode Control register.

RESET

ADV601LC Chip Reset. Asserting this pin returns all registers to reset state. Note

that the ADV601LC must be reset at least once after power-up with this active low

signal input. For more information on reset, see the SWR bit description.

P ower Supply P ins

Nam e

P ins

I/O

D escription

GND

VDD

16

13

I

Ground

+5 V dc Digital Power

REV. 0

–18–

ADV601LC

Video Inter face

receives the VSYNC, HSYNC, and FIELD signals. In master

mode, the ADV601LC generates these signals for external

hardware synchronization. In slave mode, the ADV601LC

receives these signals. Note that some video formats require

the ADV601LC to operate in slave mode only. T his control is

maintained by the host processor.

T he ADV601LC video interface supports two types of compo-

nent digital video (D1) interfaces in both compression (input)

and decompression (output) modes. T hese digital video inter-

faces include support for the Multiplexed Philips 4:2:2 and

CCIR-656/SMPT E125M—international standard.

Video interface master and slave modes allow for the generation

or receiving of synchronization and blanking signals. Definitions

for the different formats can be found later in this section. For

recommended connections to popular video decoders and

encoders, see the Connecting The ADV601LC To Popular Video

Decoders and Encoders section. A complete list of supported

video interfaces and sampling rates is included in T able V.

• 525-625 (NTSC-PAL) Control

T his control determines whether the ADV601LC is operating

on 525/NT SC video or 625/PAL video. T his information is

used when the ADV601LC is in master and decode modes so

that the ADV601LC knows where and when to generate the

HSYNC, VSYNC, and FIELD Pulses as well as when to

insert the SAV and EAV time codes (for CCIR-656 only) in

the data stream. T his control is maintained by the host pro-

cessor. T able VI shows how the 525-625 Control in the Mode

Control register works.

Table V. Com ponent D igital Video Interfaces

Nom inal

Bits/

Color

D ate

Table VI. Square P ixel Control, 525-625 Control, and

Video Form ats

Nam e

Com ponent Space

Sam pling Rate (MH z) I/F Width

CCIR-656

Multiplex

Philips

8

YCrCb 4:2:2

27

8

Max

H orizontal

Size

Max

Field

Size

YUV 4:2:2

27

8

525-625

Control

NTSC-P AL

Internally, the video interface translates all video formats to one

consistent format to be passed to the wavelet kernel. T his con-

sistent internal video standard is 4:2:2 at 16 bits accuracy.

0

1

720

243

288

CCIR-601 NT SC

CCIR-601 PAL

VITC a nd Closed Ca ptioning Suppor t

• Bipolar/Unipolar Color Component

T he video interface also supports the direct loss-less extraction

of 90-bit VIT C codes during encode and the insertion of VIT C

codes during decode. Closed Captioning data (found on active

Video Line 21) is handled just as normal active video on an

active scan line. As a result, no special dedicated support is

necessary for Closed Captioning. T he data rates for Closed

Captioning data are low enough to ensure robust operation of

this mechanism at compression ratios of 50:1 and higher. Note

that you must include Video Line 21 in the ADV601LC’s de-

fined active video area for Closed Caption support.

T his mode determines whether offsets are used on color com-

ponents. In Philips mode, this control is usually set to Bipo-

lar, since the color components are normal twos-compliment

signed values. In CCIR-656 mode, this control is set to Uni-

polar, since the color components are offset by 128. Note that

it is likely the ADV601LC will function if this control is in the

wrong state, but compression performance will be degraded.

It is important to set this bit correctly.

• Active Area Control

Four registers HST ART (horizontal start), HEND (horizon-

tal end), VST ART (vertical start) and VEND (vertical end)

determine the active video area. T he maximum active video

area is 720 by 288 pixels for a single field.

27 MHz Nom ina l Sa m pling

T here is one clock input (VCLK) to support all internal process-

ing elements. T his is a 50% duty cycle signal and must be syn-

chronous to the video data. Internally this clock is doubled using

a phase locked loop to provide for a 54 MHz internal processing

clock. T he clock interface is a two pin interface that allows a

crystal oscillator to be tied across the pins or a clock oscillator to

drive one pin. T he nominal clock rate for the video interface is

27 MHz. Note that the ADV601LC also supports a pixel rate of

13.5 MHz.

• Video Format

T his control determines the video format that is supported. In

general, the goal of the various video formats is to support

glueless interfaces to the wide variety of video formats periph-

eral components expect. T his control is maintained by the

host processor. T able VII shows a synopsis of the supported

video formats. Definitions of each format can be found later

in this section. For Video Interface pins descriptions, see the

Pin Function Descriptions.

Video Inter fa ce a nd Modes

In all, there are seven programmable features that configure the

video interface. T hese are:

• Encode-Decode Control

In addition to determining what functions the internal pro-

cessing elements must perform, this control determines the

direction of the video interface. In decode mode, the video

interface outputs data. In encode mode, the interface receives

data. T he state of the control is reflected on the ENC pin.

T his pin can be used as an enable input by external line driv-

ers. T his control is maintained by the host processor.

• Master-Slave Control

T his control determines whether the ADV601LC generates or

REV. 0

–19–

ADV601LC

Clocks a nd Str obes

Table VIII. VD ATA[7:0] P in Functions Under CCIR-656

and Multiplex P hilips

All video data is synchronous to the video clock (VCLK).

T he rising edge of VCLK is used to clock all data into the

ADV601LC.

VD ATA[7:0] P ins

CCIR-656

Multiplex P hilips

Synchr oniza tion a nd Bla nking Pins

7

6

5

4

3

2

1

0

Data9

Data8

Data7

Data6

Data5

Data4

Data3

Data2

Data9

Data8

Data7

Data6

Data5

Data4

Data3

Data2

T hree signals, which can be configured as inputs or outputs, are

used for video frame and field horizontal synchronization and

blanking. T hese signals are VSYNC, HSYNC, and FIELD.

VDATA Pins Functions With Differing Video Interface Form ats

T he functionality of the Video Interface pins depends on the

current video format. T able VIII defines how Video data pins

are used for the various formats.

Table VII. Com ponent D igital Video Form ats

Nom inal

Bit/

Com ponent

Color

Space

Data Rate

(MHz)

Master/

Slave

Form at

Num ber

Nam e

Sam pling

I/F Width

CCIR-656

Multiplex Philips

8

YCrCb

YUV

4:2:2

27

<=29.5

Master

Either

8

0x0

0x2

VCLK is driven with a 27 MHz, 50% duty cycle clock which is

synchronous with the video data. Video data is clocked on the

rising edge of the VCLK signal. When decoding, the VCLK

signal is typically transmitted along with video data in the

CCIR-656 physical interface.

Video For m a ts—CCIR-656

T he ADV601LC supports a glueless video interface to CCIR-656

devices when the Video Format is programmed to CCIR-656

mode. CCIR-656 requires that 4:2:2 data (8 bits per compo-

nent) be multiplexed and transmitted over a single 8-bit physical

interface. A 27 MHz clock is transmitted along with the data.

T his clock is synchronous with the data. T he color space of

CCIR-656 is YCrCb.

Electrically, CCIR-656 specifies differential ECL levels to be

used for all interfaces. T he ADV601LC, however, only supports

unipolar, T T L logic thresholds. Systems designs that interface

to strictly conforming CCIR-656 devices (especially when inter-

facing over long cable distances) must include ECL level shifters

and line drivers.

When in master mode, the CCIR-656 mode does not require

any external synchronization or blanking signals to accompany

digital video. Instead, CCIR-656 includes special time codes in

the stream syntax that define horizontal blanking periods, verti-

cal blanking periods, and field synchronization (horizontal and

vertical synchronization information can be derived). T hese

time codes are called End-of-Active-Video (EAV) and Start-of-

Active-Video (SAV). Each line of video has one EAV and one

SAV time code. EAV and SAV have three bits of embedded

information to define HSYNC, VSYNC and Field information

as well as error detection and correction bits.

T he functionality of HSYNC, VSYNC and FIELD Pins is

dependent on three programmable modes of the ADV601LC:

Master-Slave Control, Encode-Decode Control and 525-625

Control. T able IX summarizes the functionality of these pins in

various modes.

Table IX. CCIR-656 Master and Slave Modes H SYNC, VSYNC, and FIELD Functionality

H SYNC, VSYNC and FIELD

Functionality for CCIR-656

Master Mode (H SYNC, VSYNC

and FIELD Are O utputs)

Slave Mode (H SYNC, VSYNC

and FIELD Are Inputs)

Encode Mode (video data is input

to the chip)

Pins are driven to reflect the states of the

received time codes: EAV and SAV. T his

functionality is independent of the state of

the 525-625 mode control. An encoder is

most likely to be in master mode.

Undefined—Use Master Mode

Decode Mode (video data is output

from the chip)

Pins are output to the precise timing definitions

for CCIR-656 interfaces. T he state of the pins

reflect the state of the EAV and SAV timing

codes that are generated in the output video data.

T hese definitions are different for 525 and 625 line

systems. T he ADV601LC completely manages the

generation and timing of these pins.

Undefined—Use Master Mode

REV. 0

–20–

ADV601LC

VCLK is driven with up to a 29.5 MHz 50% duty cycle clock

synchronous with the video data. Video data is clocked on the

rising edge of the VCLK signal. T he functionality of HSYNC,

VSYNC, and FIELD pins is dependent on three programmable

modes of the ADV601LC: Master-Slave Control, Encode-

Decode Control, and 525-625 Control. T able X summarizes the

functionality of these pins in various modes.

Video For m a ts — Multiplexed Philips Video

The ADV601LC supports a hybrid mode of operation that is a

cross between standard dual lane Philips and single lane CCIR-

656. In this mode, video data is multiplexed in the same fashion in

CCIR-656, but the values 0 and 255 are not reserved as signaling

values. Instead, external HSYNC and VSYNC pins are used for

signaling and video synchronization. VCLK may range up to

29.5 MHz.

Table X. P hilips Multiplexed Video Master and Slave Modes H SYNC, VSYNC, and FIELD Functionality

H SYNC, VSYNC and FIELD

Functionality for Multiplexed

P hilips

Master Mode (H SYNC, VSYNC

and FIELD Are O utputs)

Slave Mode (H SYNC, VSYNC

and FIELD Are Inputs)

Encode Mode (video data is input

to the chip)

T he ADV601LC completely manages the generation and These pins are used to control the

timing of these pins. T he device driving the ADV601LC blanking of video and sequencing.

video interface must use these outputs to remain in

sync with the ADV601LC. It is expected that this com-

bination of modes would not be used frequently.

Decode Mode (video data is output

from the chip)

T he ADV601LC completely manages the generation

and timing of these pins.

T hese pins are used to control the

blanking of video and sequencing.

Video For m a ts—Refer ences

For more information on video interface standards, see the

following reference texts.

in the calculation of Bin Widths and re-order wavelet transform

data. T he use of current field statistics in the Bin Width calcu-

lation results in precise control over the compressed bit rate.

T he DRAM manager manages the entire operation and refresh of

the DRAM.

• For the definition of CCIR-601:

1992 – CCIR Recommendations RBT series Broadcasting Service

(Television) Rec. 601-3 Encoding Parameters of digital television

for studios, page 35, September 15, 1992.

T he interface between the ADV601LC DRAM manager and

DRAM is designed to be transparent to the user. The ADV601LC

DRAM pins should be connected to the DRAM as called out in

the Pin Function Descriptions section. T he ADV601LC re-

quires one 256K word by 16-bit, 60 ns DRAM. T he following

is a selected list of manufacturers and part numbers. All parts

can be used with the ADV601LC at all VCLK rates except

where noted. Any DRAM used with the ADV601LC must

meet the minimum specifications outlined for the Hyper Mode

DRAMs listed in T able XI. For DRAM Interface pins descrip-

tions, see the Pin Function Descriptions.

• For the definition of CCIR-656:

1992 – CCIR Recommendations RBT series Broadcasting Service

(Television) Rec. 656-1 Interfaces for digital component video

signals in 525 and 626 line television systems operating at the

4:2:2 level of Rec. 601, page 46, September 15, 1992.

H ost Inter face

T he ADV601LC host interface is a high performance interface

that passes all command and real-time compressed video data

between the host and codec. A 512 position by 32-bit wide,

bidirectional FIFO buffer passes compressed video data to and

from the host. T he host interface is capable of burst transfer

rates of up to 132 million bytes per second (4 × 33 MHz). For

host interface pins descriptions, see the Pin Function Descriptions

section. For host interface timing information, see the Host Interface

Timing section.

Table XI. AD V601LC Com patible D RAMs

Manufacturer P art Num ber

Notes

T oshiba

NEC

T C514265DJ/DZ/DFT -60 None

µPD424210ALE-60

µPD42S4210ALE-60

None

CBR Self Refresh

feature of this prod-

uct is not needed by

the ADV601LC.

None

D RAM Manager

T he DRAM Manager provides a sorting and reordering func-

tion on the sub-band coded data between the Wavelet Kernel

and the Programmable Quantizer. T he DRAM manager pro-

vides a pipeline delay stage to the ADV601LC. T his pipeline

lets the ADV601LC extract current field image statistics (min/

max pixel values, sum of pixel values, and sum of squares) used

Hitachi

HM514265CJ-60

REV. 0

–21–

ADV601LC

Com pr essed D ata-Str eam D efinition

video data transfer that matches the transfer order shown in

Figure 11 and uses the code names shown in T able XIV. T he

blocks of data listed in Figure 11 correspond to wavelet com-

pressed sections of each field illustrated in Figure 12 as a modified

Mallat diagram.

T hrough its Host Interface the ADV601LC outputs (during

encode) and receives (during decode) compressed digital video

data. T his stream of data passing between the ADV601LC and

the host is hierarchically structured and broken up into blocks of

data as shown in Figure 11. T able IV shows pseudo code for a

TIME

(CONTINUOUS STREAM OF FRAMES)

FRAME (N + M)

FRAME (N)

FRAME (N + 1)

FRAME (N + 2)

FIELD 1 SEQUENCE

FIELD 2 SEQUENCE

FIELD SEQUENCE STRUCTURE

START OF FIELD 1 OR 2 CODE

VERTICAL INTERFACE TIME CODE

FIRST BLOCK SEQUENCE

COMPLETE BLOCK SEQUENCE

FIRST BLOCK SEQUENCE STRUCTURE

SUB-BAND TYPE CODE

BIN WIDTH QUANTIZER CODE

DATA FOR MALLAT BLOCK 6

COMPLETE BLOCK SEQUENCE ORDER

(STREAM OF MALLAT

BLOCK SEQUENCES)

SEQUENCE FOR MALLAT BLOCK 9

SEQUENCE FOR MALLAT BLOCK 20

SEQUENCE FOR MALLAT BLOCK 3

COMPLETE BLOCK (INDIVIDUAL) SEQUENCE STRUCTURE

START OF BLOCK CODE

BIN WIDTH QUANTIZER CODE

DATA FOR MALLAT BLOCK

Figure 11. Hierarchical Structure of Wavelet Com pressed Fram e Data (Data Block Order)

REV. 0

–22–

ADV601LC

Table XII. P seudo-Code D escribing a Sequence of Video Fields

Com plete Sequence:

(Field Sequences)

# EOS

“Frame N; Field 1”

“Frame N; Field 2”

“Frame N+1; Field 1”

“Frame N+1; Field 2”

“Frame N+M; Field 1”

“Frame N+M; Field 2”

“Required in decode to let the ADV601LC know the sequence of

fields is complete.”

Field 1 Sequence:

# SOF1

<VIT C>

Field 2 Sequence:

# SOF2

<VIT C>

Fir st Block Sequence:

<BW>

<Huff_Data>

Com plete Block Sequence:

. . .

(Block Sequences)

. . .

Block Sequence:

# SOB1, # SOB2, # SOB3, # SOB4 or # SOB5

<BW>

<Huff_Data>

REV. 0

–23–

ADV601LC

In general, a Frame of data is made up of odd and even Fields as

shown in Figure 11. Each Field Sequence is made up of a First

Block Sequence and a Complete Block Sequence. T he First

Block Sequence is separate from the Complete Block Sequence.

T he Complete Block Sequence contains the remaining 41 Block

Sequences (see block numbering in Figure 12). Each Block

Sequence contains a start of block delimiter, Bin Width for the

block and actual encoder data for the block. A pseudo code bit

stream example for one complete field of video is shown in

T able XIII. A pseudo code bit stream example for one sequence

of fields is shown in T able XIV. An example listing of a field of

video in ADV601LC bitstream format appears in T able XVI.

Y COMPONENT

39 33

30

24

21

36

15

12

27

6

18

0

9

3

40 34

37 31

Cb COMPONENT

25

16

13

28 22

19

7

1

10

4

41

35

38 32

Cr COMPONENT

26

17

14

29 23

20

8

2

11

5

Figure 12. Block Order of Wavelet Com pressed Field Data (Modified Mallat Diagram )

REV. 0

–24–

ADV601LC

Table XIII. P seudo-Code of Com pressed Video D ata Bitstream for O ne Field of Video

Block Sequence D ata For Mallat Block Num ber . . .

# SOFn<VIT C><T YPE4><BW><Huff_Data>

n indicates field 1 or 2 Huff_Data indicates Mallat block 6 data

A typical Bin Width (BW) factor for this block is 0x1DDC

Mallat block 9 data—T ypical BW = 0x1DDC

Mallat block 20 data—T ypical BW = 0x0C2E

Mallat block 22 data—T ypical BW = 0x03A1

Mallat block 19 data—T ypical BW = 0x0C2E

Mallat block 23 data—T ypical BW = 0x03A1

Mallat block 17 data—T ypical BW = 0x0C2E

Mallat block 25 data—T ypical BW = 0x0306

Mallat block 16 data—T ypical BW = 0x0C2E

Mallat block 26 data—T ypical BW = 0x0306

Mallat block 14 data—T ypical BW = 0x0E9D

Mallat block 28 data—T ypical BW = 0x0306

Mallat block 13 data—T ypical BW = 0x0E9D

Mallat block 29 data—T ypical BW = 0x0306

Mallat block 11 data—T ypical BW = 0x2410

Mallat block 31 data—T ypical BW = 0x0114

Mallat block 10 data—T ypical BW = 0x2410

Mallat block 32 data—T ypical BW = 0x0114

Mallat block 8 data—T ypical BW = 0x2410

Mallat block 34 data—T ypical BW = 0x00E5

Mallat block 7 data—T ypical BW = 0x2410

Mallat block 35 data—T ypical BW = 0x00E6

Mallat block 5 data—T ypical BW = 0x2B46

Mallat block 37 data—T ypical BW = 0x00E6

Mallat block 4 data—T ypical BW = 0x2B46

Mallat block 38 data—T ypical BW = 0x00E6

Mallat block 2 data—T ypical BW = 0xC62B

Mallat block 40 data—T ypical BW = 0x009A

Mallat block 1 data—T ypical BW = 0xC62B

Mallat block 41 data—T ypical BW = 0x009A

Mallat block 0 data—T ypical BW = 0xA417

Mallat block 39 data—T ypical BW = 0x007F

Mallat block 12 data—T ypical BW = 0x0C1A

Mallat block 36 data—T ypical BW = 0x00BE

Mallat block 15 data—T ypical BW = 0x0A16

Mallat block 33 data—T ypical BW = 0x00BE

Mallat block 18 data—T ypical BW = 0x0A16

Mallat block 30 data—T ypical BW = 0x00E4

Mallat block 21 data—T ypical BW = 0x0301

Mallat block 27 data—T ypical BW = 0x0281

Mallat block 24 data—T ypical BW = 0x0281

Mallat block 3 data—T ypical BW = 0x23D5

# SOB4<BW><Huff_Data>

# SOB3<BW><Huff_Data>

# SOB1<BW><Huff_Data>

# SOB3<BW><Huff_Data>

# SOB1<BW><Huff_Data>

# SOB3<BW><Huff_Data>

# SOB1<BW><Huff_Data>

# SOB3<BW><Huff_Data>

# SOB1<BW><Huff_Data>

# SOB3<BW><Huff_Data>

# SOB1<BW><Huff_Data>

# SOB3<BW><Huff_Data>

# SOB1<BW><Huff_Data>

# SOB3<BW><Huff_Data>

# SOB1<BW><Huff_Data>

# SOB3<BW><Huff_Data>

# SOB1<BW><Huff_Data>

# SOB4<BW><Huff_Data>

# SOB2<BW><Huff_Data>

# SOB4<BW><Huff_Data>

# SOB2<BW><Huff_Data>

# SOB4<BW><Huff_Data>

# SOB2<BW><Huff_Data>

# SOB4<BW><Huff_Data>

# SOB2<BW><Huff_Data>

# SOB4<BW><Huff_Data>

T able XIV specifies the Mallat block transfer order and associated Start of Block (SOB) codes. Any of these SOB codes can be

replaced with an SOB# 5 code for a zero data block.

Table XIV. P seudo-Code of Com pressed Video D ata Bitstream for O ne Sequence of Video Fields

Block Sequence D ata

For Mallat Block Num ber

# SOF1<VIT C><T YPE4><BW><Huff_Data>

... (41 # SOBn blocks)

/* Mallat block 6 data */

# SOF2<VIT C><T YPE4><BW><Huff_Data>

... (41 # SOBn blocks)

/* Mallat block 6 data */

.

(any number of Fields in sequence)

# EOS

/* Required in decode to end field sequence*/

REV. 0

–25–

ADV601LC

Table XV. AD V601LC Field and Block D elim iters (Codes)

Code Nam e

Code

D escription (Align all # D elim iter Codes to 32-Bit Boundaries)

#SOF1

0xffffffff40000000

0xffffffff41000000

(96 bits)

Start of Field delimiter identifies Field1 data. # SOF1 resets the Huffman decoder and

is sufficient on its own to reset the processing of the chip during decode. Please note

that this code or # SOF2 are the only delimiters necessary between adjacent fields.

# SOF1 operates identically to # SOF2 except that during decode it can be used to

differentiate between Field1 and Field2 in the generation of the Field signal (master

mode) and/or SAV/EAV codes for CCIR-656 modes.

#SOF2

Start of Field delimiter identifies Field2 data. # SOF resets the Huffman decoder and

is sufficient on its own to reset the processing of the chip during decode. Please note

that this code or # SOF1 are the only delimiters necessary between adjacent fields.

# SOF2 operates identically to # SOF1 except that during decode it can be used to

differentiate between Field2 and Field1 in the generation of the Field signal (master

mode) and/or SAV/EAV codes for CCIR-656 modes.

<VITC>

T his is a 12-byte string of data extracted by the video interface during encode opera-

tions and inserted by the video interface into the video data during decode operations.

T he data content is 90 bits in length. For a complete description of VIT C format, see

pages 175-178 of Video Demystified: A Handbook For T he Digital Engineer (listed in

References section).

<TYPE1>

<TYPE2>

<TYPE3>

<TYPE4>

0x81

0x82

0x83

0x84

T his is an 8-bit delimiter-less type code for the first sub-band block of wavelet data.

(Model 1 Chroma)

T his is an 8-bit delimiter-less type code for the first sub-band block of wavelet data.

(Model 1 Luma)

T his is an 8-bit delimiter-less type code for the first sub-band block of wavelet data.

(Model 2 Chroma)

T his is an 8-bit delimiter-less type code for the first sub-band block of wavelet data.

(Model 2 Luma)

#SOB1

#SOB2

#SOB3

#SOB4

#SOB5

0xffffffff81

0xffffffff82

0xffffffff83

0xffffffff84

0xffffffff8f

Start of Block delimiter identifies the start of Huffman coded sub-band data. T his

delimiter will reset the Huffman decoder if a system ever experiences bit errors or gets

out of sync. T he order of blocks in the frame is fixed and therefore implied in the bit

stream and no unique # SOB delimiters are needed per block. T here are 41 # SOB

delimiters and associated BW and Huffman data within a field. # SOB1 is differenti-

ated from # SOB2, # SOB3 and # SOB4 in that they indicate which model and

Huffman table was used in the Run Length Coder for the particular block:

# SOB1 Model 1 Chroma

# SOB2 Model 1 Luma

# SOB3 Model 2 Chroma

# SOB4 Model 2 Luma

# SOB5 Zero data block. All data after this delimiter and before the next start of block

delimiter is ignored (if present at all) and assumed zero including the BW value.

REV. 0

–26–

ADV601LC

Table XVI. AD V601LC Field and Block D elim iters (Codes)

Code Nam e

Code

D escription (Align all # D elim iter Codes to 32-Bit Boundaries) (Continued)

<BW>

(16 bits, 8.8)

T his data code is not entropy coded, is always 16 bits in length and defines the Bin

Width Quantizer control used on all data in the block sub-band. During decode, this

value is used by the Quantizer. If this value is set to zero during decode, all Huffman

data is presumed to be zero and is ignored, but must be included. During encode, this

value is calculated by the external H ost and is inserted into the bit stream by the

ADV601LC (this value is not used by the quantizer). Another value calculated by the

Host, 1/BW is actually used by the Quantizer during encode.

<HUFF_DATA> (Modulo 32)

T his data is the quantized and entropy coded block sub-band data. T he data’s length is

dependent on block size and entropy coding so it is therefore variable in length. T his

field is filled with 1s making it Modulo 32 bits in length. Any Huffman decode process

can be interrupted and reset by any unexpectedly received # delimiter following a bit

error or synchronization problem.

#EOS

0xffffffffc0ffffff

T he host sends the # EOS (End of Sequence) to the ADV601LC during decode after

the last field in a sequence to indicate that the field sequence is complete. T he

ADV601LC does not append this code to the end of encoded field sequences; it must

be added by the host.

Table XVII. Video D ata Bitstream for O ne Field In a Video Sequence¹

ffff ffff 4000 0000 0000 0000 0000 0000 0000 0000 8400 00ff df0d 8eff ffff ffff

8400 00ff df0c daff ffff ffff 8300 00ff 609f ffff ffff ffff 8300 00fe c5af ffff

ffff ffff 8300 00ff 609f ffff ffff ffff 8300 00fe c5af ffff ffff ffff 8300 00ff

609f ffff ffff ffff 8300 00fe c70f ffff ffff ffff 8300 00ff 609f ffff ffff ffff

8300 00fe c70f ffff ffff ffff 8300 00ff 609f ffff ffff ffff 8300 00fe c78f ffff

ffff ffff 8300 00ff 609f ffff ffff ffff 8300 00fe c78f ffff ffff ffff 8300 00ff

6894 3fff ffff ffff 811d 40f0 90ff ffff ffff ffff 8300 00ff 6894 3fff ffff ffff

811d 40f0 90ff ffff ffff ffff 8300 00ff 68aa bfff ffff ffff 8116 80f0 9bff ffff

ffff ffff 8300 00ff 68aa bfff ffff ffff 8116 80f0 9bff ffff ffff ffff 8300 00ff

6894 3fff ffff ffff 8116 80f0 9fff ffff ffff ffff 8300 00ff 6894 3fff ffff ffff

8116 80f0 9fff ffff ffff ffff 8300 00ff fe62 a2ff ffff ffff 8103 e6e9 d74d 75d7

5d75 d75a f8f9 74eb d7af 5ebd 7af5 ebf0 f8f8 f979 7979 7979 7979 79fd 5f5f c7e3

f1f8 fc7e 3f1f 8fc7 e5fa ff6f d5f6 7d9f 67d9 f67d 9f67 d9f6 7edf abec f87c 3e1f

0f87 c3e1 f0f8 fd9f 1f1f 2f2f 2f2f 2f2f 2f2f 2f1f 2ebd 7af5 ebd7 ae9d 74e9 a56d

6b5a d6b5 a2b0 d249 24a5 ce36 db6d b6db 6db7 c6fd fd3d 3d3d 3d3d 3d3d 3d3b 7a7b

fbfb fbfb fbfb fbfb fcfd bdfe dfb7 edfb 7eef bbee fbbe dfbb dbe7 f6fd ff7f dff7

fdff 7fdf f7fd feff 3fbb effb feff bfef fbfe ffbf efff ffff ffff ffff 8300 00ff

fe62 a2ff ffff ffff 8103 e6fd bfab f9bf 57d5 f2eb 18f4 f9fd ffb7 f5ff 3feb fafc

7431 e9f4 fbff 77eb fd3f b3ec f2d5 efeb f6fe 1fbb f67e afdb f0f3 aaed edf7 fe3f

57ed fd7f bbe3 d2d3 dfe7 f87e 5f57 eefd 9fbb e5d6 2fdf e7f8 7eff abf7 7ecf ddf2

eb17 eff3 fc3f 7fd5 fbbf 67ee f975 8bf7 f9fe 1fbf eafd dfb3 f77c bac5 fbfc ff0f

dff5 7eef d9fb be5d 62fd fe7f 87ef fabf 77ec fddf 2eb1 7eff 3fc3 f7fd 5fbb f67e

ef97 58bf 7f9f e1fb feaf ddfb 3f77 cbac 5fbf cff0 fdff 57ee fd9f bbe5 d62f dfe7

f87e ffaf f77e cfab e5d6 2fe9 f3fc 7f7f d9f5 7edf abc7 431e 9f4f c7f8 7fff ffff

ffff ffff 8400 00ff dfb7 c5ff df0d 7fff ffff ffff 8202 9afc 3eff b7e9 ede9 e9e9

e9e9 e9e9 e9e9 e9e9 e9e9 e9e9 e9e9 dbef fbbe 9efe 9dbb 76ed dbb7 6edd bb76 eddb

b76e ddb7 fbbe df9f af6d b6db 6db6 db6d b6db 6db6 db6d aff6 fd3d bbed 7bde f7bd

ef7b def7 bdef 75f4 f7f4 dee9 2492 4924 924c fa7b 77da 6991 f4f7 efb4 d323 e9ed

df69 a647 d3db bed3 4c8f a7b7 7da6 991f 4f7e fb4d 323e 9edd f69a 647d 3dbb ed34

c8fa 7b77 da69 647c fd7b 6100 0000 0045 bdfd 37bb 8888 8888 8888 8888 8aff ffff

ffff ffff 8400 00ff c9a7 1fff ffff ffff 820f 00ff 7704 4fff ffff ffff 8400 00ff

c9a7 1fff ffff ffff 820f 00ff 7704 bfff ffff ffff 8400 00ff c9a7 1fff ffff ffff

8213 80ff 7703 5fff ffff ffff 8200 00ff 7743 1fff ffff ffff 8200 00ff 7743 1fff

ffff ffff 8200 00ff 7745 efff ffff ffff 8400 00ff df0c daff

NOT E

¹T his table shows ADV601LC compressed data for one field in a color ramp video sequence. T he SOF# and SOB# codes in the data are in bold text.

that can occur is loss of a complete block of Huffman data. With

the ADV601LC, this type of error results only in some blurring

of the decoded image, not complete loss of the image.

Bit Er r or Toler a nce

Bit error tolerance is ensured because a bit error within a

Huffman coded stream does not cause # delimiter symbols to be

misread by the ADV601LC in decode mode. T he worst error

REV. 0

–27–

ADV601LC

Using the AD V601LC in Com puter Applications

Many key features of the ADV601LC were driven by the demand-

ing cost and performance requirements of computer applications.

T he following ADV601LC features provide key advantages in

computer applications:

AP P LYING TH E AD V601LC

T his section includes the following topics:

• Using the ADV601LC in computer applications

• Using the ADV601LC in standalone applications

• Configuring the host interface for 6- or 32-bit data paths

• Connecting the video interface to popular video encoders and

decoders

• Host Interface

T he 512 double word FIFO provides necessary buffering of

compressed digital video to deal with PCI bus latency.

• Getting the most out of the ADV601LC

• Low Cost External DRAM

T he following Analog Devices products should be considered in

ADV601LC designs:

Unlike many other real-time compression solutions, the

ADV601LC does not require expensive external SRAM

transform buffers or VRAM frame stores.

• ADV7175/ADV7176—Digital YUV to analog composite

video encoder

• AD722—Analog RGB to analog composite video encoder

• AD1843—Audio codec with embedded video synchronization

• ADSP-21xx—Family of fixed-point digital signal processors

• AD8xxx—Family of video operational amplifiers

A0–A8

ADR0

ADR1

A2

A3

DQ1–DQ16

RAS

D0–D15

RAS

D0–D7

D8–D15

DQ0–DQ7

CAS

DQ8–DQ15

DQ16–DQ23

DQ24–DQ31

OE

DRAM

D16–D23

D24–D31

(256K

؋

16-BIT)

WE

WEL

WEH

BE0–BE1

BE2–BE3

HOST BUS

TOSHIBA TC514265DJ/DZ/DFT-60

NEC

␮PD424210ALE-60

␮PD42S4210ALE-60

1

DECODE

ADV601LC

HITACHI HM514265CJ-60

A28

A29

A30

A31

ANY DRAM USED WITH THE ADV601LC

MUST MEET THE MINIMUM SPECIFICATIONS

OUTLINED FOR THE HYPER MODE DRAMS

LISTED

CS

VCLKO

24.576MHz

XTAL

RD

WR

2

DECODE

XTAL

STATS_R

HIRQ

27MHz PAL OR NTSC

LLC

VCLK

LCODE

NOTE:

DECODE ASSERTS CS

SAA7111

1

~

ON THE

ACK

ADV601LC FOR HOST ADDRESSES

0X4000,0000 THROUGH

0X4000,0013

Y[0–7]

VDATA [0–7]

FIFO_SRQ

FIFO_ERR

FIFO_STP

2

DECODE IS HOST SPECIFIC

COMPOSITE VIDEO INPUT

Figure 13. A Suggested PC Application Design

REV. 0

–28–

ADV601LC

A0–A8

DQ1–DQ16

RAS

ADR0

ADR1

ADR2

A0–A8

D0–D15

RAS

DATA0–7

DATA8-15

DQ0–DQ7

CAS

DQ8–DQ15

DQ16–DQ23

DQ24–DQ31

DRAM

OE

(256K

؋

16-BIT)

WE

WEL

WEH

ADR0

BE0–BE1

BE2–BE3

TOSHIBA TC514265DJ/DZ/DFT-60

ADSP-21csp01

NEC

␮PD424210ALE-60

␮PD42S4210ALE-60

ADV601LC

HITACHI HM514265CJ-60

VCLKO*

CLKIN

ANY DRAM USED WITH THE ADV601LC

MUST MEET THE MINIMUM SPECIFICATIONS

OUTLINED FOR THE HYPER MODE DRAMS

LISTED

IOMS

RD

CS

RD

WR

FIFO_ERR

STATS_R

HIRQ

FLIN2

24.576MHz

XTAL

FLIN0

IRQ0

XTAL

LCODE

FLIN1

IOACK

27MHz PAL OR NTSC

LLC

ACK

VCLK

SAA7111

THE ADSP-21csp01 INTERNAL CLOCK RATE

DOUBLE THE INPUT CLOCK

Y[0–7]

VDATA [0–7]

FIFO_SRQ

FIFO_STP

*THE INPUT CLOCK RATE = 1/2 OF THE INTERNAL

CLOCK RATE, RANGING FROM 12 TO 21MHz

COMPOSITE VIDEO INPUT

Figure 14. Alternate Standalone Application Design

XTAL

XTAL VCLK

Using the AD V601LC In Standalone Applications

10k⍀

150⍀

Figure 14 shows the ADV601LC in a noncomputer based appli-

cations. Here, an ADSP-21csp01 digital signal processor pro-

vides Host control and BW calculation services. Note that all

control and BW operations occur over the host interface in this

design.

BLANK

CLOCK

P7–P0

ALSB

VCLKO

VDATA (7:0)

ADV7175

ADV601LC

(MODE 0 & SLAVE MODE)

(CCIR-656 MODE)

Connecting the AD V601LC to P opular Video D ecoder s and

Encoder s

T he following circuits are recommendations only. Analog

Devices has not actually built or tested these circuits.

Figure 16. ADV601LC and ADV7175 Exam ple Interfac-

ing Block Diagram

Using the Ra ytheon TMC22173 Video Decoder

Using the Philips SAA7111 Video Decoder

T he SAA7111 example circuit, which appears in Figure 15, is

used in this configuration on the ADV601LC Video Lab dem-

onstration board.

Raytheon has a whole family of video parts. Any member of the

family can be used. T he user must select the part needed based

on the requirements of the application. Because the Raytheon

part does not include the A/Ds, an external A/D is necessary in

this design (or a pair of A/Ds for S video).

XTAL

T he part can be used in CCIR-656 (D1) mode for a zero con-

trol signal interface. Special attention must be paid to the video

output modes in order to get the right data to the right pins (see

the following diagram).

VCLK

LLC

SAA7111

ADV601LC

VDATA (0:7)

Y(0:7)

Note that the circuit in Figure 17 has not been built or tested.

(CCIR-656 MODE)

VCLK

XTAL

TMC22153

Figure 15. ADV601LC and SAA7111 Exam ple Interfac-

ing Block Diagram

VCLK

CLOCK

ADV601LC

Using the Ana log Devices ADV7175 Video Encoder

Y(2:9)

VDATA (0:7)

Because the ADV7175 has a CCIR-656 interface, it connects

directly with the ADV601LC without “glue” logic. Note that

the ADV7175 can only be used at CCIR-601 sampling rates.

MODE SET TO:

CDEC = 1

YUVT = 1

(CCIR656 & SLAVE MODE)

F422 = X

T he ADV7175 example circuit, which appears in Figure 16, is

used in this configuration on the ADV601LC Video Lab dem-

onstration board.

Figure 17. ADV601LC and TMC22153 Exam ple CCIR-656

Mode Interface

REV. 0

–29–

ADV601LC

GETTING TH E MO ST O UT O F AD V601LC

• Scale bit stream

T he unique sub-band block structure of luminance and color

components in the ADV601LC offers many unique application

benefits. Analog Devices will offer a Feature Software Library as

well as separate feature application documentation to help users

exploit these features. T he following section provides an over-

view of only some of the features and how they are achieved with

the ADV601LC. Please refer to Figures 2 and 3 as necessary.

T he compressed video bit stream was created with simple

parsing in mind. T his type of parsing means that a lower

resolution/lower bandwidth bit stream can be extracted with

little computational burden. Generally, this effect is accom-

plished by selecting a subset of lower frequency blocks. T his

technique is useful in applications where the same video

source material must be sent over a range of different commu-

nication pipes {i.e., ISDN (128 Kbps), T 1 (1.5 Mbps) or T 3

(45 Mbps)}.

H igher Com pr ession With Inter field Techniques

T he ADV601LC normally operates as a field-independent

codec. However, through use of the sub-bands it is possible to

use the ADV601LC with interfield techniques to achieve even

higher levels of compression. In such applications, each field is

not compressed separately, thus accessing the compressed bit

stream can only be done at specific points in time. T here are

two general ways this can be accomplished:

• Use software to encode

In this case, a host CPU could encode a smaller image size

and fill in high frequency blocks with zeros. Again, image

quality would depend on the performance of the host. T he

Bin Width may be set to zero, zeroing out the data in any

particular Mallat block.

• Subsampling high frequency blocks

P ar am etr ic Im age Filter ing

T he human visual system is more sensitive to interframe

motion of low frequency block than to motion in high fre-

quency blocks. T he host software driver of the ADV601LC

allows exploitation of this option to achieve higher com-

pression. Note that the compressed bit stream can only be

accessed at points where the high frequency blocks have just

been updated.

T he ADV601LC offers a unique set of image filtering capa-

bilities not found in other compression technologies. T he

ADV601LC quantizer is capable of attenuating any or all of the

luminance or chrominance blocks during encode or decode.

Here are some of the possible applications:

• Parametric softening of color saturation and contrast during encode

or decode

• Updating the image with motion detection

Trade off image softness for higher compression. Attenua-

tion of the higher frequency blocks during encode leads to

softer images, but it can lead to much higher compression

performance.

In applications where the video is likely to have no motion for

extended periods of time (video surveillance in a vacant build-

ing, for instance), it is only necessary to update the image

either periodically or when motion occurs. By using the wave-

let sub-bands to detect motion (see later in this section), it is

possible to achieve very high levels of compression when

motion is infrequent.

• Color saturation control

T his effect is achieved by controlling gain of low pass chromi-

nance blocks during encode or decode.

• Contrast control

T his effect is achieved by controlling the gain of the low fre-

quency luminance blocks during encode or decode.

Scalable Com pr ession Technology

T he ADV601LC offers many different options for scaling the

image, the compressed bit stream bandwidth and the processing

horsepower for encode or decode. Because the ADV601LC

employs decimators, interpolators and filters in the filter bank,

the scaling function creates much higher quality images than

achieved through pixel dropping. Mixing and matching the

many scaling options is useful in network applications where

transmission pipes may vary in available bit rate, and decode/

encode capabilities may be a mix of software and hardware.

T hese are the key options:

• Fade to black

T his effect achieved by attenuation of luminance blocks.

Mixing of Two or Mor e Im ages

Blocks from different images can be mixed into the bit stream

and then sent to the ADV601LC during decode. T he result is

high quality mixing of different images. T his also provides the

capability to fade from one image to the next.

Edge or Motion D etection

• Extract scaled images by factors of 2 from the compressed bit stream

T his is useful in video editing applications where thumbnail

sketches of fields need to be displayed. In this case, editing

software can quickly extract and decode the desired image.

T his technique eliminates the burden of decoding an entire

image and then scaling to the desired size.

In certain remote video surveillance and machine vision applica-

tions, it is desirable to detect edges or motion. Edges can be

quickly found through evaluation of the high frequency blocks.

Motion searches can be achieved in two ways:

• Evaluation of the smallest luminance block. Because the size

of the smallest block is so mcuh smaller than the others, the

computational burden is significantly less than doing an

evaluation over the entire image.

• Use software to decode bit stream

Decoding an entire CCIR-601 resolution image in real time at

50/60 fields per second does require the ADV601LC hard-

ware. Analog Devices provides a bit-exact ADV601LC

simulator that can decode a scaled image in real time or a full-

size image off-line. Image size and frame rates depend on the

performance of the host processor.

• Polling the Sum of Squares registers. Because large changes in

the video data create patterns, it is possible to detect motion

in the video by polling the Sum of Squares registers, looking

for patterns and changes.

REV. 0

–30–

ADV601LC

SPECIFICATIONS

T he ADV601LC Video Codec uses a Bi-Orthogonal (7, 9) Wavelet T ransform.

RECO MMEND ED O P ERATING CO ND ITIO NS

P aram eter

D escription

Min

Max

Unit

V_DD

T_AMB

Supply Voltage

Ambient Operating T emperature

4.50

0

5.50

+70

V

°C

ELECTRICAL CH ARACTERISTICS

P aram eter

D escription

Test Conditions

Min

Max

Unit

V_IH

V_IL

V_OH

V_OL

I_IH

Hi-Level Input Voltage

Lo-Level Input Voltage

Hi-level Output Voltage

Lo-Level Output Voltage

Hi-Level Input Current

Lo-Level Input Current

T hree-State Leakage Current

Input Pin Capacitance

@ V_DD= max

@ V_DD= min

@ V_DD= min, I_OH= –0.5 mA

@ V_DD= min, I_OL= 2 mA

@ V_DD= max, V_IN= V_DDmax

@ V_DD= max, V_IN= 0 V

@ V_DD= max, V_IN= V_DDmax

@ V_DD= max, V_IN= 0 V

2.0

N/A

2.4

N/A

0.8

N/A

0.4

10

8*

V

µA

pF

I_IL

I_OZH

I_OZL

C_I

@ V_IN= 2.5 V, f_IN= 1.0 MHz, T_AMB= 25°C

C_O

Output Pin Capacitance

8*

*Guaranteed but not tested.

ABSO LUTE MAXIMUM RATINGS*

P aram eter

D escription

Min

Max

Unit

V_DD

V_IN

V_OUT

T_AMB

T_S

Supply Voltage

Input Voltage

Output Voltage

Ambient Operating T emperature

Storage T emperature

–0.3

N/A

0

–65

N/A

+7

V

°C

V_DD± 0.3

+70

+150

+280

T_L

Lead T emperature (5 sec) LQFP

*Stresses greater than those listed above under Absolute Maximum Ratings may cause permanent damage to the device. T his is a stress rating only; functional opera-

tion of the device at these or any other conditions above those indicated in the Pin Definitions section of this specification is not implied. Exposure to maximum

rating conditions for extended periods may affect device reliability.

SUP P LY CURRENT AND P O WER

P aram eter

D escription

Test Conditions

Min

Max

Unit

I_DD

Supply Current (Dynamic)

Supply Current (Soft Reset)

Supply Current (Idle)

@ V_DD= max, t_VCLK

_

_CYC= 37 ns (at 27 MHz VCLK)

0.11

0.08

0.01

0.27

0.17

0.02

A

= 37 ns (at 27 MHz VCLK)

CYC

= None

CYC

ENVIRO NMENTAL CO ND ITIO NS

P aram eter

D escription

Max

Unit

θ_CA

θ_JA

θ_JC

Case-to-Ambient T hermal Resistance

Junction-to-Ambient T hermal Resistance

Junction-to-Case T hermal Resistance

30

35

5

°C/W

CAUTIO N

T he ADV601LC is an ESD (electrostatic discharge) sensitive device. Electrostatic charges readily

accumulate on the human body and equipment and can discharge without detection. Permanent

damage may occur to devices subjected to high energy electrostatic discharges. Proper ESD

precautions are strongly recommended to avoid functional damage or performance degradation.

WARNING!

ESD SENSITIVE DEVICE

T he ADV601LC latchup immunity has been demonstrated at ≥100 mA/–100 mA on all pins when

tested to industry standard/JEDEC methods.

REV. 0

–31–

ADV601LC

TEST CO ND ITIO NS

output reaches the high impedance state (also +1.5 V). Simi-

larly, these tests conditions consider an output as enabled when

the output leaves the high impedance state and begins driving a

measured high or low voltage. T ests measure output enable time

(t_ENABLE) as the time between the reference input signal crossing

+1.5 V and the time that the output reaches the measured high

or low voltage.

Figure 18 shows test condition voltage reference and device

loading information. T hese test conditions consider an output

as disabled when the output stops driving and goes from the

measured high or low voltage to a high impedance state. T ests

measure output disable time (t_DISABLE) as the time between the

reference input signal crossing +1.5 V and the time that the

DEVICE LOADING FOR AC MEASUREMENTS

INPUT & OUTPUT VOLTAGE/TIMING REFERENCES

1.5V

I

OL

V

IH

INPUT

REFERENCE

SIGNAL

V

IL

TO

OUTPUT

+1.5V

t_ENABLED

t_DISABLED

V

2pF

OH

OUTPUT

SIGNAL

1.5V

V

OL

I

OH

Figure 18. Test Condition Voltage Reference and Device Loading

TIMING P ARAMETERS

T his section contains signal timing information for the ADV601LC. T iming descriptions for the following items appear in this

section:

• Clock signal timing

• Video data transfer timing (CCIR-656, and Multiplexed Philips formats)

• Host data transfer timing (direct register read/write access)

Clock Signal Tim ing

T he diagram in this section shows timing for VCLK input and VCLKO output. All output values assume a maximum pin

loading of 50 pF.

Table XVIII. Video Clock P eriod, Frequency, D rift and Jitter

Min VCLK_CYC

P eriod

Nom inal VCLK_CYC

P eriod (Frequency)

Max VCLK_CYC

P eriod^{1, 2}

Video Form at

CCIR-601 PAL

CCIR-601 NT SC

35.2 ns

37 ns (27 MHz)

38.9 ns

NOT ES

¹VCLK Period Drift = ±0.1 (VCLK_CYC/field.

²VCLK edge-to-edge jitter = 1 ns.

Table XIX. Video Clock D uty Cycle

Min

Nom inal

Max

VCLK Duty Cycle¹

(40%)

(50%)

(60%)

NOT E

¹VCLK Duty Cycle = t_{VCLK_HI}/(t_{VCLK_LO}) × 100.

Table XX. Video Clock Tim ing P aram eters

P aram eter

D escription

Min

Max

Unit

t_{VCLK_CYC}

t_{VCLKO_D0}

t_{VCLKO_D1}

VCLK Signal, Cycle T ime (1/Frequency) at 27 MHz

VCLKO Signal, Delay (when VCLK2 = 0) at 27 MHz

VCLKO Signal, Delay (when VCLK2 = 1) at 27 MHz

(See Video Clock Period T able)

10

29

ns

REV. 0

–32–

ADV601LC

t_{VCLK_CYC}

(I) VCLK

(O) VCLKO

(VCLK2 = 0)

t_{VCLKO_D0}

(I) VCLKO

(VCLK2 = 1)

t_{VCLKO_D1}

NOTE:

USE VCLK FOR CLOCKING VIDEO-ENCODE OPERATIONS AND USE VCLKO FOR CLOCKING VIDEO-DECODE OPERATIONS.

DO NOT TRY TO USE EITHER CLOCK FOR BOTH ENCODE AND DECODE.

Figure 19. Video Clock Tim ing

CCIR-656 Video For m at Tim ing

T he diagrams in this section show transfer timing for pixel (YCrCb), line (horizontal), and frame (vertical) data in CCIR-656 video

mode. All output values assume a maximum pin loading of 50 pF. Note that in timing diagrams for CCIR-656 video, the label CTRL

indicates the VSYNC, HSYNC, and FIELD pins.

Table XXI. CCIR-656 Video—D ecode P ixel (YCr Cb) Tim ing P ar am eter s

P aram eter

D escription

Min

Max

Units

t_{VDAT A_DC_D}

t_{VDAT A_DC_OH}

t_{CT RL_DC_D}

VDAT A Signals, Decode CCIR-656 Mode, Delay

VDAT A Signals, Decode CCIR-656 Mode, Output Hold

CT RL Signals, Decode CCIR-656 Mode, Delay

CT RL Signals, Decode CCIR-656 Mode, Output Hold

N/A

4

N/A

5

14

N/A

11

ns

t_{CT RL_DC_OH}

N/A

(O) VCLKO

(O) VDATA

(O) CTRL

VALID

t_{VDATA_DC_OH}

t_{VDATA_DC_D}

VALID

t_{CTRL_DC_OH}

t_{CTRL_DC_D}

Figure 20. CCIR-656 Video—Decode Pixel (YCrCb) Transfer Tim ing

Table XXII. CCIR-656 Video—Encode P ixel (YCr Cb) Tim ing P ar am eter s

P aram eter

D escription

Min

Max

Units

t_{VDAT A_EC_S}

t_{VDAT A_EC_H}

t_{CT RL_EC_D}

t_{CT RL_EC_OH}

VDAT A Bus, Encode CCIR-656 Mode, Setup

VDAT A Bus, Encode CCIR-656 Mode, Hold

CT RL Signals, Encode CCIR-656 Mode, Delay

CT RL Signals, Encode CCIR-656 Mode, Output Hold

2

5

N/A

20

N/A

33

ns

N/A

(I) VCLK

(I) VDATA

(O) CTRL

VALID

t_{VDATA_EC_S}

t_{VDATA_EC_H}

ASSERTED

t_{CTRL_EC_OH}

t_{CTRL_EC_D}

Figure 21. CCIR-656 Video—Encode Pixel (YCrCb) Transfer Tim ing

REV. 0

–33–

ADV601LC

Figure 22. CCIR-656 Video—Line (Horizontal) and Fram e (Vertical) Transfer Tim ing

Note that for CCIR-656 Video—Decode and Master Line (Horizontal) timing, VDAT A is synchronous with VCLKO.

REV. 0

–34–

ADV601LC

Multiplexed P hilips Video Tim ing

T he diagrams in this section show transfer timing for pixel (YCrCb) data in Multiplexed Philips video mode. For line (horizontal)

and frame (vertical) data transfer timing, see Figure 25. All output values assume a maximum pin loading of 50 pF. Note that in

timing diagrams for Multiplexed Philips video, the label CT RL indicates the VSYNC, HSYNC and FIELD pins.

Table XXIII. Multiplexed P hilips Video—D ecode and Master P ixel (YCrCb) Tim ing P aram eters

P aram eter

D escription

Min

Max

Unit

t_{VDAT A_DMM_D}

t_{VDAT A_DMM_OH}

t_{CT RL_DMM_D}

VDAT A Bus, Decode Master Multiplexed Philips, Delay

VDAT A Bus, Decode Master Multiplexed Philips, Output Hold

CT RL Signals, Decode Master Multiplexed Philips, Delay

CT RL Signals, Decode Master Multiplexed Philips, Output Hold

N/A

4

N/A

5

14

N/A

11

ns

t_{CT RL_DMM_OH}

N/A

(O) VCLKO

(O) VDATA

(O) CTRL

VALID

t_{VDATA_DMM_OH}

t_{VDATA_DMM_D}

VALID

t_{CTRL_DMM_OH}

t_{CTRL_DMM_D}

Figure 23. Multiplexed Philips Video—Decode and Master Pixel (YCrCb) Transfer Tim ing

Table XXIV. Multiplexed P hilips Video—D ecode and Slave P ixel (YCrCb) Tim ing P aram eters

P aram eter

D escription

Min

Max

Unit

t_{VDAT A_DSM_D}

t_{VDAT A_DSM_OH}

t_{CT RL_DSM_S}

t_{CT RL_DSM_H}

VDAT A Bus, Decode Slave Multiplexed Philips, Delay

VDAT A Bus, Decode Slave Multiplexed Philips, Output Hold

CT RL Signals, Decode Slave Multiplexed Philips, Setup

CT RL Signals, Decode Slave Multiplexed Philips, Hold

N/A

4

16

42

14

ns

N/A

(O) VCLKO

(O) VDATA

(I) CTRL

VALID

t_{VDATA_DSM_OH}

t_{VDATA_DSM_D}

VALID

t_{CTRL_DSM_H}

t_{CTRL_DSM_S}

Figure 24. Multiplexed Philips Video—Decode and Slave Pixel (YCrCb) Transfer Tim ing

REV. 0

–35–

ADV601LC

Figure 25. Multiplexed Philips Video–Line (Horizontal) and Fram e (Vertical) Transfer Tim ing

REV. 0

–36–

ADV601LC

Table XXV. Multiplexed P hilips Video—Encode and Master P ixel (YCrCb) Tim ing P aram eters

P aram eter

D escription

Min

Max

Unit

t_{VDAT A_EMM_S}

t_{VDAT A_EMM_H}

t_{CT RL_EMM_D}

t_{CT RL_EMM_OH}

VDAT A Bus, Encode Master Multiplexed Philips, Setup

VDAT A Bus, Encode Master Multiplexed Philips, Hold

CT RL Signals, Encode Master Multiplexed Philips, Delay

CT RL Signals, Encode Master Multiplexed Philips, Output Hold

2

5

N/A

20

N/A

33

ns

N/A

(I) VCLK

VALID

t_{VDATA_EMM_S}

(I) VDATA

(O) CTRL

t_{VDATA_EMM_H}

ASSERTED

t_{CTRL_EMM_OH}

ASSERTED

t_{CTRL_EMM_D}

Figure 26. Multiplexed Philips Video—Encode and Master Pixel (YCrCb) Transfer Tim ing

Table XXVI. Multiplexed P hilips Video—Encode and Slave P ixel (YCrCb) Tim ing P aram eters

P aram eter

D escription

Min

Max

Unit

t_{VDAT A_ESM_S}

t_{VDAT A_ESM_H}

t_{CT RL_ESM_S}

t_{CT RL_ESM_H}

VDAT A Bus, Encode Slave Multiplexed Philips Mode, Setup

VDAT A Bus, Encode Slave Multiplexed Philips Mode, Hold

CT RL Signals, Encode Slave Multiplexed Philips Mode, Setup

CT RL Signals, Encode Slave Multiplexed Philips Mode, Hold

2

5

N/A

ns

(I) VCLK

(I) VDATA

(I) CTRL

VALID

t_{VDATA_ESM_S}

t_{VDATA_ESM_H}

ASSERTED

t_{CTRL_ESM_S}

t_{CTRL_ESM_H}

Figure 27. Multiplexed Philips Video—Encode and Slave Pixel (YCrCb) Transfer Tim ing

REV. 0

–37–

ADV601LC

H ost Inter face (Indir ect Addr ess, Indir ect Register D ata, and Inter r upt Mask/Status) Register Tim ing

T he diagrams in this section show transfer timing for host read and write accesses to all of the ADV601LC’s direct registers, except

the Compressed Data register. Accesses to the Indirect Address, Indirect Register Data, and Interrupt Mask/Status registers are

slower than access timing for the Compressed Data register. For information on access timing for the Compressed Data direct regis-

ter, see the Host Interface (Compressed Data) Register T iming section. Note that for accesses to the Indirect Address, Indirect Reg-

ister Data and Interrupt Mask/Status registers, your system MUST observe ACK and RD or WR assertion timing.

Table XXVII. H ost (Indirect Address, Indirect D ata, and Interrupt Mask/Status) Read Tim ing P aram eters

P aram eter

D escription

Min

Max

Unit

t_{RD_D_RDC}

t_{RD_D_PWA}

t_{RD_D_PWD}

t_{ADR_D_RDS}

t_{ADR_D_RDH}

t_{DAT A_D_RDD}

t_{DAT A_D_RDOH}

t_{RD_D_WRT}

RD Signal, Direct Register, Read Cycle T ime (at 27 MHz VCLK)

RD Signal, Direct Register, Pulsewidth Asserted (at 27 MHz VCLK)

RD Signal, Direct Register, Pulsewidth Deasserted (at 27 MHz VCLK)

ADR Bus, Direct Register, Read Setup

ADR Bus, Direct Register, Read Hold

DAT A Bus, Direct Register, Read Delay

DAT A Bus, Direct Register, Read Output Hold (at 27 MHz VCLK)

WR Signal, Direct Register, Read-to-Write Turnaround (at 27 MHz VCLK)

ACK Signal, Direct Register, Read Delayed (at 27 MHz VCLK)

ACK Signal, Direct Register, Read Output Hold (at 27 MHz VCLK)

N/A¹

5

2

N/A

ns

N/A

26

171.6^{2, 3}

N/A

48.7⁴

8.6

11

N/A

t_{ACK_D_RDD}

t_{ACK_D_RDOH}

287.1^{5, 6}

N/A

NOT ES

¹RD input must be asserted (low) until ACK is asserted (low).

²Maximum t_{DAT A_D_RDD}varies with VCLK according to the formula: t_{DAT A_D_RDD}

= 4 (VCLK Period) +16.

(MAX)

³During ST AT S_R deasserted (low) conditions, t_{DAT A_D_RDD}may be as long as 52 VCLK periods.

⁴Minimum t_{RD_D_WRT}varies with VCLK according to the formula: t_{RD_D_WRT}

⁵Maximum t_{ACK_D_RDD}varies with VCLK according to formula: t_{ACK_D_RDD}

= 1.5 (VCLK Period) –4.1.

= 7 (VCLK Period) +14.8.

(MIN)

(MAX)

⁶During ST AT S_R deasserted (low) conditions, t_{ACK_D_RDD}may be as long as 52 VCLK periods.

t_{RD_D_RDC}

(I) RD

t_{RD_D_PWD}

t_{RD_D_PWA}

VALID

(I) ADR, BE, CS

t_{ADR_D_RDS}

t_{ADR_D_RDH}

(O) DATA

VALID

t_{DATA_D_RDD}

t_{DATA_D_RDOH}

(I) WR

t_{RD_D_WRT}

(O) ACK

t_{ACK_D_RDD}

t_{ACK_D_RDOH}

Figure 28. Host (Indirect Address, Indirect Register Data, and Interrupt Mask/Status) Read Transfer Tim ing

REV. 0

–38–

ADV601LC

Table XXVIII. H ost (Indirect Address, Indirect D ata, and Interrupt Mask/Status) Write Tim ing P aram eters

P aram eter

D escription

Min

Max

Unit

t_{WR_D_WRC}

t_{WR_D_PWA}

t_{WR_D_PWD}

t_{ADR_D_WRS}

t_{ADR_D_WRH}

t_{DAT A_D_WRS}

t_{DAT A_D_WRH}

t_{WR_D_RDT}

WR Signal, Direct Register, Write Cycle T ime (at 27 MHz VCLK)

WR Signal, Direct Register, Pulsewidth Asserted (at 27 MHz VCLK)

WR Signal, Direct Register, Pulsewidth Deasserted (at 27 MHz VCLK)

ADR Bus, Direct Register, Write Setup

ADR Bus, Direct Register, Write Hold

DAT A Bus, Direct Register, Write Setup

N/A¹

5

2

N/A

ns

–10

0

DAT A Bus, Direct Register, Write Hold

WR Signal, Direct Register, Read Turnaround (After a Write) (at 27 MHz VCLK)

ACK Signal, Direct Register, Write Delay (at 27 MHz VCLK)

ACK Signal, Direct Register, Write Output Hold

35.6²

8.6

11

t_{ACK_D_WRD}

t_{ACK_D_WROH}

182.1^{3, 4}ns

N/A ns

NOT ES

¹WR input must be asserted (low) until ACK is asserted (low).

²Minimum t_{WR_D_RDT}varies with VCLK according to the formula: t_{WR_D_RDT}

= 0.8 (VCLK Period) +7.4.

= 4.3 (VCLK Period) +14.8.

(MIN)

³Maximum t_{WR_D_WRD}varies with VCLK according to the formula: t_{ACK_D_WRD}

(MAX)

⁴During ST AT S_R deasserted (low) conditions, t_{ACK_D_WRD}may be as long as 52 VCLK periods.

t_{WR_D_WRC}

(I) WR

t_{WR_D_PWD}

t_{WR_D_PWA}

VALID

(I) ADR, BE, CS

t_{ADR_D_WRS}

t_{ADR_D_WRH}

VALID

(I) DATA

t_{DATA_D_WRH}

t_{DATA_D_WRS}

(I) RD

t_{WR_D_RDT}

(O) ACK

t_{ACK_D_WRD}

t_{ACK_D_WROH}

Figure 29. Host (Indirect Address, Indirect Register Data, and Interrupt Mask/Status) Write Transfer Tim ing

REV. 0

–39–

ADV601LC

H ost Inter face (Com pr essed D ata) Register Tim ing

T he diagrams in this section show transfer timing for host read and write transfers to the ADV601LC’s Compressed Data register.

Accesses to the Compressed Data register are faster than access timing for the Indirect Address, Indirect Register Data, and Interrupt

Mask/Status registers. For information on access timing for the other registers, see the Host Interface (Indirect Address, Indirect

Register Data, and Interrupt Mask/Status) Register T iming section. Also note that as long as your system observes the RD or WR

signal assertion timing, your system does NOT have to wait for the ACK signal between new compressed data addresses.

Table XXIX. H ost (Com pressed D ata) Read Tim ing P aram eters

P aram eter

D escription

Min

Max

Unit

t_{RD_CD_RDC}

t_{RD_CD_PWA}

t_{RD_CD_PWD}

t_{ADR_CD_RDS}

t_{ADR_CD_RDH}

t_{DAT A_CD_RDD}

t_{DAT A_CD_RDOH}

t_{ACK_CD_RDD}

t_{ACK_CD_RDOH}

RD Signal, Compressed Data Direct Register, Read Cycle T ime

RD Signal, Compressed Data Direct Register, Pulsewidth Asserted

RD Signal, Compressed Data Direct Register, Pulsewidth Deasserted

ADR Bus, Compressed Data Direct Register, Read Setup

ADR Bus, Compressed Data Direct Register, Read Hold (at 27 MHz VCLK)

DAT A Bus, Compressed Data Direct Register, Read Delay

DAT A Bus, Compressed Data Direct Register, Read Output Hold

ACK Signal, Compressed Data Direct Register, Read Delay

ACK Signal, Compressed Data Direct Register, Read Output Hold

28

10

2

N/A

10

N/A

18

N/A

ns

2

N/A

18

N/A

9

t_{RD_CD_RDC}

(I) RD

t_{RD_CD_PWA}

t_{RD_CD_PWD}

(I) ADR, BE, CS

(O) DATA

VALID

t_{ADR_CD_RDS}

t_{ADR_CD_RDH}

VALID

t_{DATA_CD_RDOH}

t_{DATA_CD_RDD}

(O) ACK

t_{ACK_CD_RDOH}

t_{ACK_CD_RDD}

Figure 30. Host (Com pressed Data) Read Transfer Tim ing

REV. 0

–40–

ADV601LC

Table XXX. H ost (Com pressed D ata) Write Tim ing P aram eters

D escription

P aram eter

Min

Max

Unit

t_{WR_CD_WRC}

t_{WR_CD_PWA}

t_{WR_CD_PWD}

t_{ADR_CD_WRS}

t_{ADR_CD_WRH}

t_{DAT A_CD_WRS}

t_{DAT A_CD_WRH}

t_{ACK_CD_WRD}

t_{ACK_CD_WROH}

WR Signal, Compressed Data Direct Register, Write Cycle T ime

WR Signal, Compressed Data Direct Register, Pulsewidth Asserted

WR Signal, Compressed Data Direct Register, Pulsewidth Deasserted

ADR Bus, Compressed Data Direct Register, Write Setup

ADR Bus, Compressed Data Direct Register, Write Hold

DAT A Bus, Compressed Data Direct Register, Write Setup

DAT A Bus, Compressed Data Direct Register, Write Hold

ACK Signal, Compressed Data Direct Register, Write Delay

ACK Signal, Compressed Data Direct Register, Write Output Hold

28

10

2

N/A

9

N/A

19

ns

N/A

t_{WR_CD_WRC}

(I) WR

t_{WR_CD_PWA}

t_{WR_CD_PWD}

(I) ADR, BE, CS

VALID

t_{ADR_CD_WRS}

t_{ADR_CD_WRH}

(I) DATA

VALID

t_{DATA_CD_WRS}

t_{DATA_CD_WRH}

(O) ACK

t_{ACK_CD_WRD}

t_{ACK_CD_WROH}

Figure 31. Host (Com pressed Data) Write Transfer Tim ing

REV. 0

–41–

ADV601LC

P INO UTS

P in

Nam e

Type

P in

Nam e

Type

P in

Nam e

Type

1

2

3

4

5

6

7

8

DAT A4

DAT A3

DAT A2

DAT A1

DAT A0

VDD

GND

RD

WR

CS

ADR1

ADR0

GND

BE2–BE3

BE0–BE1

GND

RESET

VDD

ACK

I/O

POWER

GROUND

I

GROUND

I

GROUND

I

POWER

O

POWER

GROUND

O

POWER

GROUND

POWER

O

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

CAS

WE

VDD

O

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

VDAT A4

GND

VDD

VDAT A3

VDAT A2

VDAT A1

VDAT A0

NC*

I/O

GROUND

POWER

I/O

NC

GROUND

I/O

POWER

I/O

GROUND

I/O

POWER

I/O

DDAT 15

DDAT 14

DDAT 13

DDAT 12

DDAT 11

DDAT 10

DDAT 9

DDAT 8

DDAT 7

DDAT 6

DDAT 5

DDAT 4

DDAT 3

DDAT 2

DDAT 1

DDAT 0

GND

VDD

GND

NC

VDD

GND

ENC

VCLKO

VDD

XT AL

9

NC*

GND

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

DAT A31

DAT A30

DAT A29

DAT A28

DAT A27

DAT A26

DAT A25

DAT A24

DAT A23

DAT A22

DAT A21

DAT A20

VDD

97

98

99

VDD

GND

I/O

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

GROUND

POWER

GROUND

NC

I/O

GROUND

O

HIRQ

LCODE

FIFO_SRQ

ST AT S_R

VDD

GND

VDD

DADR8

DADR7

DADR6

DADR5

DADR4

DADR3

DADR2

DADR1

DADR0

GND

DAT A19

DAT A18

DAT A17

DAT A16

GND

O

POWER

I

GROUND

I OR O

GROUND

POWER

I/O

GND

DAT A15

DAT A14

DAT A13

DAT A12

DAT A11

DAT A10

DAT A9

DAT A8

DAT A7

DAT A6

DAT A5

VCLK

GND

FIELD

HSYNC

VSYNC

GND

VDD

I/O

O

VDAT A7

VDAT A6

VDAT A5

GROUND

O

I/O

RAS

*Apply a 10 kΩ pull-down resistor to this pin.

REV. 0

–42–

ADV601LC

P IN CO NFIGURATIO N

1

2

3

4

5

6

7

8

9

DATA4

DATA3

DATA2

DATA1

DATA0

VDD

90 GND

PIN 1

IDENTIFIER

89

88

87

86

NC*

VDATA0

VDATA1

85 VDATA2

GND

84

83

82

81

VDATA3

VDD

RD

WR

GND

CS 10

VDATA4

11

12

13

ADR1

ADR0

GND

80 VDATA5

79

78

77

76

VDATA6

VDATA7

VDD

BE2–BE3 14

BE0–BE1 15

ADV601LC

GND

TOP VIEW

(Not to Scale)

16

GND

75 VSYNC

RESET 17

74

73

HSYNC

FIELD

18

VDD

19

72 GND

71

ACK

20

VDD

VCLK

70 XTAL

21

22

23

24

25

26

27

28

29

30

GND

69

68

VDD

HIRQ

LCODE

FIFO_SRQ

STATS_R

VDD

VCLKO

67 ENC

66

GND

65 VDD

64

63

GND

NC

GND

62 VDD

61

VDD

DADR8

GND

*APPLY A 10k⍀ PULL DOWN RESISTOR TO THIS PIN

REV. 0

–43–

ADV601LC

O UTLINE D IMENSIO NS

D imensions shown in inches and (mm).

120-Lead LQFP

(ST-120)

0.638 (16.20)

0.630 (16.00) SQ

0.622 (15.80)

0.063 (1.60)

MAX

0.559 (14.20)

0.551 (14.00) SQ

0.543 (13.80)

0.030 (0.75)

0.025 (0.60)

0.018 (0.45)

120

1

91

90

SEATING

PLANE

0.457

(11.6)

BSC

SQ

TOP VIEW

(PINS DOWN)

SEATING

PLANE

0.003 (0.08)

MAX

61

60

30

31

0.057 (1.45)

0.055 (1.40)

0.053 (1.35)

0.006 (0.15)

0.002 (0.05)

7°

3.5°

0°

0.008 (0.20)

0.004 (0.09)

0.016 (0.40)

BSC

LEAD PITCH

0.009 (0.23)

0.007 (0.18)

0.005 (0.13)

LEAD WIDTH

*

* THE ACTUAL POSITION OF EACH LEAD IS WITHIN 0.003

(0.07) FROM ITS IDEAL POSITION WHEN MEASURED IN THE

LATERAL DIRECTION.

CENTER FIGURES ARE TYPICAL UNLESS OTHERWISE NOTED

O RD ERING GUID E

P art Num ber

Am bient Tem perature Range¹

0°C to +70°C

P ackage D escription

P ackage O ption²

ADV601LCJST

120-Lead LQFP

ST -120

NOT ES

¹J = Commercial temperature range (0°C to +70°C).

²ST = Plastic T hin Quad Flatpack.

REV. 0

–44–


型号：	ADV601LCJSTZRL
厂家：	ADI
描述：	Ultra Low Cost Video Codec 商用集成电路
文件：	总44页 (文件大小：600K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADV601LCJSTZRL [ADI]

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