ADV7123 [ADI]
CMOS, 240 MHz Triple 10-Bit High Speed Video DAC; CMOS ， 240 MHz的三路10位高速视频DAC
| 型号： | ADV7123 |
| 厂家： | 
ADI |
| 描述： | CMOS, 240 MHz Triple 10-Bit High Speed Video DAC |
| 文件： | 总20页 (文件大小：333K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CMOS, 330 MHz
Triple 10-Bit High Speed Video DAC
a
ADV7123
FEATURES
330 MSPS Throughput Rate
FUNCTIONAL BLOCK DIAGRAM
V
AA
Triple 10-Bit D/A Converters
SFDR
–70 dB at fCLK = 50 MHz; fOUT = 1 MHz
–53 dB at fCLK = 140 MHz; fOUT = 40 MHz
RS-343A/RS-170 Compatible Output
Complementary Outputs
DAC Output Current Range 2 mA to 26 mA
TTL Compatible Inputs
Internal Reference (1.23 V)
BLANK
SYNC
BLANK AND
SYNC LOGIC
IOR
DATA
R9–R0
10
10
10
10
10
10
DAC
DAC
DAC
REGISTER
IOR
IOG
DATA
REGISTER
G9–G0
B9–B0
IOG
Single-Supply 5 V/3.3 V Operation
48-Lead LQFP Package
IOB
DATA
REGISTER
IOB
Low Power Dissipation (30 mW Min @ 3 V)
Low Power Standby Mode (6 mW Typ @ 3 V)
Industrial Temperature Range (–40؇C to +85؇C)
VOLTAGE
REFERENCE
CIRCUIT
POWER-DOWN
MODE
PSAVE
V
REF
CLOCK
ADV7123
APPLICATIONS
Digital Video Systems (1600
؋
1200 @ 100 Hz) High Resolution Color Graphics
Digital Radio Modulation
Image Processing
R
COMP
GND
SET
Instrumentation
Video Signal Reconstruction
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
1. 330 MSPS throughput
The ADV7123 (ADV®) is a triple high speed, digital-to-analog
converter on a single monolithic chip. It consists of three
high speed, 10-bit, video D/A converters with complementary
outputs, a standard TTL input interface, and a high impedance,
analog output current source.
2. Guaranteed monotonic to 10 bits
3. Compatible with a wide variety of high resolution color
graphics systems, including RS-343A and RS-170
The ADV7123 has three separate 10-bit-wide input ports. A
single 5 V/3.3 V power supply and clock are all that are required
to make the part functional. The ADV7123 has additional video
control signals, composite SYNC and BLANK.
The ADV7123 also has a Power-Save Mode.
The ADV7123 is fabricated in a 5 V CMOS process. Its mono-
lithic CMOS construction ensures greater functionality with
lower power dissipation. The ADV7123 is available in a
48-lead LQFP package.
ADV is a registered trademark of Analog Devices, Inc.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© Analog Devices, Inc., 2002
ADV7123–SPECIFICATIONS
(VAA = 5 V ؎ 5%, VREF = 1.235 V, RSET = 560 ⍀, CL = 10 pF. All specifications TMIN to TMAX1, unless other-
wise noted, TJ MAX = 110؇C.)
5 V SPECIFICATIONS
Parameter
Min
Typ
Max
Unit
Test Conditions1
STATIC PERFORMANCE
Resolution (Each DAC)
Integral Nonlinearity (BSL)
Differential Nonlinearity
10
–1
–1
Bits
LSB
LSB
0.4
0.25
+1
+1
Guaranteed Monotonic
VIN = 0.0 V or VDD
DIGITAL AND CONTROL INPUTS
Input High Voltage, VIH
Input Low Voltage, VIL
Input Current, IIN
PSAVE Pull-Up Current
Input Capacitance, CIN
2
V
V
µA
µA
pF
0.8
+1
–1
20
10
ANALOG OUTPUTS
Output Current
2.0
2.0
26.5
18.5
5
mA
mA
%
V
kΩ
pF
Green DAC, Sync = High
RGB DAC, Sync = Low
DAC to DAC Matching
Output Compliance Range, VOC
Output Impedance, ROUT
Output Capacitance, COUT
Offset Error
1.0
0
1.4
100
10
IOUT = 0 mA
Tested with DAC Output = 0 V
FSR = 17.62 mA
–0.025
–5.0
+0.025
+5.0
% FSR
% FSR
Gain Error2
VOLTAGE REFERENCE (Ext. and Int.)
Reference Range, VREF
1.12
1.235
1.35
V
POWER DISSIPATION
Digital Supply Current3
3.4
10.5
18
67
8
9
mA
mA
mA
mA
mA
mA
fCLK = 50 MHz
fCLK = 140 MHz
15
25
72
f
CLK = 240 MHz
Analog Supply Current
Standby Supply Current4
RSET = 560 Ω
RSET = 4933 Ω
PSAVE = Low, Digital, and Control
Inputs at VDD
2.1
5.0
0.5
Power Supply Rejection Ratio
0.1
%/%
NOTES
1Temperature range TMIN to TMAX: –40°C to +85°C at 50 MHz and 140 MHz, 0°C to 70°C at 240 MHz and 330 MHz.
2Gain error = {(Measured (FSC)/Ideal (FSC) –1) × 100}, where Ideal = VREF /RSET × K × (3FFH) and K = 7.9896.
3Digital supply is measured with continuous clock with data input corresponding to a ramp pattern and with an input level at 0 V and V DD
4These maximum/minimum specifications are guaranteed by characterization to be over the 4.75 V to 5.25 V range.
.
Specifications subject to change without notice.
–2–
REV. B
ADV7123
(VAA = 3.0 V–3.6 V, VREF = 1.235 V, RSET = 560 ⍀, CL = 10 pF. All specifications TMIN to TMAX2, unless
3.3 V SPECIFICATIONS1 otherwise noted, TJ MAX = 110؇C.)
Parameter
Min
Typ
Max
Unit
Test Conditions2
STATIC PERFORMANCE
Resolution (Each DAC)
Integral Nonlinearity (BSL)
Differential Nonlinearity
10
+1
+1
Bits
LSB
LSB
RSET = 680 Ω
RSET = 680 Ω
RSET = 680 Ω
–1
–1
+0.5
+0.25
DIGITAL AND CONTROL INPUTS
Input High Voltage, VIH
Input Low Voltage, VIL
Input Current, IIN
PSAVE Pull-Up Current
Input Capacitance, CIN
2.0
–1
V
V
µA
µA
pF
0.8
+1
VIN = 0.0 V or VDD
20
10
ANALOG OUTPUTS
Output Current
2.0
2.0
26.5
18.5
mA
mA
%
V
kΩ
pF
Green DAC, Sync = High
RGB DAC, Sync = Low
DAC to DAC Matching
Output Compliance Range, VOC
Output Impedance, ROUT
Output Capacitance, COUT
Offset Error
1.0
0
1.4
0
70
10
0
% FSR
% FSR
Tested with DAC Output = 0 V
FSR = 17.62 mA
Gain Error3
0
VOLTAGE REFERENCE (Ext.)
Reference Range, VREF
1.12
1.235
1.235
1.35
V
V
VOLTAGE REFERENCE (Int.)
Reference Range, VREF
POWER DISSIPATION
Digital Supply Current4
2.2
6.5
11
16
67
8
5.0
12.0
15
mA
mA
mA
mA
mA
mA
mA
fCLK = 50 MHz
f
CLK = 140 MHz
fCLK = 240 MHz
CLK = 330 MHz
f
Analog Supply Current
Standby Supply Current
72
RSET = 560 Ω
RSET = 4933 Ω
PSAVE = Low, Digital, and Control
Inputs at VDD
2.1
5.0
0.5
Power Supply Rejection Ratio
0.1
%/%
NOTES
1These maximum/minimum specifications are guaranteed by characterization to be over the 3.0 V to 3.6 V range.
2Temperature range TMIN to TMAX: –40°C to +85°C at 50 MHz and 140 MHz, 0°C to 70°C at 240 MHz and 330 MHz.
3Gain error = {(Measured (FSC)/Ideal (FSC) –1) × 100}, where Ideal = VREF /RSET × K × (3FFH) and K = 7.9896.
4Digital supply is measured with continuous clock with data input corresponding to a ramp pattern and with an input level at 0 V and V DD
Specifications subject to change without notice.
.
REV. B
–3–
ADV7123
(VAA = 5 V ؎ 5%1, VREF = 1.235 V, RSET = 560 ⍀, CL = 10 pF. All specifications are
TA = 25؇C, unless otherwise noted, TJ MAX = 110؇C.)
5 V DYNAMIC SPECIFICATIONS1
Parameter
Min
Typ
Max
Unit
AC LINEARITY
Spurious-Free Dynamic Range to Nyquist2
Single-Ended Output
fCLK = 50 MHz; fOUT = 1.00 MHz
fCLK = 50 MHz; fOUT = 2.51 MHz
67
67
63
55
62
60
54
48
57
58
52
41
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
f
CLK = 50 MHz; fOUT = 5.04 MHz
fCLK = 50 MHz; fOUT = 20.2 MHz
fCLK = 100 MHz; fOUT = 2.51 MHz
f
CLK = 100 MHz; fOUT = 5.04 MHz
fCLK = 100 MHz; fOUT = 20.2 MHz
fCLK = 100 MHz; fOUT = 40.4 MHz
f
CLK = 140 MHz; fOUT = 2.51 MHz
fCLK = 140 MHz; fOUT = 5.04 MHz
fCLK = 140 MHz; fOUT = 20.2 MHz
f
CLK = 140 MHz; fOUT = 40.4 MHz
Double-Ended Output
fCLK = 50 MHz; fOUT = 1.00 MHz
70
70
65
54
67
63
58
52
62
61
55
53
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
f
f
CLK = 50 MHz; fOUT = 2.51 MHz
CLK = 50 MHz; fOUT = 5.04 MHz
fCLK = 50 MHz; fOUT = 20.2 MHz
f
f
CLK = 100 MHz; fOUT = 2.51 MHz
CLK = 100 MHz; fOUT = 5.04 MHz
fCLK = 100 MHz; fOUT = 20.2 MHz
f
f
CLK = 100 MHz; fOUT = 40.4 MHz
CLK = 140 MHz; fOUT = 2.51 MHz
fCLK = 140 MHz; fOUT = 5.04 MHz
f
f
CLK = 140 MHz; fOUT = 20.2 MHz
CLK = 140 MHz; fOUT = 40.4 MHz
Spurious-Free Dynamic Range within a Window
Single-Ended Output
fCLK = 50 MHz; fOUT = 1.00 MHz; 1 MHz Span
fCLK = 50 MHz; fOUT = 5.04 MHz; 2 MHz Span
77
73
64
dBc
dBc
dBc
f
CLK = 140 MHz; fOUT = 5.04 MHz; 4 MHz Span
Double-Ended Output
fCLK = 50 MHz; fOUT = 1.00 MHz; 1 MHz Span
74
73
60
dBc
dBc
dBc
f
f
CLK = 50 MHz; fOUT = 5.00 MHz; 2 MHz Span
CLK = 140 MHz; fOUT = 5.00 MHz; 4 MHz Span
Total Harmonic Distortion
fCLK = 50 MHz; fOUT = 1.00 MHz
TA = 25°C
66
65
64
63
55
dBc
dBc
dBc
dBc
dBc
TMIN to TMAX
f
f
CLK = 50 MHz; fOUT = 2.00 MHz
CLK = 100 MHz; fOUT = 2.00 MHz
fCLK = 140 MHz; fOUT = 2.00 MHz
DAC PERFORMANCE
Glitch Impulse
10
23
22
33
pVs
dB
dB
dB
DAC Crosstalk3
Data Feedthrough4, 5
Clock Feedthrough4, 5
NOTES
1These maximum/minimum specifications are guaranteed by characterization over the 4.75 V to 5.25 V range.
2Note that the ADV7123 exhibits high performance when operating with an internal voltage reference, VREF
.
3DAC to DAC Crosstalk is measured by holding one DAC high while the other two are making low to high and high to low transitions.
4Clock and data feedthrough is a function of the amount of overshoot and undershoot on the digital inputs. Glitch impulse includes clock and data feedthrough.
5TTL input values are 0 V to 3 V, with input rise/fall times of –3 ns, measured from the 10% and 90% points. Timing reference points are 50% for inputs and outputs.
Specifications subject to change without notice.
–4–
REV. B
ADV7123
(VAA = 3.0 V–3.6 V1, VREF = 1.235 V, RSET = 680 ⍀, CL = 10 pF. All specifications are
TA = 25؇C, unless otherwise noted, TJ MAX = 110؇C.)
3.3 V DYNAMIC SPECIFICATIONS
Parameter
Min
Typ
Max
Unit
AC LINEARITY
Spurious-Free Dynamic Range to Nyquist2
Single-Ended Output
fCLK = 50 MHz; fOUT = 1.00 MHz
67
67
63
55
62
60
54
48
57
58
52
41
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
f
CLK = 50 MHz; fOUT = 2.51 MHz
fCLK = 50 MHz; fOUT = 5.04 MHz
fCLK = 50 MHz; fOUT = 20.2 MHz
f
CLK = 100 MHz; fOUT = 2.51 MHz
fCLK = 100 MHz; fOUT = 5.04 MHz
fCLK = 100 MHz; fOUT = 20.2 MHz
f
CLK = 100 MHz; fOUT = 40.4 MHz
fCLK = 140 MHz; fOUT = 2.51 MHz
fCLK = 140 MHz; fOUT = 5.04 MHz
f
CLK = 140 MHz; fOUT = 20.2 MHz
fCLK = 140 MHz; fOUT = 40.4 MHz
Double-Ended Output
fCLK = 50 MHz; fOUT = 1.00 MHz
70
70
65
54
67
63
58
52
62
61
55
53
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
f
CLK = 50 MHz; fOUT = 2.51 MHz
fCLK = 50 MHz; fOUT = 5.04 MHz
f
f
CLK = 50 MHz; fOUT = 20.2 MHz
CLK = 100 MHz; fOUT = 2.51 MHz
fCLK = 100 MHz; fOUT = 5.04 MHz
f
f
CLK = 100 MHz; fOUT = 20.2 MHz
CLK = 100 MHz; fOUT = 40.4 MHz
fCLK = 140 MHz; fOUT = 2.51 MHz
f
f
CLK = 140 MHz; fOUT = 5.04 MHz
CLK = 140 MHz; fOUT = 20.2 MHz
fCLK = 140 MHz; fOUT = 40.4 MHz
Spurious-Free Dynamic Range within a Window
Single-Ended Output
fCLK = 50 MHz; fOUT = 1.00 MHz; 1 MHz Span
77
73
64
dBc
dBc
dBc
f
f
CLK = 50 MHz; fOUT = 5.04 MHz; 2 MHz Span
CLK = 140 MHz; fOUT = 5.04 MHz; 4 MHz Span
Double-Ended Output
fCLK = 50 MHz; fOUT = 1.00 MHz; 1 MHz Span
74
73
60
dBc
dBc
dBc
f
CLK = 50 MHz; fOUT = 5.00 MHz; 2 MHz Span
fCLK = 140 MHz; fOUT = 5.00 MHz; 4 MHz Span
Total Harmonic Distortion
f
CLK = 50 MHz; fOUT = 1.00 MHz
TA = 25°C
66
65
64
64
55
dBc
dBc
dBc
dBc
dBc
TMIN to TMAX
f
CLK = 50 MHz; fOUT = 2.00 MHz
fCLK = 100 MHz; fOUT = 2.00 MHz
fCLK = 140 MHz; fOUT = 2.00 MHz
DAC PERFORMANCE
Glitch Impulse
10
23
22
33
pVs
dB
dB
dB
DAC Crosstalk3
Data Feedthrough4, 5
Clock Feedthrough4, 5
NOTES
1These maximum/minimum specifications are guaranteed by characterization over the 3.0 V to 3.6 V range.
2Note that the ADV7123 exhibits high performance when operating with an internal voltage reference, VREF
.
3DAC to DAC Crosstalk is measured by holding one DAC high while the other two are making low to high and high to low transitions.
4Clock and data feedthrough is a function of the amount of overshoot and undershoot on the digital inputs. Glitch impulse includes clock and data feedthrough.
5TTL input values are 0 V to 3 V, with input rise/fall times of –3 ns, measured at the 10% and 90% points. Timing reference points are 50% for inputs and outputs.
Specifications subject to change without notice.
REV. B
–5–
ADV7123
(VAA = 5 V ؎ 5%2, VREF = 1.235 V, RSET = 560 ⍀, CL = 10 pF. All specifications TMIN to TMAX
,
3
5 V TIMING SPECIFICATIONS1 unless otherwise noted, TJ MAX = 110؇C.)
Parameter
Min
Typ
Max
Unit
Condition
ANALOG OUTPUTS
Analog Output Delay, t6
Analog Output Rise/Fall Time, t7
5.5
1.0
15
1
ns
ns
ns
ns
4
5
Analog Output Transition Time, t8
6
Analog Output Skew, t9
2
CLOCK CONTROL
7
fCLK
fCLK
fCLK
0.5
0.5
0.5
50
140
240
MHz
MHz
MHz
50 MHz Grade
140 MHz Grade
240 MHz Grade
7
7
Data and Control Setup, t1
Data and Control Hold, t2
Clock Pulsewidth High, t4
Clock Pulsewidth Low t5
Clock Pulsewidth High t4
Clock Pulsewidth Low t5
Clock Pulsewidth High t4
Clock Pulsewidth Low t5
0.5
1.5
1.875
1.875
2.85
2.85
8.0
ns
ns
ns
ns
ns
ns
ns
ns
fCLK
fCLK
fCLK
fCLK
fCLK
fCLK
_
_
_
_
_
_
MAX = 240 MHz
MAX = 240 MHz
MAX = 140 MHz
MAX = 140 MHz
MAX = 50 MHz
MAX = 50 MHz
8.0
1.0
6
Pipeline Delay, tPD
1.0
2
1.0
10
Clock Cycles
ns
6
PSAVE Up Time, t10
NOTES
1Timing specifications are measured with input levels of 3.0 V (VIH) and 0 V (VIL) 0 for both 5 V and 3.3 V supplies.
2These maximum and minimum specifications are guaranteed over this range.
3Temperature range: TMIN to TMAX: –40°C to +85°C at 50 MHz and 140 MHz, 0°C to 70°C at 240 MHz.
4Rise time was measured from the 10% to 90% point of zero to full-scale transition, fall time from the 90% to 10% point of a full-scale transition.
5Measured from 50% point of full-scale transition to 2% of final value.
6Guaranteed by characterization.
7fCLK max specification production tested at 125 MHz; 5 V limits specified here are guaranteed by characterization.
Specifications subject to change without notice.
–6–
REV. B
ADV7123
(VAA = 3.0 V–3.6 V2, VREF = 1.235 V, RSET = 560 ⍀, CL = 10 pF. All specifications TMIN to
3.3 V TIMING SPECIFICATIONS1
TMAX3, unless otherwise noted, TJ MAX = 110؇C.)
Parameter
Min
Typ
Max
Unit
Condition
ANALOG OUTPUTS
Analog Output Delay, t6
Analog Output Rise/Fall Time, t7
7.5
1.0
15
1
ns
ns
ns
ns
4
5
Analog Output Transition Time, t8
6
Analog Output Skew, t9
2
CLOCK CONTROL
7
fCLK
fCLK
fCLK
fCLK
50
MHz
MHz
MHz
MHz
50 MHz Grade
140 MHz Grade
240 MHz Grade
330 MHz Grade
7
140
240
330
7
7
Data and Control Setup, t1
0.2
1.5
1.4
1.4
ns
ns
ns
ns
Data and Control Hold, t2
6
Clock Pulsewidth High, t4
Clock Pulsewidth Low, t5
fCLK_MAX = 330 MHz
fCLK_MAX = 330 MHz
fCLK_MAX = 240 MHz
fCLK_MAX = 240 MHz
fCLK_MAX = 140 MHz
fCLK_MAX = 140 MHz
fCLK_MAX = 50 MHz
fCLK_MAX = 50 MHz
6
Clock Pulsewidth High, t4
Clock Pulsewidth Low t5
Clock Pulsewidth High t4
Clock Pulsewidth Low t5
Clock Pulsewidth High t4
Clock Pulsewidth Low t5
1.875
1.875
2.85
2.85
8.0
ns
ns
ns
ns
ns
ns
8.0
1.0
6
Pipeline Delay, tPD
1.0
4
1.0
10
Clock Cycles
ns
6
PSAVE Up Time, t10
NOTES
1Timing specifications are measured with input levels of 3.0 V (VIH) and 0 V (VIL) 0 for both 5 V and 3.3 V supplies.
2These maximum and minimum specifications are guaranteed over this range.
3Temperature range: TMIN to TMAX: –40°C to +85°C at 50 MHz and 140 MHz, 0°C to 70°C at 240 MHz and 330 MHz.
4Rise time was measured from the 10% to 90% point of zero to full-scale transition, fall time from the 90% to 10% point of a full-scale transition.
5Measured from 50% point of full-scale transition to 2% of final value.
6Guaranteed by characterization.
7fCLK max specification production tested at 125 MHz; 5 V limits specified here are guaranteed by characterization.
Specifications subject to change without notice.
t3
t4
t5
CLOCK
t2
DIGITAL INPUTS
(R9–R0, G9–G0, B9–B0,
SYNC, BLANK)
DATA
t1
t8
t6
ANALOG OUTPUTS
(IOR, IOR, IOG, IOG, IOB, IOB)
t7
NOTES
1. OUTPUT DELAY (t6) MEASURED FROM THE 50% POINT OF THE RISING EDGE OF CLOCK
TO THE 50% POINT OF FULL-SCALE TRANSITION.
2. OUTPUT RISE/FALL TIME (t7) MEASURED BETWEEN THE 10% AND 90% POINTS OF FULL-SCALE TRANSITION.
3. TRANSITION TIME (t8) MEASURED FROM THE 50% POINT OF FULL-SCALE TRANSITION
TO WITHIN 2% OF THE FINAL OUTPUT VALUE.
Figure 1. Timing Diagram
REV. B
–7–
ADV7123
ABSOLUTE MAXIMUM RATINGS1
NOTES
1Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.
VAA to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Voltage on any Digital Pin . . . . . GND – 0.5 V to VAA + 0.5 V
Ambient Operating Temperature (TA) . . . . . –40°C to +85°C
Storage Temperature (TS) . . . . . . . . . . . . . . –65°C to +150°C
Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . . 150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . 300°C
Vapor Phase Soldering (1 Minute) . . . . . . . . . . . . . . . . 220°C
IOUT to GND2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to VAA
2Analog Output Short Circuit to any Power Supply or Common can be of an
indefinite duration.
ORDERING GUIDE
Speed Options
50 MHz1 140 MHz1
Package
240 MHz2
330 MHz2, 3
Plastic LQFP
(ST-48)
ADV7123KST50 ADV7123KST140 ADV7123JST240
ADV7123JST330
NOTES
1Specified for –40°C to +85°C operation.
2Specified for 0°C to 70°C operation.
3Available in 3.3 V version only.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADV7123 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
PIN CONFIGURATION
48 47 46 45 44 43 42 41 40 39 38 37
1
2
36
35
G0
G1
V
REF
PIN 1
IDENTIFIER
COMP
3
G2
34 IOR
4
33
32
31
30
29
28
27
26
25
G3
IOR
IOG
IOG
5
G4
ADV7123
TOP VIEW
(Not to Scale)
6
G5
7
G6
V
AA
8
G7
V
AA
9
G8
IOB
10
11
12
G9
IOB
BLANK
SYNC
GND
GND
13 14 15 16 17 18 19 20 21 22 23 24
–8–
REV. B
ADV7123
PIN FUNCTION DESCRIPTIONS
Pin No. Mnemonic
Function
1–10
G0–G9
R0, G0, and B0 are the least significant data bits. Unused pixel data inputs should be connected to
either the regular PCB power or ground plane.
11
BLANK
Composite Blank Control Input (TTL Compatible). A logic zero on this control input drives the analog
outputs, IOR, IOB, and IOG, to the blanking level. The BLANK signal is latched on the rising edge
of CLOCK. While BLANK is a logical zero, the R0–R9, G0–G9, and B0–B9 pixel inputs are ignored.
12
SYNC
Composite Sync Control Input (TTL Compatible). A logical zero on the SYNC input switches off a
40 IRE current source. This is internally connected to the IOG analog output. SYNC does not over-
ride any other control or data input; therefore, it should only be asserted during the blanking interval.
SYNC is latched on the rising edge of CLOCK.
If sync information is not required on the green channel, the SYNC input should be tied to logical zero.
13, 29, 30 VAA
Analog Power Supply (5 V 5%). All VAA pins on the ADV7123 must be connected.
14–23
B0–B9
R0, G0, and B0 are the least significant data bits. Unused pixel data inputs should be connected to
either the regular PCB power or ground plane.
24
CLOCK
Clock Input (TTL Compatible). The rising edge of CLOCK latches the R0–R9, G0–G9, B0–B9,
SYNC, and BLANK pixel and control inputs. It is typically the pixel clock rate of the video system.
CLOCK should be driven by a dedicated TTL buffer.
25, 26
GND
Ground. All GND pins must be connected.
27, 31, 33 IOB, IOG, IOR Differential Red, Green, and Blue Current Outputs (High Impedance Current Sources). These RGB
video outputs are specified to directly drive RS-343A and RS-170 video levels into a doubly terminated
75 Ω load. If the complementary outputs are not required, these outputs should be tied to ground.
28, 32, 34 IOB, IOG, IOR Red, Green, and Blue Current Outputs. These high impedance current sources are capable of directly
driving a doubly terminated 75 Ω coaxial cable. All three current outputs should have similar output
loads whether or not they are all being used.
35
COMP
Compensation Pin. This is a compensation pin for the internal reference amplifier. A 0.1 µF ceramic
capacitor must be connected between COMP and VAA
.
36
37
VREF
RSET
Voltage Reference Input for DACs or Voltage Reference Output (1.235 V)
A resistor (RSET) connected between this pin and GND controls the magnitude of the full-scale video
signal. Note that the IRE relationships are maintained, regardless of the full-scale output current. For
nominal video levels into a doubly terminated 75 Ω load, RSET = 530 Ω.
The relationship between RSET and the full-scale output current on IOG (assuming ISYNC is connected
to IOG) is given by:
RSET (Ω)
= 11,445 × VREF (V)/IOG (mA)
The relationship between RSET and the full-scale output current on IOR, IOG, and IOB is given by:
IOG (mA)
IOR, IOB (mA)
= 11,445 × VREF (V)/RSET (Ω) (SYNC being asserted)
= 7,989.6 × VREF (V)/RSET (Ω)
The equation for IOG will be the same as that for IOR and IOB when SYNC is not being used, i.e.,
SYNC tied permanently low.
38
PSAVE
Power Save Control Pin. Reduced power consumption is available on the ADV7123 when this pin is active.
39–48
R0–R9
Red, Green, and Blue Pixel Data Inputs (TTL Compatible). Pixel data is latched on the rising edge of
CLOCK.
REV. B
–9–
ADV7123
TERMINOLOGY
Raster Scan
Blanking Level
The most basic method of sweeping a CRT one line at a time to
generate and display images.
The level separating the SYNC portion from the video portion
of the waveform. Usually referred to as the front porch or back
porch. At 0 IRE units, it is the level that will shut off the picture
tube, resulting in the blackest possible picture.
Reference Black Level
The maximum negative polarity amplitude of the video signal.
Reference White Level
The maximum positive polarity amplitude of the video signal.
Color Video (RGB)
This usually refers to the technique of combining the three primary
colors of red, green, and blue to produce color pictures within
the usual spectrum. In RGB monitors, three DACs are required,
one for each color.
Sync Level
The peak level of the SYNC signal.
Video Signal
The portion of the composite video signal that varies in gray
scale levels between reference white and reference black. Also
referred to as the picture signal, this is the portion that may be
visually observed.
Sync Signal (SYNC)
The position of the composite video signal that synchronizes the
scanning process.
Gray Scale
The discrete levels of video signal between reference black and
reference white levels. A 10-bit DAC contains 1024 different
levels, while an 8-bit DAC contains 256.
–10–
REV. B
ADV7123
5 V–Typical Performance Characteristics
(VAA = 5 V, VREF = 1.235 V, IOUT = 17.62 mA, 50 ⍀ Doubly Terminated Load, Differential Output Loading, TA = 25؇C)
70
60
80
70
60
50
40
30
20
72.0
71.8
71.6
71.4
71.2
71.0
70.8
70.6
70.4
SFDR (DE)
SFDR (DE)
SFDR (SE)
50
40
30
20
SFDR (SE)
10
0
10
0
0.1
1
2.51
5.04
20.2
40.4
100
0.1
1
2.51
5.04
20.2
40.4
100
–10
+25
+85
f
– MHz
f
OUT
– MHz
OUT
TEMPERATURE – ؇C
TPC 1. SFDR vs. fOUT @ fCLOCK
140 MHz (Single-Ended and
Differential)
=
TPC 2. SFDR vs. fOUT @ fCLOCK
50 MHz (Single-Ended and Differential)
=
TPC 3. SFDR vs. Temperature @
f
CLOCK = 50 MHz (fOUT = 1 MHz)
76
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
1.00
0.50
SECOND
74
HARMONIC
0.75
72
70
68
66
THIRD
HARMONIC
FOURTH
HARMONIC
0.00
1023
–0.16
64
62
60
58
–0.50
–1.00
0
50
100
fCLOCK – MHz
140
160
0
2
17.62
– mA
20
CODE – INL
I
OUT
TPC 4. THD vs. fCLOCK @ fOUT = 2 MHz
(Second, Third, and Fourth Harmonics)
TPC 5. Linearity vs. IOUT
TPC 6. Typical Linearity (INL)
–5.0
–5.0
–45.0
–85.0
–5.0
–45.0
–85.0
–45.0
–85.0
0kHz
START
70.0MHz
STOP
35.0MHz
0kHz
START
35.0MHz
70.0MHz
STOP
35.0MHz
70.0MHz
STOP
0kHz
START
TPC 9. Dual-Tone SFDR @ fCLOCK
=
TPC 8. Single-Tone SFDR @ fCLOCK
140 MHz (fOUT1 = 20 MHz)
=
TPC 7. Single-Tone SFDR @ fCLOCK
140 MHz (fOUT = 2 MHz)
=
140 MHz (fOUT1 = 13.5 MHz, fOUT2
14.5 MHz)
=
REV. B
–11–
ADV7123
3 V–Typical Performance Characteristics
(VAA = 3 V, VREF = 1.235 V, IOUT = 17.62 mA, 50 ⍀ Doubly Terminated Load, Differential Output Loading, TA = 25؇C)
80
70
60
50
40
30
72.0
71.8
71.6
71.4
71.2
71.0
70.8
70.6
70.4
70
SFDR (DE)
SFDR (SE)
SFDR (DE)
60
SFDR (SE)
50
40
30
20
20
10
0
10
0
0.1
2.51
5.04
20.2
– MHz
40.4
100
0.1
1.0
2.51 5.04 20.2
– MHz
40.4
100
0
20
85
145
165
f
TEMPERATURE – ؇C
f
OUT
OUT
TPC 10. SFDR vs. fOUT @ fCLOCK
140 MHz (Single-Ended and
Differential)
=
TPC 12. SFDR vs. Temperature @
CLOCK = 50 MHz, (fOUT = 1 MHz)
TPC 11. SFDR vs. fOUT @ fCLOCK
140 MHz (Single-Ended and
Differential)
=
f
76
1.00
0.50
0.00
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
SECOND HARMONIC
74
0.75
FOURTH
72
HARMONIC
70
THIRD HARMONIC
68
1023
66
64
62
–0.42
–0.50
–1.00
60
58
0.1
0
0
50
100
140
160
CODE – INL
0
2
17.62
– mA
20
FREQUENCY – MHz
I
OUT
TPC 13. THD vs. fCLOCK @ fOUT
2 MHz (Second, Third, and Fourth
Harmonics)
=
TPC 15. Typical Linearity
TPC 14. Linearity vs. IOUT
–5.0
–5.0
–45.0
–85.0
–5.0
–45.0
–85.0
–45.0
–85.0
0kHz
START
0kHz
START
35.0MHz
70.0MHz
STOP
0kHz
START
35.0MHz
70.0MHz
STOP
35.0MHz
70.0MHz
STOP
TPC 18. Dual-Tone SFDR @ fCLOCK
=
TPC 16. Single-Tone SFDR @
fCLOCK = 140 MHz (fOUT1 = 2 MHz)
TPC 17. Single-Tone SFDR @
CLOCK = 140 MHz (fOUT1 = 20 MHz)
140 MHz (fOUT1 = 13.5 MHz, fOUT2
14.5 MHz)
=
f
–12–
REV. B
ADV7123
CIRCUIT DESCRIPTION AND OPERATION
This is done by adding appropriately weighted current sources
to the analog outputs, as determined by the logic levels on the
BLANK and SYNC digital inputs. Figure 3 shows the analog
output, RGB video waveform of the ADV7123. The influence of
SYNC and BLANK on the analog video waveform is illustrated.
The ADV7123 contains three 10-bit D/A converters, with three
input channels, each containing a 10-bit register. Also integrated
on board the part is a reference amplifier. CRT control functions
BLANK and SYNC are integrated on board the ADV7123.
Digital Inputs
Table I details the resultant effect on the analog outputs of
Thirty bits of pixel data (color information) R0–R9, G0–G9,
and B0–B9 are latched into the device on the rising edge of each
clock cycle. This data is presented to the three 10-bit DACs and
then converted to three analog (RGB) output waveforms. See
Figure 2.
BLANK and SYNC.
All these digital inputs are specified to accept TTL logic levels.
Clock Input
The CLOCK input of the ADV7123 is typically the pixel clock
rate of the system. It is also known as the dot rate. The dot rate,
and thus the required CLOCK frequency, will be determined by
the on-screen resolution according to the following equation:
CLOCK
DIGITAL INPUTS
(R9–R0, G9–G0, B9–B0,
Dot Rate = (Horiz Res) × (Vert Res) × (Refresh Rate)/
(Retrace Factor)
DATA
SYNC, BLANK)
Horiz Res
Vert Res
= Number of Pixels/Line.
= Number of Lines/Frame.
ANALOG OUTPUTS
(IOR, IOG, IOB
IOR, IOG, IOB)
Refresh Rate
= Horizontal Scan Rate. This is the rate at
which the screen must be refreshed,
typically 60 Hz for a noninterlaced system
or 30 Hz for an interlaced system.
Figure 2. Video Data Input/Output
The ADV7123 has two additional control signals that are
latched to the analog video outputs in a similar fashion. BLANK
and SYNC are each latched on the rising edge of CLOCK to
maintain synchronization with the pixel data stream.
Retrace Factor
= Total Blank Time Factor. This takes into
account that the display is blanked for a
certain fraction of the total duration of
each frame (e.g., 0.8).
The BLANK and SYNC functions allow for the encoding of
these video synchronization signals onto the RGB video output.
RED, BLUE
GREEN
mA
mA
V
V
18.62
0.7
26.67
1.000
WHITE LEVEL
100 IRE
BLANK LEVEL
SYNC LEVEL
0
0
8.05
0.3
43 IRE
0
0
NOTES:
1. OUTPUTS CONNECTED TO A DOUBLY TERMINATED 75⍀ LOAD.
2. V = 1.235V, R = 530⍀.
REF SET
3. RS-343A LEVELS AND TOLERANCES ASSUMED ON ALL LEVELS.
Figure 3. RGB Video Output Waveform
Table I. Video Output Truth Table (RSET = 530 ⍀, RLOAD = 37.5 ⍀)
DAC
Input Data
Description
IOG (mA)
IOG (mA)
IOR/IOB
IOR/IOB
SYNC
BLANK
WHITE LEVEL
VIDEO
26.67
0
18.62
Video
Video
0
0
0
0
0
1
1
0
1
0
1
0
1
1
1
1
1
0
0
3FFH
Data
Data
000H
000H
xxxH
xxxH
Video + 8.05 18.62 – Video
18.62 – Video
18.62 – Video
18.62
18.62
18.62
VIDEO to BLANK
BLACK LEVEL
BLACK to BLANK
BLANK LEVEL
SYNC LEVEL
Video
8.05
0
8.05
0
18.62 – Video
18.62
18.62
18.62
18.62
18.62
REV. B
–13–
ADV7123
Therefore, if we have a graphics system with a 1024 × 1024
resolution, a noninterlaced 60 Hz refresh rate and a retrace
factor of 0.8, then:
Analog Outputs
The ADV7123 has three analog outputs, corresponding to the
red, green, and blue video signals.
Dot Rate = 1024 × 1024 × 60/0.8
The red, green, and blue analog outputs of the ADV7123 are
high impedance current sources. Each one of these three RGB
current outputs is capable of directly driving a 37.5 Ω load, such
as a doubly terminated 75 Ω coaxial cable. Figure 4a shows the
required configuration for each of the three RGB outputs con-
nected into a doubly terminated 75 Ω load. This arrangement
will develop RS-343A video output voltage levels across a
75 Ω monitor.
=
78.6 MHz
The required CLOCK frequency is thus 78.6 MHz.
All video data and control inputs are latched into the ADV7123
on the rising edge of CLOCK, as described in the Digital Inputs
section. It is recommended that the CLOCK input to the
ADV7123 be driven by a TTL buffer (e.g., 74F244).
Video Synchronization and Control
A suggested method of driving RS-170 video levels into a 75 Ω
monitor is shown in Figure 4b. The output current levels of the
DACs remain unchanged, but the source termination resistance,
ZS, on each of the three DACs is increased from 75 Ω to 150 Ω.
The ADV7123 has a single composite sync (SYNC) input con-
trol. Many graphics processors and CRT controllers have the
ability of generating horizontal sync (HSYNC), vertical sync
(VSYNC), and composite SYNC.
IOR, IOG, IOB
In a graphics system that does not automatically generate a
composite SYNC signal, the inclusion of some additional logic
circuitry will enable the generation of a composite SYNC signal.
Z
= 75⍀
O
DACs
(CABLE)
Z
= 75⍀
S
Z
= 75⍀
L
(SOURCE
TERMINATION)
(MONITOR)
The sync current is internally connected directly to the IOG
output, thus encoding video synchronization information onto
the green video channel. If it is not required to encode sync
information onto the ADV7123, the SYNC input should be tied
to logic low.
TERMINATION REPEATED THREE TIMES
FOR RED, GREEN, AND BLUE DACs
Figure 4a. Analog Output Termination for RS-343A
Reference Input
The ADV7123 contains an on-board voltage reference. The
VREF pin is normally terminated to VAA through a 0.1 µF capaci-
tor. Alternatively, the part could, if required, be overdriven by
an external 1.23 V reference (AD1580).
IOR, IOG, IOB
Z
= 75⍀
O
DACs
(CABLE)
Z
= 150⍀
(SOURCE
TERMINATION)
S
Z
= 75⍀
L
(MONITOR)
A resistance RSET connected between the RSET pin and GND
determines the amplitude of the output video level according to
Equations 1 and 2 for the ADV7123:
TERMINATION REPEATED THREE TIMES
FOR RED, GREEN, AND BLUE DACs
IOG* (mA) = 11,445 × VREF (V)/RSET (Ω)
(1)
Figure 4b. Analog Output Termination for RS-170
IOR, IOB (mA) = 7,989.6 × VREF (V)/RSET (Ω)
(2)
More detailed information regarding load terminations for vari-
ous output configurations, including RS-343A and RS-170, is
available in an Application Note entitled Video Formats &
Required Load Terminations available from Analog Devices, pub-
lication no. E1228–15–1/89.
*Applies to the ADV7123 only when SYNC is being used. If SYNC is not being
encoded onto the green channel, Equation 1 will be similar to Equation 2.
Using a variable value of RSET, as shown in Figure 4, allows for
accurate adjustment of the analog output video levels. Use of a
fixed 560 Ω RSET resistor yields the analog output levels as quoted
in the specification page. These values typically correspond to
the RS-343A video waveform values as shown in Figure 3.
Figure 3 shows the video waveforms associated with the three
RGB outputs driving the doubly terminated 75 Ω load of
Figure 4a. As well as the gray scale levels, Black Level to White
Level, the diagram also shows the contributions of SYNC and
BLANK for the ADV7123. These control inputs add appropri-
ately weighted currents to the analog outputs, producing the specific
output level requirements for video applications. Table I details how
the SYNC and BLANK inputs modify the output levels.
D/A Converters
The ADV7123 contains three matched 10-bit D/A converters.
The DACs are designed using an advanced, high speed, seg-
mented architecture. The bit currents corresponding to each
digital input are routed to either the analog output (bit = “1”) or
GND (bit = “0”) by a sophisticated decoding scheme. As all this
circuitry is on one monolithic device, matching between the
three DACs is optimized. As well as matching, the use of identi-
cal current sources in a monolithic design guarantees monoto-
nicity and low glitch. The on-board operational amplifier stabilizes
the full-scale output current against temperature and power
supply variations.
Gray Scale Operation
The ADV7123 can be used for stand-alone, gray scale (mono-
chrome), or composite video applications (i.e., only one channel
used for video information). Any one of the three channels,
RED, GREEN, or BLUE, can be used to input the digital video
data. The two unused video data channels should be tied to
logical zero. The unused analog outputs should be terminated
with the same load as that for the used channel. In other words,
if the red channel is used and IOR is terminated with a doubly
terminated 75 Ω load (37.5 Ω), IOB and IOG should be termi-
nated with 37.5 Ω resistors. See Figure 5.
–14–
REV. B
ADV7123
Ground Planes
DOUBLY
TERMINATED
75⍀ LOAD
VIDEO
INPUT
R0
R9
The ADV7123, and associated analog circuitry, should have a
separate ground plane referred to as the analog ground plane.
This ground plane should connect to the regular PCB ground
plane at a single point through a ferrite bead, as illustrated in
Figure 7. This bead should be located as close as possible
(within three inches) to the ADV7123.
IOR
IOG
ADV7123
37.5⍀
37.5⍀
G0
G9
IOB
B0
B9
GND
The analog ground plane should encompass all ADV7123
ground pins, voltage reference circuitry, power supply bypass
circuitry, the analog output traces, and any output amplifiers.
Figure 5. Input and Output Connections for Stand-Alone
Gray Scale or Composite Video
The regular PCB ground plane area should encompass all the
digital signal traces, excluding the ground pins, leading up to
the ADV7123.
Video Output Buffers
The ADV7123 is specified to drive transmission line loads, as
are most monitors rated. The analog output configurations to
drive such loads are described in the Analog Interface section
and illustrated in Figure 5. However, in some applications it may
be required to drive long “transmission line” cable lengths. Cable
lengths greater than 10 meters can attenuate and distort high
frequency analog output pulses. The inclusion of output buffers
will compensate for some cable distortion. Buffers with large full
power bandwidths and gains between two and four will be required.
These buffers will also need to be able to supply sufficient current
over the complete output voltage swing. Analog Devices pro-
duces a range of suitable op amps for such applications. These
include the AD84x series of monolithic op amps. In very high
frequency applications (80 MHz), the AD8061 is recommended.
More information on line driver buffering circuits is given in the
relevant op amp data sheets.
Power Planes
The PC board layout should have two distinct power planes,
one for analog circuitry and one for digital circuitry. The analog
power plane should encompass the ADV7123 (VAA) and all
associated analog circuitry. This power plane should be con-
nected to the regular PCB power plane (VCC) at a single point
through a ferrite bead, as illustrated in Figure 7. This bead
should be located within three inches of the ADV7123.
The PCB power plane should provide power to all digital logic
on the PC board, and the analog power plane should provide
power to all ADV7123 power pins, voltage reference circuitry,
and any output amplifiers.
The PCB power and ground planes should not overlay portions
of the analog power plane. Keeping the PCB power and ground
planes from overlaying the analog power plane will contribute to
a reduction in plane-to-plane noise coupling.
Use of buffer amplifiers also allows implementation of other video
standards besides RS-343A and RS-170. Altering the gain compo-
nents of the buffer circuit will result in any desired video level.
Supply Decoupling
Noise on the analog power plane can be further reduced by the
use of multiple decoupling capacitors (see Figure 7).
Z
Z
1
2
0.1F
0.1F
Optimum performance is achieved by the use of 0.1 µF ceramic
capacitors. Each of the two groups of VAA should be individu-
ally decoupled to ground. This should be done by placing the
capacitors as close as possible to the device with the capacitor
leads as short as possible, thus minimizing lead inductance.
+V
S
Z
= 75⍀
O
IOR, IOG, IOB
DACs
75⍀
AD848
Z
= 75⍀
L
(CABLE)
(MONITOR)
Z
= 75⍀
S
–V
S
It is important to note that while the ADV7123 contains cir-
cuitry to reject power supply noise, this rejection decreases with
frequency. If a high frequency switching power supply is used,
the designer should pay close attention to reducing power
supply noise. A dc power supply filter (Murata BNX002) will
provide EMI suppression between the switching power supply
and the main PCB. Alternatively, consideration could be
given to using a three terminal voltage regulator.
Z
Z
(SOURCE
1
2
GAIN (G) = 1 +
TERMINATION)
Figure 6. AD848 As an Output Buffer
PC Board Layout Considerations
The ADV7123 is optimally designed for lowest noise perfor-
mance, both radiated and conducted noise. To complement the
excellent noise performance of the ADV7123, it is imperative
that great care be given to the PC board layout. Figure 7
shows a recommended connection diagram for the ADV7123.
Digital Signal Interconnect
The digital signal lines to the ADV7123 should be isolated as
much as possible from the analog outputs and other analog
circuitry. Digital signal lines should not overlay the analog
power plane.
The layout should be optimized for lowest noise on the ADV7123
power and ground lines. This can be achieved by shielding the
digital inputs and providing good decoupling. The lead length
between groups of VAA and GND pins should be shortened to
minimize inductive ringing.
Due to the high clock rates used, long clock lines to the ADV7123
should be avoided to minimize noise pickup.
REV. B
–15–
ADV7123
Any active pull-up termination resistors for the digital inputs
should be connected to the regular PCB power plane (VCC) and
not the analog power plane.
For optimum performance, the analog outputs should each have
a source termination resistance to ground of 75 Ω (doubly
terminated 75 Ω configuration). This termination resistance
should be as close as possible to the ADV7123 to minimize
reflections.
Analog Signal Interconnect
The ADV7123 should be located as close as possible to the
output connectors, thus minimizing noise pickup and reflections
due to impedance mismatch.
Additional information on PCB design is available in an application
note entitled, Design and Layout of a Video Graphics System for
Reduced EMI. This application note is available from Analog
Devices, publication no. E1309–15–10/89.
The video output signals should overlay the ground plane and
not the analog power plane, thereby maximizing the high fre-
quency power supply rejection.
POWER SUPPLY DECOUPLING (0.1F AND 0.01F
CAPACITOR FOR EACH V GROUP)
AA
L1
0.1F
0.01F
13, 29,
30
(FERRITE BEAD)
V
V
0.1F
AA
CC
V
5V (V
)
AA
AA
COMP
R9–R0
ANALOG GROUND PLANE
0.1F
10F
33F
39-48
5V (V
)
V
AA
REF
R
SET
1-10
R
530⍀
SET
MONITOR
(CRT)
VIDEO
COAXIAL CABLE
G9–G0
B9–B0
DATA
75⍀
INPUTS
IOR
IOG
IOB
14-23
75⍀
75⍀
75⍀
75⍀ 75⍀ 75⍀
ADV7123
BNC
CONNECTORS
SYNC
IOR
BLANK
COMPLEMENTARY
OUTPUTS
IOG
IOB
CLOCK
PSAVE
GND
25, 26
Figure 7. Typical Connection Diagram
–16–
REV. B
ADV7123
OUTLINE DIMENSIONS
48-Lead Plastic Quad Flatpack [LQFP]
1.4 mm Thick
(ST-48)
Dimensions shown in millimeters
1.60 MAX
PIN 1
INDICATOR
0.75
0.60
0.45
9.00 BSC
37
48
36
1
SEATING
PLANE
1.45
1.40
1.35
0.20
0.09
7.00
BSC
TOP VIEW
(PINS DOWN)
VIEW A
7؇
3.5؇
0؇
0.15
0.05
25
12
SEATING
PLANE
24
0.08 MAX
13
COPLANARITY
0.27
0.22
0.17
0.50
BSC
VIEW A
ROTATED 90؇ CCW
COMPLIANT TO JEDEC STANDARDS MS-026BBC
REV. B
–17–
ADV7123
Revision History
Location
Page
10/02—Data Sheet changed from REV. A to REV. B.
Change in title . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Change to FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Change to PRODUCT HIGHLIGHTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Change SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Change to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Change to PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Change to Reference Input section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Change to Figure 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
–18–
REV. B
–19–
–20–
相关型号：
ADV7123JSTZ240
PARALLEL, WORD INPUT LOADING, 10-BIT DAC, PQFP48, ROHS COMPLIANT, MS-026BBC, LQFP-48
ROCHESTER
ADV7123JSTZ330
PARALLEL, WORD INPUT LOADING, 10-BIT DAC, PQFP48, ROHS COMPLIANT, PLASTIC, MS-026BBC, LQFP-48
ROCHESTER
ADV7123KSTZ140
PARALLEL, WORD INPUT LOADING, 10-BIT DAC, PQFP48, ROHS COMPLIANT, MS-026BBC, LQFP-48
ROCHESTER
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