概述
数据手册ADV7127JRUZ240 概述
CMOS, 240 MHz, 10-Bit, High Speed Video DAC
ADV7127JRUZ240 数据手册
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PDF下载CMOS, 240 MHz,
10-Bit, High Speed Video DAC
Data Sheet
ADV7127
FEATURES
FUNCTIONAL BLOCK DIAGRAM
V
AA
240 MSPS throughput rate
10-bit digital-to-analog converter (DAC)
RS-343A-/RS-170-compatible output
Complementary outputs
10
I
OUT
DATA
REGISTER
10
D9 TO D0
DAC
I
OUT
DAC output current range: 2 mA to 18.5 mA
TTL-compatible inputs
Internal voltage reference
Single supply 5 V or 3.3 V operation
24-lead thin shrink small outline package (TSSOP) package
Low power dissipation
PDOWN
PSAVE
CLOCK
VOLTAGE
REFERENCE
CIRCUIT
V
POWER-DOWN
MODE
REF
ADV7127
GND
R
SET
COMP
Low power standby mode
Power-down mode
Figure 1.
Industrial temperature range (−40°C to +85°C)
APPLICATIONS
Digital video systems (1600 × 1200 at 100 Hz)
High resolution color graphics
Digital radio modulation
Image processing
Instrumentation
Video signal reconstruction
Direct digital synthesis (DDS)
Wireless local area networks (LANs)
GENERAL DESCRIPTION
The ADV7127 is a high speed, DAC on a single monolithic
chip. It consists of a 10-bit, video DAC with an on-board voltage
reference, complementary outputs, a standard TTL input
interface, and high impedance analog output current sources.
PRODUCT HIGHLIGHTS
1. 240 MSPS throughput.
2. Guaranteed monotonic to 10 bits.
3. Compatible with a wide variety of high resolution color
The ADV7127 has a 10-bit wide input port. A single 5 V or
3.3 V power supply and clock are all that are required to make
the device functional.
graphics systems including RS-343A and RS-170.
The ADV7127 is fabricated in a complementary metal-oxide
semiconductor (CMOS) process. Its monolithic CMOS
construction ensures greater functionality with low power
dissipation. The ADV7127 is available in a 24-lead TSSOP
package which includes a power-down mode and an on-board
voltage reference circuit.
Rev. A
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©1998–2017 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
ADV7127* PRODUCT PAGE QUICK LINKS
Last Content Update: 02/23/2017
COMPARABLE PARTS
View a parametric search of comparable parts.
DESIGN RESOURCES
• ADV7127 Material Declaration
• PCN-PDN Information
DOCUMENTATION
Application Notes
• Quality And Reliability
• Symbols and Footprints
• AN-205: Video Formats and Required Load Terminations
DISCUSSIONS
View all ADV7127 EngineerZone Discussions.
• AN-213: Low Cost, Two-Chip, Voltage -Controlled
Amplifier and Video Switch
Data Sheet
• ADV7127: CMOS, 240 MHz, 10-Bit, High Speed Video DAC
Data Sheet
SAMPLE AND BUY
Visit the product page to see pricing options.
REFERENCE MATERIALS
Solutions Bulletins & Brochures
TECHNICAL SUPPORT
Submit a technical question or find your regional support
number.
• Digital to Analog Converters ICs Solutions Bulletin
DOCUMENT FEEDBACK
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ADV7127
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Theory of Operation ...................................................................... 14
Digital Inputs .............................................................................. 14
Clock Input.................................................................................. 14
Reference Input........................................................................... 14
Digital-to-Analog Converter .................................................... 14
Analog Output............................................................................ 15
Gray Scale Operation................................................................. 15
Video Output Buffer .................................................................. 15
PCB Layout Considerations...................................................... 16
Ground Planes ............................................................................ 16
Power Planes ............................................................................... 16
Supply Decoupling ..................................................................... 16
Digital Signal Interconnect ....................................................... 16
Analog Signal Interconnect....................................................... 16
Outline Dimensions ....................................................................... 18
Ordering Guide .......................................................................... 18
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
5 V Electrical Characteristics...................................................... 3
3.3 V Electrical Characteristics................................................... 4
5 V Timing Specifications ........................................................... 5
3.3 V Timing Specifications........................................................ 6
Absolute Maximum Ratings............................................................ 7
ESD Caution.................................................................................. 7
Pin Configurations and Function Descriptions ........................... 8
Typical Performance Characteristics ............................................. 9
5 V .................................................................................................. 9
3.3 V ............................................................................................. 11
Terminology .................................................................................... 13
REVISION HISTORY
1/2017—Rev. 0 to Rev. A
Changes to Figure 10 to Figure 12................................................ 10
Changes to Figure 18 Caption ...................................................... 11
Deleted Power Management Section and Table II..................... 12
Changes to Figure 19 to Figure 21................................................ 12
Changed Circuit Description and Operation Section to Theory
of Operation Section ...................................................................... 14
Changes to Video Output Buffer Section.................................... 15
Changes to Supply Decoupling Section and Analog Signal
Interconnect Section ...................................................................... 16
Updated Outline Dimensions....................................................... 18
Changes to Ordering Guide.......................................................... 18
Updated Format..................................................................Universal
Deleted SOIC_W Package.................................................Universal
Change RS-170A to RS-170 ......................................... Throughout
Changes to Features Section............................................................ 1
Deleted 5 V SOIC Specifications Table.......................................... 2
Changes to Table 1............................................................................ 3
Deleted 3.3 V SOIC Specifications Table....................................... 4
Changes to Table 2............................................................................ 4
Changes to Table 3............................................................................ 5
Deleted 5 V/3.3 V Dynamic Specifications Table ........................ 6
Changes to Table 4............................................................................ 6
Changes to Table 6............................................................................ 8
Changes to Figure 9 Caption........................................................... 9
4/1998—Revision 0: Initial Version
Rev. A | Page 2 of 18
Data Sheet
ADV7127
SPECIFICATIONS
5 V ELECTRICAL CHARACTERISTICS
VAA = 5 V 5%, VREF = 1.235 V, RSET = 560 Ω, CL = 10 pF. All specifications TMIN to TMAX,1 unless otherwise noted. TJ MAX = 110°C.
Table 1.
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
STATIC PERFORMANCE
Resolution (Each DAC)
Integral Nonlinearity (INL)
Differential Nonlinearity
DIGITAL AND CONTROL INPUTS
Input Voltage
10
–1
–1
Bits
LSB
LSB
+0.4
+0.25
+1
+1
Guaranteed monotonic
High
Low
VIH
VIL
2
V
V
0.8
+1
PDOWN Input Voltage
High
Low
3
1
V
V
µA
Input Current
IIN
–1
VIN = 0.0 V or VAA
Pull-Up Current
PSAVE
20
20
10
µA
µA
pF
PDOWN
Input Capacitance
ANALOG OUTPUTS
Output Current
Output Compliance Range
Output Impedance
Output Capacitance
Offset Error
CIN
2.0
0
18.5
1.4
mA
V
kΩ
pF
VOC
ROUT
COUT
100
10
IOUT = 0 mA
–0.025
–5.0
+0.025
+5.0
% FSR Tested with DAC output = 0 V
% FSR FSR = 17.62 mA
Gain Error2
VOLTAGE REFERENCE (EXTERNAL
AND INTERNAL)3
Reference Range
POWER DISSIPATION
Supply Current
Digital
VREF
1.12
1.235
1.35
V
1.5
4
6.5
23
5
3
6
10
27
mA
mA
mA
mA
mA
mA
mA
%/%
fCLK = 50 MHz
fCLK = 140 MHz
fCLK = 240 MHz
RSET = 560 Ω
RSET = 4933 Ω
PSAVE = low, digital and control inputs at VAA
Analog
Standby4
3.8
1
6
PDOWN
Power Supply Rejection Ratio
PSRR
0.1
0.5
1 Temperature range TMIN to TMAX: −40°C to +85°C at 50 MHz and 140 MHz, and 0°C to 70°C at 240 MHz.
2 Gain error = ((Measured (FSC)/Ideal (FSC) − 1) × 100), where Ideal = VREF/RSET × K × (0x3FF) and K = 7.9896.
3 The digital supply is measured with a continuous clock, with data input corresponding to a ramp pattern, and with an input level at 0 V and VDD
4 These typical/maximum specifications are guaranteed by characterization to be over the 4.75 V to 5.25 V range.
.
Rev. A | Page 3 of 18
ADV7127
Data Sheet
3.3 V ELECTRICAL CHARACTERISTICS
VAA = 3.0 V to 3.6 V, VREF = 1.235 V, RSET = 560 Ω, CL = 10 pF. All specifications TMIN to TMAX,1 unless otherwise noted. TJ MAX = 110°C.
Table 2.
Parameter2
Symbol Min
Typ
Max
Unit
Test Conditions/Comments
STATIC PERFORMANCE
Resolution (Each DAC)
Integral Nonlinearity (INL)
Differential Nonlinearity
DIGITAL AND CONTROL INPUTS
Input Voltage
RSET = 680 Ω
10
+1
+1
Bits
LSB
LSB
–1
–1
+0.5
+0.25
High
Low
VIH
VIL
2.0
–1
V
V
0.8
PDOWN Input Voltage
High
Low
2.1
0.6
V
V
μA
μA
pF
Input Current
IIN
+1
VIN = 0.0 V or VDD
PSAVE Pull-Up Current
Input Capacitance
ANALOG OUTPUTS
Output Current
20
10
CIN
2.0
0
18.5
1.4
mA
V
kΩ
pF
% FSR
% FSR
Output Compliance Range
Output Impedance
Output Capacitance
Offset Error
VOC
ROUT
COUT
70
10
0
0
Tested with DAC output = 0 V
FSR = 17.62 mA
Gain Error3
0
VOLTAGE REFERENCE (EXTERNAL)
Reference Range
VOLTAGE REFERENCE (INTERNAL)
Reference Range
POWER DISSIPATION
Supply Current
VREF
VREF
1.12
1.235
1.235
1.35
V
V
Digital4
1
2
mA
mA
mA
mA
mA
mA
μA
fCLK = 50 MHz
fCLK = 140 MHz
fCLK = 240 MHz
RSET = 560 Ω
RSET = 4933 Ω
PSAVE = low, digital and control inputs at VDD
2.5
4
22
5
2.6
20
0.1
4.5
6
25
Analog
Standby
3
PDOWN
Power Supply Rejection Ratio
PSRR
0.5
%/%
1 Temperature range TMIN to TMAX: −40°C to +85°C at 50 MHz and 140 MHz and 0°C to 70°C at 240 MHz.
2 These maximum/minimum specifications are guaranteed by characterization to be over 3.0 V to 3.6 V range.
3 Gain error = ((Measured (FSC)/Ideal (FSC) − 1) × 100), where Ideal = VREF/RSET × K × (0x3FF) and K = 7.9896.
4 The digital supply is measured with a continuous clock, with data input corresponding to a ramp pattern, and with an input level at 0 V and VDD
.
Rev. A | Page 4 of 18
Data Sheet
ADV7127
5 V TIMING SPECIFICATIONS
VAA = 5 V 5%,1 VREF = 1.235 V, RSET = 560 Ω, CL = 10 pF. All specifications TMIN to TMAX,2 unless otherwise noted. TJ MAX = 110°C.
Table 3.
Parameter3
ANALOG OUTPUTS
Delay
Rise/Fall Time4
Transition Time5
Skew6
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
t6
t7
t8
t9
5.5
1.0
15
1
ns
ns
ns
ns
2
Not shown in Figure 2
CLOCK CONTROL7
fCLK
0.5
0.5
0.5
50
140
240
MHz
MHz
MHz
50 MHz grade
140 MHz grade
240 MHz grade
Data and Control
Setup
Hold
t1
t2
1.5
2.5
ns
ns
Clock Pulse Width
High
t4
1.875 1.1
2.85
8.0
1.875 1.25
2.85
8.0
ns
ns
ns
ns
ns
ns
fMAX = 240 MHz
fMAX = 140 MHz
fMAX = 50 MHz
fMAX = 240 MHz
fMAX = 140 MHz
fMAX = 50 MHz
Low
t5
Pipeline Delay6
Up Time
tPD
1.0
1.0
1.0
10
Clock cycles Not shown in Figure 2
PSAVE6
t10
t11
2
ns
ns
Not shown in Figure 2
Not shown in Figure 2
PDOWN
320
1 Maximum and minimum specifications are guaranteed over this range in Table 3.
2 Temperature range: TMIN to TMAX: −40°C to +85°C at 50 MHz and 140 MHz, and 0°C to 70°C at 240 MHz.
3 Timing specifications are measured with input levels of 3.0 V (VIH) and 0 V (VIL) for both 5 V and 3.3 V supplies.
4 Rise time was measured from the 10% to 90% point of zero to full-scale transition, and fall time from the 90% to 10% point of a full-scale transition.
5 Measured from 50% point of full-scale transition to 2% of final value.
6 Guaranteed by characterization.
7 fCLK maximum specification production tested at 125 MHz and 5 V. Limits specified in Table 3 are guaranteed by characterization.
Rev. A | Page 5 of 18
ADV7127
Data Sheet
3.3 V TIMING SPECIFICATIONS
VAA = 3.0 V to 3.6 V,1 VREF = 1.235 V, RSET = 560 Ω. All specifications TMIN to TMAX,2 unless otherwise noted. TJ MAX = 110°C.
Table 4.
Parameter3
ANALOG OUTPUTS
Delay
Rise/Fall Time4
Transition Time5
Skew6
Symbol Min
Typ
Max
Unit
Test Conditions/Comments
t6
t7
t8
t9
7.5
1.0
15
1
ns
ns
ns
ns
2
Not shown in Figure 2
CLOCK CONTROL7
fCLK
50
140
240
MHz
MHz
MHz
50 MHz grade
140 MHz grade
240 MHz grade
Data and Control
Setup6
t1
t2
t3
1.5
2.5
ns
ns
ns
Hold6
Clock Period6
Clock Pulse Width
High
2.5
1.1
fMAX = 240 MHz
t4
t4
t4
t5
t5
t5
ns
ns
ns
ns
ns
ns
fMAX = 240 MHz
fMAX = 140 MHz
fMAX = 50 MHz
fMAX = 240 MHz
fMAX = 140 MHz
fMAX = 50 MHz
6
6
2.85
8.0
Low6
1.4
1.0
2.85
8.0
1.0
Pipeline Delay6
Up Time
PSAVE6
tPD
1.0
10
Clock cycles
Not shown in Figure 2
t10
t11
4
ns
ns
Not shown in Figure 2
Not shown in Figure 2
PDOWN
320
1 The values stated in Table 4 were obtained using VAA in the range of 3.0 V to 3.6 V.
2 Temperature range: TMIN to TMAX: −40°C to +85°C at 50 MHz and 140 MHz, and 0°C to 70°C at 240 MHz.
3 Timing specifications are measured with input levels of 3.0 V (VIH) and 0 V (VIL) for both 5 V and 3.3 V supplies.
4 Rise time was measured from the 10% to 90% point of zero to full-scale transition, and fall time from the 90% to 10% point of a full-scale transition.
5 Measured from 50% point of full-scale transition to 2% of final value.
6 Guaranteed by characterization.
7 fCLK maximum specification production tested at 125 MHz and 3.3 V. Limits specified in Table 4 are guaranteed by characterization.
t3
t4
t5
CLOCK
t2
DIGITAL INPUTS
DATA
D9 TO D0
t1
t8
t6
ANALOG OUTPUTS
I
, I
OUT OUT
t7
NOTES
1. OUTPUT DELAY (t6) MEASURED FROM THE 50% POINT OF THE RISING
EDGE OF CLOCK TO THE 50% POINT OF FULL-SCALE TRANSITION.
2. OUTPUT RISE/FALL TIME (t7) MEASURED BETWEEN THE 10% AND
90% POINTS OF FULL-SCALE TRANSITION.
3. TRANSITION TIME (t8) MEASURED FROM THE 50% POINT OF FULL-SCALE
TRANSITION TO WITHIN 2% OF THE FINAL OUTPUT VALUE.
Figure 2. Timing Diagram
Rev. A | Page 6 of 18
Data Sheet
ADV7127
ABSOLUTE MAXIMUM RATINGS
Table 5.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Parameter
Rating
VAA to GND
Voltage on Any Digital Pin
Ambient Operating Temperature Range −40°C to +85°C
(TA)
Storage Temperature Range(TS)
Junction Temperature (TJ)
Lead Temperature (Soldering, 10 sec)
Vapor Phase Soldering (1 Minute)
IOUT to GND1
7 V
GND − 0.5 V to VAA + 0.5 V
−65°C to +150°C
150°C
300°C
220°C
0 V to VAA
ESD CAUTION
1 Analog output short circuit to any power supply or common can be of an
indefinite duration.
Rev. A | Page 7 of 18
ADV7127
Data Sheet
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
1
24
23
22
21
20
19
18
17
16
15
14
13
D1
D2
D3
D4
D5
D6
D7
D8
D9
D0
2
PSAVE
3
R
SET
4
V
REF
5
COMP
I
6
OUT
ADV7127
TOP VIEW
7
I
(Not to Scale)
OUT
8
V
AA
9
GND
10
V
GND
AA
PDOWN
DNC
11
12
CLOCK
DNC
DNC = DO NOT CONNECT
Figure 3. Pin Configuration
Table 6. Pin Function Descriptions
Pin No. Mnemonic Description
1 to 9,
24
D0 to D9
Data Inputs (TTL-Compatible). Data is latched on the rising edge of CLOCK. D0 is the least significant data bit.
Unused data inputs are connected to either the regular printed circuit board (PCB) power or ground plane. Data
inputs are red, green, or blue pixel inputs.
10, 17
11
VAA
PDOWN
Analog Power Supply (5 V 5ꢀ). All VAA pins on the ADV7127 must be connected.
Power-Down Control Pin. The ADV7127 completely powers down, including the voltage reference circuit, when
PDOWN is low.
12, 13
14
DNC
CLOCK
Do Not Connect. Do not connect to these pins.
Clock Input (TTL-Compatible). The rising edge of CLOCK latches D0 to D9 where D0 to D9 can be red, green, or
blue pixel data inputs (TTL-compatible). CLOCK is typically the pixel clock rate of the video system. CLOCK is driven
by a dedicated TTL buffer.
15, 16
18
GND
IOUT
Ground. All GND pins must be connected.
Differential Current Output. This pin is capable of directly driving a doubly terminated 75 Ω load. If not required,
this output is tied to ground.
19
20
21
IOUT
Current Output. This high impedance current source is capable of directly driving a doubly terminated 75 Ω coaxial
cable.
Compensation Pin. COMP is a compensation pin for the internal reference amplifier. A 0.1 μF ceramic capacitor
must be connected between COMP and VAA.
Voltage Reference Input. An external 1.23 V voltage reference must be connected to this pin. The use of an external
resistor divider network is not recommended. A 0.1 μF decoupling ceramic capacitor is connected between VREF
and VAA.
COMP
VREF
22
23
RSET
Full-Scale Adjust Control. A resistor (RSET) connected between this pin and GND controls the magnitude of the full-
scale video signal. Note that the IRE relationships are maintained, regardless of the full-scale output current. The
relationship between RSET and the full-scale output current on IOUT is given by IOUT (mA) = 7968 × VREF (V)/RSET (Ω).
Power Save Control Pin. The device is put into standby mode when PSAVE is low. The internal voltage reference
circuit is still active.
PSAVE
Rev. A | Page 8 of 18
Data Sheet
ADV7127
TYPICAL PERFORMANCE CHARACTERISTICS
5 V
VAA = 5 V, VREF = 1.235 V, IOUT = 17.62 µA, 50 Ω doubly terminated load, differential output loading, TA = 25°C, unless otherwise noted.
70
60
50
40
30
20
10
0
76
74
72
70
68
66
64
62
60
58
SECOND HARMONIC
SFDR (DIFFERENTIAL)
THIRD HARMONIC
FOURTH HARMONIC
SFDR (SINGLE-ENDED)
0.10
1.00
2.51
5.04
20.20
40.40
100.00
0
50
100
fCLOCK (MHz)
140
160
OUTPUT FREQUENCY (MHz)
Figure 4. SFDR vs. Output Frequency (fOUT) at fCLOCK = 140 MHz (Single-Ended
and Differential)
Figure 7. THD vs. fCLOCK at fOUT = 2 MHz (Second, Third, and Fourth Harmonics)
80
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
SFDR (DIFFERENTIAL)
70
60
50
40
30
20
10
0
SFDR (SINGLE-ENDED)
0
2.00
17.62
20.00
0.10
1.00
2.51
5.04
20.20
40.40
100.00
OUTPUT FREQUENCY (MHz)
I
(mA)
OUT
Figure 5. SFDR vs. Output Frequency (fOUT) at fCLOCK = 50 MHz (Single-Ended
and Differential)
Figure 8. Linearity vs. IOUT
72.2
72.0
71.8
71.6
71.4
71.2
71.0
70.8
70.6
70.4
1.0
0.5
0.75
0
1023
–0.16
–0.5
–1.0
CODE (INL)
TEMPERATURE (°C)
Figure 6. SFDR vs. Temperature at fCLOCK = 50 MHz (fOUT = 1 MHz)
Figure 9. Error vs. Code
Rev. A | Page 9 of 18
ADV7127
Data Sheet
–5
–5
–45
–85
2
V
= 5V
AA
V
= 5V
AA
–45
1
1
–85
0kHz
START
35.0MHz
70.0MHz
STOP
0kHz
START
35.0MHz
70.0MHz
STOP
Figure 12. Dual Tone SFDR at fCLOCK = 140 MHz
(fOUT1 = 13.5 MHz, fOUT2 = 14.5 MHz)
Figure 10. Single Tone SFDR at fCLOCK = 140 MHz (fOUT1 = 2 MHz)
–5
V
= 5V
2
AA
–45
1
–85
0kHz
START
35.0MHz
70.0MHz
STOP
Figure 11. Single Tone SFDR at fCLOCK = 140 MHz (fOUT1 = 20 MHz)
Rev. A | Page 10 of 18
Data Sheet
ADV7127
3.3 V
VAA = 3 V, VREF = 1.235 V, IOUT = 17.62 µA, 50 Ω doubly terminated load, differential output loading, TA = 25°C, unless otherwise noted.
70
60
50
40
30
20
10
0
76
74
72
70
68
66
64
62
60
58
56
SECOND HARMONIC
FOURTH HARMONIC
SFDR (DIFFERENTIAL)
SFDR (SINGLE-ENDED)
THIRD HARMONIC
0.10
2.51
5.04
20.20
40.40
100.00
0
50
100
140
160
OUTPUT FREQUENCY (MHz)
OUTPUT FREQUENCY (MHz)
Figure 13. SFDR vs. Output Frequency (fOUT) at fCLOCK = 140 MHz (Single-Ended
and Differential)
Figure 16. THD vs. fCLOCK at Output Frequency
OUT = 2 MHz (Second, Third, and Fourth Harmonics)
f
80
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
SFDR (DIFFERENTIAL)
70
SFDR (SINGLE-ENDED)
60
50
40
30
20
10
0
0.1
0.10
2.51
5.04
20.20
40.40
100.00
0
2.00
17.62
20.00
OUTPUT FREQUENCY (MHz)
I
(mA)
OUT
Figure 17. Linearity vs. IOUT
Figure 14. SFDR vs. Output Frequency (fOUT) at fCLOCK = 50 MHz (Single-Ended
and Differential)
72.0
71.8
71.6
71.4
71.2
71.0
70.8
70.6
70.4
1.0
0.5
0.75
0
1023
–0.42
–0.5
–1.0
0
20
85
145
165
CODE (INL)
TEMPERATURE (°C)
Figure 15. SFDR vs. Temperature at fCLOCK = 50 MHz, (fOUT = 1 MHz)
Figure 18. Error vs. Code
Rev. A | Page 11 of 18
ADV7127
Data Sheet
–5
–45
–85
–5
2
2
V
= 3.3V
V
= 3.3V
AA
AA
–45
1
1
–85
0kHz
START
35.0MHz
70.0MHz
STOP
0kHz
START
35.0MHz
70.0MHz
STOP
Figure 21. Dual Tone SFDR at fCLOCK = 140 MHz
(fOUT1 = 13.5 MHz, fOUT2 = 14.5 MHz)
Figure 19. Single Tone SFDR at fCLOCK = 140 MHz (fOUT1 = 2 MHz)
–5
2
V
= 3.3V
AA
–45
1
–85
0kHz
START
35.0MHz
70.0MHz
STOP
Figure 20. Single Tone SFDR at fCLOCK = 140 MHz (fOUT1 = 20 MHz)
Rev. A | Page 12 of 18
Data Sheet
ADV7127
TERMINOLOGY
Color Video (RGB)
Reference Black Level
Color video (RGB) usually refers to the technique of combining
the three primary colors of red, green, and blue to produce color
pictures within the usual spectrum. In RGB monitors, three DACs
are required, one for each color.
Reference black level is the maximum negative polarity
amplitude of the video signal.
Reference White Level
Reference white level is the maximum positive polarity
amplitude of the video signal.
Gray Scale
Gray scale is the discrete levels of video signal between the
reference black and reference white levels. A 10-bit DAC
contains 1024 different levels, whereas an 8-bit DAC contains 256.
Video Signal
Video signal is the portion of the composite video signal that varies
in gray scale levels between reference white and reference black.
It is also referred to as the picture signal, which is the portion
that can be visually observed.
Raster Scan
Raster scan is the most basic method of sweeping a CRT one
line at a time to generate and display images.
Rev. A | Page 13 of 18
ADV7127
Data Sheet
THEORY OF OPERATION
I
OUT
The ADV7127 contains one 10-bit DAC, with one input
channel containing a 10-bit register. A reference amplifier is
also integrated on board the device.
mA
V
WHITE
LEVEL
17.61 0.66
DIGITAL INPUTS
Ten bits of data (color information), D0 to D9, are latched into
the device on the rising edge of each clock cycle. This data is
presented to the 10-bit DAC and is then converted to an analog
output waveform (see Figure 22).
100 IRE
BLACK
LEVEL
0
0
CLOCK
Figure 23. IOUT RS-343A Video Output Waveform
Table 7. Video Output Truth Table (RSET = 560 Ω, RLOAD
37.5 Ω)
=
DIGITAL INPUTS
DATA
D0 TO D9
(Ω)
IOUT
Description Data
White Level
Video
IOUT (Ω)
17.62
Video
0
DAC Input
0x3FF
Data
0
ANALOG OUTPUTS
I
, I
17.62 − Video
17.62
OUT OUT
Black Level
0x000
Figure 22. Video Data Input/Output
All of these digital inputs are specified to accept TTL logic levels.
REFERENCE INPUT
The ADV7127 has an on-board voltage reference. The VREF pin
is normally terminated to VAA through a 0.1 µF capacitor.
Alternatively, the device can, if required, be overdriven by an
external 1.23 V reference (AD1580).
CLOCK INPUT
The CLOCK input of the ADV7127 is typically the pixel clock
rate of the system. It is also known as the dot rate. The dot rate,
and therefore the required CLOCK frequency, is determined by
the onscreen resolution, according to the following equation:
A resistance RSET connected between the RSET pin and the GND
pin determines the amplitude of the output video level according to
the following equation:
Dot Rate = (Horizontal Resolution × Vertical Resolution ×
Refresh Rate)/Retrace Factor
IOUT (mA) = (7968 × VREF (V))/RSET (Ω)
where:
Using a variable value of RSET allows accurate adjustment of the
analog output video levels. Use of a fixed 560 Ω RSET resistor
yields the analog output levels quoted in Specifications section.
These values typically correspond to the RS-343A video
waveform values shown in Figure 23.
Horizontal Resolution is the number of pixels per line.
Vertical Resolution is the number of lines per frame.
Refresh Rate is the horizontal scan rate at which the screen must
be refreshed, typically 60 Hz for a noninterlaced system or
30 Hz for an interlaced system.
Retrace Factor is the total blank time factor, which takes into
account that the display is blanked for a certain fraction of the
total duration of each frame (for example, 0.8).
DIGITAL-TO-ANALOG CONVERTER
The ADV7127 contains a 10-bit DAC. The DAC is designed using
an advanced, high speed, segmented architecture. The bit currents
corresponding to each digital input are routed to either the analog
output (bit = 1) or GND (bit = 0) by a sophisticated decoding
scheme. The use of identical current sources in a monolithic design
guarantees monotonicity and low glitch. The on-board operational
amplifier stabilizes the full-scale output current against temperature
and power supply variations.
If there is a graphics system with a 1024 × 1024 resolution, a
noninterlaced 60 Hz refresh rate, and a retrace factor of 0.8, then
Dot Rate = (1024 × 1024 × 60)/0.8 = 78.6 MHz
The required CLOCK frequency is 78.6 MHz.
All video data and control inputs are latched into the ADV7127 on
the rising edge of CLOCK, as previously described in the Digital
Inputs section. It is recommended that the CLOCK input to the
ADV7127 be driven by a TTL buffer (for example, 74F244).
Rev. A | Page 14 of 18
Data Sheet
ADV7127
More detailed information regarding load terminations for
ANALOG OUTPUT
various output configurations, including RS-343A and RS-170,
is available in the AN-205 Application Note, Video Formats and
Required Load Terminations.
The analog output of the ADV7127 is a high impedance current
source. The current output is capable of directly driving a 37.5 Ω
load, such as a doubly terminated 75 Ω coaxial cable. Figure 24
shows the required configuration for the output connected into
a doubly terminated 75 Ω load. This arrangement develops
RS-343A video output voltage levels across a 75 Ω monitor.
Figure 23 shows the video waveforms associated with the
current output driving the doubly terminated 75 Ω load of
Figure 24.
I
OUT
GRAY SCALE OPERATION
Z
= 75Ω
O
DAC
The ADV7127 can be used for standalone, gray scale (mono-
chrome), or composite video applications (that is, only one
channel used for video information).
(CABLE)
Z
= 75Ω
S
Z
= 75Ω
L
(SOURCE
TERMINATION)
(MONITOR)
VIDEO OUTPUT BUFFER
The ADV7127 is specified to drive transmission line loads, which is
what most monitors are rated as. The analog output configurations
to drive such loads are shown in Figure 26. However, in some
applications, it may be required to drive long transmission line
cable lengths. Cable lengths greater than 10 meters can attenuate
and distort high frequency analog output pulses. The inclusion of
the output buffers compensates for some cable distortion. Buffers
with large full power bandwidths and gains between two and four
are required. These buffers need to be able to supply sufficient
current over the complete output voltage swing. Analog Devices,
Inc., produces a range of suitable op amps for such applications.
These include the AD843/AD844/AD847 series of monolithic op
amps. In very high frequency applications (80 MHz), the AD8061
is recommended. More information on line driver buffering
circuits is given in the relevant op amp data sheets.
Figure 24. Analog Output Termination for RS-343A
A suggested method of driving RS-170 video levels into a 75 Ω
monitor is shown in Figure 25. The output current level of the
DAC remains unchanged, but the source termination resistance,
ZS, on the DAC is increased from 75 Ω to 150 Ω.
I
OUT
Z
= 75Ω
O
DAC
(CABLE)
Z
= 150Ω
S
Z
= 75Ω
L
(SOURCE
(MONITOR)
TERMINATION)
Figure 25. Analog Output Termination for RS-170
Use of buffer amplifiers also allows implementation of other video
standards besides RS-343A and RS-170. Altering the gain
components of the buffer circuit results in any desired video level.
Z
Z
1
2
+V
0.1µF
S
Z
= 75Ω
O
I
75Ω
OUT
AD848
Z
= 75Ω
(CABLE)
DAC
L
0.1µF
(MONITOR)
Z
= 75Ω
S
–V
S
(SOURCE
Z
Z
1
2
GAIN (G) = 1 +
TERMINATION)
Figure 26. AD848 As an Output Buffer
Rev. A | Page 15 of 18
ADV7127
Data Sheet
PCB LAYOUT CONSIDERATIONS
SUPPLY DECOUPLING
The ADV7127 is optimally designed for lowest noise perfor-
mance, both radiated and conducted noise. To complement the
excellent noise performance of the ADV7127, it is imperative
that great care be given to the PCB layout. Figure 27 shows a
recommended connection diagram for the ADV7127.
Noise on the analog power plane can be further reduced by the
use of multiple decoupling capacitors (see Figure 27).
Optimum performance is achieved by the use of 0.1 µF ceramic
capacitors. Each of the two groups of VAA is individually
decoupled to ground. The VAA pins (Pin 10 and Pin 17) must be
decoupled with capacitors to GND. Decouple the pins by
placing the capacitors as close as possible to the device with the
capacitor leads as short as possible between the VAA and GND
pins, thus minimizing lead inductance.
The PCB layout is optimized for lowest noise on the ADV7127
power and ground lines. Radiated and conducted noise can be
achieved by shielding the digital inputs and providing good
decoupling. The lead length between groups of VAA and GND
pins is minimized to inductive ringing.
It is important to note that while the ADV7127 contains
circuitry to reject power supply noise, this rejection decreases
with frequency. If a high frequency switching power supply is
used, the designer must pay close attention to reducing power
supply noise. A dc power supply filter (Murata BNX002)
provides an electromagnetic interface (EMI) suppression
between the switching power supply and the main PCB.
Alternatively, consider using a 3-terminal voltage regulator.
GROUND PLANES
The ADV7127 and associated analog circuitry have a separate
ground plane referred to as the analog ground plane. This
ground plane connects to the regular PCB ground plane at a
single point through a ferrite bead, as illustrated in Figure 27.
The ferrite bead is located as close as possible (within 3 inches)
to the ADV7127.
DIGITAL SIGNAL INTERCONNECT
The analog ground plane encompasses all ADV7127 ground
pins, voltage reference circuitry, power supply bypass circuitry,
the analog output traces, and any output amplifiers. The regular
PCB ground plane area encompasses all the digital signal traces,
excluding the ground pins, leading up to the ADV7127.
The digital signal lines to the ADV7127 must be isolated as
much as possible from the analog outputs and other analog
circuitry. Digital signal lines must not overlay the analog power
plane.
Due to the high clock rates used, long clock lines to the
ADV7127 must be avoided to minimize noise pickup.
POWER PLANES
The PCB layout has two distinct power planes: one for analog
circuitry and one for digital circuitry. The analog power plane
encompasses the ADV7127 (VAA) and all associated analog
circuitry. This power plane is connected to the regular PCB
power plane (VCC) at a single point through a ferrite bead, as
illustrated in Figure 27. This bead is located within 3 inches of
the ADV7127.
Any active pull-up termination resistors for the digital inputs
are connected to the regular PCB power plane (VCC) and not the
analog power plane.
ANALOG SIGNAL INTERCONNECT
The ADV7127 is located as close as possible to the output
connectors, which minimizes noise pickup and reflections due
to impedance mismatch.
The PCB power plane provides power to all digital logic on the
PCB, and the analog power plane provides power to all
ADV7127 power pins, voltage reference circuitry, and any
output amplifiers. The PCB power and ground planes do not
overlay portions of the analog power plane. Keeping the PCB
power and ground planes from overlaying the analog power
plane contributes to a reduction in plane to plane noise
coupling.
The video output signals overlay the ground plane and not the
analog power plane, thereby maximizing the high frequency
power supply rejection.
For optimum performance, the analog outputs each have a
source termination resistance to ground of 75 Ω (doubly
terminated 75 Ω configuration). This termination resistance
must be as close as possible to the ADV7127 to minimize
reflections.
Additional information on PCB design is available in the
AN-333 Application Note, Design and Layout of a Video
Graphics System for Reduced EMI.
Rev. A | Page 16 of 18
Data Sheet
ADV7127
COMP
C6
0.1µF
ANALOG POWER PLANE
V
AA
ADV7127
C3
0.1µF
C4
0.1µF
C5
0.1µF
L1 (FERRITE BEAD)
+5V (V
)
CC
V
REF
VIDEO
DATA
INPUTS
C2
10µF
C1
33µF
D0
D9
ANALOG GROUND PLANE
GND
GROUND
L2 (FERRITE BEAD)
R
SET
560Ω
R1
75Ω
PDOWN
PSAVE
CLOCK
R
SET
VIDEO
OUTPUT
I
OUT
COMPONENT
DESCRIPTION
VENDOR PART NUMBER
C1
33µF TANTALUM CAPACITOR
10µF TANTALUM
C2
C3, C4, C5, C6
L1, L2
0.1µF CERAMIC CAPACITOR
FERRITE BEAD
FAIR-RITE 274300111 OR MURATA BL01/02/03
DALE CMF-55C
R1
75Ω 1% METAL FILM RESISTOR
R
560Ω 1% METAL FILM RESISTOR DALE CMF-55C
SET
Figure 27. Typical Connection Diagram and Component List
Rev. A | Page 17 of 18
ADV7127
Data Sheet
OUTLINE DIMENSIONS
7.90
7.80
7.70
24
13
12
4.50
4.40
4.30
6.40 BSC
1
PIN 1
0.65
BSC
1.20
MAX
0.15
0.05
0.75
0.60
0.45
8°
0°
0.30
0.19
0.20
0.09
SEATING
PLANE
0.10 COPLANARITY
COMPLIANT TO JEDEC STANDARDS MO-153-AD
Figure 28. 24-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-24)
Dimensions shown in millimeters
ORDERING GUIDE
Speed
Model1
Options
240 MHz
50 MHz
50 MHz
140 MHz
50 MHz
50 MHz
140 MHz
Temperature Range Package Description
Package Option
RU-24
ADV7127JRUZ240
ADV7127KRUZ50
ADV7127KRUZ50-REEL
ADV7127KRUZ140
ADV7127KRU50
ADV7127KRU50-REEL
ADV7127KRU140
0°C to 70°C
24-Lead Thin Shrink Small Outline Package [TSSOP]
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
24-Lead Thin Shrink Small Outline Package [TSSOP]
24-Lead Thin Shrink Small Outline Package [TSSOP]
24-Lead Thin Shrink Small Outline Package [TSSOP]
24-Lead Thin Shrink Small Outline Package [TSSOP]
24-Lead Thin Shrink Small Outline Package [TSSOP]
24-Lead Thin Shrink Small Outline Package [TSSOP]
RU-24
RU-24
RU-24
RU-24
RU-24
RU-24
1 Z = RoHS Compliant Part.
©1998–2017 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D14959-0-1/17(A)
Rev. A | Page 18 of 18
ADV7127JRUZ240 CAD模型
引脚图
封装焊盘图
ADV7127JRUZ240 相关器件
| 型号 | 制造商 | 描述 | 价格 | 文档 |
| ADV7127JRZ240 | ROCHESTER | PARALLEL, WORD INPUT LOADING, 10-BIT DAC, PDSO28, SOIC-28 | 获取价格 |
|
| ADV7127JRZ240 | ADI | IC PARALLEL, WORD INPUT LOADING, 10-BIT DAC, PDSO28, SOIC-28, Digital to Analog Converter | 获取价格 |
|
| ADV7127KR140 | ADI | CMOS, 240 MHz 10-Bit High Speed Video DAC | 获取价格 |
|
| ADV7127KR140 | ROCHESTER | PARALLEL, WORD INPUT LOADING, 10-BIT DAC, PDSO28, SOIC-28 | 获取价格 |
|
| ADV7127KR140-REEL | ROCHESTER | PARALLEL, WORD INPUT LOADING, 10-BIT DAC, PDSO28, SOIC-28 | 获取价格 |
|
| ADV7127KR50 | ADI | CMOS, 240 MHz 10-Bit High Speed Video DAC | 获取价格 |
|
| ADV7127KR50 | ROCHESTER | 暂无描述 | 获取价格 |
|
| ADV7127KR50-REEL | ROCHESTER | PARALLEL, WORD INPUT LOADING, 10-BIT DAC, PDSO28, SOIC-28 | 获取价格 |
|
| ADV7127KR50-REEL | ADI | IC PARALLEL, WORD INPUT LOADING, 10-BIT DAC, PDSO28, SOIC-28, Digital to Analog Converter | 获取价格 |
|
| ADV7127KRU140 | ADI | CMOS, 240 MHz 10-Bit High Speed Video DAC | 获取价格 |
|
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