ADV7152LS135 [ADI]
CMOS 220 MHz True-Color Graphics Triple 10-Bit Video RAM-DAC; CMOS 220 MHz的真彩色图形三路10位视频RAM -DAC
| 型号： | ADV7152LS135 |
| 厂家： | 
ADI |
| 描述： | CMOS 220 MHz True-Color Graphics Triple 10-Bit Video RAM-DAC |
| 文件： | 总32页 (文件大小：456K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CMOS 220 MHz True-Color Graphics
Triple 10-Bit Video RAM-DAC
a
ADV7152
FEATURES
APPLICATIONS
220 MHz, 24-Bit (30-Bit Gam m a Corrected) True Color
Triple 10-Bit “Gam m a Correcting” D/ A Converters
Triple 256
؋
10 (256 ؋
30) Color Palette RAM On-Chip Clock Control Circuit
Palette Priority Select Registers
RS-343A/ RS-170 Com patible Analog Outputs
TTL Com patible Digital Inputs
Standard MPU l/ O Interface
10-Bit Parallel Structure
8+2 Byte Structure
Program m able Pixel Port: 24-Bit and 8-Bit (Pseudo)
Pixel Data Serializer
High Resolution, True Color Graphics
Professional Color Prepress Im aging
GENERAL D ESCRIP TIO N
T he ADV7152 (ADV®) is a complete analog output, Video
RAM-DAC on a single CMOS monolithic chip. T he part is spe-
cifically designed for use in high performance, color graphics
workstations. T he ADV7152 integrates a number of graphic
functions onto one device allowing 24-bit direct T rue-Color op-
eration at the maximum screen update rate of 220 MHz. T he
ADV7152 implements 30-bit T rue Color in 24-bit frame buffer
designs. T he part also supports other modes, including 15-bit
T rue Color and 8-bit Pseudo or Indexed Color. Either the Red,
Green or Blue input pixel ports can be used for Pseudo Color.
Multiplexed Pixel Input Ports; 1:1, 2:1
+5 V CMOS Monolithic Construction
100-Lead Plastic Quad Flatpack (QFP)
T he device consists of three, high speed, 10-bit, video D/A con-
verters (RGB), three 256 ϫ 10 (one 256 ϫ 30) color look-up
tables, palette priority selects, a pixel input data multiplexer/
serializer and a clock generator/divider circuit. T he ADV7152
implements 1:1 and 2:1 pixel data multiplexing. T he onboard
palette priority select inputs enable multiple palette devices to
be connected together for use in multipalette and window
(Continued on page 10)
Therm ally Enhanced to Achieve < 1.0؇C/ W
J C
MODES OF OPERATION
24-Bit True Color (30-Bit Gam m a Corrected)
@ 220 MHz
@ 170 MHz
@ 135 MHz
@ 110 MHz
@ 85 MHz
ADV is a registered trademark of Analog Devices, Inc.
8-Bit Pseudo Color
15-Bit True Color
FUNCTIO NAL BLO CK D IAGRAM
V
AA
256-COLOR/GAMMA
PALETTE RAM
ADV7152
RED
256 x 10
10
10
10
IOR
IOR
10-BIT
RED DAC
24
24
A
B
RED (R0–R7),
GREEN (G0–G7),
BLUE (B0–B7)
COLOR DATA
8
8
8
P
I
X
E
L
48
GREEN
256 x 10
IOG
IOG
10-BIT
GREEN DAC
MUX
2:1
BLUE
256 x 10
IOB
IOB
10-BIT
BLUE DAC
P
O
R
T
PALETTE
SELECTS
(PS0, PS1)
4
4
2
MUX
2:1
SYNC
OUTPUT
I
PLL
SYNCOUT
CONTROL REGISTERS
PIXEL MASK
V
REF
VOLTAGE
REFERENCE
CIRCUIT
CLOCK CONTROL
R
SET
DATA TO
PALETTES
REGISTER
LOADIN
LOADOUT
COMMAND
C
OMP
REGISTERS
(CR1-CR3)
CLOCK DIVIDE
&
SYNCHRONIZATION
CIRCUIT
TEST
REGISTERS
ADDRESS
REGISTER
30
COLOR REGISTERS
PRGCKOUT
MODE
REGISTER
REVISION
ID
SCKIN
SCKOUT
RED
REGISTER
GREEN
BLUE
ADDR
(A0-–A15)
REGISTER
REGISTER
REGISTER
REGISTER
(MR1)
÷32, ÷16, ÷8, ÷4, ÷2
SYNC
BLANK
MPU PORT
10 (8+2)
CLOCK
CLOCK
ECL TO CMOS
D9 – D0
GND
R/W
CE
C0 C1
REV. B
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.
Tel: 617/ 329-4700 Fax: 617/ 326-8703
1
ADV7152–SPECIFICATIONS (V = +5 V; V = +1.235 V; R
SET = 280 ⍀. IOR, IOG, IOB (R = 37.5 ⍀,
AA
REF
L
C = 10 pF); IOR, IOG, IOB = GND. All specifications TMIN to T 2 unless otherwise noted.)
L
MAX
P aram eter
All Versions
Unit
Test Conditions/Com m ents
ST AT IC PERFORMANCE
Resolution (Each DAC)
Accuracy (Each DAC)
Integral Nonlinearity
Differential Nonlinearity
Gray Scale Error
10
Bits
±1
±1
±5
LSB max
LSB max
% Gray Scale max
Binary
Guaranteed Monotonic
Coding
DIGIT AL INPUT S (Excluding CLOCK, CLOCK)
Input High Voltage, VINH
2
V min
Input Low Voltage, VINL
Input Current, IIN
Input Capacitance, CIN
0.8
±10
10
V max
µA max
pF typ
VIN = 0.4 V or 2.4 V
CLOCK INPUT S (CLOCK, CLOCK)
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN
VAA – 1.0
VAA – 1.6
±10
V min
V max
µA max
pF typ
VIN = 0.4 V or 2.4 V
Input Capacitance, CIN
10
DIGIT AL OUT PUT S
Output High Voltage, VOH
Output Low Voltage, VOL
Floating-State Leakage Current
Floating-State Output Capacitance
2.4
0.4
20
V min
ISOURCE = 400 µA
ISINK = 3.2 mA
V max
µA max
pF typ
20
ANALOG OUT PUT S
Gray Scale Current Range
Output Current
15/22
mA min/max
White Level Relative to Blank
White Level Relative to Black
Black Level Relative to Blank
Blank Level on IOR, IOB
Blank Level on IOG
17.69/20.40
16.74/18.50
0.95/1.90
0/50
6.29/8.96
0/50
mA min/max
mA min/max
mA min/max
µA min
mA min/max
µA min/max
µA typ
T ypically 19.05 mA
T ypically 17.62 mA
T ypically 1.44 mA
T ypically 5 µA
T ypically 7.62 mA
T ypically 5 µA
Sync Level on IOG
LSB Size
17.22
DAC-to-DAC Matching
Output Compliance, VOC
Output Impedance, ROUT
Output Capacitance, COUT
3
% max
V min/V max
kΩ typ
T ypically 1%
0/+1.4
100
30
pF max
IOUT = 0 mA
VOLT AGE REFERENCE
Voltage Reference Range, VREF
Input Current, IVREF
1.14/1.26
+5
V min/V max
µA typ
VREF = 1.235 V for Specified Performance
POWER REQUIREMENT S
VAA
IAA
IAA
IAA
5
V nom
3
400
370
350
330
315
0.5
mA max
mA max
mA max
mA max
mA max
%/% max
220 MHz Parts
170 MHz Parts
135 MHz Parts
110 MHz Parts
85 MHz Parts
T ypically 0.12%/%, COMP = 0.1 µF
IAA
IAA
Power Supply Rejection Ratio
DYNAMIC PERFORMANCE
Clock and Data Feedthrough4, 5
Glitch Impulse
–30
50
–23
dB typ
pV secs typ
dB typ
DAC-to-DAC Crosstalk6
NOT ES
1±5% for all versions.
2T emperature range (T MIN to T MAX): 0°C to +70°C; T J (Silicon Junction T emperature) ≤ 100°C.
3Pixel Port is continuously clocked with data corresponding to a linear ramp. T J = 100°C.
4Clock and data feedthrough is a function of the amount of overshoot and undershoot on the digital inputs. Glitch impulse includes clock and data feedthrough.
5T T L input values are 0 to 3 volts, with input rise/fall times ≤ 3 ns, measured the 10% and 90% points. T iming reference points at 50% for inputs and outputs.
6DAC-to-DAC crosstalk is measured by holding one DAC high while the other two are making low-to-high and high-to-low transitions.
Specifications subject to change without notice.
–2–
REV. B
ADV7152
1
2
TIMING CHARACTERISTICS
(V = +5 V; V = +1.235 V; R = 280 ⍀. IOR, IOG, IOB (R = 37.5 ⍀, C = 10 pF);
AA
REF
SET
L
L
IOR, IOG, I0B = GND. All specifications TMIN to T 3 unless otherwise noted.)
MAX
CLO CK CO NTRO L AND P IXEL P O RT 4
220 MH z 170 MH z 135 MH z 110 MH z 85 MH z
P aram eter
Version
Version
Version
Version
Version Units
Conditions/Com m ents
fCLOCK
t1
t2
t3
220
4.55
2
2
10
170
5.88
2.5
2.5
10
135
7.4
3
3.2
10
110
9.1
4
4
10
85
11.77
4
4
10
MHz max Pixel CLOCK Rate
ns min
ns min
ns min
ns max
Pixel CLOCK Cycle T ime
Pixel CLOCK High T ime
Pixel CLOCK Low T ime
Pixel CLOCK to LOADOUT Delay
LOADIN Clocking Rate
t4
fLOADIN
1:1 Multiplexing
2:1 Multiplexing
110
110
110
85
110
67.5
110
55
85
42.5
MHz max
MHz max
t5
LOADIN Cycle T ime
LOADIN High T ime
LOADIN Low T ime
1:1 Multiplexing
2:1 Multiplexing
9.1
9.1
9.1
11.76
9.1
14.8
9.1
18.18
11.76
23.53
ns min
ns min
t6
1:1 Multiplexing
2:1 Multiplexing
4
4
4
5
4
6
4
8
4
9
ns min
ns min
t7
1:1 Multiplexing
2:1 Multiplexing
4
4
0
5
0
τ–5
4
5
0
5
0
τ–5
4
6
0
5
0
τ–5
4
8
0
5
0
τ–5
4
9
0
5
0
τ–5
ns min
ns min
ns min
ns min
ns min
ns max
t8
t9
Pixel Data Setup T ime
Pixel Data Hold T ime
LOADOUT to LOADIN Delay
LOADOUT to LOADIN Delay
Pipeline Delay
t10
τ–t11
tPD
5
6
1:1 Multiplexing
5
5
5
5
5
CLOCKs (1 × CLOCK = t1)
2:1 Multiplexing
6
6
6
6
6
CLOCKs
t12
t13
t14
t15
10
5
5
10
5
5
10
5
5
10
5
5
10
5
5
ns max
ns max
ns min
ns min
Pixel CLOCK to PRGCKOUT Delay
SCKIN to SCKOUT Delay
BLANK to SCKIN Setup T ime
BLANK to SCKIN Hold T ime
1
1
1
1
1
ANALO G O UTP UTS7
220 MH z 170 MH z 135 MH z 110 MH z 85 MH z
Version Version Version Version Version Units
P aram eter
Conditions/Com m ents
t16
t17
t18
tSK
15
1
15
2
15
1
15
2
15
1
15
2
15
1
15
2
15
1
15
2
ns typ
ns typ
ns typ
ns max
ns typ
Analog Output Delay
Analog Output Rise/Fall T ime
Analog Output T ransition T ime
Analog Output Skew (IOR, IOG, IOB)
0
0
0
0
0
MP U P O RTS8, 9
P aram eter
220 MH z 170 MH z 135 MH z 110 MH z 85 MH z
Version Version Version Version Version Units
Conditions/Com m ents
t19
t20
t21
t22
t23
t24
3
3
3
3
3
ns min
ns min
ns min
ns min
ns min
ns max
ns max
ns min
ns min
ns min
R/W, C0, C1 to CE Setup T ime
R/W, C0, C1 to CE Hold T ime
CE Low T ime
10
45
25
5
45
20
5
10
45
25
5
45
20
5
10
45
25
5
45
20
5
10
45
25
5
45
20
5
10
45
25
5
45
20
5
CE High T ime
8
CE Asserted to Databus Driven
CE Asserted to Data Valid
CE Disabled to Databus T hree-Stated
9
9
t25
t26
t27
20
5
20
5
20
5
20
5
20
5
Write Data (D0–D9) Setup T ime
Write Data (D0–D9) Hold T ime
REV. B
–3–
ADV7152
NOT ES
1T T L input values are 0 to 3 volts, with input rise/fall times ≤ 3 ns, measured between the 10% and 90% points. ECL inputs (CLOCK, CLOCK) are
VAA–0.8 V to VAA–1.8 V, with input rise/fall times ≤ 2 ns, measured between the 10% and 90% points. T iming reference points at 50% for inputs and out-
puts. Analog output load ≤ 10 pF. Databus (D0–D9) loaded as shown in Figure 1. Digital output load for LOADOUT , PRGCKOUT , SCKOUT , I PLL and
SYNCOUT ≤ 30 pF.
2±5% for all versions.
3T emperature range (T MIN to T MAX): 0°C to +70°C; T J (Silicon Junction T emperature) ≤ 100°C.
4Pixel Port consists of the following inputs: Pixel Inputs: RED [A, B]; GREEN [A, B]; BLUE [A, B], Palette Selects: PS0 [A, B]; PS1 [A, B]; Pixel Controls:
SYNC, BLANK; Clock Inputs: CLOCK, CLOCK, LOADIN, SCKIN; Clock Outputs: LOADOUT , PRGCKOUT , SCKOUT .
5τ is the LOADOUT Cycle T ime and is a function of the Pixel CLOCK Rate and the Multiplexing Mode: 1:1 multiplexing; τ = CLOCK = t1 ns; 2:1 multi-
plexing, τ = CLOCK × 2 = 2 × t1 ns.
6T hese fixed values for Pipeline Delay are valid under conditions where t 10 and τ–t11 are met. If either t10 or τ–t11 are not met, the part will operate but the Pipe-
line Delay is increased by 2 clock cycles for 2:1 mode after calibration cycle is performed.
7Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of full-scale transition. Output rise/fall time measured between the
10% and 90% points of full-scale transition. Settling time measured from the 50% point of full-scale transition to the output remaining within ±1 LSB. (Settling time
does not include clock and data feedthrough.)
8t23 and t24 are measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.4 V or 2.4 V.
9t25 is derived from the measured time taken by the data outputs to change by 0.5 V when loaded with the circuit of Figure 1. T he measured number is then extrapo-
lated back to remove the effects of charging the 100 pF capacitor. T his means that the time, t 25, quoted in the T iming Characteristics is the true value for the device
and as such is independent of external databus loading capacitances.
Specifications subject to change without notice.
I
SINK
TO
+2.1V
OUTPUT
PIN
100pF
I
SOURCE
Figure 1. Load Circuit for Databus Access and Relinquish Tim es
t2
t3
t1
CLOCK
CLOCK
t4
LOADOUT
(1:1 MULTIPLEXING)
LOADOUT
(2:1 MULTIPLEXING)
Figure 2. LOADOUT vs. Pixel Clock Input (CLOCK, CLOCK)
t6
t5
t7
LOADIN
t8
t9
PIXEL INPUT
DATA*
VALID
DATA
VALID
DATA
VALID
DATA
*INCLUDES PIXEL DATA (R0-R7, G0-G7, B0-B7); PALETTE SELECT INPUTS (PS0-PS1); SYNC; BLANK
Figure 3. LOADIN vs. Pixel Input Data
REV. B
–4–
ADV7152
CLOCK
t10
LOADOUT
LOADIN
PIXEL INPUT
DATA*
AN BN
AN+1BN+1
AN+2BN+2
IOR, IOR
IOG, IOG
IOB, IOB
ANALOG
OUTPUT
DATA
AN-1
BN-1
AN
AN+1
BN
AN+2
BN+2
BN+1
I
, SYNCOUT
PLL
tPD
*INCLUDES PIXEL DATA (R0–R7, G0–G7, B0–B7); PALETTE SELECT INPUTS (PS0-PS1); SYNC; BLANK
Figure 4. Pixel Input to Analog Output Pipeline with Minim um LOADOUT to LOADIN Delay (2:1 Multiplex Mode)
CLOCK
τ
τ- t11
LOADOUT
LOADIN
PIXEL INPUT
AN BN
AN+1BN+1
AN+2BN+2
DATA*
IOR, IOR
IOG, IOG
IOB, IOB
ANALOG
OUTPUT
DATA
BN+1
AN+2
BN+2
AN-1
BN-1
AN
BN
AN+1
I
, SYNCOUT
PLL
tPD
*INCLUDES PIXEL DATA (R0–R7, G0–G7, B0–B7); PALETTE SELECT INPUTS (PS0–PS1); SYNC; BLANK
Figure 5. Pixel Input to Analog Output Pipeline with Maxim um LOADOUT to LOADIN Delay (2:1 Multiplex Mode)
CLOCK
PRGCKOUT
(CLOCK/4)
PRGCKOUT
(CLOCK/8)
PRGCKOUT
(CLOCK/16)
PRGCKOUT
(CLOCK/32)
t12
*INLCUDES PIXEL DATA (R0-R7, G0-G7, B0-B7); PALETTE SELECT INPUTS (PS0-PS1); SYNC; BLANK
Figure 6. Pixel Clock Input vs. Program m able Clock Output (PRGCKOUT)
REV. B
–5–
ADV7152
t14
t13
SCKIN
t15
BLANKING PERIOD
BLANK
SCKOUT
START OF SCAN
LINE (N+1)
END OF SCAN
LINE (N)
*INCLUDES PIXEL DATA (R0-R7, G0-G7, B0-B7); PALETTE SELECT INPUTS (PS0-PS1); SYNC; BLANK
Figure 7. Video Data Shift Clock Input (SCKIN) & BLANK vs. Video Data Shift Clock Output (SCKOUT)
CLOCK
t18
t16
WHITE LEVEL
90 %
IOR, IOR
IOG, IOG
IOB, IOB
ANALOG
OUTPUTS
FULL SCALE
TRANSITION
I
PLL , SYNCOUT
50 %
10 %
BLACK LEVEL
t17
NOTE:
THIS DIAGRAM IS NOT TO SCALE. FOR THE PURPOSES OF CLARITY,
THE ANALOG OUTPUT WAVEFORM IS MAGNIFIED IN TIME AND
AMPLITUDE W.R.T. THE CLOCK WAVEFORM.
IPLL AND SYNCOUT ARE DIGITAL OUTPUT SIGNALS. t16 IS THE ONLY
RELEVANT OUTPUT TIMING SPECIFICATION FOR IPLL AND SYNCOUT.
Figure 8. Analog Output Response vs. CLOCK
t19
t20
VALID
CONTROL DATA
R/W, C0, C1
t21
CE
t22
t24
t25
t23
D0–D9
R/W = 1
(READ MODE)
D0–D9
(WRITE MODE)
R/W = 0
t26
t27
Figure 9. Microprocessor Port (MPU) Interface Tim ing
REV. B
–6–
ADV7152
RECOMMENDED OPERATING CONDITIONS
P aram eter
Sym bol
Min
Typ
Max
Units
Power Supply
VAA
T A
VREF
RL
4.75
0
1.14
5.00
5.25
+70
1.26
Volts
°C
Volts
Ω
Ambient Operating T emperature
Reference Voltage
Output Load
1.235
37.5
CAUTIO N
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADV7152 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. T herefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
ABSO LUTE MAXIMUM RATINGS1
P IN ASSIGNMENTS
VAA to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Voltage on Any Digital Pin . . . . GND – 0.5 V to VAA + 0.5 V
Ambient Operating T emperature (TA) . . . . . –55°C to +125°C
Storage T emperature (TS) . . . . . . . . . . . . . . –65°C to +150°C
Junction T emperature (TJ) . . . . . . . . . . . . . . . . . . . . +150°C
Lead T emperature (Soldering, 10 secs) . . . . . . . . . . . +260°C
Vapor Phase Soldering (1 minute) . . . . . . . . . . . . . . . +220°C
Analog Outputs to GND2 . . . . . . . . . . . . . GND – 0.5 to VAA
P in
P in
P in
No. Mnem onic
No. Mnem onic
No. Mnem onic
1
2
3
4
5
6
7
8
9
SYNC
BLANK
R0A
R0B
GND
R1A
R1B
R2A
R2B
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
5 8
5 9
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
SCKOUT
SYNCOUT
GND
GND
GND
GND
G6A
G6B
G7A
G7B
PS0A
PS0B
PS1A
PS1B
B0A
B0B
B1A
B1B
B2A
B2B
B3A
B3B
B4A
B4B
B5A
B5B
B6A
B6B
B7A
B7B
CE
R/W
C0
C1
D0
D1
D2
GND
D3
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
D5
VAA
D6
D7
D8
NOT ES
D9
1Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. T his is a stress rating only and functional
operation of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
2Analog Output Short Circuit to any Power Supply or Common can be of an
indefinite duration.
GND
GND
IOB
IOR
IOG
IOB
IOG
VAA
IPLL
IOR
COMP
VREF
RSET
10 R3A
11 R3B
12 R4A
13 R4B
14 R5A
15 R5B
16 R6A
17 R6B
18 R7A
19 R7B
20 G0A
21 G0B
22 G1A
23 G1B
24 G2A
25 G2B
26 NC
27 G3A
28 G3B
29 G4A
30 G4B
O RD ERING GUID E 1, 2, 3
Speed
220 MH z ADV7152LS220
170 MH z ADV7152LS170
135 MH z ADV7152LS135
110 MH z ADV7152LS110
85 MH z ADV7152LS85
100 VAA
NOT ES
1ADV7152 is packaged in a 100-pin plastic quad flatpack, QFP.
2All devices are specified for 0°C to +70°C operation.
3Contact sales office for latest information on package design.
100-Lead QFP Configuration
51
80
ROW C
50
81
31 G5A
32 G5B
ADV7152
QFP
Top View
33 CLOCK
34 CLOCK
35 LOADIN
36 LOADOUT
37 VAA
38 VAA
39 PRGCKOUT
40 SCKIN
(Not to Scale)
PIN NO. 1 IDENTIFIER
ROW A
31
100
1
30
D4
NC = NO CONNECT .
REV. B
–7–
ADV7152
P IN FUNCTIO N D ESCRIP TIO N
Function
Mnem onic
RED (R0A . . . R0B–R7A . . . R7B),
GREEN (G0A . . . G0B–G7A. . . G7B),
BLUE (B0A . . . B0B–B7A . . . B7B)
Pixel Port (T T L Compatible Inputs). 48 pixel select inputs, with 8 bits each for Red, 8
bits for Green and 8 bits for Blue. Each bit is multiplexed [A-B] 2:1 or 1:1. It can be
configured for 24-Bit True-Color Data, 8-Bit Pseudo-Color Data and 15-Bit True-Color
Data formats. Pixel Data is latched into the device on the rising edge of LOADIN.
PS0A . . . PS0B, PS1A . . . PS1B
Palette Priority Selects (T T L Compatible Inputs): T hese pixel port select inputs deter-
mine whether or not the device’s pixel data port is selected on a pixel by pixel basis. T he
palette selects allow switching between multiple palette devices. T he device can be pre-
programmed to completely shut off the DAC analog outputs. If the values of PS0 and
PS1 match the values programmed into bits MR16 and MR17 of the Mode Register,
then the device is selected. Each bit is multiplexed [A-B] 2:1 or 1:1. PS0 and PS1 are
latched into the device on the rising edge of LOADIN.
LOADIN
Pixel Data Load Input (T T L Compatible Input). T his input latches the multiplexed
pixel data, including PS0–PS1, BLANK and SYNC into the device.
LOADOUT
Pixel Data Load Output (T T L Compatible Output). T his output control signal runs at a
divided down frequency of the pixel CLOCK input. Its frequency is a function of the
multiplex rate. It can be used to directly or indirectly drive LOADIN
fLOADOUT = fCLOCK/M
where (M = 1 for 1:1 Multiplex Mode)
where (M = 2 for 2:1 Multiplex Mode).
PRGCKOUT
Programmable Clock Output (T T L Compatible Output). T his output control signal
runs at a divided down frequency of the pixel CLOCK input. Its frequency is user
programmable and is determined by bits CR30 and CR31 of Command Register 3
fPRGCKOUT = fCLOCK/N
where N = 4, 8, 16 and 32.
SCKIN
Video Shift Clock Input (T T L Compatible Input). T he signal on this input is internally
gated synchronously with the BLANK signal. T he resultant output, SCKOUT , is a
video clocking signal that is stopped during video blanking periods.
SCKOUT
Video Shift Clock Output (T T L Compatible Output). T his output is a synchronously
gated version of SCKIN and BLANK. SCKOUT , is a video clocking signal that is
stopped during video blanking periods.
CLOCK, CLOCK
Clock Inputs (ECL Compatible Inputs). T hese differential clock inputs are designed to
be driven by ECL logic levels configured for single supply (+5 V) operation. T he clock
rate is normally the pixel clock rate of the system.
BLANK
SYNC
Composite Blank (T T L Compatible Input). T his video control signal drives the analog
outputs to the blanking level.
Composite-Sync Input (T T L Compatible Input). T his video control signal drives the
IOG analog output to the SYNC level. It is only asserted during the blanking period.
CR22 in Command Register 2 must be set if SYNC is to be decoded onto the analog
output, otherwise the SYNC input is ignored.
SYNCOUT
Composite SYNC O/P (T T L Compatible Output). T his video output is a delayed ver-
sion of SYNC. T he delay corresponds to the number of pipeline stages of the device.
D0–D9
Databus (T T L Compatible Input/Output Bus). Data, including color palette values and
device control information is written to and read from the device over this 10-bit, bidi-
rectional databus. 10-bit data or 8-bit data can be used. T he databus can be configured
for either 10-bit parallel data or byte data (8+2) as well as standard 8-bit data. Any un-
used bits of the databus should be terminated through a resistor to either he digital
power plane (VCC) or GND.
CE
Chip Enable (T T L Compatible Input). T his input must be at Logic “0” when writing to
or reading from the device over the databus (D0–D9). Internally, data is latched on the
rising edge of CE.
REV. B
–8–
ADV7152
Mnem onic
Function
R/W
Read/Write Control (T T L Compatible Input). T his input determines whether data is
written to or read from the device’s registers and color palette RAM. R/W and CE must
be at Logic “0” to write data to the part. R/W must be at Logic “1” and CE at Logic
“0” to read from the device.
C0, C1
Command Controls (T T L Compatible Inputs). T hese inputs determine the type of read
or write operation being performed on the device over the databus (see Interface T ruth
T able). Data on these inputs is latched on the falling edge of CE.
IOR; IOR, IOG; IOG, IOB;
IOB
Red, Green and Blue Current Outputs (High Impedance Current Sources). T hese RGB
video outputs are specified to directly drive RS-343A and RS-170 video levels into dou-
bly terminated 75 Ω loads.
IOR, IOG and IOB are the complementary outputs of IOR, IOG and IOB. T hese out-
puts can be tied to GND if it is not required to use differential outputs.
VREF
Voltage Reference Input (Analog Input). An external 1.235 V voltage reference is re-
quired to drive this input. An AD589 (2-terminal voltage reference) or equivalent is rec-
ommended. (Note: It is not recommended to use a resistor network to generate the
voltage reference.)
RSET
Output Full-Scale Adjust Control (Analog Input). A resistor connected between this pin
and analog ground controls the absolute amplitude of the output video signal. T he value
of RSET is derived from the full-scale output current on IOG according to the following
equations:
RSET (Ω) = C1 × RREF/IOG (mA); SYNC on GREEN
RSET (Ω) = C2 × RREF/IOG (mA); No SYNC on GREEN.
Full-Scale output currents on IOR and IOB for a particular value of RSET are given by:
IOR (mA)= C2 × RREF(V)/RSET (Ω)
and
IOB (mA) = C2 × RREF (V)/RSET (Ω)
where C1 = 6,050: PEDEST AL = 7.5 IRE
where C1 = 5,723: PEDEST AL = 0 IRE
and
where C2 = 4,323: PEDEST AL = 7.5 IRE
where C1 = 3,996: PEDEST AL = 0 IRE.
COMP
IPLL
Compensation Pin. A 0.1 µF capacitor should be connected between this pin and VAA.
Phase Lock Loop Output Current (High Impedance Current Source). T his output is
used to enable multiple ADV7150/ADV7152s along with ADV7151s to be synchronized
together with subpixel resolution when using an external PLL. T his output is triggered
either from the falling edge of SYNC or BLANK as determined by bit CR21 of Com-
mand Register 2. When activated, it supplies a current corresponding to
IPLL (mA) = 1,728 × RREF(V)/RSET (Ω)
When not using the IPLL function, this output pin should be tied to GND.
VAA
Power Supply (+5 V ± 5%). T he part contains multiple power supply pins, all should be
connected together to one common +5 V filtered analog power supply.
GND
Analog Ground. T he part contains multiple ground pins, all should be connected
together to the system’s ground plane.
REV. B
–9–
ADV7152
(Continued from page 1)
An external ECL oscillator source with differential outputs is all
that is required to drive the CLOCK and CLOCK inputs of the
ADV7152. T he part can also be driven by an external clock
generator chip circuit, such as the AD730.
applications. T he part is controlled and programmed through
the microprocessor (MPU) port. T he part also contains a num-
ber of onboard test registers, associated with self diagnostic test-
ing of the device.
T he ADV7152 is capable of generating RGB video output sig-
nals which are compatible with RS-343A and RS-170 video
standards, without requiring external buffering.
T he individual Red, Green and Blue pixel input ports allow
T rue-Color, image rendition. T rue-Color image rendition, at
speeds of up to 220 MHz, is achieved through the use of the
onboard data multiplexer/serializer. T he pixel input ports flex-
ibility allows for direct interface to most standard frame buffer
memory configurations.
T est diagnostic circuitry has been included to complement the
users system level debugging.
T he ADV7152 is fabricated in a +5 V CMOS process. Its
monolithic CMOS construction ensures greater functionality
with low power dissipation.
T he 30 bits of resolution, associated with the color look-up
table and triple 10-bit DAC, realizes 24-bit T rue-Color resolu-
tion, while also allowing for the onboard implementation of lin-
earization algorithms, such as Gamma-Correction. T his allows
effective 30-bit T rue-Color operation.
T he ADV7152 is packaged in a plastic 100-pin power quad flat-
pack (QFP). Superior thermal dissipation is achieved by inclu-
sion of a copper heatslug, within the standard package outline
to which the die is attached.
T he on-chip video clock controller circuit generates all the in-
ternal clocking and some additional external clocking signals.
P ixel P or t and Clock Contr ol Cir cuit
CIRCUIT D ETAILS AND O P ERATIO N
T he Pixel Port of the ADV7152 is directly interfaced to the
video/graphics pipeline of a computer graphics subsystem. It is
connected directly or through a gate array to the video RAM of
the systems Frame-Buffer (video memory). T he pixel port on
the device consists of:
O VERVIEW
Digital video or pixel data is latched into the ADV7152 over the
devices Pixel Port. T his data acts as a pointer to the onboard
Color Palette RAM. T he data at the RAM address pointed to is
latched into the digital-to-analog converters (DACs) and output
as an RGB analog video signal.
Color Data
RED, GREEN, BLUE
SYNC, BLANK
PS0–PS1
Pixel Controls
Palette Selects
For the purposes of clarity of description, the ADV7152 is bro-
ken down into three separate functional blocks. T hese are:
T he associated clocking signals for the pixel port include:
1. Pixel port and clock control circuit
Clock Inputs
CLOCK, CLOCK,
LOADIN, SCKIN
LOADOUT , PRGCKOUT ,
SCKOUT
2. MPU port, registers and color palette
3. Digital-to-analog converters and video outputs
Clock Outputs
T able I shows the architectural and packaging differences be-
tween other devices in the ADV715x series of workstation parts.
(For more details consult the relevant data sheets.)
T hese onboard clock control signals are included to simplify
interfacing between the part and the frame buffer. Only two
control input signals are necessary to get the part operational,
CLOCK and CLOCK (ECL Levels). No additional signals or
external glue logic are required to get the Pixel Port & Clock
Control Circuit of the part operational.
Table I. Architectural and P ackaging D ifferences of the
AD V715x Series
D escription
AD V7150*
AD V7152 AD V7151*
P ixel P or t (Color D ata)
24-Bit “Gamma” T rue Color
24-Bit “Standard” T rue Color
8-Bit “Gamma” Pseudo Color
8-Bit “Standard” Pseudo Color
15-Bit T rue Color
220 MHz – T rue Color
220 MHz – Pseudo Color
T riple 10-Bit DACs
•
•
•
•
•
•
•
•
•
•
•
•
•
•
T he ADV7152 has 48 color data inputs. T he part has two (for
2:1 multiplexing) 24-bit wide direct color data inputs. T hese
are user programmed to support a number of color data for-
mats including 24-Bit T rue Color, 15-Bit T rue Color and
8-Bit Pseudo Color (see “Color Data Formats” section) in 2:1
and 1:1 multiplex modes.
•
•
•
•
•
•
•
•
•
•
•
•
•
4:1 Multiplexing
2:1 Multiplexing
•
•
24
24
RED
8
8
8
1:1 Multiplexing
160-Lead QFP
A
B
GREEN
BLUE
24
MULTIPLEXER
100-Lead QFP
•
•
*See ADV7151 and ADV7150 data sheets for more information on these parts.
Figure 10. Multiplexed Color Inputs for the ADV7152
REV. B
–10–
ADV7152
resultant pixel or dot clock rate of 100 MHz. As mentioned in
the previous section, the ADV7152 supports a number of color
data formats in 2:1 and 1:1 multiplex modes.
Color data is latched into the parts pixel port on every rising
edge of LOADIN (see T iming Waveform, Figure 3). T he
required frequency of LOADIN is determined by the multiplex
rate, where
In 1:1 multiplex mode, the ADV7152 is clocked using the
LOADIN signal. T his means that there is no requirement for
differential ECL inputs on CLOCK and CLOCK. T he pixel
clock is connected directly to LOADIN. (Note: T he ECL
CLOCK can still be used to generate LOADOUT PRGCKOUT,
etc.)
fLOADIN = fCLOCK/2
fLOADIN = fCLOCK
2:1 Multiplex Mode
1:1 Multiplex Mode
Other pixel data signals latched into the device by LOADIN
include SYNC, BLANK and PS0–PS1.
Internally, data is pipelined through the part by the differential
pixel clock inputs, CLOCK and CLOCK. T he LOADIN con-
trol signal needs only have a frequency synchronous relationship
to the pixel CLOCK (see “Pipeline Delay & Onboard Calibra-
tion” section). A completely phase independent LOADIN signal
can be used with the ADV7152, allowing the CLOCK to occur
anywhere during the LOADIN cycle.
VIDEO MEMORY/
ADV7152
FRAME BUFFER
24
A
VRAM (BANK A)
VRAM (BANK B)
50MHz
50MHz
24
100MHz
(2 x 50MHz)
MULTIPLEXER
Alternatively, the LOADOUT signal of the ADV7152 can be
used. LOADOUT can be connected either directly or indirectly
to LOADIN. Its frequency is automatically set to the correct
LOADIN requirement.
24
B
SYNC, BLANK
Figure 11. Direct Interfacing of Video Mem ory to
ADV7152
T he BLANK and SYNC video control signals drive the analog
outputs to the blanking and SYNC levels respectively. T hese
signals are latched into the part on the rising edge of LOADIN.
T he SYNC information is encoded onto the IOG analog signal
when bit CR22 of Command Register 2 is set to a Logic “1.”
T he SYNC input is ignored if CR22 is set to “0.”
CLO CK CO NTRO L CIRCUIT
T he ADV7152 has an integrated Clock Control Circuit (Figure
12). T his circuit is capable of both generating the ADV7152’s
internal clocking signals as well as external graphics subsystem
clocking signals. T otal system synchronization can be attained
by using the parts output clocking signals to drive the control-
ling graphics processor’s master clock as well as the video frame
buffers shift clock signals.
SYNCOUT
In some applications where it is not permissible to encode
SYNC on green (IOG), SYNCOUT can be used as a separate
T T L digital SYNC output. T his has the advantage over an inde-
pendent (of the ADV7150) SYNC in that it does not necessitate
knowing the absolute pipeline delay of the part. T his allows
complete independence between LOADIN/Pixel Data and
CLOCK. T he SYNC input is connected to the device as normal
with Bit CR22 of Command Register 2 set to “0” thereby pre-
venting SYNC from being encoded onto IOG. Bit CR12 of
Command Register 1 is set to “1,” enabling SYNCOUT. T he
output signal generates a T T L SYNCOUT with correct pipeline
delay that is capable of directly driving the composite SYNC
signal of a computer monitor.
CLO CK, CLOCK Inputs
T he Clock Control Circuit is driven by the pixel clock inputs,
CLOCK and CLOCK. T hese inputs can be driven by a differ-
ential ECL oscillator running from a +5 V supply.
ECL
TO
TTL
CLOCK
CLOCK
DIVIDE BY N
DIVIDE BY M
PRGCKOUT
LOADOUT
(÷ N)
(÷ M)
P S0–P S1 (P alette P r ior ity Select Inputs)
T hese pixel port select inputs determine whether or not the de-
vice is selected. T hese controls effectively determine whether the
devices RGB analog outputs are turned-on or shut down. When
the analog outputs are shut down, IOR, IOG and IOB are
forced to 0 mA regardless of the state of the pixel and control
data inputs. T his state is determined on a pixel by pixel basis as
the PS0–PS1 inputs are multiplexed in exactly the same format
as the pixel port color data. T hese controls allow for switching
between multiple palette devices (see Appendix 4). If the values
of PS0 and PSI match the values programmed into bits MR16
and MR17 of the Mode Register, then the device is selected, if
there is no match the device is effectively shut down.
SCKOUT
LATCH
BLANK
SYNC
ENABLE
SCKIN
ADV7152
LOADIN
TO COLOR DATA
MULTIPLEXER
Multiplexing
T he onboard multiplexers of the ADV7152 eliminate the need
for external data serializer circuits. Multiple video memory de-
vices can be connected, in parallel, directly to the device. Fig-
ure 11 shows two memory banks of 50 MHz memory connected
to the ADV7152, running in 2:1 multiplex mode, giving a
M IS A FUNCTION OF MULTIPLEX RATE
M = 2 IN 2:1 MULTIPLEX MODE
M = 1 IN 1:1 MULTIPLEX MODE
N IS INDEPENDENTLY
PROGRAMMABLE
N= (4, 8, 16, 32)
Figure 12. Clock Control Circuit of the ADV7152
REV. B
–11–
ADV7152
If it is not necessary to have a known fixed number of pipeline
delays, then there is no limitation on the delay between LOAD-
OUT and LOADIN (LOADOUT (1) and LOADOUT (2)).
LOADIN and Pixel Data must conform to the setup and hold
times (t8 and t9).
Alternatively, the ADV7152 CLOCK inputs can be driven by a
Programmable Clock Generator (Figure 13), such as the
ICS1562. T he ICS1562 is a monolithic, phase-locked-loop,
clock generator chip. It is capable of synthesizing differential
ECL output frequencies in a range up to 220 MHz from a single
low frequency reference crystal.
If however, it is required that the ADV7152 has a fixed number
of pipeline delays (tPD), LOADOUT and LOADIN must con-
form to timing specifications t10 and τ-t11 as illustrated in Fig-
ures 4 and 5.
LOW FREQUENCY
OSCILLATOR
V
AA
GND
V
V
CC
CC
P RGCKO UT
+5V
220Ω
V
220Ω
CLOCK
T he PRGCKOUT control signal outputs a user programmable
clock frequency. It is a divided down frequency of the pixel
CLOCK (see Figure 8). T he rising edge of PRGCKOUT is
synchronous to the rising edge of LOADOUT
ECL
CLOCK
CLOCK
OUT+
ECL
+5V
OUT–
330Ω
GND
330Ω
GND
fPRGCKOUT = f CLOCK/N
CLOCK
GENERATOR
ADV7152
V
where N = 4, 8, 16 or 32.
AA
One application of the PRGCKOUT is to use it as the master
clock frequency of the graphics subsystems processor or
controller.
0.1 µF
V
V
OUT
REF
REF
SCKIN, SCKO UT
GND
GND
T hese video memory signals are used to minimize external sup-
port chips. Figure 15 illustrates the function that is provided.
An input signal applied to SCKIN is synchronously AND-ed
with the video blanking signal (BLANK). T he resulting signal is
output on SCKOUT . Figure 7 of the T iming Waveform section
shows the relationship between SCKOUT , SCKIN and
BLANK.
D0–D3
R/W
CS
Figure 13. PLL Generator Driving CLOCK, CLOCK of the
ADV7152
CLO CK CO NTRO L SIGNALS LO AD O UT
T he ADV7152 generates a LOADOUT control signal which
runs at a divided down frequency of the pixel CLOCK. T he
frequency is automatically set to the programmed multiplex
rate, controlled by CR36 of Command Register 3.
SCKOUT
LATCH
BLANK
fLOADOUT = fCLOCK/2
fLOADOUT = fCLOCK
2:1 Multiplex Mode
1:1 Multiplex Mode
ENABLE
SYNC
SCKIN
T he LOADOUT signal is used to directly drive the LOADIN
pixel latch signal of the ADV7152. T his is most simply achieved
by tying the LOADOUT and LOADIN pins together. Alterna-
tively, the LOADOUT signal can be used to drive the frame
buffer’s shift clock signals, returning to the LOADIN input de-
layed with respect to LOADOUT .
Figure 15. SCKOUT Generation Circuit
T he SCKOUT signal is essentially the video memory shift con-
trol signal. It is stopped during the screen retrace. Figure 16
shows a suggested frame buffer to ADV7152 interface. T his is a
minimum chip solution and allows the ADV7152 control the
overall graphics system clocking and synchronization.
LOADOUT(1)
LOADOUT
ADV7152
LOADIN
LOADOUT
VIDEO
FRAME
BUFFER
VIDEO
FRAME
BUFFER
ADV7152
LOADOUT(2)
LOADOUT
LOADIN
LOADIN
PIXEL
DATA
PIXEL
DATA
SCKIN
VIDEO
FRAME
ADV7152
BUFFER
BLANK
SCKOUT
LOADOUT
LOADIN
LOADOUT(1)
LOADOUT(2)
DELAY
PIXEL
DATA
Figure 16. ADV7152 Interface Using SCKIN and SCKOUT
Figure 14. LOADOUT vs. Pixel Clock Input (CLOCK, CLOCK)
REV. B
–12–
ADV7152
24-BIT TO 24-BIT
LOOK-UP-TABLE
24-BIT
COLOR DATA
24-BIT
PIXEL DATA
ANALOG VIDEO
OUTPUTS
P ipeline D elay and O n-Boar d Calibr ation
T he ADV7152 has a fixed number of pipeline delays (tPD), so
long as timings t10 and τ-t11 are met. However, if a fixed pipeline
delay is not a requirement, timings t10 and τ-t11 can be ignored,
a calibration cycle must be run and there is no restriction on
LOADIN to LOADOUT timing. If timings t10 and τ-t11 are not
met, the part will function correctly though with an increased
number of pipeline delays, tPD + N CLOCKS (for 2:1 mode
N = 2, for 1:1 mode N = 0). T he ADV7152 has onboard cali-
bration circuitry which synchronizes pixel data and LOADIN
with the internal ADV7152 clocking signals. Calibration can be
performed in two ways: during the devices initialization se-
quence by toggling two bits of the Mode Register, MR10 fol-
lowed by MR15, or by writing a “1” to Bit CR10 of Command
Register 1 which executes a calibration on every Vertical Sync.
8
8
8
8
8
8
RED
256 x 8
RED
OUT
8-BIT
RED DAC
GREEN
256 x 8
8-BIT
GREEN DAC
GREEN
OUT
BLUE
256 x 8
8-BIT
BLUE DAC
BLUE
OUT
Figure 18. 24-Bit to 24-Bit Direct True-Color Configuration
8-Bit “ Gam m a” P seudo Color
(CR25, CR26, CR27 = X, 0, 0 or X, 1, 0 or X, 0, 1 and
MR11 = 1)
T his mode sets the part into 8-bit Pseudo-Color operation. T he
pixel port accepts 8 bits of pixel data which indexes a 30-bit
word in the Look-Up T able RAM. T he Look-Up T able is con-
figured as a 256 location by 30 bits deep RAM (10 bits each for
Red, Green and Blue). T he output of the RAM drives the
DACs with 30-bit data (10 bits each for Red, Green and Blue).
CO LO R VID EO MO D ES
T he ADV7152 supports a number of color video modes all at
the maximum video rate. Command bits CR24–CR27 of Com-
mand Register 2 along with Bit MR11 of Mode Register 1 deter-
mine the color mode.
24-Bit “ Gam m a” Tr ue Color
(CR25, CR26, CR27 = 1, 1, 1 and MR11 = 1)
8-BIT TO 30-BIT
30-BIT
8-BIT
ANALOG VIDEO
OUTPUTS
LOOK-UP-TABLE
COLOR DATA
PIXEL DATA
T he part is set to 24-bit/30-bit T rue-Color operation. T he pixel
port accepts 24 bits of color data which is directly mapped to
the Look-Up T able RAM. T he Look-Up T able is configured as
a 256 location by 30 bits deep RAM (10 bits each for Red,
Green and Blue). T he output of the RAM drives the DACs with
30-bit data (10 bits each for Red, Green and Blue). T he RAM is
preloaded with a user determined, nonlinear function, such as a
gamma correction curve.
10
10
10
8
RED
256 x 10
RED
OUT
10-BIT
RED DAC
GREEN
256 x 10
10-BIT
GREEN DAC
GREEN
OUT
BLUE
256 x 10
10-BIT
BLUE DAC
BLUE
OUT
24-BIT TO 30-BIT
LOOK-UP-TABLE
30-BIT
COLOR DATA
24-BIT
PIXEL DATA
ANALOG VIDEO
OUTPUTS
Figure 19. 8-Bit to 30-Bit Pseudo-Color Configuration
10
10
10
8
8
8
RED
256 x 10
RED
OUT
10-BIT
RED DAC
T his mode allows for the display of 256 simultaneous colors out
of a total palette of millions of addressable colors.
GREEN
256 x 10
10-BIT
GREEN DAC
GREEN
OUT
8-Bit “ Standar d” P seudo Color
(CR25, CR26, CR27 = X, 0, 0 or X, 1, 0 or X, 0, 1 and
MR11 = 0)
T his mode sets the part into 8-bit Pseudo-Color operation. T he
pixel port accepts 8 bits of pixel data which indexes a 24-bit
word in the Look-Up T able RAM. T he Look-Up T able is con-
figured as a 256 location by 24 bits deep RAM (10 bits each for
Red, Green and Blue). T he output of the RAM drives the
DACs with 24-bit data (8 bits each for Red, Green and Blue).
BLUE
256 x 10
10-BIT
BLUE DAC
BLUE
OUT
Figure 17. 24-Bit to 30-Bit True-Color Configuration
T his mode allows for the display of full 24-bit, Gamma-
Corrected T rue-Color Images.
8-BIT TO 24-BIT
LOOK-UP-TABLE
24-BIT
COLOR DATA
8-BIT
PIXEL DATA
ANALOG VIDEO
OUTPUTS
24-Bit “ Standar d” Tr ue Color
(CR25, CR26, CR27 = 1, 1, 1 and MR11 = 0)
8
8
8
8
RED
256 x 8
RED
OUT
8-BIT
RED DAC
T his mode sets the part into direct 24-bit T rue-Color operation.
T he pixel port accepts 24 bits of color data which is directly
mapped to Look-Up T able RAM. T he Look-Up T able is con-
figured as a 256 location by 24 bits deep RAM (8 bits each for
Red, Green and Blue) and essentially acts as a bypass RAM.
T he output of the RAM drives the DACs with 24-bit data (8
bits each for Red, Green and Blue). T he RAM is preloaded with
a linear function.
GREEN
256 x 8
8-BIT
GREEN DAC
GREEN
OUT
BLUE
256 x 8
8-BIT
BLUE DAC
BLUE
OUT
T his mode allows for the display of full 24-bit T rue-Color
Images.
Figure 20. 8-Bit to 24-Bit Pseudo-Color Configuration
REV. B
–13–
ADV7152
T his mode allows for the display of 256 simultaneous colors out
of a total palette of millions of addressable colors.
P IXEL P O RT MAP P ING
T he pixel data to the ADV7152 is automatically mapped in the
parts pixel port as determined by the pixel data mode pro-
grammed (Bits CR24–CR27 of Command Register 2).
15-Bit “ Gam m a” Tr ue Color
(CR24, CR25, CR26, CR27 = 0, 0, 1, 1 or 1, 0, 1, 1 and
MR11 = 1)
T he part is set to 15-bit T rue-Color operation. T he pixel port
accepts 15 bits of color data which is mapped to the 5 LSBs of
each of the red, green and blue palettes of the Look-Up T able
RAM. T he Look-Up T able is configured as a 32 location by 30
bits deep RAM (10 bits each for Red, Green and Blue). T he
output of the RAM drives the DACs with 30-bit data (10 bits
each for Red, Green and Blue).
Pixel data in the 24-bit T rue-Color modes is directly mapped to
the 24 color inputs R0–R7, G0–G7 and B0–B7.
R7
0
R4
R3
R2
R1
R0
x
R4
R3
R2
R1
R0
256 x 10 RAM
(RED LUT)
R6
R5
R4
R3
0
0
R4
R3
R2
R1
5
5
5
10
LOCATION "31"
LOCATION "0"
R2
R1
R0
x
x
x
15-BIT TO 30-BIT
LOOK-UP-TABLE
30-BIT
COLOR DATA
15-BIT
PIXEL DATA
ANALOG VIDEO
OUTPUTS
TO
RED
DAC
x
x
R0
10
10
10
5
5
5
RED
32 x 10
RED
OUT
10-BIT
RED DAC
G7
G6
0
0
G4
G3
G2
G1
G0
x
G4
G3
G2
G1
G0
256 x 10 RAM
(GREEN LUT)
GREEN
32 x 10
10-BIT
GREEN DAC
GREEN
OUT
G5
G4
G3
0
G4
G3
G2
G1
G0
BLUE
32 x 10
10-BIT
BLUE DAC
BLUE
OUT
10
LOCATION "31"
LOCATION "0"
G2
G1
G0
x
x
x
TO
GREEN
DAC
x
x
Figure 21. 15-Bit to 30-Bit True-Color Configuration
T his mode allows for the display of 15-bit, Gamma-Corrected
T rue-Color Images.
B7
B6
0
B4
B4
B3
B2
B1
B0
x
256 x 10 RAM
(BLUE LUT)
0
B3
B2
B5
B4
B3
15-Bit “ Standar d” Tr ue Color
(CR24, CR25, CR26, CR27 = 0, 0, 1, 1 or 1, 0, 1, 1 and
MR11 = 0)
T he part is set to 15-bit T rue-Color operation. T he pixel port
accepts 15 bits of color data which is mapped to the 5 LSBs of
each of the red, green and blue palettes of the Look-Up T able
RAM. T he Look-Up T able is configured as a 32 location by 24
bits deep RAM (8 bits each for Red, Green and Blue). T he out-
put of the RAM drives the DACs with 24-bit data (8 bits each
for Red, Green and Blue).
0
B4
B3
B2
B1
B0
B1
B0
x
10
LOCATION "31"
LOCATION "0"
B2
B1
B0
TO
BLUE
DAC
x
x
x
x
PIN
ASSIGN-
MENTS
DATA
LATCHED
TO
DATA
INTERNALLY
SHIFTED
DATA LATCHES
FIRST 32
LOCATIONS
OF RAM
PIXEL
INPUT
DATA
TO 5 LSBS
PIXEL
PORT
15-BIT TO 24-BIT
LOOK-UP TABLE
24-BIT
COLOR DATA
15-BIT
PIXEL DATA
ANALOG VIDEO
OUTPUTS
Figure 23. 15-Bit True-Color Mapping Using R3–R7, G3–G7
and B3–B7
8
8
8
5
5
5
RED
32 x 8
RED
OUT
8-BIT
RED DAC
T here are three modes of operation for 8-bit Pseudo Color.
Each mode maps the input pixel data differently. Data can be
input one of the three color channels, R0–R7 or G0–G7 or
B0–B7.
GREEN
32 x 8
8-BIT
GREEN DAC
GREEN
OUT
T he part has two modes of operation for 15-bit T rue Color. In
the first mode, data is input to the device over the red, green
and blue channel (R3–R7, G3–G7 and B3–B7) and is internally
mapped to locations 0 to 31 of the Look-Up T able (LUT ) ac-
cording to Figure 23. In the second mode, data is input to the
device over just two of the color ports, red and green (R0–R7
and G0–G6) and is internally mapped to LUT locations 0 to 31
according to Figure 24. (Note: Data on unused pixel inputs is
ignored.)
BLUE
32 x 8
8-BIT
BLUE DAC
BLUE
OUT
Figure 22. 15-Bit to 24-Bit True-Color Configuration
T his mode allows for the display of 15-bit T rue-Color Images.
REV. B
–14–
ADV7152
Table II. D atabus Width Table
R7
R6
R4
0
R4
R3
R2
R1
R0
256 x 10 RAM
(RED LUT)
R3
R2
0
D atabus
Width
RAM/D AC
Resolution
Read/Write
Mode
R5
R4
R3
0
R1
R0
G4
G3
G2
R4
R3
R2
R1
10 Bit
10 Bit
8 Bit
10 Bit
8 Bit
10 Bit
8 Bit
10-Bit Parallel
8-Bit Parallel
8+2 Byte
5
10
LOCATION "31"
LOCATION "0"
R2
R1
R0
G4
G3
G2
TO
RED
DAC
8 Bit
8-Bit Parallel
R0
G7
G6
Register Mapping
x
0
0
x
256 x 10 RAM
(GREEN LUT)
T he ADV7152 contains a number of onboard registers includ-
ing the Mode Register (MR17–MR10), Address Register (A7–
A0) and nine Control Registers as well as Red (R9–R0), Green
(G9–G0) and Blue (B9–B0) Color Registers. T hese registers
control the entire operation of the part. Figure 26 shows the
internal register configuration.
G1
G0
B4
B3
G1
G0
B4
B3
B2
B1
B0
G5
G4
G3
0
G4
G3
5
10
LOCATION "31"
LOCATION "0"
G2
G1
G0
B2
G2
G1
G0
TO
GREEN
DAC
B1
B0
Control lines C1 and C0 determine which register the MPU is
accessing. C1 and C0 also determine whether the Address Reg-
ister is pointing to the color registers and look-up table RAM or
the control registers. If C1, C0 = 1, 0, the MPU has access to
whatever control register is pointed to by the Address Register
(A7–A0). If C1, C0 = 0, 1, the MPU has access to the Look-Up
T able RAM (Color Palette) through the associated color regis-
ters. T he CE input latches data to or from the part.
B7
B6
x
0
x
x
x
x
x
256 x 10 RAM
(BLUE LUT)
x
x
0
B5
B4
B3
0
x
x
x
x
x
B4
B3
B2
B1
5
10
LOCATION "31"
LOCATION "0"
B2
B1
B0
x
x
x
TO
BLUE
DAC
T he R/W control input determines between read or write ac-
cesses. T he T ruth T ables III and IV show all modes of access to
the various registers and color palette for both the 8-bit wide
databus configuration and 10-bit wide databus configuration. It
should be noted that after power-up, the devices MPU port is
automatically set to 10-bit wide operation (see Power-On Reset
section).
B0
PIN
ASSIGN-
MENTS
DATA
INTERNALLY
SHIFTED
PIXEL
INPUT
DATA
DATA
LATCHED
TO
PIXEL
PORT
DATA LATCHES
FIRST 32
LOCATIONS
OF RAM
TO 5 LSBS
Figure 24. 15-Bit True-Color Mapping Using R0–R7
and G0–G6
Color P alette Accesses
Data is written to the color palette by first writing to the address
register of the color palette location to be modified. T he MPU
performs three successive write cycles for each of the red, green
and blue registers (10 bit or 8 bit). An internal pointer moves
from red to green to blue after each write is completed. T his
pointer is reset to red after a blue write or whenever the address
register is written. During the blue write cycle, the three bytes of
red, green and blue are concatenated into a single 30-bit/24-bit
word and written to the RAM location as specified in the ad-
dress register (A7–A0). T he address register then automatically
increments to point to the next RAM location and a similar red,
green and blue palette write sequence is performed. T he address
register resets to 00H following a blue write cycle to color pal-
ette RAM location FFH.
MICRO P RO CESSO R (MP U) P O RT
T he ADV7152 supports a standard MPU Interface. All the
functions of the part are controlled via this MPU port. Direct
access is gained to the Address Register, Mode Register and all
the Control Registers as well as the Color Palette. T he follow-
ing sections describe the setup for reading and writing to all of
the devices registers.
MP U Inter face
T he MPU interface (Figure 25) consists of a bidirectional,
10-bit wide databus and interface control signals CE, C0, C1
and R/W. T he 10-bit wide databus is user configurable as
illustrated.
CONTROL REGISTERS
DATA TO
PALETTES
PIXEL MASK
REGISTER
COMMAND
REGISTERS
(CR1–CR3)
COLOR REGISTERS
30
TEST
REGISTERS
MODE
REGISTER
ADDRESS
REGISTER
RED
REGISTER
GREEN
REGISTER
BLUE
REGISTER
REVISION
REGISTER
ADDR
(A7–A0)
(MR1)
ID
REGISTER
MPU PORT
10 (8+2)
D0 – D9
CE R/W C0 C1
Figure 25. MPU Port and Register Configuration
–15–
REV. B
ADV7152
Data is read from the color palette by first writing to the address
register of the color palette location to be read. T he MPU per-
forms three successive read cycles from each of the red, green
and blue locations (10-bit or 8-bit) of the RAM. An internal
pointer moves from red to green to blue after each read is com-
pleted. T his pointer is reset to red after a blue read or whenever
the address register is written. T he address register then auto-
matically increments to point to the next RAM location, and a
similar red, green and blue palette read sequence is performed.
T he address register resets to 00H following a blue read cycle of
color palette RAM location FFH.
Register Accesses
T he MPU can write to or read from all of the ADV7152s regis-
ters. C0 and C1 determine whether the Mode Register or Ad-
dress Register is being accessed. Access to these registers is
direct. T he Control Registers are accessed indirectly. T he
Address Register must point to the desired Control Register.
Figure 28 along with the 8-bit and 10-bit Interface T ruth T ables
illustrate the structure and protocol for device communication
over the MPU port.
C1 = 1
C0 = 1
MODE REGISTER
(MR17–MR10)
ADDRESS REGISTER C1 = 0
(A7–A0)
C0 = 0
C1 = 1
C0 = 0
C1 = 0
C0 = 1
ADDRESS
REGISTER
(A7–A0)
CONTROL
REGISTERS
PIXEL TEST REGISTER
00H
01H
02H
GREEN
REGISTER
(G9–G0)
BLUE
REGISTER
(B9–B0)
RED
REGISTER
(R9–R0)
R
G
B
DAC TEST REGISTER
R
G
B
SYNC, BLANK & IPLL
TEST REGISTER
ID REGISTER (READ ONLY)
PIXEL MASK REGISTER
COMMAND REGISTER 1
COMMAND REGISTER 2
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
LOOK-UP TABLE RAM
(256 x 30)
POINTS TO LOCATION
CORRESPONDING TO
ADDRESS REG (A7–A0)
ADDRESS REG =
ADDRESS REG + 1
COMMAND REGISTER 3
RESERVED
RESERVED
RESERVED
*
*
*
(READ ONLY)
(READ ONLY)
(READ ONLY)
REVISION REGISTER
*
THIS REGISTER IS READ ONLY.
Figure 26. Internal Register Configuration and Address Decoding
Table III. Interface Truth Table (10-Bit D atabus Mode)
R/W
C1
C0
D atabus (D 9–D 0)
O peration
Result
0
0
0
1
0
1
1
0
0
DB7–DB0
DB7–DB0
DB7–DB0
Write to Mode Register
Write to Address Register
Write to Control Registers
DB7–DB0 → MR17–MR10
DB7–DB0 → A7–A0
DB7–DB0 → Control Register
(Particular Control Register Determined by Address Register)
0
0
0
0
0
0
1
1
1
DB9–DB0
DB9–DB0
DB9–DB0
Write to RED Register
Write to GREEN Register
Write to BLUE Register
DB9–DB0 → R9–R0
DB9–DB0 → G9–G0
DB9–DB0 → B9–B0
Write RGB Data to RAM Location Pointed to by Address Register (A7–A0)
Address Register = Address Register + 1
1
1
1
1
0
1
1
0
0
DB7–DB0
DB7–DB0
DB7–DB0
Read Mode Register
Read Address Register
Read Control Registers
MR17–MR10 → DB7–DB0
A7–A0 → DB7–DB0
Register Data → DB7–DB0
(Particular Control Register Determined by Address Register)
1
1
1
0
0
0
1
1
1
DB9–DB0
DB9–DB0
DB9–DB0
Read RED RAM Location
Read GREEN RAM Location
Read BLUE RAM Location
R9–R0 → DB9–DB0
G9–G0 → DB9–DB0
B9–B0 → DB9–DB0
(RAM Location Pointed to by Address Reg (A7–A0))
Address Register = Address Register + 1
DB = Data Bit.
REV. B
–16–
ADV7152
Table IV. Interface Truth Table (8-Bit D atabus Mode)*
O peration Result
D atabus
(D 9–D 0)
R/W
C1
C0
0
0
0
1
0
1
1
0
0
DB7–DB0
DB7–DB0
DB7–DB0
Write to Mode Register
Write to Address Register
Write to Control Registers
DB7–DB0 → MR17–MR10
DB7–DB0 → A7–A0
DB7–DB0 → Control Registers
(Particular Control Register Determined by Address Register (A7–A0))
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
DB9–DB2
DB1–DB0
DB9–DB2
DB1–DB0
DB9–DB2
DB1–DB0
Write to RED Register
Write to RED Register
Write to GREEN Register
Write to GREEN Register
Write to BLUE Register
Write to BLUE Register
DB9–DB2 → R9–R2
DB1–DB0 → R1–R0
DB9–DB2 → G9–G2
DB1–DB0 → G1–G0
DB9–DB2 → B9–B2
DB1–DB0 → B1–B0
Write RGB Data to RAM Location Pointed to by Address Register (A7-A0)
Address Register = Address Register + 1
1
1
1
1
0
1
1
0
0
DB7–DB0
DB7–DB0
DB7–DB0
Read Mode Register
Read Address Register
Read Control Registers
MR17–MR10 → DB7–DB0
A7–A0 → DB7–DB0
Register Data → DB7–DB0
(Particular Control Register Determined by Address Register)
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
DB9–DB2
DB1–DB0
DB9–DB2
DB1–DB0
DB9–DB2
DB1–DB0
Read RED RAM Location
Read RED RAM Location
Read GREEN RAM Location
Read GREEN RAM Location
Read BLUE RAM Location
Read BLUE RAM Location
R9–R2 → DB9–DB2
R1–R0 → DB1–DB0
G9–G2 → DB9–DB2
G1–G0 → DB1–DB0
B9–B2 → DB9–DB2
B1–B0 → DB1–DB0
(RAM Location Pointed to by Address Register (A7–A0))
Address Register = Address Register + 1
*Writing or reading 10-bit data (DB9–DB0) over an 8-bit databus (D7–D0) requires two write or two read cycles.
:DB9–DB2 is mapped to D7–D0 on the first cycle.
:DB1–DB0 is mapped to D1–D0 on the second cycle.
DB = Data Bit.
P ower -O n Reset
T he output clocking signals are also set during this reset period.
On power-up of the ADV7152 executes a power-on reset opera-
tion. T his initializes the pixel port such that the pixel sequence
AB starts at A. T he Mode Register (MR17–MR10), Command
Register 2 (CR27–CR20) and Command Register 3 (CR37–
CR30) have all bits set to a Logic “1.” Command Register 1
(CR17–CR10) has all bits set to a Logic “0.”
PRGCKOUT = CLOCK/32
LOADOUT = CLOCK/2
T he power-on reset is activated when VAA goes from 0 V to
5 V. T his reset is active for 1 µs. T he ADV7152 should not be
accessed during this reset period. T he pixel clock should be
applied at power-up.
REV. B
–17–
ADV7152
REGISTER P RO GRAMMING
MP U D atabus Width (MR12)
T he following section describes each register, including Address
Register, Mode Register and each of the nine Control Registers
in terms of its configuration.
T his bit determines the width of the MPU port. It is configured
as either a 10-bit wide (D9–D0) or 8-bit wide (D7–D0) bus.
10-bit data can be written to the device when configured in
8-bit wide mode. T he 8 MSBs are first written on D7–D0, then
the two LSBs are written over D1–D0. Bits D9–D8 are zeros in
8-bit mode.
Addr ess Register (A7–A0)
As illustrated in the previous tables, the C0 and C1 control in-
puts, in conjunction with this address register specify which con-
trol register, or color palette location is accessed by the MPU
port. T he address register is 8-bits wide and can be read from as
well as written to. When writing to or reading from the color
palette on a sequential basis, only the start address needs to be
written. After a red, green and blue write sequence, the address
register is automatically incremented.
O per ational Mode Contr ol (MR14–MR13)
When MR14 is “0” and MR13 is “1,” the part operates in
normal mode.
Calibr ate LO AD IN (MR15)
This bit automatically calibrates the onboard LOADIN/
LOADOUT synchronization circuit. A “0” to “1” transition
initiates calibration. T his bit is set to “0” in normal operation.
See “Pipeline Delay and Calibration” section. T his bit must be
run through this cycle during the initialization sequence.
MO D E REGISTER MR1 (MR19–MR10)
T he mode register is a 10-bit wide register. However for pro-
gramming purposes, it may be considered as an 8-bit wide regis-
ter (MR18 and MR19 are both reserved). It is denoted as
MR17–MR10 for simplification purposes.
P alette Select Match Bits Contr ol (MR17–MR16)
T hese bits allow multiple palette devices to work together.
When bits PSI and PS0 match MR17 and MR16 respectively,
the device is selected. If these bits do not match, the device is
not selected and the analog video outputs drive 0 mA, see
“Palette Priority Select Inputs” section.
T he diagram shows the various operations under the control of
the mode register. T his register can be read from as well written
to. In read mode, if MR18 and MR19 are read back, they are
both returned as zeros.
Contr ol Register s
T he ADV7152 has 9 control registers. T o access each register,
two write operations must be performed. T he first write to the
address register specifies which of the 9 registers is to be ac-
cessed. T he second access determines the value written to that
particular control register.
MO D E REGISTER (MR17–MR10) BIT D ESCRIP TIO N
Reset Contr ol (MR10)
T his bit is used to reset the pixel port sampling sequence. T his
ensures that the pixel sequence AB starts at A. It is reset by writ-
ing a “1” followed by a “0” followed by a “1.” T his bit must be
run through this cycle during the initialization sequence.
P ixel Test Register
(Addr ess Reg (A7–A0) = 00H )
RAM-D AC Resolution Contr ol (MR11)
T his register is used when the device is in test/diagnostic mode.
It is a 24-bit (8 bits each for RED, GREEN and BLUE) wide
read-only register which allows the MPU to read data on the
pixel port, see “T est Diagnostic” section.
When this is programmed with a “1,” the RAM is 30 bits deep
(10 bits each for red, green and blue) and each of the three
DACs is configured for 10-bit resolution. When MR11 is pro-
grammed with a “0,” the RAM is 24 bits deep (8 bits each for
red, green and blue) and the DACs are configured for 8-bit
resolution. T he two LSBs of the 10-bit DACs are pulled down
to zero in 8-bit RAM-DAC mode.
MR19
MR18
MR17 MR16
MR15
MR12
MR10
MR14 MR13
MR11
CALIBRATE
LOADIN
MPU DATA BUS
WIDTH
RESERVED*
MR12
MR15
PALETTE SELECT
MATCH BITS CONTROL
0
1
8-BIT (D7–D0)
10-BIT (D9–D0)
MR16
MR17
PS0
PS1
RAM-DAC
RESOLUTION CONTROL
OPERATIONAL MODE CONTROL
MR14 MR13
MR11
0
1
8-BIT
10-BIT
0
0
1
1
0
1
0
1
RESERVED
NORMAL OPERATION
RESERVED
RESET CONTROL
MR10
RESERVED
*
THESE BITS ARE READ-ONLY RESERVED BITS.
A READ CYCLE WILL RETURN ZEROS "00."
Mode Register 1 (MR1) (MR19–MR10)
REV. B
–18–
ADV7152
D AC Test Register
(Addr ess Reg (A7–A0) = 01H )
CO MMAND REGISTER 1 (CR1)
(Addr ess Reg (A7–A0) = 05H )
T his register is used when the device is in test/diagnostic mode.
It is a 30-bit (10 bits each for RED, GREEN and BLUE) wide
read-only register which allows MPU access to the DAC port,
see “T est Diagnostic” section.
T his register contains a number of control bits as shown in the
diagram. CR1 is a 10-bit wide register. However for program-
ming purposes, it may be considered as an 8-bit wide register
(CR18 to CR19 are reserved).
SYNC, BLANK and IP LL Test Register
(Addr ess Reg (A7–A0) = 02H )
T his register is used when the device is in test/diagnostic mode.
It is a 3-bit wide (3 LSBs) read/write register which allows
MPU access to these particular pixel control bits, see “T est
Diagnostic” section.
T he diagram below shows the various operations under the con-
trol of CR1. This register can be read from as well as written to. In
write mode, “0” should be written to CR11 and CR13–CR17.
In read mode, CR11 and CR13–CR19 are returned as zeros.
CO MMAND REGISTER 1 BIT D ESCRIP TIO N
Calibr ation Contr ol (CR10)
This bit automatically calibrates the onboard LOAD IN /
LOADOUT synchronization circuit. MR15 of Mode Register
MR1 must be set to “0.”
ID Register
(Addr ess Reg (A7–A0) = 03H )
T his is an 8-bit wide “Identification” read-only register. For the
ADV7152 it will always return the hexadecimal value 8CH.
SYNCOUT Contr ol (CR12)
P ixel Mask Register (Addr ess Reg (A7–A0) = 04H )
T he contents of the pixel mask register are individually bit-wise
logically AND-ed with the Red, Green and Blue pixel input
stream of data. It is an 8-bit read/write register with D0 corre-
sponding to R0, G0 and B0. For normal operation, this register
is set with FFH.
T his bit specified whether the video SYNCOUT signal is to be
enabled. On power up a “0” is written to the bit and
“SYNCOUT” is set three-state.
CR12
CR19
CR17
CR15
CR14
CR13
CR11
CR10
CR18
CR16
RESERVED *
SYNCOUT CONTROL
CR12
CR17–CR13
(00000)
CR11
(0)
0
1
DISABLE
THESE BITS
SHOULD BE
SET TO ZERO
THIS BIT
SHOULD BE
SET TO ZERO
ENABLE
SYNCOUT
CALIBRATION CONTROL
CR10
THESE BITS ARE READ-ONLY RESERVED BITS.
A READ CYCLE WILL RETURN ZEROS "00."
*
0
1
DISABLE
CALIBRATES
ON EVERY
VERTICAL
SYNC
(MR15=0)
Com m and Register 1 (CR1) (CR19–CR10)
REV. B
–19–
ADV7152
IP LL Tr igger Contr ol (CR21)
CO MMAND REGISTER 2 (CR2)
T his bit specifies whether the IPLL output is triggered from
BLANK or SYNC.
(Addr ess Reg (A7–A0) = 06H )
T his register contains a number of control bits as shown in the
diagram. CR2 is a 10-bit wide register. However for program-
ming purposes, it may be considered as an 8-bit wide register
(CR28 and CR29 are both reserved).
SYNC Recognition Contr ol (CR22)
T his bit specifies whether the video SYNC input is to be
encoded onto the IOG analog output or ignored.
T he diagram shows the various operations under the control of
CR2. T his register can be read from as well written to. In read
mode, CR28 and CR29 are both returned as zeros.
P edestal Enable Contr ol (CR23)
T his bit specifies whether a 0 IRE or a 7.5 IRE blanking pedes-
tal is to be generated on the video outputs.
Tr ue-Color /P seudo-Color Mode Contr ol (CR27–CR24)
T hese 4 bits specify the various color modes. T hese include a
24-bit true-color mode, two 15-bit true-color modes and three
8-bit pseudo color modes.
CO MMAND REGISTER 2 BIT D ESCRIP TIO N
R7 Tr igger P olar ity Contr ol (CR20)
T his bit determines whether the pixel data is latched into the
test registers on the rising or falling edge of R7, see “T est Diag-
nostics” section in Appendix 3.
CR27 CR26 CR25 CR24
CR23
CR22
CR21
CR20
CR29 CR28
PEDESTAL
ENABLE
CONTROL
SYNC
RECOGNITION
CONTROL
RESERVED
*
*
THESE BITS ARE READ–ONLY
RESERVED BITS.
A READ CYCLE WILL
CR22
CR23
0
1
IGNORE
DECODE
0
1
0 IRE
7.5 IRE
RETURN ZEROS "00."
I
TRIGGER
TRUE-COLOR / PSEUDO-COLOR MODE CONTROL
PLL
CONTROL
COLOR MODE
CR27 CR26 CR25 CR24
CR21
8-BIT PSEUDO COLOR ON R7–R0
8-BIT PSEUDO COLOR ON G7–G0
8-BIT PSEUDO COLOR ON B7–B0
15-BIT TRUE COLOR ON
R7–R3, G7–G3,B7–B3
0
1
0
1
0
0
0
0
0
0
0
0
0
0
1
1
0
1
SYNC
BLANK
15-BIT TRUE COLOR ON
R7–R0, G6–G0
24-BIT TRUE COLOR
1
1
0
1
1
0
1
1
R7 TRIGGER
POLARITY CONTROL
R7–R0, G7–G0, B7–B0
CR20
0
1
Com m and Register 2 (CR2) (CR29–CR20)
REV. B
–20–
ADV7152
CO MMAND REGISTER 3 (CR3)
(Addr ess Reg (A7–A0) = 07H )
T his register contains a number of control bits as shown in the
diagram. CR3 is a 10-bit wide register. However for program-
ming purposes, it may be considered as an 8-bit wide register
(CR38 and CR39 are both reserved).
BLANK P ipeline D elay Contr ol (CR35–CR32)
T hese bits specify the additional pipeline delay that can be
added to the BLANK function, relative to the overall device
pipeline delay (tPD). As the BLANK control normally enters the
video DAC from a shorter pipeline than the video pixel data,
this control is useful in deskewing the pipeline differential.
T he diagram shows the various operations under the control of
CR3. T his register can be read from as well written to. In read
mode, CR38 and CR39 are both returned as zeros.
P ixel Multiplex Contr ol (CR36)
T hese bits specify the device’s multiplex mode. It, therefore,
also determines the frequency of the LOADOUT signal.
LOADOUT is a divided down version of the pixel CLOCK.
CO MMAND REGISTER 3-BIT D ESCRIP TIO N
P RGCKO UT Fr equency Contr ol (CR31–CR30)
T hese bits specify the output frequency of the PRGCKOUT
output. PRGCKOUT is a divided down version of the pixel
CLOCK.
Revision Register
(Addr ess Reg (A7–A0) = 0BH )
T his register is a read only register containing the revision of
silicon.
CR37
CR31
CR38
CR36
CR35 CR34
CR33 CR32
CR30
CR39
EXTRA BLANK PIPELINE DELAY CONTROL
(ADDS TO PIXEL PIPELINE DELAY;
RESERVED*
t
)
PD
*
THESE BITS ARE READ-ONLY
RESERVED BITS.
A READ CYCLE WILL RETURN
ZEROS "00".
CR35 CR34 CR33 CR32
BLANK PIPELINE DELAY
0
0
0
–
–
1
0
0
0
–
–
1
0
0
1
–
–
1
0
1
0
–
–
1
tPD
tPD + 1 x LOADOUT
tPD + 2 x LOADOUT
–
–
–
–
–
–
tPD + 15 x LOADOUT
PRGCKOUT
FREQUENCY CONTROL
PIXEL MULTIPLEX CONTROL
CR37 CR36
CR31 CR30
0
0
1
1
0
1
0
1
1:1 MUXING: LOADOUT = CLOCK ÷1
2:1 MUXING: LOADOUT = CLOCK ÷2
RESERVED
0
0
1
1
0
1
0
1
CLOCK ÷4
CLOCK ÷8
CLOCK ÷16
CLOCK ÷32
RESERVED
Com m and Register 3 (CR3) (CR39–CR30)
REV. B
–21–
ADV7152
IOR, IOG, IOB
D IGITAL-TO -ANALO G CO NVERTERS
(D ACS) AND VID EO O UTP UTS
Z
= 75Ω
O
DACs
Z
=75Ω
(CABLE)
Z
= 75Ω
S
L
T he ADV7152 contains three high speed video DACs. T he
DAC outputs are represented as the three primary analog color
signals IOR (red video), IOG (green video) and IOB (blue video).
Other analog signals on the part include IPLL and VREF as well as
complementary video outputs IOR, IOG, IOB. T hese comple-
mentary outputs can be used to drive differentially terminated
video loads, they will have equal but opposite output levels to
IOR, IOG and IOB when loaded with a resistive load similar to
IOR, IOG and IOB.
(SOURCE
(MONITOR)
TERMINATION)
Figure 27. DAC Output Term ination (Doubly Term inated
75 Ω Load)
Refer ence Input and RSET
An external 1.23 V voltage reference is required to drive the
analog outputs of the ADV7152. T he reference voltage is con-
nected to the VREF input.
D ACs and Analog O utputs
T he part contains three matched 10-bit digital-to-analog con-
verters. T he DACs are designed using an advanced, high speed,
segmented architecture. T he bit currents corresponding to each
digital input are routed to either IOR, IOG, IOB (bit = “1”) or
IOR, IOG, IOB (bit = “0”). (Normally IOR, IOG, IOB = GND.)
A resistor RSET is connected between the RSET input of the part
and ground. For specified performance, RSET has a value of
280 Ω. T his corresponds to the generation of RS-343A video
levels (with SYNC on IOG and Pedestal = 7.5 IRE) into a dou-
bly terminated 75 Ω load. Figure 28 illustrates the resulting
video waveform, and the Video Output T ruth T able shows the
corresponding control input stimuli.
T he analog video outputs are high impedance current sources.
Each of the these three RGB current outputs are specified to
directly drive a 37.5 Ω load (doubly terminated 75 Ω).
IOR, IOB
IOG
mA
V
V
mA
1.000
WHITE LEVEL
19.05
26.67
0.714
92.5 IRE
BLACK LEVEL
BLANK LEVEL
1.44
0
0.054
0
0.340
0.286
9.05
7.62
7.5 IRE
40 IRE
0
0
SYNC LEVEL
Figure 28. Com posite Video Waveform (SYNC Decoded on IOG; Pedestal = 7.5 IRE; RSET = 280 Ω)
Table V. Video O utput Truth Table
IO G
(m A)
IO R, IO B
(m A)
D AC
Input D ata
D escription
SYNC
BLANK
WHIT E LEVEL
VIDEO
26.67
Video + 9.05
Video + 1.44
9.05
1.44
7.62
0
19.05
Video + 1.44
Video + 1.44
1.44
1.44
0
1
1
0
1
0
1
0
1
1
1
1
1
0
0
3FFH
Data
Data
000H
000H
xxxH
xxxH
VIDEO to BLANK
BLACK LEVEL
BLACK to BLANK
BLANK LEVEL
SYNC LEVEL
0
REV. B
–22–
ADV7152
IOR, IOB, IOG
mA
19.05 0.714
Var iations on RS-343A
V
Various other video output configurations can be implemented
by the ADV7152, including RS-170. Values of RSET for particu-
lar output video formats/levels are calculated by using the equa-
tions for RSET given in the “Pin Configuration” section. T he
table shows calculated values of RSET for some of the most com-
mon variants on the RS-343A standard. T he associated wave-
forms are shown in the diagrams.
WHITE LEVEL
100 IRE
GREY SCALE
RSET (⍀)
Video Signal
BLACK/ BLANK
LEVEL
0
0
265
280
259
SYNC decoded on IOG; Pedestal = 0 IRE
No SYNC decoded; Pedestal = 7.5 IRE
No SYNC decoded; Pedestal = 0 IRE
Figure 31. Com posite Video Waveform
(Pedestal = 0 IRE; RSET = 259 Ω)
IP LL Synchr onization O utput Contr ol
IOR, IOB
IOG
mA
18.62 0.698 26.67
mA
V
V
T his output synchronization signal is used in applications where
it is necessary to synchronize multiple palette devices (ADV7150
+ ADV7151) to subpixel resolution. Each devices IPLL output
signal is in phase with its analog RGB output signal. If multiple
devices have differing output delays, the time difference can be
derived from the IPLL signals. T his time difference is then used
to phase shift the CLOCK inputs on one or other of the devices
inputs.
WHITE
LEVEL
1.000
100 IRE
GREY SCALE
BLACK/BLANK
LEVEL
0.302
0
0
0
8.05
0
T he IPLL signal is internally triggered by either the falling edge
of SYNC or BLANK as determined by CR21 of Command
Register 2.
43 IRE
SYNC
LEVEL
Figure 29. Com posite Video Waveform (SYNC
Decoded on IOG; Pedestal = 0 IRE; RSET = 265 Ω)
IOR, IOB, IOG
mA
V
WHITE LEVEL
19.05 0.714
92.5 IRE
GREY SCALE
BLACK LEVEL
BLANK LEVEL
0.054
0
1.44
0
7.5 IRE
Figure 30. Com posite Video Waveform
(Pedestal = 7.5 IRE; RSET = 280 Ω)
REV. B
–23–
ADV7152
AP P END IX 1
BO ARD D ESIGN AND LAYO UT CO NSID ERATIO NS
T he ADV7152 is a highly integrated circuit containing both
precision analog and high speed digital circuitry. It has been
designed to minimize interference effects on the integrity of the
analog circuitry by the high speed digital circuitry. It is impera-
tive that these same design and layout techniques be applied to
the system level design such that high speed, accurate perfor-
mance is achieved. The “Recommended Analog Circuit Layout”
shows the analog interface between the device and monitor.
It is important to note that while the ADV7152 contains cir-
cuitry to reject power supply noise, this rejection decreases with
frequency. If a high frequency switching power supply is used,
the designer should pay close attention to reducing power sup-
ply noise and consider using a three terminal voltage regulator
for supplying power to the analog power plane.
D igital Signal Inter connect
The digital inputs to the ADV7152 should be isolated as much
as possible from the analog outputs and other analog circuitry.
Also, these input signals should not overlay the analog power
plane.
The layout should be optimized for lowest noise on the ADV7152
power and ground lines by shielding the digital inputs and pro-
viding good decoupling. T he lead length between groups of VAA
and GND pins should by minimized so as to minimize inductive
ringing.
Due to the high clock rates involved, long clock lines to the
ADV7152 should be avoided to reduce noise pickup.
Gr ound P lanes
Any active termination resistors for the digital inputs should be
connected to the regular PCB power plane (VCC), and not the
analog power plane.
T he ground plane should encompass all ADV7152 ground pins,
voltage reference circuitry, power supply bypass circuitry for the
ADV7152, the analog output traces, and all the digital signal
traces leading up to the ADV7152. T he ground plane is the
graphics board’s common ground plane.
Analog Signal Inter connect
T he ADV7152 should be located as close as possible to the out-
put connectors to minimize noise pick-up and reflections due to
impedance mismatch.
P ower P lanes
T he ADV7152 and any associated analog circuitry should have
its own power plane, referred to as the analog power plane (VAA).
T his power plane should be connected to the regular PCB
power plane (VCC) at a single point through a ferrite bead. T his
bead should be located within three inches of the ADV7152.
T he video output signals should overlay the ground plane, and
not the analog power plane, to maximize the high frequency
power supply rejection.
Digital Inputs, especially Pixel Data Inputs and clocking signals
(CLOCK, LOADOUT , LOADIN, etc.) should never overlay
any of the analog signal circuitry and should be kept as far away
as possible.
T he PCB power plane should provide power to all digital logic
on the PC board, and the analog power plane should provide
power to all ADV7152 power pins and voltage reference circuitry.
For best performance, the analog outputs (IOR, IOG, IOB)
should each have a 75 Ω load resistor connected to GND.
T hese resistors should be placed as close as possible to the
ADV7152 so as to minimize reflections. Normally, the differen-
tial analog outputs (IOR, IOG, IOB) are connected directly to
GND. In some applications, improvements in performance are
achieved by terminating these differential outputs with a resis-
tive load similar in value to the video load. For a doubly termi-
nated 75 Ω load, this means that IOR, IOG, IOB are each
terminated with 37.5 Ω resistors.
Plane-to-plane noise coupling can be reduced by ensuring that
portions of the regular PCB power and ground planes do not
overlay portions of the analog power plane, unless they can be
arranged such that the plane-to-plane noise is common mode.
Supply D ecoupling
For optimum performance, bypass capacitors should be installed
using the shortest leads possible, consistent with reliable opera-
tion, to reduce the lead inductance. Best performance is obtained
with 0.1 µF ceramic capacitor decoupling. Each group of VAA
pins on the ADV7152 must have at least one 0.1 µF decoupling
capacitor to GND. T hese capacitors should be placed as close
as possible to the device.
REV. B
–24–
ADV7152
POWER SUPPLY DECOUPLING (0.1µF AND 0.01µF CAPACITOR FOR EACH VAA GROUP)
0.1µF
0.01µF
0.01µF
0.01µF
0.01µF
0.1µF
0.1µF
0.1µF
+5V (VCC
)
+5V (VAA
)
ANALOG POWER PLANE
+5V (VAA
1kΩ
L1
+5V (VAA
)
)
0.1µF
33µF
(FERRITE BEAD)
VAA
0.1µF
0.1µF
(1% METAL)
COMP
VREF
RSET
AD589
(1.2V REF)
RSET
280Ω
ADV7152
CO-AXIAL CABLE
(75Ω)
75Ω
75Ω
75Ω
IOR
MONITOR
(CRT)
IOG
IOB
75Ω
75Ω
75Ω
BNC
CONNECTORS
IOR
IOG
COMPLIMENTARY
OUTPUTS
NOTES:
1. ALL RESISTORS ARE 1% METAL FILM
2. 0.1µF AND 0.01µF CAPACITORS ARE CERAMIC
3. ADDITIONAL DIGITAL CIRCUITRY OMITTED FOR CLARITY
IOB
IPLL
GND
Recom m ended Analog Circuit Layout
AP P END IX 2
TYP ICAL FRAME BUFFER INTERFACE
CLOCK
ECL
TO
TTL
CLOCK GENERATOR
CLOCK
PRGCKOUT
LOADOUT
DIVIDE BY N
DIVIDE BY M
(+M)
(÷ N)
SCKOUT
CLOCK
LATCH
BLANK
SYNC
GRAPHICS
PROCESSOR/
CONTROLLER
BLANK
ENABLE
SYNC
SCKIN
LOADIN
ADV7152
24
24
24
VRAM
(BANK A)
24
TO
FRAME
BUFFER/
MULTIPLEXER
PALETTE/RAM
& DAC
24
VIDEO MEMORY
VRAM
(BANK B)
REV. B
–25–
ADV7152
AP P END IX 3
10-BIT D ACS AND GAMMA CO RRECTIO N
10-Bit D ACs
Gam m a Correction 8 Bits vs. 10 Bits
Gam m a
10-bit RAM-DAC resolution allows for nonlinear video correc-
tion, in particular Gamma Correction. T he ADV7152 allows for
an increase in color resolution from 24-bit to 30-bit effective
color without the necessity of a 30-bit deep frame buffer. In
true-color mode, for example, the part effectively operates as a
24-bit to 30-bit color look-up table.
Corrected
(2.7)
Quantized to
8 Bits
Quantized to
10 Bits
8-Bit D ata
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
0.977797
0.979304
0.980807
0.982306
0.983801
0.985292
0.986780
0.988264
0.989744
0.991220
0.992693
0.994161
0.995626
0.997088
0.998546
1.000000
250
250
251
251
25 1
252
252
252
253
253
254
254
254
255
255
255
1001
1002
1004
1005
1007
1008
1010
1011
1013
1015
1016
1018
1019
1021
1022
1023
Up to now we have assumed that there exists a linear relation-
ship between the actual RGB values input to a monitor and the
intensity produced on the screen. T his, however, is not the case.
Half scale digital input (1000 0000) might correspond to only
20% output intensity on the CRT (Cathode Ray T ube). T he in-
tensity (ICRT ) produced on a CRT by an input value IIN is given
by:
χ
ICRT = (IIN
where χ ranges from 2.0 to 2.8.
)
If the individual values of χ for red, green and blue are known,
then so called “Gamma Correction” can be applied to each of
the three video input signals (IIN);
therefore:
1/χ
IIN(corrected) = k(IIN
)
(k = 1, normally)
1.00
0.90
0.80
0.70
0.60
0.50
0.40
0.30
0.20
0.10
0.00
T raditionally, there has been a tradeoff between implementing a
nonlinear graphics function, such as gamma correction, and
color dynamic range. T he ADV7152 overcomes this by increas-
ing the individual color resolution of each of the red, green and
blue primary colors from 8 bits per color channel to 10 bits per
channel (24 bits to 30 bits).
T he table highlights the loss of resolution when 8-bit data is
gamma-corrected to a value of 2.7 and quantized in a tradi-
tional 8-bit system. Note that there is no change in the 8-bit
quantized data for linear changes in the input data over much of
the transfer function. On the other hand, when quantized to 10
bits via the 10-bit RAMs and 10-bit DACs of the ADV7152, all
changes on the input 8-bit data are reflected in corresponding
changes in the 10-bit data.
0
32
64
96
128
160
192
224
256
INPUT CODE – Decimal
T he graph shows a typical gamma curve corresponding to a
gamma value of 2.7. T his is programmed to the red, green and
blue RAMs of the color lookup table instead of the more tradi-
tional linear function. Different curves corresponding to any
particular gamma value can be independently programmed to
each of the red, green and blue RAMs.
Gam m a Correction Curve (Gam m a Value = 2.7)
Other applications of the 10-bit RAM-DAC include closed-loop
monitor color calibration.
REV. B
–26–
ADV7152
AP P END IX 4
MULTIP LE P ALETTE AP P LICATIO NS
P alette P r ior ity Select Inputs
Note: Only one palette device is selected at any particular
instant. T he analog output levels of the unselected devices will
be 0 mA.
T he palette priority selection inputs allow up to four separate
palette devices to be used in a single system to drive a single
monitor. T he IOR, IOG and IOB analog video output signals of
each device are connected together, as shown. Signal inputs
(PS0, PS1) determine on a pixel by pixel basis which palette
device drives the monitor. T his allows for implementation of
multiple windows applications with each device acting as an
independent palette. During initialization, each device is as-
signed two match bits, MR16 (PS0) and MR17 (PS1) in Mode
Register MR1. PS0 and PS1 inputs will select one of the prepro-
grammed devices at any instant when PS0, PS1 matches MR16,
MR17, respectively. When PS0 and PS1 do not match these
bits, the DACs of the particular device are shut down, driving
RGB outputs to 0 mA. PS0 and PS1 are multiplexed similar to
the pixel data, thus allowing for subpixel resolution. T he dia-
grams show an example of one ADV7152 operating in conjunc-
tion with three ADV7151’s (Pseudo-Color RAM-DACs). Each
displayed window on the monitor is driven by one of the four
devices. Each device’s analog output signals are connected to-
gether as shown.
Other applications for the palette priority function using a mini-
mum of two devices (two ADV7152s or one ADV7152 and one
ADV7151) include:
Cursor Overlay on 24-Bit Graphics
Active Live Video Overlay (from Frame Grabber)
T ext/Character Generation and Overlay
(DEVICE: 2)
IOR, IOG, IOB
DACs
(DEVICE: 1)
IOR, IOG, IOB
Z
=75Ω
O
DACs
Z
= 75Ω
(CABLE)
S
Z = 75Ω
L
(SOURCE
(MONITOR)
TERMINATION)
Multiple Devices Term ination for a Single Monitor
ADV7152
RGB
R0–R7
ANALOG
256 x 30
RAM
VIDEO
G0–G7
B0–B7
PALETTE SELECT BITS
MR16 MR17
PS0, PS1
P0–P7
0
0
ADV7151 (1)
RGB
ANALOG
VIDEO
256 x 30
PALETTE
MONITOR
TRUE-COLOR BACKGROUND
PS0 = 0: PS1 = 0
PALETTE SELECT BITS
MR16 MR17
0
1
WINDOW 1
(Pseudo-Color)
PS0 = 0: PS1 = 1
WINDOW 3
(Pseudo-Color)
PS0 = 1: PS1 = 1
VIDEO TO MONITOR
ADV7151 (2)
WINDOW 2
(Pseudo-Color)
PS0 = 1: PS1 = 0
256 x 30
PALETTE
RGB
ANALOG
VIDEO
PALETTE SELECT BITS
MR16 MR17
1
0
ADV7151 (3)
256 x 30
PALETTE
PALETTE SELECT BITS
MR16 MR17
RGB
ANALOG
VIDEO
1
1
Multiple Devices Driving a Multiwindow Application
–27–
REV. B
ADV7152
AP P END IX 5
INITIALIZATIO N AND P RO GRAMMING
AD V7152 Initialization
T he following section gives examples of initialization of the
ADV7152 operating in various modes.
After power has been supplied, the ADV7152 must be initial-
ized. T he Mode Register and Control Registers must be set.
T he values written to the various registers will be determined by
the desired operating mode of the part, i.e., T rue Color/Pseudo
Color, 2:1 Muxing/2:1 Muxing, etc.
Exam ple 1
Color Mode
Multiplexing
Databus
24-Bit True Color
2:1
8-Bit
RAM-DAC Resolution
SYNC
Pedestal
8-Bit
Enabled on IOG
7.5 IRE
Register Initialization
C1
1
1
1
1
1
0
1
0
1
0
1
0
C0
1
1
1
1
1
0
0
0
0
0
0
0
R/W
Com m ent
Write 09H to Mode Register (MR1)
Write 08H to Mode Register (MR1)
Write 09H to Mode Register (MR1)
Write 29H to Mode Register (MR1)
Write 09H to Mode Register (MR1)
Write 04H to Address Register (A7–A0)
Write FFH to Pixel Mask Register
Write 05H to Address Register (A7–A0)
Write 00H to Command Reg 1 (CR1)
Write 06H to Address Register (A7–A0)
Write ECH to Command Reg 2 (CR2)
Write 07H to Address Register (A7–A0)
Write 40H to Command Reg 3 (CR3)
0
0
0
0
0
0
0
0
0
0
0
0
0
Resets to Normal Operation, 8-Bit Bus/RAM-DAC
*(Initializes Pipelining
*( “
*(Calibrates LOADOUT /LOADIN T iming
*( “
Address Reg Points to Pixel Mask Register
Sets the Pixel Mask to All “1s”
Address Reg Points to Command Register 1 (CR1)
Address Reg Points to Command Register 2 (CR2)
Sets 24-Bit Color, 7.5 IRE, SYNC on Green (IOG)
Address Reg Points to Command Register 3 (CR3)
Sets 2:1 Multiplexing, PRGCKOUT = CLOCK/4
1
0
Color P alette RAM Initialization
Write 00H to Address Register (A7–A0)
C1
0
0
0
0
0
0
0
•
C0
0
1
1
1
1
1
1
•
R/W
Com m ent
Points to Color Palette RAM
(Initializes Palette RAM
0
0
0
0
0
0
0
•
Write 00H (Red Data) to RAM Location (00H)
Write 00H (Green Data) to RAM Location (00H)
Write 00H (Blue Data) to RAM Location (00H)
Write 01H (Red Data) to RAM Location (01H)
Write 01H (Green Data) to RAM Location (01H)
Write 01H (Blue Data) to RAM Location (01H)
(
(
(
(
(
(
(
(
(
to a Linear Ramp**
•
•
•
•
•
•
•
•
•
•
•
•
•
Write FFH (Red Data) to RAM Location (FFH)
Write FFH (Green Data) to RAM Location (FFH)
Write FFH (Blue Data) to RAM Location (FFH)
0
0
0
1
1
1
0
0
0
(RAM Initialization Complete
**T hese four command lines reset the ADV7152. T he pipelines for each of the Red, Creen and Blue pixel inputs are synchronously reset to the Multiplexer’s
“A” input. Mode Register bit MR10 is written by a “1” followed by “0” followed by “1.” LOADIN/LOADOUT timing is internally synchronized by writing a “0”
followed by a “1” followed by a “0” to Mode Register MR15.
**T his sequence of instructions would, of course, normally be coded using some form of loop instruction.
REV. B
–28–
ADV7152
Exam ple 2
Color Mode
Multiplexing
Databus
24-Bit Gamma Corrected True Color (30 Bits)
2:1
10-Bit
RAM-DAC Resolution 10-Bit
SYNC
Ignored
Pedestal
Calibration
0 IRE
Every Vertical Sync
Register Initialization
C1
1
1
1
1
1
0
1
0
0
0
1
0
C0
1
1
1
1
1
0
0
0
0
0
0
0
R/W Com m ent
Write 0FH to Mode Register (MR1)
Write 0EH to Mode Register (MR1)
Write 0FH to Mode Register (MR1)
Write 2FH to Mode Register (MR1)
Write 0FH to Mode Register (MR1)
Write 04H to Address Register (A7–A0)
Write FFH to Pixel Mask Register
Write 05H to Address Register (A7–A0)
Write 01H to Command Reg 1 (CR1)
Write 06H to Address Register (A7–A0)
Write E0H to Command Reg 2 (CR2)
Write 07H to Address Register (A7–A0)
Write 41H to Command Reg 3 (CR3)
0
0
0
0
0
0
0
0
0
0
0
0
0
Resets to Normal Operation, 10-Bit Bus/RAM-DAC
*(Initializes Pipelining
*(
*(Calibrates LOADOUT /LOADIN T iming
*(
“
“
Address Reg Points to Pixel Mask Register
Sets the Pixel Mask to All “1s”
Address Reg Points to Command Register 1 (CR1)
Calibrates Every Vertical Sync
Address Reg Points to Command Register 2 (CR2)
Sets 24-Bit Color, 0 IRE, No SYNC
Address Reg Points to Command Register 3 (CR3)
Sets 2:1 Multiplexing, PRGCKOUT = CLOCK/8
1
0
Color P alette RAM Initialization
Write 00H to Address Register (A7–A0)
C1
0
0
0
0
0
0
0
•
C0 R/W Com m ent
0
1
1
1
1
1
1
•
0
0
0
0
0
0
0
•
Points to Color Palette RAM
(Initializes Palette RAM
Write 000H (Red Data) to RAM Location (00H)
Write 000H (Green Data) to RAM Location (00H)
Write 000H (Blue Data) to RAM Location (00H)
Write xxxH (Red Data) to RAM Location (01H)
Write xxxH (Green Data) to RAM Location (01H)
Write xxxH (Blue Data) to RAM Location (01H)
(
(
(
(
(
(
(
(
(
to a “Gamma” Ramp**
•
•
•
•
•
•
•
•
•
•
•
•
•
Write 3FFH (Red Data) to RAM Location (FFH)
Write 3FFH (Green Data) to RAM Location (FFH)
Write 3FFH (Blue Data) to RAM Location (FFH)
0
0
0
1
1
1
0
0
0
(RAM Initialization Complete
**T hese four command lines reset the ADV7152 T he pipelines for each of the Red, Green and Blue pixel inputs are synchronously reset to the Multiplexer’s “A” in-
put. Mode Register bit MR10 is written by a “1” followed by “0” followed by “1.” LOADIN/LOADOUT timing is internally synchronized by writing a “0” followed
by a “1” followed by a “0” to Mode Register MR15.
**Data for a gamma curve characteristic is obtainable in Appendix 3.
REGISTER D IAGNO STIC TESTING
2. READ after all WRITEs completed: All registers and the
T he previous examples show the register initialization sequence
color palette RAM are written to and set. Once this is
for the ADV7152. T hese show control data going to the regis-
complete, all registers are again accessed but this time in
ters and palette RAM. As well as this writing function, it may
Read-Only mode. T he table below shows this method for
also be necessary, due to system diagnostic requirements, to
Command Registers CR2 and CR3.
confirm that correct data has been transferred to each register
C1 C0 R/W D 0–D 7 Com m ent
and palette RAM location. T here are two ways to incorporate
register value/RAM value checking:
0
1
0
1
0
1
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
1
06H
E0H
07H
40H
06H
E0H
07H
40H
40H
Select Command Register 2 (CR2)
Sets 24-Bit T rue-Color
Select Command Register 3 (CR3)
Set 2:1 Mux Mode
Select CR2
CR2 Value Read-Back
Select CR3
1. READ after each WRITE: After data is written to a particular
register, it can be read back immediately. T he following table
shows an example with Command Registers CR2 and CR3.
C1 C0
R/W D 0–D 7 Com m ent
0
1
1
0
1
1
0
0
0
0
0
0
0
0
1
0
0
1
06H
E0H
E0H
07H
40H
40H
Select Command Register 2 (CR2)
Sets 24-Bit T rue-Color
Command Reg 2 Value Read-Back
Select Command Register 3 (CR3)
Set 2:1 Mux Mode
CR3 Value Read-Back
CR3 Value Read-Back
It is clear that this latter case requires more command lines
than the previous READ after each WRIT E case.
Command Reg 3 Value Read-Back
REV. B
–29–
ADV7152
AP P END IX 6
TEST D IAGNO STICS
SYNC
BLANK
GRAPHICS PIPELINE
GRAPHICS PIPELINE
COLOR
PALETTE
RAM
PIXEL
DATA
INPUT
MUX
DACs
TRIGGER
DECODE
TRIGGER
DECODE
SYNC BLANK
COLOR
DAC TEST
PIXEL TEST
REGISTER
IPLL TEST
REGISTER
REGISTERS
REGISTERS
MPU PORT
C0
C1
D9–D0
R/W
CE
Test/Diagnostic Block Diagram
T he ADV7152 contains onboard circuitry which enables both
device and system level test diagnostics. T he test circuitry can
be used to test the frame buffer memory as well as the function-
ality of the ADV7152. A number of test registers are integrated
into the part which effectively allow for monitoring of the graph-
ics pipeline. Pixel data is read from the graphics pipeline inde-
pendent of the pixel CLOCK. T he pixel data itself contains the
triggering information that latches data into the test registers.
T his allows for system diagnostics in a continuously clocked
graphics system. The test register data is then read by the micro-
processor over the MPU.
the graphics pipeline and after a number of clocks get latched
into the DAC T est Register. T his data can then be read from
the Pixel T est Register and the DAC T est Registers over the
MPU Port. T his data will remain in the Pixel T est Registers and
the DAC T est Registers until the next rising edge of R7 causes
new data to be latched in.
In the above example, the next rising edge of R7 occurs on the
Pixel n input. T herefore the data in the Pixel T est Registers and
DAC T est Registers must be read over the MPU before the
Pixel n data is applied, otherwise they will be overwritten by the
Pixel n data and the Pixel 2 data will be lost.
Access to the test registers is as described in the “Microproces-
sor (MPU) Port” section. T his section also gives the address
decode locations for the various test registers.
P ixel Test Register
T he read-only Pixel T est Register is 24 bits wide, 8 bits each for
red, green and blue. It is situated directly after the Pixel Mask
Register. After data is latched into this register by a transition on
R7, it is read in three cycles over the MPU Port as described in
the “Microprocessor (MPU) Port” section.
Test Tr igger (R7)
T he test trigger is decoded from the pixel data stream. Bit R7 of
the RED channel is assigned the task of latching pixel data into
the test registers. A “0” to “1” or a “1” to “0” (as determined
by bit CR20 of Command Register 2) transition on R7, fills the
test register with the corresponding pixel data. T his effectively
means that a sequence of data travels along the graphics pipe-
line, with the test registers taking a sample only when there is a
transition on Bit R7. T he following example shows a sequence
with the ADV7152 preset to sample the graphics pipeline on a
low to high transition of R7.
D AC Test Register
T he DAC T est Register is latched with data some CLOCKs
after the Pixel T est Register. T he DAC T est Register is a 30-bit
wide read-only register, corresponding to 10 bits each for red,
green and blue data. It is located the Color Palette RAM. If the
RAM-DAC is in 8-bit after resolution mode, the upper two bits
of the red, green and blue data will be zero. After data is latched
into the DAC T est Register by a transition on R7, it is read
in three or six cycles over the MPU Port as described in the
“Microprocessor (MPU) Port” section.
RED
GREEN
BLUE
Pixel 0:
Pixel 1:
Pixel 2:
Pixel 3:
. . . .
00000000
0........
1........
0........
. . .
00000000
........
........
00000000
........
........
SYNC, BLANK and IP LL Test Register
T his is an 8-bit wide register but with only three effective bits.
T he three lower bits correspond to SYNC, BLANK and IPLL
respectively. T he upper bits should be masked in software. T his
register is at the same position in the graphics pipeline as the
DAC T est Register. When pixel data is latched into the DAC
T est Register, the corresponding status of SYNC, BLANK and
IPLL is latched into this register. It is read over the MPU Port as
described in the “Microprocessor (MPU) Port” section.
........
........
. . . .
. . .
Pixel n-1:
Pixel n:
Pixel n:
0........
1........
0........
........
........
........
........
........
........
In the above sequence of pixels, there is a rising edge on R7 on
Pixel 2. T he Red, Green and Blue data for Pixel 2, therefore,
gets latched into the Pixel T est Register. Pixel 2 continues down
(Note: If BLANK is low, the corresponding pixel data to the
DAC T est Register will be all “0s.”)
REV. B
–30–
ADV7152
AP P END IX 7
TH ERMAL AND ENVIRO NMENTAL CO NSID ERATIO NS
T he ADV7152 is a very highly integrated monolithic silicon
Table A. Therm al Characteristics vs. Airflow
device. T his high level of integration, in such a small package,
inevitably leads to consideration of thermal and environmental
conditions in which the ADV7152 must operate. Reliability of
the device is significantly enhanced by keeping it as cool as pos-
sible. In order to avoid destructive damage to the device, the
absolute maximum junction temperature of 150°C must never
be exceeded. Certain applications, depending on pixel data
rates, may require forced air cooling, or external heatsinks. T he
following data is intended as a guide in evaluating the operating
conditions of a particular application so that optimum device
and system performance is achieved.
Air Velocity
(Linear feet/m in)
0
50
100 200
(Still Air)
θ
JA (°C/W)
No Heatsink
EG&G D10100-28 Heatsink 32
T hermalloy 2290 Heatsink 25
35
31
28
21
28
25
18
25
22
15
Ther m al Model
T he junction temperature of the device in a specific application
is given by:
It should be noted that information on package characteristics pub-
lished herein may not be the most up to date at the time of reading
this. Advances in package compounds and manufacture will inevita-
bly lead to improvements in the thermal data. Please contact your
local sales office for the most up-to-date information.
TJ = TA + PD (θJC + θCA
)
(1)
or
TJ = TA + PD (θJA
)
(2)
where:
P ower D issipation
T he diagram shows graphs of power dissipation in watts vs.
pixel clock frequency for the ADV7152.
TJ = Junction T emperature of Silicon (°C)
TA = Ambient T emperature (°C)
PD = Power Dissipation (W)
1.50
θJC = Junction to Case T hermal Resistance (°C/W)
θCA = Case to Ambient T hermal Resistance (°C/W)
θJA = Junction to Ambient T hermal Resistance (°C/W)
V
V
T
= +5V
AA
= +1.2V
REF
= 25°C
A
1.25
1.00
P ackage Enhancem ents
The standard QFP package has been enhanced to a PowerQuad2
package. T his supports an improved thermal performance come
pared to standard QFP. In this case, the die is attached to
heatslug so that the power that is dissipated can be conducted to
the external surface of the package. T his provides a highly effi-
cient path for the transfer of heat to the package surface. T he
package configuration also provides an efficient thermal path
from the ADV7152 to the Printed Circuit Board via the leads.
0.75
0.50
H eatsinks
60
80
100
120
140
160
180
200
220
T he maximum silicon junction temperature should be limited to
100°C. T emperatures greater than this will reduce long term
device reliability. T o ensure that the silicon junction tempera-
ture stays within prescribed limits, the addition of an external
heatsink may be necessary. Heatsinks, will reduce θJA as shown
in the “T hermal Characteristics vs. Airflow” table.
PIXEL CLOCK FREQUENCY – MHz
THE "TYPICAL ON-SCREEN PATTERN" CORRESPONDS TO LINEAR CHANGES IN THE
PIXEL INPUT (I. E., A BLACK TO WHITE RAMP). IN GENERAL, COLOR IMAGES TEND TO
APPROXIMATE THIS CHARACTERISTIC.
*
Typical Power Dissipation vs. Pixel Rate
P ackage Char acter istics
T he table of thermal characteristics shows typical information
for the ADV7152 (100-Lead Plastic Power QFP) using various
values of Airflow.
Junction to Case (θJC) T hermal Resistance for this particular
part is:
θJC (100-Lead Plastic Power QFP) = 1.0°C/W
(Note: 0°C is independent of airflow.)
REV. B
–31–
ADV7152
AP P END IX 8
O UTLINE D IMENSIO NS
D imensions shown in inches and (mm).
100-Lead P lastic P ower Quad Flatpack (S-100)
0.952 (24.15)
0.932 (23.65)
0.792 (20.10)
0.784 (19.90)
80
81
51
50
0.715 (18.15)
0.696 (17.65)
TOP VIEW
0.556 (14.10)
0.548 (13.90)
10
°
6°±4°
PIN 1
100
31
30
1
4°±4° MAX
0.004
(0.102)
MAX
0.014 (0.35)
0.011 (0.27)
0.054 (1.37)
0.046 (1.17)
0.030 (0.75)
0.022 (0.55)
0.134
(3.40)
MAX
0.116 (2.94)
0.096 (2.44)
0.054 (1.37)
0.046 (1.17)
0.037 (0.95)
0.026 (0.65)
REV. B
–32–
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