ADV7281A [ADI]
10-Bit, 4x Oversampled SDTV Video Decoder with Differential Inputs;
| 型号： | ADV7281A |
| 厂家： | 
ADI |
| 描述： | 10-Bit, 4x Oversampled SDTV Video Decoder with Differential Inputs 电视 |
| 文件： | 总24页 (文件大小：516K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
10-Bit, 4× Oversampled SDTV Video
Decoder with Differential Inputs
Data Sheet
ADV7281A
FEATURES
GENERAL DESCRIPTION
Worldwide NTSC/PAL/SECAM color demodulation support
One 10-bit ADC, 4× oversampling per channel for CVBS, Y/C,
and YPrPb modes
6 analog video input channels with an on-chip antialiasing filter
Video input support for CVBS (composite), S-Video (Y/C), and
YPrPb (component)
Fully differential, pseudo differential, and single-ended
CVBS video input support
NTSC/PAL/SECAM autodetection
The mobile industry processor interface (MIPI®) model of the
ADV7281A1 (ADV7281A-M) has the same pinout as and is
software compatible with the ADV7281-M with the exception
of an updated IDENT code.
The ADV7281A is a versatile one-chip, multiformat video
decoder that automatically detects standard, analog baseband
video signals and converts them into YCrCb 4:2:2 component
video data streams.
The analog input of the ADV7281A features a single, 10-bit,
analog-to-digital converter (ADC), and an on-chip, differential
to single-ended converter to accommodate the direct connec-
tion of differential, pseudo differential, or single-ended CVBS
without external amplifier circuitry.
STB diagnostics on 2 video inputs
Up to 4 V common-mode input range solution
Excellent common-mode noise rejection capabilities
5-line adaptive 2D comb filter and CTI video enhancement
Integrated AGC with adaptive peak white mode
Fast switching capability
The standard definition processor (SDP) in the ADV7281A
automatically detects PAL, NTSC, and SECAM standards in the
form of composite, S-Video (Y/C), and component. The analog
video is converted into a 4:2:2 component video data stream
that is output via a MIPI CSI-2 transmitter (Tx) interface,
hereafter referred to as MIPI Tx.
ACE
Downdither (8-bit to 6-bit)
Rovi copy protection detection
MIPI CSI-2 Tx output interface
Full featured VBI data slicer with WST support
Power-down mode available
2-wire, I2C-compatible serial interface
Qualified for automotive applications
−40°C to +105°C temperature grade
32-lead, 5 mm × 5 mm, RoHS compliant LFCSP
The ADV7281A offers short to battery (STB) diagnostic sense
inputs and general-purpose outputs.
The ADV7281A is provided in a space-saving, LFCSP surface-
mount, RoHS compliant, package. The ADV7281A is rated over
the −40°C to +105°C temperature range, making it ideal for
automotive applications.
APPLICATIONS
Advanced driver assistance
Automotive infotainment
DVRs for video security
Media players
The ADV7281A must be configured in accordance with the I2C
writes provided in the evaluation board script files available at
www.analog.com/ADV7281A.
1 Protected by U.S. Patent 5,784,120
Rev. A
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rightsof third parties that may result fromits use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks andregisteredtrademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2017–2018 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
ADV7281A
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Single-Ended Input Network.................................................... 15
Differential Input Network ....................................................... 15
Short to Battery Protection (STB)............................................ 15
Applications Information .............................................................. 16
Input Configuration................................................................... 16
STB Diagnostics.......................................................................... 17
Programming the STB Diagnostic Function.......................... 17
Adaptive Contrast Enhancement (ACE)................................. 18
MIPI Tx Output.......................................................................... 18
I2C Port Description................................................................... 19
Register Maps.................................................................................. 20
PCB Layout Recommendations.................................................... 22
Analog Interface Inputs............................................................. 22
Power Supply Decoupling ......................................................... 22
VREFN and VREFP Pins .......................................................... 22
Digital Outputs ........................................................................... 22
Exposed Metal Pad..................................................................... 22
Digital Inputs .............................................................................. 22
MIPI Tx Outputs........................................................................ 22
Typical Circuit Connections ......................................................... 23
Outline Dimensions....................................................................... 24
Ordering Guide .......................................................................... 24
Automotive Products................................................................. 24
Applications....................................................................................... 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Functional Block Diagram .............................................................. 3
Specifications..................................................................................... 4
Electrical Specifications ................................................................. 4
Video Specifications..................................................................... 5
Analog Specifications................................................................... 5
Clock and I2C Timing Specifications............................................ 6
MIPI Tx Video Output and Timing Specifications ................. 6
Absolute Maximum Ratings............................................................ 9
Thermal Resistance ...................................................................... 9
ESD Caution.................................................................................. 9
Pin Configuration and Function Descriptions........................... 10
Theory of Operation ...................................................................... 11
Analog Front End (AFE) ........................................................... 11
Standard Definition Processor (SDP)...................................... 11
Power Supply Sequencing.............................................................. 13
Optimal Power-Up Sequence.................................................... 13
Simplified Power-Up Sequence ................................................ 13
Power-Down Sequence.............................................................. 13
Crystal Resonator Design.............................................................. 14
Input Networks ............................................................................... 15
REVISION HISTORY
5/2018—Rev. 0 to Rev. A
Change to General Description Section........................................ 1
Updated Outline Dimensions....................................................... 24
9/2017—Revision 0: Initial Version
Rev. A | Page 2 of 24
Data Sheet
ADV7281A
FUNCTIONAL BLOCK DIAGRAM
CLKP
CLKN
D0P
ADV7281A
CLOCK PROCESSING BLOCK
MIPI
Tx
XTALP
XTALN
PLL
ADLLT PROCESSING
D0N
10-BIT ADC
DIGITAL
PROCESSING
BLOCK
AA
FILTER
A
A
1
2
IN
IN
ACE
2D COMB
DIFFERENTIAL
OR
SINGLE-ENDED
ANALOG VIDEO
INPUTS
AA
+
DOWN
DITHER
FILTER
A
A
3
4
IN
IN
SHA
–
ADC
VBI SLICER
AA
FILTER
GPO0
GPO1
GPO2
A
A
5
6
IN
IN
COLOR
DEMODULATOR
AA
FILTER
2
INTRQ
DIAGNOSTICS
REFERENCE
I C/CONTROL
DIAG1
DIAG2
SCLK SDATA ALSB RESET PWRDWN
Figure 1.
Rev. A | Page 3 of 24
ADV7281A
Data Sheet
SPECIFICATIONS
ELECTRICAL SPECIFICATIONS
PVDD, AVDD, DVDD, and MVDD = 1.71 V to 1.89 V, DVDDIO = 2.97 V to 3.63 V, specified at the operating temperature range, unless otherwise noted.
Table 1.
Parameter
Symbol
Test Conditions/Comments
Min Typ Max Unit
STATIC PERFORMANCE
ADC Resolution
Integral Nonlinearity
Differential Nonlinearity
DIGITAL INPUTS
N
INL
DNL
10
Bits
LSB
LSB
CVBS mode
CVBS mode
2
0.6
Input High Voltage
Input Low Voltage
Input Leakage Current
VIH
VIL
IIN
DVDDIO = 3.3 V
DVDDIO = 3.3 V
2
V
V
µA
µA
µA
pF
0.8
−10
−10
−10
+10
+15
+50
10
RESET pin
SDATA, SCLK pins
PWRDWN, ALSB pins
Capacitance
CIN
CRYSTAL INPUT
Input High Voltage
Input Low Voltage
VIH
VIL
XTALN pin
XTALN pin
1.2
2.4
V
V
0.4
DIGITAL OUTPUTS
Output High Voltage
Output Low Voltage
High Impedance Leakage Current
Output Capacitance
POWER REQUIREMENTS1, 2,
Digital Input/Output (I/O) Power Supply
PLL Power Supply
Analog Power Supply
Digital Power Supply
MIPI Tx Power Supply
Digital I/O Supply Current
PLL Supply Current
MIPI Tx Supply Current
Analog Supply Current
Single-Ended CVBS Input
Differential CVBS Input
Y/C Input
VOH
VOL
ILEAK
COUT
DVDDIO = 3.3 V, ISOURCE = 0.4 mA
DVDDIO = 3.3 V, ISINK = 3.2 mA
V
V
µA
pF
0.4
10
20
DVDDIO
PVDD
2.97 3.3
1.71 1.8
1.71 1.8
1.71 1.8
1.71 1.8
1.5
3.63
1.89
1.89
1.89
1.89
V
V
V
V
AVDD
DVDD
MVDD
IDVDDIO
IPVDD
V
mA
mA
mA
12
14
IMVDD
IAVDD
47
69
60
75
mA
mA
mA
mA
Fully differential and pseudo differential CVBS
Fully differential and pseudo differential CVBS
YPrPb Input
Digital Supply Current
Single-Ended CVBS Input
Differential CVBS Input
Y/C Input
IDVDD
60
60
60
60
mA
mA
mA
mA
YPrPb Input
POWER-DOWN CURRENTS1
Digital I/O Supply
PLL Supply
Analog Supply
Digital Supply
IDVDDIO_PD
IPVDD_PD
IAVDD_PD
IDVDD_PD
IMVDD_PD
73
46
0.2
420
4.5
1
µA
µA
µA
µA
µA
mW
MIPI Tx Supply
Total Power Dissipation in Power-Down Mode
CRYSTAL OSCILLATOR1
Transconductance
gM
30
mA/V
1 Guaranteed by characterization.
2 Typical current consumption values are measured with nominal voltage supply levels and a Society of Motion Picture and Television Engineers (SMPTE) bar test pattern.
Rev. A | Page 4 of 24
Data Sheet
ADV7281A
VIDEO SPECIFICATIONS
PVDD, AVDD, DVDD, and MVDD = 1.71 V to 1.89 V, DVDDIO = 2.97 V to 3.63 V, specified at the operating temperature range, unless otherwise
noted. Specifications guaranteed by characterization.
Table 2.
Parameter
1
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
NONLINEAR SPECIFICATIONS2
Differential Phase
Differential Gain
Luma Nonlinearity
DP
DG
LNL
CVBS input, modulated five-step
CVBS input, modulated five-step
CVBS input, five-step
0.9
0.5
2.0
Degrees
%
%
NOISE SPECIFICATIONS
Signal-to-Noise Ratio, Unweighted
SNR
Luma ramp
Luma flat field
57.1
58
60
dB
dB
dB
dB
Analog Front-End Crosstalk
Common-Mode Rejection Ratio3
LOCK TIME SPECIFICATIONS
Horizontal Lock Range
Vertical Lock Range
CMRR
73
−5
40
+5
70
%
Hz
Subcarrier Lock Range
Color Lock In Time
Synchronization Depth Range
Color Burst Range
fSC
1.3
60
kHz
Lines
%
20
5
200
200
%
Vertical Lock Time
Autodetection Switch Speed4
Fast Switch Speed5
2
100
100
Fields
Lines
ms
LUMA SPECIFICATIONS
Luma Brightness Accuracy
Luma Contrast Accuracy
CVBS, 1 V input
1
1
%
%
1 Specifications guaranteed by characterization.
2 These specifications apply for all CVBS input types (NTSC, PAL, and SECAM), as well as single-ended and differential CVBS inputs.
3 The CMRR of this circuit design is critically dependent on the external resistor matching on the circuit inputs (see the Input Networks section). The CMRR measurement
was performed with 0.1% tolerant resistors, a common-mode voltage of 1 V, and a common-mode frequency of 10 kHz.
4 Autodetection switch speed is the time required for the ADV7281A to detect which video format is present at its input, for example, PAL I or NTSC M.
5 Fast switch speed is the time required for the ADV7281A to switch from one analog input (single-ended or differential) to another, for example, switching from AIN1 to AIN2.
ANALOG SPECIFICATIONS
PVDD, AVDD, DVDD, and MVDD = 1.71 V to 1.89 V, DVDDIO = 2.97 V to 3.63 V, specified at the operating temperature range, unless otherwise
noted.
Table 3.
Parameter1
Test Conditions/Comments
Min
Typ
Max
Unit
CLAMP CIRCUITRY
External Clamp Capacitor
Input Impedance
Large Clamp Source Current
Large Clamp Sink Current
Fine Clamp Source Current
Fine Clamp Sink Current
0.1
10
0.4
0.4
10
µF
Clamps switched off
MΩ
mA
mA
µA
10
µA
1 Specifications guaranteed by characterization.
Rev. A | Page 5 of 24
ADV7281A
Data Sheet
CLOCK AND I2C TIMING SPECIFICATIONS
PVDD, AVDD, DVDD, and MVDD = 1.71 V to 1.89 V, DVDDIO = 2.97 V to 3.63 V, specified at the operating temperature range, unless otherwise noted.
Table 4.
Parameter1
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
SYSTEM CLOCK AND CRYSTAL
Nominal Frequency
28.6
3636
MHz
ppm
Frequency Stability
I2C PORT
50
SCLK Frequency
SCLK Minimum Pulse Width
High
SCLK Minimum Pulse Width
Low
400
kHz
µs
t1
t2
0.6
1.3
µs
Hold Time (Start Condition)
Setup Time (Start Condition)
SDATA Setup Time
SCLK and SDATA Rise Times
SCLK and SDATA Fall Times
Setup Time (Stop Condition)
RESET INPUT
t3
t4
t5
t6
t7
t8
0.6
0.6
100
µs
µs
ns
ns
ns
µs
300
300
0.6
RESET Pulse Width
5
ms
1 Specifications guaranteed by characterization.
t5
t3
t3
SDATA
t1
t6
SCLK
t4
t7
t8
t2
Figure 2. I2C Timing Diagram
MIPI Tx VIDEO OUTPUT AND TIMING SPECIFICATIONS
PVDD, AVDD, DVDD, and MVDD = 1.71 V to 1.89 V, DVDDIO = 2.97 V to 3.63 V, specified at the operating temperature range, unless otherwise noted.
The ADV7281A MIPI Tx conforms to the MIPI D-PHY Version 1.00.00 specification by characterization. The MIPI Tx clock lane of the
ADV7281A remains in high speed mode even when the data lane enters low power (LP) mode. For this reason, some measurements on the clock
lane that pertain to low power mode are not applicable. Unless otherwise stated, all high speed measurements were performed with the
ADV7281A operating in progressive mode and with a nominal 216 Mbps output data rate. Specifications guaranteed by characterization.
Table 5.
Parameter
Symbol
Test Conditions/Comments
Min
Typ Max
Unit
UNIT INTERVAL
Interlaced Output
UI
4.63
ns
DATA AND CLOCK LANE LP Tx DC
SPECIFICATIONS1
Thevenin Output High Level
Thevenin Output Low Level
DATA LANE LP MIPI Tx AC SPECIFICATIONS1
Rise Time, 15% to 85%
Fall Time, 85% to 15%
Rise Time, 30% to 85%
VOH
VOL
1.1
−50
1.2
0
1.3
+50
V
mV
25
25
35
ns
ns
ns
Data Lane LP Slew Rate vs. Load
Capacitance (CLOAD
)
Rev. A | Page 6 of 24
Data Sheet
ADV7281A
Parameter
Symbol
Test Conditions/Comments
Min
Typ Max
Unit
Maximum Slew Rate over Entire
Rising edge
150
mV/ns
Vertical Edge Region
Falling edge
150
mV/ns
Minimum Slew Rate
400 mV ≤ VOUT ≤ 930 mV
400 mV ≤ VOUT ≤ 700 mV
700 mV ≤ VOUT ≤ 930 mV
Pulse Width of LP Exclusive OR Clock
Falling edge
Rising edge
Rising edge
First clock pulse after stop
state or last pulse before stop
state
30
30
>0
40
mV/ns
mV/ns
mV/ns
ns
All other clock pulses
20
90
ns
ns
Period of LP Exclusive OR Clock
CLOCK LANE LP MIPI Tx AC SPECIFICATIONS1
Rise Time, 15% to 85%
25
25
ns
ns
Fall Time, 85% to 15%
Clock Lane LP Slew Rate
Maximum Slew Rate over Entire
Vertical Edge Region
Rising edge
Falling edge
150
150
mV/ns
mV/ns
Minimum Slew Rate
400 mV ≤ VOUT ≤ 930 mV
400 mV ≤ VOUT ≤ 700 mV
700 mV ≤ VOUT ≤ 930 mV
Falling edge
Rising edge
Rising edge
See Figure 3
30
30
>0
mV/ns
mV/ns
mV/ns
DATA LANE HIGH SPEED MIPI Tx SIGNALING
REQUIREMENTS
LP to High Speed Transition Stage
t9
Time that the D0P pin is at VOL
and the D0N pin is at VOH
50
ns
t10
t11
|V1|
Time that the D0P and D0N
pins are at VOL
t10 plus the high speed zero
period
40 + (4 × UI)
145 + (10 × U)
140
85 + (6 × UI)
ns
ns
High Speed Differential Voltage Swing
Differential Voltage Mismatch
Single-Ended Output High Voltages
Static Common-Mode Voltage Level
Static Common-Mode Voltage Mismatch
Dynamic Common Level Variations
50 MHz to 450 MHz
Above 450 MHz
Rise Time, 20% to 80%
Fall Time, 80% to 20%
200 270
mV p-p
mV
mV
mV
mV
10
360
200 250
5
150
25
15
0.3 × UI
0.3 × UI
mV
mV
ns
0.15
0.15
ns
High Speed to LP Transition Stage
t12
Time that the ADV7281A
drives the flipped last data bit
after sending the last payload
data bit of a high speed
transmission burst
60 + (4 × UI)
ns
t13
t14
Post end of transmission rise
time (30% to 85%)
Time from start of t12 to start
of low power state following a
high speed transmission burst
35
ns
ns
105 +
(12 × UI)
t15
Time that a low power state is
transmitted after a high speed
transmission burst
100
ns
Rev. A | Page 7 of 24
ADV7281A
Data Sheet
Parameter
Symbol
Test Conditions/Comments
Min
Typ Max
Unit
CLOCK LANE HIGH SPEED MIPI Tx
SIGNALING REQUIREMENTS
LP to High Speed Transition Stage2
See Figure 3
Time that the CLKP pin is at
50
38
ns
ns
V
OL and the CLKN pin is at VOH
Time that the CLKP and CLKN
pins are at VOL
95
Clock high speed zero period
300
140
500
200 270
ns
mV p-p
mV
High Speed Differential Voltage Swing
Differential Voltage Mismatch
Single-Ended Output High Voltages
Static Common-Mode Voltage Level
Static Common-Mode Voltage Mismatch
Dynamic Common Level Variations
50 MHz to 450 MHz
|V2|
10
360
mV
150
200 250
5
mV
mV
25
15
mV
mV
Above 450 MHz
Rise Time, 20% to 80%
Fall Time, 80% to 20%
0.15
0.15
0.3 × UI
0.3 × UI
ns
ns
HIGH SPEED MIPI Tx CLOCK TO DATA LANE
TIMING REQUIREMENTS
Data to Clock Skew
0.35 × UI
0.65 × UI
ns
1 These measurements were performed with CLOAD = 50 pF.
2 The clock lane remains in high speed mode throughout normal operation.
|V |
CLKP/CLKN
2
t9
t10
t11
D0P/D0N
V
OH
|V |
1
V
OL
t13
TRANSMIT FIRST
DATA BIT
t14
t12
t15
LOW POWER
TO
HIGH SPEED
TRANSITION
HIGH SPEED
ZERO
START OF
TRANSMISSION
SEQUENCE
HIGH SPEED DATA
TRANSMISSION
HIGH SPEED
TRAIL
HIGH SPEED
TO
LOW POWER
TRANSITION
Figure 3. ADV7281A Output Timing Diagram (Conforms with MIPI Tx Specification)
Rev. A | Page 8 of 24
Data Sheet
ADV7281A
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 6.
Parameter1
Rating
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
AVDD to GND
2.2 V
DVDD to GND
2.2 V
PVDD to GND
MVDD to GND
DVDDIO to GND
PVDD to DVDD
MVDD to DVDD
AVDD to DVDD
Digital Inputs Voltage
Digital Outputs Voltage
Analog Inputs to Ground
2.2 V
2.2 V
4 V
θ
JA is the natural convection junction to ambient thermal
resistance measured in a one cubic foot sealed enclosure as per
JEDEC JESD51. ΨJT is the junction to top thermal characterization
parameter measured on a standard test board, as per JEDEC
JESD51, allowing the heat generated in the ADV7281A die to
flow normally along preferred thermal conduction paths that more
closely represent the thermal flows in a typical application board.
−0.9 V to +0.9 V
−0.9 V to +0.9 V
−0.9 V to +0.9 V
GND − 0.3 V to DVDDIO + 0.3 V
GND − 0.3 V to DVDDIO + 0.3 V
GND − 0.3 V to AVDD + 0.3 V
Table 7. Thermal Resistance for the 32-Lead LFCSP
Package
CP-32-121
θJA
ΨJT
Unit
Maximum Junction Temperature 125°C
(TJ MAX
)
39.6
0.86
°C/W
Storage Temperature Range
Reflow Soldering (20 sec)
−65°C to +150°C
JEDEC J-STD-020
1 JEDEC JESD51 2s2p 4-layer PCB with two signal layers and two buried solid
ground planes (GND) and with nine thermal vias connecting the exposed
pad to the ground plane (GND).
1 The absolute maximum ratings assume that the DGND pins and the exposed
pad of the ADV7281A are connected together to a common ground plane
(GND). This is part of the recommended layout scheme. See PCB Layout
Recommendations for more information. The absolute maximum ratings are
stated in relation to this common ground plane.
ESD CAUTION
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rev. A | Page 9 of 24
ADV7281A
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
DGND
1
2
3
4
5
6
7
8
24
23
A
A
4
3
IN
D
VDDIO
IN
D
22 DIAG1
VDD
ADV7281A
DGND
INTRQ
GPO2
GPO1
GPO0
21
20
19
18
17
A
VDD
TOP VIEW
VREFN
VREFP
(Not to Scale)
A
A
2
1
IN
IN
NOTES
1. THE EXPOSED PAD MUST BE CONNECTED,
TOGETHER WITH THE DGND PINS, TO A COMMON
GROUND PLANE (GND).
Figure 4. Pin Configuration
Table 8. Pin Function Descriptions
Pin No.
Mnemonic
DGND
DVDDIO
Type
Description
1, 4
2
3
Ground
Power
Power
Output
Ground for Digital Supply.
Digital I/O Power Supply (3.3 V).
Digital Power Supply (1.8 V).
Interrupt Request Output. An interrupt occurs when certain signals are detected on the input
video.
DVDD
5
INTRQ
6 to 8
GPO2 to GPO0
Output
General-Purpose Outputs. These pins can be configured via I2C to allow control of external
devices.
9
D0P
D0N
CLKP
CLKN
MVDD
XTALP
Output
Output
Output
Output
Power
Positive MIPI Tx Differential Data Output.
Negative MIPI Tx Differential Data Output.
Positive MIPI Tx Differential Clock Output.
Negative MIPI Tx Differential Clock Output.
MIPI Tx Digital Power Supply (1.8 V).
Output Pin for the Crystal Oscillator Amplifier. Connect this pin to the external 28.63636 MHz
crystal, or leave it unconnected if an external 1.8 V, 28.63636 MHz clock oscillator source
clocks the ADV7281A. The crystal used with the ADV7281A must be a fundamental mode
crystal.
10
11
12
13
14
Output
15
16
XTALN
Input
Input Pin for the Crystal Oscillator Amplifier. The crystal used with the ADV7281A must be a
fundamental mode crystal. If an external 1.8 V, 28.63636 MHz clock oscillator source clocks the
ADV7281A, the output of the oscillator is fed into the XTALN pin.
PLL Power Supply (1.8 V).
Analog Video Input Channels.
PVDD
AIN1 to AIN6
Power
Input
17, 18, 23, 24,
26, 27
19
20
21
22
25
28
VREFP
VREFN
AVDD
DIAG1
DIAG2
RESET
Output
Output
Power
Input
Input
Input
Positive Internal Voltage Reference Output.
Negative Internal Voltage Reference Output.
Analog Power Supply (1.8 V).
Diagnostic Input 1.
Diagnostic Input 2.
System Reset Input (Active Low). A minimum low reset pulse width of 5 ms resets the
ADV7281A circuitry.
29
ALSB
Input
Address Least Significant Bit. This pin selects the I2C write address for the ADV7281A. When
ALSB is set to Logic 0, the write address is 0x40; when ALSB is set to Logic 1, the write address
is 0x42.
30
31
32
SDATA
SCLK
Input/output I2C Port Serial Data Input/Output.
Input
Input
I2C Port Serial Clock Input. The maximum clock rate is 400 kHz.
Power-Down. A logic low on this pin places the ADV7281A in power-down mode.
PWRDWN
EPAD (EP)
Exposed Ground Pad. The exposed pad must be connected, together with the DGND pins, to
a common ground plane (GND).
Rev. A | Page 10 of 24
Data Sheet
ADV7281A
THEORY OF OPERATION
The ADV7281A is a versatile one-chip, multiformat video decoder
that automatically detects standard analog baseband video signals
and converts them into an YCrCb 4:2:2 component video data
stream. The ADV7281A supports video signals compatible with
worldwide NTSC, PAL and SECAM standards.
The single 10-bit ADC digitizes the analog video before it is
applied to the SDP. Table 9 shows the three ADC clocking rates
to be processed that are determined by the video input format.
These clock rates ensure 4× oversampling per channel for CVBS,
Y/C, and YPrPb modes.
The analog front end (AFE) of the ADV7281A features a 6-channel
input mux, a differential to single-ended converter; and a single
10-bit ADC. The analog video inputs accept single-ended, pseudo
differential, and fully differential composite video signals as well as
S-Video and YPbPr video signals, supporting a wide range of
automotive and consumer video sources.
Table 9. ADC Clock Rates
Oversampling
Rate per Channel
Input Format
ADC Clock Rate (MHz)1
CVBS
57.27
4×
4×
4×
S-Video (Y/C) 2 114
YPrPb2
172
The incoming analog video is converted into a digital 8-bit
YCrCb 4:2:2 video stream that is output via a MIPI Tx interface.
1 Based on a 28.63636 MHz clock input to the ADV7281A.
2 Configuration writes are required for the different S-Video (Y/C) and
YPrPb modes.
The ac-coupled connection of input video signals to the
ADV7281A provides STB protection and two diagnostic sense
inputs are available. The ADV7281A also offers a downdither
mode, adaptive contrast enhancement (ACE) and general-
purpose outputs.
STANDARD DEFINITION PROCESSOR (SDP)
The standard definition processor in the ADV7281A is capable of
decoding a large selection of baseband video signals in composite
(both single-ended and differential), S-Video, and component
formats. The video standards supported by the video processor
include
The ADV7281A is programmed via a 2-wire, serial bidirectional
port (I2C-compatible) and can communicate with other devices
•
PAL B, PAL D, PAL G, PAL H, PAL I, PAL M, PAL N,
PAL Nc, PAL 60
INTRQ
via a hardware interrupt pin,
.
The ADV7281A is fabricated in a low power 1.8 V CMOS
process and is provided in a space-saving LFCSP surface-
mount, RoHS compliant package.
•
•
NTSC J, NTSC M, NTSC 4.43
SECAM B, SECAM D, SECAM G, SECAM K, SECAM L
The SDP in the ADV7281A can automatically detect the video
standard and process it accordingly.
The ADV7281A is available in an automotive grade rated over
the −40°C to +105°C temperature range, making it ideal for
automotive applications.
The ADV7281A has a five-line, superadaptive 2D comb filter that
provides superior chrominance and luminance separation when
decoding a composite video signal. This highly adaptive filter
automatically adjusts its processing mode according to the video
standard and signal quality without requiring user intervention.
Video user controls such as brightness, contrast, saturation, and
hue are also available in the ADV7281A.
ANALOG FRONT END (AFE)
The ADV7281A AFE is composed of an input mux, a differential
to single-ended converter with clamp circuitry, a set of four anti-
aliasing filters, and a single 10-bit ADC.
The 6-channel input mux applies multiple composite video
signals to the SDP and is software controlled.
The ADV7281A implements a patented Adaptive Digital Line
Length Tracking (ADLLT™) algorithm to track varying video
line lengths from sources such as a videocassette recorder (VCR).
ADLLT enables the ADV7281A to track and decode poor quality
video sources such as VCRs and noisy sources from tuner outputs
and camcorders. The ADV7281A contains a chroma transient
improvement (CTI) processor that sharpens the edge rate of
chroma transitions, resulting in sharper vertical transitions.
The next stage in the AFE features the differential to single-ended
converter and the clamp circuitry. The incorporation of a differ-
ential front end allows differential video to connect directly to the
ADV7281A. The differential front end enables small and large
signal noise rejection, improved electromagnetic interference
(EMI), and the ability to absorb ground bounce. The architecture
can support true differential, pseudo differential, and single-ended
signals.
The ADV7281A features an automatic gain control (AGC)
algorithm to ensure that the optimum luma gain is selected as
the input video varies in brightness.
In conjunction with an external resistor divider, the ADV7281A
can provide a common-mode input range of 4 V facilitating the
removal of large signal, common-mode transients present on
both the positive and negative signals of a differential channel.
ACE is an algorithm that automatically varies the contrast level
applied across an image to enhance the picture detail visible. This
enables the contrast in the dark areas of an image to increase
without saturating the bright areas, which is particularly useful
in automotive applications where it can be important to clearly
discern objects in shaded areas.
The external resistor divider is required before each analog
input channel to ensure the input signal is kept within the range
of the ADC. Current and voltage clamps in the circuit ensure
the video signal remains within the range on the ADC.
Rev. A | Page 11 of 24
ADV7281A
Data Sheet
Downdithering from eight bits to six bits enables ease of design
for standard liquid crystal display (LCD).
The ADV7281A is fully Rovi™ (formerly Macrovision® and now
rebranded as TiVo upon acquisition of the same) compatible;
detection circuitry enables Type I, Type II, and Type III protection
levels to be identified and reported to the user. The SDP is fully
robust to all Rovi signal inputs.
The SDP can handle a variety of vertical blanking interval (VBI)
data services, such as closed captioning (CCAP), wide screen
signaling (WSS), copy generation management system (CGMS),
and teletext data slicing for world standard teletext (WST). Data
is transmitted via the 8-bit video output port as ancillary data
packets (ANC).
Rev. A | Page 12 of 24
Data Sheet
ADV7281A
POWER SUPPLY SEQUENCING
OPTIMAL POWER-UP SEQUENCE
SIMPLIFIED POWER-UP SEQUENCE
The optimal power-up sequence for the ADV7281A is
guaranteed by production testing.
The simplified power-up sequence is guaranteed by
characterization.
The optimal power-up sequence for the ADV7281A is to first
power up the 3.3 V DVDDIO supply, followed by the 1.8 V supplies
(DVDD, PVDD, AVDD, and MVDD).
Alternatively, the ADV7281A can power up by asserting all
PWRDWN
supplies and the
pin simultaneously. During this
pin must remain low.
PWRDWN
RESET
operation, the
During power-up, all supplies must adhere to the specifications
listed in the Absolute Maximum Ratings section. When powering
up the ADV7281A, follow these steps:
After the supplies and
are fully asserted, wait for at
RESET RESET
least 5 ms before bringing the
pin high. After the
is fully asserted, wait 5 ms before initiating I2C communication
with the ADV7281A.
PWRDWN
RESET
pins (pull the pins low).
1. Assert the
and
2. Power up the DVDDIO supply.
3. After DVDDIO is fully asserted, power up the 1.8 V supplies.
4. After the 1.8 V supplies are fully asserted, pull
While the supplies are established, ensure that a lower rated supply
does not go above a higher rated supply level. During power-up,
all supplies must adhere to the specifications listed in the
Absolute Maximum Ratings section.
PWRDWN
the
pin high.
RESET
5. Wait 5 ms and then pull the
6. After all power supplies and the
pin high.
PWRDWN
POWER-DOWN SEQUENCE
RESET
and
The ADV7281A supplies can be deasserted simultaneously if
pins are powered up and stable, wait an additional 5 ms
DVDDIO does not go below a lower rated supply.
before initiating I2C communication with the ADV7281A.
3.3V
1.8V
3.3V SUPPLY
PWRDWN PIN
RESET PIN
1.8V SUPPLIES
PWRDWN PIN
POWER-UP
RESET PIN
POWER-UP
3.3V SUPPLY
POWER-UP
1.8V SUPPLIES
POWER-UP
TIME
5ms
5ms
WAIT
RESET
OPERATION
Figure 5. Optimal Power-Up Sequence
Rev. A | Page 13 of 24
ADV7281A
Data Sheet
CRYSTAL RESONATOR DESIGN
The ADV7281A needs a stable and accurate clock source to
guarantee its operation. This clock is typically provided by a
crystal resonator (XTAL) but can also be provided by a clock
oscillator.
Table 10. Reference XTAL Characteristics
Characteristic
Value
Unit
Package
3.2 × 2.5 × 0.8
28.63636
Fundamental
20
mm
MHz
Nominal Frequency
Mode of Oscillation
Frequency Calibration (at 25°C)
The required circuitry for an XTAL is illustrated in Figure 14. A
damping resistor (RDAMP) is required on the output of the
ADV7281A XTAL amplifier (XTALP). The damping resistor
limits the current flowing through the XTAL and the voltage
across the XTAL amplifier. To define the appropriate value of
the damping resistor, RDAMP (see the Typical Circuit Connections
section), consult the accompanying calculation tool (visit the
design resources section at www.analog.com/ADV7281A to
download the tool).
ppm
ppm
Frequency Temperature Stability
Tolerance
50
Operating Temperature Range
Maximum Equivalent Series
Resistance
−40 to +125
25
°C
Ω
Load Capacitance
Drive Level
Shunt Capacitance (Maximum)
Aging per Year
12
200
5
pF
µW
pF
The other components in the XTAL circuit must be chosen
carefully, for example, incorrectly selected load capacitors may
result in an offset to the crystal oscillation frequency. For more
information on such considerations, see the AN-1260
Application Note, Crystal Design Considerations for Video
Decoders, HDMI Receivers, and Transceivers. After the XTAL
circuit is defined, it is recommended to consult with the XTAL
vendor to ensure that the design operates with sufficient margin
across all conditions.
3
ppm
The values in Table 10 are provided for reference only. It is
recommended to characterize the operation of the XTAL circuit
thoroughly across the operating temperature range of the
application, in conjunction with the XTAL vendor, prior to
releasing any new design.
The evaluation of the ADV7281A was completed using an
XTAL with typical characteristics (see Table 10).
Rev. A | Page 14 of 24
Data Sheet
ADV7281A
INPUT NETWORKS
An input network (external resistor and capacitor circuit) is
required on the AINx input pins of the decoder. The components
of the input network depend on the video format selected for
the analog input.
Differential video transmission has several key advantages over
single-ended transmission, including the following:
•
•
•
Inherent small signal and large signal noise rejection
Improved EMI performance
Ability to absorb ground bounce
SINGLE-ENDED INPUT NETWORK
Figure 6 shows the input network to use on each AINx input pin
of the ADV7281A when using any of the following video input
formats:
Resistor R1 provides the radio frequency (RF) {please define}
end termination for the differential CVBS input lines. For a
pseudo differential CVBS input, a value of 75 Ω is
recommended for R1. For a fully differential CVBS input, a
value of 150 Ω is recommended for R1.
•
•
•
Single-ended CVBS
S-Video (Y/C)
YPrPb
The 1.3 kΩ and 430 Ω resistors create a resistor divider with a
gain of 0.25. The resistor divider attenuates the amplitude of the
input analog video, but increases the input common-mode range
of the ADV7281A to 4 V p-p. Amplifiers within the ADC restore
the amplitude of the input signal to maintain the SNR
performance.
INPUT
CONNECTOR
100nF
24Ω
VIDEO INPUT
FROM SOURCE
EXT
ESD
A
x
IN
51Ω
Figure 6. Single-Ended Input Network
The 100 nF ac coupling capacitor removes the dc bias of the analog
input video before it is fed into an AINx pin of the ADV7281A.
The clamping circuitry within the ADV7281A restores the dc
bias of the input signal to the optimal level before it is fed into
the ADC of the ADV7281A.
The 24 Ω and 51 Ω resistors supply the 75 Ω end termination
required for the analog video input. These resistors also create a
resistor divider with a gain of 0.68. The resistor divider attenuates
the amplitude of the input analog video and scales the input to
the ADC range of the ADV7281A. This resistor divider allows an
input range to the ADV7281A of up to 1.47 V p-p. Amplifiers
within the ADC restore the amplitude of the input signal so that
SNR performance is maintained.
The combination of the 1.3 kΩ and 430 Ω resistors and the
100 nF ac coupling capacitors limits the current flow into the
ADV7281A during STB events (see the Short to Battery
Protection section.
The 100 nF ac coupling capacitor removes the dc bias of the analog
input video before it is fed into an AINx pin. The clamping circuitry
within the ADV7281A restores the dc bias of the input signal to
the optimal level before it is fed into the ADC of the ADV7281A.
To achieve optimal performance, the 1.3 kΩ and 430 Ω resistors
must be closely matched; that is, all 1.3 kΩ and 430 Ω resistors
must have the same resistance tolerance and this tolerance must
be as low as possible.
DIFFERENTIAL INPUT NETWORK
SHORT TO BATTERY PROTECTION (STB)
Figure 7 shows the input network to use when differential
CVBS video is input on the AINx pins of the ADV7281A.
INPUT
In differential mode, the ADV7281A is protected against STB
events by the external 100 nF ac coupling capacitors (see Figure 7).
The external input network resistors are sized to be large enough to
reduce the current flow during an STB event but small enough not
to affect the operation of the ADV7281A.
CONNECTOR
100nF
1.3kΩ
A
1
IN
430Ω
EXT
ESD
VIDEO INPUT
The power rating of the input network resistors must be chosen to
withstand the high voltages of STB events. Similarly, the breakdown
voltage of the ac coupling capacitors must be chosen to be robust to
STB events. The R1 resistor is protected because no current or
limited current flows through it during an STB event.
R1
FROM SOURCE
430Ω
100nF
1.3kΩ
A
2
IN
INPUT
CONNECTOR
Figure 7. Differential Input Network
The ADV7281A provides two STB diagnostic pins that generate an
interrupt when an STB event occurs. For more information, see
STB Diagnostics section.
Fully differential video transmission involves transmitting two
complementary CVBS signals. Pseudo differential video trans-
mission involves transmitting a CVBS signal and a source
ground signal.
Rev. A | Page 15 of 24
ADV7281A
Data Sheet
APPLICATIONS INFORMATION
The INSEL[4:0] bits specify predefined analog input routing
schemes, eliminating the need for manual mux programming
and allowing the user to route the various video signal types to
the decoder. For example, if the CVBS input is selected, the
remaining channels are powered down.
INPUT CONFIGURATION
The input format of the ADV7281A is specified using the
INSEL[4:0] bits (see Table 11). These bits also configure the
SDP core to process CVBS, differential CVBS, S-Video(Y/C), or
component (YPrPb) format. The INSEL[4:0] bits are located in
the user sub map at Address 0x00, Bits[4:0]. For more infor-
mation about the registers, see the Register Maps section.
Table 11. Input Format Specified by the INSEL[4:0] Bits
INSEL Bits[4:0] Setting
Video Format
Analog Inputs
00000
CVBS
CVBS input on AIN1
00001
CVBS
CVBS input on AIN2
00010
CVBS
CVBS input on AIN3
00011
CVBS
CVBS input on AIN4
00100
CVBS
Reserved
00101
CVBS
Reserved
00110
CVBS
CVBS input on AIN5
00111
CVBS
CVBS input on AIN6
01000
01001
01010
01011
S-Video (Y/C)
S-Video (Y/C)
S-Video (Y/C)
S-Video (Y/C)
YPrPb
Y input on AIN1; C input on AIN2
Y input on AIN3; C input on AIN4
Reserved
Y input on AIN5; C input on AIN6
Y input on AIN1; Pb input on AIN2, Pr input on AIN3
Reserved
01100
01101
YPrPb
01110
01111
10000
10001
Differential CVBS
Differential CVBS
Differential CVBS
Differential CVBS
Reserved
Positive input on AIN1; negative input on AIN2
Positive input on AIN3; negative input on AIN4
Reserved
Positive input on AIN5, negative input on AIN6
Reserved
10010 to 11111
Rev. A | Page 16 of 24
Data Sheet
ADV7281A
Table 12. DIAG1_SLICER_PWRDN Function
DIAG1_SLICER_PWRDN Setting Diagnostic Slice Level
STB DIAGNOSTICS
The ADV7281A senses an STB event via the DIAG1 and DIAG2
pins. The DIAG1 and DIAG2 pins can sense an STB event on
either the positive or the negative differential input because of
the negligible voltage drop across Resistor R1.
0
Power up the diagnostic
circuitry for the DIAG1 pin.
1 (Default)
Power down the diagnostic
circuitry for the DIAG1 pin.
R5
DIAG1_SLICE_LEVEL[2:0], Address 0x5D, Bits[4:2],
User Sub Map
DIAG1
INPUT
R4
CONNECTOR
100nF
1.3kΩ
The DIAG1_SLICE_LEVEL[2:0] bits allow the user to set the
diagnostic slice level for the DIAG1 pin. When a voltage greater
than the diagnostic slice level is seen on the DIAG1 pin, an STB
interrupt is triggered.
A
1
IN
430Ω
EXT
ESD
VIDEO INPUT
R1
FROM SOURCE
430Ω
100nF
To set the diagnostic slice level correctly, power up the diagnostic
circuitry for the DIAG1 pin (see Table 12).
1.3kΩ
A
2
IN
INPUT
CONNECTOR
Table 13. DIAG1_SLICE_LEVEL[2:0] Settings
DIAG1_SLICE_LEVEL[2:0] Setting Diagnostic Slice Level
Figure 8. Diagnostic Connections
000
001
010
011 (Default)
100
101
110
111
75 mV
Resistors R4 and R5 divide down the voltage at the input con-
nector to protect a DIAGx pin from an STB event. The DIAGx
pin circuitry compares this voltage to a programmable reference
voltage, known as the diagnostic slice level. When the diagnostic
slice level is exceeded, an STB event occurs.
225 mV
375 mV
525 mV
675 mV
825 mV
975 mV
1.125 V
When a DIAGx pin voltage exceeds the diagnostic slice level
voltage, a hardware interrupt is triggered and indicated by
INTRQ
the
pin. A readback register is also provided, allowing
the user to determine the DIAGx pin on which the STB event
occurred.
DIAG2 Pin
DIAG2_SLICER_PWRDN, Address 0x5E, Bit 6,
User Sub Map
Use Equation 1 to find the trigger voltage for a selected
diagnostic slice level.
This bit powers up or powers down the diagnostic circuitry for
the DIAG2 pin.
R5 +R4
VSTB _TRIGGER
=
× DIAGNOSTIC_SLICE_LEVEL
(1)
R5
Table 14. DIAG2_SLICER_PWRDN Function
DIAG2_SLICER_PWRDN Setting Diagnostic Slice Level
where:
V
STB_TRIGGER is the minimum voltage required at the input
0
Power up the diagnostic
circuitry for the DIAG2 pin.
Power down the diagnostic
circuitry for the DIAG2 pin.
connector to trigger the STB interrupt on the ADV7281A.
DIAGNOSTIC_SLICE_LEVEL is the programmable reference
voltage.
1 (Default)
PROGRAMMING THE STB DIAGNOSTIC FUNCTION
DIAG2_SLICE_LEVEL[2:0], Address 0x5E, Bits[4:2],
User Sub Map
By default, the STB diagnostic function is disabled on the
ADV7281A. To enable the diagnostic function, follow the
instructions in this section.
The DIAG2_SLICE_LEVEL[2:0] bits allow the user to set the
diagnostic slice level for the DIAG2 pin. When a voltage greater
than the diagnostic slice level is seen on the DIAG2 pin, an STB
interrupt is triggered.
DIAG1 Pin
DIAG1_SLICER_PWRDN, Address 0x5D, Bit 6,
User Sub Map
For the diagnostic slice level to be set correctly, the diagnostic
circuitry for the DIAG2 pin must be powered up (see Table 14).
This bit powers up or powers down the diagnostic circuitry for
the DIAG1 pin.
Rev. A | Page 17 of 24
ADV7281A
Data Sheet
Table 15. DIAG2_SLICE_LEVEL[2:0] Settings
DIAG2_SLICE_LEVEL[2:0] Setting Diagnostic Slice Level
MIPI Tx OUTPUT
The decoder in the ADV7281A outputs an ITU-R BT.656 data
stream. The ITU-R BT.656 data stream is connected into a MIPI
Tx module. Data from the MIPI Tx module feeds into a D-PHY
physical layer and output serially from the device.
000
001
010
011 (default)
100
101
110
111
75 mV
225 mV
375 mV
525 mV
675 mV
825 mV
975 mV
1.125 V
The output of the ADV7281A consists of a single data channel
on the D0P and D0N lanes and a clock channel on the CLKP
and CLKN lanes.
Video data is output over the data lanes in high speed mode. The
data lanes enter low power mode during the horizontal and
vertical blanking periods.
ADAPTIVE CONTRAST ENHANCEMENT (ACE)
The clock lanes clock the output video. After programming the
ADV7281A, the clock lanes exit low power mode and remain in
high speed mode until the device is reset or powered down.
The ADV7281A can increase the contrast of an image depending
on the content of the picture, brightening areas and darkening
dark areas. The optional ACE feature enables the contrast within
dark areas to increase without significantly affecting the bright
areas. The ACE feature is useful in automotive applications,
where it can be important to discern objects in shaded areas.
The ADV7281A outputs video data in an 8-bit, YCrCb 4:2:2
format at a nominal data rate of 216 Mbps.
The ACE function is disabled by default. To enable the ACE
function, execute the register writes shown in Table 16. To
disable the ACE function, execute the register writes shown in
Table 17.
Table 16. Register Writes to Enable the ACE Function
Register Map
Register Address
Register Write
0x40
0x80
Description
User Sub Map (0x40 or 0x42)
User Sub Map 2 (0x40 or 0x42)
User Sub Map 2 (0x40 or 0x42)
0x0E
0x80
0x0E
Enter User Sub Map 2
Enable ACE
Reenter user sub map
0x00
Table 17. Register Writes to Disable the ACE Function
Register Map
Register Address
Register Write
0x40
0x00
Description
User Sub Map (0x40 or 0x42)
User Sub Map 2 (0x40 or 0x42)
User Sub Map 2 (0x40 or 0x42)
0x0E
0x80
0x0E
Enter User Sub Map 2
Disable ACE
Reenter user sub map
0x00
D0P
(1 BIT)
MIPI Tx DATA
OUTPUT (8 BITS)
D0N
ITU-R BT.656
ANALOG
VIDEO
INPUT
(1 BIT)
DATA LANE LP
SIGNALS (2 BITS)
DATA
STREAM
VIDEO
DECODER
MIPI
Tx
D-PHY
Tx
CLKP
(1 BIT)
CLOCK LANE LP
SIGNALS (2 BITS)
CLKN
(1 BIT)
Figure 9. MIPI Tx Output Stage of the ADV7281A
Rev. A | Page 18 of 24
Data Sheet
ADV7281A
I2C PORT DESCRIPTION
the SDATA and SCLK lines for the start condition and the
correct transmitted address.
The ADV7281A supports a 2-wire, I2C-compatible serial interface
(see Figure 10). Two inputs, serial data (SDATA) and serial clock
(SCLK), carry information between the ADV7281A and the
system I2C master controller. The I2C port of the ADV7281A
allows the user to set up and configure the decoder and read back
captured VBI data (see Figure 11).
The ADV7281A has a variety of possible I2C slave addresses and
subaddresses (see the Register Maps section). The main map of
the ADV7281A has four possible slave addresses for read and
write operations, depending on the logic level of the ALSB pin
(see Table 18).
W
The R/ bit determines the direction of the data. Logic 0 on
the LSB of the first byte means the master writes information to
the peripheral. Logic 1 on the LSB of the first byte means the
master reads information from the peripheral.
The ADV7281A acts as standard I2C slave devices on the bus.
The data on the SDATA pin is eight bits long, supporting the
W
7-bit address plus the R/ bit. The device has subaddresses to
enable access to the internal registers; therefore, it interprets the
first byte as the device address and the second byte as the starting
subaddress. The subaddresses auto-increment, allowing data to be
written to or read from the starting subaddress. A data transfer
is always terminated by a stop condition. The user can also
access any unique subaddress register individually without
updating all the registers.
Table 18. Main Map I2C Addresses
R/W Bit
ALSB Pin
Slave Address
0x40 (write)
0x41 (read)
0x42 (write)
0x43 (read)
0
0
1
1
0
1
0
1
Stop and start conditions can be detected at any stage during the
data transfer. If these conditions are asserted out of sequence with
normal read and write operations, they cause an immediate
jump to the idle condition. During a given SCLK high period,
issue only one start condition, one stop condition, or a single
stop condition followed by a single start condition. If an invalid
subaddress is issued by the user, the ADV7281A does not issue
an acknowledge and returns to the idle condition.
The ALSB pin controls Bit 1 of the slave address. By changing
the logic level of the ALSB pin, it is possible to control two
ADV7281A devices in an application without using the same
I2C slave address. The LSB (Bit 0) specifies either a read or write
operation: Logic 1 corresponds to a read operation, and Logic 0
corresponds to a write operation.
If the highest subaddress is exceeded in auto-increment mode,
take one of the following actions:
To control the device on the bus, use the following protocol:
1. The master initiates a data transfer by establishing a start
condition, defined as a high to low transition on SDATA
while SCLK remains high, and indicates that an
address/data stream follows.
In read mode, the register contents of the highest subaddress
continue to output until the master device issues a no acknow-
ledge, indicating the end of a read. A no acknowledge
condition occurs when the SDATA line is not pulled low
on the ninth pulse.
In write mode, the data for the invalid byte is not loaded
into a subaddress register. A no acknowledge is issued by
the ADV7281A, and the device returns to the idle
condition.
2. All peripherals respond to the start condition and shift
W
the next eight bits (the 7-bit address plus the R/ bit).
The bits are transferred from MSB to LSB.
3. The peripheral that recognizes the transmitted address
responds by pulling the data line low during the ninth
clock pulse; this is known as an acknowledge (ACK) bit.
4. All other devices withdraw from the bus and maintain an
idle condition. In the idle condition, the device monitors
SDATA
SCLK
S
P
1–7
8
9
1–7
8
9
1–7
DATA
8
9
START ADDR R/W ACK SUBADDRESS ACK
ACK
STOP
Figure 10. Bus Data Transfer
WRITE
S
S
SLAVE ADDR A(S) SUBADDRESS A(S)
LSB = 0
DATA
A(S)
DATA
A(M)
A(S) P
SEQUENCE
LSB = 1
READ
SEQUENCE
SLAVE ADDR A(S) SUBADDRESS A(S)
S
SLAVE ADDR A(S)
DATA
DATA
A(M) P
S = START BIT
P = STOP BIT
A(S) = ACKNOWLEDGE BY SLAVE
A(M) = ACKNOWLEDGE BY MASTER
A(S) = NO ACKNOWLEDGE BY SLAVE
A(M) = NO ACKNOWLEDGE BY MASTER
Figure 11. Read and Write Sequence
Rev. A | Page 19 of 24
ADV7281A
Data Sheet
REGISTER MAPS
The ADV7281A contains two register maps: the main map and
the CSI map (see Figure 12).
SUB_USR_EN[1:0] bits in the user sub map (Address 0x0E,
Bits[6:5]) to 00.
The main map of the ADV7281A contains three sub maps: the user
sub map, interrupt/VDP sub map, and User Sub Map 2.
Interrupt/VDP Sub Map
The interrupt/VDP sub map contains registers that program
For more information about the ADV7281A registers, see the
ADV7280A/ADV7281A/ADV7282A Device Manual.
INTRQ
internal interrupts, control the
pin, and decode VBI data.
The interrupt/VDP sub map has the same I2C slave address as
the main map. To access the interrupt/VDP sub map, set the
SUB_USR_EN bits in the main map (Address 0x0E[6:5]) to 01.
Main Map
The I2C slave address of the main map of the ADV7281A is set by
the ALSB pin (see Table 18). The main map allows the user to
program the I2C slave address of the CSI map. The three sub
maps are accessed by writing to the SUB_USR_EN[1:0] bits
(Address 0x0E, Bits[6:5]) within the user sub map (see Figure 12
and Table 19).
User Sub Map 2
User Sub Map 2 contains registers that control the ACE, down-
dither, and fast lock functions. It also contains controls that set the
acceptable input luma and chroma limits before the ADV7281A
enters free run and color kill modes.
User Sub Map 2 has the same I2C slave address as the main map.
To access User Sub Map 2, set the SUB_USR_EN[1:0] bits in the
main map (Address 0x0E Bits[6:5]) to 10.
User Sub Map
The user sub map contains registers that program the AFE and
digital core of the ADV7281A. The user sub map has the same I2C
slave address as the main map. To access the user sub map, set the
MAIN MAP
CSI MAP
DEVICE ADDRESS
DEVICE ADDRESS
ALSB PIN LOW
WRITE: 0x40
READ: 0x41
ALSB PIN HIGH
WRITE: 0x42
READ: 0x43
WRITE: 0x88 (RECOMMENDED
READ: 0x89 SETTINGS)
CSI MAP ADDRESS IS
PROGRAMMABLE AND SET BY
REGISTER 0xFE IN THE USER
SUB MAP
0x0E[6:5] = 00
0x0E[6:5] = 01
0x0E[6:5] = 10
USER
SUB MAP
INTERRUPT/VDP
SUB MAP
USER SUB
MAP 2
Figure 12. Register Map and Sub Map Access
Table 19. I2C Register Map and Sub Map Addresses
R/ Bit
W
ALSB Pin
Slave Address
0x40
0x41
0x40
0x41
0x40
0x41
0x42
0x43
0x42
0x43
0x42
0x43
0x88
0x89
SUB_USR_EN[1:0] Bits (Address 0x0E Bits[6:5]) Register Map or Sub Map
0
0
0
0
0
0
1
1
1
1
1
1
X1
X1
0 (write)
1 (read)
0 (write)
1 (read)
0 (write)
1 (read)
0 (write)
1 (read)
0 (write)
1 (read)
0 (write)
1 (read)
0 (write)
1 (read)
00
00
01
01
10
10
00
00
01
01
10
10
XX1
XX1
User sub map
User sub map
Interrupt/VDP sub map
Interrupt/VDP sub map
User Sub Map 2
User Sub Map 2
User sub map
User sub map
Interrupt/VDP sub map
Interrupt/VDP sub map
User Sub Map 2
User Sub Map 2
CSI map
CSI map
1 X and XX mean don’t care.
Rev. A | Page 20 of 24
Data Sheet
ADV7281A
CSI Map
To reset the I2C slave address of the CSI map, write to the
CSI_TX_SLAVE_ADDRESS[6:0] bits in the main register map
(Address 0xFE, Bits[7:1]). Set these bits to a value of 0x88 (I2C
write address); I2C read address is 0x89.
The CSI map contains registers that control the MIPI Tx output
stream from the ADV7281A.
The CSI map has a programmable I2C slave address, which is
programmed using Register 0xFE in the user sub map of the
main map. The default value for the CSI map address is 0x00;
however, the CSI map cannot be accessed until the I2C slave
address is reset. The recommended I2C slave address for the
CSI map is 0x88.
SUB_USR_EN[1:0] Bits, Address 0x0E, Bits[6:5]
The user sub map is available by default. The other two sub
maps are accessed using the SUB_USR_EN[1:0] bits. When
programming of the interrupt/VDP map or User Sub Map 2 is
completed, it is necessary to write to the SUB_USR_EN[1:0]
bits to return to the user sub map.
Rev. A | Page 21 of 24
ADV7281A
Data Sheet
PCB LAYOUT RECOMMENDATIONS
The ADV7281A is a high precision, high speed, mixed-signal
device. To achieve maximum performance from the device, it is
important to use a well designed PCB. This section provides
guidelines for designing a PCB for use with the ADV7281A.
VREFN AND VREFP PINS
Place the circuit associated with the VREFN and VREFP pins as
close as possible to the ADV7281A and on the same side of the
PCB as the device.
ANALOG INTERFACE INPUTS
DIGITAL OUTPUTS
When routing the analog interface inputs on the PCB, keep
track lengths to a minimum. Use 75 Ω trace impedances when
possible; trace impedances other than 75 Ω increase the chance
of reflections.
INTRQ
The ADV7281A digital outputs are
GPO2.
and GPO0 to
Minimize the trace length that the digital outputs must drive.
Longer traces have higher capacitance, requiring more current
and, in turn, causing more internal digital noise. Shorter traces
reduce the possibility of reflections.
POWER SUPPLY DECOUPLING
It is recommended that each power supply pin be decoupled
with 100 nF and 10 nF capacitors. The basic principle is to place
Adding a 30 Ω to 50 Ω series resistor can suppress reflections,
reduce EMI, and reduce current spikes inside the ADV7281A. If
using series resistors, place them as close as possible to the pins of
the ADV7281A. However, try not to add vias or extra length to the
output trace in an attempt to place the resistors closer.
a decoupling capacitor within approximately 0.5 cm of the PVDD
,
AVDD, DVDD, and MVDD power pins. Avoid placing the decoupling
capacitors on the opposite side of the PCB from the ADV7281A
because doing so introduces inductive vias in the path.
Place the decoupling capacitors between the power plane and
the power pin. Current flows from the power plane to the
capacitor and then to the power pin. Do not apply the power
connection between the capacitor and the power pin. The best
approach is to place a via near or beneath the decoupling capaci-
tor pads down to the power plane (see Figure 13).
If possible, limit the capacitance that each digital output must
drive to less than 15 pF. This recommendation can be easily
accommodated by keeping traces short and by connecting the
outputs to only one device. Loading the outputs with excessive
capacitance increases the current transients inside the ADV7281A,
creating more digital noise on the power supplies.
VIA TO SUPPLY
SUPPLY
EXPOSED METAL PAD
10nF
100nF
GROUND
VIA TO GND
The ADV7281A has an exposed metal pad on the bottom of the
package. This pad must be soldered to ground. The exposed
pad is used for proper heat dissipation, noise suppression, and
mechanical strength.
Figure 13. Recommended Power Supply Decoupling
Ensure that the power supplies connected to the ADV7281A,
DIGITAL INPUTS
PVDD and MVDD, in particular, are well regulated and filtered. For
The digital inputs of the ADV7281A are designed to work with
1.8 V signals (3.3 V for DVDDIO) and are not tolerant of 5 V
signals. Extra components are required if 5 V logic signals must
be applied to the decoder.
optimum performance of the ADV7281A, it is recommended to
isolate each supply and to use decoupling on each pin, located
as physically close to the ADV7281A package as possible.
Some graphic controllers use substantially different levels of
power when active (during active picture time) and when idle
(during horizontal and vertical sync periods). This disparity can
result in a measurable change in the voltage supplied to the analog
supply regulator, which can, in turn, produce changes in the regu-
lated analog supply voltage. This problem can be mitigated by
regulating the analog supply, or at least the PVDD supply, from a
different, cleaner power source, for example, from a 12 V supply.
MIPI Tx OUTPUTS
It is recommended that the MIPI Tx output traces be kept as
short as possible and on the same side of the PCB as the
ADV7281A device. It is also recommended that a solid plane
(preferably a ground plane) be placed on the layer adjacent to
the MIPI Tx traces to provide a solid reference plane.
MIPI Tx transmission operates in both differential and single-
ended modes. During high speed transmission, the pair of
outputs operates in differential mode; in low power mode, the
pair operates as two independent single-ended traces. Therefore, it
is recommended that each output pair be routed as two loosely
coupled, 50 Ω single-ended traces to reduce the risk of crosstalk
between the two traces in low power mode.
Using a single ground plane for the entire board is also recom-
mended. Experience has shown that the noise performance is
the same or better with a single ground plane. Using multiple
ground planes can be detrimental because each separate ground
plane is smaller, and long ground loops can result.
Rev. A | Page 22 of 24
Data Sheet
ADV7281A
TYPICAL CIRCUIT CONNECTIONS
Figure 14 provides an example of how to connect the
ADV7281A. For a detailed schematic of the ADV7281A
evaluation board, refer to the ADV7281A product page.
See the XTAL data sheet (from the XTAL vendor), the AN-1260
Application Note, and the calculator tool (visit the design
resources section at www.analog.com/ADV7281A to download)
for the correct values for C1, C2, and RDAMP
.
1.8V
3.3V
VIDDIO_
1.8V
1.8V
VDD_
VDD_
VDD_
0.1µF
DIFF1+
IN
1.3kΩ
0.1µF
0.1µF
0.1µF
0.1µF
430Ω
430Ω
10nF
10nF
10nF
10nF
75Ω
FULLY
DIFFERENTIAL
CVBS INPUT
0.1µF
IN
DIFF1–
1.8V
1.3kΩ
VDD_
3.3V
VIDDIO_
9.1kΩ
1.8V
VDD_
1.8V
VDD_
DIAG1
0.1µF
1.8V
1kΩ
VDD_
10nF
0.1µF
0.1µF
17
18
DIFF2+
IN
IN
IN
IN
1.3kΩ
430Ω
430Ω
9
IN
75Ω
PSEUDO
DIFFERENTIAL
CVBS INPUT
10
22
IN
DIFF2–
1.3kΩ
9.1kΩ
11
12
23
24
CLKP
CLKN
IN
IN
IN
IN
DIAG2
1kΩ
ADV7281A
25
0.1µF
SINGLE-ENDED
CVBS INPUT
EXAMPLE
IN
26
27
24Ω
24Ω
IN
IN
IN
IN
51Ω
6
7
8
0.1µF
XTAL CIRCUIT
SINGLE-ENDED
CVBS INPUT
EXAMPLE
IN
14
15
51Ω
C1
R
DAMP
28.63636MHz
5
INTRQ
INTRQ
C2
LOCATE AS CLOSE TO, AND ON THE SAME
SIDE OF THE PCB AS, THE ADV7281A
LOCATE VREFN AND VREFP
CAPACITOR AS CLOSE
AS POSSIBLE TO THE
ADV7281A AND ON THE
SAME SIDE OF THE PCB AS
THE ADV7281A
DVDIO
29
ALSB TIED HIGH: I2C ADDRESS = 0X42
ALSB TIED LOW: I2C ADDRESS = 0X40
19
20
VREFP
VREFN
0.1µF
32
28
31
30
PWRDWN
PWRDWN
RESET
RESET
SCLK
SCLK
SDATA
SDATA
Figure 14. Typical Connection Diagram
Rev. A | Page 23 of 24
ADV7281A
Data Sheet
OUTLINE DIMENSIONS
DETAIL A
(JEDEC 95)
5.10
5.00 SQ
4.90
0.30
0.25
0.18
PIN 1
INDICATOR
PIN 1
25
32
INDIC ATOR AREA OPTIONS
(SEE DETAIL A)
24
1
0.50
BSC
3.75
3.60 SQ
3.55
EXPOSED
PAD
17
8
16
9
0.50
0.40
0.30
0.20 MIN
TOP VIEW
TOP VIEW
BOTTOM VIEW
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.80
0.75
0.70
0.05 MAX
0.02 NOM
SECTION OF THIS DATA SHEET.
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-WHHD-5
Figure 15. 32-Lead Lead Frame Chip Scale Package [LFCSP]
5 mm × 5 mm Body and 0.75 mm Package Height
(CP-32-12)
Dimensions shown in millimeters
ORDERING GUIDE
Model1, 2
Temperature Range
−40°C to +105°C
−40°C to +105°C
Package Description
Package Option
CP-32-12
CP-32-12
ADV7281AWBCPZ-M
ADV7281AWBCPZ-M-RL
EVAL-ADV7281AMEBZ
32-Lead Lead Frame Chip Scale Package [LFCSP]
32-Lead Lead Frame Chip Scale Package [LFCSP]
Evaluation Board for the ADV7281A
1 Z = RoHS Compliant Part.
2 W = Qualified for Automotive Applications.
AUTOMOTIVE PRODUCTS
The ADV7281AW models are available with controlled manufacturing to support the quality and reliability requirements of automotive
applications. Note that these automotive models may have specifications that differ from the commercial models; therefore, designers should
review the Specification section of this data sheet carefully. Only the automotive grade products shown are available for use in automotive
applications. Contact your local Analog Devices account representative for specific product ordering information and to obtain the specific
Automotive Reliability reports for these models.
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
©2017–2018 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D16147-0-5/18(A)
Rev. A | Page 24 of 24
相关型号：
©2020 ICPDF网 联系我们和版权申明