ADV7390_15_技术文档

Low Power, Chip Scale,

10-Bit SD/HD Video Encoder

Data Sheet

ADV7390/ADV7391/ADV7392/ADV7393

Gamma correction

FEATURES

Programmable adaptive filter control

Programmable sharpness filter control

CGMS (720p/1080i) and CGMS Type B (720p/1080i)

Dual data rate (DDR) input support

Enhanced definition (ED) programmable features

(525p/625p)

8× oversampling (216 MHz output)

Internal test pattern generator

Black bar, hatch, flat field/frame

Individual Y and PrPb output delay

Gamma correction

Programmable adaptive filter control

Fully programmable YCrCb to RGB matrix

Undershoot limiter

3 high quality, 10-bit video DACs

16× (216 MHz) DAC oversampling for SD

8× (216 MHz) DAC oversampling for ED

4× (297 MHz) DAC oversampling for HD

37 mA maximum DAC output current

Multiformat video input support

4:2:2 YCrCb (SD, ED, and HD)

4:4:4 RGB (SD)

Multiformat video output support

Composite (CVBS) and S-Video (Y-C)

Component YPrPb (SD, ED, and HD)

Component RGB (SD, ED, and HD)

Lead frame chip scale package (LFCSP) options

32-lead, 5 mm × 5 mm LFCSP

Macrovision Rev 1.2 (525p/625p) (ADV7390/ADV7392 only)

CGMS (525p/625p) and CGMS Type B (525p)

Dual data rate (DDR) input support

Standard definition (SD) programmable features

16× oversampling (216 MHz)

Internal test pattern generator

Color and black bar

Controlled edge rates for start and end of active video

Individual Y and PrPb output delay

Undershoot limiter

40-lead, 6 mm × 6 mm LFCSP

Wafer level chip scale package (WLCSP) option

30-ball, 5 × 6 WLCSP with single DAC output

Advanced power management

Patented content-dependent low power DAC operation

Automatic cable detection and DAC power-down

Individual DAC on/off control

Sleep mode with minimal power consumption

74.25 MHz 8-/10-/16-bit high definition input support

Compliant with SMPTE 274M (1080i), 296M (720p),

and 240M (1035i)

Gamma correction

Digital noise reduction (DNR)

EIA/CEA-861B compliance support

Multiple chroma and luma filters

Luma-SSAF filter with programmable gain/attenuation

PrPb SSAF

Separate pedestal control on component and

composite/S-Video output

NTSC M, PAL B/D/G/H/I/M/N, PAL 60 support

NTSC and PAL square pixel operation (24.54 MHz/29.5 MHz)

Macrovision Rev 7.1.L1 (SD) and Rev 1.2 (ED) compliant

Copy generation management system (CGMS)

Closed captioning and wide screen signaling (WSS)

Integrated subcarrier locking to external video source

Complete on-chip video timing generator

On-chip test pattern generation

Programmable features

Luma and chroma filter responses

Vertical blanking interval (VBI)

Subcarrier frequency (f_SC) and phase

Luma delay

VCR FF/RW sync mode

Macrovision Rev 7.1.L1 (ADV7390/ADV7392 only)

Copy generation management system (CGMS)

Wide screen signaling (WSS)

Closed captioning

Serial MPU interface with I²C compatibility

2.7 V or 3.3 V analog operation

1.8 V digital operation

1.8 V or 3.3 V I/O operation

High definition (HD) programmable features

(720p/1080i/1035i)

4× oversampling (297 MHz)

Temperature range: −40°C to +85°C

W Grade automotive range: −40°C to +105°C

Qualified for automotive applications

Internal test pattern generator

Color and black bar, hatch, flat field/frame

Fully programmable YCrCb to RGB matrix

Rev. H

Document Feedback

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rightsof third parties that may result fromits use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks andregisteredtrademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Technical Support

www.analog.com

ADV7390/ADV7391/ADV7392/ADV7393

Data Sheet

TABLE OF CONTENTS

ED/HD Timing Reset ................................................................ 51

SD Subcarrier Frequency Lock................................................. 51

SD VCR FF/RW Sync ................................................................ 52

Vertical Blanking Interval ......................................................... 52

SD Subcarrier Frequency Control............................................ 52

SD Noninterlaced Mode............................................................ 52

SD Square Pixel Mode ............................................................... 52

Filters............................................................................................ 54

ED/HD Test Pattern Color Controls ....................................... 55

Color Space Conversion Matrix ............................................... 55

SD Luma and Color Scale Control........................................... 57

SD Hue Adjust Control.............................................................. 57

SD Brightness Detect ................................................................. 57

SD Brightness Control............................................................... 57

SD Input Standard Autodetection............................................ 58

Double Buffering........................................................................ 58

Programmable DAC Gain Control.......................................... 58

Gamma Correction.................................................................... 59

ED/HD Sharpness Filter and Adaptive Filter Controls......... 60

Features .............................................................................................. 1

Revision History ............................................................................... 3

Applications....................................................................................... 5

General Description......................................................................... 5

Functional Block Diagrams............................................................. 6

Specifications..................................................................................... 7

Power Supply Specifications........................................................ 7

Input Clock Specifications .......................................................... 7

Analog Output Specifications..................................................... 7

Digital Input/Output Specifications—3.3 V ............................. 8

Digital Input/Output Specifications—1.8 V ............................. 8

MPU Port Timing Specifications ............................................... 8

Digital Timing Specifications—3.3 V........................................ 9

Digital Timing Specifications—1.8 V...................................... 10

Video Performance Specifications ........................................... 11

Power Specifications .................................................................. 11

Timing Diagrams........................................................................ 12

Absolute Maximum Ratings.......................................................... 18

Thermal Resistance .................................................................... 18

ESD Caution................................................................................ 18

Pin Configurations and Function Descriptions ......................... 19

Typical Performance Characteristics ........................................... 21

MPU Port Description................................................................... 26

I²C Operation.............................................................................. 26

Register Map Access....................................................................... 28

Register Programming............................................................... 28

Subaddress Register (SR7 to SR0) ............................................ 28

ADV7390/ADV7391 Input Configuration ................................. 46

Standard Definition.................................................................... 46

Enhanced Definition/High Definition .................................... 46

Enhanced Definition (at 54 MHz) ........................................... 46

ADV7392/ADV7393 Input Configuration ................................. 47

Standard Definition.................................................................... 47

Enhanced Definition/High Definition .................................... 48

Enhanced Definition (at 54 MHz) ........................................... 48

Output Configuration.................................................................... 49

Design Features............................................................................... 50

Output Oversampling................................................................ 50

ED/HD Sharpness Filter and Adaptive Filter Application

Examples...................................................................................... 61

SD Digital Noise Reduction...................................................... 62

SD Active Video Edge Control................................................. 64

External Horizontal and Vertical Synchronization Control. 65

Low Power Mode........................................................................ 66

Cable Detection .......................................................................... 66

DAC Autopower-Down............................................................. 66

Sleep Mode.................................................................................. 66

Pixel and Control Port Readback............................................. 67

Reset Mechanisms...................................................................... 67

SD Teletext Insertion ................................................................. 67

Printed Circuit Board Layout and Design .................................. 69

Unused Pins ................................................................................ 69

DAC Configurations.................................................................. 69

Video Output Buffer and Optional Output Filter.................. 69

Printed Circuit Board (PCB) Layout ....................................... 70

Additional Layout Considerations for the WLCSP Package....71

Typical Applications Circuits.................................................... 72

Copy Generation Management System....................................... 74

SD CGMS .................................................................................... 74

HSYNC

VSYNC

and

HD Interlace External

Considerations............................................................................ 51

Rev. H | Page 2 of 108

Data Sheet

ADV7390/ADV7391/ADV7392/ADV7393

ED CGMS.....................................................................................74

HD CGMS....................................................................................74

CGMS CRC Functionality .........................................................74

SD Wide Screen Signaling..............................................................77

SD Closed Captioning ....................................................................78

Internal Test Pattern Generation...................................................79

SD Test Patterns...........................................................................79

ED/HD Test Patterns ..................................................................79

SD Timing ........................................................................................80

HD Timing.......................................................................................85

Video Output Levels .......................................................................86

SD YPrPb Output Levels—SMPTE/EBU N10........................86

ED/HD YPrPb Output Levels ...................................................87

SD/ED/HD RGB Output Levels................................................88

SD Output Plots ..........................................................................89

Video Standards ..............................................................................90

Configuration Scripts .....................................................................92

Standard Definition....................................................................92

Enhanced Definition ..................................................................99

High Definition.........................................................................101

ADV739x Evaluation Board ........................................................104

Outline Dimensions......................................................................105

Ordering Guide .........................................................................107

Automotive Products................................................................107

REVISION HISTORY

9/14—Rev. G to Rev. H

11/11—Rev. C to Rev. D

Changed Storage Temperature Range from −60°C to +100°C to

−60°C to +150°C; Table 13.............................................................18

Updated Figure 145, Outline Dimensions.................................105

Changes to Ordering Guide.........................................................107

Changes to Features Section............................................................1

Updated Outline Dimensions and changes to Automotive

Products Section............................................................................107

2/13—Rev. F to Rev. G

9/11—Rev. B to Rev. C

Change to Features Section..............................................................1

Changes to Table 14 ........................................................................18

Changes to Figure 62 ......................................................................48

Changes to Ordering Guide.........................................................107

Changes to MPU Port Description Section.................................26

Changes to Ordering Guide.........................................................107

7/10—Rev. A to Rev. B

Changes to Features Section............................................................1

Change to Applications Section ......................................................5

Changes to General Description.....................................................5

Added Table 2, Renumbered Subsequent Tables ..........................5

Added Figure 2, Renumbered Subsequent Figures ......................6

Changes to Full-Drive Output Current Parameter, Table 5 ........7

Changes to Table 14 ........................................................................18

Added Figure 20..............................................................................19

Changes to Table 15 ........................................................................19

Changes to ADV7390/ADV7391 Input Configuration

11/12—Rev. E to Rev. F

Updated Outline Dimensions......................................................105

Changes to Ordering Guide.........................................................107

2/12—Rev. D to Rev. E

Changes to Table 1 ............................................................................5

Changes to Digital Input/Output Specifications—

1.8 V Section ......................................................................................8

Changes to Table 15 ........................................................................21

Changes to Table 20 ........................................................................31

Changes to Table 23 ........................................................................34

Changes to Table 28 ........................................................................39

Changes to 16-Bit 4:4:4 RGB Mode Section................................47

Added External Sync Polarity Section..........................................51

Deleted ED/HD Nonstandard Timing Mode Section, Figure 63,

and Table 41, Renumbered Sequentially......................................51

Changed SD Subcarrier Frequency Lock, Subcarrier Phase

Reset, and Timing Reset Section to SD Subcarrier Frequency

Lock Section.....................................................................................52

Deleted Subaddress 0x84, Bits[2:1] Section, Timing Reset (TR)

Mode Section, Subcarrier Phase Reset (SCR) Mode Section,

Figure 64, and Figure 65.................................................................52

Changes to Ordering Guide.........................................................121

Section ..............................................................................................45

Added Additional Layout Considerations for the WLCSP

Package Section ...............................................................................71

Added Figure 97..............................................................................73

Changes to Configuration Scripts Section...................................92

Changes to Subaddress 0x00, Table 66.........................................93

Changes to Subaddress 0x00, Table 80.........................................95

Changes to Subaddress 0x00, Table 83.........................................95

Changes to Subaddress 0x00, Table 97.........................................98

Updated Outline Dimensions, Added Figure 150....................106

Changes to Ordering Guide.........................................................106

Rev. H | Page 3 of 108

ADV7390/ADV7391/ADV7392/ADV7393

Data Sheet

3/09—Rev. 0 to Rev. A

Changes to Table 30 ....................................................................... 40

Changes to Table 31 ....................................................................... 41

Added Table 32 ............................................................................... 42

Renamed Features Section to Design Features Section............. 48

Changes to ED/HD Nonstandard Timing Mode Section......... 48

Changes to Features Section............................................................ 1

Deleted Detailed Features Section, Changes to Table 1............... 4

Changes to Figure 1, Added Figure 2............................................. 5

Changes to Table 2, Input Clock Specifications Section, and

Analog Output Specifications Section........................................... 6

Changes to Digital Input/Output Specifications—3.3 V Section

and Table 5......................................................................................... 7

Added Digital Input/Output Specifications—1.8 V Section and

Table 6 ................................................................................................ 7

Changes to MPU Port Timing Specifications Section,

Default Conditions ........................................................................... 7

Changes to Digital Timing Specifications—3.3 V Section and

Table 8 ................................................................................................ 8

Added Digital Timing Specifications—1.8 V Section and

Table 9 ................................................................................................ 9

Added Video Performance Specifications Section, Default

Conditions ....................................................................................... 10

Added Power Specifications Section, Default Conditions........ 10

Changes to Table 11........................................................................ 10

Changes to Figure 16...................................................................... 16

Changes to Table 12........................................................................ 17

Changes to Table 14, Pin 19 and Pin 1 Descriptions ................. 18

Changes to MPU Port Description Section ................................ 25

Changes to I²C Operation Section ............................................... 25

Added Table 15 ............................................................................... 25

Changes to Table 17........................................................................ 28

Changes to Table 19, 0x30 Bit Description ................................. 30

Changes to Table 27........................................................................ 37

Changes to Table 29, 0x8B Bit Description................................. 39

HSYNC

VSYNC

Added the HD Interlace External

and

Considerations Section.................................................................. 49

Changes to SD Subcarrier Frequency Lock, Subcarrier Reset,

and Timing Reset Section.............................................................. 49

Changes to Subaddress 0x8C to Subaddress 0x8F Section....... 51

Changes to Programming the F_SCSection................................... 51

Changes to Subaddress 0x82, Bit 4 Section................................. 51

Added SD Manual CSC Matrix Adjust Feature Section............ 54

Added Table 47 ............................................................................... 55

Changes to Subaddress 0x9C to Subaddress 0x9F Section....... 56

Changes to Subaddress 0xBA Section.......................................... 56

Added Sleep Mode Section ........................................................... 65

Changes to Pixel and Control Port Readback Section .............. 66

Changes to Reset Mechanisms Section ....................................... 66

Added SD Teletext Insertion Section........................................... 66

Added Figure 87 ............................................................................. 67

Added Figure 88 ............................................................................. 68

Changes to DAC Configuration Section ..................................... 68

Added Unused Pins Section.......................................................... 68

Changes to Power Supply Sequencing Section........................... 70

Changes to Internal Test Pattern Generation Section ............... 77

Changes to SD Timing, Mode 0 (CCIR-656)—Slave Option

(Subaddress 0x8A = XXXXX000) Section.................................. 78

10/06—Revision 0: Initial Version

Rev. H | Page 4 of 108

Data Sheet

ADV7390/ADV7391/ADV7392/ADV7393

APPLICATIONS

Table 1. Standards Directly Supported by the LFCSP Packages

Mobile handsets

Digital still cameras

Active

Resolution

Frame

Clock Input

(MHz)

I/P¹Rate (Hz)

Standard

720 × 240

720 × 288

720 × 480

P

I

59.94

50

29.97

27

Portable media and DVD players

Portable game consoles

Digital camcorders

ITU-R

BT.601/656

Set-top box (STB)

720 × 576

640 × 480

768 × 576

I

25

27

ITU-R

BT.601/656

NTSC Square

Pixel

PAL Square

Pixel

Automotive infotainment (ADV7392 and ADV7393 only)

GENERAL DESCRIPTION

29.97

25

24.54

29.5

The ADV7390/ADV7391/ADV7392/ADV7393 are a family of

high speed, digital-to-analog video encoders on single monolithic

chips. Three 2.7 V/3.3 V, 10-bit video DACs (a single DAC for

the WLCSP package) provide support for composite (CVBS),

S-Video (Y-C), or component (YPrPb/RGB) analog outputs in

either standard definition (SD) or high definition (HD) video

formats. The single DAC WLCSP package supports CVBS

(NTSC and PAL) output only in SD resolution (see Table 2).

720 × 483

720 × 576

720 × 483

720 × 576

1920 × 1035

1280 × 720

P

I

59.94

50

59.94

50

30

29.97

60, 50, 30,

25, 24

23.97,

27

74.25

74.1758

74.25

SMPTE 293M

BTA T-1004

ITU-R BT.1358

ITU-R BT.1362

SMPTE 240M

SMPTE 296M

Optimized for low power operation, occupying a minimal

footprint, and requiring few external components, these

encoders are ideally suited to portable and power-sensitive

applications requiring TV-out functionality. Cable detection

and DAC autopower-down features ensure that power

consumption is kept to a minimum.

I

P

1280 × 720

P

74.1758

SMPTE 296M

59.94, 29.97

1920 × 1080

I

P

30, 25

29.97

30, 25, 24

23.98, 29.97 74.1758

24 74.25

74.25

74.1758

74.25

SMPTE 274M

ITU-R BT.709-5

The ADV7390/ADV7391 have an 8-bit video input port that

supports SD video formats over an SDR interface and HD video

formats over a DDR interface. The ADV7392/ADV7393 have

a 16-bit video input port that can be configured in a variety of

ways. SD RGB input is supported.

¹I = interlaced, P = progressive.

All members of the family support embedded EAV/SAV timing

codes, external video synchronization signals, and the I²C® and

communication protocol. Table 1 and Table 2 list the video

standards directly supported by the ADV739x family.

Table 2. Standards Directly Supported by the WLCSP Package

Active

Resolution

Frame

Clock Input

(MHz)

I/P¹Rate (Hz)

Standard

720 × 480

720 × 576

640 × 480

768 × 576

I

29.97

27

ITU-R

BT.601/656

ITU-R

BT.601/656

NTSC Square

Pixel

PAL Square

Pixel

25

27

29.97

25

24.54

29.5

¹I = interlaced, P = progressive.

Rev. H | Page 5 of 108

ADV7390/ADV7391/ADV7392/ADV7393

Data Sheet

FUNCTIONAL BLOCK DIAGRAMS

V_DD(2)

V_AA

DGND (2)

AGND

SCL SDA ALSB

SFL

ADV7390/ADV7391

GND_IO

V_{DD_IO}

VBI DATA SERVICE

INSERTION

MPU PORT

SUBCARRIER FREQUENCY

LOCK (SFL)

11-BIT

DAC 1

DAC 2

DAC 3

16×

YCrCb

TO

PROGRAMMABLE

ADD

FILTER

LUMINANCE

FILTER

11-BIT

DAC 2

SYNC

RGB

SDR/DDR

8-BIT SD

OR

8-BIT ED/HD

SD/ED/HD INPUT

4:2:2 TO 4:4:4

11-BIT

DAC 3

DEINTERLEAVE

PROGRAMMABLE

CHROMINANCE

FILTER

16×

FILTER

ADD

BURST

SIN/COS DDS

BLOCK

ASYNC

BYPASS

YCrCb

YCbCr

PROGRAMMABLE

TO

ED/HD FILTERS

4×

FILTER

RGB MATRIX

HDTV

TEST

PATTERN

GENERATOR

SHARPNESS AND

ADAPTIVE FILTER

CONTROL

POWER

MANAGEMENT

CONTROL

REFERENCE

AND CABLE

DETECT

R_SET

VIDEO TIMING GENERATOR

16×/4× OVERSAMPLING PLL

RESET

HSYNC

VSYNC

CLKIN PV_DDPGND EXT_LF

COMP

Figure 1. ADV7390/ADV7391 (32-Lead LFCSP)

V

_DD(2)

V_AA

DGND (2)

SCL SDA ALSB

MPU PORT

AGND

SFL

ADV7390BCBZ

GND_IO

V_{DD_IO}

VBI DATA SERVICE

INSERTION

SUBCARRIER FREQUENCY

LOCK (SFL)

16×

FILTER

PROGRAMMABLE

LUMINANCE

FILTER

ADD

SYNC

11-BIT

DAC 1

SDR/DDR

SD INPUT

8-BIT SD

4:2:2 TO 4:4:4

DEINTERLEAVE

PROGRAMMABLE

CHROMINANCE

FILTER

16×

FILTER

ADD

BURST

SIN/COS DDS

BLOCK

POWER

MANAGEMENT

CONTROL

REFERENCE

AND CABLE

DETECT

R_SET

VIDEO TIMING GENERATOR

16× OVERSAMPLING PLL

RESET

HSYNC

VSYNC

CLKIN PV_DDPGND EXT_LF

COMP

Figure 2. ADV7390BCBZ-A (30-Ball WLCSP)

V_AA

V

_DD(2)

DGND (2)

SCL SDA ALSB

MPU PORT

SFL

AGND

ADV7392/ADV7393

GND_IO

VBI DATA SERVICE

INSERTION

SUBCARRIER FREQUENCY

LOCK (SFL)

V_{DD_IO}

12-BIT

DAC 1

DAC 2

DAC 3

16×

YCrCb

TO

PROGRAMMABLE

ADD

FILTER

LUMINANCE

FILTER

12-BIT

DAC 2

SYNC

RGB

TO

YCrCb

MATRIX

RGB

SDR/DDR

8-/10-/16-BIT SD

OR

8-/10-/16-BIT ED/HD

SD/ED/HD INPUT

4:2:2 TO 4:4:4

DEINTERLEAVE

12-BIT

DAC 3

PROGRAMMABLE

CHROMINANCE

FILTER

16×

FILTER

ADD

BURST

SIN/COS DDS

BLOCK

ASYNC

BYPASS

YCrCb

YCbCr

PROGRAMMABLE

TO

ED/HD FILTERS

4×

FILTER

RGB MATRIX

HDTV

TEST

PATTERN

GENERATOR

SHARPNESS AND

ADAPTIVE FILTER

CONTROL

POWER

MANAGEMENT

CONTROL

REFERENCE

AND CABLE

DETECT

VIDEO TIMING GENERATOR

16x/4x OVERSAMPLING PLL

R_SET

RESET

HSYNC

VSYNC

CLKIN PV_DDPGND EXT_LF

COMP

Figure 3. ADV7392/ADV7393 (40-Lead LFCSP)

Rev. H | Page 6 of 108

Data Sheet

ADV7390/ADV7391/ADV7392/ADV7393

SPECIFICATIONS

POWER SUPPLY SPECIFICATIONS

All specifications T_MINto T_MAX(−40°C to +85°C), unless otherwise noted.

Table 3.

Parameter

Min

Typ

Max

Unit

SUPPLY VOLTAGES

V_DD

V_{DD_IO}

PV_DD

V_AA

1.71

2.6

1.8

3.3

1.8

3.3

1.89

3.63

1.89

3.465

V

POWER SUPPLY REJECTION RATIO

0.002

%/%

INPUT CLOCK SPECIFICATIONS

V_DD= 1.71 V to 1.89 V, PV_DD= 1.71 V to 1.89 V, V_AA= 2.6 V to 3.465 V, V_{DD_IO}= 1.71 V to 3.63 V.

All specifications T_MINto T_MAX(−40°C to +85°C), unless otherwise noted.

Table 4.

Parameter

Conditions¹

SD/ED

Min

Typ

27

Max

Unit

f_CLKIN

MHz

ED (at 54 MHz)

HD

54

74.25

MHz

CLKIN High Time, t₉

CLKIN Low Time, t₁₀

CLKIN Peak-to-Peak Jitter Tolerance

40

% of one clock cycle

ns

2

¹SD = standard definition, ED = enhanced definition (525p/625p), HD = high definition.

ANALOG OUTPUT SPECIFICATIONS

V_DD= 1.71 V to 1.89 V, PV_DD= 1.71 V to 1.89 V, V_AA= 2.6 V to 3.465 V, V_{DD_IO}= 1.71 V to 3.63 V.

All specifications T_MINto T_MAX(−40°C to +85°C), unless otherwise noted.

Table 5.

Parameter

Conditions

Min

Typ

Max

Unit

Full-Drive Output Current

R_SET= 510 Ω, R_L= 37.5 Ω

All DACs enabled

33

34.6

37

mA

R_SET= 510 Ω, R_L= 37.5 Ω

DAC 1 enabled only¹

R_SET= 4.12 kΩ, R_L= 300 Ω

DAC 1, DAC 2, DAC 3

31.5

0

33.5

37

mA

Low-Drive Output Current

DAC-to-DAC Matching

Output Compliance, V_OC

Output Capacitance, C_OUT

Analog Output Delay²

4.3

2.0

mA

%

V

pF

ns

1.4

10

6

1

DAC Analog Output Skew

DAC 1, DAC 2, DAC 3

¹The recommended method of bringing this value back to the ideal value is by adjusting Register 0x0B to the recommended value of 0x12.

²Output delay measured from the 50% point of the rising edge of the input clock to the 50% point of the DAC output full-scale transition.

Rev. H | Page 7 of 108

ADV7390/ADV7391/ADV7392/ADV7393

Data Sheet

DIGITAL INPUT/OUTPUT SPECIFICATIONS—3.3 V

V_DD= 1.71 V to 1.89 V, PV_DD= 1.71 V to 1.89 V, V_AA= 2.6 V to 3.465 V, V_{DD_IO}= 2.97 V to 3.63 V.

All specifications T_MINto T_MAX(−40°C to +85°C), unless otherwise noted.

Table 6.

Parameter

Conditions

Min

Typ

4

Max

Unit

V

µA

pF

V

µA

pF

Input High Voltage, V_IH

Input Low Voltage, V_IL

Input Leakage Current, I_IN

Input Capacitance, C_IN

Output High Voltage, V_OH

Output Low Voltage, V_OL

Three-State Leakage Current

Three-State Output Capacitance

2.0

0.8

10

V_IN= V_{DD_IO}

I_SOURCE= 400 µA

I_SINK= 3.2 mA

V_IN= 0.4 V, 2.4 V

2.4

0.4

1

4

DIGITAL INPUT/OUTPUT SPECIFICATIONS—1.8 V

When V_{DD_IO}is set to 1.8 V, all the digital video inputs and control inputs, such as I²C, HS, and VS, should use 1.8 V levels.

_DD= 1.71 V to 1.89 V, PV_DD= 1.71 V to 1.89 V, V_AA= 2.6 V to 3.465 V, V_{DD_IO}= 1.71 V to 1.89 V.

V

All specifications T_MINto T_MAX(−40°C to +85°C), unless otherwise noted.

Table 7.

Parameter

Conditions

Min

Typ

4

Max

Unit

V

pF

V

Input High Voltage, V_IH

Input Low Voltage, V_IL

Input Capacitance, C_IN

Output High Voltage, V_OH

Output Low Voltage, V_OL

Three-State Output Capacitance

0.7 V_{DD_IO}

0.3 V_{DD_IO}

I_SOURCE= 400 µA

I_SINK= 3.2 mA

V_{DD_IO}– 0.4

0.4

4

pF

MPU PORT TIMING SPECIFICATIONS

V_DD= 1.71 V to 1.89 V, PV_DD= 1.71 V to 1.89 V, V_AA= 2.6 V to 3.465 V, V_{DD_IO}= 1.71 V to 3.63 V.

All specifications T_MINto T_MAX(−40°C to +85°C), unless otherwise noted.

Table 8.

Parameter

Conditions

Min

Typ

Max

Unit

MPU PORT, I²C MODE¹

See Figure 17

SCL Frequency

0

400

kHz

µs

ns

µs

SCL High Pulse Width, t₁

SCL Low Pulse Width, t₂

Hold Time (Start Condition), t₃

Setup Time (Start Condition), t₄

Data Setup Time, t₅

SDA, SCL Rise Time, t₆

SDA, SCL Fall Time, t₇

Setup Time (Stop Condition), t₈

0.6

1.3

0.6

100

300

0.6

¹Guaranteed by characterization.

Rev. H | Page 8 of 108

Data Sheet

ADV7390/ADV7391/ADV7392/ADV7393

DIGITAL TIMING SPECIFICATIONS—3.3 V

V_DD= 1.71 V to 1.89 V, PV_DD= 1.71 V to 1.89 V, V_AA= 2.6 V to 3.465 V, V_{DD_IO}= 2.97 V to 3.63 V.

All specifications T_MINto T_MAX(−40°C to +85°C), unless otherwise noted.

Table 9.

Parameter

Conditions¹

Min

Typ

Max

Unit

VIDEO DATA AND VIDEO CONTROL PORT^{2, 3}

Data Input Setup Time, t₁₁

4

SD

2.1

2.3

1.7

1.0

1.1

1.0

2.1

2.3

1.7

1.0

1.1

1.0

ns

ED/HD-SDR

ED/HD-DDR

ED (at 54 MHz)

SD

ED/HD-SDR

ED/HD-DDR

ED (at 54 MHz)

SD

ED/HD-SDR or ED/HD-DDR

ED (at 54 MHz)

SD

ED/HD-SDR or ED/HD-DDR

ED (at 54 MHz)

SD

4

Data Input Hold Time, t₁₂

4

Control Input Setup Time, t₁₁

4

Control Input Hold Time, t₁₂

4

Control Output Access Time, t₁₃

12

10

ED/HD-SDR, ED/HD-DDR, or ED (at 54 MHz)

SD

4

Control Output Hold Time, t₁₄

4.0

ED/HD-SDR, ED/HD-DDR, or ED (at 54 MHz) 3.5

PIPELINE DELAY⁵

SD¹

CVBS/Y-C Outputs (2×)

CVBS/Y-C Outputs (8×)

CVBS/Y-C Outputs (16×)

Component Outputs (2×)

Component Outputs (8×)

Component Outputs (16×)

ED¹

SD oversampling disabled

SD oversampling enabled

SD oversampling disabled

SD oversampling enabled

68

79

67

78

69

84

Clock cycles

Component Outputs (1×)

Component Outputs (4×)

Component Outputs (8×)

HD¹

ED oversampling disabled

ED oversampling enabled

41

49

46

Clock cycles

Component Outputs (1×)

Component Outputs (2×)

Component Outputs (4×)

RESET CONTROL

HD oversampling disabled

HD oversampling enabled

40

42

44

Clock cycles

RESET Low Time

100

ns

¹SD = standard definition, ED = enhanced definition (525p/625p), HD = high definition, SDR = single data rate, DDR = dual data rate.

²Video data: P[15:0] for ADV7392/ADV7393 or P[7:0] for ADV7390/ADV7391.

³Video control:

and

.

HSYNC

VSYNC

⁴Guaranteed by characterization.

⁵Guaranteed by design.

Rev. H | Page 9 of 108

ADV7390/ADV7391/ADV7392/ADV7393

Data Sheet

DIGITAL TIMING SPECIFICATIONS—1.8 V

V_DD= 1.71 V to 1.89 V, PV_DD= 1.71 V to 1.89 V, V_AA= 2.6 V to 3.465 V, V_{DD_IO}= 1.71 V to 1.89 V.

All specifications T_MINto T_MAX(−40°C to +85°C), unless otherwise noted.

Table 10.

Parameter

Conditions¹

Min

Typ

Max

Unit

VIDEO DATA AND VIDEO CONTROL PORT^{2, 3}

Data Input Setup Time, t₁₁

4

SD

1.4

1.9

1.6

1.4

1.5

1.3

1.4

1.2

1.0

1.4

1.0

ns

ED/HD-SDR

ED/HD-DDR

ED (at 54 MHz)

SD

ED/HD-SDR

ED/HD-DDR

ED (at 54 MHz)

SD

ED/HD-SDR or ED/HD-DDR

ED (at 54 MHz)

SD

ED/HD-SDR or ED/HD-DDR

ED (at 54 MHz)

SD

4

Data Input Hold Time, t₁₂

4

Control Input Setup Time, t₁₁

4

Control Input Hold Time, t₁₂

4

Control Output Access Time, t₁₃

13

12

ED/HD-SDR, ED/HD-DDR, or ED (at 54 MHz)

SD

4

Control Output Hold Time, t₁₄

4.0

ED/HD-SDR, ED/HD-DDR, or ED (at 54 MHz) 5.0

PIPELINE DELAY⁵

SD¹

CVBS/Y-C Outputs (2×)

CVBS/Y-C Outputs (8×)

CVBS/Y-C Outputs (16×)

Component Outputs (2×)

Component Outputs (8×)

Component Outputs (16×)

ED¹

SD oversampling disabled

SD oversampling enabled

SD oversampling disabled

SD oversampling enabled

68

79

67

78

69

84

Clock cycles

Component Outputs (1×)

Component Outputs (4×)

Component Outputs (8×)

HD¹

ED oversampling disabled

ED oversampling enabled

41

49

46

Clock cycles

Component Outputs (1×)

Component Outputs (2×)

Component Outputs (4×)

RESET CONTROL

HD oversampling disabled

HD oversampling enabled

40

42

44

Clock cycles

RESET Low Time

100

ns

¹SD = standard definition, ED = enhanced definition (525p/625p), HD = high definition, SDR = single data rate, DDR = dual data rate.

²Video data: P[15:0] for ADV7392/ADV7393 or P[7:0] for ADV7390/ADV7391.

³Video control:

and

.

HSYNC

VSYNC

⁴Guaranteed by characterization.

⁵Guaranteed by design.

Rev. H | Page 10 of 108

Data Sheet

ADV7390/ADV7391/ADV7392/ADV7393

VIDEO PERFORMANCE SPECIFICATIONS

V_DD= 1.8 V, PV_DD= 1.8 V, V_AA= 3.3 V, V_{DD_IO}= 3.3 V, T_A= +25°C.

Table 11.

Parameter

Conditions

Min

Typ

Max

Unit

STATIC PERFORMANCE

Resolution

10

0.5

Bits

LSBs

Integral Nonlinearity (INL)¹

R_SET= 510 Ω, R_L= 37.5 Ω

Differential Nonlinearity (DNL)^{1, 2}R_SET= 510 Ω, R_L= 37.5 Ω

STANDARD DEFINTION (SD) MODE

Luminance Nonlinearity

Differential Gain

Differential Phase

Signal-to-Noise Ratio (SNR)³

0.5

0.6

58

%

Degrees

dB

NTSC

Luma ramp

Flat field full bandwidth

75

dB

ENHANCED DEFINITION (ED) MODE

Luma Bandwidth

Chroma Bandwidth

12.5

5.8

MHz

HIGH DEFINITION (HD) MODE

Luma Bandwidth

Chroma Bandwidth

30.0

13.75

MHz

¹Measured on DAC 1, DAC 2, and DAC 3.

²Differential nonlinearity (DNL) measures the deviation of the actual DAC output voltage step from the ideal. For +ve DNL, the actual step value lies above the ideal

step value. For −ve DNL, the actual step value lies below the ideal step value.

³Measured on the ADV7392/ADV7393 operating in 10-bit input mode.

POWER SPECIFICATIONS

V_DD= 1.8 V, PV_DD= 1.8 V, V_AA= 3.3 V, V_{DD_IO}= 3.3 V, T_A= +25°C.

Table 12.

Parameter

Conditions

Min

Typ

Max

Unit

NORMAL POWER MODE^{1, 2}

3

I_DD

SD (16× oversampling enabled), CVBS (only one DAC turned on)

SD (16× oversampling enabled), YPrPb (three DACs turned on)

ED (8× oversampling enabled)⁴

33

68

59

81

1

50

122

4

mA

HD (4× oversampling enabled)⁴

101

10

I_{DD_IO}

5

I_AA

One DAC enabled

All DACs enabled

151

10

I_PLL

SLEEP MODE

I_DD

I_AA

I_{DD_IO}

I_PLL

5

µA

0.3

0.2

0.1

¹R_SET= 510 Ω (all DACs operating in full-drive mode).

²75% color bar test pattern applied to pixel data pins.

³I_DDis the continuous current required to drive the digital core.

⁴Applicable to both single data rate (SDR) and dual data rate (DDR) input modes.

⁵I_AAis the total current required to supply all DACs.

Rev. H | Page 11 of 108

ADV7390/ADV7391/ADV7392/ADV7393

Data Sheet



t₁₃= control output access time

t₁₄= control output hold time

TIMING DIAGRAMS

The following abbreviations are used in Figure 4 to Figure 11:

In addition, see Table 35 for the ADV7390/ADV7391 pixel port

input configuration and Table 36 for the ADV7392/ADV7393

pixel port input configuration.



t₉= clock high time

t₁₀= clock low time

t₁₁= data setup time

t₁₂= data hold time

CLKIN

t₁₂

t₉

t₁₀

CONTROL

INPUTS

HSYNC

VSYNC

IN SLAVE MODE

Y0

t₁₁

Y1

Y2

PIXEL PORT

Cb0

Cr0

Cb2

t₁₃

Cr2

CONTROL

OUTPUTS

IN MASTER/SLAVE MODE

t₁₄

Figure 4. SD Input, 8-/10-Bit 4:2:2 YCrCb, Input Mode 000

CLKIN

t₉

t

t₁₂

10

CONTROL

INPUTS

HSYNC

VSYNC

IN SLAVE MODE

Y2

Y0

Y1

Y3

PIXEL PORT

Cb2

Cb0

Cr0

Cr2

t₁₁

t₁₃

CONTROL

OUTPUTS

IN MASTER/SLAVE MODE

t₁₄

Figure 5. SD Input, 16-Bit 4:2:2 YCrCb, Input Mode 000

Rev. H | Page 12 of 108

Data Sheet

ADV7390/ADV7391/ADV7392/ADV7393

CLKIN

t₁₂

t₉

t₁₀

CONTROL

INPUTS

HSYNC

VSYNC

PIXEL PORT

G0

B0

G1

B1

G2

B2

t₁₁

PIXEL PORT

R0

R1

R2

CONTROL

OUTPUTS

t₁₄

t₁₃

Figure 6. SD Input, 16-Bit 4:4:4 RGB, Input Mode 000

CLKIN

t₁₂

t₉

t₁₀

CONTROL

INPUTS

HSYNC

VSYNC

PIXEL PORT

Y0

Y1

Y2

Y3

Y4

Y5

Cb0

Cr0

Cb2

Cr2

Cb4

Cr4

t₁₁

t₁₃

CONTROL

OUTPUTS

t₁₄

Figure 7. ED/HD-SDR Input, 16-Bit 4:2:2 YCrCb, Input Mode 001

CLKIN*

t₉

t₁₀

CONTROL

INPUTS

HSYNC

VSYNC

PIXEL PORT

Cb0

Y0

Cr0

Y1

Cb2

Y2

Cr2

t₁₂

t₁₁

t₁₃

CONTROL

OUTPUTS

t₁₄

*LUMA/CHROMA CLOCK RELATIONSHIP CAN BE INVERTED USING SUBADDRESS 0x01, BITS 1 AND 2.

HSYNC VSYNC

), Input Mode 010

Figure 8. ED/HD-DDR Input, 8-/10-Bit 4:2:2 YCrCb (

/

Rev. H | Page 13 of 108

ADV7390/ADV7391/ADV7392/ADV7393

Data Sheet

CLKIN*

t₉

t₁₀

PIXEL PORT

3FF

t₁₂

00

XY

t₁₂

Cb0

Y0

Cr0

Y1

t₁₁

t₁₃

CONTROL

OUTPUTS

t₁₄

*LUMA/CHROMA CLOCK RELATIONSHIP CAN BE INVERTED USING SUBADDRESS 0x01, BITS 1 AND 2.

Figure 9. ED/HD-DDR Input, 8-/10-Bit 4:2:2 YCrCb (EAV/SAV), Input Mode 010

CLKIN

t₉

t₁₀

CONTROL

INPUTS

HSYNC

VSYNC

Cb0

Y0

Cr0

Y1

Cb2

Cr2

PIXEL PORT

Y2

t₁₂

t₁₃

t₁₄

t₁₁

CONTROL

OUTPUTS

HSYNC VSYNC

Figure 10. ED (at 54 MHz) Input, 8-/10-Bit 4:2:2 YCrCb (

/

), Input Mode 111

CLKIN

t₉

t₁₀

PIXEL PORT

3FF

00

XY

Cb0

Y0

Cr0

Y1

t₁₂

t₁₃

t₁₄

t₁₁

CONTROL

OUTPUTS

Figure 11. ED (at 54 MHz) Input, 8-/10-Bit 4:2:2 YCrCb (EAV/SAV), Input Mode 111

Rev. H | Page 14 of 108

Data Sheet

ADV7390/ADV7391/ADV7392/ADV7393

Y OUTPUT

b

HSYNC

VSYNC

PIXEL PORT

PIXEL PORT*

Y2

Y3

Y0

Y1

Cb0 Cr0 Cb2

Cr2

a

a = AS PER RELEVANT STANDARD.

b = PIPELINE DELAY. PLEASE REFER TO RELEVANT PIPELINE DELAY. THIS CAN BE FOUND IN THE DIGITAL TIMING

SPECIFICATION SECTION OF THE DATA SHEET.

A FALLING EDGE OF HSYNC INTO THE ENCODER GENERATES A SYNC FALLING EDGE ON THE OUTPUT AFTER A TIME

EQUAL TO THE PIPELINE DELAY.

HSYNC VSYNC

/

Figure 12. ED-SDR, 16-Bit 4:2:2 YCrCb (

) Input Timing Diagram

Y OUTPUT

b

HSYNC

VSYNC

Cr0

Y1

Cb0

Y0

PIXEL PORT

a

a(MIN) = 244 CLOCK CYCLES FOR 525p.

a(MIN) = 264 CLOCK CYCLES FOR 625p.

b = PIPELINE DELAY. PLEASE REFER TO RELEVANT PIPELINE DELAY. THIS CAN BE FOUND IN THE DIGITAL TIMING

SPECIFICATION SECTION OF THE DATA SHEET.

A FALLING EDGE OF HSYNC INTO THE ENCODER GENERATES A SYNC FALLING EDGE ON THE OUTPUT AFTER A TIME

EQUAL TO THE PIPELINE DELAY.

HSYNC VSYNC

) Input Timing Diagram

Figure 13. ED-DDR, 8-/10-Bit 4:2:2 YCrCb (

/

Rev. H | Page 15 of 108

ADV7390/ADV7391/ADV7392/ADV7393

Data Sheet

Y OUTPUT

b

HSYNC

VSYNC

Y2

Y3

Y0

Y1

PIXEL PORT

Cb0 Cr0 Cb2

Cr2

a

a = AS PER RELEVANT STANDARD.

b = PIPELINE DELAY. PLEASE REFER TO RELEVANT PIPELINE DELAY. THIS CAN BE FOUND IN THE DIGITAL TIMING

SPECIFICATION SECTION OF THE DATA SHEET.

A FALLING EDGE OF HSYNC INTO THE ENCODER GENERATES A FALLING EDGE OF TRI-LEVEL SYNC ON THE OUTPUT

AFTER A TIME EQUAL TO THE PIPELINE DELAY.

HSYNC VSYNC

/

Figure 14. HD-SDR, 16-Bit 4:2:2 YCrCb (

) Input Timing Diagram

Y OUTPUT

b

HSYNC

VSYNC

PIXEL PORT

Cr0

Y1

Cb0

Y0

a

a = AS PER RELEVANT STANDARD.

b = PIPELINE DELAY. PLEASE REFER TO RELEVANT PIPELINE DELAY. THIS CAN BE FOUND IN THE DIGITAL TIMING

SPECIFICATION SECTION OF THE DATA SHEET.

A FALLING EDGE OF HSYNC INTO THE ENCODER GENERATES A FALLING EDGE OF TRI-LEVEL SYNC ON THE OUTPUT

AFTER A TIME EQUAL TO THE PIPELINE DELAY.

HSYNC VSYNC

) Input Timing Diagram

Figure 15. HD-DDR, 8-/10-Bit 4:2:2 YCrCb (

/

Rev. H | Page 16 of 108

Data Sheet

ADV7390/ADV7391/ADV7392/ADV7393

HSYNC

VSYNC

Cr

Y

PIXEL PORT

Cb

Y

PAL = 264 CLOCK CYCLES

NTSC = 244 CLOCK CYCLES

Figure 16. SD Input Timing Diagram (Timing Mode 1)

t₅

t₃

SDA

SCL

t₆

t₁

t₂

t₇

t₄

t₈

Figure 17. MPU Port Timing Diagram (I²C Mode)

Rev. H | Page 17 of 108

ADV7390/ADV7391/ADV7392/ADV7393

Data Sheet

ABSOLUTE MAXIMUM RATINGS

THERMAL RESISTANCE

Table 13.

Parameter¹

Rating

θ_JAis specified for the worst-case conditions, that is, a device

soldered in a circuit board for surface-mount packages.

V_AAto AGND

V_DDto DGND

PV_DDto PGND

V_{DD_IO}to GND_IO

AGND to DGND

AGND to PGND

AGND to GND_IO

DGND to PGND

−0.3 V to +3.9 V

−0.3 V to +2.3 V

−0.3 V to +3.9 V

−0.3 V to +0.3 V

−0.3 V to V_{DD_IO}+ 0.3 V

−0.3 V to V_AA

Table 14. Thermal Resistance¹

2

3

4

Package Type

30-Ball WLCSP

32-Lead LFCSP

40-Lead LFCSP

θ_JA

35

27

26

θ_JC-TOP

θ_JC-BOTTOM

Unit

°C/W

1

32

N/A

1.2

1

¹Values are based on a JEDEC 4-layer test board.

²With the exposed metal paddle on the underside of the LFCSP soldered to

the PCB ground.

DGND to GND_IO

PGND to GND_IO

³This is the thermal resistance of the junction to the top of the package.

⁴This is the thermal resistance of the junction to the bottom of the package.

Digital Input Voltage to GND_IO

Analog Outputs to AGND

Max CLKIN Input Frequency

Storage Temperature Range (t_S)

Junction Temperature (t_J)

Lead Temperature (Soldering, 10 sec)

The ADV739x is an RoHS-compliant, Pb-free product. The lead

finish is 100% pure Sn electroplate. The device is suitable for Pb-

free applications up to 255°C ( 5°C) IR reflow (JEDEC STD-20).

80 MHz

−60°C to +150°C

150°C

The ADV739x is backward compatible with conventional SnPb

soldering processes. The electroplated Sn coating can be soldered

with SnPb solder pastes at conventional reflow temperatures of

220°C to 235°C.

260°C

¹Analog output short circuit to any power supply or common can be of an

indefinite duration.

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

ESD CAUTION

Rev. H | Page 18 of 108

Data Sheet

ADV7390/ADV7391/ADV7392/ADV7393

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

BALL A1 CORNER

1

2

3

4

5

V

R

V

DD

A

B

HSYNC

P0

DD_IO

SET

V

R

24

1

2

3

4

5

6

7

8

DD_IO

P2

P3

SET

PIN 1

INDICATOR

DAC1

VSYNC

SFL

P1

P3

P2

P4

23 COMP

22 DAC 1

21 DAC 2

20 DAC 3

P4

ADV7390/

ADV7391

TOP VIEW

(Not to Scale)

V

DD

V

COMP DGND

C

D

E

AA

DGND

P5

19

18 AGND

17 PV

V

AA

P6

DD

GND_IO

RESET

AGND

V

DGND

P6

DD

PV

DD

ALSB

P5

EXT_LF

SDA

NOTES

F

PGND

SCL

CLKIN

P7

1. THE EXPOSED PAD SHOULD BE CONNECTED

TO ANALOG GROUND (AGND).

TOP VIEW

(BALL SIDE DOWN)

Not to Scale

Figure 18. ADV7390/ADV7391 Pin Configuration

Figure 20. ADV7390BCBZ-A Pin Configuration

V

R

30

PIN 1

DD_IO

P4

1

2

SET

INDICATOR

29 COMP

28 DAC 1

27 DAC 2

26 DAC 3

P5

3

P6

4

ADV7392/

ADV7393

TOP VIEW

(Not to Scale)

P7

DD

5

V

6

25 V

AA

7

24

DGND

AGND

8

23

22

21

P8

PV

DD

9

P9

EXT_LF

PGND

10

P10

NOTES

1. THE EXPOSED PAD SHOULD BE CONNECTED

TO ANALOG GROUND (AGND).

Figure 19. ADV7392/ADV7393 Pin Configuration

Table 15. Pin Function Descriptions

Pin No.

ADV7390/

ADV7391

ADV7392/

ADV7393

ADV7390

WLCSP

Input/

Output Description

Mnemonic

9 to 7, 4 to 2,

31, 30

F5, E5, E4, C5,

C4, B5, B4, A4

P7 to P0

I

8-Bit Pixel Port (P7 to P0). P0 is the LSB. See Table 35 for

input modes (ADV7390/ADV7391).

18 to 15, 11 to

8, 5 to 2, 39 to

37, 34

P15 to P0

I

16-Bit Pixel Port (P15 to P0). P0 is the LSB. See Table 36 for

input modes (ADV7392/ADV7393).

13

27

19

F4

CLKIN

I

Pixel Clock Input for HD (74.25 MHz), ED¹(27 MHz or 54 MHz),

or SD (27 MHz).

Horizontal Synchronization Signal. This pin can also be

configured to output an SD, ED, or HD horizontal

synchronization signal. See the External Horizontal and

Vertical Synchronization Control section.

33

A2

HSYNC

I/O

26

25

32

31

B2

B3

VSYNC

SFL

I/O

Vertical Synchronization Signal. This pin can also be

configured to output an SD, ED, or HD vertical

synchronization signal. See the External Horizontal and

Vertical Synchronization Control section.

Subcarrier Frequency Lock (SFL) Input.

Rev. H | Page 19 of 108

ADV7390/ADV7391/ADV7392/ADV7393

Data Sheet

Pin No.

ADV7390/

ADV7391

ADV7392/

ADV7393

ADV7390

WLCSP

Input/

Output Description

Mnemonic

24

30

A1

R_SET

I

Controls the amplitudes of the DAC 1, DAC 2, and DAC 3

outputs. For full-drive operation (for example, into a 37.5 Ω

load), a 510 Ω resistor must be connected from R_SETto

AGND. For low-drive operation (for example, into a 300 Ω

load), a 4.12 kΩ resistor must be connected from R_SETto

AGND.

23

29

C2

B1

COMP

DAC 1

DAC 1, DAC 2,

DAC 3

SCL

SDA

O

Compensation Pin. Connect a 2.2 nF capacitor from COMP

to V_AA.

DAC Output. Full-drive and low-drive capable DAC

DAC Outputs. Full-drive and low-drive capable DACs.

O

22, 21, 20

28, 27, 26

12

11

10

14

13

12

20

F3

F2

E3

D3

I

I²C Clock Input.

I²C Data Input/Output.

ALSB sets up the LSB²of the MPU I²C address.

Resets the on-chip timing generator and sets the ADV739x

into its default mode.

I/O

I

ALSB

RESET

19

5, 28

25

6, 35

C1

A3, D4

V_AA

V_DD

P

Analog Power Supply (2.7 V or 3.3 V).

Digital Power Supply (1.8 V). For dual-supply

configurations, V_DDcan be connected to other 1.8 V

supplies through a ferrite bead or suitable filtering.

1

17

1

23

A5

E1

V_{DD_IO}

PV_DD

P

Input/Output Digital Power Supply (1.8 V or 3.3 V).

PLL Power Supply (1.8 V). For dual-supply configurations,

PV_DDcan be connected to other 1.8 V supplies through a

ferrite bead or suitable filtering.

16

15

18

6, 29

22

21

24

7, 36

E2

F1

D1

C3, D5

D2

EXT_LF

PGND

AGND

DGND

GND_IO

EPAD

I

External Loop Filter for the Internal PLL.

PLL Ground Pin.

Analog Ground Pin.

Digital Ground Pin.

Input/Output Supply Ground Pin.

Connect to analog ground (AGND).

G

32

40

External Pad

¹ED = enhanced definition = 525p and 625p.

²LSB = least significant bit. In the ADV7390/ADV7392, setting the LSB to 0 sets the I²C address to 0xD4. Setting it to 1 sets the I²C address to 0xD6. In the

ADV7391/ADV7393, setting the LSB to 0 sets the I²C address to 0x54. Setting it to 1 sets the I²C address to 0x56.

Rev. H | Page 20 of 108

Data Sheet

ADV7390/ADV7391/ADV7392/ADV7393

TYPICAL PERFORMANCE CHARACTERISTICS

Y RESPONSE IN ED 8× OVERSAMPLING MODE

1.0

EDPr/Pb RESPONSE. LINEAR INTERP FROM 4:2:2 TO 4:4:4

0

0.5

0

–10

–20

–30

–40

–50

–60

–70

–80

–0.5

–1.0

–1.5

–2.0

–2.5

–3.0

0

20

40

60

80 100 120 140 160 180 200

FREQUENCY (MHz)

0

2

4

6

8

10

12

FREQUENCY (MHz)

Figure 21. ED 8× Oversampling, PrPb Filter (Linear) Response

Figure 24. ED 8× Oversampling, Y Filter Response (Focus on Pass Band)

HD Pr/Pb RESPONSE. SSAF INTERP FROM 4:2:2 TO 4:4:4

10

EDPr/Pb RESPONSE. SSAF INTERP FROM 4:2:2 TO 4:4:4

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–10

–20

–30

–40

–50

–60

–70

–80

0

20

40

60

80 100 120 140 160 180 200

FREQUENCY (MHz)

0

18.5

37.0

55.5

74.0

92.5

111.0 129.5 148.0

FREQUENCY (MHz)

Figure 22. ED 8× Oversampling, PrPb Filter (SSAF™) Response

Figure 25. HD 4× Oversampling, PrPb (SSAF) Filter Response

(4:2:2 Input)

Y RESPONSE IN ED 8× OVERSAMPLING MODE

0

HD Pr/Pb RESPONSE. 4:4:4 INPUT MODE

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–10

–20

–30

–40

–50

–60

–70

–80

–100

0

20

40

60

80 100 120 140 160 180 200

FREQUENCY (MHz)

10 20 30 40 50 60 70 80 90 100 110 120 130 140

FREQUENCY (MHz)

Figure 23. ED 8× Oversampling, Y Filter Response

Figure 26. HD 4× Oversampling, PrPb (SSAF) Filter Response

(4:4:4 Input)

Rev. H | Page 21 of 108

ADV7390/ADV7391/ADV7392/ADV7393

Data Sheet

Y RESPONSE IN HD 4× OVERSAMPLING MODE

10

0

–10

–20

–30

–40

–50

–60

–70

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

0

18.5

37.0

55.5

74.0

92.5

111.0 129.5 148.0

0

2

4

6

8

10

12

FREQUENCY (MHz)

Figure 27. HD 4× Oversampling, Y Filter Response

Figure 30. SD PAL, Luma Low-Pass Filter Response

Y PASS BAND IN HD 4x OVERSAMPLING MODE

3.0

1.5

0

–10

–20

–30

–40

–50

–60

–70

0

–1.5

–3.0

–4.5

–6.0

–7.5

–9.0

–10.5

–12.0

0

2

4

6

8

10

12

27.750

46.250

30.063 32.375 34.688 37.000 39.312 41.625 43.937

FREQUENCY (MHz)

Figure 31. SD NTSC, Luma Notch Filter Response

Figure 28. HD 4× Oversampling, Y Filter Response (Focus on Pass Band)

0

–10

–20

–30

–40

–50

–60

–70

0

–10

–20

–30

–40

–50

–60

–70

0

2

4

6

8

10

12

0

2

4

6

8

10

12

FREQUENCY (MHz)

Figure 32. SD PAL, Luma Notch Filter Response

Figure 29. SD NTSC, Luma Low-Pass Filter Response

Rev. H | Page 22 of 108

Data Sheet

ADV7390/ADV7391/ADV7392/ADV7393

Y RESPONSE IN SD OVERSAMPLING MODE

5

0

–10

–20

–30

–40

–50

–60

–70

–80

4

3

2

1

0

–1

5

6

7

0

20

40

60

80 100 120 140 160 180 200

FREQUENCY (MHz)

0

1

2

3

4

FREQUENCY (MHz)

Figure 33. SD 16× Oversampling, Y Filter Response

Figure 36. SD Luma SSAF Filter, Programmable Gain

1

0

–10

–20

–30

–40

–50

–60

–70

0

–1

–2

–3

–4

–5

0

2

4

6

8

10

12

0

1

2

3

4

5

6

7

FREQUENCY (MHz)

Figure 34. SD Luma SSAF Filter Response up to 12 MHz

Figure 37. SD Luma SSAF Filter, Programmable Attenuation

4

2

0

–10

0

–20

–30

–40

–50

–60

–70

–2

–4

–6

–8

–10

–12

0

1

2

3

4

5

6

7

0

2

4

6

8

10

12

FREQUENCY (MHz)

Figure 35. SD Luma SSAF Filter, Programmable Responses

Figure 38. SD Luma CIF Low-Pass Filter Response

Rev. H | Page 23 of 108

ADV7390/ADV7391/ADV7392/ADV7393

Data Sheet

0

–10

–20

–30

–40

–50

–60

–70

0

–10

–20

–30

–40

–50

–60

–70

0

2

4

6

8

10

12

0

2

4

6

8

10

12

FREQUENCY (MHz)

Figure 39. SD Luma QCIF Low-Pass Filter Response

Figure 42. SD Chroma 1.3 MHz Low-Pass Filter Response

0

–10

–20

–30

–40

–50

–60

–70

0

–10

–20

–30

–40

–50

–60

–70

0

2

4

6

8

10

12

0

2

4

6

8

FREQUENCY (MHz)

Figure 43. SD Chroma 1.0 MHz Low-Pass Filter Response

Figure 40. SD Chroma 3.0 MHz Low-Pass Filter Response

0

–10

–20

–30

–40

–50

–60

–70

–10

–20

–30

–40

–50

–60

–70

0

2

4

6

8

10

12

4

6

8

10

0

2

FREQUENCY (MHz)

Figure 44. SD Chroma 0.65 MHz Low-Pass Filter Response

Figure 41. SD Chroma 2.0 MHz Low-Pass Filter Response

Rev. H | Page 24 of 108

Data Sheet

ADV7390/ADV7391/ADV7392/ADV7393

0

–10

–20

–30

–40

–50

–60

–70

0

–10

–20

–30

–40

–50

–60

–70

0

2

4

6

8

10

12

0

2

4

6

8

10

12

FREQUENCY (MHz)

Figure 45. SD Chroma CIF Low-Pass Filter Response

Figure 46. SD Chroma QCIF Low-Pass Filter Response

Rev. H | Page 25 of 108

ADV7390/ADV7391/ADV7392/ADV7393

Data Sheet

MPU PORT DESCRIPTION

Devices such as a microprocessor can communicate with the

ADV739x through a 2-wire serial (I²C-compatible) bus. After

power-up or reset, the MPU port is configured for I²C operation.

The various devices on the bus use the following protocol. The

master initiates a data transfer by establishing a start condition,

defined by a high-to-low transition on SDA while SCL remains

high. This indicates that an address/data stream follows. All

peripherals respond to the start condition and shift the next

I²C OPERATION

The ADV739x supports a 2-wire serial (I²C-compatible)

microprocessor bus driving multiple peripherals. This port

operates in an open-drain configuration. Two wires, serial data

(SDA) and serial clock (SCL), carry information between any

device connected to the bus and the ADV739x. The slave

address depends on the device (ADV7390, ADV7391,

ADV7392, or ADV7393), the operation (read or write), and the

state of the ALSB pin (0 or 1). See Table 16, Figure 47, and

Figure 48. The LSB sets either a read or a write operation. Logic

1 corresponds to a read operation, and Logic 0 corresponds to a

write operation. A1 is controlled by setting the ALSB pin of the

ADV739x to Logic 0 or Logic 1.

W

eight bits (7-bit address plus the R/ bit).

The bits are transferred from MSB down to LSB. The peripheral

that recognizes the transmitted address responds by pulling the

data line low during the ninth clock pulse. This is known as an

acknowledge bit. All other devices withdraw from the bus at

this point and maintain an idle condition. The idle condition

occurs when the device monitors the SDA and SCL lines

waiting for the start condition and the correct transmitted

W

address. The R/ bit determines the direction of the data.

Logic 0 on the LSB of the first byte means that the master writes

information to the peripheral. Logic 1 on the LSB of the first byte

means that the master reads information from the peripheral.

Table 16. ADV739x I²C Slave Addresses

The ADV739x acts as a standard slave device on the bus. The

data on the SDA pin is eight bits long, supporting the 7-bit

addresses plus the R/ bit. It interprets the first byte as the

device address and the second byte as the starting subaddress.

There is a subaddress auto-increment facility. This allows data

to be written to or read from registers in ascending subaddress

sequence starting at any valid subaddress. A data transfer is

always terminated by a stop condition. The user can also access

any unique subaddress register on a one-by-one basis without

updating all the registers.

Device

ALSB

Operation

Write

Read

Write

Read

Slave Address

0xD4

0xD5

0xD6

0xD7

0

1

0

1

ADV7390

and

ADV7392

W

Write

Read

Write

Read

0x54

0x55

0x56

0x57

ADV7391

and

ADV7393

Stop and start conditions can be detected at any stage during

the data transfer. If these conditions are asserted out of

sequence with normal read and write operations, they cause an

immediate jump to the idle condition. During a given SCL high

period, the user should issue only a start condition, a stop

condition, or a stop condition followed by a start condition. If

an invalid subaddress is issued by the user, the ADV739x does

not issue an acknowledge but returns to the idle condition. If the

user uses the auto-increment method of addressing the encoder

and exceeds the highest subaddress, the following actions are

taken:

1

0

1

0

1

A1

X

ADDRESS

CONTROL

SET UP BY

ALSB

READ/WRITE

CONTROL

0

1

WRITE

READ

Figure 47. ADV7390/ADV7392 I²C Slave Address



In read mode, the highest subaddress register contents are

output until the master device issues a no acknowledge.

This indicates the end of a read. A no acknowledge condition

occurs when the SDA line is not pulled low on the ninth pulse.

In write mode, the data for the invalid byte is not loaded

into any subaddress register, a no acknowledge is issued by

the ADV739x, and the part returns to the idle condition.

0

1

0

1

0

1

A1

X

ADDRESS

CONTROL

SET UP BY

ALSB



READ/WRITE

CONTROL

0

1

WRITE

READ

Figure 49 shows an example of data transfer for a write sequence

and the start and stop conditions. Figure 50 shows bus write

and read sequences.

Figure 48. ADV7391/ADV7393 I²C Slave Address

Rev. H | Page 26 of 108

Data Sheet

ADV7390/ADV7391/ADV7392/ADV7393

SDA

SCL

S

P

9

1–7

9

1–7

8

1–7

8

START ADDR R/W ACK SUBADDRESS ACK

DATA

ACK

STOP

Figure 49. I²C Data Transfer

WRITE

S

SLAVE ADDR A(S)

LSB = 0

SUBADDR

A(S)

DATA

A(S)

DATA

A(M)

A(S) P

SEQUENCE

LSB = 1

READ

SEQUENCE

SLAVE ADDR A(S)

A(S)

S

SLAVE ADDR A(S)

DATA

A(M) P

S = START BIT

P = STOP BIT

A(S) = ACKNOWLEDGE BY SLAVE

A(M) = ACKNOWLEDGE BY MASTER

A (S) = NO-ACKNOWLEDGE BY SLAVE

A (M) = NO-ACKNOWLEDGE BY MASTER

Figure 50. I²C Read and Write Sequence

Rev. H | Page 27 of 108

ADV7390/ADV7391/ADV7392/ADV7393

Data Sheet

REGISTER MAP ACCESS

A microprocessor can read from or write to all registers of the

ADV739x via the MPU port, except for registers that are

specified as read-only or write-only registers.

REGISTER PROGRAMMING

Table 17 to Table 34 describe the functionality of each register.

All registers can be read from as well as written to, unless

otherwise stated.

The subaddress register determines the register accessed by the

next read or write operation. All communication through the

MPU port starts with an access to the subaddress register. A

read/write operation is then performed from/to the target

address, incrementing to the next address until the transaction

is complete.

SUBADDRESS REGISTER (SR7 TO SR0)

The subaddress register is an 8-bit write-only register. After the

MPU port is accessed and a read/write operation is selected, the

subaddress is set up. The subaddress register determines which

register performs the next operation.

Table 17. Register 0x00

SR7 to

Bit Number

Register

Setting

Reset

Value

0x12

SR0

Register

Bit Description

7

6

5

4

3

2

1

0

0x00

Power

mode

Sleep mode. With this control enabled, the current consumption is

reduced to µA level. All DACs and the internal PLL circuit are

disabled. Registers can be read from and written to in sleep mode.

0

Sleep

mode off

Sleep

1

mode on

PLL and oversampling control. This control allows the internal PLL

circuit to be powered down and the oversampling to be switched off.

0

1

PLL on

PLL off

DAC 3: power on/off.

DAC 2: power on/off.

DAC 1: power on/off.

Reserved.

0

1

DAC 3 off

DAC 3 on

DAC 2 off

DAC 2 on

DAC 1 off

DAC 1 on

0

1

0

1

0

Table 18. Register 0x01 to Register 0x09

SR7 to

Bit Number¹

Reset

Value

0x00

SR0

Register

Bit Description

7

6

5

4

3

2

1

0

Register Setting

0x01

Mode

select

Reserved.

0

DDR clock edge alignment

(used only for ED²and HD

DDR modes)

0

Chroma clocked in on rising clock edge and

luma clocked in on falling clock edge.

Reserved.

Luma clocked in on rising clock edge and

chroma clocked in on falling clock edge.

0

1

0

1

Reserved

0

Input mode

(see Subaddress 0x30, Bits[7:3]

for ED/HD standard selection)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

SD input.

ED/HD-SDR input.³

ED/HD-DDR input.

Reserved.

ED (at 54 MHz) input.

Reserved

0

Rev. H | Page 28 of 108

Data Sheet

ADV7390/ADV7391/ADV7392/ADV7393

SR7 to

Bit Number¹

Reset

SR0

Register

Bit Description

7

6

5

4

3

2

1

0

Register Setting

Value

0x02

Mode

Register 0

Reserved

0

Zero must be written to this bit.

Default.

0x20

0

1

HD interlace external VSYNC

and HSYNC

If using HD HSYNC/VSYNCinterlace mode,

setting this bit to 1 is recommended (see the

HD Interlace External HSYNC and VSYNC

Considerations section for more information).

Test pattern black bar⁴

Manual CSC matrix adjust

Sync on RGB

0

1

Disabled.

Enabled.

0

1

Disable manual CSC matrix adjust.

Enable manual CSC matrix adjust.

No sync.

0

1

Sync on all RGB outputs.

RGB component outputs.

YPrPb component outputs.

No sync output.

RGB/YPrPb output select

SD sync output enable

ED/HD sync output enable

0

1

0

1

Output SD syncs on HSYNC and VSYNC pins.

No sync output.

0

1

Output ED/HD syncs on

VSYNC pins.

HSYNC

and

0x03

0x04

ED/HD

CSC

Matrix 0

x

LSBs for GY.

0x03

0xF0

ED/HD

CSC

Matrix 1

LSBs for RV.

LSBs for BU.

LSBs for GV.

LSBs for GU.

Bits[9:2] for GY.

x

0x05

0x06

0x07

0x08

0x09

ED/HD

CSC

Matrix 2

x

0x4E

0x0E

0x24

0x92

0x7C

ED/HD

CSC

Matrix 3

x

Bits[9:2] for GU.

Bits[9:2] for GV.

Bits[9:2] for BU.

Bits[9:2] for RV.

ED/HD

CSC

Matrix 4

ED/HD

CSC

Matrix 5

ED/HD

CSC

Matrix 6

¹x = Logic 0 or Logic 1.

²ED = enhanced definition = 525p and 625p.

³Available on the ADV7392/ADV7393 (40-pin devices) only.

⁴Subaddress 0x31, Bit 2 must also be enabled (ED/HD). Subaddress 0x84, Bit 6 must also be enabled (SD).

Rev. H | Page 29 of 108

ADV7390/ADV7391/ADV7392/ADV7393

Data Sheet

Table 19. Register 0x0B to Register 0x17

SR7 to

Bit Number¹

Reset

SR0

Register

Bit Description

7

0

…

0

6

0

…

0

5

0

…

1

4

0

…

1

3

0

…

1

2

0

…

1

0

1

…

1

0

1

0

…

1

Register Setting

Value

0x0B

DAC 1, DAC 2,

DAC 3 output

levels

Positive gain to DAC output voltage

0%.

0x00

+0.018%.

+0.036%.

…

+7.382%.

+7.5%.

−7.5%.

−7.382%.

−7.364%.

…

0

1

0

Negative gain to DAC output voltage

1

…

1

0

…

1

0

…

1

0

…

1

0

…

1

0

…

1

0

1

…

1

0

1

0

…

1

−0.018%.

0x0D

0x10

0x13

DAC power

mode

DAC 1 low power mode

DAC 2 low power mode

DAC 3 low power mode

0

DAC 1 low power

disabled.

DAC 1 low power enabled.

0x00

0xXX

1

0

1

DAC 2 low power

disabled.

DAC 2 low power enabled.

0

1

DAC 3 low power

disabled.

DAC 3 low power enabled.

SD = 16×, ED = 8×.

SD = 8×, ED = 4×.

SD/ED oversample rate select

Reserved

0

1

0

Cable detection DAC 1 cable detect

0

1

Cable detected on

DAC 1.

DAC 1 unconnected.

Read only

DAC 2 cable detect

0

1

Cable detected on

DAC 2.

Read only

Reserved

DAC 2 unconnected.

0

x

0

x

Unconnected DAC autopower-down

0

1

DAC autopower-down

disable.

DAC autopower-down

enable.

Reserved

0

x

0

x

0

x

Pixel Port

x

Read only.

P[7:0] readback (ADV7390/ADV7391)

Readback A²

P[15:8] readback

(ADV7392/ADV7393)

0x14

0x16

Pixel Port

x

Read only.

0xXX

P[7:0] readback (ADV7392/ADV7393)

Readback B²

Control port

readback²

Reserved

VSYNC readback

HSYNC readback

SFL readback

Reserved

x

0x17

Software reset

Reserved

0

0x00

Software reset

0

1

Writing a 1 resets the

device; this is a self-

clearing bit.

Reserved.

0

¹x = Logic 0 or Logic 1.

²For correct operation, Subaddress 0x01[6:4] must equal the default value of 000.

Rev. H | Page 30 of 108

Data Sheet

ADV7390/ADV7391/ADV7392/ADV7393

Table 20. Register 0x30

SR7 to

Bit Number

Reset

SR0

Register

Bit Description

7

6

5

4

3

2

1

0

Register Setting

Note

Value

0x30

ED/HD Mode

Register 1

ED/HD output standard

0

EIA-770.2 output

EIA-770.3 output

ED

HD

0x00

0

1

0

EIA-770.1 output

Output levels for full

input range

1

Reserved

ED/HD input

synchronization format

0

1

External

,

HSYNC VSYNC

and field inputs¹

Embedded EAV/SAV

codes

ED/HD standard²

0

1

0

1

0

1

0

1

SMPTE 293M, ITU-BT.1358 525p at 59.94 Hz

BTA-1004, ITU-BT.1362

ITU-BT.1358

ITU-BT.1362

525p at 59.94 Hz

625p at 50 Hz

SMPTE 296M-1,

SMPTE 274M-2

720p at

60 Hz/59.94 Hz

0

1

0

1

SMPTE 296M-3

SMPTE 296M-4,

SMPTE 274M-5

720p at 50 Hz

720p at

30 Hz/29.97 Hz

0

1

0

1

SMPTE 296M-6

SMPTE 296M-7,

SMPTE 296M-8

720p at 25 Hz

720p at

24 Hz/23.98 Hz

0

1

0

1

0

SMPTE 240M

1035i at

60 Hz/59.94 Hz

0

1

0

1

0

1

0

1

Reserved

SMPTE 274M-4,

SMPTE 274M-5

1080i at

30 Hz/29.97 Hz

0

1

0

1

SMPTE 274M-6

SMPTE 274M-7,

SMPTE 274M-8

1080i at 25 Hz

1080p at

30 Hz/29.97 Hz

1

0

1

SMPTE 274M-9

SMPTE 274M-10,

SMPTE 274M-11

1080p at 25 Hz

1080p at

24 Hz/23.98 Hz

1

0

1

0

ITU-R BT.709-5

Reserved

1080Psf at 24 Hz

10011 to 11111

¹Synchronization can be controlled with a combination of either

and

inputs or

and field inputs, depending on Subaddress 0x34, Bit 6.

HSYNC

VSYNC

2

HSYNC

VSYNC

Considerations section for more information.

See the HD Interlace External

and

Rev. H | Page 31 of 108

ADV7390/ADV7391/ADV7392/ADV7393

Data Sheet

Table 21. Register 0x31 to Register 0x33

SR7 to

Bit Number

Reset

Value

0x00

SR0

Register

Bit Description

7

6

5

4

3

2

1

0

1

Register Setting

Pixel data valid off.

Pixel data valid on.

4×.

0x31

ED/HD Mode

Register 2

ED/HD pixel data valid

HD oversample rate select

ED/HD test pattern enable

ED/HD test pattern hatch/field

0

1

2×.

0

1

HD test pattern off.

HD test pattern on.

Hatch.

0

1

Field/frame.

ED/HD vertical blanking interval (VBI)

open

0

1

Disabled.

Enabled.

ED/HD undershoot limiter

0

1

0

1

0

1

Disabled.

−11 IRE.

−6 IRE.

−1.5 IRE.

ED/HD sharpness filter

0

1

Disabled.

Enabled.

0x32

ED/HD Mode

Register 3

ED/HD Y delay with respect to the

0

1

0

1

0

1

0

1

0

0 clock cycles.

One clock cycle.

Two clock cycles.

Three clock cycles.

Four clock cycles.

0 clock cycles.

One clock cycle.

Two clock cycles.

Three clock cycles.

Four clock cycles.

Disabled.

0x00

falling edge of

HSYNC

ED/HD color delay with respect to the

falling edge of HSYNC

0

1

0

1

0

1

0

1

0

ED/HD CGMS enable

0

1

Enabled.

ED/HD CGMS CRC enable

ED/HD Cr/Cb sequence

0

1

Disabled.

Enabled.

0x33

ED/HD Mode

Register 4

0

1

0x68

Cb after falling edge of HSYNC.

Cr after falling edge of HSYNC.

0 must be written to this bit.

8-bit input.

Reserved

0

ED/HD input format

0

1

10-bit input¹.

Sinc compensation filter on DAC 1, DAC

2, DAC 3

0

1

Disabled.

Enabled.

Reserved

0

0 must be written to this bit.

Disabled.

Enabled.

ED/HD chroma SSAF filter

0

1

Reserved

1

1 must be written to this bit.

Disabled.

Enabled.

ED/HD double buffering

0

1

¹Available on the ADV7392/ADV7393 (40-pin devices) only.

Rev. H | Page 32 of 108

Data Sheet

ADV7390/ADV7391/ADV7392/ADV7393

Table 22. Register 0x34 to Register 0x38

SR7 to

Bit Number¹

Reset

SR0

Register

Bit Description

7

6

5

4

3

2

1

0

1

Register Setting

Value

0x34

ED/HD Mode

Register 5

ED/HD timing reset

Internal ED/HD timing counters enabled.

Resets the internal ED/HD timing counters.

HSYNC output control (see Table 55).

0x48

ED/HD HSYNC control²

ED/HD VSYNC control²

0

1

0

1

VSYNC output control (see Table 56).

Reserved

1

ED Macrovision® enable³

0

1

ED Macrovision disabled.

ED Macrovision enabled.

0 must be written to this bit.

Reserved

0

1

0 = Field input.

ED/HD VSYNC input/field

input

1 = VSYNC input.

ED/HD horizontal/vertical

counter mode⁴

0

1

Update field/line counter.

Field/line counter free running.

0x35

ED/HD Mode

Register 6

Reserved

0

0x00

Reserved

0

ED/HD sync on PrPb

0

1

Disabled.

Enabled.

ED/HD color DAC swap

0

1

DAC 2 = Pb, DAC 3 = Pr

DAC 2 = Pr, DAC 3 = Pb.

Gamma Correction Curve A.

Gamma Correction Curve B.

Disabled.

ED/HD gamma correction

curve select

0

1

ED/HD gamma correction

enable

0

1

Enabled.

ED/HD adaptive filter

mode

0

1

Mode A.

Mode B.

ED/HD adaptive filter

enable

0

1

x

Disabled.

Enabled.

0x36

0x37

0x38

ED/HD Y level⁵

ED/HD Cr level⁵

ED/HD Cb level⁵

ED/HD Test Pattern Y level

ED/HD Test Pattern Cr level

ED/HD Test Pattern Cb level

x

Y level value.

Cr level value.

Cb level value.

0xA0

0x80

¹x = Logic 0 or Logic 1.

²Used in conjunction with ED/HD sync output enable in Subaddress 0x02, Bit 7 = 1.

³Applies to the ADV7390 and ADV7392 only.

⁴When set to 0, the horizontal/vertical counters automatically wrap around at the end of the line/field/frame of the selected standard. When set to 1, the

horizontal/vertical counters are free running and wrap around when external sync signals indicate to do so.

⁵For use with ED/HD internal test patterns only (Subaddress 0x31, Bit 2 = 1).

Rev. H | Page 33 of 108

ADV7390/ADV7391/ADV7392/ADV7393

Data Sheet

Table 23. Register 0x39 to Register 0x43

SR7 to

Bit Number

Reset

Register Setting Value

0x00

SR0

Register

Bit Description

7

6

5

4

3

2

1

0

0x39

ED/HD Mode

Register 7

Reserved

0

ED/HD EIA/CEA-861B

synchronization compliance

0

1

Disabled

Enabled

Reserved

0

0X3A

ED/HD Mode

Register 8

INV_PHSYNC_POL

0

1

Disabled

Enabled

Disabled

Enabled

Disabled

Enabled

0x00

INV_PVSYNC_POL

INV_PBLANK_POL

0

1

0

1

Reserved

0

0x40

ED/HD

sharpness filter Value A

gain

ED/HD sharpness filter gain

0

…

0

1

0

…

1

0

…

1

0

1

…

1

0

Gain A = 0

Gain A = +1

…

Gain A = +7

Gain A = −8

…

Gain A = −1

Gain B = 0

Gain B = +1

…

Gain B = +7

Gain B = −8

…

1

…

1

…

1

ED/HD sharpness filter gain

Value B

0

…

0

1

0

…

1

0

…

1

0

1

…

1

0

…

1

…

1

…

1

…

1

Gain B = −1

0x41

0x42

0x43

ED/HD CGMS

Data 0

ED/HD CGMS data bits

0

C19

C11

C3

C18

C10

C2

C17

C9

C16

C8

CGMS C19 to C1

6

0x00

ED/HD CGMS

Data 1

C15

C7

C14

C6

C13

C5

C12

C4

CGMS C15 to C8

ED/HD CGMS

Data 2

C1

C0

CGMS C7 to C0

Rev. H | Page 34 of 108

Data Sheet

ADV7390/ADV7391/ADV7392/ADV7393

Table 24. Register 0x44 to Register 0x57

SR7 to

Bit Number¹

Register

Setting

A0

Reset

Value

0x00

SR0

Register

Bit Description

7

x

6

x

5

x

4

x

3

x

2

x

1

x

0

x

0x44

0x45

0x46

0x47

0x48

0x49

0x4A

0x4B

0x4C

0x4D

0x4E

0x4F

0x50

0x51

0x52

0x53

0x54

0x55

0x56

0x57

ED/HD Gamma A0

ED/HD Gamma A1

ED/HD Gamma A2

ED/HD Gamma A3

ED/HD Gamma A4

ED/HD Gamma A5

ED/HD Gamma A6

ED/HD Gamma A7

ED/HD Gamma A8

ED/HD Gamma A9

ED/HD Gamma Curve A (Point 24)

ED/HD Gamma Curve A (Point 32)

ED/HD Gamma Curve A (Point 48)

ED/HD Gamma Curve A (Point 64)

ED/HD Gamma Curve A (Point 80)

ED/HD Gamma Curve A (Point 96)

ED/HD Gamma Curve A (Point 128)

ED/HD Gamma Curve A (Point 160)

ED/HD Gamma Curve A (Point 192)

ED/HD Gamma Curve A (Point 224)

A1

A2

A3

A4

A5

A6

A7

A8

A9

ED/HD Gamma B0 ED/HD Gamma Curve B (Point 24)

ED/HD Gamma B1 ED/HD Gamma Curve B (Point 32)

ED/HD Gamma B2 ED/HD Gamma Curve B (Point 48)

ED/HD Gamma B3 ED/HD Gamma Curve B (Point 64)

ED/HD Gamma B4 ED/HD Gamma Curve B (Point 80)

ED/HD Gamma B5 ED/HD Gamma Curve B (Point 96)

ED/HD Gamma B6 ED/HD Gamma Curve B (Point 128)

ED/HD Gamma B7 ED/HD Gamma Curve B (Point 160)

ED/HD Gamma B8 ED/HD Gamma Curve B (Point 192)

ED/HD Gamma B9 ED/HD Gamma Curve B (Point 224)

B0

B1

B2

B3

B4

B5

B6

B7

B8

B9

¹x = Logic 0 or Logic 1.

Rev. H | Page 35 of 108

ADV7390/ADV7391/ADV7392/ADV7393

Data Sheet

Table 25. Register 0x58 to Register 0x5D

SR7 to

Bit Number¹

Register

Setting

Gain A = 0

Gain A = +1

…

Gain A = +7

Gain A = −8

…

Gain A = −1

Gain B = 0

Gain B = +1

…

Gain B = +7

Gain B = −8

…

Gain B = −1

Gain A = 0

Gain A = +1

…

Gain A = +7

Gain A = −8

…

Gain A = −1

Gain B = 0

Gain B = +1

…

Gain B = +7

Gain B = −8

…

Gain B = −1

Gain A = 0

Gain A = +1

…

Gain A = +7

Gain A = −8

…

Gain A = −1

Gain B = 0

Gain B = +1

…

Gain B = +7

Gain B = −8

…

Reset

Value

0x00

SR0

Register

Bit Description

7

6

5

4

3

2

1

0

0x58

ED/HD Adaptive Filter Gain 1

ED/HD Adaptive Filter Gain 1,

Value A

0

…

0

1

0

…

1

0

…

1

0

1

…

1

0

…

1

…

1

…

1

…

1

ED/HD Adaptive Filter Gain 1,

Value B

0

…

0

1

0

…

1

0

…

1

0

1

…

1

0

…

1

…

1

…

1

…

1

0x59

ED/HD Adaptive Filter Gain 2

ED/HD Adaptive Filter Gain 2,

Value A

0

…

0

1

0

…

1

0

…

1

0

1

…

1

0

0x00

…

1

…

1

…

1

…

1

ED/HD Adaptive Filter Gain 2,

Value B

0

…

0

1

0

…

1

0

…

1

0

1

…

1

0

…

1

…

1

…

1

…

1

0x5A

ED/HD Adaptive Filter Gain 3

ED/HD Adaptive Filter Gain 3,

Value A

0

…

0

1

0

…

1

0

…

1

0

1

…

1

0

0x00

…

1

…

1

…

1

…

1

ED/HD Adaptive Filter Gain 3,

Value B

0

…

0

1

0

…

1

0

…

1

0

1

…

1

0

…

1

…

1

…

1

…

1

Gain B = −1

0x5B

0x5C

0x5D

ED/HD Adaptive Filter

Threshold A

ED/HD Adaptive Filter Threshold A

ED/HD Adaptive Filter Threshold B

ED/HD Adaptive Filter Threshold C

x

Threshold A 0x00

Threshold B 0x00

Threshold C 0x00

ED/HD Adaptive Filter

Threshold B

x

ED/HD Adaptive Filter

Threshold C

¹x = Logic 0 or Logic 1.

Rev. H | Page 36 of 108

Data Sheet

ADV7390/ADV7391/ADV7392/ADV7393

Table 26. Register 0x5E to Register 0x6E

SR7 to

Bit Number

Register

Setting

Disabled

Enabled

Disabled

Enabled

H5 to H0

Reset

Value

0x00

SR0

Register

Bit Description

7

6

5

4

3

2

1

0

1

0x5E

ED/HD CGMS Type B

Register 0

ED/HD CGMS Type B

enable

ED/HD CGMS Type B

CRC enable

0

1

ED/HD CGMS Type B

header bits

H5

H4

H3

H2

H1

H0

0x5F

0x60

0x61

0x62

0x63

0x64

0x65

0x66

0x67

0x68

0x69

0x6A

0x6B

0x6C

0x6D

0x6E

ED/HD CGMS Type B

Register 1

ED/HD CGMS Type B

data bits

P7

P6

P5

P4

P3

P2

P1

P0

P7 to P0

0x00

ED/HD CGMS Type B

Register 2

ED/HD CGMS Type B

data bits

P15

P23

P31

P39

P47

P55

P63

P71

P79

P87

P95

P14

P22

P30

P38

P46

P54

P62

P70

P78

P86

P94

P13

P21

P29

P37

P45

P53

P61

P69

P77

P85

P93

P12

P20

P28

P36

P44

P52

P60

P68

P76

P84

P92

P11

P19

P27

P35

P43

P51

P59

P67

P75

P83

P91

P10

P18

P26

P34

P42

P50

P58

P66

P74

P82

P90

P98

P9

P8

P15 to P8

ED/HD CGMS Type B

Register 3

ED/HD CGMS Type B

data bits

P17

P25

P33

P41

P49

P57

P65

P73

P81

P89

P97

P16

P24

P32

P40

P48

P56

P64

P72

P80

P88

P96

P23 to P16

P31 to P24

P39 to P32

P47 to P40

P55 to P48

P63 to P56

P71 to P64

P79 to P72

P87 to P80

P95 to P88

P103 to P96

ED/HD CGMS Type B

Register 4

ED/HD CGMS Type B

data bits

ED/HD CGMS Type B

Register 5

ED/HD CGMS Type B

data bits

ED/HD CGMS Type B

Register 6

ED/HD CGMS Type B

data bits

ED/HD CGMS Type B

Register 7

ED/HD CGMS Type B

data bits

ED/HD CGMS Type B

Register 8

ED/HD CGMS Type B

data dits

ED/HD CGMS Type B

Register 9

ED/HD CGMS Type B

data bits

ED/HD CGMS Type B

Register 10

ED/HD CGMS Type B

data bits

ED/HD CGMS Type B

Register 11

ED/HD CGMS Type B

data bits

ED/HD CGMS Type B

Register 12

ED/HD CGMS Type B

data bits

ED/HD CGMS Type B

Register 13

ED/HD CGMS Type B

data bits

P103 P102 P101 P100 P99

ED/HD CGMS Type B

Register 14

ED/HD CGMS Type B

data bits

P111 P110 P109 P108 P107 P106 P105 P104 P111 to P104 0x00

P119 P118 P117 P116 P115 P114 P113 P112 P119 to P112 0x00

P127 P126 P125 P124 P123 P122 P121 P120 P127 to P120 0x00

ED/HD CGMS Type B

Register 15

ED/HD CGMS Type B

data bits

ED/HD CGMS Type B

Register 16

ED/HD CGMS Type B

data bits

Rev. H | Page 37 of 108

ADV7390/ADV7391/ADV7392/ADV7393

Data Sheet

Table 27. Register 0x80 to Register 0x83

SR7 to

Bit Number

Reset

Value

0x10

SR0

Register

Bit Description

7

6

5

4

3

2

1

0

1

0

1

0

1

Register Setting

NTSC

PAL B, PAL D, PAL G, PAL H, PAL I

PAL M

0x80

SD Mode

Register 1

SD standard

PAL N

SD luma filter

0

1

0

1

0

1

0

1

0

1

0

1

0

1

LPF NTSC

LPF PAL

Notch NTSC

Notch PAL

Luma SSAF

Luma CIF

Luma QCIF

Reserved

SD chroma filter

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1.3 MHz

0.65 MHz

1.0 MHz

2.0 MHz

Reserved

Chroma CIF

Chroma QCIF

3.0 MHz

0x82

SD Mode

Register 2

SD PrPb SSAF filter

SD DAC Output 1

0

1

Disabled

Enabled

0x0B

0

1

See Table 37

Reserved

0

SD pedestal

0

1

Disabled

Enabled

SD square pixel mode

SD VCR FF/RW sync

SD pixel data valid

0

1

Disabled

Enabled

0

1

Disabled

Enabled

0

1

Disabled

Enabled

SD active video edge

control

0

1

Disabled

Enabled

0x83

SD Mode

Register 3

SD pedestal YPrPb output

0

1

No pedestal on YPrPb

7.5 IRE pedestal on YPrPb

Y = 700 mV/300 mV

Y = 714 mV/286 mV

0x04

SD Output Levels Y

0

1

SD Output Levels PrPb

0

1

0

1

0

1

700 mV p-p (PAL), 1000 mV p-p (NTSC)

700 mV p-p

1000 mV p-p

648 mV p-p

SD vertical blanking

interval (VBI) open

0

1

Disabled

Enabled

SD closed captioning field

control

0

1

0

1

0

1

Closed captioning disabled

Closed captioning on odd field only

Closed captioning on even field only

Closed captioning on both fields

Reserved

0

Rev. H | Page 38 of 108

Data Sheet

ADV7390/ADV7391/ADV7392/ADV7393

Table 28. Register 0x84 to Register 0x87

SR7 to

Bit Number

Reset

Value

0x00

SR0

Register

Bit Description

7

6

5

4

3

2

1

0

Register Setting

0x84

SD Mode

Register 4

Reserved

0

SD SFL/SCR/TR mode select

0

1

0

1

Disabled.

SFL mode enabled.

720 pixels.

710 (NTSC), 702 (PAL).

Chroma enabled.

Chroma disabled.

Enabled.

SD active video length

SD chroma

0

1

0

1

SD burst

0

1

Disabled.

SD color bars

0

1

Disabled.

Enabled.

SD luma/chroma swap

0

1

DAC 2 = luma, DAC 3 = chroma.

DAC 2 = chroma, DAC 3 = luma.

5.17 μs.

5.31 μs.

5.59 μs (must be set for

0x86

SD Mode

Register 5

NTSC color subcarrier adjust (delay from

the falling edge of output

the start of color burst)

0

1

0

1

0

0x02

HSYNC

pulse to

Macrovision compliance).

1

Reserved.

Reserved

0

SD EIA/CEA-861B synchronization

compliance

0

1

Disabled.

Enabled.

Reserved

0

SD horizontal/vertical counter mode¹

0

1

Update field/line counter.

Field/line counter free running.

Normal.

Color reversal enabled.

Disabled.

SD RGB color swap²

0

1

0x87

SD Mode

Register 6

SD luma and color scale control

SD luma scale saturation

SD hue adjust

0

1

0x00

Enabled.

0

1

Disabled.

Enabled.

0

1

Disabled.

Enabled.

SD brightness

0

1

Disabled.

Enabled.

SD luma SSAF gain

0

1

Disabled.

Enabled.

SD input standard autodetection

0

1

Disabled.

Enabled.

Reserved

SD RGB input enable²

0

0 must be written to this bit.

SD YCrCb input.

SD RGB input.

0

1

¹When set to 0, the horizontal/vertical counters automatically wrap around at the end of the line/field/frame of the selected standard. When set to 1, the

horizontal/vertical counters are free running and wrap around when external sync signals indicate to do so.

²Available on the ADV7392/ADV7393 (40-pin devices) only.

Rev. H | Page 39 of 108

ADV7390/ADV7391/ADV7392/ADV7393

Data Sheet

Table 29. Register 0x88 to Register 0x89

SR7 to

Bit Number

Reset

Value

0x00

SR0

Register

Bit Description

Reserved

7

6

5

4

3

2

1

0

Register Setting

0x88

SD Mode Register 7

0

SD noninterlaced mode

0

1

Disabled.

Enabled.

SD double buffering

SD input format

0

1

Disabled.

Enabled.

0

1

0

1

0

8-bit YCbCr input.

16-bit YCbCr input.¹

10-bit YCbCr/16-bit SD RGB

input.¹

1

Reserved.

SD digital noise reduction

SD gamma correction enable

SD gamma correction curve select

SD undershoot limiter

0

1

Disabled.

Enabled.

0

1

Disabled.

Enabled.

0

1

Gamma Correction Curve A.

Gamma Correction Curve B.

Disabled.

−11 IRE.

−6 IRE.

0x89

SD Mode Register 8

0

1

0

1

0

1

0x00

−1.5 IRE.

Reserved

0

0 must be written to this bit.

Reserved.

Reserved

0

SD chroma delay

0

1

0

1

0

1

Disabled.

4 clock cycles.

8 clock cycles.

Reserved.

Reserved

0

0 must be written to these bits.

¹Available on the ADV7392/ADV7393 (40-pin devices) only.

Table 30. Register 0x8A to Register 0x98

SR7 to

Bit Number¹

Reset

Value

0x08

SR0

Register

Bit Description

7

6

5

4

3

2

1

0

1

Register Setting

Slave mode.

Master mode.

Mode 0.

Mode 1.

Mode 2.

0x8A

SD Timing Register 0

SD slave/master mode

SD timing mode

0

1

0

1

0

1

Mode 3.

Reserved

1

SD luma delay

0

1

0

1

0

1

No delay.

Two clock cycles.

Four clock cycles.

Six clock cycles.

−40 IRE.

SD minimum luma value

SD timing reset

0

1

−7.5 IRE.

A low-high-low transition

resets the internal SD

timing counters.

x

Rev. H | Page 40 of 108

Data Sheet

ADV7390/ADV7391/ADV7392/ADV7393

SR7 to

Bit Number¹

Reset

Value

0x00

SR0

Register

Bit Description

7

6

5

4

3

2

1

0

1

0

1

0

1

Register Setting

t_a= one clock cycle.

t_a= four clock cycles.

t_a= 16 clock cycles.

t_a= 128 clock cycles.

t_b= 0 clock cycles.

t_b= four clock cycles.

t_b= eight clock cycles.

t_b= 18 clock cycles.

t_c= t_b.

0x8B

SD Timing Register 1

Note: Applicable in

master modes only,

that is, Subaddress

0x8A, Bit 0 = 1.

SD HSYNC width

0

1

0

1

0

1

SD HSYNC to VSYNC delay

X²

0

1

0

1

0

1

0

1

SD HSYNC to VSYNC rising

edge delay (Mode 1 only)

t_c= t_b+ 32 µs.

One clock cycle.

Four clock cycles.

16 clock cycles.

128 clock cycles.

0 clock cycles.

One clock cycle.

Two clock cycles.

Three clock cycles.

SD VSYNC width (Mode 2 only)

1

0

1

x

0

1

0

1

x

SD HSYNC to pixel data adjust

0x8C

0x8D

0x8E

0x8F

SD F_SCRegister 0³

SD F_SCRegister 1³

SD F_SCRegister 2³

SD F_SCRegister 3³

SD F_SCPhase

Subcarrier Frequency Bits[7:0]

Subcarrier Frequency Bits[15:8]

Subcarrier Frequency Bits[23:16]

Subcarrier Frequency Bits[31:24]

Subcarrier Phase Bits[9:2]

x

Subcarrier Frequency

Bits[7:0].

0x1F

0x7C

0xF0

0x21

x

Subcarrier Frequency

Bits[15:8].

Subcarrier Frequency

Bits[23:16].

Subcarrier Frequency

Bits[31:24].

0x90

0x91

0x92

0x93

0x94

0x95

0x96

0x97

0x98

x

Subcarrier Phase Bits[9:2]. 0x00

Extended Data Bits[7:0]. 0x00

Extended Data Bits[15:8]. 0x00

SD Closed Captioning Extended data on even fields

SD Closed Captioning Data on odd fields

Data Bits[7:0].

Data Bits[15:8].

0x00

SD Closed Captioning Data on odd fields

SD Pedestal Register 0

SD Pedestal Register 1

SD Pedestal Register 2

SD Pedestal Register 3

Pedestal on odd fields

Pedestal on even fields

17 16 15 14 13 12 11 10 Setting any of these bits 0x00

to 1 disables the

25 24 23 22 21 20 19 18

17 16 15 14 13 12 11 10

25 24 23 22 21 20 19 18

0x00

pedestal on the line

number indicated by

the bit settings.

¹x = Logic 0 or Logic 1.

²X = don’t care.

³SD subcarrier frequency registers default to NTSC subcarrier frequency values.

Rev. H | Page 41 of 108

ADV7390/ADV7391/ADV7392/ADV7393

Data Sheet

Table 31. Register 0x99 to Register 0xA5

SR7 to

Bit Number¹

Reset

Value

SR0

Register

Bit Description

SD CGMS data

SD CGMS CRC

7

6

5

4

3

2

1

0

Register Setting

0x99

SD CGMS/WSS 0

x

CGMS Data Bits[C19:C16]

Disabled

Enabled

0x00

0

1

SD CGMS on odd fields

SD CGMS on even fields

SD WSS

0

1

Disabled

Enabled

0

1

Disabled

Enabled

0

1

Disabled

Enabled

0x9A

SD CGMS/WSS 1

SD CGMS/WSS data

x

CGMS Data Bits[C13:C8] or

WSS Data Bits[W13:W8]

0x00

SD CGMS data

x

CGMS Data Bits[C15:C14]

0x9B

0x9C

SD CGMS/WSS 2

SD scale LSB

SD CGMS/WSS data

x

CGMS Data Bits[C7:C0] or

WSS Data Bits[W7:W0]

0x00

LSBs for SD Y scale value

LSBs for SD Cb scale value

LSBs for SD Cr scale value

LSBs for SD F_SCphase

SD Y scale value

SD Y Scale Bits[1:0]

SD Cb Scale Bits[1:0]

SD Cr Scale Bits[1:0]

Subcarrier Phase Bits[1:0]

SD Y Scale Bits[9:2]

SD Cb Scale Bits[9:2]

SD Cr Scale Bits[9:2]

SD Hue Adjust Bits[7:0]

SD Brightness Bits[6:0]

Disabled

x

0x9D

0x9E

0x9F

0xA0

0xA1

SD Y scale

x

0x00

SD Cb scale

SD Cr scale

SD hue adjust

SD Cb scale value

SD Cr scale value

SD hue adjust value

SD brightness/WSS SD brightness value

SD blank WSS data

0

1

Enabled

0xA2

SD luma SSAF

SD luma SSAF gain/attenuation

(only applicable if Subaddress

0x87, Bit 4 = 1)

0

…

0

…

1

0

…

1

0

…

0

−4 dB

…

0 dB

0x00

…

1

…

1

…

0

…

0

…

+4 dB

Reserved

0

0xA3

SD DNR 0

Coring gain border (in DNR

mode, the values in brackets

apply)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

No gain

0x00

+1/16 [−1/8]

+2/16 [−2/8]

+3/16 [−3/8]

+4/16 [−4/8]

+5/16 [−5/8]

+6/16 [−6/8]

+7/16 [−7/8]

+8/16 [−1]

Coring gain data (in DNR

mode, the values in brackets

apply)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

No gain

+1/16 [−1/8]

+2/16 [−2/8]

+3/16 [−3/8]

+4/16 [−4/8]

+5/16 [−5/8]

+6/16 [−6/8]

+7/16 [−7/8]

+8/16 [−1]

Rev. H | Page 42 of 108

Data Sheet

ADV7390/ADV7391/ADV7392/ADV7393

SR7 to

Bit Number¹

Reset

Value

0x00

SR0

Register

Bit Description

7

6

5

0

4

0

3

0

2

0

1

0

Register Setting

0

0xA4

SD DNR 1

DNR threshold

0

1

…

1

…

1

…

1

…

1

…

1

…

0

…

62

1

63

Border area

Block size

0

1

Two pixels

Four pixels

Eight pixels

16 pixels

Filter A

Filter B

Filter C

Filter D

0

1

0xA5

SD DNR 2

DNR input select

0

1

0

1

0

1

0

1

0

0x00

DNR mode

0

1

DNR mode

DNR sharpness mode

0 pixel offset

One pixel offset

…

DNR block offset

0

…

1

0

…

1

0

…

1

0

1

…

0

1

14 pixel offset

15 pixel offset

¹x = Logic 0 or Logic 1.

Table 32. Register 0xA6 to Register 0xBB

SR7 to

Bit Number¹

Reset

Value

0x00

0xXX

SR0

Register

Bit Description

7

x

6

5

4

x

3

x

2

1

x

0

x

Register Setting

0xA6

0xA7

0xA8

0xA9

0xAA

0xAB

0xAC

0xAD

0xAE

0xAF

0xB0

0xB1

0xB2

0xB3

0xB4

0xB5

0xB6

0xB7

0xB8

0xB9

0xBA

SD Gamma A0

SD Gamma A1

SD Gamma A2

SD Gamma A3

SD Gamma A4

SD Gamma A5

SD Gamma A6

SD Gamma A7

SD Gamma A8

SD Gamma A9

SD Gamma B0

SD Gamma B1

SD Gamma B2

SD Gamma B3

SD Gamma B4

SD Gamma B5

SD Gamma B6

SD Gamma B7

SD Gamma B8

SD Gamma B9

SD brightness detect

SD Gamma Curve A (Point 24)

SD Gamma Curve A (Point 32)

SD Gamma Curve A (Point 48)

SD Gamma Curve A (Point 64)

SD Gamma Curve A (Point 80)

SD Gamma Curve A (Point 96)

x

A0

A1

A2

A3

A4

A5

A6

A7

A8

A9

B0

SD Gamma Curve A (Point 128)

SD Gamma Curve A (Point 160)

SD Gamma Curve A (Point 192)

SD Gamma Curve A (Point 224)

SD Gamma Curve B (Point 24)

SD Gamma Curve B (Point 32)

SD Gamma Curve B (Point 48)

SD Gamma Curve B (Point 64)

SD Gamma Curve B (Point 80)

SD Gamma Curve B (Point 96)

SD Gamma Curve B (Point 128)

SD Gamma Curve B (Point 160)

SD Gamma Curve B (Point 192)

SD Gamma Curve B (Point 224)

SD brightness value

B1

B2

B3

B4

B5

B6

B7

B8

B9

Read only

Rev. H | Page 43 of 108

ADV7390/ADV7391/ADV7392/ADV7393

Data Sheet

SR7 to

Bit Number¹

Reset

SR0

Register

Bit Description

Field count

7

6

5

4

3

2

1

0

Register Setting

Value

0xBB

Field count

x

Read only

Reserved

0x0X

Reserved

0

Encoder version code

0

1

Read only; first

encoder version²

Read only; second

encoder version

¹x = Logic 0 or Logic 1.

2

HSYNC

VSYNC

Considerations section for information about the first encoder version.

See the HD Interlace External

and

Table 33. Register 0xC9 to Register 0xCE

SR7 to

Bit Number

Reset

SR0

Register

Bit Description

7

6

5

4

3

2

1

0

1

Register Setting

Disabled.

Enabled.

Value

0xC9

Teletext control

Teletext enable

0x00

Teletext request mode

0

1

Line request signal.

Bit request signal.

VSYNC.

Teletext input pin

select¹

0

1

P0.

Reserved

0

Reserved.

0xCA

Teletext request

control

Teletext request falling

edge position control

0

1

0 clock cycles.

One clock cycle.

…

0x00

…

1

…

1

…

1

…

0

14 clock cycles.

15 clock cycles.

0 clock cycles.

One clock cycle.

…

1

Teletext request rising

edge position control

0

1

…

1

…

1

…

1

…

0

14 clock cycles.

15 clock cycles.

1

0xCB

0xCC

0xCD

0xCE

TTX Line Enable 0 Teletext on odd fields

TTX Line Enable 1 Teletext on odd fields

TTX Line Enable 2 Teletext on even fields

TTX Line Enable 3 Teletext on even fields

22 21 20 19 18 17 16 15

14 13 12 11 10

22 21 20 19 18 17 16 15

14 13 12 11 10

Setting any of these bits

to 1 enables teletext on

the line number indicated

by the bit settings.

0x00

9

8

7

9

8

7

¹The use of P0 as the teletext input pin is available on the ADV7392/ADV7393 (40-pin devices) only.

Rev. H | Page 44 of 108

Data Sheet

ADV7390/ADV7391/ADV7392/ADV7393

Table 34. Register 0xE0 to Register 0xF1

SR7 to

Bit Number¹

Reset

Value

0x00

SR0

Register²

Bit Description

MV control bits

7

x

0

6

x

0

5

x

0

4

x

0

3

x

0

2

x

0

1

x

0

x

Register Setting

0xE0

0xE1

0xE2

0xE3

0xE4

0xE5

0xE6

0xE7

0xE8

0xE9

0xEA

0xEB

0xEC

0xED

0xEE

0xEF

0xF0

0xF1

Macrovision

Bits[7:1] must be 0.

¹x = Logic 0 or Logic 1.

²Macrovision registers are available on the ADV7390 and the ADV7392 only.

Rev. H | Page 45 of 108

ADV7390/ADV7391/ADV7392/ADV7393

Data Sheet

ADV7390/ADV7391 INPUT CONFIGURATION

The ADV7390/ADV7391 support a number of different input

modes. The desired input mode is selected using Subaddress 0x01,

Bits[6:4]. The ADV7390/ADV7391 default to standard definition

(SD) mode on power-up. Table 35 provides an overview of all

possible input configurations. Each input mode is described in

detail in this section. Note that the WLCSP option is only

configured to support SD as shown in Figure 51.

The CrCb pixel data is also input on Pin P7 to Pin P0 on the

opposite edge of CLKIN. Pin P0 is the LSB.

Whether the Y data is clocked in on the rising or falling edge of

CLKIN is determined by Subaddress 0x01, Bits[2:1] (see Figure 52

and Figure 53).

CLKIN

Table 35. ADV7390/ADV7391 Input Configuration

P[7:0]

3FF

00

XY

Cb0

Y0

Cr0

Y1

Input Mode

P7 P6 P5 P4 P3 P2 P1 P0

000 SD

010 ED/HD-DDR

111 ED (at 54 MHz)

YCrCb

NOTES

1. SUBADDRESS 0x01 [2:1] SHOULD BE SET TO 00 IN THIS CASE.

Figure 52. ED/HD-DDR Input Sequence (EAV/SAV)—Option A

STANDARD DEFINITION

CLKIN

Subaddress 0x01, Bits[6:4] = 000

P[7:0]

3FF

00

XY

Y0

Cb0

Y1

Cr0

SD YCrCb data can be input in an interleaved 4:2:2 format over

an 8-bit bus rate of 27 MHz. A 27 MHz clock signal must be

provided on the CLKIN pin. If required, external synchroni-

NOTES

1. SUBADDRESS 0x01 [2:1] SHOULD BE SET TO 11 IN THIS CASE.

HSYNC

VSYNC

zation signals can be provided on the

and

pins.

Figure 53. ED/HD-DDR Input Sequence (EAV/SAV)—Option B

Embedded EAV/SAV timing codes are also supported. The

ITU-R BT.601/656 input standard is supported. The interleaved

pixel data is input on Pin P7 to Pin P0, with Pin P0 being the LSB.

MPEG2

DECODER

ADV7390/

ADV7391

CLKIN

YCrCb

ADV7390/

ADV7391

2

8

VSYNC,

YCrCb

P[7:0]

MPEG2

HSYNC

INTERLACED TO

PROGRESSIVE

DECODER

27MHz

CLKIN

2

VSYNC,

HSYNC

8

YCrCb

P[7:0]

Figure 54. ED/HD-DDR Example Application

Figure 51. SD Example Application

ENHANCED DEFINITION (AT 54 MHz)

Subaddress 0x01, Bits[6:4] = 111

ENHANCED DEFINITION/HIGH DEFINITION

Subaddress 0x01, Bits[6:4] = 010

ED YCrCb data can be input in an interleaved 4:2:2 format over

an 8-bit bus rate of 54 MHz.

Enhanced definition (ED) or high definition (HD) YCrCb data

can be input in an interleaved 4:2:2 format over an 8-bit DDR

bus. The clock signal must be provided on the CLKIN pin. If

required, external synchronization signals can be provided on

A 54 MHz clock signal must be provided on the CLKIN pin.

Embedded EAV/SAV timing codes are supported. External

synchronization signals are not supported in this mode.

HSYNC

VSYNC

the

and

pins. Embedded EAV/SAV timing

The interleaved pixel data is input on Pin P7 to Pin P0, with Pin P0

being the LSB.

codes are also supported.

8-Bit 4:2:2 ED/HD YCrCb Mode (DDR)

CLKIN

In 8-bit DDR 4:2:2 YCrCb input mode, the Y pixel data is input

on Pin P7 to Pin P0 on either the rising or falling edge of CLKIN.

Pin P0 is the LSB.

P[7:0]

3FF

00

XY

Cb0

Y0

Cr0

Y1

Figure 55. ED (at 54 MHz) Input Sequence (EAV/SAV)

Rev. H | Page 46 of 108

Data Sheet

ADV7390/ADV7391/ADV7392/ADV7393

ADV7392/ADV7393 INPUT CONFIGURATION

The ADV7392/ADV7393 support a number of different input

modes. The desired input mode is selected using Subaddress 0x01,

Bits[6:4]. The ADV7392/ADV7393 default to standard definition

(SD) mode on power-up. Table 36 provides an overview of all

possible input configurations. Each input mode is described in

detail in this section.

16-Bit 4:2:2 YCrCb Mode

Subaddress 0x87, Bit 7 = 0;

Subaddress 0x88, Bits[4:3] = 01

In 16-bit 4:2:2 YCrCb input mode, the Y pixel data is input on

Pin P15 to Pin P8, with Pin P8 being the LSB.

The CrCb pixel data is input on Pin P7 to Pin P0, with Pin P0

being the LSB.

STANDARD DEFINITION

Subaddress 0x01, Bits[6:4] = 000

The pixel data is updated at half the rate of the clock, that is, at a

rate of 13.5 MHz (see Figure 5).

Standard definition YCrCb data can be input in 4:2:2 format over

an 8-, 10-, or 16-bit bus. SD RGB data can be input in 4:4:4 format

over a 16-bit bus.

16-Bit 4:4:4 RGB Mode

Embedded EAV/SAV timing codes are not supported with SD RGB

mode. Also, master timing mode is not supported for SD RGB

input mode, therefore, external synchronization must be used.

A 27 MHz clock signal must be provided on the CLKIN pin. If

required, external synchronization signals can be provided on

HSYNC

VSYNC

the

and

pins. Embedded EAV/SAV timing

Subaddress 0x87, Bit 7 = 1

codes are also supported in 8-bit and 10-bit modes.

In 16-bit 4:4:4 RGB input mode, the red pixel data is input on

Pin P4 to Pin P0, the green pixel data is input on Pin P10 to

Pin P5, and the blue pixel data is input on Pin P15 to Pin P11.

The P0, P5, and P11 pins are the respective bus LSBs.

8-Bit 4:2:2 YCrCb Mode

Subaddress 0x87, Bit 7 = 0;

Subaddress 0x88, Bits[4:3] = 00

In 8-bit 4:2:2 YCrCb input mode, the interleaved pixel data is

input on Pin P15 to Pin P8, with Pin P8 being the LSB. The

ITU-R BT.601/656 input standard is supported.

The pixel data is updated at half the rate of the clock, that is, at a

rate of 13.5 MHz (see Figure 6).

ADV7392/

ADV7393

10-Bit 4:2:2 YCrCb Mode

2

VSYNC,

Subaddress 0x87, Bit 7 = 0;

Subaddress 0x88, Bits[4:3] = 10

MPEG2

HSYNC

DECODER

27MHz

CLKIN

In 10-bit 4:2:2 YCrCb input mode, the interleaved pixel data is

input on Pin P15 to Pin P6, with Pin P6 being the LSB. The ITU-

R BT.601/656 input standard is supported.

8/10

YCrCb

P[15:8]/P[15:6]

Figure 56. SD Example Application

Table 36. ADV7392/ADV7393 Input Configuration

Input Mode¹

P15

P14

P13

P12

P11

P10

P9

P8

P7

P6

P5

P4

P3

P2

P1

P0

000

SD²

SD RGB input enable (0x87[7]) = 0

8-bit

YCrCb

10-bit

16-bit³

YCrCb

SD RGB input enable (0x87[7]) = 1

Y

CrCb

16-bit³

B

G

R

001

010

ED/HD-SDR (16-bit)

ED/HD-DDR⁴

8-bit

Y

CrCb

ED/HD input format (0x33[2]) = 0

ED/HD input format (0x33[2]) = 1

YCrCb

10-bit

YCrCb

111

ED (at 54 MHz)

8-bit

ED/HD input format (0x33[2]) = 0

YCrCb

ED/HD input format (0x33[2]) = 1

10-bit

YCrCb

¹The input mode is determined by Subaddress 0x01, Bits[6:4].

²In SD mode, the width of the input data is determined by Subaddress 0x88, Bits[4:3].

³External synchronization signals must be used in this input mode. Embedded EAV/SAV timing codes are not supported.

⁴ED = enhanced definition = 525p and 625p.

Rev. H | Page 47 of 108

ADV7390/ADV7391/ADV7392/ADV7393

Data Sheet

ENHANCED DEFINITION/HIGH DEFINITION

Subaddress 0x01, Bits[6:4] = 001 or 010

M

PEG2

ADV7392/

ADV7393

DECODER

ED or HD YCrCb data can be input in a 4:2:2 format over an

8-/10-bit DDR bus or a 16-bit SDR bus.

CLKIN

YCrCb

8

The clock signal must be provided on the CLKIN pin. If

required, external synchronization signals can be provided on

CrCb

Y

P[7:0]

INTERLACED TO

PROGRESSIVE

P[15:8]

HSYNC

codes are also supported.

VSYNC

the

and

pins. Embedded EAV/SAV timing

2

VSYNC

HSYNC

16-Bit 4:2:2 YCrCb Mode (SDR)

Figure 59. ED/HD-SDR Example Application

In 16-bit 4:2:2 YCrCb input mode, the Y pixel data is input on

Pin P15 to Pin P8, with P8 being the LSB.

The CrCb pixel data is input on Pin P7 to Pin P0, with Pin P0

being the LSB.

MPEG2

DECODER

ADV7392/

ADV7393

8-/10-Bit 4:2:2 YCrCb Mode (DDR)

CLKIN

YCrCb

In 8-/10-bit DDR 4:2:2 YCrCb input mode, the Y pixel data is

input on Pin P15 to Pin P8/P6 on either the rising or falling

edge of CLKIN. Pin P8/P6 is the LSB.

8/10

2

YCrCb

P[15:8]/P[15:6]

INTERLACED TO

PROGRESSIVE

The CrCb pixel data is also input on Pin P15 to Pin P8/P6

on the opposite edge of CLKIN. P8/P6 is the LSB.

VSYNC

HSYNC

The 10-bit mode is enabled using Subaddress 0x33, Bit 2.

Whether the Y data is clocked in on the rising or falling edge of

CLKIN is determined by Subaddress 0x01, Bits[2:1] (see Figure 57

and Figure 58).

Figure 60. ED/HD-DDR Example Application

ENHANCED DEFINITION (AT 54 MHz)

Subaddress 0x01, Bits[6:4] = 111

ED YCrCb data can be input in an interleaved 4:2:2 format on

an 8-/10-bit bus at a rate of 54 MHz.

CLKIN

A 54 MHz clock signal must be provided on the CLKIN pin.

Embedded EAV/SAV timing codes are supported. External

synchronization signals are not supported in this mode.

P[15:8]/

P]15:6]

3FF

00

XY

Cb0

Y0

Cr0

Y1

NOTES

The interleaved pixel data is input on Pin P15 to Pin P8/P6,

with Pin P8/P6 being the LSB.

1. SUBADDRESS 0x01 [2:1] SHOULD BE SET TO 00 IN THIS CASE.

2. 10-BIT MODE IS ENABLED USING SUBADDRESS 0x33, BIT 2.

Figure 57. ED/HD-DDR Input Sequence (EAV/SAV)—Option A

The 10-bit mode is enabled using Subaddress 0x33, Bit 2.

CLKIN

P[15:8]/P[15:6]

NOTES

3FF

00

XY

Cb0

Y0

Cr0

Y1

P[15:8]/

P[15:P6]

3FF

00

XY

Y0

Cb0

Y1

Cr0

1. 10-BIT MODE IS ENABLED USING SUBADDRESS 0x33, BIT 2.

NOTES

Figure 61. ED (at 54 MHz) Input Sequence (EAV/SAV)

1. SUBADDRESS 0x01 [2:1] SHOULD BE SET TO 11 IN THIS CASE.

2. 10-BIT MODE IS ENABLED USING SUBADDRESS 0x33, BIT 2.

Figure 58. ED/HD-DDR Input Sequence (EAV/SAV)—Option B

MPEG2

DECODER

ADV7392/

ADV7393

54MHz

YCrCb

CLKIN

YCrCb

8/10

P[15:8]/P[15:6]

INTERLACED TO

PROGRESSIVE

VSYNC,

HSYNC

Figure 62 ED (at 54 MHz) Example Application

Rev. H | Page 48 of 108

Data Sheet

ADV7390/ADV7391/ADV7392/ADV7393

OUTPUT CONFIGURATION

The ADV739x supports a number of different output configurations. Table 37 to Table 39 list all possible output configurations.

Table 37. SD Output Configurations

RGB/YPrPb Output Select¹

(Subaddress 0x02, Bit 5)

SD DAC Output 1

(Subaddress 0x82, Bit 1)

SD Luma/Chroma Swap

(Subaddress 0x84, Bit 7)

DAC 1

G

Y

CVBS

DAC 2

B

Pb

Luma

Chroma

DAC 3

R

Pr

Chroma

Luma

0

1

0

1

0

1

¹If SD RGB output is selected, a color reversal is possible using Subaddress 0x86, Bit 7.

Table 38. ED/HD Output Configurations

RGB/YPrPb Output Select

(Subaddress 0x02, Bit 5)

ED/HD Color DAC Swap

(Subaddress 0x35, Bit 3)

DAC 1

DAC 2

DAC 3

0

1

0

1

0

1

G

Y

B

R

Pb

Pr

R

B

Pr

Pb

Table 39. ED (at 54 MHz) Output Configurations

RGB/YPrPb Output Select

(Subaddress 0x02, Bit 5)

ED/HD Color DAC Swap

(Subaddress 0x35, Bit 3)

DAC 1

DAC 2

DAC 3

0

1

0

1

0

1

G

Y

B

R

Pb

Pr

R

B

Pr

Pb

Rev. H | Page 49 of 108

ADV7390/ADV7391/ADV7392/ADV7393

Data Sheet

DESIGN FEATURES

However, when the CEA861 compliance bit is enabled (0x39,

Bit 5 for ED/HD modes and 0x86, Bit 3 for SD modes), the part

expects the HS or VS to be active low or high depending on the

input format selected (0x30, Bits[7:3]).

OUTPUT OVERSAMPLING

The ADV739x includes an on-chip phase-locked loop (PLL)

that allows for oversampling of SD, ED, and HD video data. By

default, the PLL is disabled. The PLL can be enabled using

Subaddress 0x00, Bit 1 = 0.

If a different polarity other than the default is required for

ED/HD modes, 0x3A, Bits[2:0] can be used to invert PHSYNCB,

PVSYNCB or PBLANKB individually regardless of whether

CEA-861-B mode is enabled. It is not possible to invert

S_HSYNC or S_VSYNC.

Table 40 shows the various oversampling rates supported in the

ADV739x.

External Sync Polarity

For SD and ED/HD modes, the ADV739x parts typically expect

HS and VS to be low during their respective blanking periods.

Table 40. Output Oversampling Modes and Rates

Input Mode

(0x01, Bits[6:4])

PLL and Oversampling

Control (0x00, Bit 1)

SD/ED Oversample Rate

Select (0x0D, Bit 3)¹

HD Oversample Rate

Select (0x31, Bit 1)¹

Oversampling Mode

and Rate

000

001/010

111

SD

ED

HD

1

0

1

0

1

0

1

0

X

1

0

X

1

0

X

1

0

X

1

0

X

SD (2×)

SD (8×)

SD (16×)

ED (1×)

ED (4×)

ED (8×)

HD (1×)

HD (2×)

HD (4×)

ED (at 54 MHz)

ED (at 54 MHz) (1×)

ED (at 54 MHz) (4×)

ED (at 54 MHz) (8×)

111

¹X = don’t care

Rev. H | Page 50 of 108

Data Sheet

ADV7390/ADV7391/ADV7392/ADV7393

There is no negative effect in setting Subaddress 0x02, Bit 0 to

high, and this bit can remain high for all the other video

standards.

HD INTERLACE EXTERNAL HSYNC AND VSYNC

CONSIDERATIONS

If the encoder revision code (Subaddress 0xBB, Bits[7:6]) = 01

or higher, the user should set Subaddress 0x02, Bit 1 to high.

To ensure exactly correct timing in HD interlace modes when

ED/HD TIMING RESET

Subaddress 0x34, Bit 0

HSYNC

VSYNC

using

and

synchronization signals. If this bit is

An ED/HD timing reset is achieved by setting the ED/HD

timing reset control bit (Subaddress 0x34, Bit 0) to 1. In this

state, the horizontal and vertical counters remain reset. When

this bit is set back to 0, the internal counters resume counting.

This timing reset applies to the ED/HD timing counters only.

set to low, the first active pixel on each line is masked in HD

interlace modes and the Pr and Pb outputs are swapped when

using the YCrCb 4:2:2 input format. Setting Subaddress 0x02,

Bit 1 to low causes the encoder to behave in the same way as the

first version of silicon (that is, this setting is backward

compatible).

SD SUBCARRIER FREQUENCY LOCK

Subcarrier Frequency Lock (SFL) Mode

If the encoder revision code (Subaddress 0xBB, Bits[7:6]) = 00,

the setting of Subaddress 0x02, Bit 1 has no effect. In this

version of the encoder, the first active pixel is masked and the

Pr and Pb outputs are swapped when using YCrCb 4:2:2 input

format. To avoid these limitations, use the newer revision of

silicon or use a different type of synchronization.

In subcarrier frequency lock (SFL) mode (Subaddress 0x84,

Bits[2:1] = 11), the ADV739x can be used to lock to an external

video source. The SFL mode allows the ADV739x to automatically

alter the subcarrier frequency to compensate for line length

variations. When the part is connected to a device such as an

ADV7403 video decoder that outputs a digital data stream in the

SFL format, the part automatically changes to the compensated

subcarrier frequency on a line-by-line basis (see Figure 63). This

digital data stream is 67 bits wide, and the subcarrier is contained

in Bit 0 to Bit 21. Each bit is two clock cycles long.

These considerations apply only to the HD interlace modes

HSYNC

VSYNC

with external

and

synchronization (EAV/SAV

mode is not affected and always has exactly correct timing).

ADV739x

CLKIN

DAC 1

DAC 2

DAC 3

LLC1

SFL

COMPOSITE

P19 TO

P10

ADV7403

VIDEO

DECODER

1

VIDEO

5

PIXEL PORT

4 BITS

RESERVED

21

0

14 BITS

SEQUENCE

4

H/L TRANSITION

COUNT START

RESET BIT

SUBCARRIER

PHASE

3

BIT

LOW

RESERVED

2

PLL INCREMENT

F

128

SC

13

0

RTC

6768

14

19

TIME SLOT 01

VALID

SAMPLE

INVALID

SAMPLE

8/LINE

LOCKED

CLOCK

5 BITS

RESERVED

1

2

FOR EXAMPLE, VCR OR CABLE.

F

PLL INCREMENT IS 22 BITS LONG. VALUE LOADED INTO ADV73xx F DDS REGISTER IS

SC

F

PLL INCREMENTS BITS[21:0] PLUS BITS[0:9] OF SUBCARRIER FREQUENCY REGISTERS.

SC

3

SEQUENCE BIT

PAL: 0 = LINE NORMAL, 1 = LINE INVERTED

NTSC: 0 = NO CHANGE

RESET ADV739x DDS.

4

5

REFER TO THE ADV7390/ADV7391 AND ADV7392/ADV7393 INPUT CONFIGURATION TABLES FOR PIXEL DATA PIN ASSIGNMENTS.

Figure 63. SD Subcarrier Frequency Lock Timing and Connections Diagram (Subaddress 0x84, Bits [2:1] = 11)

Rev. H | Page 51 of 108

ADV7390/ADV7391/ADV7392/ADV7393

Data Sheet

SD VCR FF/RW SYNC

Subaddress 0x82, Bit 5

227.5

1716













Subcarrier Register Value =

where:

×

³²= 569408543

2

In DVD record applications where the encoder is used with a

decoder, the VCR FF/RW sync control bit can be used for non-

standard input video, that is, in fast forward or rewind modes.

Subcarrier Register Value = 569408543d = 0×21F07C1F

SD F_SCRegister 0: 0x1F

SD F_SCRegister 1: 0x7C

SD F_SCRegister 2: 0xF0

SD F_SCRegister 3: 0x21

In fast forward mode, the sync information at the start of a new

field in the incoming video usually occurs before the correct

number of lines/fields is reached. In rewind mode, this sync

signal usually occurs after the total number of lines/fields is

reached. Conventionally, this means that the output video has

corrupted field signals because one signal is generated by the

incoming video and another is generated when the internal

line/field counters reach the end of a field.

Programming the F_SC

The subcarrier frequency register value is divided into four F_SC

registers as shown in the previous example. The four subcarrier

frequency registers must be updated sequentially, starting with

Subcarrier Frequency Register 0 and ending with Subcarrier

Frequency Register 3. The subcarrier frequency updates only

after the last subcarrier frequency register byte is received by

the ADV739x. The SD input standard autodetection feature

must be disabled.

When the VCR FF/RW sync control is enabled (Subaddress 0x82,

Bit 5), the line/field counters are updated according to the

VSYNC

incoming

signal and when the analog output matches

VSYNC

the incoming

signal. This control is available in all

slave-timing modes except Slave Mode 0.

Typical F_SCValues

VERTICAL BLANKING INTERVAL

Subaddress 0x31, Bit 4; Subaddress 0x83, Bit 4

Table 41 outlines the values that should be written to the

subcarrier frequency registers for NTSC and PAL B/D/G/H/I.

The ADV739x is able to accept input data that contains vertical

blanking interval (VBI) data (such as CGMS, WSS, VITS) in

SD, ED, and HD modes.

Table 41. Typical F_SCValues

Subaddress

Description

NTSC

0x1F

0x7C

0xF0

0x21

PAL B/D/G/H/I

0xCB

0x8A

0x09

0x2A

0x8C

F_SC0

If VBI is disabled (Subaddress 0x31, Bit 4 for ED/HD; Subaddress

0x83, Bit 4 for SD), VBI data is not present at the output and the

entire VBI is blanked. These control bits are valid in all master

and slave timing modes.

0x8D

F_SC1

0x8E

F_SC2

0x8F

F_SC3

SD NONINTERLACED MODE

Subaddress 0x88, Bit 1

For the SMPTE 293M (525p) standard, VBI data can be inserted

on Line 13 to Line 42 of each frame or on Line 6 to Line 43 for

the ITU-R BT.1358 (625p) standard. VBI data can be present on

Line 10 to Line 20 for NTSC and on Line 7 to Line 22 for PAL.

The ADV739x supports an SD noninterlaced mode. Using this

mode, progressive inputs at twice the frame rate of NTSC and

PAL (240p/59.94 Hz and 288p/50 Hz, respectively) can be input

into the ADV739x. The SD noninterlaced mode can be enabled

using Subaddress 0x88, Bit 1.

In SD Timing Mode 0 (slave option), if VBI is enabled, the

blanking bit in the EAV/SAV code is overwritten. It is possible

to use VBI in this timing mode as well.

A 27 MHz clock signal must be provided on the CLKIN pin.

Embedded EAV/SAV timing codes or external horizontal and

If CGMS is enabled and VBI is disabled, the CGMS data is,

nevertheless, available at the output.

HSYNC

vertical synchronization signals provided on the

VSYNC

and

data.

SD SUBCARRIER FREQUENCY CONTROL

Subaddress 0x8C to Subaddress 0x8F

pins can be used to synchronize the input pixel

The ADV739x is able to generate the color subcarrier used in

CVBS and S-Video (Y-C) outputs from the input pixel clock.

Four 8-bit registers are used to set up the subcarrier frequency.

The value of these registers is calculated using the following

equation:

All input configurations, output configurations, and features

available in NTSC and PAL modes are available in SD noninter-

laced mode. For 240p/59.94 Hz input, the ADV739x should be

configured for NTSC operation and Subaddress 0x88, Bit 1

should be set to 1.

Subcarrier Frequency Register =

For 288p/50 Hz input, the ADV739x should be configured for

PAL operation and Subaddress 0x88, Bit 1 should be set to 1.

Number of subcarrier periods in one video line

× 2³²

Number of 27 MHz clock cycles in one video line

where the sum is rounded to the nearest integer.

For example, in NTSC mode:

Rev. H | Page 52 of 108

Data Sheet

ADV7390/ADV7391/ADV7392/ADV7393

For CVBS and S-Video (Y-C) outputs, the SD subcarrier

frequency registers must be updated to reflect the input clock

frequency used in SD square pixel mode. The SD input standard

autodetection feature must be disabled in SD square pixel

mode. In square pixel mode, the timing diagrams shown in

Figure 64 and Figure 65 apply.

SD SQUARE PIXEL MODE

Subaddress 0x82, Bit 4

The ADV739x supports an SD square pixel mode (Subaddress

0x82, Bit 4). For NTSC operation, an input clock of 24.5454 MHz

is required. The active resolution is 640 × 480. For PAL

operation, an input clock of 29.5 MHz is required. The active

resolution is 768 × 576.

ANALOG

VIDEO

EAV CODE

SAV CODE

C

b

C

r

C

b

8

0

F

F A A

F B B

A

B

8

0

C

r

F

0

X

Y

1

0

8

0

1

0

8

0

1

0

1

0

F

0

X

Y

C

b

C

r

Y

INPUT PIXELS

ANCILLARY DATA

(HANC)

4 CLOCK

NTSC/PAL M SYSTEM

(525 LINES/60Hz)

272 CLOCK

1280 CLOCK

1536 CLOCK

PAL SYSTEM

(625 LINES/50Hz)

344 CLOCK

START OF ACTIVE

VIDEO LINE

END OF ACTIVE

VIDEO LINE

Figure 64. Square Pixel Mode EAV/SAV Embedded Timing

HSYNC

FIELD

PIXEL

DATA

Cr

Y

Cb

Y

PAL = 308 CLOCK CYCLES

NTSC = 236 CLOCK CYCLES

Figure 65. Square Pixel Mode Active Pixel Timing

Rev. H | Page 53 of 108

ADV7390/ADV7391/ADV7392/ADV7393

Data Sheet

EXTENDED (SSAF) PrPb FILTER MODE

FILTERS

0

–10

–20

–30

–40

–50

–60

Table 42 shows an overview of the programmable filters available

on the ADV739x.

Table 42. Selectable Filters

Filter

Subaddress

0x80

0x82

0x33

SD Luma LPF NTSC

SD Luma LPF PAL

SD Luma Notch NTSC

SD Luma Notch PAL

SD Luma SSAF

SD Luma CIF

SD Luma QCIF

0

1

2

3

4

5

6

FREQUENCY (MHz)

SD Chroma 0.65 MHz

SD Chroma 1.0 MHz

SD Chroma 1.3 MHz

SD Chroma 2.0 MHz

SD Chroma 3.0 MHz

SD Chroma CIF

SD Chroma QCIF

SD PrPb SSAF

ED/HD Sinc Compensation Filter

ED/HD Chroma SSAF

Figure 66. PrPb SSAF Filter

If this filter is disabled, one of the chroma filters shown in

Table 43 can be selected and used for the CVBS or luma/

chroma signal.

Table 43. Internal Filter Specifications

Pass-Band

Filter

Ripple (dB)¹

0.16

3 dB Bandwidth (MHz)²

Luma LPF NTSC

Luma LPF PAL

Luma Notch NTSC

Luma Notch PAL

Luma SSAF

4.24

4.81

0.1

0.09

0.1

0.04

2.3/4.9/6.6

3.1/5.6/6.4

6.45

SD Internal Filter Response

Subaddress 0x80, Bits[7:2]; Subaddress 0x82, Bit 0

The Y filter supports several different frequency responses,

including two low-pass responses, two notch responses, an

extended (SSAF) response with or without gain boost atten-

uation, a CIF response, and a QCIF response. The PrPb filter

supports several different frequency responses, including six

low-pass responses, a CIF response, and a QCIF response, as

shown in Figure 38 and Figure 39.

Luma CIF

Luma QCIF

0.127

3.02

1.5

0.65

1

1.395

2.2

3.2

0.65

0.5

Monotonic

0.09

Chroma 0.65 MHz

Chroma 1.0 MHz

Chroma 1.3 MHz

Chroma 2.0 MHz

Chroma 3.0 MHz

Chroma CIF

0.048

Monotonic

If SD Luma SSAF gain is enabled (Subaddress 0x87, Bit 4), there

are 13 response options in the range −4 dB to +4 dB. The desired

response can be programmed using Subaddress 0xA2. Variation

in frequency responses is shown in Figure 35 to Figure 37.

Chroma QCIF

¹Pass-band ripple is the maximum fluctuation from the 0 dB response in the

pass band, measured in decibels. The pass band is defined to have 0 Hz to fc

(Hz) frequency limits for a low-pass filter and 0 Hz to f1 (Hz) and f2 (Hz) to

infinity for a notch filter, where fc, f1, and f2 are the −3 dB points.

²3 dB bandwidth refers to the −3 dB cutoff frequency.

In addition to the chroma filters listed in Table 42, the ADV739x

contains an SSAF filter that is specifically designed for the color

difference component outputs, Pr and Pb. This filter has a cutoff

frequency of ~2.7 MHz and a gain of –40 dB at 3.8 MHz (see

Figure 66). This filter can be controlled with Bit 0 of Sub-

address 0x82, Bit 0.

Rev. H | Page 54 of 108

Data Sheet

ADV7390/ADV7391/ADV7392/ADV7393

ED/HD Sinc Compensation Filter Response

Table 44 shows sample color values that can be programmed

into the color registers when the output standard selection is set

to EIA770.2/EIA770.3 (Subaddress 0x30, Bits[1:0] = 00).

Subaddress 0x33, Bit 3

The ADV739x includes a filter designed to counter the effect of

sinc roll-off in DAC 1, DAC 2, and DAC 3 while operating in

ED/HD mode. This filter is enabled by default. It can be

disabled using Subaddress 0x33, Bit 3. The benefit of the filter is

illustrated in Figure 67 and Figure 68.

Table 44. Sample Color Values for EIA770.2/EIA770.3

ED/HD Output Standard Selection

Sample Color

Y Value

Cr Value

Cb Value

White

Black

Red

Green

Blue

Yellow

Cyan

235 (0xEB)

128 (0x80) 128 (0x80)

0.5

16

81

(0x10)

(0x51)

0.4

0.3

240 (0xF0)

90

(0x5A)

(0x36)

145 (0x91)

41 (0x29)

34

(0x22) 54

110 (0x6E)

240 (0xF0)

(0x10)

(0x10) 166 (0xA6)

106 (0x6A) 222 (0xDE) 202 (0xCA)

0.2

210 (0xD2) 146 (0x92) 16

170 (0xAA) 16

0.1

0

Magenta

–0.1

–0.2

–0.3

–0.4

–0.5

COLOR SPACE CONVERSION MATRIX

Subaddress 0x03 to Subaddress 0x09

The internal color space conversion (CSC) matrix automatically

performs all color space conversions based on the input mode

programmed in the mode select register (Subaddress 0x01,

Bits[6:4]). Table 45 and Table 46 show the options available in

this matrix.

0

5

10

15

20

25

30

FREQUENCY (MHz)

Figure 67. ED/HD Sinc Compensation Filter Enabled

0.5

0.4

An SD color space conversion from RGB-in to YPrPb-out is

possible on the ADV7392/ADV7393. An ED/HD color space

conversion from RGB-in to YPrPb-out is not possible.

0.3

0.2

Table 45. SD Color Space Conversion Options

0.1

YPrPb/RGB Out

(Subaddress 0x02,

RGB In/YCrCb In

(Subaddress 0x87,

Bit 7)

0

Input Output¹Bit 5)

–0.1

–0.2

–0.3

–0.4

–0.5

YCrCb YPrPb

YCrCb RGB

1

0

1

0

1

RGB²

YPrPb

RGB

0

5

10

15

20

25

30

¹CVBS/Y-C outputs are available for all CSC combinations.

²Available on the ADV7392/ADV7393 (40-pin devices) only.

FREQUENCY (MHz)

Figure 68. ED/HD Sinc Compensation Filter Disabled

Table 46. ED/HD Color Space Conversion Options

YPrPb/RGB Out

(Subaddress 0x02, Bit 5)

ED/HD TEST PATTERN COLOR CONTROLS

Subaddress 0x36 to Subaddress 0x38

Input

YCrCb

Output

YPrPb

RGB

1

0

Three 8-bit registers at Subaddress 0x36 to Subaddress 0x38

are used to program the output color of the internal ED/HD

test pattern generator (Subaddress 0x31, Bit 2 = 1), whether it

be the lines of the crosshatch pattern or the uniform field test

pattern. They are not functional as color controls for external

pixel data input.

SD Manual CSC Matrix Adjust Feature

The SD manual CSC matrix adjust feature (available for the

ADV7392 and ADV7393 only) provides custom coefficient

manipulation for RGB to YPbPr conversion (for YPbPr to RGB

conversion, this matrix adjustment is not available).

The values for the luma (Y) and color difference (Cr and Cb)

signals used to obtain white, black, and saturated primary and

complementary colors conform to the ITU-R BT.601-4

standard.

Normally, there is no need to modify the SD matrix coefficients

because the CSC matrix automatically performs the color space

conversion based on the output color space selected (see Table 46).

Note that Bit 7 in subaddress 0x87 must be set to enable RGB

input and, therefore, use the CSC manual adjustment.

Rev. H | Page 55 of 108

ADV7390/ADV7391/ADV7392/ADV7393

Data Sheet

The SD CSC matrix scalar uses the following equations:

Y = (a1 × R) + (a2 × G) + (a3 × B) + a4

On power-up, the CSC matrix is programmed with the default

values shown in Table 48.

Table 48. ED/HD Manual CSC Matrix Default Values

Pr = (b1 × R) + (b2 × G) + (b3 × B) + b4

Pb = (c1 × R) + (c2 × G) + (c3 × B) + c4

Subaddress

Default

0x03

0xF0

0x4E

0x0E

0x24

0x92

0x7C

0x03

0x04

0x05

0x06

0x07

0x08

0x09

The coefficients and their default values are located in the

registers shown in Table 47.

Table 47. SD Manual CSC Matrix Default Values

Coefficient

Subaddress

0xBD

0xBE

Default

0x42

0x81

0x19

0x10

0x70

0x5E

0x12

0x80

0x26

0x4A

0x70

0x80

a1

a2

a3

a4

b1

b2

b3

b4

c1

c2

c3

c4

0xBF

0xC0

0xC1

0xC2

0xC3

0xC4

0xC5

0xC6

When the ED/HD manual CSC matrix adjust feature is

enabled, the default coefficient values in Subaddress 0x03

to Subaddress 0x09 are correct for the HD color space only.

The color components are converted according to the following

1080i and 720p standards (SMPTE 274M, SMPTE 296M):

R = Y + 1.575Pr

G = Y − 0.468Pr − 0.187Pb

B = Y + 1.855Pb

0xC7

0xC8

The conversion coefficients should be multiplied by 315 before

being written to the ED/HD CSC matrix registers. This is

reflected in the default values for GY = 0x13B, GU = 0x03B,

GV = 0x093, BU = 0x248, and RV = 0x1F0.

ED/HD Manual CSC Matrix Adjust Feature

The ED/HD manual CSC matrix adjust feature provides custom

coefficient manipulation for color space conversions and is used

in ED and HD modes only. The ED/HD manual CSC matrix

adjust feature can be enabled using Subaddress 0x02, Bit 3.

If the ED/HD manual CSC matrix adjust feature is enabled and

another input standard (such as ED) is used, the scale values for

GY, GU, GV, BU, and RV must be adjusted according to this

input standard color space. The user should consider that the

color component conversion may use different scale values.

Normally, there is no need to enable this feature because the CSC

matrix automatically performs the color space conversion based

on the input mode chosen (ED or HD) and the output color

space selected (see Table 46). For this reason, the ED/HD

manual CSC matrix adjust feature is disabled by default.

For example, SMPTE 293M uses the following conversion:

R = Y + 1.402Pr

If RGB output is selected, the ED/HD CSC matrix scalar uses

the following equations:

G = Y − 0.714Pr − 0.344Pb

B = Y + 1.773Pb

R = GY × Y + RV × Pr

The programmable CSC matrix is used for external ED/HD

pixel data and is not functional when internal test patterns are

enabled.

G = GY × Y − (GU × Pb) − (GV × Pr)

B = GY × Y + BU × Pb

Note that subtractions are implemented in the hardware.

If YPrPb output is selected, the following equations are used:

Y = GY × Y

Programming the CSC Matrix

If custom manipulation of the ED/HD CSC matrix coefficients

is required for a YCrCb-to-RGB color space conversion, use the

following procedure:

Pr = RV × Pr

1. Enable the ED/HD manual CSC matrix adjust feature

(Subaddress 0x02, Bit 3).

2. Set the output to RGB (Subaddress 0x02, Bit 5).

3. Disable sync on PrPb (Subaddress 0x35, Bit 2).

4. Enable sync on RGB (optional) (Subaddress 0x02, Bit 4).

Pb = BU × Pb

where:

GY = Subaddress 0x05, Bits[7:0] and Subaddress 0x03, Bits[1:0].

GU = Subaddress 0x06, Bits[7:0] and Subaddress 0x04, Bits[7:6].

GV = Subaddress 0x07, Bits[7:0] and Subaddress 0x04, Bits[5:4].

BU = Subaddress 0x08, Bits[7:0] and Subaddress 0x04, Bits[3:2].

RV = Subaddress 0x09, Bits[7:0] and Subaddress 0x04, Bits[1:0].

The GY value controls the green signal output level, the BU

value controls the blue signal output level, and the RV value

controls the red signal output level.

Rev. H | Page 56 of 108

Data Sheet

ADV7390/ADV7391/ADV7392/ADV7393

For example, to adjust the hue by +4°, write 0x97 to the hue

adjust control register.

SD LUMA AND COLOR SCALE CONTROL

Subaddress 0x9C to Subaddress 0x9F

4













When enabled, the SD luma and color scale control feature can

be used to scale the SD Y, Cb, and Cr output levels. This feature

can be enabled using Subaddress 0x87, Bit 0. This feature affects

all SD output signals, that is, CVBS, Y-C, YPrPb, and RGB.

+ 128 ≈151d = 0x97

0.17578125

where the sum is rounded to the nearest integer.

To adjust the hue by −4°, write 0x69 to the hue adjust control

register.

When enabled, three 10-bit registers (SD Y scale, SD Cb scale,

and SD Cr scale) control the scaling of the SD Y, Cb, and Cr

output levels. The SD Y scale register contains the scaling factor

used to scale the Y level from 0.0 to 1.5 times its initial level.

The SD Cb scale and SD Cr scale registers contain the scaling

factors to scale the Cb and Cr levels from 0.0 to 2.0 times their

initial levels, respectively.

−4













+ 128 ≈105d = 0x69

0.17578125

where the sum is rounded to the nearest integer.

SD BRIGHTNESS DETECT

Subaddress 0xBA

The values to be written to these 10-bit registers are calculated

using the following equation:

The ADV739x allows monitoring of the brightness level of the

incoming video data. This feature is used to monitor the

average brightness of the incoming Y signal on a field-by-field

basis. The information is read from the I²C and, based on this

information, the color saturation, contrast, and brightness

controls can be adjusted (for example, to compensate for very

dark pictures).

Y, Cb, or Cr Scale Value = Scale Factor × 512

For example, if Scale Factor = 1.3

Y, Cb, or Cr Scale Value = 1.3 × 512 = 665.6

Y, Cb, or Cr Scale Value = 666 (rounded to the nearest integer)

Y, Cb, or Cr Scale Value = 1010011010b

The luma data is monitored in the active video area only. The

average brightness I²C register is updated on the falling edge of

Subaddress 0x9C, SD scale LSB = 0x2A

every

signal. The SD brightness detect register (Subad-

VSYNC

Subaddress 0x9D, SD Y scale register = 0xA6

Subaddress 0x9E, SD Cb scale register = 0xA6

Subaddress 0x9F, SD Cr scale register = 0xA6

dress 0xBA) is a read-only register.

SD BRIGHTNESS CONTROL

It is recommended that the SD luma scale saturation feature

(Subaddress 0x87, Bit 1) be enabled when scaling the Y output

level to avoid excessive Y output levels.

Subaddress 0xA1, Bits[6:0]

When this feature is enabled, the SD brightness/WSS control

register (Subaddress 0xA1) is used to control brightness by

adding a programmable setup level onto the scaled Y data. This

feature can be enabled using Subaddress 0x87, Bit 3.

SD HUE ADJUST CONTROL

Subaddress 0xA0

For NTSC with pedestal, the setup can vary from 0 IRE to 22.5 IRE.

For NTSC without pedestal (see Figure 69) and for PAL, the

When enabled, the SD hue adjust control register (Subaddress

0xA0) is used to adjust the hue on the SD composite and

chroma outputs. This feature can be enabled using Subaddress

0x87, Bit 2.

setup can vary from −7.5 IRE to +15 IRE.

NTSC WITHOUT PEDESTAL

+7.5 IRE

100 IRE

Subaddress 0xA0 contains the bits required to vary the hue of

the video data, that is, the variance in phase of the subcarrier

during active video with respect to the phase of the subcarrier

during the color burst. The ADV739x provides a range of

22.5° in increments of 0.17578125°. For normal operation

(zero adjustment), this register is set to 0x80. Value 0xFF and

Value 0x00 represent the upper and lower limits, respectively, of

the attainable adjustment in NTSC mode. Value 0xFF and Value

0x01 represent the upper and lower limits, respectively, of the

attainable adjustment in PAL mode.

0 IRE

–7.5 IRE

POSITIVE SETUP

VALUE ADDED

NEGATIVE SETUP

VALUE ADDED

NO SETUP

VALUE ADDED

Figure 69. Examples of Brightness Control Values

The SD brightness control register is an 8-bit register. The seven

LSBs of this 8-bit register are used to control the brightness

level, which can be a positive or negative value.

For example, to add a +20 IRE brightness level to an NTSC

signal with pedestal, write 0x28 to Subaddress 0xA1.

The hue adjust value is calculated using the following equation:

Hue Adjust (°) = 0.17578125° (HCR_d− 128)

0 × (SD Brightness Value) =

0 × (IRE Value × 2.015631) =

Where HCR_d= the hue adjust control register (decimal).

0 × (20 × 2.015631) = 0 × (40.31262) ≈ 0x28

Rev. H | Page 57 of 108

ADV7390/ADV7391/ADV7392/ADV7393

Data Sheet

To add a –7 IRE brightness level to a PAL signal, write 0x72 to

Subaddress 0xA1.

PROGRAMMABLE DAC GAIN CONTROL

Subaddress 0x0B

0 × (SD Brightness Value) =

It is possible to adjust the DAC output signal gain up or down

from its absolute level. This is illustrated in Figure 70.

0 × (IRE Value × 2.075631) =

DAC 1 to DAC 3 are controlled by Register 0x0B.

0 × (7 × 2.015631) = 0x(14.109417) ≈ 0001110b

0001110b into twos complement = 1110010b = 0x72

In Case A of Figure 70, the video output signal is gained. The

absolute level of the sync tip and the blanking level increase

with respect to the reference video output signal. The overall

gain of the signal is increased from the reference signal.

Table 49. Sample Brightness Control Values¹

Setup Level

(NTSC) with

Pedestal

Setup Level

(NTSC) Without Level

Pedestal

15 IRE

7.5 IRE

0 IRE

Setup

Brightness

Control Value

In Case B of Figure 70, the video output signal is reduced. The

absolute level of the sync tip and the blanking level decrease

with respect to the reference video output signal. The overall

gain of the signal is reduced from the reference signal.

(PAL)

22.5 IRE

15 IRE

7.5 IRE

0 IRE

15 IRE

7.5 IRE

0 IRE

0x1E

0x0F

0x00

0x71

−7.5 IRE

CASE A

¹Values in the range of 0x3F to 0x44 may result in an invalid output signal.

SD INPUT STANDARD AUTODETECTION

Subaddress 0x87, Bit 5

GAIN PROGRAMMED IN DAC OUTPUT LEVEL

REGISTERS, SUBADDRESS 0x0B

700mV

The ADV739x includes an SD input standard autodetect feature

that can be enabled by setting Subaddress 0x87, Bits[5:1].

When enabled, the ADV739x can automatically identify an

NTSC or a PAL B/D/G/H/I input stream. The ADV739x

automatically updates the subcarrier frequency registers with

the appropriate value for the identified standard. The ADV739x

is also configured to correctly encode the identified standard.

300mV

The SD standard bits (Subaddress 0x80, Bits[1:0]) and the

subcarrier frequency registers are not updated to reflect the

identified standard. All registers retain their default or user-

defined values.

NEGATIVE GAIN PROGRAMMED IN

CASE B

DAC OUTPUT LEVEL REGISTERS,

SUBADDRESS 0x0B

700mV

DOUBLE BUFFERING

Subaddress 0x33, Bit 7 for ED/HD;

Subaddress 0x88, Bit 2 for SD

300mV

Double-buffered registers are updated once per field. Double

buffering improves overall performance because modifications

to register settings are not be made during active video but take

effect prior to the start of the active video on the next field.

Figure 70. Programmable DAC Gain—Positive and Negative Gain

Using Subaddress 0x33, Bit 7, double buffering can be activated

on the following ED/HD registers: the ED/HD Gamma A and

Gamma B curves and ED/HD CGMS registers.

The range of this feature is specified for 7.5% of the nominal

output from the DACs. For example, if the output current of the

DAC is 4.33 mA, the DAC gain control feature can change this

output current from 4.008 mA (−7.5%) to 4.658 mA (+7.5%).

Using Subaddress 0x88, Bit 2, double buffering can be activated

on the following SD registers: the SD Gamma A and Gamma B

curves, SD Y scale, SD Cr scale, SD Cb scale, SD brightness, SD

closed captioning, and SD Macrovision Bits[5:0]

(Subaddress 0xE0, Bits[5:0]).

Rev. H | Page 58 of 108

Data Sheet

ADV7390/ADV7391/ADV7392/ADV7393

The reset value of the control registers is 0x00; that is, nominal

DAC current is output. Table 50 is an example of how the output

current of the DACs varies for a nominal 4.33 mA output current.

Gamma correction is performed on the luma data only. The

user can choose one of two correction curves, Curve A or

Curve B. Only one of these curves can be used at a time. For

ED/HD gamma correction, curve selection is controlled using

Subaddress 0x35, Bit 4. For SD gamma correction, curve

selection is controlled using Subaddress 0x88, Bit 7.

Table 50. DAC Gain Control

DAC Current

Subaddress 0x0B (mA)

% Gain

7.5000%

7.3820%

7.3640%

...

Note

The shape of the gamma correction curve is controlled by

defining the curve response at 10 different locations along the

curve. By altering the response at these locations, the shape of

the gamma correction curve can be modified. Between these

points, linear interpolation is used to generate intermediate

values. Considering the curve to have a total length of 256

points, the 10 programmable locations are at the following

points: 24, 32, 48, 64, 80, 96, 128, 160, 192, and 224. The

following locations are fixed and cannot be changed: 0, 16, 240,

and 255.

0100 0000 (0x40)

0011 1111 (0x3F)

0011 1110 (0x3E)

...

4.658

4.653

4.648

...

0000 0010 (0x02)

0000 0001 (0x01)

0000 0000 (0x00)

4.43

4.38

4.33

0.0360%

0.0180%

0.0000%

Reset value,

nominal

1111 1111 (0xFF)

1111 1110 (0xFE)

...

4.25

4.23

...

−0.0180%

−0.0360%

...

From the curve locations, 16 to 240, the values at the program-

mable locations and, therefore, the response of the gamma

correction curve, should be calculated to produce the following

result:

...

1100 0010 (0xC2)

1100 0001 (0xC1)

1100 0000 (0xC0)

4.018

4.013

4.008

−7.3640%

−7.3820%

−7.5000%

γ

x

_DESIRED= (x_INPUT

)

where:

x

_DESIREDis the desired gamma corrected output.

_INPUTis the linear input signal.

GAMMA CORRECTION

γ is the gamma correction factor.

Subaddress 0x44 to Subaddress 0x57 for ED/HD;

Subaddress 0xA6 to Subaddress 0xB9 for SD

To program the gamma correction registers, calculate the

10 programmable curve values using the following formula:

Generally, gamma correction is applied to compensate for the

nonlinear relationship between signal input and output

brightness level (as perceived on a CRT). It can also be applied

wherever nonlinear processing is used.







^γ















n −16

240 −16



γ_n=

×(240 −16) +16



where:

Gamma correction uses the function

Signal_OUT= (Signal_IN)^γ

γ_nis the value to be written into the gamma correction register

for point n on the gamma correction curve.

n = 24, 32, 48, 64, 80, 96, 128, 160, 192, or 224.

γ is the gamma correction factor.

where γ is the gamma correction factor.

Gamma correction is available for SD and ED/HD video. For

both variations, there are twenty 8-bit registers. They are used

to program Gamma Correction Curve A and Gamma

Correction Curve B.

For example, setting γ = 0.5 for all programmable curve data

points results in the following y_nvalues:

y₂₄= [(8/224)^0.5× 224] + 16 = 58

y₃₂= [(16/224)^0.5× 224] + 16 = 76

y₄₈= [(32/224)^0.5× 224] + 16 = 101

y₆₄= [(48/224)^0.5× 224] + 16 = 120

y₈₀= [(64/224)^0.5× 224] + 16 = 136

y₉₆= [(80/224)^0.5× 224] + 16 = 150

ED/HD gamma correction is enabled using Subaddress 0x35,

Bit 5. ED/HD Gamma Correction Curve A is programmed at

Subaddress 0x44 to Subaddress 0x4D, and ED/HD Gamma

Correction Curve B is programmed at Subaddress 0x4E to

Subaddress 0x57.

SD gamma correction is enabled using Subaddress 0x88, Bit 6.

SD Gamma Correction Curve A is programmed at Subaddress

0xA6 to Subaddress 0xAF, and SD Gamma Correction Curve B

is programmed at Subaddress 0xB0 to Subaddress 0xB9.

y

₁₂₈= [(112/224)^0.5× 224] + 16 = 174

₁₆₀= [(144/224)^0.5× 224] + 16 = 195

₁₉₂= [(176/224)^0.5× 224] + 16 = 214

₂₂₄= [(208/224)^0.5× 224] + 16 = 232

where the sum of each equation is rounded to the nearest integer.

Rev. H | Page 59 of 108

ADV7390/ADV7391/ADV7392/ADV7393

Data Sheet

The gamma curves in Figure 71 and Figure 72 are examples only;

any user-defined curve in the range from 16 to 240 is acceptable.

To select one of the 256 individual responses, the corresponding

gain values, ranging from −8 to +7 for each filter, must be

programmed into the ED/HD sharpness filter gain register at

Subaddress 0x40.

GAMMA CORRECTION BLOCK OUTPUT TO A RAMP INPUT

300

ED/HD Adaptive Filter Mode

250

SIGNAL OUTPUT

In ED/HD adaptive filter mode, the following registers are used:

200

0.5

•

ED/HD Adaptive Filter Threshold A

ED/HD Adaptive Filter Threshold B

ED/HD Adaptive Filter Threshold C

ED/HD Adaptive Filter Gain 1

ED/HD Adaptive Filter Gain 2

ED/HD Adaptive Filter Gain 3

ED/HD sharpness filter gain

150

100

SIGNAL INPUT

50

0

50

100

150

LOCATION

200

250

To activate the adaptive filter control, the ED/HD sharpness

filter and the ED/HD adaptive filter must be enabled

(Subaddress 0x31, Bit 7 = 1, and Subaddress 0x35, Bit 7 = 1,

respectively).

Figure 71. Signal Input (Ramp) and Signal Output for Gamma 0.5

GAMMA CORRECTION BLOCK TO A RAMP INPUT FOR

The derivative of the incoming signal is compared to the three

programmable threshold values: ED/HD adaptive filter

(Threshold A, Threshold B, and Threshold C ) registers

(Subaddress 0x5B, Subaddress 0x5C, and Subaddress 0x5D).

The recommended threshold range is 16 to 235, although any

value in the range of 0 to 255 can be used.

VARIOUS GAMMA VALUES

300

250

0.3

200

0.5

The edges can then be attenuated with the settings in the

ED/HD adaptive filter (Gain 1, Gain 2, and Gain 3) registers

(Subaddress 0x58, Subaddress 0x59 and Subaddress 0x5A), and

the ED/HD sharpness filter gain register (Subaddress 0x40).

150

1.5

100

1.8

50

There are two adaptive filter modes available. The mode is

selected using the ED/HD adaptive filter mode control

(Subaddress 0x35, Bit 6) as follows:

0

50

100

150

LOCATION

200

250

•

Mode A is used when the ED/HD adaptive filter mode

control is set to 0. In this case, Filter B (LPF) is used in the

adaptive filter block. In addition, only the programmed

values for Gain B in the ED/HD sharpness filter gain

register and ED/HD adaptive filter (Gain 1, Gain 2, and

Gain 3) registers are applied when needed. The Gain A

values are fixed and cannot be changed.

Mode B is used when ED/HD adaptive filter mode control is

set to 1. In this mode, a cascade of Filter A and Filter B is used.

Both settings for Gain A and Gain B in the ED/HD sharpness

filter gain register and ED/HD adaptive filter (Gain 1, Gain 2,

and Gain 3) registers become active when needed.

Figure 72. Signal Input (Ramp) and Selectable Output Curves

ED/HD SHARPNESS FILTER AND ADAPTIVE FILTER

CONTROLS

Subaddress 0x40; Subaddress 0x58 to Subaddress 0x5D

There are three filter modes available on the ADV739x:

sharpness filter mode and two adaptive filter modes.

•

ED/HD Sharpness Filter Mode

To enhance or attenuate the Y signal in the frequency ranges

shown in Figure 73, the ED/HD sharpness filter must be

enabled (Subaddress 0x31, Bit 7 = 1) and the ED/HD adaptive

filter must be disabled (Subaddress 0x35, Bit 7 = 0).

Rev. H | Page 60 of 108

Data Sheet

ADV7390/ADV7391/ADV7392/ADV7393

SHARPNESS AND ADAPTIVE FILTER CONTROL BLOCK

1.5

1.4

1.6

1.5

1.4

1.3

1.2

1.1

1.0

1.3

1.2

1.1

1.0

INPUT

SIGNAL

STEP

ꢀ

1.3

1.2

1.1

1.0

0.9

0.8

0.7

0.6

0.5

0.9

0.8

0.7

0.6

0.5

0

2

4

6

8

10

12

FREQUENCY (MHz)

FILTER A RESPONSE (Gain Ka)

FREQUENCY (MHz)

FILTER B RESPONSE (Gain Kb)

FREQUENCY (MHz)

FREQUENCY RESPONSE IN SHARPNESS

FILTER MODE WITH Ka = 3 AND Kb = 7

Figure 73. ED/HD Sharpness and Adaptive Filter Control

d

e

a

R2

R4

1

b

R1

c

f

1

R2

CH1 500mV

REF A

M 4.00µs

1 9.99978ms

CH1

ALL FIELDS

CH1 500mV

REF A

M 4.00µs

1 9.99978ms

CH1

ALL FIELDS

500mV 4.00µs

Block

Figure 74. ED/HD Sharpness Filter Control with Different Gain Settings for ED/HD Sharpness Filter Gain Values

Adaptive Filter Control Application

ED/HD SHARPNESS FILTER AND ADAPTIVE FILTER

APPLICATION EXAMPLES

Sharpness Filter Application

The register settings in Table 52 are used to obtain the results

shown in Figure 76, that is, to remove the ringing on the input

Y signal, as shown in Figure 75. Input data is generated by an

external signal source.

The ED/HD sharpness filter can be used to enhance or

attenuate the Y video output signal. The register settings in

Table 51 are used to achieve the results shown in Figure 74.

Input data is generated by an external signal source.

Table 52. Register Settings for Figure 76

Subaddress

Register Setting

0x00

0x01

0x02

0x30

0x31

0x35

0x40

0x58

0x59

0x5A

0x5B

0x5C

0x5D

0xFC

0x38

0x20

0x00

0x81

0x80

0x00

0xAC

0x9A

0x88

0x28

0x3F

Table 51. ED/HD Sharpness Control Settings for Figure 74

Subaddress

Register Setting

Reference¹

0x00

0xFC

0x01

0x10

0x02

0x20

0x30

0x00

0x31

0x81

0x40

0x00

0x08

0x04

0x40

0x80

0x22

a

b

c

d

e

f

0x64

¹See Figure 74.

Rev. H | Page 61 of 108

ADV7390/ADV7391/ADV7392/ADV7393

Data Sheet

In DNR mode, if the absolute value of the filter output is

smaller than the threshold, it is assumed to be noise. A

programmable amount (coring gain border, coring gain data) of

this noise signal is subtracted from the original signal. In DNR

sharpness mode, if the absolute value of the filter output is less

than the programmed threshold, it is assumed to be noise as

before. However, if the level exceeds the threshold, now being

identified as a valid signal, a fraction of the signal (coring gain

border, coring gain data) is added to the original signal to boost

high frequency components and sharpen the video image.

In MPEG systems, it is common to process the video information

in blocks of 8 pixels × 8 pixels for MPEG2 systems or 16 pixels

× 16 pixels for MPEG1 systems (block size control). DNR can

be applied to the resulting block transition areas known to

contain noise. Generally, the block transition area contains two

pixels. It is possible to define this area to contain four pixels

(border area).

Figure 75. Input Signal to ED/HD Adaptive Filter

It is also possible to compensate for variable block positioning

or differences in YCrCb pixel timing with the use of the DNR

block offset.

The digital noise reduction registers are three 8-bit registers.

They are used to control the DNR processing.

DNR MODE

DNR CONTROL

BLOCK SIZE CONTROL

BORDER AREA

BLOCK OFFSET

GAIN

Figure 76. Output Signal from ED/HD Adaptive Filter (Mode A)

CORING GAIN DATA

CORING GAIN BORDER

When the adaptive filter mode is changed to Mode B

(Subaddress 0x35, Bit 6), the output shown in Figure 77

can be obtained.

NOISE

SIGNAL PATH

INPUT FILTER

BLOCK

FILTER

SUBTRACT

OUTPUT

SIGNAL IN

Y DATA

INPUT

< THRESHOLD?

THRESHOLD

RANGE FROM

ORIGINAL SIGNAL

–

FILTER OUTPUT

> THRESHOLD

+

DNR OUT

MAIN SIGNAL PATH

DNR

SHARPNESS

MODE

DNR CONTROL

BLOCK SIZE CONTROL

BORDER AREA

BLOCK OFFSET

GAIN

CORING GAIN DATA

CORING GAIN BORDER

NOISE

SIGNAL PATH

INPUT FILTER

BLOCK

Figure 77. Output Signal from ED/HD Adaptive Filter (Mode B)

FILTER

ADD SIGNAL

ABOVE

THRESHOLD

RANGE FROM

ORIGINAL SIGNAL

OUTPUT

SD DIGITAL NOISE REDUCTION

Subaddress 0xA3 to Subaddress 0xA5

Y DATA

INPUT

> THRESHOLD?

+

FILTER OUTPUT

< THRESHOLD

Digital noise reduction (DNR) is applied to the Y data only.

A filter block selects the high frequency, low amplitude compo-

nents of the incoming signal (DNR input select). The absolute

value of the filter output is compared to a programmable

threshold value (DNR threshold control). There are two DNR

modes available: DNR mode and DNR sharpness mode.

+

DNR OUT

MAIN SIGNAL PATH

Figure 78. SD DNR Block Diagram

Rev. H | Page 62 of 108

Data Sheet

ADV7390/ADV7391/ADV7392/ADV7393

Coring Gain Border—Subaddress 0xA3, Bits[3:0]

Block Size—Subaddress 0xA4, Bit 7

These four bits are assigned to the gain factor applied to border

areas. In DNR mode, the range of gain values is 0 to 1 in

increments of 1/8. This factor is applied to the DNR filter

output that lies below the set threshold range. The result is then

subtracted from the original signal.

This bit is used to select the size of the data blocks to be

processed. Setting the block size control function to Logic 1

defines a 16 pixel × 16 pixel data block, and Logic 0 defines an

8 pixel × 8 pixel data block, where one pixel refers to two clock

cycles at 27 MHz.

In DNR sharpness mode, the range of gain values is 0 to 0.5 in

increments of 1/16. This factor is applied to the DNR filter

output that lies above the threshold range. The result is added to

the original signal.

DNR Input Select—Subaddress 0xA5, Bits[2:0]

These three bits are assigned to select the filter that is applied to

the incoming Y data. The signal that lies in the pass band of the

selected filter is the signal processed by DNR. Figure 81 shows

the filter responses selectable with this control.

Coring Gain Data—Subaddress 0xA3, Bits[7:4]

These four bits are assigned to the gain factor applied to the luma

data inside the MPEG pixel block. In DNR mode, the range of

gain values is 0 to 1 in increments of 1/8. This factor is applied

to the DNR filter output that lies below the set threshold range.

The result is then subtracted from the original signal.

1.0

FILTER D

0.8

FILTER C

0.6

In DNR sharpness mode, the range of gain values is 0 to 0.5 in

increments of 1/16. This factor is applied to the DNR filter

output that lies above the threshold range. The result is added to

the original signal.

0.4

0.2

0

FILTER B

APPLY DATA

APPLY BORDER

CORING GAIN CORING GAIN

FILTER A

O X X X X X X O O X X X X X X O

1

2

3

0

4

5

6

FREQUENCY (MHz)

OFFSET CAUSED

BY VARIATIONS IN

INPUT TIMING

O X X X X X X O O X X X X X X O

Figure 81. SD DNR Input Select

DNR Mode—Subaddress 0xA5, Bit 3

DNR27 TO DNR24 = 0x01 O X X X X X X O O X X X X X X O

This bit controls the DNR mode selected. Logic 0 selects DNR

mode; Logic 1 selects DNR sharpness mode.

Figure 79. SD DNR Offset Control

DNR Threshold—Subaddress 0xA4, Bits[5:0]

DNR works on the principle of defining low amplitude, high

frequency signals as probable noise and subtracting this noise

from the original signal.

These six bits are used to define the threshold value in the range

of 0 to 63. The range is an absolute value.

Border Area—Subaddress 0xA4, Bit 6

In DNR mode, it is possible to subtract a fraction of the signal

that lies below the set threshold, assumed to be noise, from the

original signal. The threshold is set in DNR Register 1.

When this bit is set to Logic 1, the block transition area can be

defined to consist of four pixels. If this bit is set to Logic 0, the

border transition area consists of two pixels, where one pixel

refers to two clock cycles at 27 MHz.

When DNR sharpness mode is enabled, it is possible to add a

fraction of the signal that lies above the set threshold to the

original signal because this data is assumed to be valid data and

not noise. The overall effect is that the signal is boosted (similar

to using the extended SSAF filter).

720 × 485 PIXELS

TWO-PIXEL

BORDER

(NTSC)

DATA

Block Offset Control—Subaddress 0xA5, Bits[7:4]

Four bits are assigned to this control, which allows a shift in the

data block of 15 pixels maximum. The coring gain positions are

fixed. The block offset shifts the data in steps of one pixel such

that the border coring gain factors can be applied at the same

position regardless of variations in input timing of the data.

8 × 8 PIXEL BLOCK

Figure 80. SD DNR Border Area

Rev. H | Page 63 of 108

ADV7390/ADV7391/ADV7392/ADV7393

Data Sheet

At the start of active video, the first three pixels are multiplied

by 1/8, 1/2, and 7/8, respectively. Approaching the end of active

video, the last three pixels are multiplied by 7/8, 1/2, and 1/8,

respectively. All other active video pixels pass through unpro-

cessed.

SD ACTIVE VIDEO EDGE CONTROL

Subaddress 0x82, Bit 7

The ADV739x is able to control fast rising and falling signals at

the start and end of active video to minimize ringing.

When the active video edge control feature is enabled

(Subaddress 0x82, Bit 7 = 1), the first three pixels and the last

three pixels of the active video on the luma channel are scaled

so that maximum transitions on these pixels are not possible.

LUMA CHANNEL WITH

ACTIVE VIDEO EDGE

DISABLED

LUMA CHANNEL WITH

ACTIVE VIDEO EDGE

ENABLED

100 IRE

0 IRE

100 IRE

87.5 IRE

50 IRE

12.5 IRE

0 IRE

Figure 82. Example of Active Video Edge Functionality

VOLTS

0.5

IRE:FLT

100

50

0

F2

L135

–50

2

0

4

6

8

10

12

Figure 83. Example of Video Output with Subaddress 0x82, Bit 7 = 0

VOLTS

IRE:FLT

100

50

0

0.5

0

F2

L135

–50

–2

0

2

4

6

8

10

12

Figure 84. Example of Video Output with Subaddress 0x82, Bit 7 = 1

Rev. H | Page 64 of 108

Data Sheet

ADV7390/ADV7391/ADV7392/ADV7393

EXTERNAL HORIZONTAL AND VERTICAL SYNCHRONIZATION CONTROL

For timing synchronization purposes, the ADV739x is able to accept either EAV/SAV time codes embedded in the input pixel data or

HSYNC

VSYNC

external synchronization signals provided on the

and

pins (see Table 53). It is also possible to output synchronization

HSYNC VSYNC

signals on the

and

pins (see Table 54 to Table 56).

Table 53. Timing Synchronization Signal Input Options

Signal

Condition

SD slave timing (Mode 1, Mode 2, or Mode 3) selected (Subaddress 0x8A[2:0])¹

ED/HD timing synchronization inputs enabled (Subaddress 0x30, Bit 2 = 0)

SD HSYNC In

HSYNC

VSYNC

HSYNC

VSYNC

SD VSYNC/FIELD In

ED/HD HSYNC In

ED/HD VSYNC/FIELD In

¹SD and ED/HD timing synchronization outputs must also be disabled (Subaddress 0x02[7:6] = 00).

Table 54. Timing Synchronization Signal Output Options

Signal

Condition

SD timing synchronization outputs enabled (Subaddress 0x02, Bit 6 = 1)¹

ED/HD timing synchronization outputs enabled (Subaddress 0x02, Bit 7 = 1)²

SD HSYNC Out

HSYNC

VSYNC

HSYNC

VSYNC

SD VSYNC/FIELD Out

ED/HD HSYNC Out

ED/HD VSYNC/FIELD Out

¹ED/HD timing synchronization outputs must also be disabled (Subaddress 0x02, Bit 7 = 0).

²ED/HD timing synchronization inputs must also be disabled; that is, embedded EAV/SAV timing codes must be enabled (Subaddress 0x30, Bit 2 = 1).

1, 2

HSYNC

Table 55.

Output Control

ED/HD Sync

Output Enable

(Subaddress 0x02, (Subaddress 0x02,

Bit 7)

SD Sync

Output Enable

ED/HD HSYNC Control

(Subaddress 0x34,

Bit 1)

ED/HD Input Sync Format

(Subaddress 0x30,

Bit 2)

Signal on HSYNC Pin

Tristate

Bit 6)

Duration

X

0

1

N/A

See the SD Timing

section.

Pipelined SD HSYNC

0

1

X

0

1

X

Pipelined ED/HD HSYNC

As per

HSYNC

timing.

Same as line

blanking interval.

Pipelined ED/HD

based on AV Code H bit

HSYNC

Same as

Pipelined ED/HD

embedded HSYNC.

based on horizontal

counter

1

HSYNC

pulse is aligned with the falling edge of the embedded in the output video.

In all ED/HD standards where there is an

output, the start of the

²X = don’t care.

1, 2

VSYNC

Table 56.

Output Control

ED/HD VSYNC

Control

(Subaddress

0x34, Bit 2)

ED/HD Input

Sync Format

(Subaddress

0x30, Bit 2)

ED/HD Sync

SD Sync

Output Enable

(Subaddress

0x02, Bit 7)

Output Enable

(Subaddress

0x02, Bit 6)

Signal on VSYNC Pin

Video Standard

Duration

x

0

1

x

Tristate

N/A

Interlaced

See the SD Timing

section.

Pipelined SD VSYNC/field

0

1

0

1

x

VSYNC

Pipelined ED/HD

or field signal

As per or

VSYNC

field signal timing.

Field.

All HD interlaced

standards

All ED/HD

progressive

standards

Pipelined field signal

based on AV Code F bit

VSYNC

based

Vertical blanking

interval.

Pipelined

on AV Code V bit

Rev. H | Page 65 of 108

ADV7390/ADV7391/ADV7392/ADV7393

Data Sheet

ED/HD VSYNC

Control

(Subaddress

0x34, Bit 2)

ED/HD Input

Sync Format

(Subaddress

0x30, Bit 2)

ED/HD Sync

Output Enable

(Subaddress

0x02, Bit 7)

SD Sync

Output Enable

(Subaddress

0x02, Bit 6)

Signal on VSYNC Pin

VSYNC

based on the vertical

counter

Video Standard

Duration

X

1

X

All ED/HD standards

except 525p

Aligned with

serration lines.

Pipelined ED/HD

X

1

X

525p

VSYNC

Vertical blanking

interval.

Pipelined ED/HD

based on the vertical

counter

1

VSYNC

pulse is aligned with the falling edge of the embedded in the output video.

In all ED/HD standards where there is a

²X = don’t care.

output, the start of the

LOW POWER MODE

DAC AUTOPOWER-DOWN

Subaddress 0x0D, Bits[2:0]

Subaddress 0x10, Bit 4

For power-sensitive applications, the ADV739x supports an

Analog Devices, Inc., proprietary low power mode of operation.

To use this low power mode, the DACs must be operating in

full-drive mode (R_SET= 510 Ω, R_L= 37.5 Ω). Low power mode is

not available in low-drive mode (R_SET= 4.12 kΩ, R_L= 300 Ω).

Low power mode can be independently enabled or disabled on

each DAC using Subaddress 0x0D, Bits[2:0]. Low power mode

is disabled by default on all DACs.

For power-sensitive applications, a DAC autopower-down

feature can be enabled using Subaddress 0x10, Bit 4. This

feature is available only when the cable detection feature is

enabled.

With this feature enabled, the cable detection circuitry monitors

DAC 1 and/or DAC 2 once per frame and, if they are

unconnected, automatically powers down some or all of the

DACs. Which DAC or DACs are powered down depends on the

selected output configuration. For CVBS/Y-C output configur-

ations, if DAC 1 is unconnected, only DAC 1 powers down. If

DAC 2 is unconnected, DAC 2 and DAC 3 power down.

In low-power mode, DAC current consumption is content

dependent and, on a typical video stream, it can be reduced by

as much as 40%. For applications requiring the highest possible

video performance, low power mode should be disabled.

For YPrPb and RGB output configurations, if DAC 1 is uncon-

nected, all three DACs are powered down. DAC 2 is not monitored

for YPrPb and RGB output configurations.

CABLE DETECTION

Subaddress 0x10, Bits[1:0]

Once per frame, DAC 1 and/or DAC 2 is monitored. If a cable is

detected, the appropriate DAC or DACs remain powered up for

the duration of the frame. If no cable is detected, the appropriate

DAC or DACs power down until the next frame, when the

process is repeated.

The ADV739x includes an Analog Devices proprietary cable

detection feature. The cable detection feature is available on

DAC 1 and DAC 2 when operating in full-drive mode (R_SET

=

510 Ω, R_L= 37.5 Ω, assuming a connected cable). The feature is

not available in low-drive mode (R_SET= 4.12 kΩ, R_L= 300 Ω).

For a DAC to be monitored, the DAC must be powered up in

Subaddress 0x00.

SLEEP MODE

Subaddress 0x00, Bit 0

The cable detection feature can be used with all SD, ED, and

HD video standards. It is available for all output configurations,

that is, CVBS, Y-C, YPrPb, and RGB output configurations.

In sleep mode, most of the digital I/O pins of the ADV739x are

disabled. For inputs, this means that the external data is

ignored, and internally the logic normally driven by a given

input is just tied low or high. This includes CLKIN.

For CVBS/Y-C output configurations, both DAC 1 and DAC 2

are monitored; that is, the CVBS and Y-C luma outputs are

monitored. For YPrPb and RGB output configurations, only

DAC 1 is monitored; that is, the luma or green output is

monitored.

For digital output pins, this means that the pin goes into tristate

(high impedance) mode.

There are some exceptions to allow the user to continue to

2

RESET

communicate with the part via I C: the

SCL pins are kept alive.

, ALSB, SDA and

Once per frame, the ADV739x monitors DAC 1 and/or DAC 2,

updating Subaddress 0x10, Bit 0 and/or Bit 1, respectively. If a

cable is detected on one of the DACs, the relevant bit is set to 0.

If not, the bit is set to 1.

Most of the analogue circuitry is powered down when in sleep

mode. In addition, the cable detect feature no longer works as

the DACs are powered down.

Sleep mode is enabled using Subaddress 0x00, Bit 0.

Rev. H | Page 66 of 108

Data Sheet

ADV7390/ADV7391/ADV7392/ADV7393

RESET

the

pin low long enough to cause a reset to take place.

PIXEL AND CONTROL PORT READBACK

Subaddress 0x13, Subaddress 0x14, Subaddress 0x16

All subsequent resets can be done via software.

SD TELETEXT INSERTION

Subaddress 0xC9 to Subaddress 0xCE

The ADV739x supports the readback of most digital inputs via

the I²C MPU port. This feature is useful for board-level

connectivity testing with upstream devices.

The ADV739x supports the insertion of teletext data, using a

two pin interface, when operating in PAL mode. Teletext

insertion is enabled using Subaddress 0xC9, Bit 0.

HSYNC VSYNC

, and SFL

The pixel port (P[15:0] or P[7:0]),

,

are available for readback via the MPU port. The readback

registers are located at Subaddress 0x13, Subaddress 0x14, and

Subaddress 0x16.

In accordance with the PAL WST teletext standard, teletext data

should be inserted into the ADV739x at a rate of 6.9375 Mbps.

On the ADV7390/ADV7391, the teletext data is inserted on

When using this feature, apply a clock signal to the CLKIN pin

to register the levels applied to the input pins. The SD input

mode (Subaddress 0x01, Bits[6:4] = 000) must be selected when

using this feature.

VSYNC

the

can be inserted on the

Subaddress 0xC9, Bit 2).

pin. On the ADV7392/ADV7393, the teletext data

VSYNC

or P0 pin (selectable through

RESET MECHANISMS

Subaddress 0x17, Bit 1

When teletext insertion is enabled, a teletext request signal is

output from the ADV739x to indicate when teletext data should

be inserted. The teletext request signal is output on the SFL pin.

The position (relative to the teletext data) and width of the

request signal are configurable using Subaddress 0xCA. The

request signal can operate in either a line or bit mode. The

request signal mode is controlled using Subaddress 0xC9, Bit 1.

A hardware reset is activated with a high-to-low transition on

RESET

the

pin in accordance with the timing specifications.

This resets all registers to their default values. After a hardware

reset, the MPU port is configured for I²C operation. For correct

device operation, a hardware reset is necessary after power-up.

To account for the noninteger relationship between the teletext

insertion rate (6.9375 Mbps) and the pixel clock (27 MHz),

a teletext insertion protocol is implemented in the ADV739x.

At a rate of 6.9375 Mbps, the time taken for the insertion of

37 teletext bits equates to 144 pixel clock cycles (at 27 MHz).

For every 37 teletext bits inserted into the ADV739x, the 10^th,

19^th, 28^th, and 37^thbits are carried for three pixel clock cycles, and

the remainder are carried for four pixel clock cycles (totaling

144 pixel clock cycles). The teletext insertion protocol repeats

every 37 teletext bits or 144 pixel clock cycles until all 360 teletext

bits are inserted.

The ADV739x also has a software reset accessible via the I²C

MPU port. A software reset is activated by writing a 1 to

Subaddress 0x17, Bit 1. This resets all registers to their default

values. This bit is self-clearing; that is, after a 1 has been written

to the bit, the bit automatically returns to 0.

A hardware reset is necessary after power-up for correct device

operation. If no hardware reset functionality is required by the

RESET

application, the

pin can be connected to an RC network

to provide the hardware reset necessary after power-up. After

power-up, the time constant of the RC network holds

45 BYTES (360 BITS) – PAL

ADDRESS AND DATA

TELETEXT VBI LINE

RUN-IN CLOCK

Figure 85. Teletext VBI Line

Rev. H | Page 67 of 108

ADV7390/ADV7391/ADV7392/ADV7393

Data Sheet

t_SYNTTXOUT

CVBS/Y

t_PD

HSYNC

10.2µs

TTX

DATA

TTX

DEL

TTX

REQ

PROGRAMMABLE PULSE EDGES

TTX

ST

t_SYNTTXOUT= 10.2µs.

t_PD= PIPELINE DELAY THROUGH ADV739x.

TTX

DEL

= TTX

REQ

TO TTX

DATA

(PROGRAMMABLE RANGE = 4 BITS [0 TO 15 PIXEL CLOCK CYCLES]).

Figure 86. Teletext Functionality Diagram

Rev. H | Page 68 of 108

Data Sheet

ADV7390/ADV7391/ADV7392/ADV7393

PRINTED CIRCUIT BOARD LAYOUT AND DESIGN

UNUSED PINS

Table 57. ADV739x Output Rates

HSYNC

VSYNC

pins are not used, they should be tied

Input Mode

(Subaddress 0x01,

Bits[6:4])

If the

and

to V_{DD_IO}through a pull-up resistor (10 kΩ or 4.7 kΩ). Any

other unused digital inputs should be tied to ground. Unused

digital output pins should be left floating. DAC outputs can

either be left floating or connected to GND. Disabling these

outputs is recommended.

Oversampling Output Rate (MHz)

SD

Off

On

Off

On

Off

On

27

(2×)

(8×)

(16×)

(1×)

(4×)

(8×)

(1×)

(2×)

(4×)

108

216

27

108

216

74.25

148.5

297

ED

DAC CONFIGURATIONS

The ADV739x contains three DACs. All three DACs can be

configured to operate in full-drive mode. Full-drive mode is

defined as 34.7 mA full-scale current into a 37.5 Ω load, R_L.

Full drive is the recommended mode of operation for the DACs.

HD

Alternatively, all three DACs can be configured to operate in low-

drive mode. Low-drive mode is defined as 4.33 mA full-scale

current into a 300 Ω load, R_L.

Table 58. Output Filter Requirements

Cutoff

Attenuation

–50 dB at

(MHz)

Frequency

Application Oversampling (MHz)

The ADV739x contains an R_SETpin. A resistor connected between

the R_SETpin and AGND is used to control the full-scale output

current and, therefore, the output voltage levels of DAC 1, DAC 2,

and DAC 3. For full-drive operation, R_SETmust have a value of

510 Ω and RL must have a value of 37.5 Ω. For low-drive opera-

tion, R_SETmust have a value of 4.12 kΩ, and R_Lmust have a value

of 300 Ω. The resistor connected to the R_SETpin should have a

1% tolerance.

SD

ED

HD

2×

8×

16×

1×

4×

8×

1×

2×

4×

> 6.5

> 12.5

> 30

20.5

101.5

209.5

14.5

95.5

203.5

44.25

118.5

267

> 30

The ADV739x contains a compensation pin, COMP. A 2.2 nF

compensation capacitor should be connected from the COMP

pin to V_AA.

10µH

DAC

OUTPUT

3

4

75Ω

VIDEO OUTPUT BUFFER AND OPTIONAL

OUTPUT FILTER

BNC

OUTPUT

600Ω

22pF

600Ω

1

An output buffer is necessary on any DAC that operates in low-

drive mode (R_SET= 4.12 kΩ, R_L= 300 Ω). Analog Devices

produces a range of op amps suitable for this application, for

example, the AD8061. For more information about line driver

buffering circuits, see the relevant op amp data sheet.

560Ω

Figure 87. Example of Output Filter for SD, 16× Oversampling

4.7µH

DAC

OUTPUT

3

An optional reconstruction (anti-imaging) low-pass filter (LPF)

may be required on the ADV739x DAC outputs. The filter

specifications vary with the application. The use of 16× (SD),

8× (ED), or 4× (HD) oversampling can remove the requirement

for a reconstruction filter altogether.

75Ω

BNC

OUTPUT

6.8pF

600Ω

1

600Ω

4

560Ω

For applications requiring an output buffer and reconstruction

filter, the ADA4430-1 and ADA4411-3 integrated video filter

buffers should be considered.

Figure 88. Example of Output Filter for ED, 8× Oversampling

DAC

OUTPUT

3

390nH

75Ω

BNC

OUTPUT

300Ω

3

1

33pF

75Ω

1

4

500Ω

Figure 89. Example of Output Filter for HD, 4× Oversampling

Rev. H | Page 69 of 108

ADV7390/ADV7391/ADV7392/ADV7393

Data Sheet

CIRCUIT FREQUENCY RESPONSE

0

–10

–20

–30

–40

–50

–60

–70

–80

PRINTED CIRCUIT BOARD (PCB) LAYOUT

24n

21n

18n

15n

12n

9n

–30

The ADV739x is a highly integrated circuit containing both

precision analog and high speed digital circuitry. It is designed

to minimize interference effects on the integrity of the analog

circuitry by the high speed digital circuitry. It is imperative that

these same design and layout techniques be applied to the

system-level design so that optimal performance is achieved.

MAGNITUDE (dB)

–60

–90

PHASE (Degrees)

–120

–150

–180

–210

–240

The layout should be optimized for lowest noise on the

ADV739x power and ground planes by shielding the digital

inputs and providing good power supply decoupling.

GROUP DELAY (Seconds)

6n

3n

0

It is recommended to use a 4-layer printed circuit board with

ground and power planes separating the signal trace layer and

the solder side layer.

1M

10M

100M

1G

FREQUENCY (Hz)

Figure 90. Output Filter Plot for SD, 16× Oversampling

Component Placement

Component placement should be carefully considered to

separate noisy circuits, such as clock signals and high speed

digital circuitry, from analog circuitry.

CIRCUIT FREQUENCY RESPONSE

0

480

18n

16n

–10

400

320

240

160

80

MAGNITUDE (dB)

The external loop filter components and components connected

to the COMP and R_SETpins should be placed as close as possible

to, and on the same side of the PCB as, the ADV739x. Adding

vias to the PCB to get the components closer to the ADV739x is

not recommended.

–20

–30

–40

–50

–60

–70

–80

–90

14n

PHASE

(Degrees)

12n

10n

8n

GROUP DELAY (Seconds)

It is recommended that the ADV739x be placed as close as

possible to the output connector, with the DAC output traces as

short as possible.

0

6n

–80

–160

–240

4n

The termination resistors on the DAC output traces should be

placed as close as possible to and on the same side of the PCB as

the ADV739x. The termination resistors should overlay the

PCB ground plane.

2n

0

1M

10M

100M

1G

FREQUENCY (Hz)

Figure 91. Output Filter Plot for ED, 8× Oversampling

External filter and buffer components connected to the DAC

outputs should be placed as close as possible to the ADV739x to

minimize the possibility of noise pickup from neighboring

circuitry and to minimize the effect of trace capacitance on

output bandwidth. This is particularly important when

operating in low-drive mode (R_SET= 4.12 kΩ, R_L= 300 Ω).

CIRCUIT FREQUENCY RESPONSE

0

200

120

40

PHASE

(Degrees)

MAGNITUDE (dB)

–10

–20

–30

–40

–50

GROUP DELAY (Seconds)

Power Supplies

It is recommended that a separate regulated supply be provided

for each power domain (V_AA, V_DD, V_{DD_IO}, and PV_DD). For

optimal performance, linear regulators rather than switch mode

regulators should be used. If switch mode regulators must be

used, care must be taken with regard to the quality of the output

voltage in terms of ripple and noise. This is particularly true for

the V_AAand PV_DDpower domains. Each power supply should be

individually connected to the system power supply at a single

point through a suitable filtering device, such as a ferrite bead.

–40

–120

–200

1

10

100

FREQUENCY (MHz)

Figure 92. Output Filter Plot for HD, 4× Oversampling

Rev. H | Page 70 of 108

Data Sheet

ADV7390/ADV7391/ADV7392/ADV7393

Power Supply Decoupling

ADDITIONAL LAYOUT CONSIDERATIONS FOR THE

WLCSP PACKAGE

It is recommended that each power supply pin be decoupled

with 10 nF and 0.1 µF ceramic capacitors. The V_AA, PV_DD,

Due to the high pad density and 0.5 mm pitch of the WLCSP, it

is not recommended that connections to inner bumps be routed

on the top PCB layer only.

V

_{DD_IO}, and both V_DDpins should be individually decoupled to

ground. The decoupling capacitors should be placed as close as

possible to the ADV739x with the capacitor leads kept as short

as possible to minimize lead inductance.

The traces (track and space) must fit within the limits of the

solder mask openings. Routing all traces on the top surface

layer of the board, while possible, is usually not a feasible

solution due to the limitations of the geometries imposed by

the board fabrication technology. Given a pitch of 0.5 mm with

a typical solder mask opening diameter of 0.35 mm, there is only

a 0.15 mm distance between the solder mask openings.

A 1 µF tantalum capacitor is recommended across the V_AA

supply in addition to the 10 nF and 0.1 µF ceramic capacitors.

Power Supply Sequencing

The ADV739x is robust to all power supply sequencing combin-

ations. Any sequence can be used. However, all power supplies

should settle to their nominal voltages within one second.

An alternative to routing on the top surface is to route out on

buried layers. To achieve this, the pads are connected to the

lower layers using microvias. See the AN-617 Application Note,

MicroCSP Wafer Level Chip Scale Package for additional details

about the board layout for the WLCSP package.

Digital Signal Interconnect

The digital signal traces should be isolated as much as possible

from the analog outputs and other analog circuitry. Digital

signal traces should not overlay the V_AAor PV_DDpower plane.

Due to the high clock rates used, avoid long clock traces to the

ADV739x to minimize noise pickup.

Any pull-up termination resistors for the digital inputs should

be connected to the V_{DD_IO}power supply.

Analog Signal Interconnect

DAC output traces should be treated as transmission lines with

appropriate measures taken to ensure optimal performance (for

example, impedance matched traces). The DAC output traces

should be kept as short as possible. The termination resistors on

the DAC output traces should be placed as close as possible to,

and on the same side of the PCB as, the ADV739x.

To avoid crosstalk between the DAC outputs, it is recommended

that as much space as possible be left between the traces

connected to the DAC output pins. Adding ground traces

between the DAC output traces is also recommended.

Rev. H | Page 71 of 108

ADV7390/ADV7391/ADV7392/ADV7393

Data Sheet

TYPICAL APPLICATIONS CIRCUITS

FERRITE BEAD

NOTES

1. FOR OPTIMUM PERFORMANCE, EXTERNAL COMPONENTS CONNECTED

TO THE COMP, R AND DAC OUTPUT PINS SHOULD BE LOCATED

V

DD_IO

V

POWER

DD_IO

33µF

10µF

0.1µF

0.01µF

SUPPLY

DECOUPLING

SET

GND_IO

GND_IO GND_IO

CLOSE TO, AND ON THE SAME SIDE OF THE PCB AS, THE ADV739x.

FERRITE BEAD

2

PV

DD

2. THE I C DEVICE ADDRESS IS CONFIGURABLE USING THE ALSB PIN:

PV POWER

DD

SUPPLY

DECOUPLING

33µF

10µF

0.1µF

0.01µF

PGND

2

ALSB = 0, I C DEVICE ADDRESS = 0xD4 (ADV7390/ADV7392) OR

0x54 (ADV7391/ADV7393)

PGND

2

FERRITE BEAD

ALSB = 1, I C DEVICE ADDRESS = 0xD6 (ADV7390/ADV7392) OR

V

AA

DD

0x56 (ADV7391/ADV7393)

V

POWER

AA

33µF

10µF

0.1µF

0.01µF

AGND

1µF

SUPPLY

DECOUPLING

3. THE RESISTOR CONNECTED TO THE R

TOLERANCE.

PIN SHOULD HAVE A 1%

SET

AGND

FERRITE BEAD

AGND

4. THE RECOMMENDED MODE OF OPERATION FOR THE DACs IS FULL-

V

POWER SUPPLY

DECOUPLING FOR

EACHPOWER PIN

DD

33µF

10µF

0.1µF

0.01µF

DGND

DRIVE (R

= 510Ω, R = 37.5Ω).

L

SET

DGND

V

AA

2.2nF

P0

P1

P2

P3

P4

P5

P6

P7

COMP

R

SET

ADV739x

510Ω

AGND

PIXEL PORT INPUTS

DAC1 TO DAC3 FULL DRIVE OPTION

(RECOMMENDED)

P8

P9

DAC1 TO DAC3 LOW DRIVE OPTION

OPTIONAL LPF

P10

P11

P12

P13

P14

P15

DAC 1

DAC 2

DAC 3

DAC 1

DAC 2

DAC 3

ADV7392/

ADV7393

ONLY

R

SET

4.12kΩ

OPTIONAL LPF

75Ω

AGND

ADA4411-3

AGND AGND AGND

75Ω

DAC 1

DAC 2

DAC 3

HSYNC

VSYNC

CONTROL

INPUTS/OUTPUTS

LPF

300Ω

AGND

CLKIN

CLOCK INPUT

I2C PORT

ADA4411-3

SDA

SCL

75Ω

DAC 2

LPF

TIE EITHER LOW

OR HIGH

ALSB

300Ω

AGND

RESET

EXTERNAL LOOP FILTER

ADA4411-3

PV

DD

12nF

75Ω

EXT_LF

DAC 3

LPF

150nF

170Ω

300Ω

AGND

LOOP FILTER COMPONENTS

SHOULD BE LOCATED

CLOSE TO THE EXT_LF

PIN AND ON THE

SAME SIDE OF THE PCB

AS THE ADV739x.

AGND PGND DGND DGND GND_IO

Figure 93. ADV739x (LFCSP) Typical Applications Circuit

Rev. H | Page 72 of 108

Data Sheet

ADV7390/ADV7391/ADV7392/ADV7393

FERRITE BEAD

NOTES

V

DD_IO

V

POWER

DD_IO

1. FOR OPTIMUM PERFORMANCE, EXTERNAL COMPONENTS CONNECTED

TO THE COMP, R

CLOSE TO, AND ON THE SAME SIDE OF THE PCB AS, THE ADV7390.

33µF

10µF

0.1µF

0.01µF

SUPPLY

DECOUPLING

AND DAC OUTPUT PINS SHOULD BE LOCATED

SET

GND_IO

GND_IO GND_IO

FERRITE BEAD

2

PV

DD

2. THE I C DEVICE ADDRESS IS CONFIGURABLE USING THE ALSB PIN:

PV POWER

DD

SUPPLY

DECOUPLING

33µF

10µF

0.1µF

0.01µF

PGND

2

ALSB = 0, I C DEVICE ADDRESS = 0xD4

PGND

2

FERRITE BEAD

ALSB = 1, I C DEVICE ADDRESS = 0xD6

V

AA

DD

V

POWER

AA

33µF

10µF

0.1µF

0.01µF

AGND

1µF

3. THE RESISTOR CONNECTED TO THE R

SET

TOLERANCE.

PIN SHOULD HAVE A 1%

SUPPLY

DECOUPLING

AGND

FERRITE BEAD

AGND

4. THE RECOMMENDED MODE OF OPERATION FOR THE DACs IS FULL-

DRIVE (R = 510Ω, = 37.5Ω).

R

SET

L

V

POWER SUPPLY

DECOUPLING FOR

EACH POWER PIN

DD

33µF

10µF

0.1µF

0.01µF

DGND

V

AA

2.2nF

P0

P1

P2

P3

P4

P5

P6

P7

COMP

R

SET

PIXEL PORT INPUTS

510Ω

ADV7390BCBZ

AGND

TIE EITHER

ALSB

DAC 1

LOW OR HIGH

CONTROL

INPUTS/OUTPUTS

HSYNC

VSYNC

DAC FULL DRIVE OPTION

(RECOMMENDED)

CLOCK INPUT

I2C PORT

CLKIN

OPTIONAL LPF

VIDEO

75Ω

SDA

SCL

DAC LOW DRIVE OPTION

RESET

R

SET

EXTERNAL LOOP FILTER

PV

4.12kΩ

DD

AGND

12nF

ADA4411-3

EXT_LF

150nF

170Ω

75Ω

DAC

LPF

VIDEO

LOOP FILTER COMPONENTS

SHOULD BE LOCATED

CLOSE TO THE EXT_LF

PIN AND ON THE

SAME SIDE OF THE PCB

AS THE ADV7390.

AGND PGND DGND DGND GND_IO

300Ω

AGND

Figure 94. ADV7390BCBZ-A (WLCSP) Typical Applications Circuit

Rev. H | Page 73 of 108

ADV7390/ADV7391/ADV7392/ADV7393

Data Sheet

COPY GENERATION MANAGEMENT SYSTEM

SD CGMS

Subaddress 0x99 to Subaddress 0x9B

When HD CGMS is enabled (Subaddress 0x32, Bit 6 = 1), 1080i

CGMS data is applied to Line 19 and Line 582 of the luminance

vertical blanking interval.

The ADV739x supports a copy generation management system

(CGMS) that conforms to the EIAJ CPR-1204 and ARIB TR-B15

standards. CGMS data is transmitted on Line 20 of odd fields and

Line 283 of even fields. Subaddress 0x99, Bits[6:5] control

whether CGMS data is output on odd or even fields or both.

The HD CGMS data registers are at Subaddress 0x41, Subad-

ress 0x42, and Subaddress 0x43.

The ADV739x also supports CGMS Type B packets in HD

mode (720p and 1080i) in accordance with CEA-805-A.

SD CGMS data can be transmitted only when the ADV739x is

configured in NTSC mode. The CGMS data is 20 bits long. The

CGMS data is preceded by a reference pulse of the same

amplitude and duration as a CGMS bit (see Figure 95).

When HD CGMS Type B is enabled (Subaddress 0x5E, Bit 0 = 1),

720p CGMS data is applied to Line 23 of the luminance vertical

blanking interval.

When HD CGMS Type B is enabled (Subaddress 0x5E, Bit 0 = 1),

1080i CGMS data is applied to Line 18 and Line 581 of the

luminance vertical blanking interval.

ED CGMS

Subaddress 0x41 to Subaddress 0x43;

Subaddress 0x5E to Subaddress 0x6E

The HD CGMS Type B data registers are at Subaddress 0x5E to

Subaddress 0x6E.

525p Mode

The ADV739x supports a copy generation management system

(CGMS) in 525p mode in accordance with EIAJ CPR-1204-1.

CGMS CRC FUNCTIONALITY

If SD CGMS CRC (Subaddress 0x99, Bit 4) or ED/HD CGMS

CRC (Subaddress 0x32, Bit 7) is enabled, the upper six CGMS

data bits (C19 to C14) that comprise the 6-bit CRC check

sequence are automatically calculated on the ADV739x. This

calculation is based on the lower 14 bits (C13 to C0) of the data

in the CGMS data registers, and the result is output with the

remaining 14 bits to form the complete 20 bits of the CGMS

data. The calculation of the CRC sequence is based on the

polynomial x⁶+ x + 1 with a preset value of 111111.

When ED CGMS is enabled (Subaddress 0x32, Bit 6 = 1), 525p

CGMS data is inserted on Line 41. The 525p CGMS data

registers are at Subaddress 0x41, Subaddress 0x42, and

Subaddress 0x43.

The ADV739x also supports CGMS Type B packets in 525p

mode in accordance with CEA-805-A.

When ED CGMS Type B is enabled (Subaddress 0x5E, Bit 0 = 1),

525p CGMS Type B data is inserted on Line 40. The 525p CGMS

Type B data registers are at Subaddress 0x5E to Subaddress 0x6E.

If SD CGMS CRC or ED/HD CGMS CRC is disabled, all 20 bits

(C19 to C0) are output directly from the CGMS registers (CRC

must be calculated by the user manually).

625p Mode

The ADV739x supports a copy generation management system

(CGMS) in 625p mode in accordance with IEC 62375 (2004).

If ED/HD CGMS Type B CRC (Subaddress 0x5E, Bit 1) is

enabled, the upper six CGMS Type B data bits (P122 to P127)

that comprise the 6-bit CRC check sequence are automatically

calculated on the ADV739x. This calculation is based on the

lower 128 bits (H0 to H5 and P0 to P121) of the data in the

CGMS Type B data registers. The result is output with the

remaining 128 bits to form the complete 134 bits of the CGMS

Type B data. The calculation of the CRC sequence is based on

the polynomial x⁶+ x + 1 with a preset value of 111111.

When ED CGMS is enabled (Subaddress 0x32, Bit 6 = 1), 625p

CGMS data is inserted on Line 43. The 625p CGMS data

registers are at Subaddress 0x42 and Subaddress 0x43.

HD CGMS

Subaddress 0x41 to Subaddress 0x43;

Subaddress 0x5E to Subaddress 0x6E

The ADV739x supports a copy generation management system

(CGMS) in HD mode (720p and 1080i) in accordance with

EIAJ CPR-1204-2.

If ED/HD CGMS Type B CRC is disabled, all 134 bits (H0 to H5

and P0 to P127) are output directly from the CGMS Type B

registers (CRC must be calculated by the user manually).

When HD CGMS is enabled (Subaddress 0x32, Bit 6 = 1), 720p

CGMS data is applied to Line 24 of the luminance vertical

blanking interval.

Rev. H | Page 74 of 108

Data Sheet

ADV7390/ADV7391/ADV7392/ADV7393

+100 IRE

CRC SEQUENCE

REF

+70 IRE

C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19

0 IRE

–40 IRE

49.1µs ± 0.5µs

11.2µs

2.235µs ± 20ns

Figure 95. Standard Definition CGMS Waveform

CRC SEQUENCE

+700mV

REF

BIT 1 BIT 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BIT 20

C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19

70% ± 10%

0mV

–300mV

21.2µs ± 0.22µs

22T

5.8µs ± 0.15µs

6T

T = 1/(f_H× 33) = 963ns

f_H= HORIZONTAL SCAN FREQUENCY

T ± 30ns

Figure 96. Enhanced Definition (525p) CGMS Waveform

R = RUN-IN

S = START CODE

PEAK WHITE

C0

LSB

C13

C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12

R

S

500mV ± 25mV

SYNC LEVEL

MSB

13.7µs

5.5µs ± 0.125µs

Figure 97. Enhanced Definition (625p) CGMS Waveform

CRC SEQUENCE

+700mV

REF

BIT 1 BIT 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BIT 20

70% ± 10%

C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19

0mV

T ± 30ns

–300mV

17.2µs ± 160ns

4T

22T

3.128µs ± 90ns

T = 1/(f_H× 1650/58) = 781.93ns

f_H= HORIZONTAL SCAN FREQUENCY

1H

Figure 98. High Definition (720p) CGMS Waveform

Rev. H | Page 75 of 108

ADV7390/ADV7391/ADV7392/ADV7393

Data Sheet

CRC SEQUENCE

+700mV

REF

BIT 1 BIT 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BIT 20

C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19

70% ± 10%

0mV

T ± 30ns

–300mV

22.84µs ± 210ns

22T

4T

4.15µs ± 60ns

T = 1/(f × 2200/77) = 1.038µs

H

f

= HORIZONTAL SCAN FREQUENCY

H

1H

Figure 99. High Definition (1080i) CGMS Waveform

CRC SEQUENCE

BIT 134

+700mV

START

BIT 1 BIT 2

70% ± 10%

.

0mV

–300mV

NOTES

1. PLEASE REFER TO THE CEA-805-A SPECIFICATION FOR TIMING INFORMATION.

Figure 100. Enhanced Definition (525p) CGMS Type B Waveform

CRC SEQUENCE

BIT 134

+700mV

START

BIT 1 BIT 2

70% ±10%

.

0mV

–300mV

NOTES

1. PLEASE REFER TO THE CEA-805-A SPECIFICATION FOR TIMING INFORMATION.

Figure 101. High Definition (720p and 1080i) CGMS Type B Waveform

Rev. H | Page 76 of 108

Data Sheet

ADV7390/ADV7391/ADV7392/ADV7393

SD WIDE SCREEN SIGNALING

Figure 102). The latter portion of Line 23 (after 42.5 µs from the

Subaddress 0x99, Subaddress 0x9A, Subaddress 0x9B

HSYNC

falling edge of

) is available for the insertion of video.

The ADV739x supports wide screen signaling (WSS) con-

forming to the ETSI 300 294 standard. WSS data is transmitted

on Line 23. WSS data can be transmitted only when the device

is configured in PAL mode. The WSS data is 14 bits long. The

function of each of these bits is shown in Table 59. The WSS

data is preceded by a run-in sequence and a start code (see

WSS data transmission on Line 23 can be enabled using

Subaddress 0x99, Bit 7. It is possible to blank the WSS portion

of Line 23 with Subaddress 0xA1, Bit 7.

Table 59. Function of WSS Bits

Bit Number

Bit Description

13 12 11 10

9

8

7

6

5

4

3

1

0

1

0

1

0

2

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Setting

Aspect Ratio, Format, Position

4:3, full format, N/A

14:9, letterbox, center

14:9, letterbox, top

16:9, letterbox, center

16:9, letterbox, top

>16:9, letterbox, center

14:9, full format, center

16:0, N/A, N/A

Mode

0

1

Camera mode

Film mode

Color Encoding

Helper Signals

0

1

Normal PAL

Motion Adaptive ColorPlus

Not present

0

1

Present

Reserved

0

N/A

Teletext Subtitles

0

1

No

Yes

Open Subtitles

0

1

0

1

0

1

No

Subtitles in active image area

Subtitles out of active image area

Reserved

Surround Sound

Copyright

0

1

No

Yes

0

1

No copyright asserted or unknown

Copyright asserted

Copying not restricted

Copying restricted

Copy Protection

0

1

500mV

RUN-IN

SEQUENCE

START

CODE

ACTIVE

VIDEO

W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13

11.0µs

38.4µs

42.5µs

Figure 102. WSS Waveform Diagram

Rev. H | Page 77 of 108

ADV7390/ADV7391/ADV7392/ADV7393

Data Sheet

SD CLOSED CAPTIONING

All pixels inputs are ignored on Line 21 and Line 284 if closed

captioning is enabled.

Subaddress 0x91 to Subaddress 0x94

The ADV739x supports closed captioning conforming to the

standard television synchronizing waveform for color trans-

mission. When enabled, closed captioning is transmitted during

the blanked active line time of Line 21 of the odd fields and

Line 284 of the even fields. Closed captioning can be enabled

using Subaddress 0x83, Bits[6:5].

The FCC Code of Federal Regulations (CFR) Title 47 Section

15.119 and EIA-608 describe the closed captioning information

for Line 21 and Line 284.

The ADV739x uses a single buffering method. This means that

the closed captioning buffer is only 1-byte deep. Therefore,

there is no frame delay in outputting the closed captioning data,

unlike other 2-byte deep buffering systems. The data must be

loaded one line before it is output on Line 21 and Line 284. A

Closed captioning consists of a seven-cycle sinusoidal burst that

is frequency- and phase-locked to the caption data. After the

clock run-in signal, the blanking level is held for two data bits

and is followed by a Logic 1 start bit. Sixteen bits of data follow

the start bit. The data consists of two 8-bit bytes (seven data bits

and one odd parity bit per byte). The data for these bytes is

stored in SD closed captioning registers (Subaddress 0x93 to

Subaddress 0x94).

VSYNC

typical implementation of this method is to use

to

interrupt a microprocessor, which in turn loads the new data

(two bytes) in every field. If no new data is required for

transmission, 0s must be inserted in both data registers; this is

called nulling. It is also important to load control codes, all of

which are double bytes, on Line 21. Otherwise, a TV does not

recognize them. If there is a message such as “Hello World” that

has an odd number of characters, it is important to add a blank

character at the end to make sure that the end-of-caption,

2-byte control code lands in the same field.

The ADV739x also supports the extended closed captioning

operation, which is active during even fields and encoded on

Line 284. The data for this operation is stored in SD closed

captioning registers (Subaddress 0x91 to Subaddress 0x92).

The ADV739x automatically generates all clock run-in signals

and timing that support closed captioning on Line 21 and Line 284.

10.5 ± 0.25µs

12.91µs

7 CYCLES OF

0.5035MHz

CLOCK RUN-IN

TWO 7-BIT + PARITY

ASCII CHARACTERS

(DATA)

P

A

R

I

T

Y

P

A

R

I

T

Y

S

T

A

R

T

D0 TO D6

BYTE 1

50 IRE

40 IRE

BYTE 0

REFERENCE COLOR BURST

(9 CYCLES)

FREQUENCY = F = 3.579545MHz

SC

AMPLITUDE = 40 IRE

10.003µs

27.382µs

33.764µs

Figure 103. SD Closed Captioning Waveform, NTSC

Rev. H | Page 78 of 108

Data Sheet

ADV7390/ADV7391/ADV7392/ADV7393

INTERNAL TEST PATTERN GENERATION

SD TEST PATTERNS

ED/HD TEST PATTERNS

The ADV739x is able to internally generate ED/HD color bar,

black bar, and hatch test patterns. For ED test patterns, a 27 MHz

clock signal must be applied to the CLKIN pin. For HD test

patterns, a 74.25 MHz clock signal must be applied to the

CLKIN pin.

The ADV739x is able to internally generate SD color bar and

black bar test patterns. For this function, a 27 MHz clock signal

must be applied to the CLKIN pin.

The register settings in Table 60 are used to generate an SD NTSC

75% color bar test pattern. All other registers are set as normal/

default. Component YPrPb output is available on DAC 1 to

DAC 3. On power-up, the subcarrier frequency registers default

to the appropriate values for NTSC.

The register settings in Table 62 are used to generate an ED

525p hatch test pattern. All other registers are set as normal/

default. Component YPrPb output is available on DAC 1 to

DAC 3. For component RGB output rather than YPrPb output,

0 should be written to Subaddress 0x02, Bit 5.

Table 60. SD NTSC Color Bar Test Pattern Register Writes

Subaddress

Setting

Table 62. ED 525p Hatch Test Pattern Register Writes

0x00

0x82

0x84

0x1C

0xC9

0x40

Subaddress

Setting

0x00

0x1C

0x01

0x10

For CVBS and S-Video (Y/C) output, 0xCB instead of 0xC9

should be written to Subaddress 0x82.

0x31

0x05

To generate an ED 525p black bar test pattern, the settings

shown in Table 62 should be used with an additional write of

0x24 to Subaddress 0x02.

For component RGB output rather than YPrPb output, 0 should

be written to Subaddress 0x02, Bit 5.

To generate an SD NTSC black bar test pattern, the settings

shown in Table 60 should be used with an additional write of

0x24 to Subaddress 0x02.

To generate an ED 525p flat field test pattern, the settings

shown in Table 62 should be used, except that 0x0D should be

written to Subaddress 0x31.

For PAL output of either test pattern, the same settings are used

except that Subaddress 0x80 is programmed to 0x11, and the

subcarrier frequency (F_SC) registers are programmed as shown

in Table 61.

The Y, Cr, and Cb levels for the hatch and flat field test patterns

can be controlled using Subaddress 0x36, Subaddress 0x37, and

Subaddress 0x38, respectively.

For ED/HD standards other than 525p, the settings shown in

Table 62 (and subsequent comments) are used, except that

Subaddress 0x30, Bits[7:3] are updated as appropriate.

Table 61. PAL F_SCRegister Writes

Subaddress

Description

Setting

0xCB

0x8A

0x8C

0x8D

F_SC0

F_SC1

0x8E

F_SC2

0x09

0x8F

F_SC3

0x2A

Note that, when programming the F_SCregisters, the user must

write the values in the sequence F_SC0, F_SC1, F_SC2, F_SC3. The full

F

_SCvalue to be written is only accepted after the F_SC3 write is

complete.

Rev. H | Page 79 of 108

ADV7390/ADV7391/ADV7392/ADV7393

Data Sheet

SD TIMING

Mode 0 (CCIR-656)—Slave Option (Subaddress 0x8A = X X X X X 0 0 0)

The ADV739x is controlled by the SAV (start of active video) and EAV (end of active video) time codes embedded in the pixel data. All

timing information is transmitted using a 4-byte synchronization pattern. A synchronization pattern is sent immediately before and after

VSYNC

HSYNC

each line during active picture and retrace. If the

mode.

and

pins are not used, they should be tied to V_{DD_IO}when using this

ANALOG

VIDEO

EAV CODE

SAV CODE

C

b

C

r

8

0

F

A

B

A

B

A

B

8

0

C

b

C

r

F

0

X

Y

1

0

8

0

1

0

8

0

1

0

1

0

F

0

X

Y

C

b

C

r

Y

INPUT PIXELS

ANCILLARY DATA

(HANC)

4 CLOCK

1440 CLOCK

268 CLOCK

NTSC/PAL M SYSTEM

(525 LINES/60Hz)

280 CLOCK

PAL SYSTEM

(625 LINES/50Hz)

START OF ACTIVE

VIDEO LINE

END OF ACTIVE

VIDEO LINE

Figure 104. SD Timing Mode 0, Slave Option

Mode 0 (CCIR-656)—Master Option (Subaddress 0x8A = X X X X X 0 0 1)

The ADV739x generates H and F signals required for the SAV and EAV time codes in the CCIR-656 standard. The H bit is output

HSYNC

VSYNC

.

on

and the F bit is output on

DISPLAY

VERTICAL BLANK

4

522

523

524

525

1

2

3

5

6

7

8

10

11

20

21

22

9

H

F

ODD FIELD

EVEN FIELD

DISPLAY

VERTICAL BLANK

283

285

284

260

261

262

263

264

265

266

267

268

269

270

271

272

273

274

H

F

ODD FIELD

EVEN FIELD

Figure 105. SD Timing Mode 0, Master Option, NTSC

Rev. H | Page 80 of 108

Data Sheet

ADV7390/ADV7391/ADV7392/ADV7393

DISPLAY

VERTICAL BLANK

622

623

624

625

4

22

23

1

2

3

5

6

7

21

H

F

ODD FIELD

EVEN FIELD

DISPLAY

VERTICAL BLANK

318

334

335

336

309

310

311

312

313

314

315

316

317

319

320

H

F

ODD FIELD

EVEN FIELD

Figure 106. SD Timing Mode 0, Master Option, PAL

ANALOG

VIDEO

H

F

Figure 107. SD Timing Mode 0, Master Option, Data Transitions

Mode 1—Slave Option (Subaddress 0x8A = X X X X X 0 1 0)

HSYNC

In this mode, the ADV739x accepts horizontal synchronization and odd/even field signals. When

is low, a transition of the field

HSYNC

VSYNC

and pins, respectively.

input indicates a new frame, that is, vertical retrace.

and FIELD are input on the

DISPLAY

VERTICAL BLANK

522

523

524

525

20

21

22

3

4

5

7

9

10

11

1

2

6

8

HSYNC

FIELD

ODD FIELD

EVEN FIELD

DISPLAY

VERTICAL BLANK

283

285

284

260

261

262

263

264

265

266

267

268

269

270

271

272

273

274

HSYNC

FIELD

ODD FIELD EVEN FIELD

Figure 108. SD Timing Mode 1, Slave Option, NTSC

Rev. H | Page 81 of 108

ADV7390/ADV7391/ADV7392/ADV7393

Data Sheet

DISPLAY

VERTICAL BLANK

3

4

5

7

622

623

624

625

1

2

6

21

22

23

HSYNC

FIELD

ODD FIELD

EVEN FIELD

DISPLAY

VERTICAL BLANK

309

310

311

312

313

314

315

316

318

319

320

317

334

335

336

HSYNC

FIELD

ODD FIELD

EVEN FIELD

Figure 109. SD Timing Mode 1, Slave Option, PAL

Mode 1—Master Option (Subaddress 0x8A = X X X X X 0 1 1)

In this mode, the ADV739x can generate horizontal synchronization and odd/even field signals. When

HSYNC

is low, a transition of the

field input indicates a new frame, that is, vertical retrace. The ADV739x automatically blanks all normally blank lines as required by the

HSYNC

CCIR-624 standard. Pixel data is latched on the rising clock edge following the timing signal transitions.

and FIELD are output

HSYNC

VSYNC

pins, respectively.

on the

and

HSYNC

FIELD

PIXEL

DATA

Cr

Y

Cb

Y

PAL = 132 × CLOCK/2

NTSC = 122 × CLOCK/2

Figure 110. SD Timing Mode 1, Odd/Even Field Transitions (Master/Slave)

Mode 2— Slave Option (Subaddress 0x8A = X X X X X 1 0 0)

In this mode, the ADV739x accepts horizontal and vertical synchronization signals. A coincident low transition of both

HSYNC

VSYNC

HSYNC

low transition when is high indicates the start of an even field.

and

inputs indicates the start of an odd field. A

HSYNC

VSYNC

are input on

The ADV739x automatically blanks all normally blank lines as required by the CCIR-624 standard.

HSYNC VSYNC

and

the

and

pins, respectively.

Rev. H | Page 82 of 108

Data Sheet

ADV7390/ADV7391/ADV7392/ADV7393

DISPLAY

VERTICAL BLANK

522

523

524

525

3

4

5

7

8

20

21

22

1

2

6

10

11

9

HSYNC

VSYNC

ODD FIELD

EVEN FIELD

DISPLAY

VERTICAL BLANK

283

285

284

260

261

262

263

264

265

266

267

268

269

270

271

272

273

274

HSYNC

VSYNC

EVEN FIELD

ODD FIELD

Figure 111. SD Timing Mode 2, Slave Option, NTSC

DISPLAY

VERTICAL BLANK

4

622

623

624

625

1

2

3

5

6

7

21

22

23

HSYNC

VSYNC

EVEN FIELD

ODD FIELD

DISPLAY

VERTICAL BLANK

309

310

311

312

313

314

315

316

318

319

320

317

334

335

336

HSYNC

VSYNC

EVEN FIELD

ODD FIELD

Figure 112. SD Timing Mode 2, Slave Option, PAL

Mode 2—Master Option (Subaddress 0x8A = X X X X X 1 0 1)

In this mode, the ADV739x can generate horizontal and vertical synchronization signals. A coincident low transition of both

VSYNC VSYNC HSYNC

HSYNC

and

inputs indicates the start of an odd field. A

ADV739x automatically blanks all normally blank lines as required by the CCIR-624 standard.

HSYNC VSYNC

low transition when

is high indicates the start of an even field. The

HSYNC

VSYNC

are output on the

and

pins, respectively.

HSYNC

VSYNC

PIXEL

DATA

Cb

Cr

Y

PAL = 132 × CLOCK/2

NTSC = 122 × CLOCK/2

Figure 113. SD Timing Mode 2, Even-to-Odd Field Transition (Master/Slave)

Rev. H | Page 83 of 108

ADV7390/ADV7391/ADV7392/ADV7393

Data Sheet

HSYNC

VSYNC

PAL = 864 × CLOCK/2

NTSC = 858 × CLOCK/2

PIXEL

DATA

Cb

Y

Cr

Y

Cb

PAL = 132 × CLOCK/2

NTSC = 122 × CLOCK/2

Figure 114. SD Timing Mode 2, Odd-to-Even Field Transition (Master/Slave)

Mode 3—Master/Slave Option (Subaddress 0x8A = X X X X X 1 1 0 or X X X X X 1 1 1)

In this mode, the ADV739x accepts or generates horizontal synchronization and odd/even field signals. When

HSYNC

is high, a

transition of the field input indicates a new frame, that is, vertical retrace. The ADV739x automatically blanks all normally blank lines as

HSYNC

VSYNC

HSYNC

VSYNC

and

required by the CCIR-624 standard.

pins, respectively.

and

are output in master mode and input in slave mode on the

DISPLAY

VERTICAL BLANK

522

523

524

525

4

20

21

22

10

11

1

2

3

5

6

7

8

9

HSYNC

FIELD

EVEN FIELD ODD FIELD

DISPLAY

VERTICAL BLANK

283

285

284

260

261

262

263

264

265

266

267

268

269

270

271

272

273

274

HSYNC

FIELD

ODD FIELD EVEN FIELD

Figure 115. SD Timing Mode 3, NTSC

DISPLAY

VERTICAL BLANK

622

623

624

625

1

2

3

4

5

6

7

21

22

23

HSYNC

FIELD

EVEN FIELD ODD FIELD

DISPLAY

VERTICAL BLANK

309

310

311

312

313

314

315

316

318

319

320

317

334

335

336

HSYNC

FIELD

EVEN FIELD ODD FIELD

Figure 116. SD Timing Mode 3, PAL

Rev. H | Page 84 of 108

Data Sheet

HD TIMING

ADV7390/ADV7391/ADV7392/ADV7393

DISPLAY

FIELD 1

VERTICAL BLANKING INTERVAL

1124

1125

1

2

3

4

5

6

7

8

20

21

22

560

VSYNC

HSYNC

DISPLAY

VERTICAL BLANKING INTERVAL

FIELD 2

561

562

563

564

565

566

567

568

569

570

583

584

585

1123

VSYNC

HSYNC

VSYNC

Input Timing

Figure 117. 1080i

and

Rev. H | Page 85 of 108

ADV7390/ADV7391/ADV7392/ADV7393

VIDEO OUTPUT LEVELS

Data Sheet

SD YPrPb OUTPUT LEVELS—SMPTE/EBU N10

Pattern: 100% Color Bars

700mV

300mV

Figure 118. Y Levels—NTSC

Figure 121. Y Levels—PAL

700mV

Figure 119. Pr Levels—NTSC

Figure 122. Pr Levels—PAL

700mV

Figure 120. Pb Levels—NTSC

Figure 123. Pb Levels—PAL

Rev. H | Page 86 of 108

Data Sheet

ADV7390/ADV7391/ADV7392/ADV7393

ED/HD YPrPb OUTPUT LEVELS

EIA-770.2, STANDARD FOR Y

INPUT CODE

EIA-770.3, STANDARD FOR Y

OUTPUT VOLTAGE

INPUT CODE

940

OUTPUT VOLTAGE

940

700mV

64

300mV

EIA-770.3, STANDARD FOR Pr/Pb

OUTPUT VOLTAGE

EIA-770.2, STANDARD FOR Pr/Pb

960

OUTPUT VOLTAGE

960

512

64

600mV

700mV

512

64

700mV

Figure 124. EIA-770.2 Standard Output Signals (525p/625p)

Figure 126. EIA-770.3 Standard Output Signals (1080i/720p)

EIA-770.1, STANDARD FOR Y

Y–OUTPUT LEVELS FOR

FULL INPUT SELECTION

INPUT CODE

OUTPUT VOLTAGE

782mV

INPUT CODE

1023

OUTPUT VOLTAGE

940

700mV

714mV

64

300mV

286mV

Pr/Pb–OUTPUT LEVELS FOR

FULL INPUT SELECTION

EIA-770.1, STANDARD FOR Pr/Pb

OUTPUT VOLTAGE

INPUT CODE

1023

OUTPUT VOLTAGE

960

700mV

512

64

300mV

Figure 125. EIA-770.1 Standard Output Signals (525p/625p)

Figure 127. Output Levels for Full Input Selection

Rev. H | Page 87 of 108

ADV7390/ADV7391/ADV7392/ADV7393

Data Sheet

SD/ED/HD RGB OUTPUT LEVELS

Pattern: 100%/75% Color Bars

R

700mV/525mV

300mV

G

700mV/525mV

300mV

B

700mV/525mV

300mV

Figure 130. HD RGB Output Levels—RGB Sync Disabled

Figure 128. SD/ED RGB Output Levels—RGB Sync Disabled

R

700mV/525mV

600mV

300mV

700mV/525mV

300mV

0mV

G

700mV/525mV

600mV

700mV/525mV

300mV

0mV

300mV

0mV

B

700mV/525mV

600mV

700mV/525mV

300mV

0mV

300mV

0mV

Figure 131. HD RGB Output Levels—RGB Sync Enabled

Figure 129. SD/ED RGB Output Levels—RGB Sync Enabled

Rev. H | Page 88 of 108

Data Sheet

ADV7390/ADV7391/ADV7392/ADV7393

SD OUTPUT PLOTS

VOLTS

0.6

VOLTS IRE:FLT

100

0.4

0.2

0

0.5

50

0

–0.2

F1

L76

–50

L608

0

10

20

30

40

50

60

0

10

20

30

MICROSECONDS

PRECISION MODE OFF

40

50

60

MICROSECONDS

NOISE REDUCTION: 0.00dB

APL = 39.1%

625 LINE NTSC NO FILTERING

SLOW CLAMP TO 0.00 AT 6.72µs

APL = 44.5%

525 LINE NTSC

SLOW CLAMP TO 0.00V AT 6.72µs

PRECISION MODE OFF

SYNCHRONOUS SOUND-IN-SYNC OFF

FRAMES SELECTED 1, 2, 3, 4

SYNCHRONOUS SYNC =A

FRAMES SELECTED 1, 2

Figure 132. NTSC Color Bars (75%)

Figure 135. PAL Color Bars (75%)

VOLTS

0.5

VOLTS IRE:FLT

0.6

0.4

50

0.2

0

00

0

–0.2

L575

20

F2

L238

0

10

30

40

50

60

70

0

10

20

30

40

50

60

MICROSECONDS

APL NEEDS SYNC SOURCE.

625 LINE PAL NO FILTERING

SLOW CLAMP TO 0.00 AT 6.72µs

NO BUNCH SIGNAL

NOISE REDUCTION: 15.05dB

APL = 44.3%

PRECISION MODE OFF

SYNCHRONOUS SOUND-IN-SYNC OFF

FRAMES SELECTED 1

525 LINE NTSC NO FILTERING

SLOW CLAMP TO 0.00V AT 6.72µs

SYNCHRONOUS SYNC = SOURCE

FRAMES SELECTED 1, 2

Figure 136. PAL Luma

Figure 133. NTSC Luma

VOLTS

0.5

VOLTS IRE:FLT

0.4

50

0.2

0

–0.2

–0.4

–50

–0.5

F1

L76

L575

20

0

10

30

40

50

60

0

10

20

30

40

50

60

MICROSECONDS

APL NEEDS SYNC SOURCE.

625 LINE PAL NO FILTERING

SLOW CLAMP TO 0.00 AT 6.72µs

NO BUNCH SIGNAL

NOISE REDUCTION: 15.05dB

APL NEEDS SYNC SOURCE.

525 LINE NTSC NO FILTERING

SLOW CLAMP TO 0.00 AT 6.72µs

PRECISION MODE OFF

SYNCHRONOUS SOUND-IN-SYNC OFF

FRAMES SELECTED 1

PRECISION MODE OFF

SYNCHRONOUS SYNC = B

FRAMES SELECTED 1, 2

Figure 137. PAL Chroma

Figure 134. NTSC Chroma

Rev. H | Page 89 of 108

ADV7390/ADV7391/ADV7392/ADV7393

VIDEO STANDARDS

Data Sheet

0

DATUM

H

SMPTE 274M

ANALOG WAVEFORM

DIGITAL HORIZONTAL BLANKING

272T

*1

4T

1920T

DIGITAL

ACTIVE LINE

ANCILLARY DATA

(OPTIONAL) OR BLANKING CODE

EAV CODE

SAV CODE

F

0

F

0

C

r

C

INPUT PIXELS

Y

V

Y

b

r

H*

4 CLOCK

192

0

2199

SAMPLE NUMBER

2112

2116 2156

44

188

2111

FVH* = FVH AND PARITY BITS

SAV/EAV: LINE 1–562: F = 0

SAV/EAV: LINE 563–1125: F = 1

SAV/EAV: LINE 1–20; 561–583; 1124–1125: V = 1

SAV/EAV: LINE 21–560; 584–1123: V = 0

FOR A FRAME RATE OF 30Hz: 40 SAMPLES

FOR A FRAME RATE OF 25Hz: 480 SAMPLES

Figure 138. EAV/SAV Input Data Timing Diagram (SMPTE 274M)

SMPTE 293M

ANALOG WAVEFORM

ANCILLARY DATA

(OPTIONAL)

DIGITAL

SAV CODE

F

EAV CODE

F

ACTIVE LINE

F

0

F

0

C

b

C

r

C

r

INPUT PIXELS

V

Y

V

Y

H*

4 CLOCK

853 857

SAMPLE NUMBER

719

723 736

DATUM

799

0

719

0

H

DIGITAL HORIZONTAL BLANKING

FVH* = FVH AND PARITY BITS

SAV: LINE 43–525 = 200H

SAV: LINE 1–42 = 2AC

EAV: LINE 43–525 = 274H

EAV: LINE 1–42 = 2D8

Figure 139. EAV/SAV Input Data Timing Diagram (SMPTE 293M)

ACTIVE

VIDEO

ACTIVE

VIDEO

VERTICAL BLANK

522 523 524 525

1

2

5

6

7

8

9

12

13

14

15

16

42

43

44

Figure 140. SMPTE 293M (525p)

Rev. H | Page 90 of 108

Data Sheet

ADV7390/ADV7391/ADV7392/ADV7393

ACTIVE

VIDEO

ACTIVE

VIDEO

VERTICAL BLANK

12

13

1

2

5

6

7

8

9

43

44

45

622 623

624 625

4

10

11

Figure 141. ITU-R BT.1358 (625p)

DISPLAY

VERTICAL BLANKING INTERVAL

7

1

2

3

4

5

6

747

748

749

750

26

27

744

745

8

25

Figure 142. SMPTE 296M (720p)

DISPLAY

VERTICAL BLANKING INTERVAL

FIELD 1

560

1

2

5

6

7

8

21

22

1124

1125

3

4

20

DISPLAY

VERTICAL BLANKING INTERVAL

FIELD 2

561

562

563

564

565

566

567

568

569

570

583

584

585

1123

Figure 143. SMPTE 274M (1080i)

Rev. H | Page 91 of 108

ADV7390/ADV7391/ADV7392/ADV7393

CONFIGURATION SCRIPTS

Data Sheet

The scripts listed in the following pages can be used to configure the ADV739x for basic operation. Certain features are enabled by

default. If required for a specific application, additional features can be enabled. Table 63 lists the scripts available for SD modes of

operation. Similarly, Table 98 and Table 115 list the scripts available for ED and HD modes of operation, respectively. For all scripts, only

the necessary register writes are included. All other registers are assumed to have their default values. The WLCSP package supports only

scripts in Table 65, Table 79, Table 82, and Table 96. In those scripts, Subaddress 0x00 must be set to 0x10.

STANDARD DEFINITION

Table 63. SD Configuration Scripts

Input Format

525i (NTSC)

Input Data Width¹

8-bit SDR

Synchronization Format

EAV/SAV

HSYNC VSYNC

/

EAV/SAV

Input Color Space

YCrCb

RGB

Output Color Space

Table Number

Table 64

Table 65

Table 66

Table 67

Table 68

Table 69

Table 70

Table 71

Table 72

Table 73

Table 74

Table 75

Table 76

Table 77

Table 78

YPrPb

CVBS/Y-C (S-Video)

YPrPb

8-bit SDR

RGB

HSYNC VSYNC

/

EAV/SAV

10-bit SDR

16-bit SDR

YPrPb

HSYNC VSYNC

/

HSYNC VSYNC

/

EAV/SAV

CVBS/Y-C (S-Video)

RGB

HSYNC VSYNC

/

HSYNC VSYNC

YPrPb

/

HSYNC VSYNC

RGB

/

HSYNC VSYNC

YPrPb

/

HSYNC VSYNC

RGB

CVBS/Y-C (S-Video)

RGB

/

HSYNC VSYNC

/

RGB

NTSC Sq. Pixel

8-bit SDR

16-bit SDR

EAV/SAV

HSYNC VSYNC

/

YCrCb

RGB

CVBS/Y-C (S-Video)

Table 79

Table 80

625i (PAL)

PAL Sq. Pixel

8-bit SDR

10-bBit SDR

10-bit SDR

16-bit SDR

8-bit SDR

16-bit SDR

EAV/SAV

HSYNC VSYNC

/

EAV/SAV

HSYNC VSYNC

/

YCrCb

RGB

YPrPb

CVBS/Y-C (S-Video)

YPrPb

Table 81

Table 82

Table 83

Table 84

Table 85

Table 86

Table 87

Table 88

Table 89

Table 90

Table 91

Table 92

Table 93

Table 94

Table 95

Table 96

Table 97

RGB

EAV/SAV

YPrPb

HSYNC VSYNC

/

HSYNC VSYNC

/

EAV/SAV

CVBS/Y-C (S-Video)

RGB

HSYNC VSYNC

/

HSYNC VSYNC

YPrPb

/

HSYNC VSYNC

RGB

/

HSYNC VSYNC

YPrPb

/

HSYNC VSYNC

RGB

CVBS/Y-C (S-Video)

RGB

/

HSYNC VSYNC

/

EAV/SAV

RGB

YCrCb

RGB

CVBS/Y-C (S-Video)

HSYNC VSYNC

/

¹SDR = single data rate.

Rev. H | Page 92 of 108

Data Sheet

ADV7390/ADV7391/ADV7392/ADV7393

Table 64. 8-Bit 525i YCrCb In (EAV/SAV), YPrPb Out

Table 68. 8-Bit 525i YCrCb In, RGB Out

Subaddress Setting Description

0x17

0x00

0x01

0x80

0x02

0x1C

0x00

0x10

Software reset.

0x17

0x00

0x01

0x02

0x1C

0x00

0x10

Software reset.

All DACs enabled. PLL enabled (16×).

SD input mode.

All DACs enabled. PLL enabled (16×).

SD input mode.

NTSC standard. SSAF luma filter

enabled.

RGB output enabled. RGB output sync

enabled.

1.3 MHz chroma filter enabled.

0x80

0x82

0x10

0xC9

NTSC standard. SSAF luma filter

enabled. 1.3 MHz chroma filter enabled.

0x82

0xC9

Pixel data valid. YPrPb out. SSAF PrPb

filter enabled. Active video edge

control enabled. Pedestal enabled.

Pixel data valid. RGB out. SSAF PrPb

filter enabled. Active video edge

control enabled. Pedestal enabled.

0x8A

0x0C

Timing Mode 2 (slave). HSYNC/VSYNC

synchronization.

Table 65. 8-Bit 525i YCrCb In (EAV/SAV), CVBS/Y-C Out

Subaddress Setting Description

0x17

0x00

0x02

0x1C

0x10

0x00

0x10

Software reset

Table 69. 10-Bit 525i YCrCb In (EAV/SAV), YPrPb Out

Subaddress Setting Description

All DACs enabled. PLL enabled (16×).

WLCSP required.

0x17

0x00

0x01

0x80

0x02

0x1C

0x00

0x10

Software reset.

0x01

0x80

SD input mode.

All DACs enabled. PLL enabled (16×).

SD input mode.

NTSC standard. SSAF luma filter

enabled. 1.3 MHz chroma filter enabled.

NTSC standard. SSAF luma filter

0x82

0xCB

Pixel data valid. CVBS/Y-C (S-Video)

out. SSAF PrPb filter enabled. Active

video edge control enabled. Pedestal

enabled.

enabled. 1.3 MHz chroma filter enabled.

0x82

0x88

0xC9

0x10

Pixel data valid. YPrPb out. SSAF PrPb

filter enabled. Active video edge

control enabled. Pedestal enabled.

10-bit input enabled.

Table 66. 8-Bit 525i YCrCb In, YPrPb Out

Subaddress Setting Description

Table 70. 10-Bit 525i YCrCb In, YPrPb Out

Subaddress Setting Description

0x17

0x00

0x01

0x80

0x02

0x1C

0x00

0x10

Software reset.

All DACs enabled. PLL enabled (16×).

SD input mode.

0x17

0x00

0x01

0x80

0x02

0x1C

0x00

0x10

Software reset.

All DACs enabled. PLL enabled (16×).

SD input mode.

NTSC standard. SSAF luma filter

enabled. 1.3 MHz chroma filter enabled.

0x82

0x8A

0xC9

0x0C

Pixel data valid. YPrPb out. SSAF PrPb

filter enabled. Active video edge

control enabled. Pedestal enabled.

NTSC standard. SSAF luma filter

enabled. 1.3 MHz chroma filter enabled.

0x82

0xC9

Pixel data valid. YPrPb out. SSAF PrPb

filter enabled. Active video edge

control enabled. Pedestal enabled.

Timing Mode 2 (slave). HSYNC/VSYNC

synchronization.

0x88

0x8A

0x10

0x0C

10-bit input enabled.

Timing Mode 2 (slave). HSYNC/VSYNC

synchronization.

Table 67. 8-Bit 525i YCrCb In (EAV/SAV), RGB Out

Subaddress Setting Description

0x17

0x00

0x01

0x02

0x1C

0x00

0x10

Software reset.

All DACs enabled. PLL enabled (16×).

SD input mode.

RGB output enabled. RGB output sync

enabled.

0x80

0x82

0x10

0xC9

NTSC standard. SSAF luma filter

enabled. 1.3 MHz chroma filter enabled.

Pixel data valid. RGB out. SSAF PrPb

filter enabled. Active video edge

control enabled. Pedestal enabled.

Rev. H | Page 93 of 108

ADV7390/ADV7391/ADV7392/ADV7393

Data Sheet

Table 71. 10-Bit 525i YCrCb In, CVBS/Y-C Out

Table 74. 16-Bit 525i YCrCb In, YPrPb Out

Subaddress Setting Description

0x17

0x00

0x01

0x80

0x02

0x1C

0x00

0x10

Software reset.

0x17

0x00

0x01

0x80

0x02

0x1C

0x00

0x10

Software reset.

All DACs enabled. PLL enabled (16×).

SD input mode.

All DACs enabled. PLL enabled (16×).

SD input mode.

NTSC standard. SSAF luma filter

enabled. 1.3 MHz chroma filter enabled.

0x82

0xCB

Pixel data valid. CVBS/Y-C (S-Video) out.

SSAF PrPb filter enabled. Active video

edge control enabled. Pedestal enabled.

0x82

0xC9

Pixel data valid. YPrPb out. SSAF PrPb

filter enabled. Active video edge

control enabled. Pedestal enabled.

0x88

0x8A

0x10

0x0C

10-bit input enabled.

0x88

0x8A

0x10

0x0C

16-bit RGB input enabled.

Timing Mode 2 (slave). HSYNC/VSYNC

synchronization.

HSYNC VSYNC

/

Timing Mode 2 (slave).

synchronization.

Table 72. 10-Bit 525i YCrCb In (EAV/SAV), RGB Out

Table 75. 16-Bit 525i YCrCb In, RGB Out

Subaddress Setting Description

0x17

0x00

0x01

0x02

0x1C

0x00

0x10

Software reset.

0x17

0x00

0x01

0x02

0x1C

0x00

0x10

Software reset

All DACs enabled. PLL enabled (16×).

SD input mode.

All DACs enabled. PLL enabled (16×).

SD input mode.

RGB output enabled. RGB output sync

enabled.

RGB output enabled. RGB output sync

enabled.

0x80

0x82

0x10

0xC9

NTSC standard. SSAF luma filter

enabled. 1.3 MHz chroma filter enabled.

0x80

0x82

0x10

0xC9

NTSC standard. SSAF luma filter

enabled. 1.3 MHz chroma filter enabled.

Pixel data valid. RGB out. SSAF PrPb

filter enabled. Active video edge

control enabled. Pedestal enabled.

Pixel data valid. RGB out. SSAF PrPb

filter enabled. Active video edge

control enabled. Pedestal enabled.

0x88

0x10

10-bit input enabled.

0x88

0x8A

0x10

0x0C

16-bit RGB input enabled.

Timing Mode 2 (slave). HSYNC/VSYNC

synchronization.

Table 73. 10-Bit 525i YCrCb In, RGB Out

Subaddress Setting Description

Table 76. 16-Bit 525i RGB In, YPrPb Out

Subaddress Setting Description

0x17

0x00

0x01

0x02

0x1C

0x00

0x10

Software reset.

All DACs enabled. PLL enabled (16×).

SD input mode.

0x17

0x00

0x01

0x80

0x02

0x1C

0x00

0x10

Software reset.

All DACs enabled. PLL enabled (16×).

SD input mode.

RGB output enabled. RGB output sync

enabled.

0x80

0x82

0x10

0xC9

NTSC standard. SSAF luma filter

enabled. 1.3 MHz chroma filter enabled.

NTSC standard. SSAF luma filter

enabled. 1.3 MHz chroma filter enabled.

Pixel data valid. RGB out. SSAF PrPb

filter enabled. Active video edge

control enabled. Pedestal enabled.

0x82

0xC9

Pixel data valid. YPrPb out. SSAF PrPb

filter enabled. Active video edge

control enabled. Pedestal enabled.

0x88

0x8A

0x10

0x0C

10-bit input enabled.

0x87

0x88

0x8A

0x80

0x10

0x0C

RGB input enabled.

Timing Mode 2 (slave). HSYNC/VSYNC

synchronization.

16-bit RGB input enabled.

Timing Mode 2 (slave). HSYNC/VSYNC

synchronization.

Rev. H | Page 94 of 108

Data Sheet

ADV7390/ADV7391/ADV7392/ADV7393

Table 77. 16-Bit 525i RGB In, CVBS/Y-C Out

Subaddress Setting Description

Table 80. 16-Bit NTSC Square Pixel RGB In, CVBS/Y-C Out

Subaddress Setting Description

0x17

0x00

0x01

0x80

0x02

0x1C

0x00

0x10

Software reset.

0x17

0x00

0x01

0x80

0x02

0x1C

0x00

0x10

Software reset.

All DACs enabled. PLL enabled (16×).

SD input mode.

All DACs enabled. PLL enabled (16×).

SD input mode.

NTSC standard. SSAF luma filter

enabled. 1.3 MHz chroma filter enabled.

0x82

0xCB

Pixel data valid. CVBS/Y-C (S-Video) out.

SSAF PrPb filter enabled. Active video

edge control enabled. Pedestal enabled.

0x82

0xDB

Pixel data valid. CVBS/Y-C (S-Video) out.

SSAF PrPb filter enabled. Active video

edge control enabled. Pedestal

0x87

0x88

0x8A

0x80

0x10

0x0C

RGB input enabled.

enabled. Square pixel mode enabled.

16-bit RGB input enabled.

0x87

0x88

0x8A

0x80

0x10

0x0C

RGB input enabled.

Timing Mode 2 (slave). HSYNC/VSYNC

synchronization.

16-bit RGB input enabled.

Timing Mode 2 (slave). HSYNC/VSYNC

synchronization.

0x8C

0x8D

0x8E

0x8F

0x55

0x25

Subcarrier frequency register values

for CVBS and/or S-Video (Y-C) output

in NTSC square pixel mode (24.5454

MHz input clock).

Table 78. 16-Bit 525i RGB In, RGB Out

Subaddress Setting Description

0x17

0x00

0x01

0x02

0x1C

0x00

0x10

Software reset.

All DACs enabled. PLL enabled (16×).

SD input mode.

RGB output enabled. RGB output sync

enabled.

Table 81. 8-Bit 625i YCrCb In (EAV/SAV), YPrPb Out

Subaddress Setting Description

0x80

0x82

0x10

0xC9

NTSC standard. SSAF luma filter

enabled. 1.3 MHz chroma filter enabled.

0x17

0x00

0x01

0x80

0x02

0x1C

0x00

0x11

Software reset.

All DACs enabled. PLL enabled (16×).

SD input mode.

Pixel data valid. RGB out. SSAF PrPb

filter enabled. Active video edge

control enabled. Pedestal enabled.

PAL standard. SSAF luma filter enabled.

1.3 MHz chroma filter enabled.

0x87

0x88

0x8A

0x80

0x10

0x0C

RGB input enabled.

0x82

0xC1

Pixel data valid. YPrPb out. SSAF PrPb

filter enabled. Active video edge

control enabled.

16-bit RGB input enabled.

Timing Mode 2 (slave). HSYNC/VSYNC

synchronization.

Table 82. 8-Bit 625i YCrCb In (EAV/SAV), CVBS/Y-C Out

Subaddress Setting Description

Table 79. 8-Bit NTSC Square Pixel YCrCb In (EAV/SAV),

CVBS/Y-C Out

Subaddress Setting Description

0x17

0x00

0x02

0x1C

0x10

0x00

0x11

Software reset.

All DACs enabled. PLL enabled (16×).

WLCSP required.

0x17

0x00

0x02

0x1C

0x10

0x00

0x10

Software reset

All DACs enabled. PLL enabled (16×).

WLCSP required.

0x01

0x80

SD input mode.

PAL standard. SSAF luma filter enabled.

1.3 MHz chroma filter enabled.

0x01

0x80

SD input mode.

NTSC standard. SSAF luma filter

0x82

0xC3

Pixel data valid. CVBS/Y-C (S-Video)

out. SSAF PrPb filter enabled. Active

video edge control enabled.

enabled. 1.3 MHz chroma filter enabled.

0x82

0xDB

Pixel data valid. CVBS/Y-C (S-Video)

out. SSAF PrPb filter enabled. Active

video edge control enabled. Pedestal

enabled. Square pixel mode enabled.

0x8C

0x8D

0x8E

0x8F

0xCB

0x8A

0x09

0x2A

Subcarrier frequency register values

for CVBS and/or S-Video (Y-C) output

in PAL mode (27 MHz input clock).

0x8C

0x8D

0x8E

0x8F

0x55

0x25

Subcarrier frequency register values

for CVBS and/or S-Video (Y-C) output

in NTSC square pixel mode (24.5454

MHz input clock).

Rev. H | Page 95 of 108

ADV7390/ADV7391/ADV7392/ADV7393

Data Sheet

Table 83. 8-Bit 625i YCrCb In, YPrPb Out

Table 87. 10-Bit 625i YCrCb In, YPrPb Out

Subaddress Setting Description

0x17

0x00

0x01

0x80

0x02

0x1C

0x00

0x11

Software reset.

0x17

0x00

0x01

0x80

0x02

0x1C

0x00

0x11

Software reset.

All DACs enabled. PLL enabled (16×).

SD input mode.

All DACs enabled. PLL enabled (16×).

SD input mode.

PAL standard. SSAF luma filter enabled.

1.3 MHz chroma filter enabled.

PAL standard. SSAF luma filter enabled.

1.3 MHz chroma filter enabled.

0x82

0x8A

0xC1

0x0C

Pixel data valid. YPrPb out. SSAF PrPb

filter enabled. Active video edge

control enabled.

0x82

0xC1

Pixel data valid. YPrPb out. SSAF PrPb

filter enabled. Active video edge

control enabled.

Timing Mode 2 (slave). HSYNC/VSYNC

synchronization.

0x88

0x8A

0x10

0x0C

10-bit input enabled.

Timing Mode 2 (slave). HSYNC/VSYNC

synchronization.

Table 84. 8-Bit 625i YCrCb In (EAV/SAV), RGB Out

Table 88. 10-Bit 625i YCrCb In, CVBS/Y-C Out

Subaddress Setting Description

0x17

0x00

0x01

0x02

0x1C

0x00

0x10

Software reset.

Subaddress Setting Description

All DACs enabled. PLL enabled (16×).

SD input mode.

0x17

0x00

0x01

0x80

0x02

0x1C

0x00

0x11

Software reset.

All DACs enabled. PLL enabled (16×).

SD input mode.

RGB output enabled. RGB output sync

enabled.

PAL standard. SSAF luma filter enabled.

1.3 MHz chroma filter enabled.

0x80

0x82

0x11

0xC1

PAL standard. SSAF luma filter enabled.

1.3 MHz chroma filter enabled.

0x82

0xC3

Pixel Data Valid. CVBS/Y-C (S-Video)

Out. SSAF PrPb filter enabled. Active

video edge control enabled.

Pixel data valid. RGB out. SSAF PrPb

filter enabled. Active video edge

control enabled.

0x88

0x8A

0x10

0x0C

10-bit input enabled.

Timing Mode 2 (slave). HSYNC/VSYNC

synchronization.

Table 85. 8-Bit 625i YCrCb In, RGB Out

Subaddress Setting Description

0x8C

0x8D

0x8E

0x8F

0xCB

0x8A

0x09

0x2A

Subcarrier frequency register values

for CVBS and/or S-Video (Y-C) output

in PAL mode (27 MHz input clock).

0x17

0x00

0x01

0x02

0x1C

0x00

0x10

Software reset.

All DACs enabled. PLL enabled (16×).

SD input mode.

RGB output enabled. RGB output sync

enabled.

Table 89. 10-Bit 625i YCrCb In (EAV/SAV), RGB Out

Subaddress Setting Description

0x80

0x82

0x11

0xC1

PAL standard. SSAF luma filter enabled.

1.3 MHz chroma filter enabled.

0x17

0x00

0x01

0x02

0x1C

0x00

0x10

Software reset.

Pixel data valid. RGB out. SSAF PrPb

filter enabled. Active video edge

control enabled.

All DACs enabled. PLL enabled (16×).

SD input mode.

RGB output enabled. RGB output sync

enabled.

0x8A

0x0C

Timing Mode 2 (slave). HSYNC/VSYNC

synchronization.

0x80

0x82

0x11

0xC1

PAL standard. SSAF luma filter enabled.

1.3 MHz chroma filter enabled.

Pixel data valid. RGB out. SSAF PrPb

filter enabled. Active video edge

control enabled.

Table 86. 10-Bit 625i YCrCb In (EAV/SAV), YPrPb Out

Subaddress Setting Description

0x17

0x00

0x01

0x80

0x02

0x1C

0x00

0x11

Software reset.

0x88

0x10

10-bit input enabled.

All DACs enabled. PLL enabled (16×).

SD input mode.

PAL standard. SSAF luma filter enabled.

1.3 MHz chroma filter enabled.

0x82

0x88

0xC1

0x10

Pixel data valid. YPrPb out. SSAF PrPb

filter enabled. Active video edge

control enabled.

10-bit input enabled.

Rev. H | Page 96 of 108

Data Sheet

ADV7390/ADV7391/ADV7392/ADV7393

Table 90. 10-Bit 625i YCrCb In, RGB Out

Table 93. 16-Bit 625i RGB In, YPrPb Out

Subaddress Setting Description

0x17

0x00

0x01

0x02

0x1C

0x00

0x10

Software reset.

0x17

0x00

0x01

0x80

0x02

0x1C

0x00

0x11

Software reset.

All DACs enabled. PLL enabled (16×).

SD input mode.

All DACs enabled. PLL enabled (16×).

SD input mode.

RGB output enabled. RGB output sync

enabled.

PAL standard. SSAF luma filter enabled.

1.3 MHz chroma filter enabled.

0x80

0x82

0x11

0xC1

PAL standard. SSAF luma filter enabled.

1.3 MHz chroma filter enabled.

0x82

0xC1

Pixel data valid. YPrPb out. SSAF PrPb

filter enabled. Active video edge

control enabled.

Pixel data valid. RGB out. SSAF PrPb

filter enabled. Active video edge

control enabled.

0x87

0x88

0x8A

0x80

0x10

0x0C

RGB input enabled.

16-bit RGB input enabled.

0x88

0x8A

0x10

0x0C

10-bit input enabled.

Timing Mode 2 (slave). HSYNC/VSYNC

synchronization.

Timing Mode 2 (slave). HSYNC/VSYNC

synchronization.

Table 94. 16-Bit 625i RGB In, CVBS/Y-C Out

Subaddress Setting Description

Table 91. 16-Bit 625i YCrCb In, YPrPb Out

Subaddress Setting Description

0x17

0x00

0x01

0x80

0x02

0x1C

0x00

0x11

Software reset.

All DACs enabled. PLL enabled (16×).

SD input mode.

0x17

0x00

0x01

0x80

0x02

0x1C

0x00

0x11

Software reset.

All DACs enabled. PLL enabled (16×).

SD input mode.

PAL standard. SSAF luma filter enabled.

1.3 MHz chroma filter enabled.

PAL standard. SSAF luma filter enabled.

1.3 MHz chroma filter enabled.

0x82

0xC3

Pixel data valid. CVBS/Y-C (S-Video)

out. SSAF PrPb filter enabled. Active

video edge control enabled.

0x82

0xC1

Pixel data valid. YPrPb out. SSAF PrPb

filter enabled. Active video edge

control enabled.

0x87

0x88

0x8A

0x80

0x10

0x0C

RGB input enabled.

16-bit RGB input enabled.

Timing Mode 2 (slave). HSYNC/VSYNC

synchronization.

0x88

0x8A

0x10

0x0C

16-bit RGB input enabled.

Timing Mode 2 (slave). HSYNC/VSYNC

synchronization.

0x8C

0x8D

0x8E

0x8F

0xCB

0x8A

0x09

0x2A

Subcarrier frequency register values

for CVBS and/or S-Video (Y-C) output

in PAL mode (27 MHz input clock).

Table 92. 16-Bit 625i YCrCb In, RGB Out

Subaddress Setting Description

0x17

0x00

0x01

0x02

0x1C

0x00

0x10

Software reset.

All DACs enabled. PLL enabled (16×).

SD input mode.

Table 95. 16-Bit 625i RGB In, RGB Out

Subaddress Setting Description

RGB output enabled. RGB output sync

enabled.

0x17

0x00

0x01

0x02

0x1C

0x00

0x10

Software reset.

0x80

0x82

0x11

0xC1

PAL standard. SSAF luma filter enabled.

1.3 MHz chroma filter enabled.

All DACs enabled. PLL enabled (16×).

SD input mode.

Pixel data valid. RGB out. SSAF PrPb

filter enabled. Active video edge

control enabled.

RGB output enabled. RGB output sync

enabled.

0x80

0x82

0x11

0xC1

PAL standard. SSAF luma filter enabled.

1.3 MHz chroma filter enabled.

0x88

0x8A

0x10

0x0C

16-bit RGB input enabled.

Timing Mode 2 (slave). HSYNC/VSYNC

synchronization.

Pixel data valid. RGB out. SSAF PrPb

filter enabled. Active video edge

control enabled.

0x87

0x88

0x8A

0x80

0x10

0x0C

RGB input enabled.

16-bit RGB input enabled.

Timing Mode 2 (slave). HSYNC/VSYNC

synchronization.

Rev. H | Page 97 of 108

ADV7390/ADV7391/ADV7392/ADV7393

Data Sheet

Table 96. 8-Bit PAL Square Pixel YCrCb In (EAV/SAV),

CVBS/Y-C Out

Table 97. 16-Bit PAL Square Pixel RGB In, CVBS/Y-C Out

Subaddress Setting Description

0x17

0x00

0x01

0x80

0x02

0x1C

0x00

0x11

Software reset.

0x17

0x00

0x02

0x1C

0x10

0x00

0x11

Software reset.

All DACs enabled. PLL enabled (16×).

SD input mode.

All DACs enabled. PLL enabled (16×).

WLCSP required.

PAL standard. SSAF luma filter enabled.

1.3 MHz chroma filter enabled.

0x01

0x80

SD input mode.

0x82

0xD3

Pixel data valid. CVBS/Y-C (S-Video)

out. SSAF PrPb filter enabled. Active

video edge control enabled. Square

pixel mode enabled.

PAL standard. SSAF luma filter enabled.

1.3 MHz chroma filter enabled.

0x82

0xD3

Pixel data valid. CVBS/Y-C (S-Video)

out. SSAF PrPb filter enabled. Active

video edge control enabled. Square

pixel mode enabled.

0x87

0x88

0x8A

0x80

0x10

0x0C

RGB input enabled.

16-bit RGB input enabled.

Timing Mode 2 (slave). HSYNC/VSYNC

synchronization.

0x8C

0x8D

0x8E

0x8F

0x0C

0x8C

0x79

0x26

Subcarrier frequency register values

for CVBS and/or S-Video (Y-C) output

in PAL square pixel mode (29.5 MHz

input clock).

0x8C

0x8D

0x8E

0x8F

0x0C

0x8C

0x79

0x26

Subcarrier frequency register values

for CVBS and/or S-Video (Y-C) output

in PAL square pixel mode (29.5 MHz

input clock).

Rev. H | Page 98 of 108

Data Sheet

ADV7390/ADV7391/ADV7392/ADV7393

ENHANCED DEFINITION

Table 98. ED Configuration Scripts

Input Format

Input Data Width

Synchronization Format

EAV/SAV

HSYNC VSYNC

/

EAV/SAV

HSYNC VSYNC

/

Input Color Space

YCrCb

Output Color Space

Table Number

Table 107

Table 109

Table 108

Table 110

Table 99

Table 100

Table 101

Table 102

525p

8-bit DDR

YPrPb

RGB

YPrPb

RGB

YPrPb

RGB

10-bit DDR

16-bit SDR

YCrCb

525p

YCrCb

RGB

625p

8-bit DDR

10-bit DDR

16-bit SDR

EAV/SAV

YCrCb

YPrPb

RGB

YPrPb

RGB

YPrPb

RGB

Table 111

Table 113

Table 112

Table 114

Table 103

Table 104

Table 105

Table 106

HSYNC VSYNC

/

EAV/SAV

HSYNC VSYNC

RGB

/

Table 99. 16-Bit 525p YCrCb In (EAV/SAV), YPrPb Out

Table 102. 16-Bit 525p YCrCb In, RGB Out

Subaddress Setting Description

0x17

0x00

0x01

0x30

0x02

0x1C

0x10

0x04

Software reset.

0x17

0x00

0x01

0x02

0x1C

0x10

Software reset.

All DACs enabled. PLL enabled (8×).

ED-SDR input mode.

All DACs enabled. PLL enabled (8×).

ED-SDR input mode.

525p at 59.94 Hz. EAV/SAV synchroni-

zation. EIA-770.2 output levels.

RGB output enabled. RGB output sync

enabled.

0x31

0x01

Pixel data valid.

0x30

0x31

0x00

0x01

525p at 59.94 Hz. HSYNC/VSYNC synch-

ronization. EIA-770.2 output levels.

Pixel data valid.

Table 100. 16-Bit 525p YCrCb In, YPrPb Out

Subaddress Setting Description

Table 103. 16-Bit 625p YCrCb In (EAV/SAV), YPrPb Out

Subaddress Setting Description

0x17

0x00

0x01

0x30

0x02

0x1C

0x10

0x00

Software reset.

All DACs enabled. PLL enabled (8×).

ED-SDR input mode.

0x17

0x00

0x01

0x30

0x02

0x1C

0x10

0x1C

Software reset.

All DACs enabled. PLL enabled (8×).

ED-SDR input mode.

525p at 59.94 Hz. HSYNC/VSYNC synch-

ronization. EIA-770.2 output levels.

Pixel data valid.

0x31

0x01

625p at 50 Hz. EAV/SAV synchroni-

zation. EIA-770.2 output levels.

0x31

0x01

Pixel data valid.

Table 101. 16-Bit 525p YCrCb In (EAV/SAV), RGB Out

Subaddress Setting Description

Table 104. 16-Bit 625p YCrCb In, YPrPb Out

Subaddress Setting Description

0x17

0x00

0x01

0x02

0x1C

0x10

Software reset.

All DACs enabled. PLL enabled (8×).

ED-SDR input mode.

0x17

0x00

0x01

0x30

0x02

0x1C

0x10

0x18

Software reset.

All DACs enabled. PLL enabled (8×).

ED-SDR input mode.

RGB output enabled. RGB output sync

enabled.

0x30

0x31

0x04

0x01

525p at 59.94 Hz. EAV/SAV synchroni-

zation. EIA-770.2 output levels.

625p at 50 Hz. HSYNC/VSYNC synch-

ronization. EIA-770.2 output levels.

Pixel data valid.

0x31

0x01

Pixel data valid.

Rev. H | Page 99 of 108

ADV7390/ADV7391/ADV7392/ADV7393

Data Sheet

Table 105. 16-Bit 625p YCrCb In (EAV/SAV), RGB Out

Subaddress Setting Description

Table 109. 8-Bit 525p YCrCb In (EAV/SAV), RGB Out

Subaddress Setting Description

0x17

0x00

0x01

0x02

0x1C

0x10

Software reset.

0x17

0x00

0x01

0x02

0x1C

0x20

Software reset.

All DACs enabled. PLL enabled (8×).

ED-SDR input mode.

All DACs enabled. PLL enabled (8×).

ED-DDR input mode. Luma data

clocked on falling edge of CLKIN.

RGB output enabled. RGB output sync

enabled.

0x02

0x30

0x31

0x10

0x04

0x01

RGB output enabled. RGB output sync

enabled.

0x30

0x31

0x1C

0x01

625p at 50 Hz. EAV/SAV synchroniza-

tion. EIA-770.2 output levels.

525p at 59.94 Hz. EAV/SAV synchro-

nization. EIA-770.2 output levels.

Pixel data valid.

Table 106. 16-Bit 625p YCrCb In, RGB Out

Subaddress Setting Description

Table 110. 10-Bit 525p YCrCb In (EAV/SAV), RGB Out

Subaddress Setting Description

0x17

0x00

0x01

0x02

0x1C

0x10

Software reset.

0x17

0x00

0x01

0x02

0x1C

0x20

Software reset.

All DACs enabled. PLL enabled (8×).

ED-SDR input mode.

All DACs enabled. PLL enabled (8×).

ED-DDR input mode. Luma data

clocked on falling edge of CLKIN.

RGB output enabled. RGB output sync

enabled.

0x02

0x30

0x10

0x04

RGB output enabled. RGB output sync

enabled.

0x30

0x31

0x18

0x01

625p at 50 Hz. HSYNC/VSYNC synch-

ronization. EIA-770.2 output levels.

Pixel data valid.

525p at 59.94 Hz. EAV/SAV synchro-

nization. EIA-770.2 output levels.

0x31

0x33

0x01

0x6C

Pixel data valid.

10-bit input enabled.

Table 107. 8-Bit 525p YCrCb In (EAV/SAV), YPrPb Out

Subaddress Setting Description

0x17

0x00

0x01

0x02

0x1C

0x20

Software reset.

Table 111. 8-Bit 625p YCrCb In (EAV/SAV), YPrPb Out

Subaddress Setting Description

All DACs enabled. PLL enabled (8×).

ED-DDR input mode. Luma data

clocked on falling edge of CLKIN.

0x17

0x00

0x01

0x02

0x1C

0x20

Software reset.

All DACs enabled. PLL enabled (8×).

0x30

0x31

0x04

0x01

525p at 59.94 Hz. EAV/SAV synchro-

nization. EIA-770.2 output levels.

ED-DDR input mode. Luma data

clocked on falling edge of CLKIN.

Pixel data valid.

0x30

0x31

0x1C

0x01

625p at 50 Hz. EAV/SAV synchroniza-

tion. EIA-770.2 output levels.

Pixel data valid.

Table 108. 10-Bit 525p YCrCb In (EAV/SAV), YPrPb Out

Subaddress Setting Description

0x17

0x00

0x01

0x02

0x1C

0x20

Software reset.

Table 112. 10-Bit 625p YCrCb In (EAV/SAV), YPrPb Out

Subaddress Setting Description

All DACs enabled. PLL enabled (8×).

ED-DDR input mode. Luma data

clocked on falling edge of CLKIN.

0x17

0x00

0x01

0x02

0x1C

0x20

Software reset.

All DACs enabled. PLL enabled (8×).

0x30

0x04

525p at 59.94 Hz. EAV/SAV synchro-

nization. EIA-770.2 output levels.

ED-DDR input mode. Luma data

clocked on falling edge of CLKIN.

0x31

0x33

0x01

0x6C

Pixel data valid.

0x30

0x1C

625p at 50 Hz. EAV/SAV synchroniza-

tion. EIA-770.2 output levels.

10-bit input enabled.

0x31

0x33

0x01

0x6C

Pixel data valid.

10-bit input enabled.

Rev. H | Page 100 of 108

Data Sheet

ADV7390/ADV7391/ADV7392/ADV7393

Table 113. 8-Bit 625p YCrCb In (EAV/SAV), RGB Out

Table 114. 10-Bit 625p YCrCb In (EAV/SAV), RGB Out

Subaddress Setting Description

0x17

0x00

0x01

0x02

0x1C

0x20

Software reset.

0x17

0x00

0x01

0x02

0x1C

0x20

Software reset.

All DACs enabled. PLL enabled (8×).

ED-DDR input mode. Luma data

clocked on falling edge of CLKIN.

ED-DDR input mode. Luma data

clocked on falling edge of CLKIN.

0x02

0x30

0x31

0x10

0x1C

0x01

RGB output enabled. RGB output sync

enabled.

0x02

0x30

0x10

0x1C

RGB output enabled. RGB output sync

enabled.

625p at 50 Hz. EAV/SAV synchroni-

zation. EIA-770.2 output levels.

625p at 50 Hz. EAV/SAV synchroni-

zation. EIA-770.2 output levels.

Pixel data valid.

0x31

0x33

0x01

0x6C

Pixel data valid.

10-bit input enabled.

HIGH DEFINITION

Table 115. HD Configuration Scripts

Input Format

Input Data Width

Synchronization Format

EAV/SAV

HSYNC VSYNC

/

EAV/SAV

HSYNC VSYNC

/

Input Color Space

YCrCb

Output Color Space

Table Number

Table 124

Table 126

Table 125

Table 127

Table 116

Table 117

Table 118

Table 119

720p

8-bit DDR

YPrPb

RGB

YPrPb

RGB

YPrPb

RGB

10-bit DDR

16-bit SDR

YCrCb

720p

YCrCb

RGB

1080i

8-bit DDR

10-bit DDR

16-bit SDR

EAV/SAV

YCrCb

YPrPb

RGB

YPrPb

RGB

YPrPb

RGB

Table 128

Table 130

Table 129

Table 131

Table 120

Table 121

Table 122

Table 123

HSYNC VSYNC

/

EAV/SAV

HSYNC VSYNC

RGB

/

Rev. H | Page 101 of 108

ADV7390/ADV7391/ADV7392/ADV7393

Data Sheet

Table 116. 16-Bit 720p YCrCb In (EAV/SAV), YPrPb Out

Subaddress Setting Description

Table 121. 16-Bit 1080i YCrCb In, YPrPb Out

Subaddress Setting Description

0x17

0x00

0x01

0x30

0x02

0x1C

0x10

0x2C

Software reset.

0x17

0x00

0x01

0x30

0x02

0x1C

0x10

0x18

Software reset.

All DACs enabled. PLL enabled (4×).

HD-SDR input mode.

All DACs enabled. PLL enabled (4×).

HD-SDR input mode.

720p at 60 Hz/59.94 Hz. EAV/SAV syn-

chronization. EIA-770.3 output levels.

1080i at 30 Hz/29.97 Hz. HSYNC/VSYNC

synchronization. EIA-770.3 output levels.

0x31

0x01

Pixel data valid. 4× oversampling.

0x31

0x01

Pixel data valid. 4× oversampling.

Table 122. 16-Bit 1080i YCrCb In (EAV/SAV), RGB Out

Subaddress Setting Description

Table 117. 16-Bit 720p YCrCb In, YPrPb Out

Subaddress Setting Description

0x17

0x00

0x01

0x02

0x1C

0x10

Software reset.

0x17

0x00

0x01

0x30

0x02

0x1C

0x10

0x28

Software reset.

All DACs enabled. PLL enabled (4×).

HD-SDR input mode.

All DACs enabled. PLL enabled (4×).

HD-SDR input mode.

RGB output enabled. RGB output sync

enabled.

720p at 60 Hz/59.94 Hz. HSYNC/VSYNC

synchronization. EIA-770.3 output levels.

Pixel data valid. 4× oversampling.

0x30

0x31

0x6C

0x01

1080i at 30 Hz/29.97 Hz. EAV/SAV syn-

chronization. EIA-770.3 output levels.

0x31

0x01

Pixel data valid. 4× oversampling.

Table 118. 16-Bit 720p YCrCb In (EAV/SAV), RGB Out

Subaddress Setting Description

Table 123. 16-Bit 1080i YCrCb In, RGB Out

Subaddress Setting Description

0x17

0x00

0x01

0x02

0x1C

0x10

Software reset.

All DACs enabled. PLL enabled (4×).

HD-SDR input mode.

0x17

0x00

0x01

0x02

0x1C

0x10

Software reset.

All DACs enabled. PLL enabled (4×).

HD-SDR input mode.

RGB output enabled. RGB output sync

enabled.

RGB output enabled. RGB output sync

enabled.

0x30

0x31

0x2C

0x01

720p at 60 Hz/59.94 Hz. EAV/SAV syn-

chronization. EIA-770.3 output levels.

0x30

0x31

0x18

0x01

1080i at 30 Hz/29.97 Hz. HSYNC/VSYNC

synchronization. EIA-770.3 output levels.

Pixel data valid. 4× oversampling.

Table 119. 16-Bit 720p YCrCb In, RGB Out

Subaddress Setting Description

Table 124. 8-Bit 720p YCrCb In (EAV/SAV), YPrPb Out

Subaddress Setting Description

0x17

0x00

0x01

0x02

0x1C

0x10

Software reset.

0x17

0x00

0x01

0x02

0x1C

0x20

Software reset.

All DACs enabled. PLL enabled (4×).

HD-SDR input mode.

All DACs enabled. PLL enabled (4×).

HD-DDR input mode. Luma data

clocked on falling edge of CLKIN.

RGB output enabled. RGB output sync

enabled.

0x30

0x31

0x2C

0x01

720p at 60 Hz/59.94 Hz. EAV/SAV syn-

chronization. EIA-770.3 output levels.

0x30

0x31

0x28

0x01

720p at 60 Hz/59.94 Hz. HSYNC/VSYNC

synchronization. EIA-770.3 output levels.

Pixel data valid. 4× oversampling.

Table 125. 10-Bit 720p YCrCb In (EAV/SAV), YPrPb Out

Subaddress Setting Description

Table 120. 16-Bit 1080i YCrCb In (EAV/SAV), YPrPb Out

Subaddress Setting Description

0x17

0x00

0x01

0x02

0x1C

0x20

Software reset.

0x17

0x00

0x01

0x30

0x02

0x1C

0x10

0x6C

Software reset.

All DACs enabled. PLL enabled (4×).

HD-SDR input mode.

HD-DDR input mode. Luma data

clocked on falling edge of CLKIN.

1080i at 30 Hz/29.97 Hz. EAV/SAV syn-

chronization. EIA-770.3 output levels.

0x30

0x2C

720p at 60 Hz/59.94 Hz. EAV/SAV syn-

chronization. EIA-770.3 output levels.

0x31

0x01

Pixel data valid. 4× oversampling.

0x31

0x33

0x01

0x6C

Pixel data valid. 4× oversampling.

10-bit input enabled.

Rev. H | Page 102 of 108

Data Sheet

ADV7390/ADV7391/ADV7392/ADV7393

Table 126. 8-Bit 720p YCrCb In (EAV/SAV), RGB Out

Table 129. 10-Bit 1080i YCrCb In (EAV/SAV), YPrPb Out

Subaddress Setting Description

0x17

0x00

0x01

0x02

0x1C

0x20

Software reset.

0x17

0x00

0x01

0x02

0x1C

0x20

Software reset.

All DACs enabled. PLL enabled (4×).

HD-DDR input mode. Luma data

clocked on falling edge of CLKIN.

HD-DDR input mode. Luma data

clocked on falling edge of CLKIN.

0x02

0x30

0x31

0x10

0x2C

0x01

RGB output enabled. RGB output sync

enabled.

0x30

0x6C

1080i at 30 Hz/29.97 Hz. EAV/SAV syn-

chronization. EIA-770.3 output levels.

720p at 60 Hz/59.94 Hz. EAV/SAV syn-

chronization. EIA-770.3 output levels.

0x31

0x33

0x01

0x6C

Pixel data valid. 4× oversampling.

10-bit input enabled.

Pixel data valid. 4× oversampling.

Table 130. 8-Bit 1080i YCrCb In (EAV/SAV), RGB Out

Subaddress Setting Description

Table 127. 10-Bit 720p YCrCb In (EAV/SAV), RGB Out

Subaddress Setting Description

0x17

0x00

0x01

0x02

0x1C

0x20

Software reset.

0x17

0x00

0x01

0x02

0x1C

0x20

Software reset.

All DACs enabled. PLL enabled (4×).

HD-DDR input mode. Luma data

clocked on falling edge of CLKIN.

HD-DDR input mode. Luma data

clocked on falling edge of CLKIN.

0x02

0x30

0x31

0x10

0x6C

0x01

RGB output enabled. RGB output sync

enabled.

0x02

0x30

0x10

0x2C

RGB output enabled. RGB output sync

enabled.

1080i at 30 Hz/29.97 Hz. EAV/SAV syn-

chronization. EIA-770.3 output levels.

720p at 60 Hz/59.94 Hz. EAV/SAV syn-

chronization. EIA-770.3 output levels.

Pixel data valid. 4× oversampling.

0x31

0x33

0x01

0x6C

Pixel data valid. 4× oversampling.

10-bit input enabled.

Table 131. 10-Bit 1080i YCrCb In (EAV/SAV), RGB Out

Subaddress Setting Description

Table 128. 8-Bit 1080i YCrCb In (EAV/SAV), YPrPb Out

Subaddress Setting Description

0x17

0x00

0x01

0x02

0x1C

0x20

Software reset.

All DACs enabled. PLL enabled (4×).

0x17

0x00

0x01

0x02

0x1C

0x20

Software reset.

HD-DDR input mode. Luma data

clocked on falling edge of CLKIN.

All DACs enabled. PLL enabled (4×).

HD-DDR input mode. Luma data

clocked on falling edge of CLKIN.

0x02

0x30

0x10

0x6C

RGB output enabled. RGB output sync

enabled.

0x30

0x31

0x6C

0x01

1080i at 30 Hz/29.97 Hz. EAV/SAV syn-

chronization. EIA-770.3 output levels.

1080i @ 30 Hz/29.97 Hz. EAV/SAV syn-

chronization. EIA-770.3 output levels.

Pixel data valid. 4× oversampling.

0x31

0x33

0x01

0x6C

Pixel data valid. 4× oversampling.

10-bit input enabled.

Rev. H | Page 103 of 108

ADV7390/ADV7391/ADV7392/ADV7393

ADV739X EVALUATION BOARD

Data Sheet

These two boards allow the user to perform a complete

To accommodate evaluation of the ADV7390/ADV7391/

ADV7392/ADV7393, Analog Devices provides a two-board

solution. The ADV739x evaluation platform front-end board

contains an Analog Devices decoder (ADV7403) and an FPGA.

The back-end board (where the actual ADV739x is attached) is

connected to the front-end board through a connector.

evaluation of the part, although it is also possible to order only

the back-end board. Note that these two boards must be

ordered separately.

For more information about the evaluation boards, see the

evaluation board documentation available on the Analog

Devices product web page.

ADV739x EVALUATION PLATFORM

FRONT FRONT-END BOARD

ADV739x EVALUATION BOARD

EXPANSION PORT

CVBS

RGB

CVBS

ADV7403

DECODER

RGB

FPGA

ADV739x

ENCODER

YPrPb

YC

USB

Figure 144. ADV739x Front-End and Back-End Evaluation Boards

Rev. H | Page 104 of 108

Data Sheet

ADV7390/ADV7391/ADV7392/ADV7393

OUTLINE DIMENSIONS

5.10

5.00 SQ

4.90

0.60 MAX

PIN 1

INDICATOR

25

32

24

1

0.50

BSC

PIN 1

INDICATOR

4.75

BSC SQ

3.25

3.10 SQ

2.95

EXPOSED

PAD

17

8

16

9

0.50

0.40

0.30

0.25 MIN

TOP VIEW

BOTTOM VIEW

3.50 REF

0.80 MAX

0.65 TYP

12° MAX

1.00

0.85

0.80

0.05 MAX

0.02 NOM

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

COPLANARITY

0.08

0.30

0.25

0.18

SEATING

PLANE

SECTION OF THIS DATA SHEET.

0.20 REF

COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2

Figure 145. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

5 mm × 5 mm Body, Very Thin Quad

(CP-32-2)

Dimensions shown in millimeters

5.10

5.00 SQ

4.90

0.30

0.25

0.18

PIN 1

INDICATOR

PIN 1

INDICATOR

25

32

24

1

0.50

BSC

3.45

3.30 SQ

3.15

EXPOSED

PAD

17

8

16

9

0.50

0.40

0.30

0.25 MIN

TOP VIEW

BOTTOM VIEW

3.50 REF

0.80

0.75

0.70

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

0.05 MAX

0.02 NOM

COPLANARITY

0.08

SECTION OF THIS DATA SHEET.

SEATING

PLANE

0.20 REF

COMPLIANT TO JEDEC STANDARDS MO-220-WHHD.

Figure 146. 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ]

5 mm × 5 mm Body, Very Very Thin Quad

(CP-32-13)

Dimensions shown in millimeters

Rev. H | Page 105 of 108

ADV7390/ADV7391/ADV7392/ADV7393

Data Sheet

6.10

6.00 SQ

5.90

0.60 MAX

PIN 1

INDICATOR

31

30

40

1

5.85

5.75 SQ

5.65

0.50

BSC

PIN 1

INDICATOR

4.25

4.10 SQ

3.95

EXPOSED

PAD

(BOTTOM VIEW)

10

11

21

20

0.50

0.40

0.30

0.20 MIN

TOP VIEW

4.50 REF

0.80 MAX

0.65 TYP

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

12° MAX

1.00

0.85

0.80

0.05 MAX

0.02 NOM

SECTION OF THIS DATA SHEET.

COPLANARITY

0.08

0.20 REF

0.30

0.23

0.18

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-2

Figure 147. 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

6 mm × 6 mm Body, Very Thin Quad

(CP-40-1)

Dimensions shown in millimeters

2.565

2.525

2.485

3

2

1

5

4

A

BALL A1

IDENTIFIER

B

C

D

E

F

3.045

3.005

2.965

2.50

REF

0.50

BALL PITCH

BOTTOM VIEW

(BALL SIDE UP)

TOP VIEW

(BALL SIDE DOWN)

0.390

0.360

0.330

2.00 REF

0.660

0.600

0.540

SIDE VIEW

COPLANARITY

0.05

0.360

0.320

0.280

SEATING

PLANE

0.270

0.240

0.210

Figure 148. 30-Ball Wafer Level Chip Scale Package [WLCSP]

(CB-30-3)

Dimensions shown in millimeters

Rev. H | Page 106 of 108

Data Sheet

ADV7390/ADV7391/ADV7392/ADV7393

ORDERING GUIDE

Temperature

Range

Macrovision³

Anti-Taping

Model^{1, 2}

Package Description

Package Option

CP-32-2

ADV7390BCPZ

−40°C to +85°C

−40°C to +105°C

−40°C to +85°C

−40°C to +105°C

−40°C to +85°C

−40°C to +105°C

−40°C to +85°C

−40°C to +105°C

Yes

No

Yes

No

N/A

Yes

No

Yes

No

32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

ADV7390BCPZ-REEL

ADV7390WBCPZ

ADV7390WBCPZ-RL

ADV7390BCBZ-A-RL

ADV7391BCPZ

ADV7391BCPZ-REEL

ADV7391WBCPZ

ADV7391WBCPZ-RL

ADV7391BCBZ-A-RL

ADV7392BCPZ

ADV7392BCPZ-REEL

ADV7392BCPZ-3REEL

ADV7392WBCPZ

ADV7392WBCPZ-REEL

ADV7393BCPZ

ADV7393BCPZ-REEL

ADV7393WBCPZ

ADV7393WBCPZ-REEL

EVAL-ADV739xFEZ

EVAL-ADV7390EBZ

EVAL-ADV7391EBZ

EVAL-ADV7392EBZ

EVAL-ADV7393EBZ

32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-32-13

30-Ball Wafer Level Chip Scale Package [WLCSP]

32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

CB-30-3

CP-32-2

32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-32-13

30-Ball Wafer Level Chip Scale Package [WLCSP]

40-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

ADV739x Evaluation Platform Front-End Board

ADV7390 Evaluation Board

CB-30-3

CP-40-1

ADV7391 Evaluation Board

ADV7392 Evaluation Board

ADV7393 Evaluation Board

¹Z = RoHS Compliant Part.

²W = Qualified for Automotive Applications.

³Macrovision-enabled ICs require the buyer to be an approved licensee (authorized buyer) of ICs that are able to output Macrovision Rev 7.1.L1-compliant video.

AUTOMOTIVE PRODUCTS

The ADV7390W, ADV7391W, ADV7392W, and ADV7393W models are available with controlled manufacturing to support the quality

and reliability requirements of automotive applications. Note that these automotive models may have specifications that differ from the

commercial models; therefore, designers should review the Specifications section of this data sheet carefully. Only the automotive grade

products shown are available for use in automotive applications. Contact your local Analog Devices account representative for specific

product ordering information and to obtain the specific Automotive Reliability reports for these models.

Rev. H | Page 107 of 108

ADV7390/ADV7391/ADV7392/ADV7393

NOTES

Data Sheet

I²C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).

registered trademarks are the property of their respective owners.

D06234-0-9/14(H)

Rev. H | Page 108 of 108


型号：	ADV7390_15
厂家：	ADI
描述：	Low Power, Chip Scale, 10-Bit SD/HD Video Encoder
文件：	总108页 (文件大小：1922K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADV7390_15 [ADI]

相关型号：

ADV7391

ADV7391BCPZ

ADV7391BCPZ-REEL

ADV7391EBZ

ADV7391WBCPZ

ADV7391WBCPZ-RL

ADV7391_15

ADV7392

ADV7392BCPZ

ADV7392BCPZ-3REEL

ADV7392BCPZ-REEL

ADV7392EBZ