ADV7401BSTZ-80 [ADI]
10-Bit, Integrated, Multiformat SDTV/HDTV Video Decoder and RGB Graphics Digitizer; 10位，集成，多格式SDTV / HDTV视频解码器和RGB图形数字化仪
| 型号： | ADV7401BSTZ-80 |
| 厂家： | 
ADI |
| 描述： | 10-Bit, Integrated, Multiformat SDTV/HDTV Video Decoder and RGB Graphics Digitizer |
| 文件： | 总20页 (文件大小：402K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
10-Bit, Integrated, Multiformat SDTV/HDTV
Video Decoder and RGB Graphics Digitizer
ADV7401
FEATURES
GENERAL DESCRIPTION
Four 10-bit ADCs sampling up to 140 MHz
(140 MHz speed grade only)
12 analog input channel mux
SCART fast blank support
Internal antialias filters
NTSC/PAL/SECAM color standards support
525p-/625p-component progressive scan support
720p-/1080i-component HDTV support
Digitizes RGB graphics up to 1280 × 1024 @ 75 Hz (SXGA)
(140 MHz speed grade only)
24-bit digital input port supports data from DVI/HDMI Rx IC
Any-to-any, 3 × 3 color-space conversion matrix
Industrial temperature range (−40°C to +85°C)
12-bit 4:4:4/8-bit 4:2:2 DDR pixel output interface
Programmable interrupt request output pin
VBI data slicer (including teletext)
The ADV7401 is a high quality, single chip, multiformat video
decoder and graphics digitizer. This multiformat decoder
supports the conversion of PAL, NTSC, and SECAM standards
in the form of composite or S-video into a digital ITU-R BT.656
format. The ADV7401 also supports the decoding of a
component RGB/YPrPb video signal into a digital YCrCb or
RGB pixel output stream. The support for component video
includes standards such as 525i, 625i, 525p, 625p, 720p, 1080i,
1250i, and many other HD and SMPTE standards. Graphic
digitization is also supported by the ADV7401; it is capable of
digitizing RGB graphics signals from VGA to SXGA rates and
converting them into a digital RGB or YCrCb pixel output
stream. SCART and overlay functionality are enabled by the
ADV7401’s ability to simultaneously process CVBS and
standard definition RGB signals. The mixing of these signals is
controlled by the fast blank pin.
The ADV7401 contains two main processing sections. The first
is the standard definition processor (SDP), which processes all
PAL, NTSC, and SECAM signal types. The second is the
component processor (CP), which processes YPrPb and RGB
component formats, including RGB graphics. For more specific
descriptions of the ADV7401 features, see the Detailed
Functionality and Detailed Description sections.
APPLICATIONS
LCD/DLP™ rear projection HDTVs
PDP HDTVs
CRT HDTVs
LCD/DLP front projectors
LCD TV (HDTV ready)
HDTV STBs with PVR
Hard-disk-based video recorders
Multiformat scan converters
DVD recorders with progressive scan input support
AVR receiver
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2005–2009 Analog Devices, Inc. All rights reserved.
ADV7401
TABLE OF CONTENTS
Features .............................................................................................. 1
SDP Pixel Data Output Modes ................................................. 13
CP Pixel Data Output Modes ................................................... 13
Composite and S-Video Processing......................................... 13
Component Video Processing.................................................. 14
RGB Graphics Processing ......................................................... 14
Digital Video Input Port............................................................ 14
General Features......................................................................... 14
Detailed Description...................................................................... 15
Analog Front End....................................................................... 15
Standard Definition Processor (SDP)...................................... 15
Component Processor ............................................................... 15
Pixel Input/Output Formatting .................................................... 17
Recommended External Loop Filter Components.................... 18
Typical Connection Diagram ....................................................... 19
Outline Dimensions....................................................................... 20
Ordering Guide .......................................................................... 20
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 3
Electrical Characteristics................................................................. 4
Video Specifications......................................................................... 6
Timing Characteristics..................................................................... 7
Analog Specifications....................................................................... 8
Absolute Maximum Ratings............................................................ 9
Stress Ratings ................................................................................ 9
Package Thermal Performance................................................... 9
Thermal Specifications ................................................................ 9
ESD Caution.................................................................................. 9
Pin Configuration and Function Descriptions........................... 10
Timing Diagrams............................................................................ 12
Detailed Functionality ................................................................... 13
Analog Front End....................................................................... 13
REVISION HISTORY
10/09—Rev. SpA to Rev. B
Changes to Endnote 8, Table 3........................................................ 7
Changes to Table 8.......................................................................... 15
Changes to Ordering Guide .......................................................... 20
9/05—Rev. Sp 0 to Rev. SpA
Deleted EDTV.....................................................................Universal
Added AVR Receiver to Applications Section.............................. 1
Changes to Table 3............................................................................ 7
Changes to Figure 2........................................................................ 10
Changes to Function Descriptions of Pin 37 and Pin 38 .......... 11
Change Pin 70 Type........................................................................ 11
Change to Crystal MHz Unit Value ............................................. 13
Added Pixel Input Information to Table 9 and Table 10........... 17
4/05—Revision Sp0: Initial Version
Rev. B | Page 2 of 20
ADV7401
FUNCTIONAL BLOCK DIAGRAM
OUTPUT FIFO AND FORMATTER
Figure. 1.
Rev. B | Page 3 of 20
ADV7401
ELECTRICAL CHARACTERISTICS
@ AVDD = 3.15 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.71 V to 1.89 V, nominal input range 1.6 V.
Operating temperature range, unless otherwise noted.
Table 1.
Parameter1, 2, 3
Symbol
Test Conditions
Min Typ
Max
Unit
STATIC PERFORMANCE4, 5
Resolution (each ADC)
Integral Nonlinearity
Integral Nonlinearity
Integral Nonlinearity
Integral Nonlinearity
Integral Nonlinearity
Differential Nonlinearity
Differential Nonlinearity
Differential Nonlinearity
Differential Nonlinearity
Differential Nonlinearity
DIGITAL INPUTS8
N
10
2.5
Bits
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
INL
INL
INL
INL
INL
DNL
DNL
DNL
DNL
DNL
BSL at 27 MHz (at a 10-bit level)
BSL at 54 MHz (at a 10-bit level)
BSL at 74 MHz (at a 10-bit level)
BSL at 110 MHz (at an 8-bit level)ꢀ
BSL at 135 MHz (at an 8-bit level)7
At 27 MHz (at a 10-bit level)
At 54 MHz (at a 10-bit level)
At 74 MHz (at a 10-bit level)
At 110 MHz (at an 8-bit level)ꢀ
At 135 MHz (at an 8-bit level)7
0.ꢀ
−0.ꢀ/+0.7
1.4
0.ꢁ
1.5
−0.2/+0.25
−0.2/+0.25
0.ꢁ
−0.2/+1.5
−0.ꢁ/+3.0
−0.ꢁꢁ/+2.5
Input High Voltageꢁ
Input Low Voltage10
Input High Voltage
Input Low Voltage
VIH
VIL
VIH
VIL
IIN
2
V
V
V
V
μA
μA
pF
0.8
HS_IN, VS_IN low trigger mode
HS_IN, VS_IN low trigger mode
Pins listed in Note 11
0.7
0.3
Input Current
−ꢀ0
−10
+ꢀ0
+10
10
All other input pins
Input Capacitance8
DIGITAL OUTPUTS
CIN
Output High Voltage12
Output Low Voltage12
High Impedance Leakage Current
VOH
VOL
ILEAK
ISOURCE = 0.4 mA
ISINK = 3.2 mA
Pins listed in Note 13
All other output pins
2.4
V
V
μA
μA
pF
0.4
ꢀ0
10
20
Output Capacitance8
POWER REQUIREMENTS8
Digital Core Power Supply
Digital I/O Power Supply
PLL Power Supply
COUT
DVDD
DVDDIO
PVDD
AVDD
IDVDD
1.ꢀ5 1.8
3.0 3.3
2
V
V
V
V
3.ꢀ
1.8ꢁ
3.45
1.71 1.8
3.15 3.3
105
137
10ꢀ
4
Analog Power Supply
Digital Core Supply Current
CVBS input sampling at 54 MHz
Graphics RGB sampling at 135 MHz
SCART RGB FB sampling at 54 MHz
CVBS input sampling at 54 MHz
Graphics RGB sampling at 135 MHz
CVBS input sampling at 54 MHz
Graphics RGB sampling at 135 MHz
CVBS input sampling at 54 MHz
Graphics RGB sampling at 135 MHz
SCART RGB FB sampling at 54 MHz
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
ms
Digital I/O Supply Current
PLL Supply Current
IDVDDIO
IPVDD
1ꢁ
11
12
ꢁꢁ
242
2ꢀꢁ
2.25
1ꢀ
Analog Supply Current14
IAVDD
Power-Down Current
Green Mode Power-Down
Power-Up Time
IPWRDN
IPWRDNG Sync bypass function
TPWRUP
20
1 The min/max specifications are guaranteed over this range.
2 Temperature range TMIN to TMAX: −40°C to +85°C (0°C to 70°C temperature range for ADV7401KSTZ-140).
Rev. B | Page 4 of 20
ADV7401
3 All specifications obtained using programming scripts with the following sequence included: Addr 0x0E - data 0x80, Addr 0x54 - data 0x00, Addr 0x0E - data 0x00.
4 All ADC linearity tests performed at input range of full scale – 12.5%, and at zero scale + 12.5%.
5 Max INL and DNL specifications obtained with part configured for component video input.
ꢀ Specification for ADV7401BSTZ-110 and ADV7401KSTZ-140 only.
7 Specification for ADV7401KSTZ-140 only.
8 Guaranteed by characterization.
ꢁ To obtain specified VIH level on Pin 38, Register 0x13 (wo) must be programmed with value 0x04. If Register 0x13 is programmed with value 0x00,
then VIH on Pin 38 = 1.2 V.
10 To obtain specified VIL level on Pin 38, Register 0x13 (wo) must be programmed with value 0x04. If Register 0x13 is programmed with value 0x00,
then VIL on Pin 38 = 0.4 V.
11 Pins 1, 2, 13, 14, 1ꢀ, 1ꢁ, 24, 2ꢁ, 30, 31, 32, 33, 34, 35, 45, 7ꢁ, 83, 84, 87, 88, ꢁ5, ꢁꢀ, ꢁ7, 100.
12
V
and VOL levels obtained using default drive strength value (0xD5) in Register Subaddress 0xF4.
OH
13 Pins 3, 13, 14, 1ꢁ, 24, 2ꢁ, 30, 31, 32, 33, 34, 45.
14 Analog current measurements for CVBS made with ADC0 powered up only, For RGB, ADC0, ADC1 and ADC2 powered up only, for SCART FB, all ADCs powered up.
Rev. B | Page 5 of 20
ADV7401
VIDEO SPECIFICATIONS
@ AVDD= 3.15 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.71 V to 1.89 V. Operating temperature range,
unless otherwise noted.
Table 2.
Parameter1, 2, 3
Symbol
Test Conditions
Min
Typ
Max
Unit
NONLINEAR SPECIFICATIONS
Differential Phase
Differential Gain
Luma Nonlinearity
NOISE SPECIFICATIONS
SNR Unweighted
DP
DG
LNL
CVBS input, modulated 5 step
CVBS input, modulated 5 step
CVBS input, 5 step
0.5
0.5
0.5
degree
%
%
Luma ramp
54
58
5ꢀ
ꢀ0
ꢀ0
dB
dB
dB
SNR Unweighted
Analog Front End Crosstalk
Luma flat field
LOCK TIME SPECIFICATIONS
Horizontal Lock Range
Vertical Lock Range
−5
40
+5
70
%
Hz
FSC Subcarrier Lock Range
Color Lock in Time
1.3
ꢀ0
kHz
line
%
Sync Depth Range4
20
5
200
200
Color Burst Range
%
Vertical Lock Time
2
100
field
line
Horizontal Lock Time
CHROMA SPECIFICATIONS
Hue Accuracy
Color Saturation Accuracy
Color AGC Range
HUE
CL_AC
1
1
degree
%
%
5
400
Chroma Amplitude Error
Chroma Phase Error
Chroma Luma Intermodulation
0.5
0.4
0.2
%
degree
%
LUMA SPECIFICATIONS
Luma Brightness Accuracy
Luma Contrast Accuracy
CVBS, 1 V input
CVBS, 1 V input
1
1
%
%
1 The min/max specifications are guaranteed over this range.
2 Temperature range TMIN to TMAX: −40°C to +85°C (0°C to 70°C temperature range for ADV7401KSTZ-140).
3 Guaranteed by characterization.
4 Nominal sync depth is 300 mV at 100% sync depth range.
Rev. B | Page ꢀ of 20
ADV7401
TIMING CHARACTERISTICS
@ AVDD = 3.15 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.71 V to 1.89 V. Operating temperature range,
unless otherwise noted.
Table 3.
Parameter1, 2, 3
Symbol Test Conditions
Min
Typ
Max
Unit
SYSTEM CLOCK AND CRYSTAL
Crystal Nominal Frequency
Crystal Frequency Stability
Horizontal Sync Input Frequency
LLC1 Frequency Range4
I2C PORT5
28.ꢀ3ꢀ3ꢀ
MHz
ppm
kHz
50
110
140
14.8
12.825
MHz
SCLK Frequency
400
kHz
μs
μs
μs
μs
ns
ns
ns
μs
SCLK Min Pulse Width High
SCLK Min Pulse Width Low
Hold Time (Start Condition)
Setup Time (Start Condition)
SDA Setup Time
SCLK and SDA Rise Time
SCLK and SDA Fall Time
Setup Time for Stop Condition
RESET FEATURE
t1
t2
t3
t4
t5
tꢀ
t7
t8
0.ꢀ
1.3
0.ꢀ
0.ꢀ
100
300
300
0.ꢀ
Reset Pulse Width
5
ms
CLOCK OUTPUTS
LLC1 Mark Space Ratio
DATA and CONTROL OUTPUTS
Data Output Transition Time SDR (SDP)ꢀ
tꢁ:t10
45:55
55:45 % duty cycle
t11
t12
t13
t14
t15
t1ꢀ
t17
t18
Negative clock edge
to start of valid data
End of valid data to
negative clock edge
End of valid data to
negative clock edge
Negative clock edge
to start of valid data
3.ꢀ
2.4
2.8
0.1
ns
ns
ns
ns
ns
ns
ns
ns
Data Output Transition Time SDR (SDP)ꢀ
Data Output Transition Time SDR (CP)7
Data Output Transition Time SDR (CP)7
Data Output Transition Time DDR (CP)7, 8
Data Output Transition Time DDR (CP)7, 8
Data Output Transition Time DDR (CP)7, 8
Data Output Transition Time DDR (CP)7, 8
Positive clock edge to −4 + TLLC1/4
end of valid data
Positive clock edge to 0.25 + TLLC1/4
start of valid data
Negative clock edge
to end of valid data
Negative clock edge
to start of valid data
−2.ꢁ5 + TLLC1/4
−0.5 + TLLC1/4
DATA and CONTROL INPUTS5
Input Setup Time (Digital Input Port)
t1ꢁ
t20
HS_IN, VS_IN
DE_IN, data inputs
HS_IN, VS_IN
ꢁ
2.2
7
ns
ns
ns
ns
Input Hold Time (Digital Input Port)
DE_IN, data inputs
2
1 The min/max specifications are guaranteed over this range.
2 Temperature range TMIN to TMAX: −40°C to +85°C (0°C to 70°C temperature range for ADV7401KSTZ-140).
3 Guaranteed by characterization.
4 Maximum LLC1 frequency is 80 MHz for ADV7401BSTZ-80 and is 110 MHz for ADV7401BSTZ-110.
5 TTL input values are 0 V to 3 V, with rise/fall times ≤3 ns, measured between the 10% and ꢁ0% points.
ꢀ SDP timing figures obtained using default drive strength value (0xD5) in Register Subaddress 0xF4.
7 CP timing figures obtained using max drive strength value (0xFF) in register subaddress 0xF4.
8 DDR timing specifications dependent on LLC1 output pixel clock; TLLC1/4 = ꢁ.25 ns at LLC1 = 27 MHz.
Rev. B | Page 7 of 20
ADV7401
ANALOG SPECIFICATIONS
@ AVDD = 3.1.5 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.71 V to 1.89 V. Operating temperature
range, unless otherwise noted. Recommended analog input video signal range: 0.5 V to 1.6 V, typically 1 V p-p.
Table 4.
Parameter1, 2, 3
Test Conditions
Min
Typ
Max
Unit
CLAMP CIRCUITRY
External Clamp Capacitor
Input Impedance4
Input Impedance of Pin 51 (FB)
CML
0.1
10
20
1.8ꢀ
μF
MΩ
kΩ
V
Clamps switched off
ADC Full-Scale Level
ADC Zero-Scale level
ADC Dynamic Range
Clamp Level (When Locked)
CML + 0.8 V
CML − 0.8 V
1.ꢀ
CML – 0.2ꢁ2 V
CML – 0.4 V
CML – 0.2ꢁ2 V
CML – 0 V
CML – 0.3 V
CML – 0.3 V
0.75
V
V
V
V
V
V
V
V
CVBS input
SCART RGB input (R, G, B signals)
S-Video input (Y signal)
S-Video input (C signal)
Component input (Y, Pr, Pb signals)
PC RGB input (R, G, B signals)
SDP only
SDP only
SDP only
SDP only
V
Large Clamp Source Current
Large Clamp Sink Current
Fine Clamp Source Current
Fine Clamp Sink Current
mA
mA
μA
μA
0.ꢁ
17
17
1 The min/max specifications are guaranteed over this range.
2 Temperature range TMIN to TMAX: −40°C to +85°C (0°C to 70°C temperature range for ADV7401KSTZ-140).
3 Guaranteed by characterization.
4 Except Pin 51 (FB).
Rev. B | Page 8 of 20
ADV7401
ABSOLUTE MAXIMUM RATINGS
STRESS RATINGS
Table 5.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameter
Rating
AVDD to AGND
DVDD to DGND
PVDD to AGND
DVDDIO to DGND
DVDDIO to AVDD
PVDD to DVDD
DVDDIO to PVDD
DVDDIO to DVDD
AVDD to PVDD
AVDD to DVDD
Digital Inputs Voltage to
DGND
Digital Outputs Voltage to
DGND
Analog Inputs to AGND
Maximum Junction
4 V
2.2 V
2.2 V
4 V
−0.3 V to +0.3 V
−0.3 V to +0.3 V
−0.3 V to +2 V
−0.3 V to +2 V
−0.3 V to +2 V
−0.3 V to +2 V
DGND − 0.3 V to DVDDIO + 0.3 V
PACKAGE THERMAL PERFORMANCE
To reduce power consumption when using the part the user is
advised to turn off any unused ADCs .
The junction temperature must always stay below the
maximum junction temperature (TJ MAX) of 125°C. This
equation shows how to calculate the junction temperature:
DGND − 0.3 V to DVDDIO + 0.3 V
AGND − 0.3 V to AVDD + 0.3 V
TJ = TA Max + (θJA × WMax
where:
A Max = 85°C.
JA = 30°C/W.
)
Temperature (TJ MAX
Storage Temperature Range
Infrared Reflow Soldering
(20 sec)
)
125°C
−ꢀ5°C to +150°C
T
θ
W
Max = ((AVDD × IAVDD) + (DVDD × IDVDD) +
(DVDDIO × IDVDDIO) + (PVDD × IPVDD)).
2ꢀ0°C
THERMAL SPECIFICATIONS
Table 6.
Thermal Characteristics
Symbol
θJC
θJA
Test Conditions
Typ
7
30
Unit
°C/W
°C/W
Junction-to-Case Thermal Resistance
Junction-to-Ambient Thermal Resistance
4-layer PCB with solid ground plane
4-layer PCB with solid ground plane (still air)
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. B | Page ꢁ of 20
ADV7401
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
AIN12
AIN5
P32
PIN 1
2
P31
3
AIN11
AIN4
INT
4
CS/HS
5
AIN10
TEST0
CAPC2
CAPC1
BIAS
DGND
6
DVDDIO
7
P15
8
P14
9
P13
10
P12
AGND
CML
ADV7401
11
DGND
12
REFOUT
AVDD
CAPY2
CAPY1
AGND
TEST1
AIN3
DVDD
LQFP
TOP VIEW
(Not to Scale)
13
14
15
16
17
18
19
20
21
22
23
24
25
P29
P28
SFL/SYNC_OUT
SCLK2
DGND
DVDDIO
SDA2
P11
AIN9
AIN2
AIN8
P10
AIN1
P9
AIN7
P8
SOG
P27
FB
P7
Figure 2. Pin Configuration
Table 7. Pin Function Descriptions
Pin No.
5, 11, 17, 40, 8ꢁ
4ꢁ, 50, ꢀ0, ꢀꢀ
ꢀ, 18
12, 3ꢁ, ꢁ0
ꢀ3
Mnemonic
Type
Function
DGND
AGND
DVDDIO
DVDD
AVDD
PVDD
FB
G
G
P
P
P
P
I
Digital Ground.
Analog Ground.
Digital I/O Supply Voltage (3.3 V).
Digital Core Supply Voltage (1.8 V).
Analog Supply Voltage (3.3 V).
PLL Supply Voltage (1.8 V).
Fast Switch Overlay Input. This pin switches between CVBS and RGB
analog signals.
47, 48
51
54, 5ꢀ, 58, 72, 74, 7ꢀ, 53, 55,
57, 71, 73, 75
AIN1 to AIN12
I
Analog Video Input Channels.
42, 41, 28, 27, 2ꢀ, 25, 23, 22,
10, ꢁ, 8, 7, ꢁ4, ꢁ3, ꢁ2, ꢁ1
P2 to Pꢁ, P12 to P1ꢁ
O
Video Pixel Output Port.
33, 32, 31, 30, 2ꢁ, 24, 14, 13
44, 43, 21, 20, 45, 34, 2, 1,
P22 to P2ꢁ
P0 to P1, P10 to P11,
I/O
I
Video Input/Output Port
Video Pixel Input Port.
100, ꢁ7, ꢁꢀ, ꢁ5, 88, 87, 84, 83 P20 to P21, P31 to P40
3
INT
O
Interrupt. This pin can be active low or active high. When SDP/CP status
bits change this pin triggers. The set of events that triggers an interrupt
is under user control.
Rev. B | Page 10 of 20
ADV7401
Pin No.
Mnemonic
Type
Function
4
HS/CS
O
HS is a Horizontal Synchronization Output Signal (SDP and CP modes).
CS is a Digital Composite Synchronization Signal (and can be selected
while in CP mode).
ꢁꢁ
ꢁ8
VS
FIELD/DE
O
O
Vertical Synchronization Output Signal (SDP and CP modes).
Field Synchronization Output Signal (all interlaced video modes). This
pin also can be enabled as a Data Enable signal (DE) in CP mode to allow
direct connection to a HDMI/DVI Tx IC.
81, 1ꢁ
82, 1ꢀ
SDA1, SDA2
I/O
I
I2C Port Serial Data Input/Output Pins. SDA1 is the data line for the
control port and SDA2 is the data line for the VBI readback port.
I2C Port Serial Clock Input (max clock rate of 400 kHz). SCLK1 is the clock
line for the control port and SCLK2 is the clock line for the VBI data
readback port.
SCLK1, SCLK2
80
ALSB
I
This pin selects the I2C address for the ADV7401 control and VBI
readback ports. ALSB set to Logic 0 sets the address for a write to control
port of 0x40 and the readback address for the VBI port of 0x21. ALSB set
to a logic high sets the address for a write to control port of 0x42 and the
readback address for the VBI port of 0x23.
78
3ꢀ
RESET
LLC1
I
System Reset Input, Active Low. A minimum low reset pulse width of 5
ms is required to reset the ADV7401 circuitry.
LLC1 is a line-locked output clock for the pixel data (range is 12.825 MHz
to 140 MHz for ADV7401KSTZ-140; 12.825 MHz to 110 MHz for
ADV7401BSTZ-110; 12.825 MHz to 80 MHz for ADV7401BSTZ-80).
O
38
37
XTAL
I
Input pin for 28.ꢀ3ꢀ3ꢀ MHz crystal, or can be overdriven by an external
3.3 V 28.ꢀ3ꢀ3ꢀ MHz clock oscillator source to clock the ADV7401.
This pin should be connected to the 28.ꢀ3ꢀ3ꢀ MHz crystal or left as a no
connect if an external 3.3 V 28.ꢀ3ꢀ3ꢀ MHz clock oscillator source is used
to clock the ADV7401. In crystal mode, the crystal must be a
fundamental crystal.
XTAL1
O
4ꢀ
70
5ꢁ
15
ELPF
TEST0
TEST1
SFL/SYNC_OUT
O
NC
O
The recommend external loop filter must be connected to this ELPF pin.
This pin should be left unconnected or alternatively tied to AGND.
This pin should be left unconnected.
Subcarrier Frequency Lock (SFL). This pin contains a serial output stream
which can be used to lock the subcarrier frequency when this decoder is
connected to any Analog Devices digital video encoder. SYNC_OUT is
the sliced sync output signal available only in CP mode.
O
ꢀ4
ꢀ5
ꢀ1, ꢀ2
ꢀ8, ꢀꢁ
ꢀ7
REFOUT
CML
CAPY1, CAPY2
CAPC1, CAPC2
BIAS
O
O
I
I
O
Internal Voltage Reference Output.
Common-Mode Level Pin (CML) for the internal ADCs.
ADC Capacitor Network.
ADC Capacitor Network.
External Bias Setting Pin. Connect the recommended resistor (1.35 kΩ)
between pin and ground.
8ꢀ
HS_IN/CS_IN
I
Can be configured in CP mode to be either a digital HS input signal or a
digital CS input signal used to extract timing in a 5-wire or 4-wire RGB
mode.
85
7ꢁ
VS_IN
DE_IN
I
I
VS Input Signal. Used in CP mode for 5-wire timing mode.
Data Enable Input Signal. Used in 24-bit digital input port mode (for
example, processing 24-bit RGB data from a DVI Rx IC).
35
DCLK_IN
I
Clock Input Signal. Used in 24-bit digital input mode (for example,
processing 24-bit RGB data from a DVI Rx IC) and also in digital CVBS
input mode.
52
77
SOG
SOY
I
I
Sync on Green Input. Used in embedded sync mode.
Sync on Luma Input. Used in embedded sync mode.
Rev. B | Page 11 of 20
ADV7401
TIMING DIAGRAMS
t3
t5
t3
SDA1/SDA2
t6
t1
SCLK1/SCLK2
t2
t7
t4
t8
Figure 3. I2C Timing
t9
t10
LLC1
t11
t12
P2–P9, P12–P19,
P22–P29, VS, HS,
FIELD/DE,
SFL/SYNC_OUT
Figure 4. Pixel Port and Control SDR Output Timing (SD Core)
t9
t10
LLC1
t13
t14
P2–P9, P12–P19,
P22–P29
Figure 5. Pixel Port and Control SDR Output Timing (CP Core)
LLC1
t16
t18
t15
t17
P6–P9,
P12–P19
Figure 6. Pixel Port and Control DDR Output Timing (CP Core)
DCLK_IN
t20
t9
t10
HS_IN
VS_IN
DE_IN
CONTROL
INPUTS
P0–P1, P10–P11,
P20–P21, P22–P29,
P31–P32, P33–P40
t19
Figure 7. Digital Input Port and Control Input Timing
Rev. B | Page 12 of 20
ADV7401
DETAILED FUNCTIONALITY
ANALOG FRONT END
•
•
Proprietary architecture for locking to weak, noisy, and
unstable sources from VCRs and tuners
•
•
•
•
•
Four high quality 10-bit ADCs enable true 8-bit video
decoder
IF filter block compensates for high frequency luma
attenuation due to tuner SAW filter
12 analog input channel mux enables multisource
connection without the requirement of an external mux
•
•
•
Chroma transient improvement (CTI)
Luminance digital noise reduction (DNR)
Four current and voltage clamp control loops ensure any
dc offsets are removed from the video signal
Color controls include hue, brightness, saturation, contrast,
and Cr and Cb offset controls
SCART functionality and SD RGB overlay on CVBS
controlled by fast blank input
•
•
Certified Macrovision copy protection detection on
composite and S-video for all worldwide formats
(PAL/NTSC/SECAM)
Four internal antialias filters to remove out-of-band noise
on standard definition input video signals
SDP PIXEL DATA OUTPUT MODES
4× oversampling (54 MHz) for CVBS, S-video, and YUV
modes
•
•
•
8-bit ITU-R BT.656 4:2:2 YCrCb with embedded time
codes and/or HS, VS, and FIELD
•
•
•
Line-locked clock output (LLC)
Letterbox detection supported
16-bit YCrCb with embedded time codes and/or HS, VS,
and FIELD
Free-run output mode provides stable timing when no
video input is present
24-bit YCrCb with embedded time codes and/or HS, VS,
and FIELD
•
Vertical blanking interval data processor
CP PIXEL DATA OUTPUT MODES
TeleText
•
•
•
Single data rate (SDR) 8-bit 4:2:2 YCrCb for 525i, 625i
Video Programming System (VPS)
Vertical Interval Time Codes (VITC)
Closed captioning (CC) and extended data service (EDS)
Wide screen signaling (WSS)
Single data rate (SDR) 16-bit 4:2:2 YCrCb for all standards
Single data rate (SDR) 24-bit 4:4:4 YCrCb/RGB for all
standards
Copy generation management system (CGMS)
Gemstar™ 1×/2× electronic program guide compatible
•
•
Double data rate (DDR) 8-bit 4:2:2 YCrCb for all standards
•
•
Clocked from a single 28.63636 MHz crystal
Double data rate (DDR) 12-bit 4:4:4 YCrCb/RGB for all
standards
Subcarrier frequency lock (SFL) output for downstream
video encoder
COMPOSITE AND S-VIDEO PROCESSING
•
Support for NTSC (J, M, 4.43), PAL (B, D, I, G, H, M, N,
60) and SECAM B/D/G/K/L standards in the form of
CVBS and S-video
•
•
Differential gain typically 0.5%
Differential phase typically 0.5°
•
Superadaptive 2D 5-line comb filters for NTSC and PAL
give superior chrominance and luminance separation for
composite video
•
•
Full automatic detection and autoswitching of all
worldwide standards (PAL/NTSC/SECAM)
Automatic gain control with white peak mode ensures the
video is always processed without loss of the video
processing range
•
Adaptive digital line length tracking (ADLLT™)
Rev. B | Page 13 of 20
ADV7401
DIGITAL VIDEO INPUT PORT
COMPONENT VIDEO PROCESSING
•
Supports raw 8-bit CVBS data from digital tuner
•
•
Formats supported include 525i, 625i, 525p, 625p, 720p,
1080i, and many other HDTV formats
•
Support for 24-bit RGB input data from DVI Rx chip,
output converted to YCrCb 4:2:2
Automatic adjustments include gain (contrast) and offset
(brightness); manual adjustment controls are also
supported
•
Support for 24-bit 4:4:4, 16-bit 4:2:2 525i, 625i, 525p, 625p,
1080i, 720p, VGA to SXGA @ 60 Hz input data from
HDMI Rx chip, output converted to 16-bit 4:2:2 YCrCb
•
•
•
•
Support for analog component YPrPb/RGB video formats
with embedded sync or with separate HS, VS, or CS
GENERAL FEATURES
Any-to-any, 3 × 3 color space conversion matrix supports
YCrCb-to-RGB and RGB-to-YCrCb
•
HS, VS, and FIELD output signals with programmable
position, polarity, and width
Standard identification (STDI) enables system level
component format detection
INT
, signals
•
Programmable interrupt request output pin,
SDP/CP status changes
Supports two I2C host port interfaces (control and VBI)
Synchronization source polarity detector (SSPD) deter-
mines the source and polarity of the synchronization
signals that accompany the input video
•
•
Low power consumption: 1.8 V digital core, 3.3 V analog
and digital I/O, low power power-down mode, and green
PC mode
•
•
•
Certified Macrovision copy protection detection on
component formats (525i, 625i, 525p, and 625p)
•
Industrial temperature range (−40°C to +85°C)
(except ADV7401KSTZ-140)
Free-run output mode provides stable timing when no
video input is present
•
•
140 MHz speed grade (ADV7401KST-140)
100-lead, 14 mm × 14 mm, Pb-free LQFP
Arbitrary pixel sampling support for nonstandard video
sources
RGB GRAPHICS PROCESSING
•
140 MSPS conversion rate supports RGB input resolutions
up to 1280 × 1024 @ 75 Hz (SXGA); (110 MSPS conversion
rate for ADV7401BSTZ-110); (80 MSPS conversion rate for
ADV7401BSTZ-80)
•
Automatic or manual clamp and gain controls for graphics
modes
•
•
•
Contrast and brightness controls
32-phase DLL allows optimum pixel clock sampling
Automatic detection of sync source and polarity by SSPD
block
•
•
Standard identification is enabled by STDI block
RGB can be color space converted to YCrCb and
decimated to a 4:2:2 format for video centric backend IC
interfacing
•
•
Data enable (DE) output signal supplied for direct
connection to HDMI/DVI Tx IC
Arbitrary pixel sampling support for nonstandard video
sources
Rev. B | Page 14 of 20
ADV7401
DETAILED DESCRIPTION
ANALOG FRONT END
The SDP has an IF filter block that compensates for attenuation
in the high frequency luma spectrum due to tuner SAW filter.
The ADV7401 analog front end comprises four 10-bit ADCs
that digitize the analog video signal before applying it to the
SDP or CP (see Table 8 for sampling rates). The analog front
end uses differential channels to each ADC to ensure high
performance in a mixed-signal application.
The SDP has specific luminance and chrominance parameter
control for brightness, contrast, saturation, and hue.
The ADV7401 implements a patented adaptive-digital-line-
length-tracking (ADLLT) algorithm to track varying video
line lengths from sources such as a VCR. ADLLT enables the
ADV7401 to track and decode poor quality video sources
such as VCRs, noisy sources from tuner outputs, VCD players,
and camcorders. The SDP also contains a chroma transient
improvement (CTI) processor. This processor increases the
edge rate on chroma transitions, resulting in a sharper
video image.
The front end also includes a 12-channel input mux that enables
multiple video signals to be applied to the ADV7401. Current
and voltage clamps are positioned in front of each ADC to
ensure that the video signal remains within the range of the
converter. Fine clamping of the video signals is performed
downstream by digital fine clamping in either the CP or SDP.
Optional antialiasing filters are positioned in front of each
ADC. These filters can be used to band-limit standard
definition video signals, removing spurious, out-of-band noise.
The SDP can process a variety of VBI data services, such as
TeleText, closed captioning (CC), wide screen signaling (WSS),
video programming system (VPS), vertical interval time codes
(VITC), copy generation management system (CGMS),
Gemstar 1×/2×, and extended data service (XDS). The
ADV7401 SDP section has a Macrovision 7.1 detection circuit
that allows it to detect Types I, II, and III protection levels. The
decoder is also fully robust to all Macrovision signal inputs.
The ADCs are configured to run in 4× oversampling mode
when decoding composite and S-video inputs; 2× oversampling
is performed for component 525i, 625i, 525p, and 625p sources.
All other video standards are 1× oversampled. Oversampling
the video signals reduces the cost and complexity of external
anti-aliasing filters with the benefit of an increased signal-to-
noise ratio (SNR).
COMPONENT PROCESSOR
The ADV7401 can support simultaneous processing of CVBS
and RGB standard definition signals to enable SCART compat-
ibility and overlay functionality. A combination of CVBS and
RGB inputs can be mixed and output under control of I2C
registers and the fast blank pin.
The CP section is capable of decoding/digitizing a wide range of
component video formats in any color space. Component video
standards supported by the CP are 525i, 625i, 525p, 625p, 720p,
1080i, 1250i, VGA up to SXGA @ 75 Hz (ADV7401KSTZ-140
only), and many other standards not listed here.
Table 8. Maximum ADC Sampling Rates
The CP section of the ADV7401 contains an AGC block.
When no embedded sync is present, the video gain can be set
manually. The AGC section is followed by a digital clamp
circuit that ensures the video signal is clamped to the correct
blanking level. Automatic adjustments within the CP include
gain (contrast) and offset (brightness); manual adjustment
controls are also supported.
Model
Maximum ADC Sampling Rate
ADV7401BSTZ-80
ADV7401BSTZ-110
ADV7401WBSTZ-110
ADV7401KSTZ-140
80 MHz
110 MHz
110 MHz
140 MHz
STANDARD DEFINITION PROCESSOR (SDP)
A fully programmable, any-to-any, 3 × 3 color space conversion
matrix is placed between the analog front end and the CP
section. This enables YPrPb-to-RGB and RGB-to-YCrCb
conversions. Many other standards of color space can be
implemented using the color space converter.
The SDP section is capable of decoding a large selection of
baseband video signals in composite S-video and YUV formats.
The video standards supported by the SDP include PAL
B/D/I/G/H, PAL60, PAL M, PAL N, NTSC M/J, NTSC 4.43, and
SECAM B/D/G/K/L. The ADV7401 can automatically detect
the video standard and process it accordingly.
The SDP has a 5-line superadaptive 2D comb filter that gives
superior chrominance and luminance separation when decod-
ing a composite video signal. This highly adaptive filter auto-
matically adjusts its processing mode according to video
standard and signal quality with no user intervention required.
Rev. B | Page 15 of 20
ADV7401
The output section of the CP is highly flexible. It can be config-
ured in single data rate mode (SDR) with one data packet per
clock cycle or in a double data rate (DDR) mode where data is
presented on the rising and falling edges of the clock. In SDR
mode, a 16-bit 4:2:2 or 24-bit 4:4:4 output is possible. In these
modes HS, VS, and FIELD/DE (where applicable) timing refer-
ence signals are provided. In DDR mode, the ADV7401 can be
configured in an 8-bit 4:2:2 YCrCb or 12-bit 4:4:4 RGB/ YCrCb
pixel output interface with corresponding timing signals.
The CP section contains circuitry to enable the detection of
Macrovision encoded YPrPb signals for 525i, 625i, 525p, and
625p. It is designed to be fully robust when decoding these
types of signals.
VBI extraction of CGMS data is performed by the CP section
of the ADV7401 for interlaced, progressive, and high definition
scanning rates. The data extracted can be read back over the
I2C interface. For more detailed product information about the
ADV7401, contact your local ADI sales office or email
video.products@analog.com.
The ADV7401 is capable of supporting an external DVI/
HDMI receiver. The digital interface expects 24-bit 4:4:4 or
16-bit 4:2:2 bit data (either graphics RGB or component video
YCrCb), accompanied by HS, VS, DE, and a fully synchronous
clock signal. The data is processed in the CP and output as
16-bit 4:2:2 YCrCb data.
Rev. B | Page 1ꢀ of 20
ADV7401
PIXEL INPUT/OUTPUT FORMATTING
Table 9. SDP, CP Pixel Input/Output Pin Map (P19 to P0)
Processor, Format,
Pixel Port Pins P[19:0]
and Mode
19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
SDP
Video out, 8-bit,
4:2:2
YCrCb[7:0]OUT
Y[7:0]OUT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
SDP
Video out,
16-bit, 4:2:2
CrCb[7:0]OUT
Cb[7:0]OUT
-
-
SDP
Video out,
Y[7:0]OUT
24-bit, 4:4:4
SM-SDP
Digital tuner
input[1]
Output choices are the same as video out 16-bit or pseudo 8-bit DDR
CP
CP
8-bit, 4:2:2, DDR D7 D6 D5 D4 D3 D2 D1 D0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
12-bit, 4:4:4, RGB D7 D6 D5 D4 D3 D2 D1 D0
DDR
D11 D10 D9 D8
-
-
-
-
-
-
-
CP
Video out,
16-bit, 4:2:2
CHA[7:0]OUT (for example, Y[7:0])
CHA[7:0]OUT (for example, G[7:0])
CHA[7:0]OUT (for example, Y[7:0])
-
-
-
CHB/C[7:0]OUT (for example, Cr/Cb[7:0])
CHB[7:0]OUT (for example, B[7:0])
CP
Video out,
24-bit, 4:4:4
-
SM-CP
HDMI receiver
support, 24-bit,
4:4:4 input
R[5:4]IN
CHB/C[7:0]OUT (for example, Cr/Cb[7:0])
R[1:0]IN
SM-CP
HDMI receiver
support, 16-bit,
pass-through
CHA[7:0]OUT (for example, Y[7:0])
-
-
CHB/C[7:0]OUT (for example, Cr/Cb[7:0])
-
-
Table 10. SDP, CP Pixel Input/Output Pin Map (P40 to P20)
Processor, Format,
Pixel Port Pins P[40:31], P[29:20]
and Mode
40
39 38 37 36 35 34 33 32 31 29 28 27 26 25 24 23 22 21 20
SDP
Video out, 8-bit,
4:2:2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
SDP
SDP
Video out, 16-bit,
4:2:2
Video out, 24-bit,
4:4:4
Cr[7:0]OUT
SM-SDP Digital tuner
input[1]
DCVBS[7:0]IN
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
CP
8-bit, 4:2:2, DDR
-
-
-
-
-
-
-
-
CP
12-bit, 4:4:4, RGB
DDR
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
CP
Video out, 16-bit,
4:2:2
CP
Video out, 24-bit,
4:4:4 input
CHC[7:0]OUT (for example, R[7:0])
B[7:0]IN
SM-CP
HDMI receiver
support, 24-bit,
4:4:4 input
G[7:0]IN
R[7:6]IN
R[3:2]IN
SM-CP
HDMI receiver
support, 16-bit,
pass-through
CHA[7:0]IN
-
-
CHB/C[7:0]IN
-
-
Rev. B | Page 17 of 20
ADV7401
RECOMMENDED EXTERNAL LOOP FILTER
COMPONENTS
The external loop filter components for the ELPF pin should
be placed as close as possible to the respective pins. Figure 8
shows the recommended component values.
PIN 46–ELPF
1.69kΩ
10nF
82nF
PVDD = 1.8V
Figure 8. ELPF Components
Rev. B | Page 18 of 20
ADV7401
TYPICAL CONNECTION DIAGRAM
D D D I O V
D D D I O V
V S D S
V S D S
V S D S
1 8
6
8 9
4 0
1 1
D D D V
D D D V
D D D V
9 0
3 9
1 2
O
O
V S D S I
V S D S I
1 7
5
P V S S
5 0
D D A V
6 3
P V S S
4 9
D
D
P V D
P V D
4 8
4 7
V S A S
V S A S
T E S T 0
6 0
6 6
7 0
Ω 7 k 2 .
Ω 7 k 2 .
Ω 5 6
Ω 7 5
Ω 7 5
Ω 7 5
Ω 7 5
Ω 7 5
Ω 7 5
Ω 7 5
Ω 7 5
Ω 7 5
Figure 9. ADV7401
Rev. B | Page 1ꢁ of 20
ADV7401
OUTLINE DIMENSIONS
16.20
16.00 SQ
15.80
1.60 MAX
0.75
0.60
0.45
100
1
76
75
PIN 1
14.20
14.00 SQ
13.80
TOP VIEW
(PINS DOWN)
1.45
1.40
1.35
0.20
0.09
7°
3.5°
0°
25
51
50
0.15
0.05
26
SEATING
PLANE
0.08
0.27
0.22
0.17
COPLANARITY
VIEW A
0.50
BSC
LEAD PITCH
VIEW A
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MS-026-BED
Figure 10. 100-Lead Low Profile Quad Flat Package [LQFP]
(ST-100-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
ADV7401BSTZ-802
ADV7401BSTZ-1102
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
0°C to 70°C
Package Description
Package Option
ST-100-1
100-Lead Low Profile Quad Flat Package (LQFP)
100-Lead Low Profile Quad Flat Package (LQFP)
ST-100-1
3
ADV7401WBSTZ-1102
100-Lead Low Profile Quad Flat Package (LQFP)
100-Lead Low Profile Quad Flat Package (LQFP)
Evaluation Board
ST-100-1
ADV7401KSTZ-1402
EVAL-ADV7401EBZ2
ST-100-1
1 The ADV7401 is a Pb-free, environmentally friendly product. It is manufactured using the most up-to-date materials and processes. The coating on the leads of each
device is 100% pure Sn electroplate. The device is suitable for Pb-free applications, and is able to withstand surface-mount soldering at up to 255°C ( 5°C). In addition,
it is backward compatible with conventional SnPb soldering processes. This means that the electroplated Sn coating can be soldered with SnPb solder pastes at
conventional reflow temperatures of 220°C to 235°C.
2 Z = RoHS Compliant Part.
3 Automotive Product.
Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent
Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
©2005–2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05340-0-10/09(B)
Rev. B | Page 20 of 20
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