ADV7482_技术文档

Integrated Video Decoder

and HDMI Receiver

ADV7482

Data Sheet

Component video processor

FEATURES

Any-to-any 3 × 3 color space conversion (CSC) matrix

Contrast/brightness/hue/saturation video adjustment

Timing adjustments controls for horizontal sync

(HS)/vertical sync (VS)/data enable (DE) timing

Video mute function

Serial digital audio output interface

HDMI audio extraction support

Advanced audio muting feature

I²S-compatible, left justified and right justified audio

output modes

8-channel TDM output mode available

2 Mobile Industry Processor Interface (MIPI) Camera Serial

Interface 2 (CSI-2) transmitters

4-lane transmitter with 4 lanes, 2 lanes, and 1 lane muxing

options for HDMI/SDP/digital input port sources

1-lane transmitter for standard definition processor (SDP)

sources

8-bit digital input/output port

General

2-wire serial microprocessor unit (MPU) interface (I²C

compatible)

−40°C to +85°C temperature grade

100-ball, 9 mm × 9 mm, RoHS-compliant CSP_BGA package

Qualified for automotive applications

Analog input

Worldwide NTSC/PAL/SECAM color demodulation support

with autodetection

One 10-bit ADC, 4× oversampling for CVBS, Y/C, and YPbPr

8 analog video input channels with on-chip antialiasing

filter

Fully differential, pseudo differential, and single-ended

CVBS video input support

STB diagnostics on differential video inputs

CVBS (composite), Y/C (S-Video), and YPbPr (component)

video input support

Fast switching capability between analog inputs

Adaptive contrast enhancement (ACE)

Excellent common-mode noise rejection capabilities

Rovi (Macrovision) copy protection detection

Up to 4 V common-mode input range solution

Vertical blanking interval (VBI) data slicer

High-Definition Multimedia Interface (HDMI) capable

receiver

HDCP authentication and decryption support

162 MHz maximum pixel clock frequency, allowing HDTV

formats up to 1080p and display resolutions up to UXGA

(1600 × 1200 at 60 Hz)

HDCP repeater support, up to 25 KSVs supported

Integrated CEC controller, CEC 1.4 compatible

Adaptive TMDS equalizer

APPLICATIONS

Portable devices

Automotive infotainment (head unit and rear seat

entertainment systems)

5 V detect and Hot Plug assert

HDMI repeaters and video switches

FUNCTIONAL BLOCK DIAGRAM

RXCP/RXCN

ALSB

ADV7482

2

SCLK

I C SLAVE

RX0P/RX0N

RX1P/RX1N

RX2P/RX2N

SDATA

HDMI

RECEIVER

INTRQ1

INTRQ2

INTERRUPTS

CONTROLLER

DDC_SCL

DDC

CEC

DDC_SDA

HPD

I2S_MCLK

I2S_LRCLK

I2S_SCLK

I2S_SDATA

AUDIO

PROCESSOR

AUDIO OUTPUT

FORMATTER

HPD

EDID RAM

HDCP

CEC

CP

CORE

RX_5V

4-LANE

MIPI CSI-2

TRANSMITTER

CLKAP/CLKAN

DA0P/DA0N TO

DA3P/DA3N

LLC

8-BIT TTL

INPUT/OUTPUT

P0 TO P7

AIN1 TO

AIN8

SD

CORE

AFE

1-LANE

MIPI CSI-2

TRANSMITTER

CLKBP/CLKBN

DB0P/DB0N

DIAG1 TO

DIAG4

DIAGNOSTIC

Figure 1.

Rev. 0

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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Technical Support

www.analog.com

ADV7482

Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Power Supply Recommendation .................................................. 16

Power-Up Sequence ................................................................... 16

Power-Down Sequence.............................................................. 16

Thoery of Operation ...................................................................... 17

HDMI Receiver........................................................................... 17

Component Processor ............................................................... 17

Analog Front End....................................................................... 17

Short to Battery Diagnostics..................................................... 18

Standard Definition Processor ................................................. 18

8-Bit Digital Input/Output Port ............................................... 19

Audio Processing........................................................................ 19

MIPI CSI-2 Transmitters........................................................... 19

Interrupts..................................................................................... 19

Outline Dimensions....................................................................... 20

Ordering Guide .......................................................................... 20

Automotive Products................................................................. 20

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

General Description ......................................................................... 3

Detailed Functional Block Diagram .............................................. 4

Specifications..................................................................................... 5

Electrical Characteristics............................................................. 5

Analog Video Specifications ....................................................... 7

MIPI Video Output Specifications............................................. 8

Analog Specifications................................................................... 8

Timing Specifications .................................................................. 9

Absolute Maximum Ratings.......................................................... 12

Thermal Resistance .................................................................... 12

ESD Caution................................................................................ 12

Pin Configuration and Function Descriptions........................... 13

REVISION HISTORY

6/14—Revision 0: Initial Version

Rev. 0 | Page 2 of 20

Data Sheet

ADV7482

GENERAL DESCRIPTION

The ADV7482 is an integrated video decoder and HDMI®

receiver, targeted at connectivity enabled head units requiring a

wired, uncompressed digital audio/video link from smartphones,

and other consumer electronics devices to support streaming

and integration of cloud-based multimedia content and

applications into an automotive infotainment system.

The automatic gain control (AGC) and clamp restore circuitry

allow an input video signal up to 1.0 V p-p at the analog video

input pins of the ADV7482. Alternatively, the AGC and clamp

restore circuitry can be bypassed for manual settings.

The SDP of the ADV7482 is capable of decoding a large

selection of analog baseband video signals in composite, S-Video,

and component formats. The SDP supports worldwide NTSC,

PAL, and SECAM standards.

The ADV7482 HDMI capable receiver supports a maximum

pixel clock frequency of 162 MHz, allowing HDTV formats up

to 1080p, and display resolutions up to UXGA (1600 × 1200 at

60 Hz). The device integrates a consumer electronics control

(CEC) controller that supports the capability discovery and

control (CDC) feature. The HDMI input port has dedicated 5 V

detect and Hot Plug™ assert pins.

The ADV7482 features an 8-bit digital input/output port,

supporting input and output video resolutions up to 720p/1080i

in both the 8-bit interleaved 4:2:2 SDR and DDR modes.

To enable glueless interfacing of these video input sources to the

latest generation of infotainment system on chips (SoCs), the

ADV7482 features two MIPI® CSI-2 transmitters. The four-lane

transmitter provides four data lanes, two data lanes, and one

data lane muxing options, and can be used to output video from

the HDMI receiver, the SDP, and the digital input port. The

single-lane transmitter can be used to output video from the

SDP only.

The HDMI receiver includes an adaptive transition minimized

differential signaling (TMDS) equalizer that ensures robust

operation of the interface with long cables.

The ADV7482 contains a component processor (CP) that

processes the video signals from the HDMI receiver. It provides

features such as contrast, brightness, and saturation

adjustments, as well as free run and timing adjustment controls

for HS/VS/DE timing.

The ADV7482 offers a flexible audio output port for audio data

extracted from HDMI streams. The HDMI receiver has

advanced audio functionality, such as a mute controller that

prevents audible extraneous noise in the audio output.

Additionally, the ADV7482 can be set to output time division

multiplexing (TDM) serial audio, which allows the transmission

of eight multiplexed serial audio channels on a single audio

output interface port.

The ADV7482 analog front end (AFE) comprises a single high

speed, 10-bit analog-to-digital converter (ADC) that digitizes

the analog video signal before applying it to the SDP.

The eight analog video inputs can accept single-ended, pseudo

differential, and fully differential composite video signals, as

well as S-Video and YPbPr video signals, supporting a wide

range of consumer and automotive video sources.

The ADV7482 is programmed via a 2-wire, serial, bidirectional

port (I²

C compatible).

Short to battery (STB) events can be detected on differential

input video signals. STB protection is provided by ac coupling

the input video signals. The ADV7482, in combination with an

external resistor divider, provides a common-mode input range

of 4 V, enabling the removal of large signal common-mode

transients present on the video lines.

Fabricated in an advanced CMOS process, the ADV7482 is

available in a 9 mm × 9 mm, RoHS-compliant, 100-ball

CSP_BGA package and is specified over the −40°C to +85°C

temperature range.

The ADV7482 is offered in automotive and industrial versions.

Rev. 0 | Page 3 of 20

ADV7482

Data Sheet

DETAILED FUNCTIONAL BLOCK DIAGRAM

ADV7482

SCLK

SDATA

ALSB

2

I C SLAVE/

CONTROL

GENERAL

INTERRUPTS

CONTROLLER

INTRQ1

INTRQ2

PACKET/

INFOFRAME

MEMORY

RESET

5V DETECT AND

HPD PIN

CONTROLLER

HPD

RX_5V

I2S_MCLK

I2S_LRCLK

I2S_SCLK

I2S_SDATA

AUDIO

PROCESSOR

PACKET

PROCESSOR

AUDIO OUTPUT

FORMATTER

CEC

CONTROLLER

CEC

EDID/

HDCP

KEYS

HDCP

ENGINE

DDC_SDA

DDC_SCL

REPEATER

CONTROLLER

PLL

RXCP/RXCN

8-BIT

MIPI CSI-2

TRANSMITTER A

CLKAP/

CLKAN

RX0P/RX0N

RX1P/RX1N

RX2P/RX2N

TO

COMPONENT

PROCESSOR

(CP)

COLOR

HDMI

PROCESSOR

6-BIT

DITHER

BLOCK

SAMPLER

EQUALIZER

SPACE

CONVERSION

DA0P/DA0N

DA1P/DA1N

DA2P/DA2N

DA3P/DA3N

LLC

P0

P1

P2

P3

P4

P5

P6

P7

CSI-2 Tx

D-PHY Tx

8-BIT

DIGITAL

INPUT/

OUTPUT

PORT

CLOCK PROCESSING BLOCK

ADLLT PROCESSING

XTALP

XTALN

PLL

MIPI CSI-2

TRANSMITTER B

AFE

STANDARD DEFINITION

PROCESSOR (SDP)

AIN1

AIN2

AIN3

AIN4

AIN5

AIN6

AIN7

AIN8

AA

10-BIT ADC

FILTER

CLKBP/

CLKBN

ACE

2D COMB

AA

FILTER

+

SHA

CSI-2 Tx

D-PHY Tx

DOWN-

DITHER

DB0P/

DB0N

VBI SLICER

ADC

AA

FILTER

–

COLOR DEMOD

AA

FILTER

STANDARD

AUTODETECTION

DIAG1

DIAG2

DIAG3

DIAG4

VREFP

VREFN

REFERENCE

DIAGNOSTICS

Figure 2.

Rev. 0 | Page 4 of 20

Data Sheet

ADV7482

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

AVDD = 1.71 V to 1.89 V, DVDD = 1.71 V to 1.89 V, PVDD = 1.71 V to 1.89 V, MVDD = 1.71 V to 1.89 V, CVDD = 1.71 V to 1.89 V,

DVDDIO = 3.14 V to 3.46 V, and TVDD = 3.14 V to 3.46 V, specified at operating temperature range, unless otherwise noted.

Table 1.

Parameter

Symbol

Test Conditions/Comments

Min Typ

Max

Unit

STATIC PERFORMANCE

Resolution (Each ADC)

Integral Nonlinearity

Differential Nonlinearity

DIGITAL INPUTS¹

N

INL

DNL

10

Bits

LSB

CVBS mode

2

0.6

SCLK, SDATA, RESET, ALSB, LLC, and P0 to P7

DVDDIO = 3.14 V to 3.46 V

Input High Voltage

Input Low Voltage

Input Leakage Current

Input Capacitance²

CRYSTAL INPUT

V_IH

V_IL

I_IN

2

V

µA

pF

0.8

+10

10

−10

C_IN

Input High Voltage

Input Low Voltage

DIGITAL OUTPUTS¹

V_IH

V_IL

XTALP

1.2

V

0.4

LLC, P0 to P7, I2S_MCLK, I2S_SCLK, I2S_LRCLK,

I2S_SDATA, SDATA, INTRQ1 and INTRQ2 (when

configured to drive when active)

Output High Voltage

Output Low Voltage

High Impedance Leakage Current

Output Capacitance²

V_OH

V_OL

I_LEAK

C_OUT

DVDDIO = 3.14 V to 3.46 V and I_SOURCE= 0.4 mA

DVDDIO = 3.14 V to 3.46 V and I_SINK= 3.2 mA

2.4

V

µA

pF

0.4

20

10

POWER REQUIREMENTS

Digital Power Supply

HDMI Terminator Supply

HDMI Comparator Supply

PLL Power Supply

D_VDD

T_VDD

1.71 1.8

3.14 3.3

1.71 1.8

3.14 3.3

1.71 1.8

1.89

3.46

1.89

3.46

1.89

V

C_VDD

P_VDD

M_VDD

D_VDDIO

A_VDD

MIPI Transmitters Power Supply

Digital Input/Output Power Supply¹

Analog Power Supply

3.3 V operation

CURRENT CONSUMPTION^{1, 2, 3, 4}

Digital Supply Current

Single-Ended CVBS Input

Fully Differential and Pseudo Differential

CVBS Input

I_DVDD

279

mA

74.5

74.7

Y/C Input

YPbPr Input

HDMI Input

8-Bit Digital Input

HDMI Terminator Supply Current

Single-Ended CVBS Input

Fully Differential and Pseudo Differential

CVBS Input

71.3

72.8

68.1

32.5

mA

I_TVDD

40

0.7

Y/C Input

0.7

35

mA

YPbPr Input

HDMI Input

8-Bit Digital Input

0.7

Rev. 0 | Page 5 of 20

ADV7482

Data Sheet

Parameter

Symbol

Test Conditions/Comments

Min Typ

Max

Unit

mA

HDMI Comparator Supply Current

Single-Ended CVBS Input

Fully Differential and Pseudo Differential

CVBS Input

I_CVDD

92

0.1

Y/C Input

YPbPr Input

HDMI Input

8-Bit Digital Input

PLL Supply Current

Single-Ended CVBS Input

Fully Differential and Pseudo Differential

CVBS Input

Y/C Input

YPbPr Input

HDMI Input

8-Bit Digital Input

MIPI Transmitters Supply Current

Single-Ended CVBS Input

Fully Differential and Pseudo Differential

CVBS Input

Y/C Input

YPbPr Input

HDMI Input

8-Bit Digital Input

Digital Input/Output Supply Current

Single-Ended CVBS Input

Fully Differential and Pseudo Differential

CVBS Input

Y/C Input

YPbPr Input

HDMI Input

8-Bit Digital Input

Analog Supply Current

Single-Ended CVBS Input

Fully Differential and Pseudo Differential

CVBS Input

0.1

63.9

0.1

mA

I_PVDD

52

77

78

93

37.5

37.7

29.2

27.9

mA

I_MVDD

I_DVDDIO

I_AVDD

23.3

23.2

45.7

38.1

mA

0.2

3.6

0.2

mA

51.9

70

Y/C Input

YPbPr Input

HDMI Input

63

mA

78.5

0.1

8-Bit Digital Input

POWER-DOWN CURRENTS^{2, 5}

Digital Supply

HDMI Terminator Supply

HDMI Comparator Supply

PLL Supply

MIPI Transmitters Supply

Digital Input/Output Supply

Analog Supply

Total Power Dissipation in Power-Down

Mode

I_{DVDD_PD}

I_{TVDD_PD}

I_{CVDD_PD}

I_{PVDD_PD}

I_{MVDD_PD}

I_{DVDDIO_PD}

I_{AVDD_PD}

0.2

0.4

0.1

0.2

0.1

4

mA

mW

¹The 8-bit digital input/output port is only available when the DVDDIO supply is between 3.14 V and 3.46 V.

²Guaranteed by lab characterization.

³Typical current consumption values are recorded with nominal voltage supply levels (including DVDDIO = 3.3 V), Philips test pattern, and at room temperature.

⁴Maximum current consumption values are recorded with maximum rated voltage supply levels (including DVDDIO = 3.46 V), MoireX video pattern for analog inputs,

pseudorandom test pattern for digital inputs, and at worst-case temperature.

⁵Typical power-down current consumption values are recorded with nominal voltage supply levels (including DVDDIO = 3.3 V) at room temperature.

Rev. 0 | Page 6 of 20

Data Sheet

ADV7482

ANALOG VIDEO SPECIFICATIONS

AVDD = 1.71 V to 1.89 V, DVDD = 1.71 V to 1.89 V, PVDD = 1.71 V to 1.89 V, MVDD = 1.71 V to 1.89 V, CVDD = 1.71 V to 1.89 V,

DVDDIO = 3.14 V to 3.46 V, and TVDD = 3.14 V to 3.46 V, specified at operating temperature range, unless otherwise noted.

Table 2.

Parameter

Symbol

Test Conditions/Comments

Min Typ

Max

Unit

NONLINEAR SPECIFICATIONS^{1, 2}

Differential Phase

Differential Gain

Luma Nonlinearity

DP

DG

LNL

CVBS input, modulated five-step

CVBS input, five-step

0.9

0.5

2.0

Degrees

%

NOISE SPECIFICATIONS

Signal-to-Noise Ratio, Unweighted²

SNR

Luma ramp

57.1

58

60

dB

Luma flat field

Analog Front-End Crosstalk³

Common-Mode Rejection Ratio^{2, 4}

LOCK TIME SPECIFICATIONS

Horizontal Lock Range³

Vertical Lock Range³

Subcarrier Lock Range³

Color Lock-In Time³

Synchronization Depth Range³

Color Burst Range³

Fast Switch Speed^{2, 5}

CMRR

73

−5

40

1.3

60

20

5

+5

70

%

Hz

kHz

Lines

%

f_SC

200

%

ms

100

¹These specifications apply to all CVBS input types, as well as to single-ended and differential CVBS inputs.

²Guaranteed by lab characterization.

³Guaranteed by design.

⁴The CMRR of this circuit design is critically dependent on the external resistor matching its inputs. This measurement was performed with 0.1% tolerant resistors, a

common-mode voltage of 1 V, and a common-mode frequency of 10 kHz.

⁵The time it takes the ADV7482 to switch from one analog input (single ended or differential) to another, for example, switching from AIN1 to AIN2.

Rev. 0 | Page 7 of 20

ADV7482

Data Sheet

MIPI VIDEO OUTPUT SPECIFICATIONS

AVDD = 1.71 V to 1.89 V, DVDD = 1.71 V to 1.89 V, PVDD = 1.71 V to 1.89 V, MVDD = 1.71 V to 1.89 V, CVDD = 1.71 V to 1.89 V,

DVDDIO = 3.14 V to 3.46 V, and TVDD = 3.14 V to 3.46 V, specified at operating temperature range, unless otherwise noted.

The ADV7482 MIPI CSI-2 transmitters conform to the MIPI D-PHY Version 1.00.00 specification by characterization. The clock lane of

the ADV7482 remains in high speed (HS) mode even when the data lane enters low power (LP) mode. For this reason, some

measurements on the clock lane that pertain to low power mode are not applicable. Unless otherwise stated, all high speed measurements

were performed with the ADV7482 operating with a nominal 1 Gbps output data rate.

Table 3

Parameter

Symbol

Min

Typ

Max

Unit

UNIT INTERVAL¹

UI

1

12.5

ns

DATA LANE LP Tx DC SPECIFICATIONS²

Thevenin Output

High Level

Low Level

V_OH

V_OL

1.1

−50

1.2

0

1.3

+50

V

mV

CLOCK LANE LP Tx DC SPECIFICATIONS²

Thevenin Output

High Level

Low Level

V_OH

V_OL

1.1

−50

1.2

0

1.3

+50

V

mV

DATA LANE HS Tx SIGNALING REQUIREMENTS

High Speed Differential Voltage Swing

Differential Voltage Mismatch

Single-Ended Output High Voltages

Static Common-Mode Voltage Level

CLOCK LANE HS Tx SIGNALING REQUIREMENTS

High Speed Differential Voltage Swing

Differential Voltage Mismatch

Single-Ended Output High Voltages

Static Common-Mode Voltage Level

HS Tx CLOCK TO DATA LANE TIMING REQUIREMENTS

Data to Clock Skew

|V₁|

140

200

270

10

360

250

mV p-p

mV

150

140

200

mV

|V₂|

270

10

360

250

mV p-p

mV

150

200

mV

0.35 × UI

0.65 × UI

ns

¹Guaranteed by design.

²These measurements were performed with C_LOAD= 50 pF.

ANALOG SPECIFICATIONS

AVDD = 1.71 V to 1.89 V, DVDD = 1.71 V to 1.89 V, PVDD = 1.71 V to 1.89 V, MVDD = 1.71 V to 1.89 V, CVDD = 1.71 V to 1.89 V,

DVDDIO = 3.14 V to 3.46 V, and TVDD = 3.14 V to 3.46 V, specified at operating temperature range, unless otherwise noted.

Table 4.

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

CLAMP CIRCUITRY

External Clamp Capacitor

Large Clamp

Required by design

0.1

µF

Source Current

Sink Current

0.32

mA

Fine Clamp

Source Current

Sink Current

7

µA

Rev. 0 | Page 8 of 20

Data Sheet

ADV7482

TIMING SPECIFICATIONS

AVDD = 1.71 V to 1.89 V, DVDD = 1.71 V to 1.89 V, PVDD = 1.71 V to 1.89 V, MVDD = 1.71 V to 1.89 V, CVDD = 1.71 V to 1.89 V,

DVDDIO = 3.14 V to 3.46 V, and TVDD = 3.14 V to 3.46 V, specified at operating temperature range, unless otherwise noted.

Table 5.

Parameter

Symbol Test Conditions

Min Typ

28.63636

Max

Unit

CLOCK AND CRYSTAL

Nominal Frequency¹

Frequency Stability¹

Input LLC Clock Frequency

Range^{2, 3}

Required by design

DVDDIO = 3.14 V to 3.46 V

MHz

ppm

MHz

50

148.5

13.5

Output LLC Clock Frequency

DVDDIO = 3.14 V to 3.46 V

148.5

MHz

Range^{2, 3}

I2S_SCLK Frequency³

I2S_MCLK Frequency³

I²C PORT

12.288 MHz

24.576 MHz

SCLK Frequency

400

kHz

µs

ns

µs

SCLK Minimum Pulse Width High t₁

0.6

1.3

0.6

100

SCLK Minimum Pulse Width Low

Hold Time (Start Condition)

Setup Time (Start Condition)

SDATA Setup Time

SCLK and SDATA Rise Times

SCLK and SDATA Fall Times

Setup Time (Stop Condition)

RESET FEATURE

t₂

t₃

t₄

t₅

t₆

t₇

t₈

300

0.6

RESET Pulse Width¹

5

ms

8-BIT DIGITAL INPUT PORT²

LLC High Time³

DVDDIO = 3.14 V to 3.46 V

t₂₁

45

55

% duty

cycle

% duty

cycle

LLC Low Time³

SDR and DDR Modes Setup Time

SDR and DDR Modes Hold Time

DDR Mode Setup Time

DDR Mode Hold Time

8-BIT DIGITAL OUTPUT PORT²

t₂₂

t₂₃

t₂₄

t₂₅

Data latched on rising edge

Data latched on falling edge

DVDDIO = 3.14 V to 3.46 V

1

ns

LLC High Time

t₂₆

40

60

% duty

cycle

% duty

cycle

LLC Low Time

40

SDR Modes Setup Time^{4, 5}

SDR Modes Hold Time^{4, 5}

DDR Modes Setup Time^{4, 5}

DDR Modes Hold Time^{4, 5}

DDR Mode Setup TIme^{4, 5}

DDR Modes Hold Time^{4, 5}

t₃₆

t₃₇

t₂₇

t₂₈

t₂₉

t₃₀

At P0 to P7 output pin, data latched on rising

edge

At P0 to P7 output pin, data latched on rising

edge

At P0 to P7 output pin, data latched on rising

edge

At P0 to P7 output pin, data latched on rising

edge

At P0 to P7 output pin, data latched on falling

edge

At P0 to P7 output pin, data latched on falling

edge

1.98

2.50

1.66

3.52

1.71

3.17

ns

Rev. 0 | Page 9 of 20

ADV7482

Data Sheet

Parameter

Symbol Test Conditions

Min Typ

Max

Unit

I²S PORT, MASTER MODE

I2S_SCLK High Time

t₃₁

45

55

% duty

cycle

% duty

cycle

I2S_SCLK Low Time

I2S_LRCLK Data Transition Time

t₃₂

t₃₃

t₃₄

t₃₅

End of valid data to I2S_SCLK falling edge

10

5

ns

I2S_SCLK falling edge to start of valid data

End of valid data to I2S_SCLK falling edge

I2S_SCLK falling edge to start of valid data

I2S_SDATA Data Transition Time

5

¹Required by design.

²The 8-bit digital input/output port is only available when the DVDDIO supply is between 3.14 V and 3.46 V.

³Guaranteed by design.

⁴These specifications only apply when the LLC_DLL_PHASE[4:0] (IO Map, Register 0x0C[4:0]) is set to 00000.

⁵Guaranteed by lab characterization.

Timing Diagrams

t₅

t₃

SDATA

SCLK

t₁

t₆

t₄

t₇

t₈

t₂

Figure 3. I²C Timing

t₂₁

t₂₂

t₂₃

LLC

P7 TO P0

Figure 4. 8-Bit Digital Pixel Video Input, SDR Video Data Timing

t₂₁

LLC

t₂₄

t₂₃

t₂₅

t₂₂

P7 TO P0

Figure 5. 8-Bit Digital Pixel Video Input, DDR Video Data Timing

t

26

LLC

t₃₆

t₃₇

P7 TO P0

Figure 6. 8-Bit Digital Pixel Video Output, SDR Video Data Timing

Rev. 0 | Page 10 of 20

Data Sheet

ADV7482

t₂₆

LLC

t₂₇

t₂₉

t₂₈

t₃₀

P7 TO P0

Figure 7. 8-Bit Digital Pixel Video Output, DDR Video Data Timing

t₃₁

I2S_SCLK

t₃₂

I2S_LRCLK

I2S_SDATA

t₃₃

t₃₄

LEFT JUSTIFIED

MODE

MSB

MSB – 1

MSB

t₃₅

t₃₄

I2S_SDATA

2

I S MODE

MSB – 1

t₃₅

t₃₄

I2S_SDATA

RIGHT JUSTIFIED

MODE

MSB

LSB

t₃₅

Figure 8. I²S Timing

Rev. 0 | Page 11 of 20

ADV7482

Data Sheet

ABSOLUTE MAXIMUM RATINGS

THERMAL RESISTANCE

Table 6.

Parameter

Rating

To reduce power consumption when using the ADV7482, turn

off unused sections of the device.

TVDD, DVDDIO to GND

AVDD, PVDD, MVDD, DVDD, CVDD 2.2 V

to GND

CVDD to DVDD

MVDD to DVDD

PVDD to DVDD

AVDD to DVDD

Digital Inputs Voltage to GND

4 V

Due to printed circuit board (PCB) metal variation, and,

therefore, variation in PCB heat conductivity, the value of θ_JA

may differ for various PCBs.

−0.3 V to +0.3 V

GND − 0.3 V to DVDDIO +

0.3 V

GND − 0.3 V to DVDDIO +

0.3 V

−0.3 V to AVDD + 0.3 V

−0.3 V to PVDD + 0.3 V

−0.3 V to CVDD + 0.3 V

The most efficient measurement solution is achieved using the

package surface temperature to estimate the die temperature.

This eliminates the variance associated with the θ_JAvalue.

Do not exceed the maximum junction temperature (T_Jmax) of

125°C. The following equation calculates the junction

temperature (T_J) using the measured package surface

temperature and applies only when no heat sink is used on the

device under test (DUT):

Digital Outputs Voltage to GND

Analog Inputs to GND

XTALN and XTALP to GND

HDMI Digital Inputs Voltage to

GND

T_J= T_S+ (Ψ_JT×W_TOTAL

)

5 V Tolerant Inputs Voltage to

GND^{1, 2}

Maximum Junction Temperature

(T_Jmax)

Storage Temperature Range

Infrared Reflow Soldering

(20 sec)

−0.3 V to +5.5 V

125°C

where:

T_Sis the package surface temperature (°C).

Ψ_JT= 0.81°C/W for the 100-ball CSP_BGA (based on 2s2p test

board defined by JEDEC standards.

−65°C to +150°C

260°C

W

_TOTAL= (PVDD × I_PVDD) + (TVDD × I_TVDD) − P_UpStream

(CVDD × I_CVDD) + (AVDD × I_AVDD) + (DVDD × I_DVDD) +

(DVDDIO × I_DVDDIO) + (MVDD × I_MVDD

+

)

¹The following inputs are 3.3 V inputs but are 5 V tolerant: DDC_SCL,

DDC_SDA, HPD, RX_5V, and CEC.

where P_UpStreamis the quantity of TVDD power consumed on the

upstream HDMI transmitter. P_UpStreamcan be estimated to be

around 110 mW for a nominal HDMI transmitter.

²The following inputs are 1.8 V inputs but are 5 V tolerant: DIAG1, DIAG2,

DIAG3, and DIAG4.

Stresses at or above those listed under Absolute Maximum

Ratings may cause permanent damage to the product. This is a

stress rating only; functional operation of the product at these

or any other conditions above those indicated in the operational

section of this specification is not implied. Operation beyond

the maximum operating conditions for extended periods may

affect product reliability.

ESD CAUTION

Rev. 0 | Page 12 of 20

Data Sheet

ADV7482

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

2

3

4

5

6

7

8

9

10

GND

I2S_

SDATA

GND

RX2P

RX1P

RX0P

RXCP

DDC_SCL

DNC

GND

A

B

C

D

E

F

A

B

C

D

E

F

I2S_

SCLK

MVDD

CLKAN

DA0N

DA1N

DA2N

DA3N

DB0N

CLKBN

CVDD

RX2N

RX1N

TEST2

GND

P4

RX0N

TVDD

GND

DNC

P7

RXCN

CEC

DDC_SDA

RX_5V

DIAG4

DIAG3

VREFN

VREFP

RESET

SCLK

HPD

AIN7

GND

AIN8

I2S_

LRCLK

I2S_

MCLK

CLKAP

DA0P

DA1P

DA2P

DA3P

DB0P

CLKBP

TEST3

INTRQ2

INTRQ1

TEST

DVDD

GND

DVDD

P1

GND

AVDD

GND

DNC

AIN5

AIN6

AIN3

AIN4

AIN1

AIN2

DIAG1

PVDD

XTALN

DIAG2

GND

G

H

J

G

H

J

DVDDIO

MVDD

P2

P5

XTALP

GND

1

MVDD

2

P0

3

P3

4

P6

5

LLC

6

DNC

7

SDATA

8

ALSB

9

GND

10

K

DNC = DO NOT CONNECT. LEAVE THIS PIN UNCONNECTED.

Figure 9. Pin Configuration

Table 7. Pin Function Descriptions

Pin No.

Mnemonic

Type

Description

Ground.

I2S Audio Output.

Ground.

HDMI Digital Input Channel 2.

HDMI Digital Input Channel 1.

HDMI Digital Input Channel 0.

HDMI Input Clock.

A1

A2

A3

A4

A5

A6

A7

GND

I2S_SDATA

GND

RX2P

RX1P

Ground

Output

Ground

HDMI

RX0P

RXCP

HDMI

A8

A9

A10

B1

B2

DDC_SCL

DNC

GND

MVDD

I2S_SCLK

CVDD

HDMI

HDCP Slave Serial Clock.

Do Not Connect. Leave this pin unconnected.

Ground.

MIPI Supply Voltage (1.8 V).

Audio Serial Clock.

HDMI Comparator Supply Voltage (1.8 V). This is the supply for the

HDMI sensitive analog circuitry. Blocks on this supply include the

TMDS PLL and the equalizers.

Miscellaneous

Ground

Power

Output

Power

B3

B4

B5

B6

B7

B8

B9

B10

RX2N

RX1N

RX0N

RXCN

DDC_SDA

HPD

HDMI

Ground

HDMI Digital Input Channel 2 Complement.

HDMI Digital Input Channel 1 Complement.

HDMI Digital Input Channel 0 Complement.

HDMI Input Clock Complement.

HDCP Slave Serial Data.

HDMI Hot Plug Assert.

Ground.

GND

Rev. 0 | Page 13 of 20

ADV7482

Data Sheet

Pin No.

C1

C2

C3

C4

C5

C6

C7

Mnemonic

CLKAN

CLKAP

I2S_LRCLK

I2S_MCLK

TEST2

Type

Description

Output

Miscellaneous

Power

MIPI Transmitter A Negative Output Clock.

MIPI Transmitter A Positive Output Clock.

Audio Left/Right Clock.

Audio Master Clock Output.

Test Pin 2. Pull down via a large pull-down resistor to ground.

HDMI Terminator Supply Voltage (3.3 V).

CEC Channel.

TVDD

CEC

HDMI

C8

RX_5V

HDMI

HDMI 5 V Detect. A large pull-down resistor (100 kΩ, typical) to

ground must be connected to this pin.

C9

C10

D1

D2

D3

D4

D5

D6

D7

D8

D9

D10

E1

E2

E3

E4

E5

E6

E7

E8

E9

E10

F1

F2

F3

F4

F5

F6

F7

F8

AIN7

AIN8

Input

Analog Video Input Channel.

MIPI Transmitter A Negative Data Output.

MIPI Transmitter A Positive Data Output.

Test Pin 3. Pull up to DVDDIO via a pull-up resistor (4.7 kΩ).

Digital Supply Voltage (1.8 V).

Ground.

DA0N

DA0P

TEST3

DVDD

GND

DIAG4

AIN5

AIN6

DA1N

DA1P

INTRQ2

GND

AVDD

DIAG3

AIN3

Output

Miscellaneous

Power

Ground

Input

Ground.

Analog Video Diagnostic Input. This input is 5 V tolerant.

Analog Video Input Channel.

MIPI Transmitter A Negative Data Output.

MIPI Transmitter A Positive Data Output.

Interrupt Request Output.

Ground.

Input

Output

Ground

Power

Input

Output

Ground

Output

Input

Ground.

Analog Supply Voltage (1.8 V).

Analog Video Diagnostic Input. This input is 5 V tolerant.

Analog Video Input Channel.

MIPI Transmitter A Negative Data Output.

MIPI Transmitter A Positive Data Output.

Interrupt Request Output.

Ground.

AIN4

DA2N

DA2P

INTRQ1

GND

VREFN

AIN1

Ground.

Internal Voltage Reference Output.

Analog Video Input Channel.

MIPI Transmitter A Negative Data Output.

MIPI Transmitter A Positive Data Output.

Do Not Connect. Leave this pin unconnected.

Digital Supply Voltage (1.8 V).

Ground.

F9

F10

G1

G2

G3

G4

G5

G6

G7

G8

G9

G10

AIN2

Input

DA3N

DA3P

TEST

DVDD

GND

VREFP

DIAG1

DIAG2

Output

Miscellaneous

Power

Ground

Output

Input

Ground.

Internal Voltage Reference Output.

Analog Video Diagnostic Input. This input is 5 V tolerant.

Input

Rev. 0 | Page 14 of 20

Data Sheet

ADV7482

Pin No.

H1

H2

H3

H4

H5

H6

H7

H8

Mnemonic

Type

Description

DB0N

DB0P

DVDDIO

P1

Output

Power

Input/Output

Miscellaneous

Input

MIPI Transmitter B Negative Data Output.

MIPI Transmitter B Positive Data Output.

Digital Input/Output Supply Voltage (3.3 V).

Video Pixel Input/Output Port.

Do Not Connect. Leave this pin unconnected.

P4

DNC

RESET

System Reset Input, Active Low. A minimum low reset pulse of

5 ms is required to reset the chip.

H9

H10

J1

J2

J3

J4

J5

J6

J7

PVDD

GND

CLKBN

CLKBP

MVDD

P2

P5

P7

DNC

SCLK

XTALN

Power

Ground

Output

PLL Supply Voltage (1.8 V).

Ground.

MIPI Transmitter B Negative Output Clock.

MIPI Transmitter B Positive Output Clock.

MIPI Supply Voltage (1.8 V).

Video Pixel Input/Output Port.

Do Not Connect. Leave this pin unconnected.

I²C Port Serial Clock Input.

Crystal Output. This pin must be connected to the 28.63636 MHz

crystal or not connected if an external 1.8 V, 28.63636 MHz clock

oscillator is used. In crystal mode, the crystal must be a

fundamental crystal.

Power

Input/Output

Miscellaneous

Input

J8

J9

Output

J10

XTALP

Input

Crystal Input or External Clock Input. This pin must be connected

to the 28.63636 MHz crystal or connected to an external 1.8 V,

28.63636 MHz clock oscillator if a clock oscillator is used. In crystal

mode, the crystal must be a fundamental crystal.

K1

K2

K3

K4

K5

K6

K7

K8

K9

GND

MVDD

P0

P3

P6

Ground

Power

Ground.

MIPI Supply Voltage (1.8 V).

Input/Output

Miscellaneous

Input/Output

Input

Video Pixel Input/Output Port.

Line Locked Clock. Input/output clock for the pixel data.

Do Not Connect. Leave this pin unconnected.

I²C Port Serial Data Input/Output.

Main I²C Address Selection Pin. This pin selects the main I²C

address (IO Map I²C address) for the part. When ALSB is set to

Logic 0, the IO Map I²C write address is 0xE0; when ALSB is set to

Logic 1, the IO Map I²C write address is 0xE2.

LLC

DNC

SDATA

ALSB

K10

GND

Ground

Ground.

Rev. 0 | Page 15 of 20

ADV7482

Data Sheet

POWER SUPPLY RECOMMENDATION

POWER-UP SEQUENCE

POWER-DOWN SEQUENCE

Adhere to the absolute maximum ratings at all times during

power-up (see Table 6). The power-up sequence for the

ADV7482 is as follows:

The ADV7482 power supplies can be deasserted simultaneously

as long as a higher rated supply (for example, D_VDDIO) does not

fall to a voltage level less than a lower rated supply (for example,

D

_VDD), and the absolute maximum ratings specifications are

RESET

1. Assert

(pull the pin low).

followed.

2. Power up the 3.3 V supplies (D_VDDIOand T_VDD). These

supplies must be powered up simultaneously.

3. Power up the 1.8 V supplies (D_VDD, C_VDD, P_VDD, M_VDD, and

A_VDD). These supplies must be powered up simultaneously.

RESET

4.

can be deasserted (pulled high) 5 ms after all

supplies are fully powered up.

RESET

5. After all power supplies and the

pin are powered up

and stable, wait an additional 5 ms before initiating I²C

communication with the ADV7482.

3.3V

RESET

0V

3.3V

3.3V SUPPLIES

0V

1.8V

1.8V SUPPLIES

0V

RESET > 5ms

Figure 10. Supply Power-Up Sequence

Rev. 0 | Page 16 of 20

Data Sheet

ADV7482

THOERY OF OPERATION

•

Support for all video modes supported by the HDMI

HDMI RECEIVER

receiver. These include 525i, 625i, 525p, 625p, 1080i, 1080p,

and display resolutions from VGA (640 × 480 at 60 Hz) to

UXGA (1600 × 1200 at 60 Hz).

Manual adjustments including gain (contrast), offset

(brightness), hue, and saturation.

Free run output mode that provides stable timing when no

video input is present.

Timing adjustments controls for HS/VS/DE timing.

The HDMI receiver supports video formats ranging from 480i

to 1080p, and display resolutions from VGA (640 × 480 at

60 Hz) to UXGA (1600 × 1200 at 60 Hz).

•

The HDMI receiver allows programmable equalization of the

HDMI data signals. This equalization compensates for the high

frequency losses inherent in HDMI and DVI cabling, especially

at longer lengths and higher frequencies. The receiver is capable

of equalizing for cable lengths up to 30 meters to achieve robust

receiver performance.

ANALOG FRONT END

The HDMI interface of the ADV7482 allows for authentication

of a video receiver, decryption of encoded data at the receiver,

and renewability of that authentication during transmission, as

specified by the HDCP 1.4 protocol.

The ADV7482 AFE comprises a single high speed, 10-bit ADC

that digitizes the analog video signal before applying it to the

SDP. The AFE uses differential channels to the ADC to ensure

high performance in mixed-signal applications and to enable

differential CVBS to be connected directly to the ADV7482.

Dual extended display identification data (EDID) support is

provided via an on-chip 512-byte EDID RAM. The EDID RAM

must be programmed at power-up. It can be configured as two

256-byte EDIDs, or as a single 512-byte EDID.

Up to eight analog inputs can be connected to the AFE. The

front end also includes an 8-channel input mux that enables

different configurations of single-ended CVBS (up to eight),

pseudo differential or fully differential CVBS (up to four), Y/C

(up to four), and YPbPr (up to two) analog inputs.

The ADV7482 has a synchronization regeneration block used to

regenerate the data enable (DE) signal based on the measurement

of the video format being displayed and to filter the horizontal

and vertical synchronization signals to prevent glitches.

Current clamps are positioned in front of the ADC to ensure

that the video signal remains within the range of the converter.

A resistor divider network is required before each analog input

channel to ensure that the input signal is within the range of the

ADC. Figure 11 shows a typical voltage divider network for

single-ended inputs, Figure 12 shows a typical voltage divider

network for pseudo differential inputs, and Figure 13 shows a

typical voltage divider network for fully differential inputs. The

choice of the resistor divider shown in Figure 13 provides a

common-mode range of up to 4 V in fully differential CVBS

input mode. Fine clamping of the video signal is performed

downstream by digital fine clamping within the ADV7482.

The HDMI receiver also supports TMDS error reduction

coding, 4-bit (TERC4) error detection, used for the detection of

corrupted HDMI packets.

The main HDMI receiver features include

•

162.0 MHz (UXGA at 24 BPP) maximum TMDS clock

frequency.

•

Integrated fully adaptive equalizer for cable lengths up to

30 meters.

•

HDCP 1.4 support.

Internal HDCP keys.

HDCP repeater support, up to 25 key selection vectors

(KSVs) supported.

ANALOG

INPUT

100nF

AIN

24Ω

51Ω

•

PCM audio packet support.

Support for 8-channel TDM output data up to 48 kHz.

Repeater support.

Internal EDID RAM (512-byte for single mode, and

256-byte for dual mode operation).

Hot Plug assert output pin (HPD).

CEC controller.

Figure 11. Typical Single-Ended Input Voltage Divider Network

ANALOG INPUT

100nF

1.3kΩ

AINx

CVBS_P

•

430Ω

75Ω

COMPONENT PROCESSOR

430Ω

100nF

ANALOG INPUT

CVBS_N

1.3kΩ

The ADV7482 has one any-to-any 3 × 3 CSC matrix. The CSC

block is located in the processing path before the CP section.

CSC enables YCbCr-to-RGB and RGB-to-YCbCr conversions.

Many other standards of color space can be implemented using

the color space converter.

AINy

Figure 12. Typical Pseudo Differential Input Resistor Divider Network

CP features include

Rev. 0 | Page 17 of 20

ADV7482

Data Sheet

ANALOG INPUT

100nF

1.3kΩ

R4

AINx

CVBS_P

DIAGx

R5

100nF

430Ω

ANALOG INPUT

CVBS_P

1.3kΩ

150Ω

AINx

430Ω

100nF

430Ω

ANALOG INPUT

CVBS_N

75Ω

OR

150Ω

1.3kΩ

AINy

430Ω

ANALOG INPUT

CVBS_N

Figure 13. Typical Fully Differential Input Resistor Divider Network

100nF

1.3kΩ

AINy

The ADC features three clocking rates that allow 4×

oversampling per channel for CVBS mode, Y/C mode, and

YPbPr mode.

Figure 14. Diagnostic Connection for Differential Inputs

Resistors R4 and R5 divide down the voltage at the input

connector to protect the DIAGx pin from an STB event. The

DIAGx pin circuitry compares this voltage to a programmable

reference voltage, known as the diagnostic slice level. When the

diagnostic slice level is exceeded, an STB event has occurred.

The fully differential AFE of the ADV7482 provides inherent

small and large signal noise rejection, improved electromagnetic

interference (EMI) protection, and the ability to absorb ground

bounce. Support is provided for both true differential and

pseudo differential signals.

R4 and R5 are sized to allow the use of low cost, small footprint

resistors that are tolerant of STB events.

The main AFE features include

•

A single 172 MHz, 10-bit ADC that enables true 8-bit

video decoding.

Use the following equation to find the STB voltage for a selected

diagnostic slice level.

8-channel analog input mux that enables multiple source

connections without the requirement of an external mux.

A current clamp control loop that ensures that any dc

offsets are removed from the video signal entering the SDP.

Diagnostic capability on all differential inputs.

Support for 4 V common-mode input range.

Support for analog input signals up to 1 V p-p.

Support for single-ended, pseudo differential, and fully

differential inputs.

R5 + R4

R5

V_{STB_TRIGGER}

=

×DIAGNOSTIC_SLICE_LEVEL

where:

_{STB_TRIGGER}is the minimum voltage required at the input

V

•

connector to trigger the STB interrupt on the ADV7482.

DIAGNOSTIC_SLICE_LEVEL is the programmable reference

voltage.

For example, with a diagnostic slice level programmed to

1.125 V, an R4 value of 9.1 kΩ, and an R5 value of 1 kΩ, the

minimum voltage required at the input connector to trigger the

STB interrupt is approximately 11.4 V.

SHORT TO BATTERY DIAGNOSTICS

In differential mode, the ADV7482 is protected against STB

events by ac coupling capacitors (see Figure 12 and Figure 13).

The input network resistors are sized to reduce the current flow

during an STB event, thus preventing damage to the resistors.

Note that the input network resistors and the ac coupling

capacitors must be chosen with ratings guaranteeing they are

able to withstand the high voltage of STB events.

When the DIAGx pin voltage exceeds the diagnostic slice level

voltage, a hardware interrupt is triggered and indicated by one

of the interrupt pins. A readback register specifies the input on

which the STB event occurred.

STANDARD DEFINITION PROCESSOR

The ADV7482 is capable of decoding a large selection of

baseband video signals in composite (both single-ended and

differential), S-Video, and component formats. The video

standards supported by the video processor include

The four diagnostic inputs of the ADV7482 provide diagnostic

capability for all differential inputs. The ADV7482 can detect an

STB event on either the positive or the negative composite input

and trigger an interrupt. The 75 Ω (pseudo differential) or 150 Ω

(fully differential) parallel termination resistor enables one

DIAGx pin to sense an STB event on either input, because there

is a minimal voltage drop across the resistor.

• PAL B, PAL D, PAL G, PAL H, PAL I, PAL M, PAL N,

PAL Nc, and PAL 60

• NTSC J, NTSC M, and NTSC 4.43

• SECAM B, SECAM D, SECAM G, SECAM K, and SECAM L

The ADV7482 can automatically detect the video standard and

process it accordingly.

The ADV7482 has a five-line adaptive 2D comb filter that

provides superior chrominance and luminance separation when

decoding a composite video signal. This highly adaptive filter

automatically adjusts its processing mode according to the

Rev. 0 | Page 18 of 20

Data Sheet

ADV7482

video standard and signal quality without requiring user

intervention. Video user controls such as brightness, contrast,

saturation, and hue are also available with the ADV7482.

conditions that may result in audible extraneous noise in the

audio output. On detection of these conditions, a 2-channel

linear PCM audio signal can be ramped down to a mute state to

prevent audio clicks or pops.

The ADV7482 implements the patented Adaptive Digital Line

Length Tracking (ADLLT™) algorithm to track varying video

line lengths from sources such as a VCR. ADLLT enables the

ADV7482 to track and decode poor quality video sources such

as VCRs and noisy sources from tuner outputs, VCD players,

and camcorders. The ADV7482 contains a chroma transient

improvement (CTI) processor that sharpens the edge rate of

chroma transitions, resulting in sharper vertical transitions.

The audio is output on a single flexible serial digital audio

output port supporting I²S-compatible, left justified, and right

justified audio output modes in master mode only. TDM is also

supported, allowing up to eight audio channels with a sample

rate up to 48 kHz to be transmitted over the single serial digital

audio interface.

MIPI CSI-2 TRANSMITTERS

The ACE of the ADV7482 offers improved visual detail using

an algorithm that automatically varies contrast levels to enhance

picture detail. ACE allows the contrast of an image to increase

depending on the content of the picture. Typically, this allows

bright areas to be made brighter and dark areas to be made

darker. However, the ADV7482 ACE feature also allows the

contrast within dark areas to increase without significantly

affecting the bright areas of the picture. This feature is

particularly useful in automotive applications, where it is

important to discern objects in shaded areas.

The ADV7482 features two MIPI CSI-2 transmitters: a four-

lane transmitter (Transmitter A) and a single lane transmitter

(Transmitter B).

The four-lane transmitter consists of four differential data lanes

(DA0N, DA0P, DA1N, DA1P, DA2N, DA2P, DA3N and DA3P),

and a differential clock lane (CLKAN and CLKAP). It supports

four data lanes, two data lanes, and one data lane muxing

options, and can be used to transmit video received on either

the HDMI receiver (processed through the CP), the 8-bit digital

input port, or the AFE (processed through the SDP).

Down dithering converts the output of the ADV7482 from an

8-bit to a 6-bit output, enabling ease of design for standard LCD

panels.

The main features of the four-lane MIPI transmitter

(Transmitter A) include

•

Support for 8-bit and 10-bit YCbCr 4:2:2 video modes.

Support for 24-bit RGB 4:4:4 (RGB888), 18-bit RGB 4:4:4

(RGB666), and 16-bit RGB 4:4:4 (RGB565) video modes.

Support for video formats ranging from 480i to 1080p, and

display resolutions from VGA to UXGA (certain

restrictions apply to the muxing option, video mode, and

video format that can be selected).

The SDP can process a variety of VBI data services, such as

closed captioning (CCAP), wide screen signaling (WSS), and

copy generation management system (CGMS).

•

The ADV7482 is fully Rovi®(Macrovision®) compliant; detection

circuitry enables Type I, Type II, and Type III protection levels

to be identified and reported to the user. The decoder is also

fully robust to all Macrovision signal inputs.

•

Data lanes and clock lane remapping to ease PCB layout.

8-BIT DIGITAL INPUT/OUTPUT PORT

The single lane transmitter consists of a single differential data

lane (DB0N and DB0P) and a differential clock lane (CLKBN

and CLKBP). It transmits video received on the AFE (processed

through the SDP).

The ADV7482 features an 8-bit digital bidirectional port. The

following formats are supported both as input and output ports:

•

8-bit interleaved 4:2:2 SDR input/output with embedded

timing codes

The main features of the single lane MIPI transmitter

(Transmitter B) include

•

8-bit interleaved 4:2:2 DDR input/output with embedded

timing codes

•

Support for 8-bit YCbCr 4:2:2 video mode.

Support for 480i and 576i video formats.

The maximum input and output video resolution supported is

720p/1080i in both SDR and DDR modes.

INTERRUPTS

Video received on the 8-bit digital input port can be routed to

the four-lane MIPI CSI-2 transmitter. Video sent on the 8-bit

digital output port can be routed from either the SD core or the

CP core.

The ADV7482 features two interrupt request pins. INTRQ1 and

INTRQ2 can be programmed to trigger interrupts based on

various selectable events related to the HDMI receiver (video

and audio related), the SDP, and the CP.

AUDIO PROCESSING

The ADV7482 features an audio processor that handles the

audio extracted from the HDMI stream by the HDMI receiver.

It contains an audio mute controller that can detect a variety of

Rev. 0 | Page 19 of 20

ADV7482

Data Sheet

OUTLINE DIMENSIONS

9.10

9.00 SQ

8.90

A1 BALL

CORNER

A1 BALL

CORNER

10

9

8

7

6

5

4

3

2

1

A

B

C

D

E

F

7.20

BSC SQ

0.80

BSC

G

H

J

K

BOTTOM VIEW

DETAIL A

0.90

REF

TOP VIEW

0.975

0.910

0.845

0.26

REF

DETAIL A

*

0.383

0.343

0.303

1.400

1.253

1.173

0.50

0.45

0.40

COPLANARITY

0.12

SEATING

PLANE

BALL DIAMETER

*

COMPLIANT TO JEDEC STANDARDS MO-275-DDAB-1

WITH THE EXCEPTION TO PACKAGE HEIGHT

Figure 15. 100-Ball Chip Scale Package Ball Grid Array [CSP_BGA]

(BC-100-4)

Dimensions shown in millimeters

ORDERING GUIDE

Model^{1, 2, 3}

Temperature Range

Package Description

Package Option

BC-100-4

ADV7482WBBCZ

ADV7482WBBCZ-RL

−40°C to +85°C

100-Ball Chip Scale Package Ball Grid Array [CSP_BGA]

¹Z = RoHS Compliant Part.

²W = Qualified for Automotive Applications.

³This device is programmed with internal HDCP keys. Customer must have HDCP adopter status (consult Digital Protection, LLC, for licensing requirements) to

purchase any components with internal HDCP keys

AUTOMOTIVE PRODUCTS

The ADV7482W models are available with controlled manufacturing to support the quality and reliability requirements of automotive

applications. Note that these automotive models may have specifications that differ from the commercial models; therefore, designers

should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in

automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to

obtain the specific Automotive Reliability reports for these models.

I²C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).

registered trademarks are the property of their respective owners.

D12047-0-6/14(0)

Rev. 0 | Page 20 of 20


型号：	ADV7482
厂家：	ADI
描述：	Integrated Video Decoder and HDMI Receiver
文件：	总20页 (文件大小：372K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADV7482 [ADI]

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