ADXL180DCZ [ADI]
Analog Circuit;
| 型号： | ADXL180DCZ |
| 厂家： | 
ADI |
| 描述： | Analog Circuit |
| 文件： | 总60页 (文件大小：817K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Configurable, High g,
iMEMS Accelerometer
ADXL180
Data Sheet
FEATURES
GENERAL DESCRIPTION
Wide sensor range: 50 g to 500 g
Adjustable filter bandwidth: 100 Hz to 800 Hz
Configurable communication protocol
2-wire, current mode bus interface
Selectable sensor data resolution: 8 bit or 10 bit
Continuous auto-zero
The ADXL180 iMEMS® accelerometer is a configurable, single
axis, integrated satellite sensor that enables low cost solutions
for front and side impact airbag applications. Acceleration data
is sent to the control module via a digital 2-wire current loop
interface bus. The communication protocol is programmable for
compatibility with various automotive interface bus standards.
Fully differential sensor and interface circuitry
High resistance to EMI/RFI
Sensor self-test
The sensor g range is configurable to provide full-scale ranges
from ±±0 g to ±±00 g. The sensor signal third-order, low-pass
Bessel filter bandwidth is configurable at 100 Hz, 200 Hz,
400 Hz, and 800 Hz.
5.0 V to 14.5 V operation
8 bits of user-defined OTP memory
32-bit electronic serial number
Dual device per bus option
The 10-bit analog-to-digital converter (ADC) allows either 8-bit
or 10-bit acceleration data to be transmitted to the control module.
Each part has a unique electronic serial number. The device is
rated for operation from −40°C to +12±°C and is available in a
± mm × ± mm LFCSP package.
APPLICATIONS
Crash sensing
FUNCTIONAL BLOCK DIAGRAM
ADXL180
V
V
V
BP
BC
BN
SERIAL
PORT
SERIAL
NUMBER
COMM
INTERFACE
OSCILLATOR/
TIMING
GENERATOR
OTP
FUSE
ROM
TRIMS
V/Q
V
SCI
SYNC
DETECT
CONFIGURATION
DATA
PROGRAM
INTERFACE
3-POLE
BESSEL
FILTER
10-
BIT
ADC
DIFF
SENSOR
AUTO-
ZERO
DEMOD
AMP
MOD
VOLTAGE
REGULATOR
STATE
MACHINE
V
DD
SUPPLY
MONITOR
V
CM
REF
SELF-
TEST
V
V
SCO
CM
Figure 1.
Rev. B
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Technical Support
©2008–2018 Analog Devices, Inc. All rights reserved.
www.analog.com
ADXL180
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Phase 2: Mode Description ....................................................... 30
Phase 3: Self-Test Diagnostic.................................................... 37
Phase 4: Auto-Zero Initialization............................................. 40
Phase 5: Normal Operation ...................................................... 40
Signal Range and Filtering ............................................................ 41
Transfer Function Overview..................................................... 41
Range............................................................................................ 41
Three-Pole Bessel Filter............................................................. 41
Auto-Zero Operation................................................................. 41
Error Detection............................................................................... 43
Overview ..................................................................................... 43
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 3
Specifications..................................................................................... 4
Absolute Maximum Ratings............................................................ 7
ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions............................. 8
Terminology ...................................................................................... 9
Theory of Operation ...................................................................... 10
Overview...................................................................................... 10
Acceleration Sensor.................................................................... 10
Signal Processing ........................................................................ 11
Digital Communications State Machine ................................. 11
2-Wire Current Modulated Interface....................................... 11
Synchronous Operation and Dual Device Bus....................... 11
Programmed Memory and Configurability............................ 11
Physical Interface............................................................................ 13
Application Circuit..................................................................... 13
Current Modulation................................................................... 13
Manchester Data Encoding....................................................... 14
Operation at Low VBP or Low VDD............................................ 14
Operation at High VDD............................................................... 14
Communications Timing and Bus Topologies ........................... 15
Data Transmission...................................................................... 15
Asynchronous Communication ............................................... 16
Synchronous Communication.................................................. 17
Synchronous Communication Mode—Dual Device............. 19
Data Frame Definition................................................................... 23
Data Frame Transmission Format............................................ 23
Data Frame Configuration Options......................................... 23
Acceleration Data Coding ......................................................... 25
State Vector Coding ................................................................... 26
State Vector Descriptions .......................................................... 26
Transmission Error Detection Options ................................... 27
Application Layer: Communication Protocol State Machine... 28
ADXL180 State Machine ........................................................... 28
Phase 1: Power-on-Reset Initialization.................................... 28
Phase 2: Device Data Transmission ......................................... 28
Parity Error Due to Communications Protocol Configuration
Bit Error....................................................................................... 43
Self-Test Error............................................................................. 44
Offset Error/Offset Drift Monitoring...................................... 44
Voltage Regulator Monitor Reset Operation.......................... 44
Test and Diagnostic Tools.............................................................. 45
VSCI Signal Chain Input Test Pin .............................................. 45
VSCO Analog Signal Chain Output Test Pin ............................ 45
Configuration Specification.......................................................... 46
Overview ..................................................................................... 46
Configuration Mode Transmit Communications Protocol.. 47
Configuration Mode Command (Receive) Communications
Protocol........................................................................................ 48
Configuration Mode Communications Handshaking.......... 49
Configuration and User Data Registers .................................. 50
Configuration Mode Exit .......................................................... 50
Serial Number and Manufacturer Identification Data
Registers....................................................................................... 50
Programming the Configuration and User Data Registers .. 50
OTP Programming Conditions and Considerations ............ 51
Configuration/User Register OTP Parity................................ 51
Configuration Mode Error Reporting..................................... 51
Configuration Register Reference................................................ 52
UD[7:0] User Data Bits.............................................................. 53
UD8 Configuration Bit.............................................................. 53
BDE .............................................................................................. 53
SCOE............................................................................................ 53
FDLY ............................................................................................ 53
ADME.......................................................................................... 53
STI ................................................................................................ 53
Rev. B | Page 2 of 60
Data Sheet
ADXL180
FC[1:0]..........................................................................................53
RG[2:0] .........................................................................................53
MD[1:0]........................................................................................54
SYEN.............................................................................................55
AZE ...............................................................................................55
ERC ...............................................................................................55
DAT...............................................................................................55
SVD...............................................................................................55
CUPAR and CUPRG ..................................................................55
Axis of Sensitivity............................................................................56
Branding...........................................................................................57
Outline Dimensions........................................................................58
Ordering Guide ...........................................................................58
REVISION HISTORY
1/2018—Rev. A to Rev. B
Updated Outline Dimensions........................................................28
Change to Ordering Guide ............................................................58
11/2008—Rev. 0 to Rev. A
Added Data Transmission Section................................................15
Added New Figure 10, Renumbered Sequentially......................15
Added New Figure 11 .....................................................................16
Changes to Figure 14 ......................................................................18
Changes to Figure 16 ......................................................................20
Changes to Synchronization Pulse Detection Section ...............17
8/2008—Revision 0: Initial Version
Rev. B | Page 3 of 60
ADXL180
Data Sheet
SPECIFICATIONS
TA = −40°C to +125°C, VBP − VBN = 5.0 V to 14.5 V, fLP = 400 Hz, acceleration = 0 g, unless otherwise noted.
Table 1.
Parameter1
SENSOR
Symbol Min
Typ
Max
Unit
Test Conditions/Comments
Scale Factor
50 g Range
8-Bit Data
10-Bit Data
100 g Range
8-Bit Data
10-Bit Data
150 g Range
8-Bit Data
10-Bit Data
200 g Range
8-Bit Data
10-Bit Data
250 g Range
8-Bit Data
10-Bit Data
350 g Range
8-bit Data
10-bit Data
500 g Range
8-Bit Data
10-Bit Data
Offset
Measurement frequency: 100 Hz
See Table 37
0.465 0.50
0.116 0.1250
0.535 g/LSB
0.134 g/LSB
0.930 1.00
0.233 0.2500
1.070 g/LSB
0.268 g/LSB
1.395 1.50
0.349 0.3750
1.605 g/LSB
0.401 g/LSB
1.860 2.00
0.465 0.5000
2.140 g/LSB
0.535 g/LSB
2.325 2.50
0.581 0.625
2.675 g/LSB
0.669 g/LSB
3.255 3.50
0.830 0.8925
3.745 g/LSB
0.955 g/LSB
4.650 5.00
1.163 1.2500
5.350 g/LSB
1.338 g/LSB
All ranges, auto-zero disabled
8-Bit Data
−12
−48
+11
+47
LSB
LSB
10-Bit Data
Noise (Peak-to-Peak)
8-Bit Data
10-Bit Data
Self Test
50 g range
10 Hz to 400 Hz
10 Hz to 400 Hz
2
3
LSB
LSB
2
Amplitude
20
20
25
30
30
2
g
g
%
%
kHz
Internal Self-Test Limit
Nonlinearity
Cross-Axis Sensitivity
Resonant Frequency
Q
STI enabled, see Table 35
Of full-scale range
0.2
−5
+5
12.8
1.5
LOW-PASS FILTER
Frequency Response
Third-order
Bessel
Pass Band
fLP
Programmable, see Table 38
−3 dB Frequency
−3 dB Frequency
−3 dB Frequency
−3 dB Frequency
AUTO-ZERO
670
335
167.5 200
83.75 100
800
400
880
440
220
110
Hz
Hz
Hz
Hz
Update Rate
Slow Mode
Fast Mode
5.0
0.5
sec/LSB 10-bit LSB
sec/LSB 10-bit LSB
Rev. B | Page 4 of 60
Data Sheet
ADXL180
Parameter1
Symbol Min
Typ
Max
Unit
Test Conditions/Comments
REGULATOR VOLTAGE MONITOR
Regulator Operating Voltage
Power-Up Reset Voltage
Overvoltage Level
Reset Hysteresis Voltage
COMMUNICATIONS INTERFACE
Quiescent (Idle) Current
Modulation Current
Signal Current
VDD
VPUR
VOV
4.20
4.0
4.95
0.12
V
V
V
V
3.77
4.7
4.23
5.3
See Figure 33
See Figure 33
VHYST
ILDLE
IMOD
ISIG
IDET
tB
5
6
7.7
30
37.7
26
mA
mA
mA
mA
μs
23
28
18
25
31
22
8
ISIG = IIDLE + IMOD
Total including IIDLE
tB = 8 × tCLK
Autodelay Detect Current
Data Bit Period2
Data Bit Duty Cycle
Data Bit Rise/Fall
DDC
45
50
53
%
DDC = tA/tB, see Figure 7
See Figure 7
Fall Time
Rise Time
tR
tF
400
350
1000 ns
1000 ns
Encoding
Manchester
35
See Figure 8
See Figure 12
ADC Conversion Time2
Error Checking (Selectable)
Number of CRC Bits
Number of Parity Bits
Synchronization Pulse Detect
No Detect Limit
tADC
μs
3
1
x³ + x¹+ x0
Even
VSPND
VSPT
3.0
V
V
Detect Threshold
3.5
VBP − VBN + VSPT ≤ 14.5 V; see Figure 14
Threshold Hysteresis
Synchronization Pulse Detect tSPD
Time
0.1
8
V
tCLK
See Figure 14
See Figure 14
Synchronization Pulse
Discharge (Pull-Down)
Time
Synchronization Mode
Transmission Delay
tSPP
40
63
tCLK
tSTD
tCLK
See Figure 14
Configuration Mode Receive
Communications Interface
Detect Threshold
Threshold Hysteresis
Interbit Time
Data 0 Pulse Width
Data 1 Pulse Width
Configuration Mode
Response Time
Configuration Mode Write
Delay Time
VBP During Fuse
Programming
VBP Current During Fuse
Programming
All @ 25°C only; VBP − VBN + VCT ≤ 12.25 V
See Figure 35
VCT
5.25
V
V
tCLK
tCLK
tCLK
μs
0.1
tIB
250
40
80
See Figure 35
See Figure 35
See Figure 35
See Figure 35
tPG0
tPG1
tTM1
55
15
24
50
tTM2
VBPF
IFP
μs
V
See Figure 35
7.5
Compliant up to the maximum operating
voltage
Maximum drawn by the part
mA
Rev. B | Page 5 of 60
ADXL180
Data Sheet
Parameter1
Symbol Min
Typ
Max
Unit
Test Conditions/Comments
ASYNCHRONOUS MODE TIMING2
Message Transmission Period
Phase 2, Mode 0
All Other Phases and Modes
Initialization State (Phase 1)
Device Data State (Phase 2)
Mode 0
tPM0
tP
tI
456
228
100
μs
μs
ADIFX compatible
ms
ms
ms
ms
ms
ms
tDD0
tDD1
tDD2
tDD3
4.10
109
109
117
Mode 1
Mode 2
Mode 3
Self-Test State (Phase 3)
Self-Test Time3
Self-Test Interval
Self-Test Cycle
Auto-Zero Initialization State
(Phase 4)
tST
394
ms
ms
ms
sec
See Figure 28
See Figure 28
See Figure 28
tSTI
tSTC
tAZ
21.9
65.7
14.94
SYNCHRONOUS MODE TIMING4
Message Transmission Period
tPS
tI
N/A
100
Determined by sync pulse, See Figure 14,
minimum tPS = tSPD + tSTD + tM + tB
Initialization State1 (Phase 1)
Device Data State (Phase 2)
Mode 0
Mode 1
Mode 2
ms
ms
ms
ms
ms
ms
tDD0s
tDD1s
tDD2s
tDD3s
9 × tPS
480 × tPS
480 × tPS
512 × tPS
Mode 3
Self-Test State (Phase 3)
Self-Test Time3
Self-Test Interval
Self-Test Cycle
Auto-Zero Initialization State
(Phase 4)
tSTS
1728 × tPS
96 × tPS
288 × tPS
65,535 × tPS
ms
ms
ms
sec
tSTIS
tSTCS
tAZs
CLOCK
Period2
PSRR
tCLK
1.05
1.0
<1
0.95
μs
fCLK = 1/tCLK
LSB
8-bit LSB; test conditions: VBP − VBN = 7.00 V,
V
AC = 500 mV p-p, 100 kHz to 1.1 MHz
POWER SUPPLY HOLDUP TIME
500
30
ns
@ IBUS = ISIG
THERMAL RESISTANCE, JUNCTION θJC
TO CASE
°C/W
1 All parameters are specified using the application circuit shown in Figure 6. CB = 10 nF, CVDD = 100 nF.
2 All timing is driven from the on-chip master clock.
3 tST and tSTS are the times for six self-test cycles. This is the maximum number of cycles in the internal self-test mode.
4 Transmission timing is defined by the internal system clock in asynchronous mode and by the synchronization pulse period in synchronous mode.
Rev. B | Page 6 of 60
Data Sheet
ADXL180
ABSOLUTE MAXIMUM RATINGS
Table 2.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Parameter
Rating
Supply Voltage (VBP − VBN)
Voltage at Any Pin with
Respect to VBN Except VBP
−0.3 V to +21 V
−0.3 V to VDD + 0.3 V
Storage Temperature Range
Soldering Temperature
Operating Temperature Range
ESD All Pins
Latch-Up Current
Mechanical Shock
Unpowered
−55°C to +150°C
255°C
−40°C to +125°C
1.5 kV HBM
100 mA
ESD CAUTION
4000 g (0.5 ms, half sine)
Powered
2000 g (0.5 ms, half sine);
−0.3 V to +7.0 V
1.2 m
20°C/minute
Drop Test (onto Concrete)1
Thermal Gradient
1 Soldered to FR4 coupon printed circuit board (PCB) at the dimensions of
25.4 mm × 25 mm. During test, the PCB is fastened to a support with 46 g
mass, equivalent to a typical satellite module PCB.
tP
tP
CRITICAL ZONE
tL TO tP
RAMP-UP
tL
tL
T
SMAX
T
SMIN
RAMP-DOWN
tS
PREHEAT
T
= 25°C
A
t = 25°C TO PEAK
TIME
Figure 2. ADXL180 Pb-Free Solder Profile
Table 3. ADXL Solder Profile Parameters
Profile Feature
Small Body Pb-Free Assemblies
Average Ramp-Up Rate (TL to TP)
3°C/second maximum
Preheat Temperature Min (TS min) to Temperature Max (TS max) 150°C to 200°C
Time (min to max) (tS)
60 sec to 180 sec
3°C/second maximum
217°C
60 sec to 150 sec
260°C +5/−5°C
TS max to TL Ramp-Up Rate
Time Maintained Above Temperature (TL)
Time (tL)
Peak Temperature (TP)
Time Within 5°C of Actual Peak Temperature (tP)
Ramp-Down Rate
Time 25°C to Peak Temperature
20 sec to 40 sec
6°C/sec maximum
8 minutes maximum
Rev. B | Page 7 of 60
ADXL180
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
V
CM
V
NC
14
NC
13
SCI
16
15
NC
1
V
12
BP
V
CM
DAP1
V
2
3
V
V
11
10
CM
CM
ADXL180
TOP VIEW
(Not to Scale)
V
BN
BN
V
BN
DAP2
NC
4
9
V
BC
5
6
7
8
V
V
V
BN
NC
DD
SCO
NC = NO CONNECT
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
2
3
NC
VCM
VBN
Reserved for Analog Devices, Inc., Use Only. VBN or do not connect.
Reserved for Analog Devices Use Only. Do not connect.
Negative Bus Voltage.
4
5
6
7
NC
VDD
NC
VSCO
VBN
Reserved for Analog Devices Use Only. VBN or do not connect.
Voltage Regulator Bypass Capacitor.
Reserved for Analog Devices Use Only. VBN or do not connect.
Reserved for Analog Devices Use Only. Do not connect.
Negative Bus Voltage.
8
9
VBC
VBN
VCM
VBP
NC
Daisy-Chain Connection. Daisy-chain connection to VBP of the second device or do not connect.
Negative Bus Voltage.
Reserved for Analog Devices Use Only. Do not connect.
Positive Bus Voltage.
Reserved for Analog Devices Use Only. VBN or do not connect.
Reserved for Analog Devices Use Only. VBN or no connect
Analog Signal Chain Input. VBN when not in use.
Reserved for Analog Devices Use Only. Do not connect.
Exposed Pad: Reserved for Analog Devices Use Only. Do not connect.
Exposed Pad: Negative Bus Voltage.
10
11
12
13
14
15
16
DAP1
DAP2
NC
VSCI
VCM
VCM
VBN
Rev. B | Page 8 of 60
Data Sheet
ADXL180
TERMINOLOGY
Idle Current
Full-Scale Range (FSR)
Idle current is the current of the device when at rest, waiting for
a synchronization pulse, or in between current modulation.
The full-scale range of a device, also referred to as the dynamic
range, is the maximum and minimum g level that reports on the
output following the internal filtering. As a reference, there is
usually a trade-off in increased sensitivity and resolution for
decreased full-scale range, and vice versa.
Modulation Current
Modulation current is the amount of current that the ADXL180
device pulls from the bus when communicating. For more
information, see Figure 7.
Noise
Phase
Device noise is the noise content between 10 Hz and 400 Hz, as
noted in the Specifications Table 1. Device noise can be measured
by performing an FFT on the digital output and measuring the
noise content between the specified frequency limits.
A phase is a stage in the ADXL180 state machine. For more
information, see Figure 22.
Mode
Mode refers to the selection of the Phase 2 method of device
data communication. The ADXL180 is configurable into four
unique operating modes.
Sensitivity
The sensitivity of a device is the amount of output change per
input change. In this device, it is most usually referred to in
units of LSB/g.
CRC
A cyclic redundancy check (CRC) is calculated from a set of
data and then transmitted alongside that data. If the calculation
technique is defined and known to the receiving device, the
receiver can then check whether the CRC bits match the data. If
they do not match, a transmission error has occurred.
Scale Factor
The scale factor is the amount of input change per output change.
In this device, it is most usually referred to in units of g/LSB.
Offset
Offset is the low frequency component of the output signal that
is not due to changes in input acceleration. Slow moving effects,
such as temperature changes and self-heating during start up,
may affect offset, but the time scale for these effects is beyond
that of a typical shock or crash event.
Parity
Parity is defined by the count of 1s in a binary string of data.
If this count is even, then the data is determined to have even
parity. Often a bit is used, such as the CUPAR, in a configuration
register that is defined in such a way as to establish a particular
parity in the register to detect single bit changes during the life
of the device. This is possible because a single bit change changes
parity and a monitor circuit can detect this. Similarly, a parity
bit can be added in a data transmission to detect single bit errors
if the parity of communication is preestablished for the transmit
and receive systems.
Auto-Zero
Auto-zero is an offset compensation technique intended to
reduce the long term offset drift effects of temperature and
aging. This technique is designed to limit interaction with true
acceleration signals. For more information, see Figure 32.
Rise/Fall Times
The device rise time is defined as the amount of time necessary
for the Manchester encoded signal (IMOD) to transition from 10%
to 90% of its final value (ISIG). Device fall time is the amount of
time required for the IMOD signal to fall from 90% of ISIG to within
10% of IIDLE
.
Rev. B | Page 9 of 60
ADXL180
Data Sheet
THEORY OF OPERATION
sensor is such that the displacement signal is differential
OVERVIEW
between the two measurement channels. Using the fully
differential sensor and an antiphase clocking scheme helps
reject electrical environmental noise (see Figure 5).
The ADXL180 is a complete satellite system, including
acceleration sensor, data filtering, digital protocol functionality,
and a 2-wire, high-voltage, current-modulated bus interface
communications port.
The ADXL180 acceleration sensor uses two electrically isolated,
mechanically coupled sensors to measure acceleration as shown
in Figure 5. The clock phasing of the readout is such that the
electrical signal due to acceleration is differential between the
channels and environmental disturbances couple in as a common-
mode signal. The following differential amplifier can then extract
the acceleration signal while suppressing the environmental noise.
ACCELERATION SENSOR
The ADXL180 provides a fully differential sensor structure and
circuit path. This device uses electrical feedback with zero force
feedback. Figure 4 is a simplified view of one of the differential
sensor elements. Each sensor includes several differential capa-
citor unit cells. Each cell is composed of fixed plates attached to the
substrate and movable plates attached to the frame. Displacement
of the frame changes the differential capacitance, which the on-
chip circuitry measures.
Electrical feedback adjusts the amplitudes of the fixed capacitor
plates’ drive signals such that the ac signal on the moving plates
is zero. The feedback signal is linearly proportional to the applied
acceleration. This feedback technique ensures that there is no
net electrostatic force applied to the sensor.
Complementary signals drive the fixed capacitor plates. The
relative phasing between the two halves of the differential
ANCHOR
MOVABLE
FRAME
PLATE
CAPACITORS
FIXED
PLATES
UNIT SENSING
CELL
UNIT SELF-TEST
FORCING CELL
MOVING
PLATE
ANCHOR
Figure 4. Simplified View of ADXL180 Sensor Under Acceleration
ACCELERATION SENSING AXIS
+X-AXIS SENSOR
+
EMI DISTURBANCE RESPONSE
COMMON TO BOTH CHANNELS
SPRING
0
+
V
OUT
AMP
–
ISOLATED
MECHANICAL
COUPLINGS
0
ACCELERATION RESPONSE
DIFFERENTIAL BETWEEN CHANNELS
–X-AXIS SENSOR
–
Figure 5. Differential Acceleration Sensing
Rev. B | Page 10 of 60
Data Sheet
ADXL180
SIGNAL PROCESSING
SYNCHRONOUS OPERATION AND DUAL DEVICE
BUS
The ADXL180 contains an on-board set of signal processing
blocks both prior to and after ADC conversion. The first stage is
a fully differential, switched capacitor, low-pass, three-pole
Bessel filter. Range scaling is also handled in one of the filter
blocks, enabling 50 g to 500 g range capability. At this point, an
analog output test signal (VSCO) is available to the user in a
diagnostic mode. The signal then converts by a 10-bit rail-to-rail
SAR ADC. In the digital section, an auto-zero routine is
available to the user as part of the state machine in addition to
error detection features such as offset drift detection.
In a point-to-point bus topology, the ADXL180 supports asyn-
chronous transmission of data to the receive device every 228 μs,
controlled by the on-board state machine. A synchronous option
is also available, allowing two devices to be on the same bus
using time division multiplexing where each device transmits its
data during a known time slot.
Synchronization is achieved by voltage modulated synchronization
pulses, configuring the ADXL180 device into a synchronous
mode, and establishing data frame time slots. The high voltage
communication port registers valid synchronization pulses and
enables message-by-message advancement of the state machine
rather than asynchronous timed regular data transmission.
DIGITAL COMMUNICATIONS STATE MACHINE
The ADXL180 digital state machine is based on a Core 5 phase
state machine implemented in high density CMOS. This state
machine handles the sequential states of
PROGRAMMED MEMORY AND CONFIGURABILITY
Factory-Programmed Serial Number and Manufacturer
Information
Phase 1. Initialization.
Phase 2. Device data transmission, including individual serial
number and user-programmed data.
Phase 3. Self-diagnostic, including automatic full electro-
mechanical self-test with internal error detection
available.
Phase 4. Auto-zero initialization, if selected. During this phase,
acceleration data is already available.
Phase 5. Normal acceleration data transmission.
The ADXL180 includes a 32-bit factory-programmed serial
number, as shown in Table 5. This serial number transmits
during Phase 2 of startup for all devices to enable robust quality
tracking of individual devices, and it is field readable. In addition,
this data includes revision information and manufacturer identi-
fication in case multiple devices used within a single application
are from different manufacturers or generations of parts.
User-Programmable Data Register
2-WIRE CURRENT MODULATED INTERFACE
The ADXL180 gives the user an 8-bit register of user-program-
mable data, which is transmitted during Phase 2 of the state
machine. In addition, the UD8 bit, a ninth user-available bit,
is transmitted separately during Phase 2 and can be used for
various purposes, such as orientation definition or module type.
The data that is generated during these five phases is trans-
mitted using a 2-wire high voltage communication port. This
allows the device to be powered by a fixed supply voltage, and
communicate back to the system or ECU electronics by modulating
current. Current modulated messages are encoded using Man-
chester encoding.
Table 5. Factory Programmed and User-Programmed Memory
MSB
D7
LSB
Configuration Mode
Programmed By Register Address
Configuration Mode
Register Name
D6
D5
D4
D3
D2
D1
D0
User
0000b
0001b
0010b
0011b
1011b
1100b
1101b
1110b
1111b
UREG
CREG0
CREG1
CREG2
SN0
SN1
SN2
SN3
MFGID
UD7
UD8
STI
UD6
BDE
AZE
UD5
UD4
UD3
UD2
UD1
DLY1
DAT
RG1
SNB1
UD0
DLY0
MAN
RG0
MD1 MD0 FDLY DLY2
SYEN ADME ERC
FC0
SVD
RG2
CUPRG CUPAR SCOE FC1
Factory
SNB7 SNB6 SNB5 SNB4 SNB3 SNB2
SNB15 SNB14 SNB13 SNB12 SNB11 SNB10 SNB9
SNB23 SNB22 SNB21 SNB20 SNB19 SNB18 SNB17 SNB16
SNB31 SNB30 SNB29 SNB28 SNB27 SNB26 SNB25 SNB24
SNPRG SNPAR REV2 REV1 REV0 MFGID2 MFGID1 MFGID0
SNB0
SNB8
Rev. B | Page 11 of 60
ADXL180
Data Sheet
User-Programmed Configuration
Application Layer (ISO Layer 7)
At each of these previously described points in the system, the
ADXL180 is highly configurable for different applications. The
organization and configurable items are briefly described in this
section but are covered in depth in the remainder of this data sheet.
The serial number and configuration data transmission mode
and self-test (internal self-test pass/fail discrimination or
external self-test data evaluation).
Other signal processing related aspects of the function of the
ADXL180 can also be configured as follows:
Physical Layer (ISO Layer 1)
The bus interface hardware definition including the phase of
Manchester encoding and synchronization pulse enable/disable.
•
•
•
•
Sensor scale factor (range)
Signal chain low-pass filter bandwidth
Auto-zero: enable/disable
Data Link Layer (ISO Layer 2)
User-defined data in the user data register
The specifics of the data frame format including the data width
(8-bit or 10-bit data), state vector (enable/disable), and error
detection (parity or CRC).
Rev. B | Page 12 of 60
Data Sheet
ADXL180
PHYSICAL INTERFACE
APPLICATION CIRCUIT
CURRENT MODULATION
When the ADXL±80 device is powered on, it uses current
modulation to transmit data. Normally, the device pulls IIDLE
current. When modulating, an additional current of IMOD is
pulled from the sensor bus. See Figure 7.
A typical application circuit is shown in Figure 6. The two capa-
citors shown in Figure 6 are typically ceramic, X7R, multilayer
SMT capacitors. Maximum recommended values of ESR and
ESL are 250 mΩ and 2 nH, respectively. Capacitor tolerances of
±±0ꢀ are recommended.
ADXL180
V
V
BP
BP
SUPPLY AND
CONFIGURATION
BUS
V
DD
C
10nF
B
C
VDD
100nF
V
V
BN
BN
Figure 6. Application Circuit
tB
tA
90%
I
MOD
50%
10%
I
IDLE
tRF
TIME
Figure 7. Communication Current Modulation Timing
Rev. B | Page 13 of 60
ADXL180
Data Sheet
Table 6. MAN Options
Manchester
MAN Coding
MANCHESTER DATA ENCODING
Start
Bits
To encode data within the current modulation, the ADXL180
uses Manchester encoding. Manchester encoding works on the
principle of transitions representing binary 1s and 0s, as shown
in Figure 8. Manchester encoding uses a set of predefined start
bits to transmit the clocking within each message, see Figure 9.
The pattern of the start bits allows the receiver to synchronize
itself to the bit stream. These start bits are user selectable.
Logic 0
Logic 1
0
Manchester-1
(Default)
1, 0
Falling edge Rising edge
1
Manchester-2
0, 0
Rising edge Falling edge
The phase of the Manchester encoded data can be selected via
a bit in the configuration registers. See Figure 8 and Figure 9
for details. The configuration bit that sets the phase of the Man-
chester encoder also sets the value of the two start bits. The start
bits are 1, 0 for Manchester-1 and 0, 0 for Manchester-2. For
phase and start bit information, see Table 6.
START BITS
LOGIC 1
LOGIC 0 LOGIC 1
LOGIC 0
I
I
SIG
BUS
CURRENT
OPERATION AT LOW VBP OR LOW VDD
IDLE
The ADXL180 monitors its internal regulator voltage to ensure
proper operation. If the bus voltage drops, or the internal regu-
lator voltage drops below the VPUR reset threshold, the device
resets. See the Voltage Regulator Monitor Reset Operation
section.
Figure 8. Manchester-1, Start Bits and Phase
START BITS
LOGIC 0
LOGIC 0 LOGIC 1
LOGIC 0
OPERATION AT HIGH VDD
I
I
SIG
BUS
CURRENT
If the regulator pin detects a high voltage, such as from a
short or leakage condition, the ADXL180 detects an error.
See the Voltage Regulator Monitor Reset Operation section
for more details.
IDLE
Figure 9. Manchester-2, Bit Coding
Rev. B | Page 14 of 60
Data Sheet
ADXL180
COMMUNICATIONS TIMING AND BUS TOPOLOGIES
DATA TRANSMISSION
The analog data (available to the user by enabling the VSCO
output) is sampled every 228 μs when the device is configured
to run asynchronously. In synchronous operation, an ADC
conversion is triggered upon the detection of a valid sync pulse.
In both cases, the data is held until a subsequent ADC
conversion is performed. This results in an additional time
delay of either 228 μs or one sync pulse period from the
sampling of the analog data to when it is transmitted via
manchester encoded data. Analog-to-digital conversions are
performed prior to the device entering run-time mode
(Phase 5) thereby ensuring that the data from the ADC is never
in an unknown state. This holds true upon receipt of the first
sync pulse in run-time mode (Phase 5).
n1
n0
n2
n4
n5
INPUT
ACCELERATION
n–2 n–1
n9
…
n8
n7
n6
n3
ADC CONVERSION
(38µs CONVERSION
EVERY 228µs.)
…
…
n0
n1
ADXL180 RETURN
CURRENT
n1
n0
n4
n5
DIGITAL
WAVEFORM
n–3 n–2 n–1
n3
n6
n8
…
…
n7
n2
THE DATA ACQUIRED DURING A GIVEN ADC CYCLE IS NOT
TRANSMITTED UNTIL A SUBSEQUENT DATA ACQUISITION
IS PERFORMED. IN ASYNCHRONOUS OPERATION MODE,
THIS DELAY 228µs.
Figure 10. Asynchronous Data Transmission (Timing Not To Scale)
Rev. B | Page 15 of 60
ADXL180
Data Sheet
n1
n0
n2
n4
INPUT
ACCELERATION
n5
n–2 n–1
n9
n8
n7
…
n6
n3
ONCE A VALID SYNC PULSE IS DETECTED
THE DEVICE WILL PERFORM AN ADC
CONVERSION ON THE (AVAILABLE) ANALOG
INPUT SIGNAL.
SYNC PULSE
…
ADC CONVERSION
(PERFORMED AFTER SYNC
PULSE DETECTION)
n0
…
THE DATA FROM THE ADC CONVERSION
IS HELD UNTIL A SUBSEQUENT SYNC PULSE
IS TRANSMITTED TO THE DEVICE.
ADXL180 RETURN
CURRENT
n0
…
n1
n0
n4
n5
DIGITAL
WAVEFORM
n–3 n–2 n–1
n3
n6
n8
…
n7
n2
Figure 11. Synchronous Data Transmission (Timing Not To Scale)
ASYNCHRONOUS COMMUNICATION
1
tP
ADC SAMPLE
tADC
1
tP
2
2
tM
tM
I
LOOP CURRENT
MOD
DATA FRAME
DATA FRAME
I
IDLE
TIME
1tP
2tM
=
tDD DURING PHASE 2, MODE 0
=
tCLK TIMES THE NUMBER OF BITS TRANSMITTED
Figure 12. Asynchronous Mode Data Transmission Timing
The ADXL180 data transmissions in their default mode run
asynchronous to the control module. In this mode, the ADXL180
timing is entirely based on the internal clock of the device. After
the initialization phases are complete, the ADXL180 begins to
transmit sensor data every 228 μs. The device transmits sensor
data until the supply voltage falls below the required minimum
operating level. If an internal error is detected, the device trans-
mits the appropriate error code until the supply voltage falls
below the required minimum operating level.
Asynchronous Single Device Point-to-Point Topology
A single device is wired in the point-to-point configuration
as shown in Figure 13. This configuration must be used in
asynchronous mode. Do not use two asynchronous devices on
one bus because communications errors are very likely to occur.
Rev. B | Page 16 of 60
Data Sheet
ADXL180
pulse is fully below VSPND, the pulse is rejected and not detected.
The counter saturates at zero. The synchronization pulse is con-
sidered valid on the next clock after the counter is incremented
to seven counts. The counter is gated off (blanked) after a valid
synchronization pulse is detected. Once the sync pulse has been
recognized as valid, a command is issued to start the acceleration
data analog-to-digital conversion. The ADC does not run conti-
nuously in synchronous mode.
CENTER
MODULE
NC
NC
V
V
V
V
BP
BN
BN
BC
DEVICE 1
Figure 13. Asynchronous Point-To-Point Topology
SYNCHRONOUS COMMUNICATION
The synchronization pulse detector is reenabled after tB, which
is an idle bit transmission following the last data frame bit (see
the Data Frame Definition section). At this point, the device is
ready to receive the next sync pulse.
The ADXL180 data transmission can be synchronized to the
control module. This synchronization is accomplished by the
control module generating a synchronization pulse to the
ADXL180. The synchronization pulse is a voltage pulse that
is superimposed on the supply voltage by the center module.
Figure 14 shows the synchronization pulse timing. Upon detecting
a synchronization pulse, the ADXL180 transmits its data.
If the application requires or uses a pulse of nonuniform shape,
such as, for example, rising above VSPT and subsequently
toggling such that it falls below VSPT one or more times before
tSPD, consult Analog Devices, Inc., applications support for
further information on application specific pulse recognition.
Configuring the ADXL180 for Synchronous Operation
Table 7. Sync Enable (SYEN) Options
SYEN Definition
Note, this counter means that when an invalid length sync pulse
of less than seven counts is followed less than seven counts later
by a subsequent sync pulse, detection may occur when the
counter is incremented further by less than seven counts by the
second pulse.
0
Synchronization pulse disabled. The device transmits
data every 228 μs based on the internal clock of the
device. Data is transmitted according to an internal state
machine sequence when powered on (default).
1
Synchronization pulse enabled. The device requires a
synchronization pulse to sample and transmit data. Data
transmission is in accordance with the internal state
machine of the device.
Bus Discharge Enable
Table 8. Bus Discharge Enable
BDE
Definition
0
1
Bus discharge disabled (default).
Bus discharge enabled. Only active when SYEN = 1.
The user-defined SYEN bit determines whether the device is
used in synchronous operation or remains asynchronous.
SYEN, as shown in Table 7, must be set to SYEN = 1 to enable
synchronous operation.
The bus discharge enable (BDE) bit in the configuration registers
can be set to aid in the discharge of the bus voltage after a syn-
chronization pulse is detected. If the BDE bit is set, the ADXL180
changes the bus current (IBUS) level from IIDLE to ISIG once a valid
synchronization pulse is detected. The control module then sets
the voltage on the bus to the nominal operating level. The bus
capacitance is discharged by the ADXL180 device. The current
level of ISIG acts as an active pull-down current to return the VBP
voltage to the nominal supply voltage. The pull-down current
pulse can also be used as a handshake with the control module
acting as an acknowledgement of the synchronization pulse.
Synchronization Pulse Detection
The ADXL180 uses a digital integration method to validate the
synchronization pulse. The ADXL180 detects the supply voltage
(VBP) rising above the level of VSPT. The state of the level detection
circuit controls the count direction of an up-down counter. The
counter is clocked every 1 μs. The counter is incremented if the
ADXL180 detects a level exceeding VSPT. The counter is decre-
mented if the ADXL180 detects a level below VSPND. Operation
is not defined between these thresholds. If the synchronization
Rev. B | Page 17 of 60
ADXL180
Data Sheet
NO DETECT CASE
DETECT CASE
tPS
V
SPT
V
SPND
BUS
VOLTAGE
V
SP
tSPD
tB
tSPD
SYNCH
DETECT/
SYNC DETECT BLANKING
BLANKING
tADC
tADC
ADC BUSY
tSTD
BUS DISCHARGE
CURRENT
BUS DISCHARGE CURRENT
(IF BDE = 1)
tSPP
(IF BDE = 1)
tM
DATA FRAME
ADXL180
RETURN
CURRENT
DATA FRAME
DATA CONTAINED IS FROM
THE PERVIOUS ADC CONVERSION.
Figure 14. Synchronization Pulse Timing (Single Device)
Rev. B | Page 18 of 60
Data Sheet
ADXL180
Synchronous Single Device Point-to-Point Topology
ADXL180 devices to share a single pair of wires from the
control module for power and communications. This is
accomplished using time division multiplexing where each
device transmits its data during a known time slot. The time
slot used by each device is determined by the delay time from
detection of a synchronization pulse to the beginning of data
transmission. The data transmission delay time is selectable in
the configuration registers. The following discussion uses the
convention that the first time slot is named Time Slot A and the
second time slot is named Time Slot B (see Figure 16). The two
ADXL180 devices can be wired in either a parallel or series
mode as described in the following sections. If a synchronization
pulse is not detected, no data is sent. This is true for all initiali-
zation phases and normal run-time operation. Note that the
minimum synchronization pulse period is
A single device is wired in the point-to-point configuration as
shown in Figure 15. The standard use of this configuration is
with no delay devices. It is possible to use this topology with
fixed delay devices as well, such as if line noise reduction after a
sync pulse transmission is desired.
CENTER
MODULE
NC
NC
V
V
V
V
BC
BP
BN
BN
DEVICE 1
Figure 15. Single Device—Synchronous Communication
SYNCHRONOUS COMMUNICATION MODE—DUAL
DEVICE
t
SPD + tDLY + tM + tB
The ADXL180 can be used in a dual device synchronous
communication mode. This mode allows a maximum of two
Rev. B | Page 19 of 60
ADXL180
Data Sheet
V
SPT
V
BP
BUS
VOLTAGE
tSPD
tB
SYNC
DETECT/
BLANKING
DEVICE 1
tSTD
BUS
DISCHARGE
CURRENT
tSPP
tM
AD22181
RETURN
CURRENT
DEVICE 1
DEVICE 1
tB
SYNC
DETECT/
BLANKING
tDLY
tM
AD22181
RETURN
CURRENT
DEVICE 2
DEVICE 2
tSPP
TIME SLOT A
DEVICE 1
TIME SLOT B
DEVICE 2
BUS
CURRENT
TIME
Figure 16. Synchronization Pulse Timing (Dual Device)
Rev. B | Page 20 of 60
Data Sheet
ADXL180
The autodelay mode allows two identically configured devices
to be wired in a series configuration. The two devices automatically
configure the two node network upon power up. The configura-
tion bit (ADME) must be set to enable the autodelay mode. A
device with the ADME bit set sinks a bus current of IDET for 6 ms
upon power up.
Configuring Synchronous Operation
Delay Selection
As shown in Table 9, the user can select the data timing of the
second device to establish the predefined data slots. This allows
for the fastest possible sampling, if required, and Table 9 shows
the number of data frame bits the first device may transmit to
ensure no overlap. To further reduce device interference from
line or system circuit effects, use higher FDLY amounts than the
minimum.
The first device in the series configuration (Device 2) detects
the presence of the other device in the series (Device 1) by
sensing the IDET current passing though itself from Pin VBP to
Pin VBC during the first 6 ms of the power-up initialization
Phase 1. If the current draw of Device 1 is present, Device 2
delays its data transmission by the amount of time programmed
into the configuration register via Bit DLY2, Bit DLY1, and
Bit DLY0. Therefore, Device 2 transmits its data during Time
Slot B. The data transmission delay time of Device 2 is usually
selected based on the number of bits in the data frame. After
receiving a valid synchronization pulse, only Device 1 sinks ISIG
as an active pull-down current (if the BDE bit is set) to return
the VBP voltage to the nominal supply voltage. Device 2 (using
Time Slot B) never sinks ISIG as an active pull-down even if the
BDE bit is set.
Table 9. Data Transmission Delay Codes
Delay Time
Maximum First Data
Frame Bits
DLY2 DLY1 DLY0 (tDLY
)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
205 μs
213 ꢀs
221 ꢀs
229 ꢀs
237 ꢀs
245 ꢀs
253 ꢀs
261 ꢀs
11
12
13
14
15
16
17
18
In a single device network, the unit that would be called Device 1
is not present. Therefore, the single device detects no current
draw through the VBC pin during the power-on initialization. In
this case, the single device transmits data during Time Slot A.
This allows a device programmed with a nonminimum delay
time to be used as either Device 1 or Device 2 in a series
configuration or as a single device.
Fixed Delay Mode
Fixed delay mode establishes which device transmits in the
second time slot. FDLY requires that either (but not both) of
the two devices on the bus have the FDLY bit programmed to
enable the data frame transmission delay time. The device with
the FDLY bit set is named Device 2. Device 2 delays its data
transmission by the amount of time programmed into the
configuration register via Bit DLY2, Bit DLY1, and Bit DLY0.
After receiving a valid synchronization pulse, only Device 1,
without the FDLY bit set, sinks ISIG as an active bus pull-down
current (if the BDE bit is set) to return the VBP voltage to the
nominal supply voltage.
The autodelay mode detect function samples the state of the
autodelay detect sense circuit every 500 μs during the first 6 ms
of Phase 1. A total of four consecutive samples must be valid to
place the device in the autodelay mode.
Caution: do not send an additional valid sync pulse during the
blanking period, tSTD or tB, for either device, because it incurs
the risk of the signal being misinterpreted and a change in
message response timing.
Table 10. Fixed Delay Mode
FDLY Definition
0
1
Fixed delay mode disabled (default).
Fixed delay mode enabled. Device transmits data in the
time slot delayed by tDLY as defined by DLY2 to DLY0.
Dual Device Synchronous Parallel Topology
The two devices are wired in a parallel configuration as shown in
Figure 17. This configuration must be run in the fixed delay mode.
Caution: do not set Device 2 using Time Slot B as BDE = 1.
Only Device 1 should draw ISIG as an active pull-down when the
BDE bit is set. It is good practice to never have BDE = 1 and
FDLY = 1 in the same device.
CENTER
MODULE
NC
NC
NC
NC
V
V
V
V
V
V
V
V
BC
BP
BN
BN
BC
BP
BN
BN
Autodelay Mode
DEVICE 1
DEVICE 2
Table 11. Autodelay Mode Enable (ADME) Options
ADME Definition
Figure 17. Dual Device—Parallel Configuration
0
Autodelay mode is disabled. The part does not check
for a second device on the line and does not pull any
extra current during startup (default).
1
Autodelay mode detection is enabled. Pull down IDET
for 6 ms at power up.
Rev. B | Page 21 of 60
ADXL180
Data Sheet
Dual Device Synchronous Series Topology
CENTER
MODULE
The two devices are wired in a series configuration as shown in
Figure 18. The series configuration can be configured to run in
either of two modes: fixed delay or autodelay. These modes are
configured using the FDLY and ADME bits in the configuration
registers.
NC
NC
V
V
V
V
V
V
V
V
BC
BP
BN
BN
BC
BP
BN
BN
DEVICE 1
DEVICE 2
Figure 18. Dual Device—Series Configuration
Rev. B | Page 22 of 60
Data Sheet
ADXL180
DATA FRAME DEFINITION
DATA FRAME TRANSMISSION FORMAT
tM
DATA BITS
START START
BIT 0 BIT 1
I
MOD
LOOP
CURRENT
I
IDLE
0
tB
DATA BITS
START START
BIT 0
BIT 1
LOGIC SIGNAL
AT CONTROL
MODULE DECODER
‘0’
‘1’
0
TIME
Figure 19. Data Message Timing (Manchester-1, Bit Coding)
A data frame starts with two start bits. The value of these two
bits is determined by the Manchester encoding mode select bit.
See the Manchester Data Encoding section. Figure 19 shows the
basic format and timing of the data frame. A 1-bit idle time is
an implicit stop bit at the end of a data frame.
Error checking—a single parity bit or a 3-bit CRC code can
be selected.
State vector—identifies the type of data in the data field. It
can be disabled. When it is disabled, it is not transmitted.
Data—the device data and sensor data can be transmitted
in either 8-bit or 10-bit mode.
DATA FRAME CONFIGURATION OPTIONS
Figure 20 diagrams the protocol data frame construction
options. The data frame can be broken into four specific fields
as follows:
Depending on the settings of the configuration register bits
(ERC, SVD, and DAT), the data frame can be from 11 bits to
18 bits in length. Figure 20 shows the formats of the available
data frames. Note that the error checking field is transmitted
first when the CRC is selected but transmitted last when parity
is selected. See Figure 20 for specific examples of full protocol
configurations.
Start bits—two start bits are always transmitted at the start
of the data frame. These bits are used to synchronize the
center module decoder with the Manchester encoded signal.
Rev. B | Page 23 of 60
ADXL180
Data Sheet
CREG BIT NAME
TRANSMITTED FIRST
ERC
SVD
DAT
START
BITS
STATE
CRC
1
10-BIT DATA
VECTOR
0
1
0
2
0
1
2
0
1
1
2
2
3
4
5
6
7
7
8
9
0
0
0
0
1
1
1
1
0
0
1
0
1
0
1
0
1
START
BITS
STATE
VECTOR
CRC
1
8-BIT DATA
0
1
1
0
0
1
1
0
1
0
0
0
0
0
0
0
2
2
2
0
0
0
0
0
3
1
1
1
1
1
2
0
3
3
6
6
6
6
9
4
7
7
7
7
5
8
6
9
START
BITS
CRC
1
10-BIT DATA
0
1
2
2
2
2
4
5
START
BITS
CRC
1
8-BIT DATA
0
1
3
4
5
START
BITS
STATE
VECTOR
10-BIT DATA
P
0
0
1
1
2
3
4
5
5
8
8
9
START
BITS
STATE
VECTOR
8-BIT DATA
P
0
0
1
1
1
1
2
3
6
6
4
7
7
START
BITS
10-BIT DATA
P
0
0
1
2
4
5
START
BITS
8-BIT DATA
P
0
0
1
2
3
4
5
Figure 20. Data Frame Formats
Rev. B | Page 24 of 60
Data Sheet
ADXL180
Table 14. 8-Bit Full Sensor Data Range Coding
ACCELERATION DATA CODING
Binary (Twos
01 1111 1111
01 1111 1110
01 1111 1101
01 1111 1100
00 0000 0001
00 0000 0000
11 1111 1111
11 1111 1110
10 0000 0010
10 0000 0001
10 0000 0000
Decimal Hex
Complement) Description
+127
0x7F
0111 1111
Most positive (+FS)
acceleration value
+126
+125
…
0x7E
0x7D
…
0111 1110
0111 1101
…
…
…
…
+1
0
−1
…
0x01
0x00
0xFF
…
0000 0001
0000 0000
1111 1111
…
1000 0010
1000 0001
1000 0000
…
Zero (0) acceleration value
…
…
…
…
−126
−127
−128
0x82
0x81
0x80
Most negative (−FS)
acceleration value
0
–FS
+FS
Table 15. 10-Bit Full Sensor Data Range Coding
ACCELERATION INPUT
Figure 21. 10-Bit ADC Transfer Characteristic
Binary (Twos
Decimal Hex
Complement) Description
Table 12. DAT Data Bit Options
DAT Definition
+511
0x1FF 01 1111 1111
Most positive (+FS)
acceleration value
0
10-bit data sensor data transmitted. 8-bit Phase 2
configuration data left justified in 10-bit data frame
(default).
+510
+509
…
+1
0
−1
…
−510
−511
−512
0x1FE 01 1111 1110
0x1FD 01 1111 1101
…
…
…
…
…
…
1
8-bit sensor data transmitted.
0x01
0x00
00 0000 0001
00 0000 0000
The sensor data coding is dependent on the configuration
register bit settings. Either 8-bit or 10-bit sensor data can be
transmitted. This 8-bit or 10-bit data range is either full range
or reduced range. Whether the data range is full or reduced
depends on the setting of the state vector disable and auto-zero
enable configuration register bits. For more information, see
Table 13.
Zero (0) acceleration value
0x3FF 11 1111 1111
…
…
…
…
…
…
0x202 10 0000 0010
0x201 10 0000 0001
0x200 10 0000 0000
Most negative (−FS)
acceleration value
Table 16. 8-Bit Reduced Sensor Data Range Coding
Table 13. Full and Reduced Sensor and Device Data Ranges
SVD1
AZE2
Data Range
Binary (Twos
Decimal Hex
Complement) Description
0
0
1
1
0
1
0
1
Full
+116
0x74
0111 0100
Most positive (+FS)
Reduced
Reduced3
Reduced3
acceleration value
…
0
…
0x00
…
…
0000 0000
Zero (0) acceleration
value
1 SVD is the state vector disable configuration bit.
2 AZE is the auto-zero enable configuration bit.
3 A configuration error is reported if Phase 2 Mode 0 is selected with the state
vector disabled (SVD = 1). The ADXL180 transmits a configuration error code
during run time and no sensor data is transmitted.
…
…
…
…
−116
0x8C
1000 1100
Most negative (−FS)
acceleration value
Table 17. 10-Bit Reduced Sensor Data Range Coding
Binary (Twos
Complement) Description
Decimal Hex
+464
0x1D0 01 1101 0000
Most positive (+FS)
acceleration value
…
…
…
…
0
…
0x000 00 0000 0000
Zero (0) acceleration value
…
…
…
−464
0x230 10 0011 0000
Most negative (−FS)
acceleration value
Rev. B | Page 25 of 60
ADXL180
Data Sheet
The 3-bit state vector field contains a code that defines the
STATE VECTOR CODING
meaning of the data contained in the 8- or 10-bit data field.
These definitions are listed in Table 19. When selected, the 3-bit
state vector is appended to the 8- or 10-bit data field and
transmitted as part of the data frame.
Table 18. SVD Data Bit Options
SVD Definition
0
1
State vector is enabled (default).
State vector is disabled, a reduced data range is used.
STATE VECTOR DESCRIPTIONS
Table 19. State Vector Table
SV2 SV1 SV0 State
Phase1 Data In Frame
Description
0
0
0
Normal
operation
5
Sensor data
This is the running state of the ADXL180. During this state,
an analog-to-digital conversion is performed, and the
resulting sensor data is transmitted every 228 μs in asyn-
chronous mode or every 250 μs in synchronous mode.
0
0
1
Device data
2
Serial number/manufacturer
ID/range/user and configuration tion data. See the ADXL180 State Machine section for
The data field contains serial number and/or configura-
register data
the device data transmission specifics for each MD1 to
MD0 selection.
0
0
1
1
1
1
0
0
0
1
0
1
Self Test 0
Self Test 1
3
Sensor data with the self-test
signal unasserted
Sensor data with the self-test
signal asserted
The ADXL180 is in sensor self-test mode. The internal
sensor self-test signal is unasserted.
The ADXL180 is in sensor self-test mode. The internal
sensor self-test signal is asserted.
The ADXL180 is in Phase 4. The auto-zero function is
running in the fast initialization mode.
This state vector indicates that the data sent is from the
OTP memory of the ADXL180. This data type is only
sent when the device is in configuration mode.
3
Auto-zero
initialization
OTP memory
data
4
Sensor data
NA
OTP memory data
(configuration mode data)
1
1
1
1
0
1
Status/error
Reserved
NA
NA
Status/error data (see Table 39)
Reserved
This state is set when an internal error is detected by
the ADXL180. The data field contains the error type. See
the Error Detection section for details.
1 NA is not applicable.
Rev. B | Page 26 of 60
Data Sheet
ADXL180
calculation is performed from MSB to LSB on the entire data
TRANSMISSION ERROR DETECTION OPTIONS
frame. The CRC state registers are initialized to zero. Therefore,
when checking the result of the transmission, the final CRC
check state should be zero. The three CRC bits are always the
three least significant bits in the transmission.
There are two error checking methods available: a 3-bit CRC
and a 1-bit parity check. These are determined by the user-
selected Bit ERC.
Table 20. Error Check (ERC) Bit Options
ERC Definition
Parity Encoding
The ADXL180 can be programmed so that the LSB of each data
transmission contains a 1-bit parity check bit. The 1-bit parity
check is even parity. The parity algorithm sets the parity bit to
be either a one or a zero; thus, the resulting number of ones
transmitted in the data frame is always an even number.
0
A 3-bit CRC is included in the message. CRC is calculated
using the polynomial x3 + x1 + x0. (Default.)
One parity bit is included in the message. CRC is not used.
It is a bit that is set such that even parity is achieved in
the transmitted message.
1
CRC Encoding
The ADXL180 can be programmed to utilize a 3-bit CRC. The
polynomial used for the encoding is x3 + x1 + x0. The CRC
Rev. B | Page 27 of 60
ADXL180
Data Sheet
APPLICATION LAYER: COMMUNICATION PROTOCOL STATE MACHINE
Table 21. ADXL180 Start-Up Sequence Summary
Phase 1
Initialization
Phase 4 Auto-Zero
Initialization
Phase 5
Run Time
Name
Phase 2 Device Data
Phase 3 Self-Test
Function
Power-on reset
None
Sequence self-test
pattern
Fast auto-zero
Slow auto-
zero
Data Type
Transmitted
None
Serial number,
configuration and range
Sensor, range, device OK Sensor
or delimiter
Sensor
PHASE 1: POWER-ON-RESET INITIALIZATION
ADXL180 STATE MACHINE
The power-on-reset initialization period is typically 100 ms
long. It is the period of time from when the internal reset signal
is deasserted until the beginning of Phase 2. This time allows
for circuit stabilization and entry into configuration mode. No
data is transmitted during Phase 1. No errors are reported
during Phase 1. Additionally, until phase 1 is exited, the device
does not respond to a transmitted sync pulse (see Table 21).
After power is applied and stabilized, the ADXL180 follows a
five-phase start-up sequence. The basic function of each phase
is fixed as shown in Figure 22. The five phases and the function
modes available in each phase are detailed in the following
sections.
RESET
V
> V
PUR
DD
PHASE 2: DEVICE DATA TRANSMISSION
RESET
RESET
Overview
PHASE 1 INITIALIZATION
The device data consists of the serial number and configuration
data. Device data is transmitted during Phase 2. This data can
be transmitted in one of four configurable modes (see Table 22).
These modes are described in detail in the following sections.
The parity of all OTP memory blocks is continuously monitored
(provided that the block has been programmed) beginning at
the end of Phase 2. See the Parity Encoding section for more
details.
PHASE 2
DEVICE DATA
ERROR
RESET
PHASE 3
SELF-TEST
Table 22. MD Phase 2 Device Data Mode Select Codes
ERROR
MD1 MD0 Name
Definition
0
0
0
1
Mode 0 ADIFX mode device data (default)
Mode 1 Range data only (range selection
limited)
Mode 2 8-bit coded device data
Mode 3 10-bit coded device data
RESET
RESET
PHASE 4
AUTO-ZERO INITIALIZATION
1
1
0
1
ERROR
ERROR
During Phase 2, if Mode 0, Mode 1, or Mode 2 is selected, the
device data is 8-bit data. If the 10-bit data mode is selected in
combination with Phase 2 Mode 0, Mode 1, or Mode 2, the 8-bit
device data is left justified in the 10-bit data field. The two LSBs
are held at zero (see Table 24).
PHASE 5
NORMAL OPERATION
RESET
ERROR STATE
TRANSMIT ERROR CODE
Figure 22. ADXL180 Start-Up Sequence
Rev. B | Page 28 of 60
Data Sheet
ADXL180
Influence of MD on Data Range
Table 23. MD Settings and Device Data Ranges
Mode (Device Data)
MD1
MD0
0
0
0
0
SVD1
AZE2
0
1
0
Data Range
Full
Reduced
Configuration error
Configuration error
Full
Reduced
Reduced
Reduced
Full
Reduced
Reduced
Reduced
Full
0: ADIFX3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
(All Configuration Data, Serial Number, and
Manufacturer ID)
1
1: Range Data Only3
(Limited Range Selection)
1
1
1
1
0
1
0
1
2: 8-Bit Coded Device Data3
(UD[7:0], Serial Number, and Range)
0
0
0
0
0
1
0
1
3: 10-Bit Coded Device Data4
(UD[7:0], Serial Number, and Range)
1
0
1
1
Reduced
Reduced
Reduced
1
0
1
1
1 SVD is the state vector disable configuration bit.
2 AZE is the auto-zero enable configuration bit
3 If Phase 2 Mode 0, Mode 1, or Mode 2 is selected, the device data is 8-bit data. If the 10-bit data mode is selected in combination with Phase 2 Mode 0, Mode 1, or Mode
2, the 8-bit device data is left justified in the 10-bit data field. The two LSBs are held at zero (see Table 24).
4 The 10-bit device data mode (Phase 2 Mode 3) is incompatible with the 8-bit data mode (the DAT bit is set to 1). The device transmits a configuration error code if
Phase 2 Mode 3 is selected and the DAT bit is set to 1. No sensor data is transmitted.
Device Data Mapping in Phase 2
Table 24. Phase 2 Device Data Bit Mapping in 10-Bit Sensor Data Mode
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
Device
Data MSB
Device
Data
Device
Data
Device
Data
Device
Data
Device
Data
Device
Data
Device
Data LSB
0
0
Table 25. Phase 2 Device Data Bit Mapping in 8-Bit Sensor Data Mode
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
Device Data LSB
Device Data MSB
Device Data
Device Data
Device Data
Device Data
Device Data
Device Data
Rev. B | Page 29 of 60
ADXL180
Data Sheet
Asynchronous Mode
PHASE 2: MODE DESCRIPTION
Mode 0
The device data is transmitted at a time interval of 456 μs based
on the internal clock of the ADXL180. The 456 μs period is
twice the normal transmission time interval of 228 μs.
The Mode 0 option for Phase 2 transmits the entire contents of
the configuration registers, the serial number and the manufac-
turer ID byte. The total number of messages transmitted during
Phase 2, Mode 0 is 9.
Synchronous Mode
In synchronous mode, the device data is transmitted in
response to the synchronization pulse generated by the control
module. See the Synchronization Pulse Detection section.
PHASE 1
TRANSMIT SN0 BYTE
tP
TRANSMIT SN1 BYTE
tP
TRANSMIT SN2 BYTE
tP
TRANSMIT SN3 BYTE
PHASE 2
MODE 0
tP
9 × tP
TRANSMIT MANUFACTURER ID
BYTE
tP
TRANSMIT UREG BYTE
tP
TRANSMIT CREG0 BYTE
tP
TRANSMIT CREG1 BYTE
tP
TRANSMIT CREG2 BYTE
tP
PHASE 3
Figure 23. Phase 2 Mode 0 State Machine
Table 26. Mode 0 Serial Number and Configuration Data Byte Sequence
Byte 8
Byte 7
Byte 6
Byte 5
Byte 4
Byte 3
SN3
Byte 2
Byte 1
Byte 0
CREG2
CREG1
CREG0
UREG
Manufacturer ID
SN2
SN1
SN0
Table 27. Mode 0 Manufacturer ID Byte
MSB
LSB
MFGID0
SNPRG
SNPAR
REV2
REV1
REV0
MFGID2
MFGID1
Rev. B | Page 30 of 60
Data Sheet
ADXL180
Table 28. Mode 0 Manufacturer ID Byte Codes
A configuration error is flagged when Phase 2 Mode 1 is
selected with a range code selection that sets a range other than
one of the ranges listed in Table 29. In this case, the error state is
entered immediately instead of entering Phase 1. See Table 39
for the error coding. When both Phase 2 Mode 1 and the 10-bit
data mode are selected, all range data is transmitted with two
zero value LSBs appended (that is, left-justified data), as shown
in Table 24. Note that, when Mode 1 is selected with the state
vector enabled and auto-zero is not enabled, the full range
sensor data coding is used (see the Data Frame Transmission
Format section).
Manufacturer
ID Byte Field
Code
(Binary)
Comments
MFGID2|MFGID2|MGFID0 101b
Analog Devices
identification code
Die revision code
REV2|REV1|REV0
000b
Mode 1
When Phase 2 Mode 1 is selected, only the range data is
transmitted during Phase 2. The total number of messages
transmitted during Phase 2 Mode 1 is 480.
PHASE 1
Therefore, the positive and negative full-scale ends of the sensor
data range overlap with the range and error codes. The state
vector distinguishes between the types of transmitted data. The
state vector identifies the range data as device data (state vector
= 001b) and error codes as status/error data (state vector = 110b).
Normal operation sensor data has a state vector of 000b (see
Table 19 for details).
480 × tP
PHASE 2
MODE 1
TRANSMIT RANGE BYTE
479
PHASE 3
Figure 24. Phase 2 Mode 1 State Machine
Table 29. Phase 2 Mode 1 Range Data Coding
8-Bit Data
10-Bit Data
Hex
Decimal
Hex
Decimal
−488
State Vector Code
Description
−122
−125
−128
0x86
0x83
0x80
0x218
0x20C
0x200
001b
001b
001b
250 g measurement range
50 g measurement range
100 g measurement range
−500
−512
Rev. B | Page 31 of 60
ADXL180
Data Sheet
Mode 2
used (see the Data Frame Transmission Format section).
Therefore, the positive and negative full-scale ends of the sensor
data range overlap with the device data and status/error codes.
The state vector distinguishes between the types of transmitted
data. The state vector identifies the device data (state vector =
001b) and the status/error codes (state vector = 110b). Normal
operation sensor data has a state vector of 000b. See Table 19
and Table 16.
Device Data
When Mode 2 is selected, the device data that is transmitted
consists of the UREG byte, four configuration register bytes (see
Figure 26), and the 4-byte serial number. The data is transmitted
one bit per message. Each message represents either a Logic 0 or
a Logic 1. The code, 0x7A (+122d), represents a Logic 0 and the
code, 0x79 (+121d), represents a Logic 1 in 8-bit data mode. See
Table 30 for both 8-bit and 10-bit data coding. The delimiter code
depends on the range setting in the configuration registers. The
delimiter byte used for each range setting is listed in Table 31.
The data is transmitted in the following sequence and as shown
in Figure 25. The total number of messages transmitted during
Mode 2 Phase 2 is 480.
PHASE 1
PHASE 2
TRANSMIT DELIMITER CODE
MODE 2
63
1. Transmit delimiter code 64 times.
2. Transmit 32 messages of serial number data (32 bits of
information, one bit per message).
TRANSMIT SN DATA BIT CODE
3. Transmit 12 messages of user bits (12 bits of information,
one bit per message). See Table 32.
31
480 × tP
4. Transmit delimiter code eight times.
5. Repeat Step 2 through Step 4 seven times.
TRANSMIT USER DATA BIT CODE
11
User Bits and User Register (UREG)
The user bits (U11 to U0) information transmitted during
Phase 2 Mode 2 maps into the user and configuration register
data stored in the OTP memory of the ADXL180. This includes
the 8-bits in the UREG. The mapping is shown in Table 32. See
the Configuration Specification section for information about
the definition and function of the user and configuration
registers data bits.
TRANSMIT DELIMITER CODE
7
7
PHASE 3
10-Bit Data and Mode 2
Figure 25. Phase 2 Mode 2 State Machine
During Phase 2 when both Mode 2 and the 10-bit data mode
are selected, all device data messages are transmitted with two
zero-value LSBs appended (that is, left-justified data). Note that,
when Mode 2 is selected with the state vector enabled and the
auto-zero is not enabled, the full range sensor data coding is
Rev. B | Page 32 of 60
Data Sheet
ADXL180
PHASE 1
PHASE 2
PHASE 3
ST DATA/
STATUS
SERIAL NUMBER
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
USER BITS
DELIMITER
33 34 35 36 37 38 39 40 41 42 43 44
45 46 47 48 49 50 51 52
Figure 26. Phase 2 Mode 2 Device Data Transmission
Table 30. Phase 2 Mode 2 Sensor and Device Data Coding
8-Bit Data 10-Bit Data
Decimal
Hex
Decimal
Hex
Data Type
Undefined
Undefined
Error code
Undefined
Undefined
Logic 0
Description
+127
+126
+125
+124
+123
+122
+121
+120
+119
+118
+117
+116
+115
…
0x7F
0x7E
0x7D
0x7C
0x7B
0x7A
0x79
0x78
0x77
0x76
0x75
0x74
0x73
…
+508
+504
+500
+496
+492
+488
+484
+480
+476
+472
+468
+464
+460
…
0x1FC
0x1F8
0x1F4
0x1F0
0x1EC
0x1E8
0x1E4
0x1E0
0x1DC
0x1D8
0x1D4
0x1D0
0x1CC
…
Unused
Unused
Device error
Unused
Device OK
Device data : Logic 0
Device data : Logic 1
Unused
Logic 1
Undefined
Undefined
Undefined
Undefined
Acceleration data
Acceleration data
…
Unused
Unused
Unused
Most positive (+FS) acceleration value
0
…
0x00
…
0
…
0x 000
…
Acceleration data
…
Zero (0) acceleration value
−115
−116
−117
−118
−119
−120
−121
−122
−123
−124
−125
0x8D
0x8C
0x8B
0x8A
0x89
0x88
0x87
0x86
0x85
0x84
0x83
−460
−464
−468
−472
−476
−480
−484
−488
−492
−496
−500
0x234
0x230
0x22C
0x228
0x224
0x220
0x21C
0x218
0x214
0x210
0x20C
Acceleration data
Acceleration data
Undefined
Undefined
Undefined
Undefined
Undefined
Status code
Undefined
Undefined
Status code
Most negative (−FS) acceleration value
Unused
Unused
Unused
Unused
Unused
250 g measurement range
Unused
Unused
50 g measurement range
Rev. B | Page 33 of 60
ADXL180
Data Sheet
8-Bit Data
10-Bit Data
Decimal
−126
−127
Hex
Decimal
Hex
Data Type
Undefined
Undefined
Status code
Description
0x82
0x81
0x80
−504
−508
−512
0x208
0x204
0x200
Unused
Unused
−128
±100 g measurement range
Table 31. Phase 2 Mode 2 Delimiter Coding
8-Bit Data
10-Bit Data
Range
50 g
State Vector Code
Decimal
Hex
Decimal
−500
−512
−500
−500
−488
−500
−500
Hex
001b
001b
001b
001b
001b
001b
001b
−125
−128
−125
−125
−122
−125
−125
0x83
0x80
0x83
0x83
0x86
0x83
0x83
0x20C
0x200
0x20C
0x20C
0x218
0x20C
0x20C
100 g
150 g
200 g
250 g
350 g
500 g
Rev. B | Page 34 of 60
Data Sheet
ADXL180
Table 32. Phase 2 Mode 2 User Bit Mapping
32 times for each nybble number. The specific meaning of each
data nybble is defined in Table 33. The total number of messages
transmitted during Phase 2 in Mode 3 is (32 × 16) = 512.
User Bit
U11
U10
U09
U08
U07
U06
U05
U04
U03
U02
U01
U00
Device Data Bit Name
SYEN
RG2
RG1
RG0
UD7
UD6
UD5
UD4
UD3
UD2
UD1
UD0
User Register (UREG)
The User Register UREG[7:0], in Mode 3 transmit during
Nybble 7 (UREG[7:4]) and Nybble 8 (UREG[3:0]).
Use with State Vector Enabled
When Mode 3 is selected with the state vector enabled and the
auto-zero not enabled, the full range sensor data coding is used
(see the Data Frame Transmission Format section). Therefore,
the positive and negative full-scale ends of the sensor data range
overlap with the device data and status data codes. The state vector
distinguishes between the types of transmitted data. The state
vector identifies the device data (state vector = 001b) and status
codes as status/error data (state vector = 110b). Normal opera-
tion sensor data has a state vector of 000b (see Table 19).
Mode 3
Device Data
In Phase 2 Mode 3, the 10-bit data codes, −512 (0x200) to −481
(0x21F), are used to transmit the device data. The data coding
is shown in Table 34 and in Figure 27. One 4-bit nybble of the
device data (encoded as one of 16 nybble codes) is transmitted
in each 10-bit message. The number of the data nybble is identi-
fied by the preceding nybble number (NN) code as detailed in
Table 33. This allows a total of (16 × 4) = 64 unique bits of device
data to be transmitted during Phase 2. Each message is repeated
Illegal Configuration: Mode 3 and 8-Bit Data
A configuration error is flagged if Phase 2 Mode 3 is selected
and the configuration register is programmed to select the 8-bit
data mode. In this case, the error state is entered immediately
instead of Phase 1. See the Error Detection section for more
information.
PHASE 1
PHASE 2
PHASE 3
DATA
16
DATA
16
DATA1
NN1 DATA1 NN2 DATA2
NN2 DATA2
NN16
NN16
NN1
32 MESSAGES
32 MESSAGES
32 MESSAGES
Figure 27. Mode 3 Device Data Transmission
Table 33. Phase 2 Mode 3 Device Data Mapping
Device Data Nybble No.
11
Definition
Binary Code
001
Nybble Sent
0011
Protocol ID
2
3
4
5
Number of nybbles sent
Manufacturer
Sensor type
Sensor range2
16
10000
101
00001
0000
0000
1010
0001
0000
Analog Devices
Accelerometer
100 g
50 g
0001
0001
200 g
0010
0010
Other
0011
0011
6
BDE and RS
RS = 0, BDE = 0
RS = 0, BDE = 1
RS = 1, BDE = 0
RS = 1, BDE = 1
0 to 255
0000
0001
0010
0011
XXXX3
XXXX
XXXX
XXXX
0000
0001
0010
0011
XXXX
XXXX
XXXX
XXXX
7
8
9
10
User data (UD Bits[7:4])
User data (UD Bits[3:0])
Serial number (Bits[31:28])
Serial number (Bits[27:24])
0 to 255
Rev. B | Page 35 of 60
ADXL180
Data Sheet
Device Data Nybble No.
Definition
Serial number (Bits[23:20])
Binary Code
XXXX
XXXX
XXXX
XXXX
Nybble Sent
XXXX
XXXX
XXXX
XXXX
11
12
13
14
15
16
Serial number (Bits[19:16])
Serial number (Bits[15:12])
Serial number (Bits[11:8])
Serial number (Bits[7:4])
Serial number (Bits[3:0])
XXXX
XXXX
XXXX
XXXX
1 Data Nybble 1 is transmitted first.
2 If the configuration register settings have configured the ADXL180 for a range other than 50 g, 100 g, or 200 g, the other code (0011b) is sent. In these cases, the UD
bits can be used to indicate the actual range.
3 X indicates that the data is device dependent.
Table 34. Phase 2 Mode 3 Sensor and Device Data Coding
Decimal
Hex
Data Type
Description
511
…
0x1FF
…
Undefined
Undefined
Unused
Unused
501
0x1F5
0x1F4
0x1F3
…
Undefined
Unused
500
Status
Device Error
499
…
Undefined
Undefined
Unused
Unused
488
0x1E8
0x1E7
0x1E6
…
Undefined
Unused
487
Status
Device OK
486
…
Undefined
Undefined
Unused
Unused
465
0x1D1
0x1D0
…
0x000
…
0x230
0x22F
…
Undefined
Unused
464
…
0
…
−464
−465
…
Acceleration Data
Acceleration Data
Acceleration Data
Acceleration Data
Acceleration Data
Undefined
Most positive (+FS) acceleration value
…
Zero (0) acceleration value
…
Most negative (−FS) acceleration value
Unused
Unused
Undefined
−480
−481
−482
−483
−484
−485
−486
−487
−488
−489
−490
−491
−492
−493
−494
−495
−496
0x220
0x21F
0x21E
0x21D
0x21C
0x21B
0x21A
0x219
0x218
0x217
0x216
0x215
0x214
0x213
0x212
0x211
0x210
Undefined
Unused
Data Nybble
Data Nybble
Data Nybble
Data Nybble
Data Nybble
Data Nybble
Data Nybble
Data Nybble
Data Nybble
Data Nybble
Data Nybble
Data Nybble
Data Nybble
Data Nybble
Data Nybble
Data Nybble
Device Data 1111
Device Data 1110
Device Data 1101
Device Data 1100
Device Data 1011
Device Data 1010
Device Data 1001
Device Data 1000
Device Data 0111
Device Data 0110
Device Data 0101
Device Data 0100
Device Data 0011
Device Data 0010
Device Data 0001
Device Data 0000
Rev. B | Page 36 of 60
Data Sheet
ADXL180
Decimal
−497
−498
−499
−500
−501
−502
−503
−504
−505
−506
−507
−508
−509
−510
−511
−512
Hex
Data Type
Description
0x20F
0x20E
0x20D
0x20C
0x20B
0x20A
0x209
0x208
0x207
0x206
0x205
0x204
0x203
0x202
0x201
0x00
Nybble Number
Nybble Number
Nybble Number
Nybble Number
Nybble Number
Nybble Number
Nybble Number
Nybble Number
Nybble Number
Nybble Number
Nybble Number
Nybble Number
Nybble Number
Nybble Number
Nybble Number
Nybble Number
Device Data Nybble 16
Device Data Nybble 15
Device Data Nybble 14
Device Data Nybble 13
Device Data Nybble 12
Device Data Nybble 11
Device Data Nybble 10
Device Data Nybble 9
Device Data Nybble 8
Device Data Nybble 7
Device Data Nybble 6
Device Data Nybble 5
Device Data Nybble 4
Device Data Nybble 3
Device Data Nybble 2
Device Data Nybble 1
toggled by selecting or deselecting the STI configuration bit, as
shown in Table 35.
PHASE 3: SELF-TEST DIAGNOSTIC
The ADXL180 has two self-test modes, internal and external. In
both modes the ADXL180 applies an internally generated electro-
static force to the sensor, simulating an acceleration force. This
force causes the sensor proof-mass to displace. This displacement
is transduced by the sensor interface electronics and passed
through the signal chain to the ADC. When in external self-test
mode, the ADXL180 transmits sensor data while activating the
self-test signal several times. When in internal self-test mode,
the ADXL180 transmits data dependent on the setting of the
Phase 2 Mode select bits. While doing so, the ADXL180 activates
the self-test signal several times. It then examines the results
and either continues the start-up initialization sequence or
reports an error. The detailed operation of the two self-test
modes is described in the following sections.
Table 35. Self Test Internal (STI) Options
STI
Definition
0
External self-test. User must monitor self-test data to
verify proper operation. Device does not monitor its own
response to the self-test stimulus. (Default.)
1
Internal self-test. The device internally monitors self-test
data to determine proper operation.
External Self-Test
The external self-test mode applies an electrostatic force to the
sensor (simulating an acceleration force) and transmits the
sensor data to the control module. This allows the control
module to measure the subsequent change in the sensor output
value. The signal path low-pass filter of the ADXL180 has a
slower response time than the rise time of the internal self-test
control (STC) signal. Therefore, the sensor data transmitted
during the external self-test sequence follows the rise and fall
times of the low pass filter in response to the internal STC
signal. The state vector (if enabled) provides the relative timing
information indicating when the internal STC signal is applied
to the sensor.
Concept of Self-Test
The fixed plates in the forcing cells are normally kept at the
same potential as that of the movable frame. When self-test is
activated, the voltage between the fixed plates and the moving
plates in the forcing cells is changed. This creates an attractive
electrostatic force, which causes the frame to move toward one
set of fixed plates. The entire signal channel is active; therefore,
the sensor displacement causes a signal change at the output of
the ADC.
The STC signal activates six times during the self-test state of
the ADXL180 (see Figure 28). During external self-test, an
average of the zero self-test value is computed and subsequently
used to provide an initial offset correction value for the auto-
zero function. See the Phase 4: Auto-Zero Initialization section
for more information.
Internal and External Self-Test Option
There are two selectable modes of operation for self-test. The
self-test modes are internal and external. The self-test mode is
Rev. B | Page 37 of 60
ADXL180
Data Sheet
PHASE 3
tST
PHASE 4
LOOP
CURRENT
I
MOD
I
IDLE
tSTC
tSTI
tSTI
tSTI
tSTI
STC
TIME
Figure 28. External Self-Test Control Timing
c. Calculate difference (VSTP) − (VSTZ1) and compare to
specified minimum and maximum difference.
d. Calculate the absolute difference (VSTZ1) − (VSTZ2) and
compare to the maximum value.
e. If delta is less than or equal to four counts (10 bits),
then the self-test is a pass.
Internal Self-Test
The internal mode self-test applies an electrostatic force to
the sensor (simulating an acceleration force) and measures
the change in the sensor output value. A self-test cycle (tSTC
constitutes one activation and deactivation of the self-test
force. A self-test cycle is considered passed if the change in
the sensor output value falls within the expected minimum
and maximum self-test response levels. The internal self-test
(Phase 3) is exited and Phase 4 is entered upon completing
the second of any two successful self-test cycles.
)
f. If delta is greater than or equal to five counts (10 bits),
then the self-test is a fail.
10. If any measurements in Step 9 fail to achieve the defined
limits, then repeat Step 1 through Step 9. Repeat a maximum
of five times.
A self-test cycle is considered failed if the change in the sensor
output value is not within the expected levels. The self-test cycle
is then repeated. The self-test cycle is run a maximum of six
times. The internal self-test (Phase 3) is exited and the error
state entered if fewer than two of the six self-test cycles pass.
Once the error state is entered, the self-test error code is
transmitted until the device is reset.
11. If fewer than two out of the six self-test cycles pass, an internal
self-test error flag is set. The error state is then entered. The
self-test error code is sent until the device is reset.
12. Phase 4 is entered upon completing the second of any two
successful self-test cycles.
Influence of MD Selections On Transmitted Self-Test Data
Table 36. Phase 3 Data Transmitted During Internal Self-Test
The internal self-test sequence is as follows:
1. Wait 32 consecutive ADC samples.
2. Average 64 consecutive ADC samples (VSTZ1).
3. Enable self-test voltage.
4. Wait 32 consecutive ADC samples.
5. Average 64 consecutive ADC samples (VSTP).
6. Disable self-test voltage.
7. Wait 32 consecutive ADC samples.
8. Average 64 consecutive ADC samples (VSTZ2).
9. Compare measured values.
MD1
MD0
Data
0
0
1
1
0
1
0
1
Device OK
Range
Delimiter
Device OK
When the internal self-test mode is selected, the type of data
transmitted during Phase 3 is dependent on the setting of the
Phase 2 mode select bits (MD1 and MD0). See Table 36 and
Table 39 for the Device OK code. See the Phase 2: Device Data
Transmission section for specifics of the delimiter and range codes.
a. Compare (VSTZ1) to specified minimum and maximum
offset tolerance.
b. Compare (VSTZ2) to specified minimum and maximum
offset tolerance.
Rev. B | Page 38 of 60
Data Sheet
ADXL180
ENTER SELF-TEST CYCLE
WAIT 32 SAMPLES
CALCULATE
STD = V – V
STP STZ1
NO
AVERAGE 64 SAMPLES
STD
MIN
< STD < STD
YES
V
MAX
STZ1
ASSERT SELF-TEST SIGNAL
WAIT 32 SAMPLES
CALCULATE
STZ = |V – V
|
STZ1 STZ2
NO
STZ ≤ 4 LSB*
AVERAGE 64 SAMPLES
V
*10-BIT LSB
STP
YES
INCREMENT PASS COUNT
DEASSERT
SELF-TEST SIGNAL
INCREMENT CYCLE COUNT
WAIT 32 SAMPLES
YES
ENTER PHASE 4
PASS COUNT = 2
NO
AVERAGE 64 SAMPLES
V
STZ2
NO
NO
NO
CYCLE COUNT = 6
YES
ENTER SELF-TEST CYCLE
OFFSET
MIN
< V
< OFFSET
MAX
STZ1
YES
SET SELF-TEST FAIL CODE
ENTER ERROR STATE
OFFSET < V
MIN STZ2
< OFFSET
MAX
YES
Figure 30. Internal Self-Test State Machine
Figure 29. First Half Is Joined to Second Half of ST Chain
Rev. B | Page 39 of 60
ADXL180
Data Sheet
specifics. No acceleration data is transmitted when the
ADXL180 is in the error state.
PHASE 4: AUTO-ZERO INITIALIZATION
If auto-zero is not enabled, upon entering Phase 4, the
ADXL180 immediately passes from Phase 4 to Phase 5.
PHASE 5: NORMAL OPERATION
If auto-zero is not enabled, upon entering Phase 5, the
ADXL180 transmits the measured (raw) acceleration signal
every 228 μs (in asynchronous mode) until power down. In
synchronous mode, raw data is transmitted in response to every
synchronization pulse until power down.
Fast Auto-Zero Mode
If auto-zero is enabled, the fast auto-zero routine begins upon
entering Phase 4. The last offset average measurement (VSTZ2)
of Phase 3 is used as a starting value for the fast auto-zero
routine. This occurs whether internal or external self-test has
been selected. See the External Self-Test section. The auto-zero
function is described in the Auto-Zero Operation section.
Slow Auto-Zero
If auto-zero is enabled, the slow auto-zero routine begins upon
entering Phase 5. The ADXL180 transmits the offset corrected
acceleration signal every 228 μs (in asynchronous mode) until
power down. In synchronous mode, offset corrected data is
transmitted in response to every synchronization pulse until
power down. The auto-zero function is described in the Auto-
Zero Operation section.
The ADXL180 transmits the offset corrected sensor data every
228 μs in asynchronous mode during Phase 4. When in
synchronous mode, the ADXL180 transmits the offset corrected
sensor data after receiving a valid synchronization pulse during
Phase 4. The number of sensor values sent during Phase 4 is
65,535. Therefore, in asynchronous mode, the Phase 4 time
period is nominally 15 seconds long, during which time the
device fully responds to acceleration input.
Error Reporting
Although the auto-zero routine continually corrects for offset
drift, if an error is detected during Phase 5, (for example, offset
out of range, OTP parity error, and so forth), the appropriate
error code is set and the error state is entered. The error code is
transmitted until the device is reset. See Table 39 for error code
specifics. No acceleration data is transmitted when the
ADXL180 is in the error state.
Error Reporting
If an error is detected during Phase 4, (for example, offset out of
range, OTP parity error, and so forth), the appropriate error
code is set and the error state is entered. The error code is
transmitted until the device is reset. See Table 39 for error code
Rev. B | Page 40 of 60
Data Sheet
ADXL180
SIGNAL RANGE AND FILTERING
TRANSFER FUNCTION OVERVIEW
THREE-POLE BESSEL FILTER
The three-pole, low-pass Bessel filter has a selectable −3 dB
corner (fLP). The corner can be set to 100 Hz, 200 Hz, 400 Hz, or
800 Hz by programming the filter corner (FC) bits in the
configuration registers. In the pass band between fHP and fLP, the
response of the ADXL180 is flat with the nominal scale factor
defined by the settings of the range (RG) bits in the
Table 38. FC Low-Pass Filter Bandwidth Frequency Select
Codes
FC1
FC0
−3 dB LP Frequency
0
0
400 Hz
0
1
ꢀ00 Hz
1
0
100 Hz
configuration registers (see Figure 31). The auto-zero function
creates a first-order high-pass filter with a −3 dB corner at fLP.
Note that the output of this filter is slew rate limited. The auto-
zero function can be disabled by setting the appropriate bit in
the configuration registers. See the Specifications section for
more information.
1
1
800 Hz
By configuring the FC1 and FC0 bits as shown in Table 38, the
output filter on the ADXL 180 can be set. This adjusts the −3 dB
frequency of the output filter to the desired bandwidth. The
ADXL180 low-pass filter is a third-order, low-pass Bessel filter
with a −60 dB per decade roll-off. See the Specifications table
for more information on the tolerances of the low-pass filter
bandwidth.
–3dB
NOMINAL
SENSITIVITY
AUTO-ZERO OPERATION
+20dB/DECADE
–60dB/DECADE
The auto-zero function is enabled by setting the appropriate bit
in the configuration registers, see Table 44. This function helps
reduce slow offset drifts due to aging, temperature, and so forth.
The acceleration signal offset is determined by passing the
acceleration signal through a one-pole digital low-pass filter.
The output of this filter is then slew rate limited. The slew rate
limited offset value is then subtracted from the acceleration
data. This forms a slew rate limited high-pass filter as shown in
Figure 32.
LSB/g
AUTO-ZERO FILTER
BESSEL FILTER
fHP
fLP
FREQUENCY
Figure 31. Bode Plot of ADXL180 Transfer Function
RANGE
Table 37. RG[2:0] Sensor Range Select Codes
If auto-zero mode is enabled, a fast offset compensation is
performed during start up of Phase 4 (fast auto-zero mode).
The filter output is set to the last zero reading average
performed by the self-test (Phase 3). The −3 dB frequency of
the digital low-pass filter is approximately 0.08 Hz, and the slew
rate limiter output (and therefore the offset correction) is
updated every 0.5 seconds. The fast update mode (Phase 4) is
15 seconds long in asynchronous mode and 65,535 × tPS in
synchronous mode (see the Phase 4: Auto-Zero Initialization
section).
RG2
RG1
RG0
Range
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
±±0 g
±100 g
±ꢀ±0 g
±1±0 g
±ꢀ00 g
±ꢁ±0 g
±±00 g
Not used
The ADXL180 is configurable into the g-ranges shown in Table 37.
Adjusting the device g-range alters the g/LSB scale factor.
Selecting the 50 g range offers increased data resolution of
0.125 g/LSB; however, input signals above 50 g appear clipped
on the output of the device. Selecting a higher g-rating decreases
the resolution of data; however, it allows for a wider full-scale
range of observable signals.
If auto-zero mode is enabled, an offset compensation is
performed during normal operation (Phase 5). This offset
compensation is performed at a slower rate than during the
auto-zero initialization (Phase 4). The −3 dB frequency of the
digital low-pass filter is approximately 0.01 Hz and the slew rate
limiter output (and therefore the offset correction) is updated
every five seconds. The slow update mode persists until power
down. See the Phase 5: Normal Operation section.
The range of the offset corrected output is reduced compared to
when the auto-zero is disabled. This is the function of the
limiter block in Figure 32. This range reduction is shown in
Table 16 and Table 17.
Rev. B | Page 41 of 60
ADXL180
Data Sheet
Offset Drift Monitoring
appropriate error code is sent in the next data frame transmitted
to the control module (see the Offset Error/Offset Drift
Monitoring section). This message is sent continuously until
power to the ADXL180 is removed. The error status clears on
the next power-on-reset.
Cumulative offset drift is monitored during the normal
operation of the ADXL180. Offset drift monitoring occurs at
the same rate as auto-zero but runs independent of whether
auto-zero is enabled or disabled. An offset error is flagged if the
offset correction exceeds the maximum specified value. The
AUTO-ZERO DISABLE
M
U
X
TO SERIAL
PORT
LIMITER
g-
BESSEL
LP FILTER
10-BIT
ADC
SENSOR
DIGITAL
LP
FILTER
OFFSET
OVERRANGE DETECT
SLEW RATE
LIMITER
TRANSMISSION PERIOD
FAST/SLOW
LIMITER ENABLE
Figure 32. Auto-Zero Signal Path
Rev. B | Page 42 of 60
Data Sheet
ADXL180
ERROR DETECTION
PARITY ERROR DUE TO COMMUNICATIONS
PROTOCOL CONFIGURATION BIT ERROR
OVERVIEW
The ADXL180 monitors its internal operation and reports
errors. The error reporting codes differ depending on whether
the state vector has been enabled. Table 39 describes the errors
and the specific codes transmitted in various configurations.
The state vector allows the ADXL180 to report specific errors if
enabled. If the state vector is not enabled, a single error code is
sent regardless of the type of error. The error code is transmitted
every 228 μs in asynchronous mode until power down. The
error code is transmitted in response to every synchronization
pulse in synchronous mode until power down.
As shown in Table 39, an error code is generated if the parity of
the ADXL180 device OTP memory is incorrect. However, if this
error is due to a parity error in one of the ERC, SVD, DAT, or MAN
bits that govern the format of the transmitted message, the error
code is transmitted in an alternate data format. Receive system
designs that recognize repeated message transmissions, wrong
data lengths, and incorrect Manchester encoding help to detect
more easily that an error code is being set.
Table 39. Status/Error Coding
State Vector Enabled
State Vector Disabled
8-Bit
Data Mode
10-Bit
Data Mode
8-Bit
Data Mode
10-Bit
Data Mode
Error
Error Reporting Active in Phases
Configuration Error
Offset Error
Self-Test Error
OTP Parity Error
Device OK
0x7F
127d
126d
125d
124d
123d
122d
0x1F9
505d
504d
503d
502d
487d
500d
0x7D
125d
125d
125d
125d
123d
125d
0x1F4
500d
500d
500d
500d
487d
500d
2
5
4, 51
4, 5
3
0x7E
0x7D
0x7C
0x7B
0x7A
0x1F8
0x1F7
0x1F6
0x1E7
0x1F4
0x7D
0x7D
0x7D
0x7B
0x7D
0x1F4
0x1F4
0x1F4
0x1E7
0x1F4
Device Not OK (NOK)
3, 4, 5
1 A self-test error reported during Phase 5 indicates a failure of the internal self-test circuit, not a sensor self-test error.
Rev. B | Page 43 of 60
ADXL180
Data Sheet
the ADXL180 continuously monitors long term offset drift. If
the long-term offset correction exceeds the maximum specified
value, then an offset error is reported. This error is reported
independent of whether or not the auto-zero functionality has
been enabled.
SELF-TEST ERROR
In the ADXL180, self-test is automatically run during Phase 3.
If the internal self-test mode is selected, then the device enters
into the self-test routine as detailed in Figure 29 and Figure 30.
The device reports a failure during Phase 3 if it does not detect
two successful self-test pulses. When external self-test is
enabled, the device enters into the self- test routine as detailed
in Figure 29 and Figure 30; however, it reports all six self-test
pulses to the control module. The control module is responsible
for designation of a device failure.
VOLTAGE REGULATOR MONITOR RESET
OPERATION
The control module can reset the ADXL180 by lowering the bus
supply voltage to cause a power-fail reset. Figure 33 shows that,
for both the undervoltage and overvoltage trip thresholds, there
is a nominal 120 mV hysteresis before the voltage regulator
returns to within specification. No data transmission occurs
while the ADXL180 is in the reset state. The bus current is held
at the idle level during reset.
OFFSET ERROR/OFFSET DRIFT MONITORING
During Phase 3, an offset calculation is performed by averaging
the offset value with self-test deasserted (see Figure 29 for more
details). If this value is outside of the datasheet specifications,
then an error is reported at the start of Phase 5. Additionally,
V
OV
V
V
HYST
HYST
V
DD
(NOMINAL)
V
PUR
POWER OK
RESET
TIME
Figure 33. Voltage Regulator Monitor Reset Functionality
Rev. B | Page 44 of 60
Data Sheet
ADXL180
TEST AND DIAGNOSTIC TOOLS
VSCI SIGNAL CHAIN INPUT TEST PIN
VSCO ANALOG SIGNAL CHAIN OUTPUT TEST PIN
The VSCI signal chain input test pin allows the excitation of the
signal chain from the input of the sensor interface circuitry
(sensor amplifier) through to the output of the current mode
serial port. The function of this pin becomes active after the pin
input voltage exceeds the level of about 0.8 V. Below this level,
the ADXL180 does not respond to the voltage applied to the
VSCI pin. Above the threshold limit of 0.8 V, the voltage signal at
the VSCI pin is applied to the sensor interface circuitry in parallel
with the sensor signal.
The VSCO analog signal chain output test pin provides access to
the sensor signal chain analog output voltage at the output of
the Bessel filter. This signal is filtered and ranged as defined by
the configuration register settings. It is before the digital auto-
zero function in the signal chain. Therefore, it is not auto-
zeroed. The configuration register SCOE bit must be set to 1 to
enable this output. The signal output resistance is typically
50 Ω. Connect this output to a high impedance input only.
Table 40. SCOE VSCO Signal Chain Output Enable
SCOE Definition
The applied signal is zero when the input signal is equal to the
common-mode potential of the sensor interface circuitry
(~VDD/2 V), see Figure 34. The VSCI input scaling for all ranges
is typically about 640 μV/g. The scaling of the VSCI input voltage
to the ADC code output is dependent on the range setting of
the part.
0
1
VSCO output disabled. (Default.)
VSCO output enabled. Analog output prior to ADC
conversion is present on VSCO pin. Connect VSCO to high
impedance input, or data or sensor data may be
adversely affected.
+600g
Table 41. Typical VSCO Sensitivity Per g-Range
g-Range
Sensitivity
32.8 mV/g
16.4 mV/g
10.8 mV/g
8.2 mV/g
6.56 mV/g
4.69 mV/g
3.28 mV/g
50 g
100 g
150 g
200 g
250 g
350 g
500 g
0g
–600g
~0.8
V
/2
~3.2
DD
TEST PIN VOLTAGE
V
SCI
Figure 34. VSCI Signal Chain Input Test Pin Transfer Function
Rev. B | Page 45 of 60
ADXL180
Data Sheet
CONFIGURATION SPECIFICATION
the ADXL180 via voltage modulation of the VBP pin with
OVERVIEW
respect to the VBN pin. This signal uses pulse duration modula-
tion to combine the clock and digital data. The clock and data
are encoded as shown in Figure 35.
The ADXL180 configuration mode allows access to the user-
programmable nonvolatile configuration registers used to
define the function of the device. The configuration mode is
entered by writing a 16-bit configuration mode enable key code
to the VBP pin during Phase 1 of the ADXL180 start-up sequence,
which begins immediately after power is applied to the ADXL180.
The 16-bit configuration mode enable key code is 0x5A5A with
no start or parity bits (see Figure 36). The configuration mode
key is sent LSB first. Note that the configuration mode key code
is 16 bits long and the configuration mode read/write command
data frames are 14 bits long. This helps avoid misinterpretation
of either by the ADXL180.
The ADXL180 acknowledges entering the configuration mode
by transmitting the contents of the CREG2 register. This register
contains the configuration/user data programming bit (CUPRG)
status. This allows the user’s configuration/test system to deter-
mine whether the ADXL180 configuration OTP fuse memory
has been programmed without further communication. If the
configuration mode is not entered within the Phase 1 initializa-
tion time period, the ADXL180 treats the pulses on the VBP pin
as synchronization pulses (in synchronous mode) or ignores
them in asynchronous mode.
All configuration mode data sent to the ADXL180, including
the configuration mode enable key code is communicated to
tIB
tIB
tIB
tIB
tIB
tPGO
tPG1
tPG1
tPG0
V
CT
V
BP
DATA
0
0
1
1
CLOCK
TIME
Figure 35. Configuration Mode Receive Pulse Width Data and Clock Encoding
CONFIGURATION MODE ENABLE KEY DATA FRAME (16 BITS)
TRANSMITTED
FIRST
CONFIGURATION MODE KEY
0
1
0
1
1
0
1
0
0
1
0
1
1
0
1
0
Figure 36. Configuration Mode Enable Key Code Data Frame
ttm1
ttm2
16-BIT CONFIG MODE KEY CODE
V
BP
18-BIT TRANSMIT DATA:
CREG2
I
BUS
TIME
Figure 37. Configuration Mode Entry Key Code Sequence
Rev. B | Page 46 of 60
Data Sheet
ADXL180
DATA FRAME (18 BITS)
DATA
TRANSMITTED
FIRST
START
BITS
STATE
ADDRESS
P
0
VECTOR
1
0
0
1
2
0
1
2
3
4
5
6
7
0
1
2
3
Figure 38. Configuration Mode Transmit Data Frame
This is an 18-bit protocol (including the two start bits). Although
similar to the ADIFX protocol, it is different in that parity, and
not CRC, is used as the error checking code. This distinguishes
configuration mode messages from normal operation messages.
Figure 38 shows the configuration mode data frame format.
CONFIGURATION MODE TRANSMIT
COMMUNICATIONS PROTOCOL
In configuration mode, the ADXL180 transmits the configura-
tion mode register data through the current mode Manchester
encoded serial port. The configuration mode protocol is fixed
regardless of the actual settings of the configuration registers
(RAM or OTP). The transmit communication protocol used by
the ADXL180 in configuration mode is
Table 42 shows the configuration mode transmit data bit mapping.
Excluding the two start bits, the word is 16 bits long. Data Bit
DB15 (transmitted last) is the parity bit. The configuration
mode transmit parity is even. The parity bit is set to either 1 or
0 to make the total number of 1s in the 16-bit word an even
number. Data Bits[DB14:DB11] are the four configuration
mode register address bits. The following eight data bits, DB10
through DB3, are the eight configuration mode register data
bits. The next three bits, DB2 through DB0, are the state vector
bits. In the configuration mode, the state vector is 101b. This
data frame format is different from the ADIFX format.
•
•
•
•
•
•
•
•
•
Manchester-1 data encoding
Two start bits (10b)
4-bit configuration mode register address field
8-bit configuration mode register data field
3-bit state vector field (101b)
One parity bit (even)
Synchronization pulse disabled
Auto-zero disabled
Data is transmitted LSB first
Rev. B | Page 47 of 60
ADXL180
Data Sheet
operation and a 1 indicates a read operation. The parity bit is set
for even parity. The parity bit should be set to 0 or 1 to make the
total number of 1s in the data frame even. The data is
transmitted LSB first as shown in Table 42.
CONFIGURATION MODE COMMAND (RECEIVE)
COMMUNICATIONS PROTOCOL
The 8-bit configuration register data is passed to the ADXL180
with a read/write command bit, a 4-bit configuration register
address, and a parity bit as shown in Figure 39. The read/write
bit is set to indicate the desired action. A 0 indicates a write
RECEIVE DATA FRAME (14 BITS)
TRANSMITTED
FIRST
DATA
ADDRESS
R/W
0
P
0
0
1
2
3
4
5
6
7
0
1
2
3
Figure 39. Configuration Mode Command (Receive) Data Frame
Table 42. Configuration Mode Transmit Data Bit Mapping
DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2
DB1
DB0
Parity Addr 3 Addr 2 Addr 1 Addr 0 Data
Data Data Data Data Data Data Data State
State
State
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Vector 2 Vector 1 Vector 0
(MSB)
(LSB)
Rev. B | Page 48 of 60
Data Sheet
ADXL180
written to RAM, read back from the RAM, and transmitted to
the user’s test/configuration system as a handshake. This provides
a data integrity check for data write commands. If there is an
attempt to write data to a RAM register after the CUPRG bit is
set, the data is ignored by the ADXL180 (that is, it has no affect
on the device). The data returned by the ADXL180 is the
contents of the addressed OTP fuse register. This is the same
result as if a data read command had been issued.
CONFIGURATION MODE COMMUNICATIONS
HANDSHAKING
Configuration mode communications uses a handshaking
protocol. Following the completion of a data write or data read
command being written to the ADXL180, a data frame is
transmitted from the ADXL180 through the current mode
serial port. This forms a handshake acknowledgment with the
test system (see Figure 40). The source of the data (RAM or
OTP) transmitted in the handshake data frame is dependent
on whether the OTP memory has been programmed.
When the test/configuration system sends a data read command,
the data contained in the data frame is ignored and the data that
is contained in the addressed configuration mode register is
sent to the test/configuration system in response. The data sent
is always read from the RAM registers. If the CUPRG bit has
not been set (that is, the OTP fuses are not programmed), the
RAM contains the last data written to it by the configuration/
test system. When the CUPRG bit is set (that is, the OTP fuses
are programmed) the fuse data is loaded into the RAM registers
(see Figure 42).
Upon receiving a configuration mode data frame, if a parity
error is detected, the ADXL180 returns a handshake data frame
with the state vector code set to the status/error state vector
code (110b). The 8-bit data field and the 4-bit address field are
both set to all 0s.
When the test system sends a data write command, the data that
was written to the addressed configuration mode register is then
DATA READ SEQUENCE
DATA WRITE SEQUENCE
ttm1
ttm2
ttm1
ttm2
DATA READ
HANDSHAKE
DATA WRITE
V
BP
HANDSHAKE
TRANSMI
T
TRANSMIT
DATA
DATA
I
BUS
TIME
Figure 40. Configuration Mode Write Data and Read Data Sequences
Rev. B | Page 49 of 60
ADXL180
Data Sheet
The ADXL180 can be configured to send this data as part of the
device data transmitted during Phase 2 of the power-up
initialization sequence.
CONFIGURATION AND USER DATA REGISTERS
The configuration and user data registers are the user register,
UREG, and the three configuration registers, CREG0, CREG1,
and CREG2 (see Table 44). The ADXL180 can be programmed
to provide a variety of signal chain characteristics and device
operating modes via Configuration Register CREG0, Configu-
ration Register CREG1, and Configuration Register CREG2.
The configuration register and user register data can be
programmed into nonvolatile OTP memory.
PROGRAMMING THE CONFIGURATION AND USER
DATA REGISTERS
When the desired configuration and user data has been written
to the UREG and CREG registers, writing a 1 to the configura-
tion/user data program command bit (CUPRG) causes the four
bytes of configuration/user data to be permanently written to
the configuration/user data OTP fuse memory. The OTP fuses
are programmed sequentially by the ADXL180 without further
user intervention. This takes about 12 ms (tCUP in Figure 41).
The ADXL180 ignores all test system read and write commands
while it is programming the fuses.
In general, the CREG registers hold data that alters the function
of the ADXL180. The data contained in the UREG has no affect
on the operation of the ADXL180. The UREG bits are typically
used to indicate information such as module housing type and
sensing axis. The ADXL180 can be programmed to transmit the
UREG bits as part of the device data during power-up Phase 2,
depending on the Phase 2 mode that is selected.
The ADXL180 acknowledges the completion of the program-
ming sequence of the configuration/user data OTP memory by
sending the contents of the CREG2 register as described in the
Configuration Mode Transmit Communications Protocol section.
The CREG2 register contains the configuration/user data pro-
gramming bit (CUPRG). This allows the test/configuration
system to verify that the configuration/user data programming
bit has been programmed without further communication. The
contents of all of the configuration and user registers should then
be read to confirm that they have been programmed to the desired
settings. Figure 41 illustrates a sample sequence of commands
to write and then program the configuration and user registers.
CONFIGURATION MODE EXIT
The configuration mode is exited by writing 0x80 to
Address 1010b. A communication handshake is transmitted
by the ADXL180 after the configuration mode exit address is
written. The ADXL180 reenters its start-up sequence at the
beginning of the initialization phase (Phase 1) immediately
upon exiting the configuration mode. This method does not
generate a device reset. Alternatively, the configuration mode
can be exited by lowering the bus supply voltage to cause a
power-on-reset to occur. This method generates a device reset.
Once programmed, the OTP fuse memory settings are loaded
into the RAM registers during the Phase 1 initialization of the
ADXL180 start-up sequence. Figure 42 shows the basic struc-
ture of the configuration and user RAM/OTP memory structure.
SERIAL NUMBER AND MANUFACTURER
IDENTIFICATION DATA REGISTERS
The serial number and manufacturer identification data
registers can be read in configuration mode. The manufacturer
identification register is fixed at the mask level. The serial
number is programmed during the final manufacturing stages.
CONFIGURATION
MODE KEY
SEQUENCE
DATA
WRITE
SEQ
DATA
WRITE
SEQ
DATA
WRITE
SEQ
DATA
WRITE
SEQ
INTERNAL CONFIGURATION
REGISTER OTP PROGRAMMING
SEQUENCE
DATA
WRITE
CM
CREG2
CREG1
UREG
CREG0
V
EXIT
BP
CREG2
HANDSHAKE
I
BUS
tCUP
V
DD
TIME
Figure 41. Example Configuration Register OTP Programming Sequence
Rev. B | Page 50 of 60
Data Sheet
ADXL180
FROM RECEIVE
SERIAL PORT
A
TO TRANSMIT
SERIAL PORT AND
CONFIGURATION
CONTROL LOGIC
RAM
MUX
OTP
PROGRAM
OTP
DATA
OTP
FUSE
B
CUPRG
SEL
Figure 42. Configuration Mode RAM and OTP Register Structure
The CUPRG bit is automatically programmed to the locked
state (1) at the end of the configuration/user data OTP fuse
programming sequence. This prevents any further writes to the
UREG and CREG RAM registers as well as disables the confi-
guration/user data OTP fuse programming circuitry. The read
value of this bit indicates whether the configuration/user data
OTP memory has been programmed (that is, locked). A 1
indicates that the OTP memory block has been programmed
and further test system writes to either the RAM or OTP
configuration/user data registers are ignored.
handshake back to the command module. Do not attempt to
write to the configuration registers or attempt another OTP
programming step until this handshake has been received.
CONFIGURATION/USER REGISTER OTP PARITY
The configuration/user data OTP CU parity bit (CUPAR) must
be programmed to provide even parity for the configuration/
user data OTP memory. The CUPAR bit should be set to either
a 1 or a 0 to make the total number of 1s in the configuration/
user data OTP memory (including the value of the OTP CU
parity bit) an even number. The configuration/user data OTP
memory is defined as CREG0, CREG1, CREG2, and UREG.
The parity calculation must include the state of all register bits
including all of the UD and NU bits. The CUPRG bit must also
be included. During normal operation, once the configuration/
user data programming bit is set, the ADXL180 monitors the
parity of the configuration/user data OTP memory and com-
pares it against the programmed value of the CU parity bit in
CREG2. An OTP parity error is flagged if the monitored parity
and the programmed parity differ. See the Error Detection
section.
OTP PROGRAMMING CONDITIONS AND
CONSIDERATIONS
Note that all configuration/user OTP registers are programmed
when the CUPRG bit is set regardless of whether the registers
have been written to. The OTP registers can be programmed
one time only.
During normal operation and in configuration mode, the
internal voltage regulator is operating at 4.2 V nominal. This
internal voltage changes to a nominal value of 6.5 V during the
time that the ADXL180 is programming the configuration and
user OTP fuses (tCUP). The VBP supply voltage must be held at or
above the minimum fuse programming value specified in the
specification table for proper fuse programming. The VBP supply
current is increased during fuse programming as shown in
Figure 41. The configuration/test system must supply at least
the value IFP as specified. The configuration and user registers
are production tested for user programming at 25°C.
CONFIGURATION MODE ERROR REPORTING
The receive communication parity error and the OTP
programming voltage error are the two errors reported by
the ADXL180 when in configuration mode. The OTP parity,
configuration and other normal mode (run-time) errors are
suppressed in configuration mode. The state vector code is set
to a state vector of 5 (101b). The 8-bit error data code is shown
in Table 43. The 4-bit address field is set to 8 (1000b).
If the minimum programming voltage is not achieved, the
ADXL180 does not respond to subsequent communications
requests because it waits for the required programming voltage.
The device does not attempt to program unless the required
voltage level is achieved. The user’s test system should include
a timeout check if the device does not respond due to this sit-
uation. When properly programmed, the ADXL180 issues a
Table 43. Configuration Mode Error Codes
Error Data Code
Error Description
0000 0000b
Configuration mode receive parity error
Rev. B | Page 51 of 60
ADXL180
Data Sheet
CONFIGURATION REGISTER REFERENCE
The following tables define the codes for each programmable field in the three configuration registers (CREG0, CREG1, and CREG2).
The default setting (unprogrammed state) of all bits in all configuration registers is zero. As a result, the default configuration of the
ADXL180 is compatible with the ADIFX operation mode and communication protocol as implemented in the ADXS101 satellite
transmitter.
Table 44. Configuration and User Data Bit Map1, 2
Configuration
Mode Register
Address
Configuration
Mode Register
Name
MSB
D7
LSB
D6
D5
D4
D3
D2
D1
D0
0000b
0001b
0010b
0011b
0100b…1001b
1010b
1011b
1100b
1101b
UREG
CREG0
CREG1
CREG2
NU
CMEXIT
SN0
SN1
UD7
UD8
STI
CUPRG
X
UD6
BDE
AZE
CUPAR
X
0
SNB6
SNB14
SNB22
SNB30
SNPAR
UD5
MD1
SYEN
SCOE
X
UD4
MD0
ADME
FC1
X
0
SNB4
SNB12
SNB20
SNB28
REV1
UD3
FDLY
ERC
FC0
X
UD2
DLY2
SVD
RG2
X
UD1
DLY1
DAT
RG1
X
UD0
DLY0
MAN
RG0
X
0
SNB0
SNB8
SNB16
SNB24
MFGID0
1
0
0
0
0
SNB7
SNB15
SNB23
SNB31
SNPRG
SNB5
SNB13
SNB21
SNB29
REV2
SNB3
SNB11
SNB19
SNB27
REV0
SNB2
SNB10
SNB18
SNB26
SNB1
SNB9
SNB17
SNB25
SN2
SN3
MFGID
1110b
1111b
MFGID2 MFGID1
1 X is don’t care.
2 NU is not used.
Rev. B | Page 52 of 60
Data Sheet
ADXL180
UD[7:0] USER DATA BITS
FDLY
The user register is for arbitrary user data. It does not have any
influence on sensor operation. This data is transmitted during
Phase 2 of the state machine. For more information on trans-
mission format and timing, in particular depending on the
setting of MD bits, see the ADXL180 State Machine section.
Table 49. Fixed Delay Mode
FDLY Definition
0
1
Fixed delay mode disabled (default).
Fixed delay mode enabled. Device transmits data in the
time slot delayed by tDLY as defined by DLY[2:0].
Table 45. User Data Bit Definitions
Bit
ADME
Names Definition
Table 50. Autodelay Mode Enable (ADME ) Options
UD0
UD1
UD2
UD3
UD4
UD5
UD6
UD7
User Data Bit 0. No function, data only.
User Data Bit 1. No function, data only.
User Data Bit 2. No function, data only.
User Data Bit 3. No function, data only.
User Data Bit 4. No function, data only.
User Data Bit 5. No function, data only.
User Data Bit 6. No function, data only.
User Data Bit 7. No function, data only.
ADME Definition
0
Autodelay mode disabled. The part does not check for
a second device on the line and does not pull any extra
current during startup. (Default.)
1
Autodelay mode detection enabled. IDET pull-down for
6 ms at power-up.
STI
Table 51. Self Test Internal (STI) Options
UD8 CONFIGURATION BIT
STI
Definition
0
External self-test. User must monitor self-test data to
verify proper operation. Device does not monitor its own
response to the self-test stimulus. (Default.)
Internal self-test. The device monitors its own self-test
data to determine proper operation.
Table 46. UD8 Configuration Bit
UD8
Definition
0
1
Reserved, don’t care (default)
Reserved, don’t care
1
The value of the RS bit may be transmitted during Phase 2, inde-
pendent of UD[7:0], depending on the selection of the MD bits.
Table 52. Phase 3 Data Transmitted When STI = 1
MD1
MD0
Data
0
0
1
1
0
1
0
1
Device OK
Range
Delimiter
Device OK
BDE
Table 47. Bus Discharge Enable
BDE Definition
0
1
Bus discharge disabled (default).
Bus discharge enabled. Only active when SYEN = 1.
FC[1:0]
The bus discharge enable (BDE) bit enables a discharge of the
bus voltage after a synchronization pulse is detected. If the BDE
bit is set, the ADXL180 changes the bus current (IBUS) level from
Table 53. FC Low-Pass Filter Bandwidth Frequency Select Codes
FC1
FC0
−3 dB LP Frequency
0
0
400 Hz
I
IDLE to ISIG when a valid synchronization pulse has been detected.
0
1
1
0
200 Hz
100 Hz
See the Synchronous Communication section for more details
and timing information.
1
1
800 Hz
SCOE
RG[2:0]
Table 48. SCOE VSCO Signal Chain Output Enable
SCOE Definition
Table 54. RG[2:0] Sensor Range Select Codes
RG2
RG1
RG0
Range
0
1
VSCO output disabled. (Default.)
0
0
0
50 g
VSCO output enabled. Analog output prior to ADC
conversion is present on VSCO pin. Connect VSCO to high
impedance input or data or sensor data may be
adversely affected.
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
100 g
250 g
150 g
200 g
350 g
500 g
Not used
Rev. B | Page 53 of 60
ADXL180
Data Sheet
MD[1:0]
Table 56. Phase 2 (Device Data) Transmission Mode Select
Codes
Table 55. Phase 2 (Device Data) Transmission Mode Select
Codes
MD1
MD0
Data
MD1 MD0 Name
Definition
0
0
1
1
0
1
0
1
Device OK
Range
Delimiter
Device OK
0
0
0
1
Mode 0 ADIFX mode device data
Mode 1 Range data only (range selection
limited)
Mode 2 8-bit coded device data
Mode 3 10-bit coded device data
1
1
0
1
Table 57. MD Settings and Device Data Ranges with SVD and AZE Settings (Replication of Table 23)
Mode (Device Data)
0: ADIFX3
(All Configuration Data, Serial Number And Manufacturer ID)
MD1
MD0
SVD1
AZE2
0
Data Range
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Full
0
0
1
Reduced
Configuration error
Configuration error
Full
0
0
0
0
0
1
1: Range Data Only3
(Limited Range Selection)
0
1
0
0
1
1
Reduced
Reduced
Reduced
Full
0
1
0
0
1
1
2: 8-Bit Coded Device Data3
(UD[7:0], Serial Number And Range)
1
0
0
1
0
1
Reduced
Reduced
Reduced
Full
1
0
0
1
0
1
3: 10-Bit Coded Device Data4
(UD[7:0], Serial Number And Range)
1
1
0
1
1
1
Reduced
Reduced
Reduced
1
1
0
1
1
1
1 SVD is the state vector disable configuration bit.
2 AZE is the auto-zero enable configuration bit.
3 If Phase 2 Mode 0, Mode 1, or Mode 2 is selected, the device data is 8-bit data. If the 10-bit data mode is selected in combination with Phase 2 Mode 0, Mode 1, or
Mode 2, the 8-bit device data is left justified in the 10-bit data field. The two LSBs are held at zero (see Table 24).
4 The 10-bit device data mode (Phase 2 Mode 3) is incompatible with the 8-bit data mode (the DAT bit is set to 1). The device transmits a configuration error code if
Phase 2 Mode 3 is selected and the DAT bit is set to 1. No sensor data is transmitted.
Rev. B | Page 54 of 60
Data Sheet
ADXL180
SYEN
DAT
Table 58. Sync Enable (SYEN) Options
Table 61. DAT Data Bit Options
DAT Definition
SYEN
Definition
0
Synchronization pulse disabled. Device transmits data
according to state machine based on internal clock
every 228 μs when powered (default).
0
10-bit data sensor data transmitted. 8-bit Phase 2
configuration data left-justified in 10-bit data frame
(default).
1
Synchronization pulse enabled. The device requires a
synchronization pulse to sample and transmit data
according to state machine.
1
8-bit sensor data transmitted.
SVD
AZE
Table 62. SVD Data Bit Options
SVD
Definition
Table 59. AZE Auto Zero Enable
0
1
State vector enabled (default).
State vector disabled, reduced data range used.
AZE
Definition
0
Auto-zero function is disabled. Phase 4 has no
messages. Device immediately moves to normal data
(Phase 5) after self-test (Phase 3). (Default.)
CUPAR AND CUPRG
1
Auto-zero function enabled. See Auto-Zero Operation
section for details.
Table 63. Device Configuration Bit Definitions
Name
Setting Definition
CUPAR
0
1
0
Data dependent setting
Data dependent setting
ERC
Table 60. Error Check (ERC) Bit Options
ERC Definition
CUPRG
Configuration OTP memory not
programmed
1
Configuration OTP memory
programmed
0
3-bit CRC is included in message. Calculate CRC using the
polynomial x3 + x1 + x0. (Default.)
1
One parity bit is included in the message. CRC is not used.
It is a bit that is set such that even parity is achieved in
the transmitted message.
Rev. B | Page 55 of 60
ADXL180
Data Sheet
AXIS OF SENSITIVITY
X
= 0g
OUT
ADXL180
XXXX
XXXX
X
= –1g
X
= +1g
OUT
OUT
X
X
X X X
X X X
1 8 L 0 A D X
X
= 0g
OUT
X
= 0g
OUT
EARTH’S SURFACE
Figure 43. Output Response vs. Orientation
Rev. B | Page 56 of 60
Data Sheet
BRANDING
ADXL180
XL
180Z
Y
Y
W
W
#
CL P
CL CL CL CL
Figure 44. ADXL180 Laser Brand
Table 64. ADXL180 Branding Key
Line
Text
Description
1
2
3
3
4
4
XL
180Z
YY
WW
CL
P
Accelerometer
ADXL180Z
Year code
Week code
Lot code
Country of origin (Philippines)
Rev. B | Page 57 of 60
ADXL180
Data Sheet
OUTLINE DIMENSIONS
0.50
BSC
0.25
BSC
PIN 1
INDIC
PIN 1
INDICATOR
0.15 MAX
ATOR
1.83
1.73
1.63
0.20
MIN
EXPOSED
PADS
5.10
5.00 SQ
4.90
0.50
0.40
0.30
(BOTTOM VIEW)
1.62
1.52
1.42
TOP VIEW
3.31
3.21
3.11
1.50
1.45
1.40
3.70
3.60
3.50
0.05 MAX
0.02 NOM
0.30
0.25
0.18
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SEATING
PLANE
1.35
1.25
1.15
SECTION OF THIS DATA SHEET.
Figure 45. 16-Lead Lead Frame Chip Scale Package [LFCSP]
5 mm × 5 mm Body and 1.45 mm Package Height
(CP-16-8)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
ADXL180WCPZA-RL
Temperature Range
Package Description
Package Option
CP-16-8
−40°C to +125°C
16-Lead LFCSP
1 Z = RoHS Compliant Part.
Rev. B | Page 58 of 60
Data Sheet
NOTES
ADXL180
Rev. B | Page 59 of 60
ADXL180
NOTES
Data Sheet
©2008–2018 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07544-0-1/18(B)
Rev. B | Page 60 of 60
相关型号：
ADXL195WBRDZA-RL
Single-axis, High Performance Accelerometer with Dual Spectrum Signal Processing
ADI
©2020 ICPDF网 联系我们和版权申明