ADXL373BCCZ-RL [ADI]
Micropower, 3-Axis, ±400 g, Digital Output, MEMS Accelerometer;
| 型号： | ADXL373BCCZ-RL |
| 厂家： | 
ADI |
| 描述： | Micropower, 3-Axis, ±400 g, Digital Output, MEMS Accelerometer |
| 文件： | 总52页 (文件大小：1118K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Micropower, 3-Axis, 400 g, Digital Output,
MEMS Accelerometer
Data Sheet
ADXL373
FEATURES
GENERAL DESCRIPTION
400 g measurement range
160 Hz to 2560 Hz user selectable bandwidth with 4-pole
antialiasing filter
Selectable oversampling ratio
Adjustable high-pass filter
Ultra Low power
Power can be derived from a coin cell battery
19 µA at 2560 Hz ODR, 2.5 V supply
Low power wake-up mode for low g activity detection
1.4 µA instant on mode with adjustable threshold
0.1 µA standby mode
Built-in features for system level power savings
Autonomous interrupt processing without processor
intervention
Ultra low power event monitoring: detects impacts and
wakes up fast enough to capture the transient events
Adjustable low g threshold activity and inactivity detection
Wide operating voltage range: 1.6 V to 3.5 V
Acceleration sample synchronization via external trigger
SPI digital interface and I2C interface format support
12-bit output at 200 mg/LSB scale factor
Wide temperature range: −40°C to +105°C
Small, thin 3.00 mm × 3.25 mm × 1.06 mm package
The ADXL373 is an ultra low power, 3-axis, 400 g
microelectromechanical systems (MEMS) accelerometer that
consumes 19 µA at a 2560 Hz output data rate (ODR). The
ADXL373 does not power cycle its front end to achieve its low
power operation and therefore does not run the risk of aliasing
the output of the sensor.
In addition to its ultra low power consumption, the ADXL373
enables impact detection while providing system level power
reduction.
Two additional lower power modes with interrupt driven,
wake-up features are available for monitoring motion during
periods of inactivity. In wake-up mode, acceleration data can be
averaged to obtain a low enough output noise to trigger on low
g thresholds. In instant on mode, the ADXL373 consumes
1.4 μA while continuously monitoring the environment for
impacts. When an impact event that exceeds the internally set
threshold is detected, the device switches to normal operating
mode fast enough to record the event.
High g applications tend to experience acceleration content over
a wide range of frequencies. The ADXL373 includes a four-pole,
low-pass antialiasing filter to attenuate out-of-band signals that are
common in high g applications. The ADXL373 also incorporates a
high-pass filter to eliminate initial and slow changing errors
such as ambient temperature drift.
APPLICATIONS
Impact and shock detection
Asset health assessment
Portable Internet of Things (IoT) edge nodes
Concussion and head trauma detection
The ADXL373 provides 12-bit output data at 200 mg/LSB scale
factor. The user can access configuration and data registers via
the serial peripheral interface (SPI) or I2C protocol. The ADXL373
operates over a wide supply voltage range and is available in a
3.00 mm × 3.25 mm × 1.06 mm package.
In this data sheet, multifunction pin names may be referenced
by their relevant function only.
FUNCTIONAL BLOCK DIAGRAM
V
V
S
DD I/O
4-POLE
ADXL373
AXIS ANITALIASING
DEMODS
FILTERS
INT1
INT2
MOSI
MISO
DIGITAL,
FIFO,
AND
12-BIT
ADC
3-AXIS
SENSOR
SPI
CS
SCLK
GND
Figure 1.
Rev. A
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ADXL373
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Serial Interface............................................................................ 27
Multibyte Transfers .................................................................... 27
Invalid Addresses and Address Folding .................................. 27
Register Map ................................................................................... 28
Register Details ............................................................................... 30
Analog Devices ID Register...................................................... 30
Analog Devices MEMS ID Register......................................... 30
Device ID Register ..................................................................... 30
Product Revision ID Register ................................................... 30
Status Register............................................................................. 31
Activity Status Register.............................................................. 31
X-Axis Data Register, MSB ....................................................... 32
X-Axis Data Register, LSB......................................................... 32
Y-Axis Data Register, MSB ....................................................... 32
Y-Axis Data Register, LSB......................................................... 32
Z-Axis Data Register, MSB ....................................................... 33
Z-Axis Data Register, LSB......................................................... 33
Offset Trim Registers................................................................. 33
X-Axis Activity Threshold Register, MSB............................... 34
X-Axis of Activity Threshold Register, LSB............................ 35
Y-Axis Activity Threshold Register, MSB............................... 35
Y-Axis of Activity Threshold Register, LSB............................ 36
Z-Axis Activity Threshold Register, MSB............................... 36
Z-Axis of Activity Threshold Register, LSB............................ 36
Activity Time Register ............................................................... 37
X-Axis Inactivity Threshold Register, MSB............................ 37
X-Axis of Inactivity Threshold Register, LSB......................... 38
Y-Axis Inactivity Threshold Register, MSB............................ 38
Y-Axis of Inactivity Threshold Register, LSB......................... 39
Z-Axis Inactivity Threshold Register, MSB ............................ 39
Z-Axis of Inactivity Threshold Register, LSB ......................... 39
Inactivity Time Registers........................................................... 40
Inactivity Timer Register, MSB ................................................ 40
Inactivity Timer Register, LSB.................................................. 40
X-Axis Motion Warning Threshold Register, MSB............... 41
X-Axis of Motion Warning Notification Register, LSB......... 41
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 3
Specifications..................................................................................... 4
Interrupt Pin Digital Output Specifications ............................. 5
SPI Specifications ......................................................................... 6
I2C Specifications.......................................................................... 8
Absolute Maximum Ratings............................................................ 9
Thermal Resistance ...................................................................... 9
Recommended Soldering Profile ............................................... 9
Electrostatic Discharge (ESD) Ratings ...................................... 9
ESD Caution.................................................................................. 9
Pin Configuration and Function Descriptions........................... 10
Typical Performance Characteristics ........................................... 11
Theory of Operation ...................................................................... 16
Mechanical Device Operation .................................................. 16
Operating Modes........................................................................ 16
Bandwidth ................................................................................... 17
Power and Noise Trade-Off ...................................................... 17
Power Savings ............................................................................. 18
Autonomous Event Detection....................................................... 19
Activity and Inactivity................................................................ 19
Motion Warning ......................................................................... 22
Impact Detection Features ............................................................ 23
Wide Bandwidth......................................................................... 23
Instant On Impact Detection.................................................... 23
Interrupts ......................................................................................... 24
Interrupt Pins.............................................................................. 24
Types of Interrupts ..................................................................... 24
Additional Features ........................................................................ 25
Using an External Clock............................................................ 25
Synchronized Data Sampling.................................................... 25
Self Test ........................................................................................ 25
User Register Protection............................................................ 26
User Offset Trims ....................................................................... 26
Serial Communications ................................................................. 27
Y-Axis Motion Warning Notification Threshold Register,
MSB.............................................................................................. 42
Rev. A | Page 2 of 52
Data Sheet
ADXL373
Y-Axis of Motion Warning Notification Register, LSB..........42
RESET (Clears) Register, Device in Standby Mode ...............48
Applications Information...............................................................49
Applications Examples ...............................................................49
Operation at Voltages Other than 2.5 V ..................................50
Operation at Temperatures Other than Ambient...................50
Mechanical Considerations for Mounting ..............................50
Axes of Acceleration Sensitivity................................................51
Outline Dimensions........................................................................52
Ordering Guide ...........................................................................52
Z-Axis Motion Warning Notification Threshold Register,
MSB...............................................................................................42
Z-Axis Motion Warning Notification Register, LSB...............43
High-Pass Filter Settings Register.............................................43
Interrupt Pin Function Map Registers .....................................44
External Timing Control Register ............................................45
Measurement Control Register .................................................46
Power Control Register ..............................................................47
Self Test Register..........................................................................48
REVISION HISTORY
4/2021—Revision A: Initial Version
Rev. A | Page 3 of 52
ADXL373
Data Sheet
SPECIFICATIONS
TA = 25°C, VS = 2.5 V, VDD I/O = 2.5 V, 2560 Hz ODR, 1280 Hz bandwidth, acceleration = 0 g, and default register settings, unless otherwise
noted.
Table 1.
Parameter
Test Conditions/Comments
Min Typ
Max
Unit
SENSOR INPUT
Each axis
Measurement Range
Nonlinearity
400
0.5
23
2.5
g
%
kHz
%
Percentage of full scale
Sensor Resonant Frequency
Cross Axis Sensitivity1
OUTPUT RESOLUTION
All Operating Modes
SCALE FACTOR
Each axis
Each axis
12
Bits
Scale Factor Calibration Error
10
%
Scale Factor at Output from X-Axis (XOUT), Output
from Y-Axis (YOUT), and Output from Z-Axis (ZOUT
Expressed in mg/LSB
Expressed in LSB/g
200
mg/LSB
)
5
0.1
LSB/g
%/°C
Scale Factor Change due to Temperature2
0 g OFFSET
0 g Output
Each axis
XOUT, YOUT, ZOUT
At VS = 2.1 V
1.6 V ≤ VS ≤ 3.5 V
−6
−14
1
1
+6
+14
g
g
0 g Offset vs. Temperature2
Normal Operation
NOISE PERFORMANCE
RMS Noise
XOUT, YOUT, ZOUT
Each axis
60
mg/°C
Normal Operation
Low Noise Mode
BANDWIDTH
3.5
3
LSB
LSB
ODR
User selectable
User selectable, available corner frequencies
scales with ODR setting
320
0.20
5120
24.4
Hz
Hz
High Pass Filter, −3 dB Corner
Low Pass (Antialiasing) Filter, −3 dB Corner
Four-pole low-pass filter, user selectable,
bandwidth and ODR are set independent of
each other
160
ODR/2 Hz
POWER SUPPLY
Operating Voltage Range (VS)
Input and Output Voltage Range (VDD I/O
1.6
1.6
2.1
2.1
3.5
VS
V
V
)
Supply Current
Measurement Mode
Normal Operation
Low Noise Mode
2560 Hz ODR
19
29
1.4
µA
µA
µA
Instant On Mode
Wake-Up Mode
Varies with wake-up rate
At slowest wake-up rate
0.7
<0.1
µA
µA
Standby
Rev. A | Page 4 of 52
Data Sheet
ADXL373
Parameter
Power Supply Rejection Ratio (PSRR)
Test Conditions/Comments
Min Typ
Max
Unit
Source capacitance (CS)3 = 1.1 µF, input and
output capacitance (CIO3) = 1.1 µF, input is
100 mV sine wave on VS
Input Frequency
100 Hz to 1 kHz
1 kHz to 250 kHz
−20
−17
dB
dB
Turn On Time
Power-Up to Standby
Measurement Mode Instruction First Sample
2560 Hz ODR
3
CS = 1.1 µF and CIO3 = 1.1 µF
5
ms
ms
Filter settle bit = 0
Filter settle bit = 1
<69
<1
1
Instant On Ultra Low Power (ULP) Monitoring to
Full Bandwidth Data
ms
°C
ENVIRONMENTAL TEMPERATURE
Operating Range
−40
+105
1 Cross axis sensitivity is defined as coupling between any two axes.
2 −40°C to +25°C or +25°C to +105°C.
3 CS and CIO are power coupling capacitors. See the Applications Information section for more information.
INTERRUPT PIN DIGITAL OUTPUT SPECIFICATIONS
Table 2.
Limit1
Max
Parameter
Test Conditions/Comments
Min
Unit
DIGITAL OUTPUT
Low Level Output Voltage (VOL)
High Level Output Voltage (VOH)
IOL
Low level output current (IOL) = 500 µA
High level output current (IOH) = −300 µA
VOL = VOL, max
0.2 × VDD I/O
V
V
µA
µA
pF
0.8 × VDD I/O
500
IOH
VOH = VOH, min
−300
8
PIN CAPACITANCE
RISE/FALL TIME
Rise Time (tR)2
Input frequency (fIN) = 1 MHz, input voltage (VIN) = 2.0 V
Load capacitance on the digital pin (CLOAD) = 150 pF
CLOAD = 150 pF
210
150
ns
ns
Fall Time (tF)3
1 Limits based on characterization results, not production tested.
2 Rise time is measured as the transition time from VOL, max to VOH, min of the interrupt pin.
3 Fall time is measured as the transition time from VOH, min to VOL, max of the interrupt pin.
Rev. A | Page 5 of 52
ADXL373
Data Sheet
SPI SPECIFICATIONS
TA = 25°C, VS = 2.5 V, and VDDI/O = 2.5 V, unless otherwise noted.
Table 3. SPI Logic Levels and Timing
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
INPUT DC LEVELS
Low Level Input Voltage (VIL)
0.3 × VDDI/O
V
High Level Input Voltage (VIH)
Low Level Input Current (IIL)
High Level Input Current (IIH)
0.7 × VDDI/O
−0.1
V
µA
µA
VIN = 0 V
VIN = VDDI/O
0.1
OUTPUT DC LEVELS
VOL
IOL = IOL, MIN
0.2 × VDDI/O
V
VOH
IOL
IOH
IOL = IOH, MAX
VOL = VOL, MAX
VOL = VOH, MIN
0.8 × VDDI/O
−10
V
mA
mA
4
INPUT AC
SCLK Frequency
0.1
40
40
20
20
40
20
20
20
10
MHz
ns
ns
SCLK High Time (tHIGH
SCLK Low Time (tLOW
)
)
Setup Time (tCSS
)
ns
CS
CS
CS
Hold Time (tCSH
)
ns
Disable Time (tCSD
)
ns
Rising SCLK Setup Time (tSCLKS
MOSI Setup Time (tSU)
MOSI Hold Time (tHD)
)
ns
ns
ns
OUTPUT AC
Propagation Delay (tP)
Enable MISO Time (tEN)
Disable MISO Time (tDIS
CLOAD = 30 pF
30
20
ns
ns
ns
30
)
SPI Timing Diagrams
tCSD
CS
t
SCLKS
t
tCSS
CSH
tLOW
tHIGH
SCLK
tSU
tHD
MOSI
tDIS
tEN
tP
MISO
Figure 2. SPI Timing Diagram
CS
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
SCLK
MOSI
A6 A5 A4 A3 A2 A1 A0 RW
MISO
D7 D6 D5 D4 D3 D2 D1 D0
Figure 3. SPI Timing Diagram, Single Byte Read
Rev. A | Page 6 of 52
Data Sheet
ADXL373
CS
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
SCLK
MOSI
A6 A5 A4 A3 A2 A1 A0 RW D7 D6 D5 D4 D3 D2 D1 D0
MISO
Figure 4. SPI Timing Diagram, Single Byte Write
CS
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
SCLK
MOSI
A6 A5 A4 A3 A2 A1 A0 RW
BYTE n
BYTE 1
MISO
D7 D6 D5 D4 D3 D2 D1 D0 D7
D0 D7 D6 D5 D4 D3 D2 D1 D0
Figure 5. SPI Timing Diagram, Multibyte Read
CS
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
SCLK
BYTE n
BYTE 1
MOSI
MISO
A6 A5 A4 A3 A2 A1 A0 RW D7 D6 D5 D4 D3 D2 D1 D0 D7
D0 D7 D6 D5 D4 D3 D2 D1 D0
Figure 6. SPI Timing Diagram, Multibyte Write
Rev. A | Page 7 of 52
ADXL373
Data Sheet
I2C SPECIFICATIONS
TA = 25°C, VS = 2.5 V, and VDDI/O = 1.8 V, unless otherwise noted.
Table 4. I2C Logic Level and Timing
I2C_HSM_EN = 0
Typ
I2C_HSM_EN = 1
Typ
Parameter
INPUT AC
Min
Max
Min
Max
Unit
SCLK Frequency
0
1
0
3.4
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCLK High Time (tHIGH
SCLK Low Time (tLOW
Start Setup Time (tSUSTA
Start Hold Time (tHDSTA
Data Setup Time (tSUDAT
)
260
500
260
260
50
0
260
500
120
320
160
160
10
)
)
)
)
)
Data Hold Time (tHDDAT
Stop Setup Time (tSUSTO
Bus Free Time (tBUF
SCL Input Rise Time (tRCL
SCL Input Fall Time (tFCL
SDA Input Rise Time (tRDA
SDA Input Fall Time (tFDA
OUTPUT AC
)
0
160
150
)
)
120
120
120
120
20
20
20
20
80
80
160
160
)
20 × (VDD/5.5)
20 × (VDD/5.5)
)
)
CLOAD
550
400
pF
I2C Timing Diagrams
tFDA
tRDA
tBUF
SDA
tSUSTA
tSUSTA tHDSTA
tSUDAT
tHDDAT
tRCL
tSUSTO
tFCL
tLOW
tHIGH
SCL
Figure 7. I2C Timing Diagram
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37
SCL
RPT.
START
START
SDA
DEVICE ADDRESS
REGISTER ADDRESS
DEVICE ADDRESS
DATA BYTE
STOP
A6 A5 A4 A3 A2 A1 A0 RW AK
0
A6 A5 A4 A3 A2 A1 A0 AK
A6 A5 A4 A3 A2 A1 A0
AK
AK
D7 D6 D5 D4 D3 D2 D1 D0
RW
INDICATES SDA IS CONTROLLED BY ADXL373
Figure 8. I2C Timing Diagram, Single Byte Read
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
SCL
START
SDA
DEVICE ADDRESS
A6 A5 A4 A3 A2 A1 A0
REGISTER ADDRESS
DATA BYTE
STOP
0
A6 A5 A4 A3 A2 A1 A0
RW AK
AK
AK
D7 D6 D5 D4 D3 D2 D1 D0
INDICATES SDA IS CONTROLLED BY ADXL373
Figure 9. I2C Timing Diagram, Single Byte Write
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 19
SCL
START
DEVICE ADDRESS
REGISTER ADDRESS
DATA BYTE 1
DATA BYTE n
A6 A5 A4 A3 A2 A1 A0
SDA
RW AK
0
A6 A5 A4 A3 A2 A1 A0 AK
AK D7
D0 AK D7 D6 D5 D4 D3 D2 D1 D0 AK
D7 D6 D5 D4 D3 D2 D1 D0
INDICATES SDA IS CONTROLLED BY ADXL373
Figure 10. I2C Timing Diagram, Multibyte Write
Rev. A | Page 8 of 52
Data Sheet
ADXL373
ABSOLUTE MAXIMUM RATINGS
Table 5.
Table 7. Recommended Soldering Profile
Condition
Parameter
Acceleration
Any Axis, Unpowered
Any Axis, Powered
VS
VDD I/O
All Other Pins
Output Short-Circuit Duration (Any Pin to
Ground)
Storage Temperature Range
Rating
Profile Feature
Sn63/Pb37
Pb-Free
Average Ramp Rate (Time
Maintained Above Liquidous
Temperature (TL) to Peak
Temperature (TP))
Preheat
Minimum Temperature (TSMIN
3°C/sec max
3°C/sec max
10,000 g for 0.1 ms
10,000 g for 0.1 ms
−0.3 V to +3.6 V
−0.3 V to +3.6 V
−0.3 V to VS
)
100°C
150°C
60 sec to
120 sec
150°C
200°C
60 sec to
180 sec
Indefinite
Maximum Temperature (TSMAX
Time (TSMIN to TSMAX) (tS)
)
−50°C to +150°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
TSMAX to TL
Ramp-Up Rate
Time Maintained Above TL
TL
3°C/sec max
183°C
60 sec to
150 sec
240 + 0/−5°C
10 sec to
30 sec
3°C/sec max
217°C
60 sec to
150 sec
260 + 0/−5°C
20 sec to
40 sec
Time (tL)
Peak Temperature (TP)
Time Within 5°C of Actual Peak
Temperature (tP)
THERMAL RESISTANCE
Ramp-Down Rate
Time 25°C to Peak Temperature
6°C/sec max
6 minutes
max
6°C/sec max
8 minutes
max
Thermal performance is directly linked to printed circuit
board (PCB) design and operating environment. Careful
attention to PCB thermal design is required.
ELECTROSTATIC DISCHARGE (ESD) RATINGS
θ
JA is the natural convection, junction to ambient thermal
resistance measured in a one cubic foot sealed enclosure.
JC is the junction to case thermal resistance.
The following ESD information is provided for handling of
ESD-sensitive devices in an ESD protected area only.
θ
Human body model (HBM) per ANSI/ESDA/JEDEC JS-001.
Table 6.
Package Type1
CC-16-4
θJA
150
θJC
85
Unit
°C/W
Device Weight
18 mg
ESD Ratings for ADXL373
Table 8. ADXL373, 16-Terminal LGA
1 Thermal impedance simulated values are based on a JEDEC 2S2P thermal
test board with four thermal vias. See JEDEC JESD-51.
ESD Model
Withstand Threshold (V)
Class
HBM
2000
1C
RECOMMENDED SOLDERING PROFILE
Figure 11 and Table 7 provide details about the recommended
ESD CAUTION
soldering profile.
CRITICAL ZONE
tP
T
TO T
L
P
T
P
L
RAMP-UP
T
tL
T
SMAX
T
SMIN
tS
RAMP-DOWN
PREHEAT
t25°C TO PEAK
TIME
Figure 11. Recommended Soldering Profile
Rev. A | Page 9 of 52
ADXL373
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
14
16
15
1
2
3
4
5
13
12
11
10
9
V
GND
DDI/O
NIC
GND
ADXL373
TOP VIEW
INT1
RESERVED
SCLK
(Not to Scale)
RESERVED
INT2
RESERVED
6
8
7
NOTES
1. NIC = NOT INTERNALLY CONNECTED. THE NIC PINS
NOT INTERNALLY CONNECTED.
Figure 12. Pin Configuration (Top View)
Table 9. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
VDD I/O
Supply Voltage for Digital Input and Output.
2, 15
3, 5, 10
4
6
7
8
NIC
RESERVED
SCLK
MOSI/SDA
MISO
Not Internally Connected. The NIC pins are not internally connected.
Reserved. The RESERVED pins can be left unconnected or connected to GND.
SPI Serial Communications Clock.
SPI Master Output, Slave Input (MOSI). I2C Serial Data (SDA).
SPI Master Input, Slave Output.
SPI Chip Select in SPI Mode ( ).I2C Serial Communications Clock (SCL).
CS
/SCL
CS
9
11
12, 13, 16
14
INT2
INT1
GND
VS
Interrupt 2 Output. The INT2 pin also serves as the input for synchronized sampling.
Interrupt 1 Output. The INT1 pin also serves as the input for external clocking.
Ground. The GND pins must be connected to ground.
Supply Voltage.
Rev. A | Page 10 of 52
Data Sheet
ADXL373
TYPICAL PERFORMANCE CHARACTERISTICS
35
40
35
30
25
20
15
10
5
30
25
20
15
10
5
0
0
–14 –12 –10 –8 –6 –4 –2
0
2
4
6
8
10 12 14 16
5.00
4.90
4.9
5.04
5.08
5.12
5.16
5.20
5.24
5.28
0g OFFSET (LSB)
SENSITIVITY (LSB/g)
Figure 13. X-Axis 0 g Offset at 25°C, VS = 2.1 V
Figure 16. X-Axis Sensitivity at 25°C, VS = 2.1 V
35
30
25
20
15
10
5
50
45
40
35
30
25
20
15
10
5
0
0
–16 –14 –12 –10 –8 –6 –4 –2
0
2
4
6
8
10 12 14
4.96
5.02
5.08
5.14
5.20
5.26
5.32
0g OFFSET (LSB)
SENSITIVITY (LSB/g)
Figure 14. Y-Axis 0 g Offset at 25°C, VS = 2.1 V
Figure 17. Y-Axis Sensitivity at 25°C, VS = 2.1 V
18
16
14
12
10
8
60
50
40
30
20
10
0
6
4
2
0
–20 –15 –10 –5
0
5
10 15 20 25 30 35 40 45 50 55
5.0
5.1
5.2
5.3
5.4
5.5
5.6
SENSITIVITY (LSB/g)
0g OFFSET (LSB)
Figure 15. Z-Axis 0 g Offset at 25°C, VS = 2.1 V
Figure 18. Z-Axis Sensitivity at 25°C, VS = 2.1 V
Rev. A | Page 11 of 52
ADXL373
Data Sheet
35
30
25
20
15
10
5
10
8
6
4
2
0
–2
–4
–6
–8
0
–100
–60
–20
20
60
100
140
180
–60
–40
–20
0
20
40
60
80
100
120
120
120
0g OFFSET TEMPERATURE COEFFICIENT (mg/°C)
TEMPERATURE (°C)
Figure 19. X-Axis 0 g Offset Temperature Coefficient
Figure 22. X-Axis 0 g Normalized Offset vs. Temperature
10
8
35
30
25
20
15
10
5
6
4
2
0
–2
–4
–6
0
–60
–40
–20
0
20
40
60
80
100
–100
–60
–20
20
60
100
140
180
TEMPERATURE (°C)
0g OFFSET TEMPERATURE COEFFICIENT (mg/°C)
Figure 20. Y-Axis 0 g Offset Temperature Coefficient
Figure 23. Y-Axis 0 g Normalized Offset vs. Temperature
30
25
20
15
10
5
10
8
6
4
2
0
–
–
–
–
2
4
6
8
0
–160
–120
–80
–40
0
40
80
120
–60
–40
–20
0
20
40
60
80
100
0g OFFSET TEMPERATURE COEFFICIENT (mg/°C)
TEMPERATURE (°C)
Figure 21. Z-Axis 0 g Offset Temperature Coefficient
Figure 24. Z-Axis 0 g Normalized Offset vs. Temperature
Rev. A | Page 12 of 52
Data Sheet
ADXL373
25
20
45
40
35
30
25
20
15
10
5
15
10
5
0
–5
–10
–15
–20
–25
–30
0
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
–0.05 –0.03 –0.01
0.01
0.03
0.05
0.07
0.09
SUPPLY VOLTAGE (V)
SENSITIVITY TEMPERATURE COEFFICIENT (%/°C)
Figure 25. X-Axis Offset Variation with Respect to Supply Voltage
Figure 28. X-Axis Sensitivity Temperature Coefficient
50
45
40
35
30
25
20
15
10
5
30
20
10
0
–10
–20
–30
0
–0.03 –0.01
0.01
0.03
0.05
0.07
0.09
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
–0.05
SENSITIVITY TEMPERATURE COEFFICIENT (%/°C)
SUPPLY VOLTAGE (V)
Figure 26. Y-Axis Offset Variation with Respect to Supply Voltage
Figure 29. Y-Axis Sensitivity Temperature Coefficient
50
40
25
20
15
10
5
30
20
10
0
–10
–20
–30
0
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
–0.20 –0.12 –0.04
0.04
0.12
0.20
0.28
0.36
SUPPLY VOLTAGE (V)
SENSITIVITY TEMPERATURE COEFFICIENT (%/°C)
Figure 30. Z-Axis Sensitivity Temperature Coefficient
Figure 27. Z-Axis Offset Variation with Respect to Supply Voltage
Rev. A | Page 13 of 52
ADXL373
Data Sheet
45
40
35
30
25
20
15
10
5
45
40
35
30
25
20
15
10
5
0
0
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
15
16
17
18
19
20
21
22
CURRENT CONSUMPTION (µA)
CURRENT CONSUMPTION (µA)
Figure 34. Current Consumption at 25°C, Wake-Up Mode, VS = 2.1 V
Figure 31. Current Consumption at 25°C, Normal Mode, 3200 Hz ODR,
VS = 2.1 V
20
18
16
14
12
10
8
30
25
20
15
10
5
6
4
2
0
0
–5
–3
–1
1
3
5
7
9
24
25
26
27
28
29
30
31
CLOCK FREQUENCY DEVIATION FROM IDEAL (%)
CURRENT CONSUMPTION (µA)
Figure 32. Current Consumption at 25°C, Low Noise Mode, 3200 Hz ODR,
VS = 2.1 V
Figure 35. Clock Frequency Deviation from Ideal at 25°C, ODR = 3200 Hz,
VS = 2.1 V
30
25
20
15
10
5
30
25
20
15
10
5
0
0
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
–14
–10
–6
–2
2
6
10
14
CURRENT CONSUMPTION (µA)
CLOCK FREQUENCY DEVIATION FROM IDEAL (%)
Figure 33. Current Consumption at 25°C, Instant On Mode, 3200 Hz ODR,
VS = 2.1 V
Figure 36. Clock Frequency Deviation from Ideal at 25°C, ODR = 6400 Hz,
VS = 2.1 V
Rev. A | Page 14 of 52
Data Sheet
ADXL373
12
10
8
20
18
16
14
12
10
8
1.6V
2.5V
3.5V
6
4
6
4
2
2
0
0
20
29
33
37
41
45
49
53
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90 100 105
TEMPERATURE (°C)
CURRENT CONSUMPTION (nA)
Figure 37. Current Consumption at 25°C, Standby Mode, VS = 2.1 V
Figure 40. Standby Current vs. Temperature, Instant On Mode
10
12
1.6V
1.6V
2.5V
3.5V
2.5V
9
3.5V
10
8
8
7
6
5
4
3
2
1
0
6
4
2
0
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90 100 105
TEMPERATURE (°C)
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90 100 105
TEMPERATURE (°C)
Figure 38. Standby Current vs. Temperature
Figure 41. Standby Current vs. Temperature, Wake-Up Mode
40
35
30
25
20
15
10
5
1.6V
2.5V
3.5V
0
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90 100 105
TEMPERATURE (°C)
Figure 39. Measurement Mode Current vs. Temperature, Normal Mode
Rev. A | Page 15 of 52
ADXL373
Data Sheet
THEORY OF OPERATION
The ADXL373 is a complete 3-axis acceleration measurement
system that operates at extremely low power levels. Acceleration is
reported digitally and the device communicates via the SPI and
I2C protocols. Built-in digital logic enables autonomous
operation and implements functions that enhance system level
power savings.
section). The current drawn in this mode is determined by both
of these parameters.
Table 10. Wake-Up Current in μA at Different Wake-Up
Timer and Filter Settings
FILTER_SETTLE Bit Settings
Wake-Up Timer (ms)
When Set to 1
When Set to 0
MECHANICAL DEVICE OPERATION
65
130
260
640
2560
5120
10240
30720
1.3
16.7
15
The moving component of the sensor is a polysilicon surface-
micromachined structure built on top of a silicon wafer.
Polysilicon springs suspend the structure over the surface of
the wafer and provide a resistance against acceleration forces.
0.98
0.84
0.76
0.71
0.71
0.7
12.4
8.4
3.5
2.2
1.5
1
Deflection of the structure is measured using differential
capacitors that consist of independent fixed plates and plates
attached to the moving mass. Acceleration deflects the structure
and unbalances the differential capacitor, resulting in a sensor
output whose amplitude is proportional to acceleration. Phase
sensitive demodulation determines the magnitude and polarity
of the acceleration.
0.7
If motion is detected, the accelerometer can respond
autonomously in several ways, depending on the device
configuration, including the following:
•
•
•
Switch into full bandwidth measurement mode.
Signal an interrupt to a microcontroller.
Wake up downstream circuitry.
OPERATING MODES
The ADXL373 has three operating modes. Measurement mode
is used for continuous, wide bandwidth sensing. Wake-up mode
is used for limited bandwidth low g activity detection. Instant on
mode is used for low power impact detection. Measurement can
be suspended completely by placing the device in standby mode.
While in wake-up mode, all registers have normal read and
write functionality, and real-time data can be read from the data
registers at the reduced wake-up rate. However, there are no
interrupts available in wake-up mode.
Measurement Mode
Instant On Mode
Measurement mode is the normal operating mode of the
ADXL373. In this mode, acceleration data is read continuously
and the accelerometer consumes 19 µA (typical) at an ODR of
2560 Hz using a 2.5 V supply. Actual current consumption is
dependent on the ODR chosen. All features described in this
data sheet are available when operating the ADXL373 in
measurement mode. After entering measurement mode,
the first output value does not appear until after the filter
settling time has passed. This time is selectable using the
FILTER_SETTLE bit in the POWER_CTL register. See the
Filter Settling Time section for more details.
Instant on mode enables extremely low power impact detection.
In this mode, the accelerometer constantly monitors the
environment while consuming a low current of 1.4 μA (typical).
When an event that exceeds an internal threshold is detected,
the device switches into measurement mode to record the event.
The target default threshold is 20 g to 30 g but can vary. A
register option allows the threshold to be increased to a target of
60 g to 80 g if the default threshold is too low.
To save power, no new digital acceleration data is made available
until the accelerometer switches into normal operation. However,
all registers have normal read/write functionality.
Wake-Up Mode
Standby Mode
Wake-up mode is ideal for simple detection of the presence or
absence of motion at an extremely low power consumption.
Wake-up mode is particularly useful for the implementation of
a low g motion activated on and off switch, allowing the rest of
the system to be powered down until sustained activity is detected.
Placing the ADXL373 in standby mode suspends measurement
and reduces current consumption to <0.1 µA. All interrupts are
cleared, and no new interrupts are generated. The ADXL373
powers up in standby mode with all sensor functions turned off.
In wake-up mode, the device is powered down for a duration of
time equal to the wake-up timer, set by the WAKEUP_RATE
bits in the TIMING register, and then turns on for a duration
equal to the filter settling time (see the Filter Settling Time
Rev. A | Page 16 of 52
Data Sheet
ADXL373
activity detection is turned on, no effect is visible on the device
output, but inadvertent activity or inactivity interrupts can be
triggered before the settling time has elapsed.
BANDWIDTH
Low-Pass Antialiasing Filter
High g events often include acceleration content over a wide
range of frequencies. The analog-to-digital converter (ADC) of
the ADXL373 samples the input acceleration at the user selected
ODR. In the absence of antialiasing filters, input signals whose
frequency is more than half of the ODR alias or that fold into
the measurement bandwidth can lead to inaccurate measurements.
To mitigate this inaccuracy, a four-pole low-pass filter is
provided at the input of the ADC. The filter bandwidth is user
selectable and the default bandwidth is 160 Hz. The maximum
bandwidth is constrained to at most half of the ODR to ensure
that the Nyquist criteria is not violated.
Selectable ODR
The ADXL373 can report acceleration data at 320 Hz, 640 Hz,
1280 Hz, 2560 Hz, or 5120 Hz. The ODR is user selectable and
the default is 320 Hz. If the user selects an antialiasing filter
bandwidth greater than half the ODR, the device defaults the
bandwidth to 50% of the ODR. Increasing or decreasing the
ODR increases or decreases the current consumption,
accordingly, as shown in Figure 42.
50
40
30
20
10
0
High-Pass Filter
The ADXL373 offers a one-pole high-pass filter with a user
selectable −3 dB frequency. Applications that do not require dc
acceleration measurements can use the high-pass filter to
minimize constant or slow varying offset errors, including
initial bias, bias drift due to temperature and bias drift due to
supply voltage.
The high-pass filter is a first-order infinite impulse response
(IIR) filter. Table 11 lists the available −3 dB frequencies, which
are user selectable and dependent on the output data rate. The
high-pass and low-pass filters can be used simultaneously to set
up a band-pass option.
256
1024
4096
OUTPUT DATA RATE (Hz)
Figure 42. Measurement Mode Current vs. ODR for Five ADXL373 Devices
Under Test (DUTs)
Table 11. High-Pass Filter, −3 dB Corner Frequencies
POWER AND NOISE TRADE-OFF
ODR (Hz)
The noise performance of the ADXL373 in normal operation
(typically 3.5 LSB rms at 2560 Hz ODR and 1280 Hz bandwidth)
is adequate for most applications depending on bandwidth and
the desired resolution. For cases where lower noise is necessary,
the ADXL373 provides a lower noise operating mode that trades
reduced noise for a somewhat higher current consumption. In
all cases, operating at a higher bandwidth setting increases the
rms noise. Operating with a lower bandwidth decreases the
noise from the numbers listed in Table 12.
Setting
00
01
10
11
5120
24.38
12.46
6.30
2560
12.19
6.23
3.15
1.59
1280
6.10
3.12
1.58
0.79
640
3.05
1.56
0.79
0.40
320
1.52
0.78
0.39
0.20
3.17
Filter Settling Time
The FILTER_SETTLE bit determines the time after the
measurement mode instruction, at which, the first output value
is recorded in the data registers. By default, the value of this bit is
0, and the turn-on time is approximately 463 ms, ensuring that
all the filters have time to settle before data is output. If this bit
is set to 1, the first output value is reported <1 ms after the
measurement mode instruction is given. The time taken for the
antialiasing filter to settle and correct data to begin appearing is
approximately 4/ODR. If using activity detection, the reference
level is set after this time.
Table 12 details the current consumption and noise densities
obtained for normal operation and the lower noise mode at a
typical 2.5 V supply.
Table 12. Noise and Current Consumption at VS = 2.5 V,
ODR = 2560 Hz, Bandwidth = 1280 Hz
RMS Noise
Typical (LSB)
Current Consumption
Typical (µA)
Mode
Normal Operation
Low Noise
3.5
3
19
29
It is not recommended to set the FILTER_SETTLE bit to 1 if the
high-pass filter or low-pass filter for activity detection are enabled.
These filters require a full 463 ms to begin outputting correct
data. If the high-pass filter is turned on, any data output may be
incorrect before 463 ms has elapsed. If the low-pass filter for
Rev. A | Page 17 of 52
ADXL373
Data Sheet
POWER SAVINGS
Operating the ADXL373 at a higher supply voltage also
decreases noise. Table 13 lists the current consumption and
noise densities obtained for normal operation and the lower
noise mode at the highest recommended supply, 3.5 V.
The digital interface of the ADXL373 is implemented with
system level power savings in mind. The following features
enhance power savings:
•
Burst reads and writes reduce the number of SPI
communication cycles required to configure the device and
retrieve data.
Concurrent operation of activity and inactivity detection
enables set it and forget it operation. Linked and loop
modes further reduce communications power by enabling
the clearing of interrupts without processor intervention.
Table 13. Noise and Current Consumption at VS = 3.5 V,
ODR = 2560 Hz, Bandwidth = 1280 Hz
RMS Noise
Typical (LSB)
Current Consumption
Typical (µA)
•
Mode
Normal Operation
Low Noise
3
2.5
32
44
Rev. A | Page 18 of 52
Data Sheet
ADXL373
AUTONOMOUS EVENT DETECTION
In many applications, it is advantageous for activity detection to
be based not on an absolute threshold but on a deviation from a
reference point or orientation. Activity detection with a
deviation is particularly useful because it removes the effect on
activity detection of the static 1 g imposed by gravity as well as
any static offset errors, which can be up to several gs. In absolute
activity detection, when the threshold is set to less than 1 g,
activity is immediately detected in this case.
ACTIVITY AND INACTIVITY
The ADXL373 features built-in logic that detects activity
(acceleration more than a user set threshold) and inactivity
(acceleration less than a user set threshold). Activity and inactivity
events can be used as triggers to manage the accelerometer
operating mode, trigger an interrupt to a host processor, and/or
autonomously drive a motion switch.
Detection of an activity or inactivity event is indicated in the
STATUS2 register and can be configured to generate an interrupt.
In addition, the activity status of the device, that is, whether it is
moving or stationary, is indicated by the AWAKE bit (STATUS
register), described in the Using the AWAKE Bit section.
In the referenced configuration, activity is detected when
acceleration samples are more than an internally defined
reference by a user defined amount for the user defined amount
of time, as described by
Abs(Acceleration − Reference) > Threshold
where Abs is the absolute value.
Activity and inactivity detection can be used when the
accelerometer is in either measurement mode or wake-up
mode. However, the activity and inactivity interrupts are not
available in wake-up mode because the device is inherently
looking for activity in this mode, and any changes to the activity
or inactivity detection features must be made while the device is
in standby mode.
Consequently, activity is detected only when the acceleration
has deviated sufficiently from the initial orientation. The default
setting for the accelerometer is in absolute mode. After it is
placed in referenced mode through the appropriate register
setting, the reference for activity detection is calculated as soon
as the full bandwidth measurement mode is turned on. To reset
the reference, it is necessary to put the device back into absolute
mode and then back into referenced mode. The new reference
is set as soon as the device enters full bandwidth measurement
mode again. If using both activity and inactivity detection in
referenced mode, both must be set back to absolute mode
before the reference can be reset.
Low-Pass Activity Detect Filter
The ADXL373 combines high g impact detection and low g
movement detection in one device. For low g detection, an
internal low-pass filter with a −3 dB corner of approximately
8 Hz averages data to reduce the rms noise, allowing accurate
detection of activity or inactivity thresholds as low as 1 g. For
high g impact detection, the low-pass activity detect filter can
be turned off through a register setting. When using both the
low-pass activity detect filter and the high-pass filter, the user
must select a high-pass filter corner that does not exceed 8 Hz.
Otherwise, activity detection data is severely attenuated.
If the FILTER_SETTLE bit is set to 1, set reference mode after
entering measurement mode or else the reference may not be
correct. If both the high-pass filter and low-pass filter for
activity detection are disabled, do not enable reference mode
earlier than 4/ODR after entering measurement mode. If either
filter is enabled, do not enable reference mode earlier than
463 ms after entering measurement mode.
Activity Detection
An activity event is detected when acceleration in at least one
enabled axis remains above a specified threshold for a specified
time. Enabled axes, thresholds, and time are user selected. Each
axis has its own activity threshold, but the activity timer is shared
among all three axes. When multiple axes are selected, an over
threshold event on any one enabled axis triggers the activity
detection.
Activity Timer
Ideally, the intent of activity detection is to wake up a system
only when motion is intentional, ignoring noise or small,
unintentional movements. In addition to being sensitive to low
g events, the ADXL373 activity detection algorithm is robust in
filtering out undesired triggers.
Referenced and Absolute Configurations
The ADXL373 activity detection functionality includes a timer
to filter out unwanted motion and ensure that only sustained
motion is recognized as activity. The timer period depends on
the ODR selected. At 2560 Hz and under, the timer period is
approximately 8.25 ms, and at 5120 Hz, the timer period is
approximately 4.125 ms. For activity detection to trigger, above
threshold activity must be sustained for a time equal to the
number of activity timer periods specified in the activity time
Activity detection can be configured as referenced or absolute
mode for all axes through the ACT_REF bit in the
THRESH_ACT_X_L register.
When using absolute activity detection, acceleration samples are
compared directly to a user set threshold to determine whether
motion is present. For example, if a threshold of 0.5 g is set and
the acceleration on the z-axis is 1 g longer than the user defined
activity time, the activity status asserts.
Rev. A | Page 19 of 52
ADXL373
Data Sheet
register (Address 0x29). For example, a setting of 10 in this
register means that above threshold activity must be sustained
for 82.5 ms at 2560 Hz ODR. A register value of zero results in
single sample activity detection. The maximum allowable
activity time is approximately 2.1 sec (or 0.53 sec at 5120 Hz
ODR). Note that the activity timer is operational in
measurement mode only.
Referenced inactivity, like referenced activity, is particularly
useful for eliminating the effects of the static acceleration due to
gravity, as well as other static offsets. With absolute inactivity, if
the inactivity threshold is set lower than 1 g, a device resting
motionless may never detect inactivity. With referenced inactivity,
the same device under the same configuration detects inactivity.
The default setting for the accelerometer is in absolute mode.
After the accelerometer has been placed in referenced mode
through the appropriate register setting, the reference for
inactivity detection is calculated as soon as full bandwidth
measurement mode is turned on. To reset the reference, it is
necessary to put the device back into absolute mode and then
back into referenced mode. The new reference is set as soon as
the device enters full bandwidth measurement mode again. If
using both inactivity and activity detection in referenced mode,
both must be set back to absolute mode before the reference can
be reset.
Activity Detection in Wake-Up Mode
If activity detection is enabled while the device is in wake-up
mode, the device uses single sample activity detection, no
matter the activity time register setting. If activity is detected,
the device automatically returns to full bandwidth measurement
mode. However, the activity interrupt is not generated unless
the activity time setting is zero. If the activity time setting is not
zero after entering measurement mode, the interrupt is not
generated until the device sees sustained activity for the amount
of time given in the activity time register. The awake interrupt
automatically goes high upon entering measurement mode if the
device is in default mode or autosleep mode. If the device is in
linked or loop mode (but not autosleep), it is linked to the
activity interrupt, which behaves as mentioned in the Activity
Detection section.
If the FILTER_SETTLE bit is set to 1, set reference mode after
entering measurement mode or else the reference may not be
correct. If both the high-pass filter and low-pass filter for
activity detection are disabled, do not enable reference mode
earlier than 4/ODR after entering measurement mode. If either
filter is enabled, do not enable reference mode earlier than
463 ms after entering measurement mode.
After the device automatically enters measurement mode due to
activity detection, if autosleep is not on, the device must be
placed manually back into wake-up mode.
Inactivity Timer
The ADXL373 inactivity detect functionality includes a timer to
allow detection of sustained inactivity. The timer period is
approximately 32.5 ms regardless of the ODR. For inactivity
detection to trigger, under threshold inactivity must be sustained
for a time equal to the number of inactivity timer periods
specified in the inactivity time registers (Address 0x30 and
Address 0x31). For example, a setting of 10 in these registers
means that under threshold inactivity must be sustained for
325 ms. A value of zero in these registers results in single
sample inactivity detection. The maximum allowable inactivity
time is approximately 35.5 minutes.
Inactivity Detection
An inactivity event is detected when acceleration in all enabled
axes remains less than a specified threshold for a specified time.
Enabled axes, threshold, and time are user selected. Each axis
has its own inactivity threshold, but the inactivity timer is
shared among all three axes. When multiple axes are selected,
all enabled axes must stay lower than the threshold for the
required amount of time to trigger inactivity detection.
Referenced and Absolute Configurations
Inactivity detection is also configurable as referenced or absolute
through the INACT_REF bit in the THRESH_INACT_X_L
register. When using absolute inactivity detection, acceleration
samples are compared directly to a user set threshold for the user
set time to determine the absence of motion. Inactivity is detected
when enough consecutive samples are all less than the threshold.
Linking Activity and Inactivity Detection
When in measurement mode or wake-up mode, the activity and
inactivity detection functions can be used concurrently and
processed manually by a host processor, or these functions can
be configured to interact in several other ways through use of
default mode, linked mode, loop mode, and autosleep.
When using referenced inactivity detection, inactivity is
detected when acceleration samples are within a user specified
amount from an internally defined reference for a user defined
amount of time.
Rev. A | Page 20 of 52
Data Sheet
ADXL373
Default Mode
Loop Mode
In default mode, activity and inactivity detection are both
available simultaneously and all interrupts must be serviced by
a host processor. A processor must read each interrupt before it
is cleared and can be used again. Refer to the Interrupts section
for information on clearing interrupts.
In loop mode, motion detection operates as described in the
Linked Mode section, but interrupts do not need to be serviced
by a host processor. This configuration simplifies the implemen-
tation of commonly used motion detection and enhances power
savings by reducing the amount of power used in bus
communication.
The flowchart in Figure 43 shows default mode operation.
The flowchart in Figure 45 shows loop mode operation.
WAIT FOR
ACTIVITY
EVENT
WAIT FOR
PROCESSOR TO
CLEAR INTERRUPT
AWAKE = 1
AWAKE = 1
WAIT FOR
ACTIVITY
EVENT
WAIT FOR
INACTIVITY
EVENT
INACTIVITY
INTERRUPT
TRIGGERS
ACTIVITY
INTERRUPT
TRIGGERS
AWAKE = 0
AWAKE = 1
Figure 45. Activity and Inactivity Operation in Loop Mode Flowchart
WAIT FOR
PROCESSOR TO
CLEAR INTERRUPT
WAIT FOR
INACTIVITY
EVENT
Autosleep
If autosleep is selected, after the device is placed in wake-up
mode (see the Wake-Up Mode section), it automatically sets to
loop mode and begins looking for activity. When activity is
detected, the device automatically enters measurement mode
and immediately begins looking for inactivity. When inactivity
is detected, the device automatically re-enters wake-up mode.
Note that the device must be manually placed in wake-up mode
before autosleep can begin functioning. The device does not
automatically enter wake-up mode if the device is started up
manually in measurement mode.
NOTES
1. THE AWAKE BIT DEFAULTS TO 1 WHEN ACTIVITY AND INACTIVITY
ARE NOT LINKED.
Figure 43. Activity and Inactivity Operation in Default Mode Flowchart
Linked Mode
In linked mode, activity and inactivity detection are linked to
each other so that only one of the functions is enabled at any
given time. As soon as activity is detected, the device is assumed
to be moving (or awake) and stops looking for activity. Rather,
inactivity is expected as the next event. Therefore, only inactivity
detection operates.
Using the AWAKE Bit
Similarly, when inactivity is detected, the device is assumed to
be stationary (or asleep). Thus, activity is expected as the next
event. Therefore, only activity detection operates.
The AWAKE bit in the STATUS register (Address 0x04)
indicates whether the ADXL373 is awake or asleep. In default
mode or autosleep mode, the AWAKE bit is high whenever the
device is in measurement mode. In linked or loop mode, the
AWAKE bit is high whenever the device experiences an activity
condition, and it is low when the device experiences an
inactivity condition.
In linked mode, each interrupt must be serviced by a host
processor before the next interrupt is enabled.
The flowchart in Figure 44 shows linked mode operation.
WAIT FOR
ACTIVITY
EVENT
WAIT FOR
PROCESSOR TO
CLEAR INTERRUPT
AWAKE = 0
INACTIVITY
INTERRUPT
The awake signal can be mapped to the INT1 pin or INT2 pin,
allowing the pin to serve as a status output to connect or
disconnect power to downstream circuitry based on the awake
status of the accelerometer. Used in conjunction with loop
mode, this configuration implements a simple, autonomous
motion activated switch.
WAIT FOR
WAIT FOR
INACTIVITY
EVENT
AWAKE = 1
ACTIVITY
INTERRUPT
PROCESSOR TO
CLEAR INTERRUPT
If the turn on time of downstream circuitry can be tolerated,
this motion switch configuration can save significant system
level power by eliminating the standby current consumption of
the remainder of the application circuit. This standby current
can often exceed the full operating current of the ADXL373.
Figure 44. Activity and Inactivity Operation in Linked Mode Flowchart
Rev. A | Page 21 of 52
ADXL373
Data Sheet
exceeded the second threshold. The motion warning threshold
is controlled by the THRESH_ACT2_x_x registers and by the
ACTIVITY2 interrupt, which is sent only to the INT2 pin. Each
axis has its own motion warning threshold. However, the
motion warning activity interrupt does not have an activity
timer. It is only used for single sample activity detection. The
motion warning threshold also shares the same referenced and
absolute configuration as the primary activity detection.
MOTION WARNING
In addition to the activity threshold previously described, the
ADXL373 offers a secondary motion warning threshold. The
motion warning threshold can be set independently of the
activity threshold. The threshold does not have any
functionality related to autosleep, linked or loop mode, or the
device awake status. The purpose of the motion warning
functionality is to issue a notification to the system, via a status
bit and/or interrupt, that the observed acceleration has
Rev. A | Page 22 of 52
Data Sheet
ADXL373
IMPACT DETECTION FEATURES
Impact detection applications often require high g and high
bandwidth acceleration measurements, and the ADXL373 is
designed with these applications in mind. Several features are
included that target impact detection and aim to simplify the
system design.
INSTANT ON IMPACT DETECTION
The ADXL373 instant on mode is an ultra low power mode that
continuously monitors the environment for impact events that
exceed a built-in threshold. When an impact is detected, the
device switches into full bandwidth measurement mode and
captures the impact profile.
WIDE BANDWIDTH
An impact is a transient event that produces an acceleration
pulse with frequency content over a wide range. A sufficiently
wide bandwidth is needed to capture the impact event because
lowering bandwidth has the effect of reducing the magnitude of
the recorded signal, resulting in measurement inaccuracy.
No digital data is available in instant on mode. The user can
configure the device to detect an impact between a threshold
level of either 20 g to 30 g or 60 g to 80 g by using the
INSTANT_ON_THRESH bit in the POWER_CTL register.
When an impact beyond the selected threshold is detected, the
ADXL373 switches to measurement mode and begins
outputting digital data.
The ADXL373 can operate with bandwidths of up to 2560 Hz at
extremely low power levels. A steep filter roll-off is also useful
for effective suppression of out of band content. The ADXL373
incorporates a four-pole, low-pass antialiasing filter for this
purpose.
After the accelerometer is in full bandwidth measurement
mode, it must be set back into instant on mode manually by
first writing the device into measurement mode, and then back
to instant on mode. The accelerometer cannot return to instant on
mode automatically.
Rev. A | Page 23 of 52
ADXL373
Data Sheet
INTERRUPTS
Several of the built-in functions of the ADXL373 can trigger
interrupts to alert the host processor of certain status conditions.
The functionality of these interrupts is described in this section.
Alternate Functions
The INT1 and INT2 pins can be configured for use as input
pins instead of for signaling interrupts. INT1 is used as an
external clock input when the EXT_CLK bit in the TIMING
register is set. INT2 is used as the trigger input for synchronized
sampling when the EXT_SYNC bit in the TIMING register is
set. One or both of these alternate functions can be used
concurrently. However, if an interrupt pin is used for its
alternate function, the INTx pin cannot be used simultaneously
to signal interrupts.
INTERRUPT PINS
Interrupts can be mapped to either (or both) of two designated
output pins, INT1 and INT2, by setting the appropriate bits in
the INT1_MAP register and INT2_MAP register, respectively.
All functions can be used simultaneously. If multiple interrupts
are mapped to one pin, the OR combination of the interrupts
determines the status of the pin.
TYPES OF INTERRUPTS
Activity and Inactivity Interrupts
If no functions are mapped to an interrupt pin, that pin is
automatically configured to a high impedance (high-Z) state.
The INTx pins are also placed in the high-Z state upon a reset.
The ACTIVITY bit, INACT bit, and ACTIVITY2 bit in the
STATUS2 register are set when activity and inactivity are
detected, respectively. Detection procedures and criteria are
described in the Register Details section.
When a certain status condition is detected, the INTx pin that
condition is mapped to activates. The configuration of the INTx
pin is active high by default so that when the pin is activated, it
goes high. However, this configuration can be switched to active
low by setting the INTx_LOW bit in the appropriate INTx_MAP
register.
Data Ready Interrupt
The DATA_RDY bit in the STATUS register is set when new
valid data is available and is cleared when no new data is
available.
The INTx pins can connect to the interrupt input of a host
processor where interrupts are responded to with an interrupt
routine. Because multiple functions can be mapped to the same
pin, the STATUS register can determine which condition
caused the interrupt to trigger.
The DATA_RDY bit does not set while any of the data registers
are being read. If DATA_RDY = 0 prior to a register read and
new data becomes available during the register read,
DATA_RDY remains 0 until the read completes and then only
sets to 1.
Interrupts are cleared in several of the following ways:
•
Reading the STATUS2 register clears ACTIVITY and
inactivity interrupts. However, if activity detection is
operating in default mode and the activity or inactivity
timers are set to 0, the only way to clear the activity or
inactivity bits, respectively, is to set the device into standby
mode and restart full bandwidth measurement mode.
Reading the STATUS2 register clears the ACTIVITY2
interrupt with no caveats.
If DATA_RDY = 1 prior to a register read, it is cleared at the
start of the register read.
If DATA_RDY = 1 prior to a register read and new data
becomes available during the register read, DATA_RDY is
cleared to 0 at the start of the register read and remains 0
throughout the read. When the read completes, DATA_RDY
is set to 1.
•
•
Reading from the data registers clears the DATA_RDY
interrupt.
Both INTx pins are push-pull low impedance pins with an
output impedance of about 500 Ω (typical) and digital output
specifications as detailed in Table 2. Both INTx pins have bus
keepers that hold the pins to a valid logic state when the pins
are in high impedance mode.
To prevent interrupts from being falsely triggered during
configuration, disable interrupts while their settings, such as
thresholds, timings, or other values, are configured.
Rev. A | Page 24 of 52
Data Sheet
ADXL373
ADDITIONAL FEATURES
Because of internal timing requirements, the maximum
allowable external trigger frequencies are as follows:
USING AN EXTERNAL CLOCK
When operating at 2560 Hz ODR or lower, the ADXL373 has a
built-in 307.2 kHz (typical) clock that, by default, serves as the
time base for internal operations. At 5120 Hz ODR, this clock
speed increases to 614.4 kHz (typical). If desired, an external
clock can be provided instead, for either improved clock
frequency accuracy or for control of the output data rate. To use
an external clock, set the EXT_CLK bit (Bit 1) in the TIMING
register (Register 0x3D) and apply a clock to the INT1 pin.
•
•
•
1-axis data: 2480 Hz
2-axis data: 2160 Hz
3-axis data: 1760 Hz
These values are doubled when an ODR rate of 5120 Hz is
selected. Additionally, the trigger signal applied to the INT2 pin
must meet the following criteria:
•
•
•
The trigger signal must be active high.
The external clock can operate at the nominal 307.2 kHz or
slower (when using ODR ≤ 2560 Hz), or 614.4 kHz or slower
(when using ODR = 5120 Hz) to allow the user to achieve any
desired output data rate. Lower external clock rates must be
used with caution, because external clock rates can result in
aliasing of high frequency signals that can be present in certain
applications.
The pulse width of the trigger signal must be at least 53 µs.
The minimum sampling frequency is set only by system
requirements. Samples need not be polled at any minimum
rate. However, if samples are polled at a rate lower than the
bandwidth set by the antialiasing filter, aliasing may occur.
The EXT_SYNC bit is an active high signal. Due to the
asynchronous nature of the internal clock and external sync,
there may be a one ODR clock cycle difference between
consecutive external sync pulses. The external sync sets the ODR of
the system. For example, if sending an external sync at a 2 kHz
rate, all 3-axes (if enabled) are sampled in that 2 kHz window.
ODR and bandwidth scale proportionally with the clock. The
ADXL373 provides a discrete number of options for ODR.
Output data rates other than those provided are achieved by
selecting an appropriate clock frequency. For example, to
achieve a 2048 Hz ODR, use the 2560 Hz setting with a clock
frequency that is 80% of nominal, or 245.76 kHz. Bandwidth
also scales by the same ratio, therefore, if a 320 Hz bandwidth
setting is selected, the resulting bandwidth is 256 Hz.
SELF TEST
When the self test function is invoked, an electrostatic force
is applied to the mechanical sensor. This electrostatic force
moves the mechanical sensing element in the same manner
as acceleration, and the acceleration experienced by the
device increases because of this force. The high-pass filter
is automatically disabled for this feature.
SYNCHRONIZED DATA SAMPLING
For applications that require a precisely timed acceleration
measurement, the ADXL373 features an option to synchronize
acceleration sampling to an external trigger. The EXT_SYNC
bit in the TIMING register enables this feature. When the
EXT_SYNC bit is set to 1, the INT2 pin automatically
reconfigures for use as the sync trigger input.
Self Test Procedure
The self test function is enabled via the ST bit in the SELF_TEST
register, Register 0x40. The ST_DONE bit indicates when the test is
completed. Figure 46 describes the self test profile from when ST
is set until ST_DONE goes high, which typically takes around
200 ms. Self test is considered successful if ΔST is greater than
5 LSB.
When external triggering is enabled, it is up to the system
designer to ensure that the sampling frequency meets system
requirements. Sampling too infrequently causes aliasing. Noise
can be lowered by oversampling. However, sampling at too high a
frequency may not allow enough time for the accelerometer to
process the acceleration data and convert the data to valid
digital output.
When the Nyquist criterion is met, signal integrity is
maintained. An internal antialiasing filter is available in the
ADXL373 and can assist the system designer in maintaining
signal integrity. To prevent aliasing, set the filter bandwidth to a
frequency no greater than half the sampling rate. For example,
when sampling at 1280 Hz, set the filter bandwidth to no higher
than 640 Hz.
|ΔST| > 5 LSB
TIME
ST
ST_DONE
Figure 46. Self Test Waveform
Rev. A | Page 25 of 52
ADXL373
Data Sheet
The recommended procedure for using the self test functionality is
as follows:
Protection is implemented via a 99-bit error correcting (Hamming
type) code and detects both single bit and double bit errors. The
check bits are recomputed any time a write to any of the protected
registers occurs. At any time, if the stored version of the check
bits is not in agreement with the current check bit calculation,
the ERR_USER_REGS bit in the STATUS register is set.
1. Ensure that the low-pass activity filter is enabled.
2. Place the device in measurement mode.
3. Wait until the filter settling time passes.
4. Start the self test by setting the ST bit in the SELF_TEST
register (Register 0x40).
5. Read the acceleration data from the z-axis (Register 0x0C
and Register 0x0D) and store the data until the self test
completes (ST_DONE goes high).
The ERR_USER_REGS bit in the STATUS register starts high
when set on an unconfigured device and clears after the first
register write.
USER OFFSET TRIMS
6. Average the first 50 ms of data right after ST is set.
7. Average the last 50 ms of data right before ST_DONE goes
high.
The ADXL373 has a 4-bit offset trim for each axis that allows
users to add positive or negative offset to the default static
acceleration values and correct any deviations from ideal that
may result as a consequence of varying the operating parameters of
the device. The offset trims have a full-scale range of approximately
60 LSB with a trim profile as shown in Figure 47.
8. If the difference between the two averaged values is greater
than 5 LSB, the self test passes.
During the deviation of the z-axis, the x-axis and y-axis also show
deviation, which is normal. However, the outputs of the x-axis
and y-axis cannot be used to qualify pass or fail of the self test.
80
X-AXIS
Y-AXIS
Z-AXIS
60
40
USER REGISTER PROTECTION
The ADXL373 includes user register protection for single event
upsets (SEUs). An SEU is a change of state caused by ions or
electromagnetic radiation striking a sensitive node in a micro-
electronic device. The state change is a result of the free charge
created by ionization in or close to an important node of a logic
element (for example, a memory bit). The SEU itself is not con-
sidered permanently damaging to transistor or circuit
20
0
–20
–40
–60
–80
functionality but it can create erroneous register values. The
registers protected from SEU are Register 0x20 to Register 0x3F.
0
2
4
6
8
10
12
14
16
REGISTER VALUE
Figure 47. User Offset Trim Profile
Rev. A | Page 26 of 52
Data Sheet
ADXL373
SERIAL COMMUNICATIONS
V
DD I/O
SERIAL INTERFACE
The ADXL373 is designed to communicate in either the SPI or
the I2C protocol. The ADXL373 automatically detects the
format being used, requiring no configuration control to select
the format.
R
R
P
ADXL373
PROCESSOR
P
CS/SCL
MOSI/SDA
SCLK
DIN/OUT
DOUT
SCL
SPI Protocol
The timing scheme follows: phase (CPHA) = polarity (CPOL) = 0.
The ADXL373 supports a SCLK frequency up to 10 MHz. Wire
the ADXL373 for SPI communication as shown in Figure 48. For
successful communication, follow the logic thresholds and
timing parameters in Table 3. Ignore data transmitted from the
ADXL373 to the master device during writes to the ADXL373.
Figure 49. I2C Connection Diagram (Address 0x53)
If other devices are connected to the same I2C bus, the nominal
operating voltage level of these other devices cannot exceed
V
DD I/O by more than 0.3 V. External pull-up resistors (RP) are
necessary for proper I2C operation.
ADXL373
PROCESSOR
MULTIBYTE TRANSFERS
CS/SCL
MOSI/SDA
MISO
DOUT
DOUT
DIN
Both the SPI and I2C protocols support multibyte transfers, also
known as burst transfers. A register read or write begins with
the address specified in the command and auto-increments for
each additional byte in the transfer. Always read acceleration
data using multibyte transfers to ensure that a concurrent and
complete set of x, y, and z acceleration data is read.
SCLK
DOUT
Figure 48. 4-Wire SPI Connection Diagram
I2C Protocol
When writing data to the ADXL373 in I2C mode, the negative
acknowledgement (NACK) bit never generates. Instead, an
acknowledgement (ACK) bit is sent after every received byte
because it is not known how many bytes are included in the
transfer. The master decides how many bytes are sent and ends
the transaction with the stop condition.
The ADXL373 supports standard (100 kHz), fast (up to 1 MHz),
and high speed (up to 3.4 MHz) data transfer modes if the bus
parameters given in Table 4 are met. There is no minimum SCL
frequency, with the exception that when reading data, the clock
must be fast enough to read an entire sample set before new
data overwrites it. Single or multiple byte reads and writes are
supported. When the MISO pin is low, the I2C address for the
device is 0x1D and an alternate I2C address of 0x53 can be
chosen by pulling the MISO pin high.
INVALID ADDRESSES AND ADDRESS FOLDING
The ADXL373 has a 6-bit address bus, mapping only 104 registers
in the possible 256-register address space. The addresses do not
fold to repeat the registers at addresses greater than 104.
Attempted access to register addresses above 104 are mapped to
the invalid register at 0x67 and have no functional effect.
There are no internal pull-up or pull-down resistors for any
unused pins. Therefore, there is no known state or default state
for the MISO and SCLK pins if left floating or unconnected. It is a
requirement that SCLK be connected to ground when
communicating to the ADXL373 using I2C.
Register 0x00 to Register 0x41 are for customer access, as
described in Table 14. Register 0x42 to Register 0x67 are
reserved for factory use.
Due to communication speed limitations, the maximum output
data rate when using 400 kHz I2C is 640 Hz and scales linearly
with a change in the I2C communication speed. For example,
using I2C at 200 kHz limits, the maximum ODR to 320 Hz.
Operation at an output data rate above the recommended
maximum can result in an undesirable effect on the acceleration
data, including missing samples or additional noise.
Rev. A | Page 27 of 52
ADXL373
Data Sheet
REGISTER MAP
Table 14. Register Map
Reg Name
Bits Bit 7
[7:0]
Bit 6
Bit 5
Bit 4
Bit 3
DEVID_AD
DEVID_MST
Bit 2
Bit 1
Bit 0
Reset R/W
0xAD R
0x00 DEVID_AD
0x01 DEVID_MST
0x02 PARTID
[7:0]
0x1D R
[7:0]
DEVID_PRODUCT
REVID
0xFA
0x02
R
R
0x03 REVID
[7:0]
0x04 STATUS
[7:0] ERR_USER_ AWAKE
REGS
USER_NVM_BUSY
ACTIVITY
RESERVED
DATA_RDY 0xA0 R
0x05 STATUS2
0x06 RESERVED
0x07 RESERVED
0x08 XDATA_H
0x09 XDATA_L
0x0A YDATA_H
0x0B YDATA_L
0x0C ZDATA_H
0x0D ZDATA_L
[7:0] RESERVED ACTIVITY2
INACT
RESERVED
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
R
R
R
R
R
R
R
R
R
R
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
RESERVED
RESERVED
XDATA[11:4]
XDATA[3:0]
RESERVED
RESERVED
RESERVED
YDATA[11:4]
ZDATA[11:4]
RESERVED
YDATA[3:0]
ZDATA[3:0]
0x0E RESERVED
to
0x1F
0x20 OFFSET_X
0x21 OFFSET_Y
0x22 OFFSET_Z
[7:0]
[7:0]
[7:0]
RESERVED
RESERVED
RESERVED
OFFSET_X
OFFSET_Y
OFFSET_Z
0x00 R/W
0x00 R/W
0x00 R/W
0x00 R/W
0x23 THRESH_ACT_X_H [7:0]
0x24 THRESH_ACT_X_L [7:0]
0x25 THRESH_ACT_Y_H [7:0]
0x26 THRESH_ACT_Y_L [7:0]
0x27 THRESH_ACT_Z_H [7:0]
0x28 THRESH_ACT_Z_L [7:0]
THRESH_ACT_X[10:3]
THRESH_ACT_X[2:0]
THRESH_ACT_Y[2:0]
THRESH_ACT_Z[2:0]
RESERVED
ACT_REF ACT_X_EN 0x00 R/W
0x00 R/W
THRESH_ACT_Y[10:3]
THRESH_ACT_Z[10:3]
ACT_COUNT
RESERVED
RESERVED
ACT_Y_EN 0x00 R/W
0x00 R/W
ACT_Z_EN 0x00 R/W
0x00 R/W
0x29 TIME_ACT
[7:0]
0x2A THRESH_INACT_X_H [7:0]
0x2B THRESH_INACT_X_L [7:0]
0x2C THRESH_INACT_Y_H [7:0]
0x2D THRESH_INACT_Y_L [7:0]
0x2E THRESH_INACT_Z_H [7:0]
0x2F THRESH_INACT_Z_L [7:0]
THRESH_INACT_X[10:3]
RESERVED
THRESH_INACT_Y[10:3]
RESERVED
THRESH_INACT_Z[10:3]
RESERVED
0x00 R/W
THRESH_INACT_X[2:0]
THRESH_INACT_Y[2:0]
THRESH_INACT_Z[2:0]
INACT_REF INACT_X_EN 0x00 R/W
0x00 R/W
INACT_Y_EN 0x00 R/W
0x00 R/W
INACT_Z_EN 0x00 R/W
0x00 R/W
0x30 TIME_INACT_H
0x31 TIME_INACT_L
[7:0]
[7:0]
INACT_COUNT[15:8]
INACT_COUNT[7:0]
0x00 R/W
0x32 THRESH_ACT2_X_H [7:0]
0x33 THRESH_ACT2_X_L [7:0]
0x34 THRESH_ACT2_Y_H [7:0]
0x35 THRESH_ACT2_Y_L [7:0]
0x36 THRESH_ACT2_Z_H [7:0]
0x37 THRESH_ACT2_Z_L [7:0]
THRESH_ACT2_X[10:3]
0x00 R/W
THRESH_ACT2_X[2:0]
THRESH_ACT2_Y[2:0]
THRESH_ACT2_Z[2:0]
RESERVED
THRESH_ACT2_Y[10:3]
RESERVED
THRESH_ACT2_Z[10:3]
RESERVED
ACT2_REF ACT2_X_EN 0x00 R/W
0x00 R/W
ACT2_Y_EN 0x00 R/W
0x00 R/W
ACT2_Z_EN 0x00 R/W
Rev. A | Page 28 of 52
Data Sheet
ADXL373
Reg Name
Bits Bit 7
[7:0]
Bit 6
Bit 5
Bit 4
RESERVED
Bit 3
Bit 2
Bit 1
Bit 0
Reset R/W
0x38 HPF
HPF_CORNER
0x00 R/W
0x39 RESERVED
0x3A RESERVED
0x3B INT1_MAP
[7:0]
RESERVED
RESERVED
0x00
0x00
R
R
[7:0]
[7:0] INT1_LOW AWAKE_INT1 ACT_INT1
INACT_INT1
RESERVED
RESERVED
DATA_RDY_ 0x00 R/W
INT1
0x3C INT2_MAP
[7:0] INT2_LOW AWAKE_INT2 ACT2_INT2
INACT_INT2
DATA_RDY_ 0x00 R/W
INT2
0x3D TIMING
[7:0]
ODR
WAKEUP_RATE
EXT_CLK EXT_SYNC 0x00 R/W
0x3E MEASURE
[7:0] USER_OR_ AUTOSLEEP
DISABLE
LINKLOOP
LOW_NOISE
BANDWIDTH
MODE
ST_DONE ST
0x00 R/W
0x00 R/W
0x00 R/W
0x3F POWER_CTL
[7:0] I2C_HSM_ RESERVED
EN
INSTANT_ON_
THRESH
FILTER_
SETTLE
LPF_DISABLE HPF_DISABLE
0x40 SELF_TEST
0x41 RESET
[7:0]
[7:0]
RESERVED
RESET
0x00 W
Rev. A | Page 29 of 52
ADXL373
Data Sheet
REGISTER DETAILS
ANALOG DEVICES ID REGISTER
Address: 0x00, Reset: 0xAD, Name: DEVID_AD
This register contains the Analog Devices, Inc., ID, 0xAD.
7
6
5
4
3
2
1
0
1
0
1
0
1
1
0
1
[7:0 ] DEVID_AD (R)
Analog Devices ID, 0xAD.
Table 15. Bit Descriptions for DEVID_AD
Bits
Bit Name
Settings
Description
Analog Devices ID, 0xAD.
Reset
Access
[7:0]
DEVID_AD
Not applicable
0xAD
R
ANALOG DEVICES MEMS ID REGISTER
Address: 0x01, Reset: 0x1D, Name: DEVID_MST
This register contains the Analog Devices MEMS ID, 0x1D.
7
6
5
4
3
2
1
0
0
0
0
1
1
1
0
1
[7 :0] DEVID_M ST (R)
Analog Devices MEMS ID, 0x1D.
Table 16. Bit Descriptions for DEVID_MST
Bits
Bit Name
Settings
Description
Analog Devices MEMS ID, 0x1D.
Reset
Access
[7:0]
DEVID_MST
Not applicable
0x1D
R
DEVICE ID REGISTER
Address: 0x02, Reset: 0xFA, Name: PARTID
This register contains the device ID, 0xFA (372 octal).
7
6
5
4
3
2
1
0
1
1
1
1
1
0
1
0
[7:0 ] DEVID_PRODUCT (R)
Device ID, 0xFA (372 Octal).
Table 17. Bit Descriptions for PARTID
Bits
Bit Name
Settings
Description
Reset
Access
[7:0]
DEVID_PRODUCT
Not applicable
Device ID, 0xFA (372 Octal).
0xFA
R
PRODUCT REVISION ID REGISTER
Address: 0x03, Reset: 0x02, Name: REVID
This register contains the mask revision ID, beginning with 0x00 and incrementing for each subsequent revision.
7
6
5
4
3
2
1
0
0
0
0
0
0
0
1
0
[7:0] REVID (R)
Mask Revision.
Table 18. Bit Descriptions for REVID
Bits
Bit Name
Settings
Description
Reset
0x02
Access
[7:0]
REVID
Not applicable
Mask Revision.
R
Rev. A | Page 30 of 52
Data Sheet
ADXL373
STATUS REGISTER
Address: 0x04, Reset: 0xA0, Name: STATUS
This register includes the following bits that describe various conditions of the ADXL373.
Table 19. Bit Descriptions for STATUS
Bits Bit Name
Settings
Description
Reset Access
7
6
5
ERR_USER_REGS
AWAKE
Not applicable SEU Event. An SEU event is detected in a user register.
Not applicable Awake Status. Activity is detected and the device is moving.
0x1
0x0
0x1
0x0
0x0
R
R
R
R
R
USER_NVM_BUSY Not applicable 1 = nonvolatile memory (NVM) is busy programming fuses.
[4:1] RESERVED
DATA_RDY
Not applicable Reserved.
0
Not applicable Status is high after the full data set completes. A complete x, y, and z
measurement was made, and results can be read.
ACTIVITY STATUS REGISTER
Address: 0x05, Reset: 0x00, Name: STATUS2
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[ 7 ] RESERVED
[ 3:0 ] RESERVED
[ 6 ] ACT IVIT Y2 ( R)
Status of ACTIVITY2.
[ 4 ] INACT ( R)
Inactivity.
[ 5] ACT IVIT Y ( R)
Activity.
Table 20. Bit Descriptions for STATUS2
Bits
Bit Name
RESERVED
ACTIVITY2
ACTIVITY
INACT
Settings
Description
Reset
0x0
Access
7
Not applicable
Not applicable
Not applicable
Not applicable
Not applicable
Reserved.
R
R
R
R
R
6
Status of ACTIVITY2.
0x0
5
Activity. Activity is detected.
Inactivity. Inactivity is detected.
Reserved.
0x0
4
0x0
[3:0]
RESERVED
0x0
Rev. A | Page 31 of 52
ADXL373
Data Sheet
X-AXIS DATA REGISTER, MSB
Address: 0x08, Reset: 0x00, Name: XDATA_H
These two registers contain the x-axis acceleration data. Data is left justified and formatted as twos complement. XDATA_H contains the
eight MSBs, and XDATA_L contains the four LSBs of the 12-bit value.
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:0] XDATA[11:4] (R)
X-Axis Data.
Table 21. Bit Descriptions for XDATA_H
Bits
Bit Name
Settings
Description
Reset
Access
[7:0]
XDATA[11:4]
Not applicable
X-Axis Data.
0x0
R
X-AXIS DATA REGISTER, LSB
Address: 0x09, Reset: 0x00, Name: XDATA_L
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:4] XDATA[3:0] (R)
X-Axis Data.
[3:0] RESERVED
Table 22. Bit Descriptions for XDATA_L
Bits
[7:4]
[3:0]
Bit Name
XDATA[3:0]
RESERVED
Settings
Description
X-Axis Data.
Reserved.
Reset
0x0
Access
Not applicable
Not applicable
R
R
0x0
Y-AXIS DATA REGISTER, MSB
Address: 0x0A, Reset: 0x00, Name: YDATA_H
The YDATA_H and YDATA_L registers contain the y-axis, LSB and MSB acceleration data. Data is left justified and formatted as twos
complement. YDATA_H contains the eight MSBs, and YDATA_L contains the four LSBs of the 12-bit value.
YDATA_L latches on a read of YDATA_H to ensure data integrity.
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:0] YDATA[11:4] (R)
Y-Axis Data.
Table 23. Bit Descriptions for YDATA_H
Bits
Bit Name
Settings
Description
Reset
Access
[7:0]
YDATA[11:4]
Not applicable
Y-Axis Data.
0x0
R
Y-AXIS DATA REGISTER, LSB
Address: 0x0B, Reset: 0x00, Name: YDATA_L
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:4] YDATA[3:0] (R)
Y-Axis Data.
[3:0] RESERVED
Table 24. Bit Descriptions for YDATA_L
Bits
[7:4]
[3:0]
Bit Name
YDATA[3:0]
RESERVED
Settings
Description
Y-Axis Data.
Reserved.
Reset
0x0
Access
Not applicable
Not applicable
R
R
0x0
Rev. A | Page 32 of 52
Data Sheet
ADXL373
Z-AXIS DATA REGISTER, MSB
Address: 0x0C, Reset: 0x00, Name: ZDATA_H
These two registers contain the z-axis acceleration data. Data is left justified and formatted as twos complement. ZDATA_H contains the
eight MSBs, and ZDATA_L contains the four LSBs of the 12-bit value.
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:0] ZDATA[11:4] (R)
Z-Axis Data.
Table 25. Bit Descriptions for ZDATA_H
Bits
Bit Name
Settings
Description
Reset
Access
[7:0]
ZDATA[11:4]
Not applicable
Z-Axis Data.
0x0
R
Z-AXIS DATA REGISTER, LSB
Address: 0x0D, Reset: 0x00, Name: ZDATA_L
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:4] ZDATA[3:0] (R)
Z-Axis Data.
[3:0] RESERVED
Table 26. Bit Descriptions for ZDATA_L
Bits
[7:4]
[3:0]
Bit Name
ZDATA[3:0]
RESERVED
Settings
Description
Z-Axis Data.
Reserved.
Reset
0x0
Access
Not applicable
Not applicable
R
R
0x0
OFFSET TRIM REGISTERS
Offset trim registers are each four bits and offer user set, offset adjustments in twos complement format. The scale factor of these registers
is shown in Figure 47.
X-Axis Offset Trim Register, LSB
Address: 0x20, Reset: 0x00, Name: OFFSET_X
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:4] RESERVED
[3:0] OFFSET_X (R/W)
Offset added to x-axis data.
Table 27. Bit Descriptions for OFFSET_X
Bits
[7:4]
[3:0]
Bit Name
RESERVED
OFFSET_X
Settings
Description
Reset
0x0
Access
R
Not applicable
Reserved.
Customizable by customer
Offset added to x-axis data.
0x0
R/W
Rev. A | Page 33 of 52
ADXL373
Data Sheet
Y-Axis Offset Trim Register, LSB
Address: 0x21, Reset: 0x00, Name: OFFSET_Y
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:4] RESERVED
[3:0] OFFSET_Y (R/W)
Offset added to y-axis data.
Table 28. Bit Descriptions for OFFSET_Y
Bits
[7:4]
[3:0]
Bit Name
RESERVED
OFFSET_Y
Settings
Description
Reset
0x0
Access
R
Not applicable
Reserved.
Customizable by customer
Offset added to y-axis data.
0x0
R/W
Z-Axis Offset Trim Register, LSB
Address: 0x22, Reset: 0x00, Name: OFFSET_Z
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:4] RESERVED
[3:0] OFFSET_Z (R/W)
Offset added to z-axis data.
Table 29. Bit Descriptions for OFFSET_Z
Bits
[7:4]
[3:0]
Bit Name
RESERVED
OFFSET_Z
Settings
Description
Reset
0x0
Access
R
Not applicable
Reserved.
Customizable by customer
Offset added to z-axis data.
0x0
R/W
X-AXIS ACTIVITY THRESHOLD REGISTER, MSB
Address: 0x23, Reset: 0x00, Name: THRESH_ACT_X_H
This 11-bit unsigned value sets the threshold for activity detection. This value is set in codes and the scale factor is 100 mg/code. To
detect activity, the absolute value of the 12-bit acceleration data is compared with the 11-bit (unsigned) activity threshold value. The
THRESH_ACT_X_L register contains the least significant bits, and the THRESH_ACT_X_H register contains the most significant byte
of the activity threshold value.
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:0] THRESH_ACT_X[10:3] (R/W)
Threshold for Activity Detection.
Table 30. Bit Descriptions for THRESH_ACT_X_H
Bits Bit Name Settings
Description
Reset Access
0x0 R/W
[7:0] THRESH_ACT_X[10:3] Customizable by
customer
Threshold for Activity Detection. These bits are the 8 MSBs of
the x-axis threshold.
Rev. A | Page 34 of 52
Data Sheet
ADXL373
X-AXIS OF ACTIVITY THRESHOLD REGISTER, LSB
Address: 0x24, Reset: 0x00, Name: THRESH_ACT_X_L
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
1
[7:5] THRESH_ACT_X[2:0] (R/W)
Threshold for Activity Detection.
[0] ACT_X_EN (R/W)
Enable activity detection using x-axis data.
0: X-axis ignored
1: X-axis used
[4:2] RESERVED
[1] ACT_REF (R/W)
Selects referenced or absolute activity processing.
0: Referenced activity processing
1: Absolute activity processing
Table 31. Bit Descriptions for THRESH_ACT_X_L
Bits Bit Name
Settings
Description
Reset Access
[7:5] THRESH_ACT_X[2:0] Customizable by
customer
Threshold for Activity Detection. These bits are the 3 LSBs of x-axis 0x0
threshold.
R/W
[4:2] RESERVED
Not applicable
Reserved.
0x0
0x0
R
1
ACT_REF
Selects referenced or absolute activity processing.
Referenced activity processing.
Absolute activity processing.
Enable activity detection using x-axis data.
X-axis ignored.
R/W
1
0
0
ACT_X_EN
0x0
R/W
0
1
X-axis used.
Y-AXIS ACTIVITY THRESHOLD REGISTER, MSB
Address: 0x25, Reset: 0x00, Name: THRESH_ACT_Y_H
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:0] THRESH_ACT_Y[10:3] (R/W)
Threshold for Activity Detection.
Table 32. Bit Descriptions for THRESH_ACT_Y_H
Bits Bit Name
Settings
Description
Reset Access
0x0 R/W
[7:0] THRESH_ACT_Y[10:3] Customizable by
customer
Threshold for Activity Detection. These bits are the 8 MSBs of y-
axis threshold.
Rev. A | Page 35 of 52
ADXL373
Data Sheet
Y-AXIS OF ACTIVITY THRESHOLD REGISTER, LSB
Address: 0x26, Reset: 0x00, Name: THRESH_ACT_Y_L
Table 33. Bit Descriptions for THRESH_ACT_Y_L
Bits Bit Name
Settings
Description
Reset Access
[7:5] THRESH_ACT_Y[2:0] Customizable by
customer
Threshold for Activity Detection. These bits are the 3 LSBs of y-axis
threshold.
0x0
R/W
[4:1] RESERVED
ACT_Y_EN
Not applicable
Reserved.
0x0
0x0
R
0
Enable activity detection using y-axis data.
Y-axis ignored.
R/W
0
1
Y-axis used.
Z-AXIS ACTIVITY THRESHOLD REGISTER, MSB
Address: 0x27, Reset: 0x00, Name: THRESH_ACT_Z_H
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:0] THRESH_ACT_Z[10:3] (R/W)
Threshold for Activity Detection.
Table 34. Bit Descriptions for THRESH_ACT_Z_H
Bits Bit Name Settings
Description
Reset Access
0x0 R/W
[7:0] THRESH_ACT_Z[10:3] Customizable by
customer
Threshold for Activity Detection. These bits are the 8 MSBs of
z-axis threshold.
Z-AXIS OF ACTIVITY THRESHOLD REGISTER, LSB
Address: 0x28, Reset: 0x00, Name: THRESH_ACT_Z_L
Table 35. Bit Descriptions for THRESH_ACT_Z_L
Bits Bit Name
Settings
Description
Reset Access
[7:5] THRESH_ACT_Z[2:0] Customizable by
customer
Threshold for Activity Detection. These bits are the 3 LSBs of z-axis 0x0
threshold.
R/W
[4:1] RESERVED
ACT_Z_EN
Not applicable
Reserved.
0x0
0x0
R
0
Enable activity detection using z-axis data.
Z-axis ignored.
R/W
0
1
Z-axis used.
Rev. A | Page 36 of 52
Data Sheet
ADXL373
ACTIVITY TIME REGISTER
Address: 0x29, Reset: 0x00, Name: TIME_ACT
The activity timer implements a robust activity detection that minimizes false positive motion triggers. When the timer is used, only
sustained motion can trigger activity detection. The time (in milliseconds) is given by the following equation:
Time = TIME_ACT × 4.125 ms per code
where:
TIME_ACT is the value set in this register.
4.125 ms per code is the scale factor of the TIME_ACT register for ODR = 5120 Hz. The scale factor is 8.25 ms per code for ODR =
2560 Hz and values less than 2560 Hz. See the Activity Timer section for more information.
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[ 7 :0 ] ACT _CO UNT ( R/W )
Number of multiples of 4.125 ms activity
timer for which above threshold acceleration
to detect activity.
Table 36. Bit Descriptions for TIME_ACT
Bits Bit Name Settings Description
[7:0] ACT_COUNT Customizable Number of multiples of 4.125 ms activity timer for which above threshold
Reset Access
0x0 R/W
by customer
acceleration to detect activity. The scale factor is 4.125 ms per code for 5120 Hz
ODR, and the scale factor is 8.25 ms per code for 2560 Hz ODR and values less
than 2560 Hz.
X-AXIS INACTIVITY THRESHOLD REGISTER, MSB
Address: 0x2A, Reset: 0x00, Name: THRESH_INACT_X_H
This 11-bit unsigned value sets the threshold for inactivity detection. This value is set in codes and the scale factor is 100 mg per code. To
detect inactivity, the absolute value of the 12-bit acceleration data is compared with the 11-bit (unsigned) inactivity threshold value. The
THRESH_INACT_X_L register contains the least significant bits, and the THRESH_INACT_X_H register contains the most significant
byte of the inactivity threshold value.
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:0] THRESH_INACT_X[10:3] (R/W)
Threshold for Inactivity Detection.
Table 37. Bit Descriptions for THRESH_INACT_X_H
Bits Bit Name Settings
Description
Reset Access
0x0 R/W
[7:0] THRESH_INACT_X[10:3] Customizable by
customer
Threshold for Inactivity Detection. These bits are the 8 MSBs
of x-axis.
Rev. A | Page 37 of 52
ADXL373
Data Sheet
X-AXIS OF INACTIVITY THRESHOLD REGISTER, LSB
Address: 0x2B, Reset: 0x00, Name: THRESH_INACT_X_L
Table 38. Bit Descriptions for THRESH_INACT_X_L
Bits Bit Name
Settings
Description
Reset Access
[7:5] THRESH_INACT_X[2:0] Customizable by
customer
Threshold for Inactivity Detection. These bits are the 3 LSBs of
the x-axis.
0x0
R/W
[4:2] RESERVED
Not applicable
Reserved.
0x0
0x0
R
1
INACT_REF
Selects referenced or absolute inactivity processing.
Referenced inactivity processing.
Absolute inactivity processing.
X-axis masked from participating in inactivity detection.
X-axis ignored.
R/W
1
0
0
INACT_X_EN
0x0
R/W
0
1
X-axis used.
Y-AXIS INACTIVITY THRESHOLD REGISTER, MSB
Address: 0x2C, Reset: 0x00, Name: THRESH_INACT_Y_H
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:0] THRESH_INACT_Y[10:3] (R/W)
Threshold for Inactivity Detection.
Table 39. Bit Descriptions for THRESH_INACT_Y_H
Bits Bit Name
Settings
Description
Reset Access
0x0 R/W
[7:0] THRESH_INACT_Y[10:3] Customizable by
customer
Threshold for Inactivity Detection. These bits are the 8 MSBs of
the y-axis.
Rev. A | Page 38 of 52
Data Sheet
ADXL373
Y-AXIS OF INACTIVITY THRESHOLD REGISTER, LSB
Address: 0x2D, Reset: 0x00, Name: THRESH_INACT_Y_L
Table 40. Bit Descriptions for THRESH_INACT_Y_L
Bits Bit Name
Settings
Description
Reset Access
[7:5] THRESH_INACT_Y[2:0] Customizable by
customer
Threshold for Inactivity Detection. These bits are the 3 LSBs of
the y-axis.
0x0
R/W
[4:1] RESERVED
INACT_Y_EN
Not applicable
Reserved.
0x0
0x0
R
0
Y-axis masked from participating in inactivity detection.
R/W
0
1
Y-axis ignored.
Y-axis used.
Z-AXIS INACTIVITY THRESHOLD REGISTER, MSB
Address: 0x2E, Reset: 0x00, Name: THRESH_INACT_Z_H
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:0] THRESH_INACT_Z[10:3] (R/W)
Threshold for Inactivity Detection.
Table 41. Bit Descriptions for THRESH_INACT_Z_H
Bits Bit Name
Settings
Description
Reset Access
[7:0] THRESH_INACT_Z[10:3] Customizable by
customer
Threshold for Inactivity Detection. These bits are the 8 MSBs of 0x0
the z-axis.
R/W
Z-AXIS OF INACTIVITY THRESHOLD REGISTER, LSB
Address: 0x2F, Reset: 0x00, Name: THRESH_INACT_Z_L
Table 42. Bit Descriptions for THRESH_INACT_Z_L
Bits Bit Name
Settings
Description
Reset Access
[7:5] THRESH_INACT_Z[2:0] Customizable by
customer
Threshold for Inactivity Detection. These bits are the 3 LSBs of
the z-axis.
0x0
R/W
[4:1] RESERVED
INACT_Z_EN
Not applicable
Reserved.
0x0
0x0
R
0
Z-axis masked from participating in inactivity detection.
R/W
0
1
Z-axis ignored.
Z-axis used.
Rev. A | Page 39 of 52
ADXL373
Data Sheet
INACTIVITY TIME REGISTERS
The 16-bit value in these registers sets the time that all enabled axes must be lower than the inactivity threshold for an inactivity event to
be detected. The TIME_INACT_L register holds the eight LSBs, and the TIME_INACT_H register holds the eight MSBs of the 16-bit
TIME_INACT value.
Calculate the time as follows:
Time = TIME_INACT × 32.5 ms per code
where:
TIME_INACT is the 16-bit value set by the TIME_INACT_L register (eight LSBs) and the TIME_INACT_H register (eight MSBs).
32.5 ms per code is the scale factor of the TIME_INACT_L register and TIME_INACT_H register for 2560 Hz and values less than
2560 Hz. The scale factor is 16.25 ms per code of ODR = 5120 Hz. See the Inactivity Timer section for more information.
INACTIVITY TIMER REGISTER, MSB
Address: 0x30, Reset: 0x00, Name: TIME_INACT_H
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[ 7 :0 ] INACT _CO UNT [ 15:8 ] ( R/W )
Number of multiples of 32.5 ms inactivity
timer for which below threshold acceleration
is required to detect inactivity
Table 43. Bit Descriptions for TIME_INACT_H
Bits Bit Name Settings Description
Reset Access
0x0 R/W
[7:0] INACT_COUNT[15:8] Customizable
by customer
Number of multiples of 32.5 ms inactivity timer for which below
threshold acceleration is required to detect inactivity. The scale factor is
32.5 ms per code for 2560 Hz ODR and values less than 2560 Hz, and the
scale factor is 16.25 ms per code for 5120 Hz ODR.
INACTIVITY TIMER REGISTER, LSB
Address: 0x31, Reset: 0x00, Name: TIME_INACT_L
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[ 7 :0 ] INACT _CO UNT [ 7 :0 ] ( R/W )
Number of multiples of 32.5 ms inactivity
timer for which below threshold acceleration
is required to detect inactivity
Table 44. Bit Descriptions for TIME_INACT_L
Bits Bit Name Settings
Description
Reset Access
0x0 R/W
[7:0] INACT_COUNT[7:0] Customizable by
customer
Number of multiples of 32.5 ms inactivity timer for which below
threshold acceleration is required to detect inactivity.
Rev. A | Page 40 of 52
Data Sheet
ADXL373
X-AXIS MOTION WARNING THRESHOLD REGISTER, MSB
Address: 0x32, Reset: 0x00, Name: THRESH_ACT2_X_H
This 11-bit unsigned value sets the threshold for motion detection. This value is set in codes, and the scale factor is 100 mg/code. To
detect motion, the absolute value of the 12-bit acceleration data is compared with the 11-bit (unsigned) ACTIVITY2 threshold value. The
THRESH_ACT2_X_L register contains the LSBs, and the THRESH_ACT2_X_H register contains the MSB of the ACTIVITY2 threshold
value.
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7 :0 ] THRESH_ACT2 _X[1 0 :3 ] (R/W )
OTN Threshold.
Table 45. Bit Descriptions for THRESH_ACT2_X_H
Bits Bit Name Settings Description
Reset Access
[7:0] THRESH_ACT2_X[10:3] Customizable by
customer
Other threshold notification (OTN) Threshold. The 8 MSBs of the x-axis 0x0
threshold for motion warning interrupt.
R/W
X-AXIS OF MOTION WARNING NOTIFICATION REGISTER, LSB
Address: 0x33, Reset: 0x00, Name: THRESH_ACT2_X_L
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
1
[7:5] THRESH_ACT2_X[2:0] (R/W)
OTN Threshold.
[0] ACT2_X_EN (R/W)
X-axis ACT2 enable.
0: X-axis ignored
1: X-axis used
[4:2] RESERVED
[1] ACT2_REF (R/W)
Selects referenced or absolute over threshold
notification processing.
0: Referenced activity processing.
1: Absolute activity processing
Table 46. Bit Descriptions for THRESH_ACT2_X_L
Bits Bit Name Settings Description
Reset Access
[7:5] THRESH_ACT2_X[2:0] Customizable by
customer
OTN Threshold. The 3 LSBs of the x-axis threshold for motion
warning interrupt.
0x0
R/W
[4:2] RESERVED
Not applicable
Reserved.
0x0
0x0
R
1
ACT2_REF
Selects referenced or absolute over threshold notification processing.
Referenced activity processing.
Absolute activity processing.
R/W
1
0
0
ACT2_X_EN
X-axis ACTIVITY2 (ACT2) enable. When set to 1, the x-axis
participates in motion warning notification detection.
0x0
R/W
0
1
X-axis ignored.
X-axis used.
Rev. A | Page 41 of 52
ADXL373
Data Sheet
Y-AXIS MOTION WARNING NOTIFICATION THRESHOLD REGISTER, MSB
Address: 0x34, Reset: 0x00, Name: THRESH_ACT2_Y_H
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7 :0 ] THRESH_ACT2 _Y[1 0 :3 ] (R/W )
OTN Threshold.
Table 47. Bit Descriptions for THRESH_ACT2_Y_H
Bits Bit Name Settings
Description
Reset Access
[7:0] THRESH_ACT2_Y[10:3] Customizable by
customer
OTN Threshold. The 8 MSBs of the y-axis threshold for motion
warning interrupt.
0x0
R/W
Y-AXIS OF MOTION WARNING NOTIFICATION REGISTER, LSB
Address: 0x35, Reset: 0x00, Name: THRESH_ACT2_Y_L
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
1
[7:5] THRESH_ACT2_Y[2:0] (R/W)
OTN Threshold.
[0] ACT2_Y_EN (R/W)
Y-axis ACT2 enable.
0: Y-axis ignored
1: Y-axis used
[4:1] RESERVED
Table 48. Bit Descriptions for THRESH_ACT2_Y_L
Bits Bit Name
Settings
Description
Reset Access
[7:5] THRESH_ACT2_Y[2:0] Customizable by
customer
OTN Threshold. The 3 LSBs of the y-axis threshold for motion
warning interrupt.
0x0
R/W
[4:1] RESERVED
ACT2_Y_EN
Not applicable
Reserved.
0x0
0x0
R
0
Y-axis ACT2 enable. When the value is 1, the y-axis participates in
motion warning notification detection.
R/W
0
1
Y-axis ignored.
Y-axis used.
Z-AXIS MOTION WARNING NOTIFICATION THRESHOLD REGISTER, MSB
Address: 0x36, Reset: 0x00, Name: THRESH_ACT2_Z_H
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7 :0 ] THRESH_ACT2 _Z[1 0 :3 ] (R/W )
OTN Threshold.
Table 49. Bit Descriptions for THRESH_ACT2_Z_H
Bits Bit Name Settings
Description
Reset Access
0x0 R/W
[7:0] THRESH_ACT2_Z[10:3] Customizable by
customer
OTN Threshold. The 8 MSBs of the z-axis threshold for motion
warning interrupt.
Rev. A | Page 42 of 52
Data Sheet
ADXL373
Z-AXIS MOTION WARNING NOTIFICATION REGISTER, LSB
Address: 0x37, Reset: 0x00, Name: THRESH_ACT2_Z_L
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
1
[7:5] THRESH_ACT2_Z[2:0] (R/W)
OTN Threshold.
[0] ACT2_Z_EN (R/W)
Z-axis ACT2 enable.
0: Z-axis ignored
1: Z-axis used
[4:1] RESERVED
Table 50. Bit Descriptions for THRESH_ACT2_Z_L
Bits Bit Name
Settings
Description
Reset Access
[7:5] THRESH_ACT2_Z[2:0] Customizable by
customer
OTN Threshold. The 3 LSBs of the z-axis threshold for motion
warning interrupt.
0x0
R/W
[4:1] RESERVED
ACT2_Z_EN
Not applicable
Reserved.
0x0
0x0
R
0
Z-axis ACT2 enable. When the value is 1, the z-axis participates in
motion warning notification detection.
R/W
0
1
Z-axis ignored.
Z-axis used.
HIGH-PASS FILTER SETTINGS REGISTER
Address: 0x38, Reset: 0x00, Name: HPF
Use this register to specify parameters for the internal high-pass filter.
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:2 ] RESERVED
[1:0 ] HPF_CORNER (R/W )
High-Pass Filter Corner Frequency Selection.
00: High Pass Filter Corner 0.
01: High Pass Filter Corner 1.
10: High Pass Filter Corner 2.
11: High Pass Filter Corner 3.
Table 51. Bit Descriptions for HPF
Bits Bit Name
[7:2] RESERVED
[1:0] HPF_CORNER
Settings
Description
Reset Access
Not applicable Reserved.
0x0
0x0
R
High-Pass Filter Corner Frequency Selection.
R/W
00 High-Pass Filter Corner 0. At ODR 5120 Hz = 30.48 Hz, at ODR 2560 Hz = 15.24 Hz, at
ODR 1280 Hz = 7.61 Hz, at ODR 640 Hz = 3.81 Hz, and at ODR 320 Hz = 1.90 Hz.
01 High-Pass Filter Corner 1. At ODR 5120 Hz = 15.58 Hz, at ODR 2560 Hz = 7.79 Hz, at
ODR 1280 Hz = 3.89 Hz, at ODR 640 Hz = 1.94 Hz, and at ODR 320 Hz = 0.97 Hz.
10 High-Pass Filter Corner 2. At ODR 5120 Hz = 7.88 Hz, at ODR 2560 Hz = 3.94 Hz, at
ODR 1280 Hz = 1.97 Hz, at ODR 640 Hz = 0.98 Hz, and at ODR 320 Hz = 0.49 Hz.
11 High-Pass Filter Corner 3. At ODR 5120 Hz = 3.96 Hz, at ODR 2560 Hz = 1.98 Hz, at
ODR 1280 Hz = 0.99 Hz, at ODR 640 Hz = 0.49 Hz, and at ODR 320 Hz = 0.24 Hz.
Rev. A | Page 43 of 52
ADXL373
Data Sheet
INTERRUPT PIN FUNCTION MAP REGISTERS
Address: 0x3B, Reset: 0x00, Name: INT1_MAP
The INT1_MAP register and INT2_MAP register configure the INT1 pin and INT2 t pin, respectively. Bits[6:0] select which function(s)
generate an interrupt on the pin. If the corresponding bit is set to 1, the function generates an interrupt on the INTx pin. Bit B7
configures whether the pin operates in active high (B7 low) or active low (B7 high) mode. Any number of functions can be selected
simultaneously for each pin. If multiple functions are selected, their conditions are OR'ed together to determine the INTx pin state. The
status of each function can be determined by reading the STATUS register. If no interrupts are mapped to an INTx pin, the pin remains in
a high impedance state.
Table 52. Bit Descriptions for INT1_MAP
Bits
Bit Name
Settings
Description
Reset
0x0
0x0
0x0
0x0
0x0
0x0
Access
R/W
R/W
R/W
R/W
R
7
INT1_LOW
Configures INT1 for active low operation.
Map awake interrupt onto INT1.
Map activity interrupt onto INT1.
Map inactivity interrupt onto INT1.
Reserved.
6
AWAKE_INT1
ACT_INT1
5
4
INACT_INT1
RESERVED
[3:1]
0
DATA_RDY_INT1
Map data ready interrupt onto INT1.
R/W
INT2 Function Map Register
Address: 0x3C, Reset: 0x00, Name: INT2_MAP
Table 53. Bit Descriptions for INT2_MAP
Bits
Bit Name
Settings
Description
Reset
Access
R/W
R/W
R/W
R/W
R
7
INT2_LOW
Configures INT2 for active low operation.
Map awake interrupt onto INT2.
Map activity 2 interrupt onto INT2.
Map inactivity interrupt onto INT2.
Reserved.
0x0
0x0
0x0
0x0
0x0
0x0
6
AWAKE_INT2
ACT2_INT2
INACT_INT2
RESERVED
5
4
[3:1
0
DATA_RDY_INT2
Map data ready interrupt onto INT2.
R/W
Rev. A | Page 44 of 52
Data Sheet
ADXL373
EXTERNAL TIMING CONTROL REGISTER
Address: 0x3D, Reset: 0x00, Name: TIMING
Use this register to control the ADXL373 timing parameters: ODR and external timing triggers.
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:5] ODR (R/W)
[0] EXT_SYNC (R/W)
Output Data Rate.
Enable external trigger.
000: 320 Hz ODR
001: 640 Hz ODR
010: 1280 Hz ODR
011: 2560 Hz ODR
100: 5120 Hz ODR
[1] EXT_CLK (R/W)
Enable external clock.
[4:2] WAKEUP_RATE (R/W)
Timer Rate for Wake-up Mode.
0: 65 ms
1: 130 ms
10: 260 ms
11: 640 ms
100: 2560 ms
101: 5120 ms
110: 10240 ms
111: 30720 ms
Table 54. Bit Descriptions for TIMING
Bits
Bit Name
Settings
Description
Output Data Rate.
Reset
Access
[7:5]
ODR
0x0
R/W
000 320 Hz ODR.
001 640 Hz ODR.
010 1280 Hz ODR.
011 2560 Hz ODR.
100 5120 Hz ODR.
[4:2]
WAKEUP_RATE
Timer rate for wake-up mode.
65 ms.
130 ms.
0x0
R/W
0
1
10 260 ms.
11 640 ms.
100 2560 ms.
101 5120 ms.
110 10,240 ms.
111 30,720 ms.
1
0
EXT_CLK
Customizable by customer
Customizable by customer
Enable external clock.
Enable external trigger.
0x0
0x0
R/W
R/W
EXT_SYNC
Rev. A | Page 45 of 52
ADXL373
Data Sheet
MEASUREMENT CONTROL REGISTER
Address: 0x3E, Reset: 0x00, Name: MEASURE
Use this register to control several measurement settings.
Table 55. Bit Descriptions for MEASURE
Bits Bit Name
Settings
Description
Reset Access
7
USER_OR_DISABLE Customizable
by customer
User overrange disable.
0x0
R/W
6
AUTOSLEEP
Customizable
by customer
Autosleep. When set to 1, autosleep is enabled, and the device enters
wake-up mode automatically upon detection of inactivity. Activity and
inactivity detection must be in linked mode or loop mode (the
LINKLOOP bits in the MEASURE register) to enable autosleep. Otherwise,
the bit is ignored.
0x0
R/W
[5:4] LINKLOOP
Link/loop activity processing. These bits select how activity and
inactivity processing are linked.
0x0
R/W
0
1
Default mode. Activity and inactivity detection, when enabled, operate
simultaneously and their interrupts (if mapped) must be acknowledged
by the host processor by reading the STATUS register. Autosleep is
disabled in this mode.
Linked mode. Activity and inactivity detection are linked sequentially so
that only one is enabled at a time. Their interrupts (if mapped) must be
acknowledged by the host processor by reading the STATUS register.
10 Looped mode. Activity and inactivity detection are linked sequentially
so that only one is enabled at a time. Their interrupts are internally
acknowledged (do not need to be serviced by the host processor). To
use either linked or looped mode, both ACT_x_EN and INACT_x_EN
must be set to 1. Otherwise, the default mode is used. For additional
information, refer to the Linking Activity and Inactivity Detection section.
3
LOW_NOISE
Low Noise. Selects low noise operation.
0x0
0x0
R/W
R/W
0
1
Normal operation. Device operates at the normal noise level and
ultralow current consumption
Low noise operation. Device operates at ~1/3 the normal noise level.
[2:0] BANDWIDTH
Bandwidth. Select the desired output signal bandwidth. A four-pole
low-pass filter at the selected frequency limits the signal bandwidth.
000 160 Hz bandwidth.
001 320 Hz bandwidth.
010 640 Hz bandwidth.
011 1280 Hz bandwidth.
100 2560 Hz bandwidth.
Rev. A | Page 46 of 52
Data Sheet
ADXL373
POWER CONTROL REGISTER
Address: 0x3F, Reset: 0x00, Name: POWER_CTL
Table 56. Bit Descriptions for POWER_CTL
Bits Bit Name
Settings
Description
Reset Access
7
I2C_HSM_EN
Customizable by
customer
I2C Speed Select. 1 = high speed mode.
0x0
R/W
6
5
RESERVED
Not applicable
Reserved.
0x0
0x0
R
INSTANT_ON_THRESH
User Selectable Instant On Threshold. 0 = low threshold, and 1 =
high threshold.
R/W
0
1
Selects the low instant on threshold.
Selects the high instant on threshold.
4
FILTER_SETTLE
User Selectable Filter Settling Period. 0 = 370 ms settle period, 0x0
and 1 = 16 ms settle period.
R/W
0
1
1
1
Filter settling set to 462.5 ms.
Filter settling set to 4/ODR. Ideal for when the filters are disabled.
3
2
LPF_DISABLE
HPF_DISABLE
Disables the low-pass filter.
Disables the digital high-pass filter.
Mode of Operation.
0x0
0x0
0x0
R/W
R/W
R/W
[1:0] MODE
11 Full bandwidth measurement mode.
10 Instant on mode.
01 Wake-up mode.
00 Standby.
Rev. A | Page 47 of 52
ADXL373
Data Sheet
SELF TEST REGISTER
Address: 0x40, Reset: 0x00, Name: SELF_TEST
Refer to the Self Test section for information on the operation of the self test feature, and see the Self Test Procedure section for guidelines
on how to use this functionality.
Table 57. Bit Descriptions for SELF_TEST
Bits
[7:2]
1
Bit Name
RESERVED
ST_DONE
ST
Settings
Description
Reset
0x0
Access
Reserved.
R
Self test finished.
0x0
R
0
Self test. Writing a 1 to this bit initiates self test. Writing a 0 clears self test.
0x0
R/W1
RESET (CLEARS) REGISTER, DEVICE IN STANDBY MODE
Address: 0x41, Reset: 0x00, Name: RESET
Table 58. Bit Descriptions for RESET
Bits
Bit Name
Settings
Description
Reset
0x0
Access
[7:0]
RESET
Customizable by customer
Writing code 0x52 resets the device.
W
Rev. A | Page 48 of 52
Data Sheet
ADXL373
APPLICATIONS INFORMATION
VS Supply Start-Up Threshold
APPLICATIONS EXAMPLES
This section includes application circuits, highlighting useful
features of the ADXL373.
During start-up or power cycling of the ADXL373, the VS supply
must always be started up from less than 100 mV. When the
device is in operation, any time power is removed from the
ADXL373 or falls less than 1.6 V, the VS supply must be discharged
lower than 100 mV. The VS supply start-up threshold specification
is a mandatory requirement.
Power Supply Decoupling
Figure 50 shows the recommended bypass capacitors for use
with the ADXL373.
V
V
S
DD I/O
Hold Time
C
C
IO
S
To ensure a successful power-on reset, the VS supply must be
held less than 100 mV for at least 200 ms before reapplying the
supply to the device.
V
V
S
DD I/O
ADXL373
MOSI
MISO
SCLK
CS
INT1
INT2
SPI
INTERFACE
INTERRUPT
CONTROL
Rise Time
GND
For the worst case scenario (a 100 mV at Vs start up and a
200 ms hold time), the VS supply rise time must be linear and
within 250 µs to reach 1.6 V (see Figure 51).
Figure 50. Recommended Bypass Capacitors
V
S
3.3V
A 0.1 µF ceramic capacitor (CS) at VS and a 0.1 µF ceramic
capacitor (CIO) at VDD I/O placed as close as possible to the
ADXL373 supply pins is recommended to adequately
decouple the accelerometer from noise on the power supply.
It is recommended that VS and VDD I/O be separate supplies to
minimize digital clocking noise on the VS supply. If separation
of the supplies is not possible, additional filtering of the supplies
may be necessary.
≤250µs
1.6V
If additional decoupling is necessary, a resistor or ferrite
bead no larger than 100 Ω in series with VS is recommended.
Additionally, increasing the bypass capacitance on VS to a 1 µF
tantalum capacitor in parallel with a 0.1 µF ceramic capacitor
can also improve noise.
0.1V
0V
≥200ms
Figure 51. Power Supply Requirements
Notice that fully discharging the power supply to the ground
level allows a much more relaxed rise time, ≤ 600 µs, from 0 V
to 1.6 V for a 200 ms hold time.
Ensure that the connection from the ADXL373 ground to
the power supply ground has low impedance because noise
transmitted through ground has an effect similar to noise
transmitted through VS.
To enable supply discharge, it is recommended to power the
device from a microcontroller general-purpose input and output
(GPIO), connect a shutdown discharge switch to the supply, or
use a voltage regulator with a shutdown discharge feature.
Power Supply Requirements
The ADXL373 operates using supply voltage rails ranging from
1.6 V to 3.5 V. The operating voltage range (VS) specified in
Table 1 ranges from 1.6 V to 3.5 V to account for inaccuracies
and transients of up to 10% on the supply voltage.
When power cycling the ADXL373, it is highly recommended
to fully discharge the device to ground level (Vs = 0 V) on each
power cycle. If this is not possible, care must be taken regarding
the following specifications:
•
•
•
VS supply start-up threshold
Hold time
Rise time
Rev. A | Page 49 of 52
ADXL373
Data Sheet
Using External Timing Triggers
OPERATION AT VOLTAGES OTHER THAN 2.5 V
Figure 52 shows an application diagram for using the INT1 pin
as the input for an external clock. In this mode, the external
clock determines all accelerometer timing, including the output
data rate and bandwidth. Set the EXT_CLK bit in the TIMING
register to enable external clock functionality.
The ADXL373 is tested and specified at a supply voltage of VS =
2.5 V. However, the ADXL373 can be powered with a VS as high
as 3.5 V or as low as 1.6 V. Some performance parameters
change as the supply voltage changes, including the supply
current, noise, offset, and sensitivity.
V
V
S
DD I/O
OPERATION AT TEMPERATURES OTHER THAN
AMBIENT
C
C
IO
S
V
V
The ADXL373 is tested and specified at an ambient temperature.
However, it is rated for temperatures between −40°C and +105°C.
Some performance parameters change along with temperature,
such as offset, sensitivity, clock performance, and current. Some
of these temperature variations are characterized in Table 1, and
others are shown in the figures within the Typical Performance
Characteristics section.
S
DD I/O
ADXL373
MOSI
EXTERNAL
CONTROL
INT1
INT2
MISO
SCLK
CS
SPI
INTERFACE
INTERRUPT
CONTROL
GND
Figure 52. INT1 Pin as Input for External Clock
Figure 53 shows an application diagram for using the INT2 pin
as a trigger for synchronized sampling. Acceleration samples are
produced every time this trigger is activated. Set the
MECHANICAL CONSIDERATIONS FOR MOUNTING
Mount the ADXL373 on the PCB in a location close to a hard
mounting point of the PCB to the case. Mounting the ADXL373
at an unsupported PCB location, as shown in Figure 54, can
result in large, apparent measurement errors due to undamped
PCB vibration. Locating the accelerometer near a hard mounting
point ensures that any PCB vibration at the accelerometer is
higher than the mechanical sensor resonant frequency of the
accelerometer and, therefore, effectively invisible to the
accelerometer. Multiple mounting points close to the sensor or a
thicker PCB also help to reduce the effect of system resonance
on the performance of the sensor.
EXT_SYNC bit in the TIMING register to enable this feature.
V
V
S
DD I/O
C
C
IO
S
V
V
S
DD I/O
ADXL373
MOSI
MISO
SCLK
CS
INTERRUPT
CONTROL
SAMPLING
TRIGGER
INT1
INT2
SPI
INTERFACE
GND
ACCELEROMETERS
Figure 53. Using the INT2 Pin to Trigger Synchronized Sampling
PCB
MOUNTING POINTS
Figure 54. Incorrectly Placed Accelerometers
Rev. A | Page 50 of 52
Data Sheet
ADXL373
AXES OF ACCELERATION SENSITIVITY
A
Z
A
Y
A
X
Figure 55. Axes of Acceleration Sensitivity (Corresponding Output Increases when Accelerated Along the Sensitive Axis)
X
Y
Z
= 1g
= 0g
= 0g
OUT
OUT
OUT
TOP
GRAVITY
X
Y
Z
= 0g
= –1g
= 0g
X
Y
Z
= 0g
= 1g
= 0g
OUT
OUT
OUT
OUT
OUT
OUT
T O P
X
Y
Z
= 0g
= 0g
= 1g
X
Y
Z
= 0g
= 0g
= –1g
OUT
OUT
OUT
OUT
OUT
OUT
X
Y
Z
= –1g
= 0g
= 0g
OUT
OUT
OUT
Figure 56. Output Response vs. Orientation to Gravity
0.9250
0.3000
3.3500
0.5000
0.8000
3.500
Figure 57. Recommended Printed Wiring Board Land Pattern
(Dimensions Shown in Millimeters)
Rev. A | Page 51 of 52
ADXL373
Data Sheet
OUTLINE DIMENSIONS
3.35
3.25
3.15
0.25 × 0.35
1.00
REF
REF
PIN 1
INDICATOR
AREA
PIN 1
INDICATOR
0.10
REF
13
1
0.50
BSC
14
16
6
3.10
3.00
2.90
0.375
REF
0.475 × 0.25
REF
8
5
9
BOTTOM VIEW
TOP VIEW
SIDE VIEW
0.3375
REF
1.14
1.06
1.00
SEATING
PLANE
Figure 58. 16-Terminal Land Grid Array [LGA]
(CC-16-4)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
−40°C to +105°C
−40°C to +105°C
Package Description
Package Option
CC-16-4
CC-16-4
Ordering Quantity
4,000
1,000
ADXL373BCCZ-RL
ADXL373BCCZ-RL7
EVAL-ADXL373Z
16-Terminal Land Grid Array [LGA]
16-Terminal Land Grid Array [LGA]
Evaluation Board
1 Z = RoHS Compliant Part.
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
©2021 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D17210-4/21(A)
Rev. A | Page 52 of 52
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