AN-1026中文资料_数据手册_规格书

AN-1026

APPLICATION NOTE

One Technology Way • P. O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com

High Speed Differential ADC Driver Design Considerations

by John Ardizzoni and Jonathan Pearson

For the discussions that follow, some definitions are in order.

If the input signal is balanced, V_IPand V_INare nominally equal

in amplitude and opposite in phase with respect to a common

reference voltage. When the input is single-ended, one input is

at a fixed voltage, and the other varies with respect to it. In either

case, the input signal is defined as V_IP– V_IN.

INTRODUCTION

Most modern high performance ADCs use differential inputs to

reject common-mode noise and interference, increase dynamic

range by a factor of 2, and improve overall performance due to

balanced signaling. Though ADCs with differential inputs can

accept single-ended input signals, optimum ADC performance

is achieved when the input signal is differential. ADC drivers—

circuits often specifically designed to provide such signals—perform

many important functions, including amplitude scaling, single-

ended-to-differential conversion, buffering, common-mode offset

adjustment, and filtering. Since the introduction of the AD8138,

differential ADC drivers have become essential signal conditioning

elements in data acquisition systems.

The differential-mode input voltage, V_{IN, dm}, and the common-

mode input voltage, V_{IN, cm}, are defined in Equation 1 and

Equation 2.

V

_{IN, dm}= V_IP– V_IN

(1)

V_IP+V_IN

V_{IN, cm}

=

(2)

2

This common-mode definition is intuitive when applied to

balanced inputs, but it is also valid for single-ended inputs.

R

F1

R

G1

V

A

+

V

IP

V

–

ON

The output also has a differential mode and a common mode,

defined in Equation 3 and Equation 4.

V

IN, dm

OCM

OUT, dm

–

V

+

IN

OP

V

R

A

G2

R

F2

V_{OUT, dm}= V_OP– V_ON

V_OP+V_ON

(3)

Figure 1. Differential Amplifier

V_{OUT, cm}

=

(4)

A basic fully differential voltage-feedback ADC driver is shown

in Figure 1. Two differences from a traditional op-amp feedback

circuit can be seen. The differential ADC driver has an additional

output terminal (V_ON) and an additional input terminal (V_OCM).

These terminals provide great flexibility when interfacing

signals to ADCs that have differential inputs.

2

Note the difference between the actual output common-mode

voltage, V_{OUT, cm}, and the V_OCMinput terminal, which establishes

the output common-mode level.

The analysis of differential ADC drivers is considerably more

complex than that of traditional op amps. To simplify the algebra, it

is expedient to define two feedback factors, β1 and β2, as given

in Equation 5 and Equation 6.

Instead of a single-ended output, the differential ADC driver

produces a balanced differential output, with respect to V_OCM

,

between V_OPand V_ON. (P indicates positive and N indicates

negative.) The V_OCMinput controls the output common-mode

voltage. As long as the inputs and outputs stay within their

specified limits, the output common-mode voltage must equal

the voltage applied to the V_OCMinput. Negative feedback and

high open-loop gain cause the voltages at the amplifier input

terminals, V_A+ and V_A–, to be essentially equal.

R_G1

_F1+ R_G1

β₁=

β₂=

(5)

(6)

R

R_G2

_F2+ R_G2

R

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

AN-1026

APPLICATION NOTE

TABLE OF CONTENTS

Introduction ...................................................................................... 1

Noise ...............................................................................................7

Supply Voltage ...............................................................................9

Harmonic Distortion ................................................................. 10

Bandwidth and Slew Rate.......................................................... 11

Stability ........................................................................................ 11

PC Board Layout ........................................................................ 12

Revision History ............................................................................... 2

Terminating the Input to an ADC Driver................................. 3

Input Common-Mode Voltage Range (ICMVR)......................... 5

Input and Output Coupling: AC or DC .................................... 6

Output Swing ................................................................................ 7

REVISION HISTORY

11/09—Revision 0: Initial Version

Rev. 0 | Page 2 of 16

APPLICATION NOTE

AN-1026

In most ADC driving applications, β₁= β₂, but the general closed-

loop equation for V_{OUT, dm}, in terms of V_IP, V_IN, V_OCM, β₁, and β₂, is

useful to gain insight into how beta mismatch affects performance.

The equation for V_{OUT, dm}, shown in Equation 7, includes the finite

frequency-dependent, open-loop voltage gain of the amplifier, A(s).

TERMINATING THE INPUT TO AN ADC DRIVER

ADC drivers are frequently used in systems that process high

speed signals. Devices separated by more than a small fraction

of a signal wavelength must be connected by electrical transmission

lines with controlled impedance to avoid losing signal integrity.

Optimum performance is achieved when a transmission line is

terminated at both ends in its characteristic impedance. The driver

is generally placed close to the ADC, so controlled-impedance

connections are not required between them; however, the incoming

signal connection to the ADC driver input is often long enough

to require a controlled-impedance connection, terminated in

the proper resistance.

⎡

⎢

⎤

⎥

⎡

⎢

⎣

⎤

⎥

⎦

(

β₁− β₂

)

1+

+V_IP

(

1− β₁

)

−V_IN

(

1− β₂

)

2

V_OCM

V_OUT,dm

=

(7)

2

β₁+ β₂

A

(

s

)

(

β₁+ β₂

)

⎢

⎥

⎣

⎦

When β₁≠ β₂, the differential output voltage depends on V_OCM

,

which is an undesirable outcome because it produces an offset and

excess noise in the differential output. The gain bandwidth product

of the voltage-feedback architecture is constant. Interestingly,

the gain in the gain bandwidth product is the reciprocal of the

averages of the two feedback factors.

The input resistance of the ADC driver, whether differential or

single-ended, must be greater than or equal to the desired

termination resistance so that a termination resistor, R_T, can be

added in parallel with the amplifier input to achieve the required

resistance. All ADC drivers in the examples considered here are

designed to have balanced feedback ratios, as shown in Figure 2.

When β₁= β₂≡ β, Equation 7 reduces to Equation 8.

⎡

⎢

⎤

⎥

V_{OUT, dm}

⎡

⎢

⎣

⎤

⎥

⎦

R

R_F

R_G

1

F

=

(8)

1

R

G

V_{IN, dm}

1 +

A(s)

(β

)

⎢

⎥

⎣

⎦

R

V

OCM

IN, dm

This is a more familiar-looking expression; the ideal closed-loop

R

G

R

gain becomes simply R_F/R_Gwhen A(s) → ∞ . The gain bandwidth

product is also more familiar looking, with the noise gain equal

to 1/β, just as with a traditional op amp.

F

Figure 2. Differential Amplifier Input Impedance

Because the voltage between the two amplifier inputs is driven

to a null by negative feedback, they are virtually connected, and

the differential input resistance, R_IN, is simply 2 × R_G. To match

the transmission line resistance, R_L, place resistor, R_T, as calculated

in Equation 11, across the differential input. Figure 3 shows

typical resistances R_F= R_G= 200 Ω, desired R_{L, dm}= 100 Ω, and

R_T= 133 Ω.

The ideal closed-loop gain for a differential ADC driver with

matched feedback factors is seen in Equation 9.

V_{OUT, dm}

R_F

A_V=

=

(9)

V_{IN, dm}

R_G

Output balance, an important performance metric for differential

ADC drivers, has two components: amplitude balance and phase

balance. Amplitude balance is a measure of how closely the two

outputs are matched in amplitude; in an ideal amplifier, they are

exactly matched. Output phase balance is a measure of how close

the phase difference between the two outputs is to 180°. Any

imbalance in output amplitude or phase produces an undesirable

common-mode component in the output. The output balance

error (Equation 10) is the log ratio of the output common-mode

voltage produced by a differential input signal to the output

differential-mode voltage produced by the same input signal,

expressed in decibels.

1

R_T=

(11)

1

−

R_LR_IN

200Ω

R

= 100Ω

V

R

L, dm

OCM

T

200Ω

1

R

=

= 133Ω

T

1

−

100Ω

400Ω

⎡

⎢

⎤

⎥

ΔV_{OUT, cm}

Figure 3. Matching a 100 Ω Line

Output Balance Error = 20log₁₀

(10)

ΔV

⎢

⎣

⎥

⎦

OUT, dm

An internal common-mode feedback loop forces V_{OUT, cm}to

equal the voltage applied to the V_OCMinput, producing excellent

output balance.

Rev. 0 | Page 3 of 16

AN-1026

APPLICATION NOTE

Terminating a single-ended input requires significantly more

effort. Figure 4 illustrates how an ADC driver operates with a

single-ended input and a differential output.

3.5V

In Figure 5, a single-ended-to-differential gain of 1, a 50 Ω

input termination, and feedback and gain resistors with values

in the neighborhood of 200 Ω are required to keep noise low.

267Ω

200Ω

V

ON

2.5V

–

V

+

V

2.5V

OCM

OUT, dm

1.5V

R

F

V

OP

500Ω

200Ω

2V

200Ω

R

G

500Ω

V

Figure 5. Single-Ended Input Impedance

ON

V

–

V

+

IN

V

2.5V

OCM

0V

OUT, dm

Equation 12 provides the single-ended input resistance, 267 Ω.

Equation 13 indicates that the parallel resistance, R_T, should be

61.5 Ω to bring the 267 Ω input resistance down to 50 Ω.

V

OP

R

G

500Ω

–2V

R

F

500Ω 3.5V

1.75V

1

R_T=

= 61.5

(13)

1.25V

0.75V

2.5V

1

−

50ꢀ 267ꢀ

1.5V

Figure 4. Example of Single-Ended Input to ADC Driver

Figure 6 shows the circuit with source and termination resistances.

The open-circuit voltage of the source, with its 50 Ω source

resistance, is 2 V p-p. When the source is terminated in 50 Ω,

the input voltage is reduced to 1 V p-p, which is also the

differential output voltage of the unity-gain driver.

200Ω

Although the input is single-ended, V_{IN, dm}is equal to V_IN.

Because resistors R_Fand R_Gare equal and balanced, the gain

is unity, and the differential output, V_OP− V_ON, is equal to the

input, that is, 4 V p-p. V_{OUT, cm}is equal to V_OCM= 2.5 V and,

from the lower feedback circuit, input voltages V_A+and V_A−

are equal to V_OP/2.

50Ω

200Ω

2.5V

V

ON

–

V

+

R

Using Equation 3 and Equation 4, V_OP= V_OCM+ V_IN/2, an in-phase

swing of 1 V about 2.5 V. V_ON= V_OCM– V_IN/2, an antiphase

swing of 1 V about 2.5 V. Thus, V_A+and V_A−swing 0.5 V

about 1.25 V. The ac component of the current that must be

supplied by V_INis (2 V – 0.5 V)/500 Ω = 3 mA, so the resistance

to ground that must be matched, looking in from V_IN, is 667 Ω.

T

V

OCM

2V p-p

OUT, dm

61.5Ω

V

OP

200Ω

Figure 6. Single-Ended Circuit with Source and Termination Resistances

This circuit may initially appear to be complete, but an unmatched

resistance of 61.5 Ω in parallel with 50 Ω has been added to the

upper R_Galone. This changes the gain and single-ended input

resistance and mismatches the feedback factors. For small gains, the

change in input resistance is small and neglected for the moment,

but the feedback factors must still be matched. The simplest way

to accomplish this is to add resistance to the lower R_G. Figure 7

shows a Thevenin equivalent circuit in which the previously

mentioned parallel combination acts as the source resistance.

The general formula for determining this single-ended input

resistance when the feedback factors of each loop are matched

is shown in Equation 12, where R_{IN, se}is the single-ended input

resistance.

⎛

⎜

⎞

⎟

R_G

R_F

R_G+ R_F

⎜

⎟

R_{IN, se}

=

(12)

1−

⎜

⎟

2×

(

)

⎝

⎠

R

TH

27.6Ω

This is a starting point for calculating the termination resistance.

However, it is important to note that amplifier gain equations

are based on the assumption of a zero impedance input source. A

significant source impedance that must be matched in the presence

of an imbalance caused by a single-ended input inherently adds

resistance only to the upper R_G. To retain the balance, this must

be matched by adding resistance to the lower R_G, but this affects

the gain.

V

TH

1.1V p-p

Figure 7. Thevenin Equivalent of Input Source

With this substitution, a 27.6 Ω resistor, R_TS, is added to the

lower loop to match loop feedback factors, as seen in Figure 8.

R

200Ω

F

R

200Ω

TH

27.6Ω

G

Although it may be possible to determine a closed-form solution to

the problem of terminating a single-ended signal, an iterative

method is generally used. The need for it will become apparent

in the following example.

V

ON

–

V

+

V

TH

1.1V p-p

V

2.5V

OCM

OUT, dm

V

OP

R

G

200Ω

TS

27.6Ω

R

F

200Ω

Figure 8. Balanced Single-Ended Termination Circuit

Rev. 0 | Page 4 of 16

APPLICATION NOTE

AN-1026

Note that the Thevenin voltage of 1.1 V p-p is larger than the

properly terminated voltage of 1 V p-p, and the gain resistors

are each increased by 27.6 Ω, decreasing the closed-loop gain.

These opposing effects tend to cancel each other out for large

resistors (>1 kΩ) and small gains (1 or 2), but are not entirely

canceled out for small resistors or higher gains.

A single iteration of the method described here works well for

closed-loop gains of 1 or 2. For higher gains, the value of R_TS

gets closer to the value of R_G, and the difference between the

value of R_{IN, se}calculated in Equation 18 and that calculated in

Equation 12 becomes greater. Several iterations are required for

these cases.

The circuit in Figure 8 is now easily analyzed, and the differential

output voltage is calculated in Equation 14.

This should not be arduous: the recently released differential

amplifier calculator tools, ADIsimDiffAmp™ and ADI Diff Amp

Calculator™, do all the heavy lifting; they perform the above

calculations in a matter of seconds. See www.analog.com for

more information.

⎛

⎜

⎝

⎞

⎟

⎠

200ꢀ

227.6ꢀ

V_OUT,dm=1.1V p - p

= 0.97 V p - p

(14)

The differential output voltage is not quite at the desired level of

1 V p-p, but a final independent gain adjustment is available by

modifying the feedback resistance as shown in Equation 15.

INPUT COMMON-MODE VOLTAGE RANGE (ICMVR)

ICMVR specifies the range of voltage that can be applied to the

differential amplifier inputs for normal operation. The voltage

appearing at those inputs can be referred to as ICMV, V_acm, or V_A.

This specification is often misunderstood. The most frequent

difficulty is determining the actual voltage at the differential

amplifier inputs, especially with respect to the input voltage.

The amplifier input voltage (V_A) can be calculated when the

variables V_{IN, cm}, β, and V_OCMare known, using the general

Equation 19 for unequal βs or the simplified Equation 20 for

equal βs.

⎛

⎜

⎝

⎞

⎟

⎠

Desired V_OUT,dm

R_F= 227.6 ꢀ

=

1.1 V p- p

(15)

⎛

⎞

1.0 V p- p

1.1 V p- p

⎜

⎝

⎟

⎠

227.6ꢀ

= 206.9 ꢀ

Figure 9 shows the completed circuit, implemented with

standard 1% resistor values.

R

205Ω

F

R

IN, se

2β₁β₂V_OCM+ V β₂

(

1− β₁

β₁+ β₂

V_OCM−V_ICM

)

+V_INβ₁(1− β₂)

IP

V_acmorV_A

=

(19)

(20)

R

±

S

G

50Ω

200Ω

V

ON

–

V

+

R

T

V_acmor V =V_{IN cm}+ β

(

)

V

2.5V

OCM

A

,

2V p-p

OUT, dm

±

61.9Ω

V

OP

Note that V_Ais always a scaled-down version of the input signal

(as shown in Figure 4). The input common-mode voltage range

differs among amplifier types. Analog Devices, Inc., high speed

differential ADC drivers have two configurations of input stages,

centered and shifted. The centered ADC drivers have about 1 V of

headroom from each supply rail (hence centered). The shifted input

stages add two transistors to allow the inputs to swing closer to

the –V_Srail. Figure 10 shows a simplified input schematic of a

typical differential amplifier (Q2 and Q3).

R

G

R

200Ω

TS

28Ω

R

F

205Ω

Figure 9. Complete Single-Ended Termination Circuit

Referring to Figure 9, the single-ended input resistance of the

driver, R_{IN, se}, has changed due to changes in R_Fand R_G. The

gain resistances of the driver are 200 Ω in the upper loop and

200 Ω + 28 Ω = 228 Ω in the lower loop. Calculation of R_{IN, se}

with differing gain resistance values first requires two values of

beta to be calculated, as shown in Equation 16 and Equation 17.

A

Q2

Q3

–IN

+IN

Q1

Q4

200ꢀ

R_F+ R_G405ꢀ

R_G

β₁=

β₂=

=

= 0.494

(16)

(17)

R_G+ R_TS

R_F+ R_G+ R_TS433ꢀ

228ꢀ

Figure 10. Simplified Differential Amplifier with Shifted ICMVR

=

= 0.527

The shifted input architecture allows the differential amplifier to

process a bipolar input signal, even when the amplifier is powered

from a single supply, making it well suited for single-supply

applications with inputs at or below ground. The additional PNP

transistors (Q1 and Q4) at the input shift the input to the differential

pair up by one transistor V_be. For example, with –0.3 V applied

at –IN, Point A is 0.7 V, allowing the differential pair to operate

properly. Without the PNPs (centered input stage), –0.3 V at

Point A would reverse-bias the NPN differential pair and halt

normal operation.

The input resistance, R_{IN, se}, is calculated as shown in Equation 18.

R_G

β₁

(

β₁+ β₂

)

= 271ꢀ

R_IN,se

=

(18)

(

β₂+ 1

)

This differs little from the original calculated value of 267 Ω

and does not have a significant effect on the calculation of R_T,

because R_{IN, se}is in parallel with R_T.

If a more exact overall gain is necessary, higher precision or

series trim resistors can be used.

Rev. 0 | Page 5 of 16

AN-1026

APPLICATION NOTE

Table 1. High Speed ADC Driver Specifications

Supply Voltage (V)

ADC Driver

Slew

ICMVR

V_OCM

Output

Swing

from

BW

Rate

Noise

I_SUPPLY

(mA)

Part No.

AD8132

AD8137

(MHz) (V/μs) (nV)

5 V

+5 V

+3.3 V

+3 V

5 V +5 V

+3.3 V

+3 V

Rails (V)

350

76

1200

450

8

–4.7 to +3

–4 to +4

0.3 to 3

1 to 4

0.3 to 1.3

1 to 2.3

0.3 to 1

1 to 2

3.6

4

1 to 3.7

1 to 4

N/A

0.3 to 1

1 to 2

1

12

8.25

1 to 2.3

Rail to

rail

3.2

AD8138

AD8139

320

410

1150

800

5

–4.7 to +3.4 0.3 to 3.2 N/A

–4 to +4 1 to 4 N/A

N/A

3.8

1 to 3.8

N/A

1.4

20

25

2.25

Rail to

rail

ADA4927-1/ 2300

ADA4927-2

5000

2800

6000

4700

6800

1.4

3.6

2.2

2.6

2.3

–3.5 to +3.5 1.3 to 3.7 N/A

–4.8 to +3.2 0.2 to 3.2 N/A

N/A

3.5

3.8

1.5 to 3.5 N/A

1.2 to 3.2 N/A

N/A

1.2

20

9

ADA4932-1/ 1000

ADA4932-2

1

ADA4937-1/ 1900

ADA4937-2

N/A

–4.7 to +3.4 0.3 to 3.4 N/A

N/A 1.1 to 3.9 0.9 to 2.4 N/A

0.3 to 3

0.3 to 1.2 N/A

N/A

3.7

1.2 to 3.8 1.2 to 2.1 N/A

1.3 to 3.7 N/A N/A

1.3 to 3.5 1.3 to 1.9 N/A

0.9

1.2

0.8

40

37

ADA4938-1/ 1000

ADA4938-2

N/A

ADA4939-1/ 1400

ADA4939-2

N/A

AC-coupled, single-ended-to-differential applications are similar to

their differential-input counterparts but have common-mode

ripple, a scaled-down replica of the input signal, at the amplifier

input terminals. An ADC driver with a centered input common-

mode range places the average input common-mode voltage

near the middle of its specified range, providing plenty of

margin for the ripple in most applications.

Table 1 provides a quick reference to many specifications of

Analog Devices ADC drivers, including which drivers feature a

shifted ICMVR and which do not.

INPUT AND OUTPUT COUPLING: AC OR DC

The need for ac or dc coupling can have a significant impact on

the choice of a differential ADC driver. The considerations

differ between input and output coupling.

When input coupling is optional, it is worth noting that ADC

drivers with ac-coupled inputs dissipate less power than similar

drivers with dc-coupled inputs because no dc common-mode

current flows in either feedback loop.

An ac-coupled input stage is illustrated in Figure 11.

R

F

C

IN

R

G

AC coupling the ADC driver outputs is useful when the ADC

requires an input common-mode voltage that differs substantially

from that available at the output of the driver. The drivers have

maximum output swing when V_OCMis set near midsupply; this

presents a problem when driving low voltage ADCs with very

low input common-mode voltage requirements. A simple solution

to this predicament is to ac-couple the connection between the

driver output and the ADC input (see Figure 12), removing the

dc common-mode voltage of the ADC from the driver output

and allowing a common-mode level suitable for the ADC to be

applied on its side of the ac coupling. For example, the driver

could be running on a single 5 V supply with V_OCM= 2.5 V and

the ADC could be running on a single 1.8 V supply with a required

input common-mode voltage of 0.9 V applied at ADC CMV.

V

OCM

R

C

G

IN

R

F

Figure 11. AC-Coupled ADC Driver

For differential-to-differential applications with ac-coupled inputs,

the dc common-mode voltage appearing at the amplifier input

terminals is equal to the dc output common-mode voltage

because dc feedback current is blocked by the input capacitors.

Also, the feedback factors at dc are matched and exactly equal to

unity. V_OCM, and consequently the dc input common mode, is very

often set near midsupply. An ADC driver with a centered input

common-mode range works well in these types of applications,

with the input common-mode voltage near the center of its

specified range.

R

F

C

OUT

R

G

R

OUT

ADC

CMV

TO

ADC

V

OCM

R

G

C

OUT

R

F

Figure 12. DC-Coupled Inputs with AC-Coupled Outputs

Rev. 0 | Page 6 of 16

APPLICATION NOTE

AN-1026

–20

–30

Drivers with shifted input common-mode ranges generally

work best in dc-coupled systems operating on single supplies.

This is because the output common-mode voltage is divided

down through the feedback loops, and its variable components

can get close to ground, which is the negative rail. With single-

ended inputs, the input common-mode voltage gets even closer

to the negative rail due to the input-related ripple.

V

= 2V p-p

OUT

–40

HD2 @ 10MHz

HD3 @ 10MHz

HD2 @ 30MHz

HD3 @ 30MHz

–50

–60

–70

–80

Systems running on dual supplies, with single-ended or differential

inputs and ac coupling or dc coupling, usually work well with either

type of input stage because of the increased headroom.

–90

–100

–110

–120

Table 2 summarizes the most common ADC driver input

stage types used with various input coupling and power supply

combinations. However, these choices may not always be the

best; each system should be analyzed on a case-by-case basis.

1.4

1.6

1.8

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

V

(V)

OCM

Figure 13. Harmonic Distortion vs. V_OCMat Various Frequencies for the

ADA4932 with a 5 V Supply

Table 2. Coupling and Input Stage Options

Figure 13 shows harmonic distortion vs. V_OCMat various

frequencies for the ADA4932, which is specified with

a typical output swing to within 1.2 V of each rail (headroom).

The output swing is the sum of V_OCMand V_PEAKof the signal (1 V).

Note that the distortion starts to accelerate above 2.8 V

(3.8 V_PEAK, or 1.2 V below the 5 V rail). At the low end,

distortion is still low at 2.2 V (–1 V_PEAK). The same type of

behavior appears in the discussions of bandwidth and slew rate.

Input Coupling Input Signal Power Supplies Input Type

Any

AC

DC

AC

DC

Any

Dual

Either

Centered

Shifted

Centered

Single-ended Single

Differential

Single

OUTPUT SWING

NOISE

To maximize the dynamic range of an ADC, it should be driven

to its full input range. However, care is needed when driving the

ADC. If the ADC is driven too hard, the input may be damaged;

if it is not driven hard enough, resolution is lost. Driving the

ADC to its full input range does not mean that the amplifier

output must swing to its full range. A major benefit of

ADC imperfections include quantization noise, electronic—or

random—noise, and harmonic distortion. Important in most

applications, noise is usually the most important performance

metric in broadband systems.

All ADCs inherently have quantization noise, which depends

on the number of bits (n); quantization noise can be decreased

by increasing the number of bits (n). Because even ideal

converters produce quantization noise, it is used as a benchmark

against which to compare random noise and harmonic distortion.

The output noise from the ADC driver should be comparable to

or lower than the random noise and distortion of the ADC.

Beginning with a review of the characterization of ADC noise

and distortion, how to weigh ADC driver noise against the

performance of the ADC will be shown.

differential outputs is that each output must swing only half as

much as a traditional single-ended output. The driver outputs

can stay away from the supply rails, allowing decreased

distortion. However, this is not the case for single-ended drivers.

As the output voltage of the driver approaches the rail, the

amplifier loses linearity and introduces distortion.

For applications where every millivolt of output voltage is

required, see Table 1 for ADC drivers that have rail-to-rail

outputs with typical headroom ranging from a few millivolts to a

few hundred millivolts, depending on the load.

Quantization noise occurs because the ADC quantizes analog

signals that have infinite resolution into a finite number of discrete

levels. An n-bit ADC has 2ⁿbinary levels. The difference between

one level and the next represents the finest difference that can

be resolved; it is referred to as a least significant bit (LSB), or q,

for the quantum level. One quantum level is therefore 1/2ⁿof

the range of the converter. If a varying voltage is converted by a

perfect n-bit ADC, then converted back to analog and subtracted

from the input of the ADC, the difference looks like noise. It

has an rms value of

q

1

RMS Quantization Noise =

=

(21)

12 2ⁿ12

Rev. 0 | Page 7 of 16

AN-1026

APPLICATION NOTE

From this, the logarithmic (dB) formula for the signal-to-

quantizing-noise ratio of an n-bit ADC over its Nyquist

bandwidth can be derived (Equation 22); it is the best

achievable SNR for an n-bit converter.

⎡

⎢

⎤

⎥

1

SINAD(dB) = 20log₁₀

(24)

THD + N

⎢

⎣

⎥

⎦

If SINAD is substituted for the signal-to-quantizing-noise ratio

(Equation 22), an effective number of bits (ENOB) that a converter

can have if its signal-to-quantizing-noise ratio is the same as its

SINAD (Equation 25) can be defined.

Signal-to-Quantization-Noise Ratio (dB) = 6.02n + 1.76 dB (22)

Random noise in ADCs, a combination of thermal, shot, and

flicker noise, is generally larger than the quantization noise.

Harmonic distortion, resulting from nonlinearities in the ADC,

produces unwanted signals in the output that are harmonically

related to the input signals. Total harmonic distortion and noise

(THD + N) is an important ADC performance metric that

compares the electronic noise and harmonic distortion with an

analog input that is close to the full-scale input range of the ADC.

Electronic noise is integrated over a bandwidth that includes the

frequency of the last harmonic to be considered. In Equation 23,

the total THD includes the first five harmonic distortion

SINAD(dB) = 6.02(ENOB) + 1.76 dB

(25)

ENOB can also be expressed in terms of SINAD as shown in

Equation 26.

SINAD(dB) −1.76 dB

ENOB =

(26)

6.02

ENOB can be used to compare noise performance of an ADC

driver with that of the ADC to determine its suitability to drive

that ADC. A differential ADC noise model is shown in Figure 14.

V

components, which are root-sum-squared along with the noise.

nRG1

nRF1

R

F1

G1

THD + Noise =

i_nIN+

[

v₂(rms) ²

]

+

[

v₃(rms) ²

]

+

[

v₄(rms) ²

v₁(rms) ²

]

+

[

v₅(rms) ²

]

+

[

v₆(rms) ²

+ v_n

]

2

+

V

nIN

V

[

]

no, dm

i_nIN–

(23)

V

OCM

The input signal is v₁, the first five harmonic distortion products

are v₂through v₆, and the ADC electronic noise is v_n.

V

nCM

R

F2

G2

V

nRG2

V

nRF2

The reciprocal of THD + noise, the signal-to-noise-and-distortion

ratio (SINAD) is usually expressed in decibels (Equation 24).

Figure 14. Noise Model of Differential ADC Driver

The contributions to the total output noise density of each of

the eight sources are shown in Equation 27 for the general case

and when β₁= β₂≡ β.

2v_nIN

β₁+ β₂

v_nIN

β

v_{no, dm}due to v_nIN

v_{no, dm}due to v_nCM

=

for β₁= β₂= β

2v_nCM

(

β₁− β₂

)

=

= 0 for β₁= β₂= β

β₁+ β₂

2i_{nIN +}

(

1 − β₁

)

R_G

1

v_{no, dm}due to i_{nIN +}

=

(

i_{nIN +}

)

(

R_F1for β₁= β₂= β

)

β₁+ β₂

2i_{nIN −}

(

1 − β₂

)

R_G

2

v_{no, dm}due to i_{nIN −}

v_{no, dm}due to v_nRG1

=

(

i_{nIN −}

)

(

R_F2

)

for β₁= β₂= β

β₁+ β₂

(

2 4kTR_G1

)

(

1 − β₁

)

⎛

⎜

⎝

⎞

⎟

⎠

R_F1

R_G1

=

4kTR_G1

4kTR_G2

for β₁= β₂= β

β₁+ β₂

(

2 4kTR_G2

)

(

1 − β₂

)

⎛

⎞

R_F2

R_G2

⎜

⎝

⎟

⎠

v_{no, dm}due to v_nRG2

v_{no, dm}due to v_nRF1

v_{no, dm}due to v_nRF2

=

for β₁= β₂= β

β₁+ β₂

2β₁4kTR_F1

β₁+ β₂

=

4kTR_F1for β₁= β₂= β

4kTR_F2for β₁= β₂= β

2β₁4kTR_F2

β₁+ β₂

=

(27)

Rev. 0 | Page 8 of 16

APPLICATION NOTE

AN-1026

The total output noise voltage density, v_{no, dm}, is calculated by

computing the root-sum square of these components. Entering

the equations into a spreadsheet is the best way to calculate the

total output noise voltage density. The ADI Diff Amp Calculator,

which quickly calculates noise, gain, and other differential ADC

driver behaviors, is also available at www.analog.com.

SUPPLY VOLTAGE

Considering supply voltage and current is a quick way to narrow

the choice of ADC drivers. Table 1 provides a compact reference

to ADC driver performance with respect to power supply. The

supply voltage influences bandwidth, signal swing, and ICMVR.

Weighing the specifications and reviewing the trade-offs are

important to differential amplifier selection.

ADC driver noise performance can now be compared with the

ENOB of an ADC. Take for example, a differential driver with a gain

of 2 for the AD9445 ADC on a 5 V supply with a 2 V full-scale input;

it processes a direct-coupled broadband signal occupying a 50 MHz

(−3 dB) bandwidth, limited with a single-pole filter. From the data

sheet listing of the ENOB specifications for various conditions,

ENOB = 12 bits for a Nyquist bandwidth of 50 MHz.

Power-supply rejection (PSR) is another important specification.

The role of power supply pins as inputs to the amplifier is often

ignored. Any noise on the power supply lines or coupled into

them can potentially corrupt the output signal.

For example, consider the ADA4937-1 with 50 mV p-p at 60 MHz

of noise on the power line. Its PSR at 50 MHz is −70 dB. This

means that the noise on the power supply line reduces to

approximately 16 μV at the amplifier output. In a 16-bit system

with a 1 V full-scale input, 1 LSB is 15.3 μV; the noise from the

power supply line therefore swamps the LSB.

The ADA4939 is a high performance, broadband differential ADC

driver that can be direct coupled. It is a good candidate to drive

the AD9445 with respect to noise. The data sheet recommends

R_F= 402 Ω and R_G= 200 Ω for a differential gain of approximately

2. A total output voltage noise density for this configuration is

9.7 nV√Hz.

To improve this situation, add series SMT ferrite beads, L1 and

L2, and shunt bypass capacitors, C1 and C2 (see Figure 15).

First, calculate the system noise bandwidth, B_N, which is the

bandwidth of an equivalent rectangular low-pass filter that

outputs the same noise power as the actual filter that determines

the system bandwidth for a given constant input noise power

spectral density. For a one-pole filter, B_Nis equal to π/2 times

the 3 dB bandwidth, as shown in Equation 28.

V+

L1

U1

C1

AD8138AR

10nF

3

8

2

1

5

–OUT

π

2

⎛

⎜

⎝

⎞

⎟

⎠

V

OCM

6

B =

50 MHz = 78.5 MHz

(28)

N

4

+OUT

Next, integrate the noise density over the square root of the system

bandwidth to obtain the output rms noise (see Equation 29).

C2

10nF

L2

v

_{no, dm}(rms) = (9.7 nV/√Hz)(√78.5 MHz)= 86 μV rms (29)

The amplitude of the noise is presumed to have a Gaussian

distribution; therefore, using the common 3σ limits for the

peak-to-peak noise (noise voltage swings between these limits

about 99.7% of the time), the peak-to-peak output noise is

calculated as

V–

Figure 15. Power Supply Bypassing

At 50 MHz, the ferrite bead has an impedance of 60 Ω and the

10 nF (0.01 ꢁF) capacitor has an impedance of 0.32 Ω. The

attenuator formed by these two elements provides 45.5 dB of

attenuation (see Equation 32).

v

_{no, dm}(p-p) ≈ 6(86 μV rms) = 516 μV p-p

(30)

Now compare the peak-to-peak output noise of the driver with

1 LSB voltage of the AD9445 LSB, based on an ENOB of 12 bits

and full-scale input range of 2 V, as calculated in Equation 31.

0.32

0.32 + 60

⎛

⎜

⎝

⎞

⎟

⎠

Divider Attenuation = 20log

= −45.5 dB (32)

The divider attenuation combines with the PSR of –70 dB to

provide approximately 115 dB of rejection. This reduces the

noise to approximately 90 nV p-p, well below 1 LSB.

One LSB = 2 V/2¹²= 488 μV

(31)

The peak-to-peak output noise from the driver is comparable to

the LSB of the ADC with respect to 12 bits of the ENOB; the

driver is therefore a good choice to consider in this application

from the standpoint of noise. The final determination must be

made by building and testing the driver and ADC combination.

Rev. 0 | Page 9 of 16

AN-1026

APPLICATION NOTE

The HD2 at 50 MHz is approximately −88 dBc, relative to a

2 V p-p input signal. To compare the harmonic distortion level

to 1 ENOB LSB, this level must be converted to a voltage as shown

in Equation 33.

HARMONIC DISTORTION

Low harmonic distortion in the frequency domain is important

in both narrow-band and broadband systems. Nonlinearities in

the drivers generate single-tone harmonic distortion and multitone,

intermodulation distortion products at amplifier outputs.

−88

20

⎛

⎞

⎜

⎟

HD2 =

(

2 V p - p

)

10

≈ 80 ꢁV p - p

(33)

⎜

The same approach used in the noise analysis example can be

applied to distortion analysis, comparing the harmonic distortion

of the ADA4939 with 1 LSB of the AD9445’s ENOB of 12 bits

with a 2 V full-scale output. One ENOB LSB is 488 μV in the

noise analysis.

⎝

⎠

This distortion product is only 80 μV p-p, or 16% of 1 ENOB

LSB. Thus, from a distortion standpoint, the ADA4939 is a

good choice to consider as a driver for the AD9445 ADC.

Because ADC drivers are negative feedback amplifiers, output

distortion depends on the amount of loop gain in the amplifier

circuit. The inherent open-loop distortion of a negative feedback

amplifier is reduced by a factor of 1/(1 + LG), where LG is the

available loop gain.

The distortion data in the specifications table of the ADA4939

is given for a gain of 2, comparing second and third harmonics

at various frequencies. Table 3 shows the harmonic distortion

data for a gain of 2 and differential output swing of 2 V p-p.

Table 3. Second and Third Harmonic Distortion of the ADA4939

The input (error voltage) of the amplifier is multiplied by a large

forward voltage gain, A(s), then passes through the feedback

factor, β, to the input, where it adjusts the output to minimize the

error. Therefore, the loop gain of this type of amplifier is A(s) × β;

as the loop gain (A(s), β, or both) decreases, harmonic distortion

increases. Voltage feedback amplifiers, such as integrators, are

designed to have large A(s) at dc and low frequencies, and then

roll off as 1/f toward unity at a specified high frequency. As A(s)

rolls off, loop gain decreases and distortion increases. Therefore,

the harmonic distortion characteristic is the inverse of A(s).

Parameter

Harmonic Distortion (dBc)

HD2 @ 10 MHz

HD2 @ 70 MHz

HD2 @ 100 MHz

HD3 @ 10 MHz

HD3 @ 70 MHz

HD3 @ 100 MHz

−102

−83

−77

−101

−97

−91

The data shows that harmonic distortion increases with frequency

and that HD2 is worse than HD3 in the bandwidth of interest

(50 MHz). Harmonic distortion products are higher in frequency

than the frequency of interest, so their amplitude can be reduced

by system band-limiting. If the system had a brick-wall filter at

50 MHz, then only the frequencies higher than 25 MHz are of

concern because all harmonics of higher frequencies are eliminated

by the filter. Nevertheless, the system was evaluated up to 50 MHz

because any filtering that is present may not sufficiently suppress

the harmonics, and distortion products can alias back into the

signal bandwidth. Figure 16 shows the harmonic distortion vs.

frequency of the ADA4939 for various supply voltages with a

2 V p-p output.

Current feedback amplifiers use an error current as the feedback

signal. The error current is multiplied by a large forward

transresistance, T(s), which converts it to the output voltage,

then passes through the feedback factor, 1/R_F, which converts

the output voltage to a feedback current that tends to minimize

the input error current. The loop gain of an ideal current feedback

amplifier is therefore T(s) × (1/R_F) = T(s)/R_F. Like A(s), T(s) has

a large dc value and rolls off with increasing frequency, reducing

loop gain and increasing the harmonic distortion.

Loop gain also depends directly upon the feedback factor, 1/R_F.

The loop gain of an ideal current feedback amplifier does not

depend on a closed-loop voltage gain; therefore, harmonic

distortion performance does not degrade as the closed-loop

gain increases. In a real current feedback amplifier, loop gain

does have some dependence on the closed-loop gain but not

nearly to the extent that it does in a voltage feedback amplifier.

This makes a current feedback amplifier, such as the ADA4927,

a better choice than a voltage feedback amplifier for applications

requiring high closed-loop gain and low distortion.

–60

V

= 2V p-p

OUT, dm

–65

–70

HD2, V (SPLIT SUPPLY) = ±2.5V

S

HD3, V (SPLIT SUPPLY) = ±2.5V

S

HD2, V (SPLIT SUPPLY) = ±1.65V

S

HD3, V (SPLIT SUPPLY) = ±1.65V

S

–75

–80

–85

HD2 ≈ –88dBc @ 50MHz

–90

–95

–100

–105

–110

1

10

100

FREQUENCY (MHz)

Figure 16. Harmonic Distortion vs. Frequency

Rev. 0 | Page 10 of 16

APPLICATION NOTE

AN-1026

Figure 17 shows how well distortion performance holds up as

the closed-loop gain increases for the ADA4927.

Slew rate (a large signal parameter) refers to the maximum rate of

change the amplifier output can track the input, without excessive

distortion. Consider the sine wave output at the slew rate.

–40

V

,

= 2V p-p

OUT dm

V_O= V_Psin 2πft

(34)

–50

–60

–70

–80

The derivative (rate of change) of Equation 34 at the zero crossing,

the maximum rate, is

dv

dt

_max= 2πfV_P

(35)

–90

–100

–110

–120

–130

where:

dv/dt max is the slew rate.

V_Pis the peak voltage.

f is the full power bandwidth (FPBW). Solving for FPBW,

G = 1

G = 10

G = 20

Slew Rate

FPBW =

1

10

100

1k

(36)

FREQUENCY (MHz)

2πVp

Figure 17. Distortion vs. Frequency and Gain

Therefore, when selecting an ADC driver, it is important

to consider the gain, bandwidth, and slew rate (FPBW) to

determine if the amplifier is adequate for the application.

BANDWIDTH AND SLEW RATE

Bandwidth and slew rate are especially important in ADC

driver applications. Typically, the small signal bandwidth is the

bandwidth of a device, whereas the slew rate measures the maximum

rate of change at the amplifier output for large signal swings.

STABILITY

Stability considerations for differential ADC drivers are the same as

for op amps. The key specification is phase margin. The phase

margin of a particular amplifier configuration can be determined

from the data sheets; however, in a real system, parasitic effects in the

PC board layout can reduce it significantly.

Effective usable bandwidth (EUBW), an acronym analogous to

ENOB, describes bandwidth. Many ADC drivers and op amps

boast wide bandwidth specifications; however, not all that band-

width is usable. For example, −3 dB bandwidth is a conventional

way to measure bandwidth, but it does not mean that all the

bandwidth is usable. The amplitude and phase errors of the

−3 dB bandwidth can be seen a decade earlier than the actual

break frequency. An excellent way to determine the usable

bandwidth is to consult the distortion plots on the data sheet.

The stability of a negative voltage, feedback amplifier depends on

the magnitude and sign of its loop gain, A(s) × β. The differential

ADC driver is a bit more complicated than a typical op amp circuit

because it has two feedback factors. Loop gain is seen in the

denominators of Equation 7 and Equation 8. Equation 37 describes

the loop gain for the unmatched feedback factor case (β₁≠ β₂).

Figure 18 shows that to maintain greater than −80 dBc for

second and third harmonics, the ADC driver should not be used

for frequencies greater than 60 MHz. Because each application

is different, the system requirements are a guide to the appropriate

driver with sufficient bandwidth and adequate distortion

performance.

A(s)

(

β₁+ β₂

2

)

Loop Gain =

(37)

With unmatched feedback factors, the effective feedback factor

is simply the average of the two feedback factors. When they are

matched and defined as β, the loop gain simplifies to A(s) × β.

–50

For a feedback amplifier to be stable, its loop gain must not be

allowed to equal −1 or its equivalent, an amplitude of +1 with

phase shift of −180°. For a voltage feedback amplifier, the point

where the magnitude of loop gain equals 1 (that is, 0 dB) on its

open-loop gain frequency plot is where the magnitude of A(s)

equals the reciprocal of the feedback factor. For basic amplifier

applications, the feedback is purely resistive, introducing no

phase shifts around the feedback loop. With matched feedback

factors, the frequency independent reciprocal of the feedback

factor, 1 + R_F/R_G, is often referred to as the noise gain. If the

constant noise gain in decibels is plotted on the same graph as

the open-loop gain, A(s), the frequency where the two curves

intersect is where the loop gain is 1, or 0 dB. The difference

between the phase of A(s) at that frequency and −180° is defined as

the phase margin; for stable operation, it should be greater than

or equal to 45°.

HD2, G = 1, R = 200Ω

F

HD3, G = 1, R = 200Ω

F

HD2, G = 2, R = 402Ω

–60

–70

F

HD3, G = 2, R = 402Ω

F

–80

–90

–100

–110

–120

1

10

100

FREQUENCY (MHz)

Figure 18. Distortion Curves for ADA4937 Current Feedback ADC Driver

Rev. 0 | Page 11 of 16

AN-1026

APPLICATION NOTE

Figure 19 illustrates the unity-loop gain point and phase margin

for the ADA4932 with R_F/R_G= 1 (noise gain = 2).

The loop gain is 0 dB where the 300 Ω feedback resistance

horizontal line intersects the transimpedance magnitude curve.

At this frequency, the phase of T(s) is approximately −135°,

resulting in a phase margin of +45°. Phase margin and stability

increase as R_Fincreases and decrease as R_Fdecreases. Current

feedback amplifiers should always use purely resistive feedback

with sufficient phase margin.

80

60

40

20

90

GAIN

R

F

45

1 +

= 2

(6dB)

G

PHASE

0

LOOP

GAIN = 0dB

–45

–90

–135

–180

–225

–270

PC BOARD LAYOUT

6

0

When a stable ADC driver is designed, it must be realized on a

PC board. Some phase margin is lost because of the parasitic

elements of the board, which must be kept to a minimum. Of

particular concern are load capacitance, feedback loop inductance,

and summing node capacitance. Each of these parasitic reactances

adds lagging phase shift to the feedback loops, thereby reducing

phase margin. A design may lose 20° or more of phase margin

due to poor PC board layout.

–20

–40

–60

–80

PHASE

MARGIN ≈ 70°

1k

10k

100k

1M

10M

100M

1G

10G

FREQUENCY (Hz)

Figure 19. ADA4932 Open-Loop Gain Magnitude and Phase vs. Frequency

With voltage feedback amplifiers, it is best to use the smallest

possible R_Fto minimize the phase shift due to the pole formed

by R_Fand the summing node capacitance. If large R_Fis required,

that capacitance can compensate with small capacitors, C_F, across

each feedback resistor with values such that R_FC_Fequals R_G

times the summing node capacitance.

Further examination of Figure 19 shows that the ADA4932 has

approximately 50° of phase margin at a noise gain of 1 (100%

feedback in each loop). Although it is not practical to operate ADC

drivers at zero gain, this observation shows that the ADA4932

can operate stably at fractional differential gains (for example,

R_F/R_G= 0.25, noise gain = 1.25). This is not true for all differential

ADC drivers. Minimum stable gains can be seen in all ADC

driver data sheets.

PC board layout is necessarily one of the last steps in a design.

Unfortunately, it is also one of the most overlooked steps in a

design, even though high speed circuit performance is highly

dependent on layout. A high performance design can be

compromised, or even rendered useless, by a sloppy or poor

layout. Although all aspects of proper high speed PC board

design cannot be covered here, a few key topics will be addressed.

Phase margin for current feedback ADC drivers can also be

determined from open-loop responses. Instead of forward gain,

A(s), current feedback amplifiers use forward transimpedance,

T(s), with an error current as the feedback signal. The loop gain

of a current feedback driver with matched feedback resistors is

T(s)/R_F; therefore, the magnitude of the current feedback amplifier

loop gain is equal to 1 (that is, 0 dB) when T(s) = R_F. This point

can be easily located on the open-loop transimpedance and phase

plot, in the same way as for the voltage feedback amplifier. Plotting

the ratio of a resistance to 1 kΩ allows resistances to be expressed

on a log plot. Figure 20 illustrates the unity-loop gain point and

phase margin of the ADA4927 current feedback, differential

ADC driver with R_F= 300 Ω.

Parasitic elements rob high speed circuits of performance.

Parasitic capacitance is formed by component pads and traces

and ground or power planes. Long traces without ground planes

form parasitic inductances, which can lead to ringing in transient

responses and other unstable behaviors. Parasitic capacitance is

especially dangerous at the summing nodes of an amplifier

because it introduces a pole in the feedback response, causing

peaking and instability. One solution is to make sure that the

areas beneath the ADC driver mounting and feedback

component pads are clear of ground and power planes

throughout all layers of the board.

1k

100

10

50

MAGNITUDE

PHASE

0

To minimize undesired parasitic reactances, keep all traces as

short as possible. Outer layer 50 Ω PC board traces on FR-4

contribute roughly 2.8 pF/inch and 7 nH/inch. These parasitic

reactances increase by about 30% for inner layer 50 Ω traces.

Additionally, make sure that there is a ground plane under long

traces to minimize trace inductance. Keeping traces short and small

helps to minimize both parasitic capacitance and inductance and

maintains the integrity of the design.

–50

–100

1

–135

–150

PHASE

MARGIN ≈ 45°

0.3

0.1

–180

–200

10

100

1k

10k 100k

1M

10M 100M 1G

10G

FREQUENCY (Hz)

Figure 20. ADA4927 Open-Loop Gain Magnitude and Phase vs. Frequency

Rev. 0 | Page 12 of 16

APPLICATION NOTE

AN-1026

Power supply bypassing is another key area of concern for layout;

make sure that the power supply bypass capacitors, as well as the

V_OCMbypass capacitor, are located as close to the amplifier pins

as possible. In addition, using multiple bypass capacitors on the

power supplies helps to ensure that a low impedance path is

provided for broadband noise. Figure 21 shows a typical differential

amplifier schematic with power supply bypassing and a low-pass

filter on the output. The low-pass filter limits the bandwidth and

noise entering the ADC. Ideally, the power supply bypassing

capacitor returns are close to the load returns; this helps to reduce

circulating currents in the ground plane and improves ADC driver

performance (see Figure 22).

Use of ground plane, and grounding in general, is a detailed and

complex subject and beyond the scope of this application note.

However, a few key points are as follows (see Figure 22):

•

Connect the analog and digital grounds together at one

point only. This minimizes the interaction of analog and

digital currents flowing in the ground plane, which

ultimately leads to noise in the system.

•

Terminate the analog power supply into the analog power

plane and the digital power supply into the digital power

plane.

For mixed-signal ICs, terminate the analog ground returns

into the analog ground plane and the digital ground returns

into the digital ground plane and tie the two planes

together using only one small connection to minimize the

mixing of digital and analog currents (see Figure 23.)

R4

+V

S

C2

C3

Refer to A Practical Guide to High-Speed Printed-Circuit-Board

Layout for a detailed discussion about high speed printed

circuit board (PCB) layout at www.analog.com.

R2

R

R6

R7

S

C6

C7

V

TO

ADC

OCM

R

U1

T

C1

The information in this application note is intended to help you

think about the many considerations that must be taken into

account when you design with ADC drivers. Understanding

differential amplifiers and paying attention to the details of ADC

driver design at the outset of a project minimizes future problems,

lowers risk, and ensures a robust design.

R3

R1

C4

C5

–V

S

R5

Figure 21. ADC Driver with Power Supply Bypassing and Output Low-Pass Filter

R2

R4

C2

R6

R7

R

T

C3

C4

C6

C7

U1

C1

C5

R1

R3

R5

(a)

(b)

Figure 22. Component Side (a), Circuit Side (b)

V

D

A

D

V

A

ANALOG

CIRCUITS

DIGITAL

CIRCUITS

MIXED

SIGNALS

AGND

DGND

SYSTEM

STAR

GROUND

A

D

ANALOG

CIRCUITS

DIGITAL

CIRCUITS

ANALOG SUPPLY

DIGITAL SUPPLY

Figure 23. Mixed Signal Grounding

Rev. 0 | Page 13 of 16

AN-1026

NOTES

APPLICATION NOTE

Rev. 0 | Page 14 of 16

APPLICATION NOTE

NOTES

AN-1026

Rev. 0 | Page 15 of 16

AN-1026

NOTES

APPLICATION NOTE

registered trademarks are the property of their respective owners.

AN08263-0-11/09(0)

Rev. 0 | Page 16 of 16

型号	制造商	描述	价格	文档
AN-1027	CYMBET	Ultra Low Power Microcontroller Backup Using the EnerChip	获取价格
AN-1028	FAIRCHILD	Maximum Power Enhancement Techniques for SOT-223 Power MOSFETs	获取价格
AN-1029	FAIRCHILD	Maximum Power Enhancement Techniques for SO-8 Power MOSFETs	获取价格
AN-1030	CYMBET	EVAL-08 Frequently Asked Questions & Troubleshooting	获取价格
AN-1032	FAIRCHILD	Performance Restrictions Associated with 3.5 Watts SO-8 Power MOSFETs	获取价格
AN-1036	CYMBET	Using the EnerChip CC in Energy Harvesting Designs	获取价格
AN-1039	ADI	Correcting Imperfections in IQ Modulators to Improve RF Signal Fidelity	获取价格
AN-1040	CYMBET	EVAL Kit GUI Software and TI Firmware Readme	获取价格
AN-1041	CYMBET	EnerChip CC Li-Ion Battery Charger with Integrated Energy Storage	获取价格
AN-1042	CYMBET	EnerChip CC Backup Power for Epson RX-8564 Real-Time Clock	获取价格

AN-1026

AN-1026 概述

AN-1026 数据手册

AN-1026 相关器件

AN-1026 相关文章

热门型号