AN-502_技术文档

AN-502

a

APPLICATION NOTE

One Technology Way• P.O. Box9106 • Norwood, MA 02062-9106 • 781/329-4700 •World Wide Web Site: http://www.analog.com

Designing a Superheterodyne Receiver Using an IF Sam pling Diversity Chipset

by Brad Brannon

Abstract: The paper introduces a chipset to sim plify re-

ceiver design and puts forth a design exam ple based on

GSM but can be extended to m any open or closed air

interface. Advances in analog converter technology

now allow IF sam pling which can greatly sim plify re-

ceiver design. Advances in digital integrated circuits

also advance the state of the art in term s of digital tun-

ing and filtering. Together these two chips can replace

m any of the cum bersom e stages of a traditional analog

receiver with predictable and reliable perform ance.

sacrificing perform ance? Perhaps the real question is

can perform ance be enhanced. One solution is to digi-

tize the analog signals and do the processing in a DSP.

Once in the digital dom ain, m any creative and propri-

etary processes can take place to enhance and add

value, while elim inating m any of the m anufacturing

problem s (alignm ent and com ponent yield) that often

increase the cost of m anufacturing and reduce m argins.

Already, it is com m on practice to use an analog-to-

digital converter to form the detector and a DSP (digital

signal processor) to process the data. However, this

does not reduce the cost or com plexity of the design (to

digitize the baseband), it sim ply adds flexibility. What is

needed is an analog to digital converter that can digitize

closer to the antenna. Sam pling at the antenna is not

realistic since som e am ount of band select and filtering

m ust occur prior to the ADC to m inim ize adjacent chan-

nel issues. However, sam pling at the first IF is practical.

The superheterodyne receiver is still a workhorse in re-

ceiver technology. It has served its duty faithfully for

m any years now. However new technologies in receiver

com ponent designs are offering to extend the possibili-

ties into the digital age.

A typical receiver design m ay consist of two or three

down conversions to provide the sensitivity and selec-

tivity required of the individual receiver. With each

down conversion, a local oscillator, m ixer and filter are

required. Each additional stage adds com plexity, cost

and difficulty of m anufacture.

FILTER &

LNA

FILTER &

LNA

ADC

DSP

LO

FILTER

&

LNA

FILTER

&

LNA

FILTER

&

LNA

DETECTOR

PROCESS

Figure 2. Digital Receiver Block Diagram

IF SAMPLING

LO

Recent advances in converter technology have allowed

data converters to faithfully sam ple analog signals as

high as several hundred MHz. Sam ple rates need only

be as high as twice the signal bandwidth to keep the

Nyquist principle. Since m ost air interface standards

are less than a few MHz wide, sam ple rates in the tens of

MHz are required, elim inating the need for extrem ely

fast sam ple rates in radio design. Thus allowing for low

cost digitizers.

Figure 1. Typical Receiver Block Diagram

As shown above in the block diagram , receiver technol-

ogy can be “straight forward”, however, im plem enta-

tion and m anufacture can be another story.

There are several key issues that m ust be addressed. Of

course, the issues of noise and intercept point are al-

ways of concern when it com es to receiver design.

However, in m oderate and high volum e applications,

questions about assem bly and test begin to arise. It is

one thing to build one in the lab, but it is a com pletely

different story to build m any in production. With three

local oscillators, m ixers and IF strips, alignm ent can be

a real issue, even with autom ated tools. To keep

m anufacturing cost low, several of these analog stages

m ust be elim inated, but how can this be done without

One such analog to digital converter (ADC) that per-

form s this function is the AD6600. The AD6600 can

digitize up to 20 MSPS and sam ple analog signals up to

250 MHz with 60 dB spurious free dynam ic range. In ad-

dition to high perform ance data conversion, this ADC

also includes gain control and dual inputs to facilitate

diversity applications.

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A regenerative positive feedback com parator is tied to

each point and referenced to full-scale of the A/D con-

verter. Once one of the com parators is tripped it stays in

the state until it is reset by the falling edge of the encode.

The 5 com parator outputs are decoded into a 3-bit word

that is used to select the proper attenuation.

Six dB of digital hysteresis is used to elim inate level un-

certainty at the threshold points due to noise and am pli-

tude variations. The peak detector m onitors both

positive and negative excursions of the input signal to

accurately track com plex m odulated signals.

FLT+

FLT–

ENC

A_SEL

B_SEL

ENC

AD6600

TIMING

UNIT

2x

CLOCK

OUT

ATTEN

600⍀

V

A

IN

11

11-BIT

ADC

DIGITAL

OUTPUTS

T/H

3

AB_OUT

RSSI

1

3

RSSI

CONTROL

B

IN

GAIN

BLOCK

ATTEN

GND

PEAK

DETECTOR

The RSSI follows the IF envelop one clock cycle before

the conversion is m ade. During this tim e period, the

RSSI watches for the signal peaks and prior to digitiza-

tion, the RSSI word is set to the appropriate attenuation

factor to prevent the ADC from overranging on the fol-

lowing conversion cycle. The RSSI always allows an ex-

tra 6 dB of ADC headroom to prevent clipping if the

signal power has increased unexpectedly. This is true

until the last attenuator is selected. Then the ADC will

clip in a norm al m anner. The RSSI word is m ade avail-

able to read via the RSSI pins. The 11-bit ADC output

form s the m antissa of a binary floating point word, while

the RSSI the exponent. This data can be interpreted in

several ways. The data can be converted in software by

using the following pseudo-code:

V

CC

Figure 3. AD6600 Block Diagram

The block diagram above shows the details of the

AD6600 IF data converter. The AD6600 Dual Channel,

Gain Ranging ADC with RSSI (Receiver Signal Strength

Indicator) consists of three stages. The first consists of a

pair of 1 GHz phase com pensated step attenuators fol-

lowed by an output selection m ultiplexor. The second

stage is a wide input bandwidth 11-bit ADC based on the

AD9042, 12-bit 41 MSPS analog-to-digital converter. The

third stage is a high speed synchronous peak detector

and RSSI control interface. Together these on-chip sys-

tem s form a high dynam ic range IF sam pling ADC. The

AD6600 is fabricated on an advanced bipolar integrated

circuit process.

r0 = dm (rssi);

r2 = 5;

r0 = r2-r0;

The input attenuator consists of two identical inputs.

These dual inputs m ay be diversity channels, two inde-

pendent IF signals or only one input m ay be used. The

attenuation factor is controlled through a range of 30 dB

in 6 dB steps by on-chip switches. The m atching be-

tween the gain settings is better than 0.5 dB and m ain-

tains a bandwidth of alm ost 1 GHz so the phase delay is

sm all. Likewise the phase m ism atches between differ-

ent attenuator settings is very sm all, less than 0.2 de-

grees up to 200 MHz analog input. Additionally, the

input im pedance does not change with attenuator set-

tings so there is no AM to PM distortion.

r1 = dm (adc);(11 bits, MSB justified into DSP word)

rshift r1, r0; (arithm etic shift to extend the sign bit)

An ASIC/PLD can be used to convert the code to fixed

point or a digital preprocessor such as the AD6620 (to be

discussed later) can be used to convert the data. The re-

sulting data can then be treated as a standard 16-bit

fixed point word.

Since the analog front end has a bandwidth of nearly

one-gigahertz and the ADC a bandwidth of 450 MHz, a

filter is required to bandwidth lim it the wideband noise

out of the attenuator and MUX stage. This sim ple exter-

nal LC filter is tuned to the chosen IF frequency and is

designed to settle quickly between clock cycles. To expe-

dite settling between sam ples, an internal clam p circuit

is utilized to discharge the filter. This m inim izes feed

through between inputs (cross talk) because of the natu-

ral tim e constant of the resonant network. Overall, the

AD6600 achieves 60 dB SFDR and 57 dB SNR with ana-

log inputs up to 300 MHz, providing true IF sam pling

with baseband perform ance. See Figure 4.

Since one ADC serves both attenuator inputs, two con-

trol pins are provided to select which attenuator is con-

nected to the ADC. The options allow one or both inputs

to be connected to the ADC. When both inputs are se-

lected, the ADC alternates between the two on a clock by

clock basis. An output pin, AB_OUT, indicates which in-

put is currently available on the digital output sim plify-

ing interface logic.

The on-chip RSSI (Receive Strength Signal Indicator)

controls the Input attenuator. The RSSI peak detector

function consists of a high-speed com parator bank. The

peak detector has five reference points, with each refer-

ence point being 6 dB lower than the previous one.

Once digitized, the signal would have to be processed.

With a typical sam ple rate of 20 MHz, data would stream

too fast for even the hottest DSP to do m uch with in

term s of filtering, m uch less process the data for user

–2–

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0

–12

inform ation. Therefore, som e preprocessing of the data

m ust occur. With a sam ple rate of 20 MHz, the data

bandwidth would be 10 MHz, m uch m ore than is needed

for m ost air interfaces. Therefore, one thing that prepro-

cessing should achieve is to reduce the data bandwidth

as well as the data rate. Thus in addition to the ADC

(analog-to-digital converter) a DSP preprocessor is

required.

–24

–36

–48

–60

–72

–84

–96

0

–12

–24

–36

–48

–60

–72

–84

–96

–108

–120

–108

–120

–132

–144

0

1/8

1/4

3/8

1/2

1/8TH SCALE NCO PERFORMANCE

Figure 6. AD6620 NCO Spurious Perform ance at 1/8th

the Clock Rate

DIVERSITY CHIPSET

The AD6600 and AD6620 form the heart of a chipset for

IF sam pling and processing. Between the two chips,

AGC, digitizing, data rate reduction and channel filtering

are perform ed. The benefits from this pair are im m ense.

First, the integration level allows reduced system size

and power reduction. This is achieved through the elim i-

nation of analog IF stages along with their respective

com ponents. Second, alignm ent tim e is greatly re-

duced. Since filters and oscillators are now digitally

im plem ented there is no need to adjust them at the

point of m anufacture.

0

1/8

1/4

3/8

IN

1/2

FFT PERFORMANCE AT 250MHz A

Figure 4. AD6600 FFT with 250 MHz Analog Input

DIGITAL PREPROCESSING

As shown in the diagram below, the AD6620 perform s

m any functions. First it functions as a quadrature de-

m odulator, separating the I and Q signals for later pro-

cessing. The CIC (cascaded integrator com b) filters

provide data rate decim ation and low pass filtering.

Overall decim ation rates can be program m ed from 1 (in-

clusive) to over 8192. The RAM Coefficient Filter, a sum

of product design, provides program m able filter perfor-

m ance, covering a wide range of designs.

2x CLK

CLK

A/B

SCLK

SDI

SCLK

SDO

SDI

MAIN

INPUT

A/B OUT

AD6600

3 RSSI BITS

11 DATA BITS

E[2..0]

SDO

DIVERSITY

INPUT

IN[15..5] SDFS

AD6620

SDFS

ENCODE

DSP

Figure 7. AD6600/AD6620 Diversity Receiver Chipset

I

REAL,

DUAL REAL,

OR

COMPLEX

INPUTS

SERIAL

OR

PARALLEL

OUTPUTS

RAM

COEF

FILTER

2

5

OUTPUT

FORMAT

CIC

FILTER

CIC

FILTER

Aside from the figures of m erit m entioned above, the

chipset also features a seam less interchip interface. The

interchip connections are point to point and are de-

signed for single layer wiring. Additionally, the serial

output port of the AD6620 wires directly to a num ber of

industry standard DSPs including the ADSP-21xx and

ADSP-210x fam ilies.

Q

COS

–SIN

EXTERNAL

SYNC

CIRCUITRY

␮P OR

SERIAL

CONTROL

JTAG

PORT

COMPLEX

NCO

Figure 5. AD6620 Block Diagram

The num erically controlled oscillator (NCO) provides

spurious perform ance to better than –105 dBc. This ultra

clean digital local oscillator is m ixed with the digitized

input through 18-bit m ultipliers. As shown in the spec-

tral plot below of the NCO, spurious perform ance is hid-

den well in the 16-bit noise floor shown below.

The Diversity Chipset is applicable for m any different air

interfaces including narrow band FM, IS-136, CDMA,

GSM and m any others. The use of such a chipset re-

quires m any of the traditional techniques in receiver de-

sign as well as som e new considerations. However, the

end result is a m ore econom ical solution capable of

m uch m ore than a traditional analog receiver.

Interstage precision is m aintained at 18 bits while indi-

vidual stages use m uch higher precision to prevent arti-

facts due to truncation. Data out of the AD6620 can be

delivered to the DSP through either a standard serial in-

terface or through a parallel interface as a m em ory

m apped address device. Data can be delivered in 16-,

24- or 32-bit precision.

GSM and the Diversity Chipset

The rem ainder of this report focuses on a design analy-

sis of one such design. The chosen exam ple is GSM be-

cause it is one of the m ost technically challenging in

term s of selectivity. The analysis shown can just as

–3–

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easily be applied to any of the other standards and have

already been im plem ented. The front end is traditionally

referred to as the “radio” and consists of the antenna

connection through the ADC.

analog chain is the second SAW filter. This effectively

elim inates harm onics of the am plifier chain prior to

digitization.

The first am plifier between the SAWs could be a vari-

able gain am p as shown. This is not used for AGC pur-

poses but instead to rem ove variation in com ponent

values either from lot to lot, or over tem perature. Toler-

ances in insertion loss can be rem oved as a system cali-

bration by setting the gain of this am plifier. Insertion

losses of filters, m ixers and am plifiers often worsen as

tem perature increases. The gain of this am plifier could

be configured to increase with tem perature to com pen-

sate for reduced conversion efficiency as a function of

tem perature.

This report reviews the RF perform ance requirem ents in

term s of the Diversity Chipset. Throughout this writing,

certain assum ptions about the RF section, ADC noise

and process gains (to be explained later) are m ade. The

basis of this work is the GSM specification for 900 MHz

as proposed by ETSI recom m endation 05.05. Since

variations in receiver design exist, m any possible de-

signs solutions exist, this being but one. Many options

exist in term s of sam ple rate, decim ation and digital sig-

nal processing that change the receivers ability to deal

with noise. In fact, the post ADC processing (DSP) deter-

m ines m uch of the total receiver perform ance, and as a

result, represents m uch of the proprietary inform ation

surrounding m any m anufacturers total receiver design.

Total RF and IF conversion gain is 35 dB to 40 dB. With a

m axim um input signal of –13 dBm , this would overdrive

the ADC. The last IF am plifier should be a lim it or clip-

ping am plifier to prevent this. This does not adversely

effect perform ance since the input signal is phase

m odulated. Adaptive equalization requires am plitude

inform ation, however at the point where the signal is so

large as to overdrive the data converter, equalization is

no longer necessary. The dem odulation/equalization

process will still recover the signal.

Block Diagram

The following diagram is the one analyzed and will form

the core discussion from this point forward. Various ad-

vantages will be discussed to m any of the options.

The design consists of one RF strip and 1 IF strip. The RF

section has a net gain of only about 3 dB, considering

the filter losses and m ixer conversion loss. As with tradi-

tional receiver designs, m ost of the gain is in the IF strip

where filters have im proved selectivity sufficiently to

prevent overdrive from off channel signals (adjacent

channel rejection). This form s a single analog down con-

version with a second down conversion being per-

form ed digitally by the AD6620.

Total receiver dynam ic range is derived from the RF/IF

processing above, plus the 30 dB of gain ranging pro-

vided by the AD6600 as well as the 11-bit ADC incorpo-

rated in the AD6600.

RF Filtering

The purpose of the helical (preselect or band select) fil-

ter is to block out of band signals from entering the RF

stages of the receiver. In a typical base station, this filter

could consist of the bandwidth characteristics of the an-

tenna, the RF trap or coupler (to keep Tx out of the Rx),

and the broad band pass filter. As seen below, this filter

should exhibit the lowest insertion loss possible, be-

cause receiver NF is directly (1 dB per dB) related to in-

sertion loss at the front of the chain. High perform ance

receivers would likely integrate a low loss m icrostrip fil-

ter directly on the PCB to m inim ize loss in this stage, es-

pecially 1800 MHz and 1900 MHz applications. This filter

m ay also be a helical or dielectric filter, which is used to

perform band filtering. This filter ensures that following

stages are not disrupted by any rem aining out of band

signals, including the base station transm it signals. The

filters can be designed specifically to block the transm it

side as in TOKO part num bers 6DFSC and 6DFSD.

In the front end, the LNA is in front of the m ixer. This

arrangem ent m inim izes noise figure because the lossy

elem ent is behind a gain block. Another possibilities is

that the m ixer could be ahead of the LNA which m axi-

m izes interm odulation perform ance, although, as seen

later in the analysis, m eeting spurious perform ance is

not too difficult with the am plifier ahead of the m ixer.

However, with the m ixer ahead of the am plifier, receiver

noise figure is insufficient to m eet sensitivity require-

m ents due to the insertion loss of the m ixer.

After the m ixer and band pass filter is a fixed gain

am p. This am plifier is working with relatively sm all sig-

nals and has no difficulty with interm odulation perfor-

m ance. The bulk of the IF gain is located between the

two SAW filters. This allows adjacent signals to be at-

tenuated prior to am plification, which im proves the in-

term odulation perform ance. The last com ponent in the

HELICAL

BANDPASS

FILTER

–2dB

SAW #1

G = –5dB

SAW #2

G = –5dB

AD6600

ADC

AD6620

DDC

LOSS 2dB

G = 13dB G = 6.3dB

NF = 2.6dB

G = 15dB

NF = 3.8dB

G = 16dB

G = 11؎8dB

Figure 8. Signal Path Details

–4–

AN-502

where Noise is the noise in the desire channel caused by

phase noise, x(f) is the phase noise expressed in non-log

form at and p(f) is the spectral density function of the

GMSK function. For this exam ple, assum e that the GSM

signal power is –13 dBm . Also, assum e that the LO has a

phase noise that is constant across frequency (m ost of-

ten, the phase noise reduces with carrier offset). Under

these assum ptions when this equation is integrated

over the channel bandwidth, a sim ple equation falls out.

Since x(f) was assum ed to be constant (PN—phase

noise) and the integrated power of a full-scale GSM

channel is –13 dBm , the equation sim plifies to:

RF Am plifiers and Mixers

RF gain stages are available in m any form s, including

discrete, m onolithic and hybrid/MCM technologies.

Vendors such as Watkins-J ohnson, M/A-Com m , Mini-

Circuits and RF Micro Devices offering RF front ends

suitable for use in m any low noise, high intercept appli-

cations. Two of the better am plifiers are the AH1 and

RF2312 (m anufactured by Watkins-J ohnson and RF

Micro Devices respectively). These devices provide 13 dB

to 15 dB of gain with noise figures of 2.6 dB and 3.8 dB

respectively with even better perform ance planned in

the future.

Noise = PN × Signal_adjacent

or in log form ,

While large RF gains im prove noise figure they also

reduce interm odulation perform ance by increasing

wideband signal levels to the m ixer. As shown, the

architecture requires 13 dB of gain.

Noise = PN_log+ Signal_log

Noise = PN + (–13 dBm )

Low loss m ixers should also be used; however, they

should have high intercept points. For exam ple, a m ixer

with a +27 dBm LO drive level typically provides an in-

put intercept point of +37 dBm . Thus, two signals at

–43 dBm would give 3rd order interm odulation products

at about –200 dBm . However, if the intercept point were

lowered to +17 dBm , these products would increase to

–163 dBm . As signal levels are increased, interm odula-

tion perform ance will reduce rapidly. However, the GSM

specification requires only –43 dBm two-tone inter-

m odulation perform ance when receiving a reference

sensitivity signal. Although m ost m anufacturers work

hard to exceed required perform ance, m any m ixers in

this perform ance range are available. With this in m ind,

the highest intercept point m ixers readily available

should be used. Thus, for this reference design, a

+27 dBm LO drive level m ixer is specified. These are

available from a num ber of sources, including Mini-

Circuits. Insertion loss for this m ixer is 6.3 dB.

PN_required= Noise – (–13 dBm )

Since the goal is to require that phase noise be lower

than therm al noise. Assum ing that therm al noise at the

m ixer is the sam e as at the antenna, –121 dBm (therm al

noise in 200 kHz at the antenna) can be used. Thus, the

phase noise from the LO m ust be lower than –108 dBm

with an offset of 200 kHz.

IF Am ps and IF Configuration

In all radio designs, the IF is the m ost critical stage. Most

of the receiver selectivity and alm ost all blocker rejec-

tion is gained in the IF stage though the use of ceram ic,

crystal or SAW filters. The balance of the selectivity is

gained through oversam pling and FIR filtering. In GSM

as well as other standards, the SAW filters play a vital

role in the im plem entation of this receiver. First, the

SAW filters do provide som e channel selection, but not

in the usual sense where all adjacent signal are

rem oved. The second and prim ary purpose of the SAW

filters is to keep the AGC (RSSI in the AD6600) from

responding adversely to adjacent and alternate chan-

nel signals. Third, they should adequately block

unwanted m ixer signals from entering the analog-to-

digital converter.

In addition to the large LO drive levels for optim um per-

form ance, these LO signals m ust exhibit very low phase

noise perform ance. The frequency dom ain process of

the m ixer is convolution (the tim e dom ain process of the

m ixer is m ultiplication). As a result of m ixing, phase

noise from the LO causes energy from adjacent (and ac-

tive) channels is integrated into the desired channel as

an increased noise floor. To determ ine the am ount of

noise in an unused channel when an alternate channel is

occupied by a full-power signal, the following analysis is

offered.

This is actually quite im portant since large LO and RF

signals are present in the m ixer output and the AD6600

has a 1 GHz, RSSI input bandwidth. The blocking charac-

teristics of the SAW filters are im portant in order to keep

the RSSI circuitry from tracking an unwanted signal.

These unwanted signals can take several form s. The

obvious is adjacent or alternate channel signals. They

could also include RF signals coupling directly from the

antenna or even take the form of an LO signal coupling

through the m ixer. Several things can be done to m ini-

m ize interstage coupling of these out of band signals.

First, careful shielding and grounding can m inim ize

interstage coupling and, second, proper im pedance

m atching can m axim ize the efficiency of the filter.

Although not usually the case, assum e that the phase

noise in the 200 kHz GSM channel is constant at this

level (m ost often, phase noise reduces with carrier off-

set). In this case, the following equation is valid:

+0.1

Noise =

x(f )× p (f )df

f = –0.1

∫

–5–

AN-502

In cases where contam ination is not through conduc-

tion, but radiation and coupling, a differential IF stage

can greatly aid in the suppression of feed through sig-

nals. For exam ple, in cases such as radiation, differential

inputs would likely receive the sam e contam ination. Due

to very low com m on-m ode gain of the filters, am plifiers

and ADC’s, effective contam ination will be greatly re-

duced. Since SAW filters are generally differential in,

differential out devices, this com m on-m ode rejection

should be taken advantage of in the design of high per-

form ance receivers. Additionally, differential IF am plifi-

ers that aid in m atching differential filters to am plifiers

are becom ing available. Already, m any high perfor-

m ance ADCs take advantage of differential m ode inputs,

such as the AD6600 and AD6640.

From the GSM specification 05.05, in-band blocking re-

quirem ents are as shown below:

600 kHz ≤ Offset < 800 kHz

800 kHz ≤ Offset < 1.6 MHz

1.6 MHz ≤ Offset < 3 MHz

>3 MHz

–26 dBm Signal Level

–16 dBm Signal Level

–13 dBm Signal Level

In addition to the in-band blocking requirem ents, con-

sideration m ust be given to co-channel and adjacent

channel interference. Co-channel interference can not

be filtered and m ust be accounted for in the equaliza-

tion. The specification allows for co-channel C/I of up to

9 dB. Additionally, interferers in the next channel over

(±200 kHz, which is the adjacent channel) are difficult to

filter and m ust be elim inated with the digital filter (i.e.,

the AD6620), accom m odated for in the equalization, or

assum ed not present. At 400 kHz offset (alternate chan-

nel), GSM also specifies that the interferer can be 41 dB

stronger than the signal of interest. Som e filtering can

be expected from the SAW filters and m ore from the

digital filter as shown below.

SAW Filter Requirem ents

In addition to digital filtering provided by decim ating

filters such as the AD6620, SAW filters are required to

filter unwanted signals from the ADC input. If insuffi-

ciently filtered, these signals will be aliased back into the

usable band of the AD6600 and cause C/I problem s. If

severe enough, the unwanted im age could dom inate the

dem odulation process and becom e the prim ary signal

instead of the im age. The GSM specification refers to

these as blockers. To determ ine what filter requirem ents

are needed, the following discussion is offered. Som e

references are m ade to the AD6600 and AD6620, but

where necessary, the AD6600 and AD6620 data sheets

should be referenced.

In the AD6600, the blockers and interferers cause 2 m ain

problem s. The first is that they can disrupt the RSSI cir-

cuitry causing the gain control circuitry to respond to

one of the adjacent channels and not the one of interest,

thus causing the receiver to be desensitized. The second

problem is that if the IF output is inadequately filtered

then signals that are outside the Nyquist band will be

aliased back in band and possibly override the signal of

interest. With these points in consideration, a SAW filter

specification can be defined that prevents disruption of

the RSSI control and prevents aliasing of out of band

signals back in band by the sam pling process.

The AD6600 for GSM applications can be run at

13 MSPS. It can be run in two m odes. The first is sam -

pling only 1 IF signal with an effective sam ple rate of

13 MSPS. The second option is sam pling both a m ain

antenna and a diversity antenna, each at 6.5 MSPS. The

second option will be considered here because it poses

the strictest specifications on the SAW filters.

Relaxation’s can be achieved by increasing the sam ple

rate, which softens the transition band requirem ents of

the filters. Other com m on sam ple rates for GSM include

17 1/3 (64 × bit rate) and 19.5 (72 × bit rate) MSPS.

Before an in-depth analysis of the SAW filter require-

m ents, the receiver sensitivity analysis m ust first be per-

form ed in order to understand what the signal levels are

and by how m uch they m ust be attenuated.

GSM Receiver Sensitivity

Receiver sensitivity is largely based on the noise figure.

By careful selection of IF frequencies and ADC signal

placem ent, the effects of harm onics can be greatly re-

duced. Additionally, the use of dither can also im prove

som e types of spurious signals.

The m ain RF LO will have 200 kHz steps for channel se-

lection. The NCO of the AD6620 can perform additional

fine-tuning when fine-tuning is necessary due to Dop-

pler Shift or handset frequency tolerance.

Receiver Noise

For this exam ple, a sam ple rate of 6.5 MHz is used. Thus,

When analyzing the sensitivity of a receiver, the first

place to start is by determ ining how m uch therm al noise

exist in the bandwidth of the signal. The equation below

shows the calculation for therm al noise on the receiver

input.

the Nyquist bandwidth will be 3.25 MHz with

a

13 MSPS clock and operating in diversity m ode. The

aliased IF will therefore be placed at or near 1.6 MHz. For

this exam ple, an IF frequency of 170.0 MHz was chosen.

While other choices exist, 170 MHz works for both low

and high side injection at both 900 and 1800 MHz. This

allows the sam pled IF to fall no less than 1.6 MHz from

either dc or FS/2 for a variety of sam ple rates.

N_antenna= k × T × BW

In this equation, k is Boltzm ann’s constant, T is absolute

tem perature and BW is bandwidth. Evaluating this ex-

pression at room tem perature and across the 200 kHz

GSM signal bandwidth gives 0.8284 fem ptowatts or

–121 dBm .

–6–

AN-502

Total receiver noise can then be calculated using the fol-

lowing equation:

SAW #1

G = –5dB

SAW #2

G = –5dB

AD6620

DDC

AD6600

ADC

G = 15dB

NF = 3.8dB

G = 15dB

NF = 3.8dB

N_IF= N_antenna+ G + NF

IP3 = +40dBm

The form of this equation shows that the antenna ther-

m al noise is gained up by the conversion gain “G” of the

receiver, plus degraded further by the receiver noise fig-

ure. For our purposes “G” is the net sum of signal gains

and losses. The noise figure (NF) is not accounted for in

“G” and m ust be separately calculated.

Figure 10. IF Circuit Details

Exam ining the noise figure through the IF stage gives

the analysis below. The IF stage is broken down as

shown above. Power gain through the IF stage is 20 dB.

A noise analysis sim ilar to that of the RF stage gives an

IF noise figure of 8.88 dB and an intercept point of

+34.9 dBm .

Cascaded Noise Figure of Dow n Converter

The figure below shows the RF section of the receiver. It

is convenient to separate the receiver into a wideband

section and a narrow band section. This is due to the fact

that once the IF filters begin to filter off channel signals,

receiver perform ance becom es lim ited by the signal of

interest. Conversely, the front end is m ore sensitive to

the effects of off channel signals such as blockers and

interferers.

Total Cascaded Perform ance

Total perform ance for both the RF and IF paths shows

that total cascaded gain is 37.7 dB and cascaded noise

figure is 6.24 dB. As shown in the fist stage, the C/I in the

RF stage is 70 dB. After the SAW filters, they are still in-

significant and m eet the 9 dB C/I spec for all conditions.

+4

–8

5

4

3

2

1

–14

–20

–26

–32

HELICAL

FILTER

–2dB

BANDPASS

LOSS 2dB

G = 13dB

NF = 2.6dB

G = –6.3dB

IP3 = +35dBm

G = 15dB

NF = 3.8dB

IP3 = +40dBm

Figure 9. RF Circuit Details

–63

From the circuit above, the cascaded noise figure can be

determ ined. Converting the log num bers above to their

linear representations and solving the equation below

gives a cascaded noise factor of 1.579.

–89

–92

0

4

8

12 16 20 24 28 32 36 42 44 48 52 56 60

SNR – dB

1.819–1 4.266–1

1.585–1

2.239–1

F =1.585+

+

Figure 11. AD6600 SNR vs. Analog Input Power

0.631 0.631×20 0.631×20×0.234 0.631×20×0.234×0.631

F = 4.005

With an input signal of –101 dBm at the antenna port,

the SNR is thus 13.8 dB at the ADC input. The final dis-

cussion is thus how m uch the ADC degrades the SNR of

the received signal. To determ ine this, the input signal

level to the ADC m ust be known. Thus with a –101 dBm

signal on the antenna and a conversion gain of 37.7 dB,

the input signal to the ADC is –63.7 dBm .

NF = 6.03 dB

In sum m ary, the front-end section has a cascaded noise

figure of 6 dB, a conversion gain of 17.7 dB, and an inter-

cept point of about +38 dBm .

This results in an SNR at the output of the front end of

13.9 dB with the desired test signal at the input of

–101 dBm . In term s of interm odulation perform ance

based on 05.05 section 5.2, predicted perform ance is

–153 dBm at the output of the RF stage. This is a C/I al-

m ost 70 dB, m ore than adequate to m eet the required

perform ance. Since the m ixers are often the m ost costly

item in the design, a cheaper (and lower intercept point

m ixer) can be used than the one shown here.

With an input of –63 dBm , the AD6600 provides about

25 dB of wideband SNR. However, since the sam ple rate

is 6.5 MSPS and our signal bandwidth is 200 kHz, the

effective SNR is increased by the process gain, in this

case 15.1 dB (10 log (6.5/0.2)). Thus the effective SNR of

the ADC is about 40 dB.

Assum e a full-scale ADC SNR of 60 dB, a full-scale range

of about 32 m V (in the sm allest range), a signal band-

width of 200 kHz and a sam ple rate of 6.5 MSPS. This

results in a noise voltage of 307 nV in 200 kHz of band-

width. In the sam e 200 kHz of bandwidth, the analog por-

tion of the receiver delivers –77 dBm (–121 + 37.7 + 6.24) of

noise power. Into the im pedance of the AD6600, this is

64 µV. Thus, the ADC noise is sm all com pared with the

Cascaded Noise Figure of IF Processing

From our initial design, the following IF is offered. For

the m ean tim e, the variable gain am plifier and lim iting

am plifiers have been replaced with fixed gain devices.

The final design should include the specialty devices

shown in the original design.

–7–

AN-502

With a 200 kHz interferer, the interferer is 9 dB above the

signal level at the input, and the analog filters internal to

the AD6600 provide little or no rejection. Therefore, at

the ADC input, the interferer is about –35 dB. This is not

enough to trip the RSSI unless peaking occurs. If this

does occur only 1 RSSI step will be inserted causing the

SNR to fall 6 dB to 24.9 dB. This is m ore than enough for

equalization with an acceptably low FER.

total therm al noise into the ADC. Thus overall the analog

portion of the system and not the ADC determ ines SNR

for this receiver. Based on this data, a m inim um SNR of

10 dB exists with an input at the reference sensitivity.

This is enough to satisfy the requirem ents of equaliza-

tion. Better sensitivity can be achieved by selection of

quieter analog com ponents, especially the band select

filter and the low noise am plifier.

In the case of the 400 kHz interferer, the signal level on

the radio input is 41 dB above the desired signal. Since

each of the two SAW filters provide 13 dB of rejection, a

total of 26 dB can be expected for a net signal level 15 dB

above the desired signal. Thus with the desired signal

of –46.3 dBm , the interferer is –31.3 dBm which would

cause 1 RSSI step to be inserted and possibly two. In the

later case 12 dB of SNR loss would result for a net SNR

of 19 dB, still m ore than adequate for a low fram e error

rate (FER).

SAW Filter Requirem ents Continued

As m entioned earlier, the SAW filter provides som e

am ount of receiver selectivity. However the prim ary

goal of the SAW filter is to prevent the adjacent signals

from desensitizing the RSSI of the AD6600.

With

a signal 3 dB above the reference level of

–104 dBm , the ADC input level is –63.3 dBm . At this

point, the SNR is 13.9 dB. The key is to m aintain this

SNR as various blockers and interferers com e in-band.

This is the purpose of the SAW filters. Since the AD6600

is a gain ranging ADC, out of band signals of sufficient

am plitude can desensitize the AD6600 to the desired sig-

nals. For exam ple, if a signal passes to the ADC with a

level above –32 dBm , the first RSSI trip point will be

reached and cause the front end to attenuate the input

by 6 dB. This would reduce the SNR by 6 dB. Thus, any

undesired signals m ust be kept at such a level that the

input of the AD6600 is kept below –32 dBm on the high

side or below –38 dBm on the low side. This is because

the AD6600 em ploys gain hystereses to prevent gain

‘chattering’ during norm al signal fluctuations. Nor-

m ally, the upper trip point of –32 dBm can be used since

norm al power up ram ping of the transm itted signal will

cause the RSSI hystereses control to reset between us-

ers. The lower trip point is used in the case of fading

profiles when the signal m agnitude is falling.

In the case of the blocker tests, the desired signal is 3 dB

above the reference sensitivity of –101 dBm . As before,

this gives an SNR of 13.9 dB. Now in the 600 kHz case, a

m axim um block level of –26 dBm m ust be tolerated. In

this case, a m inim um rejection of 23 dB is needed from

each SAW filter for a total of 46 dB. Thus the input

blocker is (–26 + 37.7 – 46) or –34.3 dBm , which is below

the RSSI threshold.

Between 800 kHz and 3 MHz, the receiver m ust tolerate

blockers at –16 dBm . From the filter inform ation, the

SAW filters provide a total rejection of 56 dB. As before,

the blocker is (–16 + 37.7 – 56) or –34.3 dBm , again below

the RSSI threshold.

Finally, blockers outside 3 MHz m ay be up to –13 dBm .

The SAW filters provide 106 dB of rejection to these sig-

nals. Thus, ADC input levels to >3 MHz blockers are

(–13 + 37.7 – 106) or –82 dBm , which are well below any

RSSI thresholds. Furtherm ore, the desired signal is at

(–101+37.7) or –63.3 dBm . Since the sam ple rate is

6.5 MHz and our signal placem ent puts the signal at 1/4

the clock rate (about 1.6 MHz), the potential exists for the

blocker to alias directly on top of our desired signal. In

this case however, we have a C/I ratio of (–63.3 – –82.0)

or 18.7 dB, 9 dB better than the equalizer is required to

tolerate from a co-channel interferer!

Table I.

Interferer and

Blocker

Level

SAW

AD6620

200 kHz

400 kHz

600 kHz

800 kHz

>3 MHz

+9 dBc

0

18

+41 dBc

–26 dBm

–18 dBm

–13 dBm

25 dB

37 dB

47 dB

104 dB

25 dB

45 dB

Table I shows the interferers and blockers of interest.

Absent from this list is the 600 kHz interferer (Section

6.3) because it is equivalent to a blocker at –35 dBm ,

9 dB below the interferer, which should not disrupt

either the AD6600 perform ance or the equalization. The

600 kHz blocking specification is included in the Table I.

Looking at the SAW filter plots below it can be seen that

actual rejections are better than those shown by these

calculations. This provides greater insurance that RSSI

gain stages will not switch im properly and reduce the

SNR below 13 dB.

To achieve 106 dB of out of band rejection, two filters

m ust be cascaded. One filter could be used as a roofing

filter; however, the burden of the channeling filter would

then be placed on a single filter. Therefore, two identical

filters would allow the perform ance to be split equally

For the interferer specs, the desired signal is 20 dB

above the reference point. This generates an SNR of

30.9 dB on an input signal level of –46.3.

–8–

AN-502

the internal hystereses, only one clock cycle is required

before the effects of the old analog input are flushed.

Thus, the AD6600 would respond accurately with adja-

cent tim e slots at –13 dBm allowing for one sam ple clock

recovery, which is only 4% of a data bit.

1⌬

2

Digital Filtering and Decim ation

4

3

Since the sam ple rate of the ADC is m uch higher than

the DSP can process, data decim ation is required. Addi-

tionally, off channel signals and noise m ust be filtered to

im prove the SNR of the ADC. The result of oversam pling

followed by digital filtering is called process gain. Since

the sam ple rate is 6.5 MSPS and the filtered bandwidth

m ust be about 200 kHz for GSM, the process gain is

10 log (6.5/0.2) or 15.1 dB. As stated before, the ADC pro-

vides an SNR of about 40 dB under reference signal level

conditions. This is m ore than enough to prevent the

AD6600/AD6620 pair from being the perform ance-

lim iting portion of the system .

CENTER: 170.000 000 MHz

SPAN: 8.000 000 MHz

Figure 12. SAW Filter Perform ance Plot

between the two. The following table is used to define

SAW filter acoustic perform ance. In addition to the

required rejection, som e m argin has again been added.

For the GSM receiver, a 6.5 MSPS clock provides 24

tim es oversam pling of the bit rate. Thus the decim ation

factor should be 24. The AD6620 can perform one com -

plex m ultiply for each clock cycle supplied. However, if a

clock is provided that is a m ultiple of the data rate, m ore

m ultiplies and hence m ore taps can be perform ed on the

data set. To facilitate this feature of the AD6620, the

AD6600 has a 2×-clock output. This clock can be used to

double the num ber taps that the AD6600 can process.

Thus, in our prim ary exam ple of 6.5 MSPS, the 2× clock

will allow a FIR filter up to 48 taps to be used.

Table II.

Single SAW Filter Specifications

For More Inform ation, Reference

SAWTEK Part Num ber 855297

Offset Frequency

100 kHz

400 kHz

600 kHz

800 kHz

Rejection

0

13

23

28

>3 MHz

53

Insertion Loss

Passband Ripple

Delay Variation

<6 dB

<0.5 dB

<350 ns

Such a filter has been designed and the results are

shown below. The filter design software provided for

the AD6620 determ ined the im pulse response and deci-

m ation rate distribution. Decim ation was distributed as

two in the CIC2, three in the CIC5 and four in the RCF.

Out-of-Band Perform ance

Outs-of-band specifications require tolerance to 0 dBm

blockers. For out of band blockers, the SAW filters pro-

vide very little additional rejection. However, the dielec-

tric filters in the RF front end provide additional

rejection. Typical filters from TOKO show that 20 MHz

out of band, rejection is easily obtainable down to 25 dB.

The m atching networks of the SAW filters will gain addi-

tional rejection. However, worst case im ages can occur

at (0 + 37.7 – 106 – 25) or –93.3 dBm at the ADC input,

well below the worst in-band interferers.

0

–25

–50

–75

–100

Adjacent Tim e Slot Requirem ents

–125

Reference sensitivity is m easured while the adjacent

tim e slots are at a power level that is 50 dB above the

reference level. This does not effect the AD6600 because

the RSSI is updated on a per clock basis. Thus when one

data burst ends, and the next encode clock for the

AD6600 occurs, the RSSI circuit is reset. Even counting

–150

0

1

2

3

COMPOSITE FREQUENCY RESPONSE – MHz

Figure 13. Digital Filter Perform ance, Nyquist View

–9–

AN-502

0

In this pass band perform ance shown, adequate attenu-

ation is provided to prevent the RSSI from disruption

from blockers and jam m ers are required in the GSM

specification. Also, sufficient rejection is achieved to

prevent aliasing of signals as they fold within the ADC.

–25

–50

–75

Outside the passband, rejection continues to be flat. As

shown in Figure 16, rejection from the high side

of the IF out to 2 GHz continues to be flat at about

–105 dBFS.

–100

–125

Finally, adding the perform ance of the digital filter to the

analog filter provides the following perform ance. As

seen in Figure 17, additional pass band shaping results

as well as even m ore stop band rejection. The graph

here has the three im ages superim posed. The first is the

–150

0

100

200

300

400

500

COMPOSITE FREQUENCY RESPONSE – kHz

Figure 14. Digital Filter Perform ance, Channel View

0

Measured Receiver Perform ance

The receiver described here was assem bled and the

digital filter program m ed as designed above. Data was

then taken on the various param eters of the IF sub-cir-

cuit, the m ost critical and unique to this im plem entation.

The results are shown here.

–20

–40

–60

The first critical point of the IF is that of the SAW filters

and their ability to reject off channel signals to a degree

that will prevent the gain ranging from being disrupted.

It was very quickly shown that SAW filters do not pro-

vide m uch rejection for signals at 2 GHz (typical high

side local oscillator for a PCS basestation) when oper-

ated in the singled-ended m ode. This is due to the ca-

pacitive coupling between the input and output

transducers. However, this coupling is approxim ately

com m on m ode between the two output term inals.

Therefore, taken differentially, the 2 GHz can be com -

pletely rejected. In addition to the local oscillator, this

im proves rejection of the reverse traffic that is usually

generated in close proxim ity to the sensitive receiver

circuit as well as any other strong RF fields that m ay en-

ter the receiver intended or otherwise.

–80

–100

–120

10M

150M

270M

410M

550M

670M

1G

IF INPUT FREQUENCY – Hz

Figure 16. IF Frequency Response, 10 MHz to 1 GHz

basic dual SAW filter perform ance. The second is the

com bined SAW perform ance and digital filtering and

the third is the required GSM m asking required for the

AD6600 and AD6620 to properly operate. As seen there

is plenty of m argin for all frequencies. Additionally,

digital filtering provides additional m argin in off channel

rejection, which now provides over 130 dB rejection.

Run differentially, the dual SAW filters do indeed pro-

vide the pass band and stop band perform ance required

as shown below in Figure 15.

0

–20

–40

0

–20

–40

–60

–80

GSM

MASKING

BASIC DUAL

SAW FILTER

PERFORMANCE

–100

–120

–140

–160

–180

COMBINED

SAW FILTER

PERFORMANCE

SERIES 1

–80

AND DIGITAL FILTERING

167

168

169

170

171

172

173

–100

–120

FREQUENCY – MHz

Figure 17. SAW Perform ance, Com bined Perform ance

and GSM Requirem ents

167

168

169

170

171

172

173

FREQUENCY – MHz

Figure 15. IF Frequency Response (In Band)

–10–

AN-502

0

–12

GSM 05.05 Blocker and Interferer Testing

Testing the receiver against the GSM specifications

m akes a m ore critical review of the receiver design. The

critical specifications are the blocker and interferer tests,

which provide m ultitone in-band requirem ents. These

tests are outlined below in the tables. Since our receiver

consists only of the IF filters and clam p am plifier, the

test signals were injected at a level as would be found

on the output of the m ixer.

–24

–36

–48

–60

–72

–84

–96

–108

–120

–132

Table III.

Interferer Frequency

Offset

–144

0

128

256

384

512

C/ I Level

Figure 19. 400 kHz Interferer

0

9 dBc

±200 kHz

±400 kHz

±600 kHz

–9 dBc

–41 dBc

–49 dBc

Rejection at 400 kHz is very sim ilar to that of 200 kHz. As

before, the digital filtering provides additional rejection.

By 400 kHz offset, the filter perform ance has reached the

m axim um rejection of just greater than 100 dB. Thus af-

ter filtering the spurious is again gone and the in-band

SNR is still about 32 dB.

Shown in Table III are the carrier to interferer levels as

specified by GSM. The zero offset frequency (co-chan-

nel) interferer is a function of the equalizer perform ance

and thus not discussed in this report. However, all other

frequencies are of interest and will be tested. The plots

below show the receiver perform ance to the ADC output

for the 200 kHz, 400 kHz and 600 kHz interferer specs.

0

–12

–24

–36

–48

–60

0

–12

–72

–84

–24

–96

–36

–108

–120

–132

–48

–60

–72

–144

–84

0

128

256

384

512

–96

Figure 20. 600 kHz Interferer

–108

–120

–132

The final interferer test is at 600 kHz. By 600 kHz, the

SAW filters have begun rejecting the signal and all that

rem ains are various spurious signals. It should be noted

that none of the spurs in the above plot are 600 kHz. As

with the 400 kHz offset test, the digital filter provides

another 100 dB of rejection and the spurious products

are all rem oved leaving an in-band SNR of 30 dB.

–144

0

128

256

384

512

Figure 18. 200 kHz Interferer

In the 200 kHz blocker test above, the 200 kHz signal has

been rejected to 6 dBc by the SAW filters. Before equal-

ization, this signal is to be passed to the digital filter

(AD6620) where the spectrum will be filtered. At 200 kHz

offset, our digital filter should have at least 70 dB of

rejection. Thus after filtering, the spurious will be about

–76 dBc and the SNR in the channel of interest will be

32.3 dB, m ore than enough for a low bit error rate.

Table IV.

Blocker

C/ I Level

600 kHz ≤ Offset < 800 kHz

800 kHz ≤ Offset < 1.6 MHz

1.6 MHz ≤ Offset < 3 MHz

>3 MHz

–26 dBm Signal Level

–16 dBm Signal Level

–13 dBm Signal Level

–11–

AN-502

0

–12

The blocking requirem ents are shown in Table IV. Again,

the inputs to the IF filters were driven as if they had been

processed by a proper front end, but the signal levels

were representative of the blocking specification. Since

blocking perform ance should be worse on the low fre-

quency edge, the blocking tests were perform ed at the

lower frequency corner.

–24

–36

–48

–60

–72

–84

0

–12

–96

–108

–120

–132

–24

–36

–48

–144

0

128

256

384

512

–60

Figure 23. 1600 kHz Blocker

–72

–84

The final two plots are for the 1600 kHz and 3000 kHz

offset blocker. As seen, the SNR is consistent at 15 dB

and spurious rejection com plete. Thus inclusion, the in-

terferer and blocker test should pose no problem to a

receiver im plem ented with the AD6600 and AD6620

Diversity Chipset.

–96

–108

–120

–132

–144

0

128

256

384

512

Figure 21. 600 kHz Blocker

0

–12

As can be seen, only the desired carrier is present, the

600 kHz blocker is suppressed into the noise floor. As

before, digital filtering will then rem ove excess noise

and provide an SNR of 15 dB. Since this test is per-

form ed 3 dB above m inim um sensitivity, this test de-

fines what the m inim um sensitivity for the receiver.

Under these conditions, the reference sensitivity is

–104 dBm , giving an SNR of 12 dB. Most equalizers will

function adequately with 10 dB of SNR. Therefore pro-

–24

–36

–48

–60

–72

–84

–96

–108

–120

–132

viding

a total sensitivity for the receiver of about

–106 dBm .

–144

0

128

256

384

512

0

–12

Figure 24. 3 MHz Blocker

GSM Receiver Sum m ary

–24

–36

In sum m ary, the AD6600 can m ake a very effective IF

sam pling receiver, elim inating m any of the passive and

active com ponents associated with m ultiple down con-

version receivers. Based on the analog receiver design

required, it is quite feasible to produce a receiver with

the required sensitivity as well. In fact, com ponents ex-

ist that readily fill the requirem ents. These include RF

am ps, RF m ixers, SAW filters, and now ADCs and digital

drop receivers. Continued developm ent of GaAs am pli-

fiers and m ixers will continue to im prove receiver

perform ance. The continuing m ove to differential com -

ponents such as am plifiers and m ixers will also tend to

increase the perform ance of these system s. This will re-

duce the com m on-m ode problem s within the receiver

design such as LO coupling and RF bleed through.

–48

–60

–72

–84

–96

–108

–120

–132

–144

0

128

256

384

512

Figure 22. 800 kHz Blocker

At 800 kHz, an im age appears, but is again suppressed

with digital filtering. As before, SNR is about 15 dB,

which gives an overall sensitivity of –106 dBm .

–12–


型号：	AN-502
厂家：	ADI
描述：	Designing a Superheterodyne Receiver Using an IF Sampling Diversity Chipset 设计一个超外差接收机使用的IF采样多样性芯片组接收机
文件：	总12页 (文件大小：203K)
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AN-502 [ADI]

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