ANMG04 [ADI]

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ANMG04
型号: ANMG04
厂家: ADI    ADI
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ANMG04  
ANMG04 (4-CH Auto Sensitivity Calibration Capacitive Touch Sensor)  
SPECIFICATION  
VER. Preliminary  
November, 2013  
ADSemiconductor Confidential  
ADSemiconductor®  
ANMG04 (4-CH Auto Sensitivity Calibration Capacitive Touch Sensor)  
Revision History  
Rev.  
Description of change  
Date  
Originator  
Pre. First creation  
13. 11. 28.  
KD PARK  
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Content  
Revision History.................................................................................................................2  
1
Features...............................................................................................................................4  
1.1  
1.2  
General Features ...................................................................................................4  
Applications..........................................................................................................4  
2
3
4
Block Diagram....................................................................................................................5  
Pin Configuration ...............................................................................................................6  
Pin Description ...................................................................................................................7  
4.1  
Pin Map (14 SOP package) ..................................................................................8  
5
6
Absolute Maximum Rating ................................................................................................9  
ESD & Latch-up Characteristics ........................................................................................9  
6.1  
6.2  
ESD Characteristics..............................................................................................9  
Latch-up Characteristics.......................................................................................9  
7
8
Electrical Characteristics..................................................................................................10  
ANMG04 Implementation................................................................................................11  
8.1  
8.2  
8.3  
8.4  
8.5  
Typical current consumption..............................................................................11  
CS implementation .............................................................................................11  
LED drive implementation .................................................................................12  
Parallel output.....................................................................................................12  
SCL, SDA implementation.................................................................................12  
9
I2C Interface......................................................................................................................13  
9.1  
9.2  
9.3  
9.4  
9.5  
9.6  
9.7  
9.8  
9.9  
I2C Enable / Disable............................................................................................13  
Start & stop condition.........................................................................................13  
Data validity........................................................................................................13  
Byte format.........................................................................................................13  
Acknowledge......................................................................................................13  
First byte.............................................................................................................14  
Transferring data.................................................................................................15  
I2C write and read operations in normal mode...................................................16  
I2C timing diagram .............................................................................................16  
10 ANMG04 control register list...........................................................................................17  
10.1  
10.2  
I2C Register Map ................................................................................................17  
Details.................................................................................................................18  
11 Recommended Circuit Diagram .......................................................................................25  
11.1 ANMG04 (14 SOP)............................................................................................25  
12 MECHANICAL DRAWING ...........................................................................................27  
12.1 Mechanical Drawing of ANMG04 (14 SOP).....................................................27  
13 MARKING DESCRIPTION............................................................................................28  
13.1 Marking Description of ANMG04 (14 SOP) .....................................................28  
NOTES: ...................................................................................................................................29  
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ANMG04 (4-CH Auto Sensitivity Calibration Capacitive Touch Sensor)  
1 Features  
1.1 General Features  
4-Channel capacitive sensor with auto sensitivity calibration  
Available LED PWM drive up to 4  
Multi interface - I2C serial interface / Parallel outputs  
Selectable output operation mode (Single output / Multi output)  
Adjustable 256 steps sensitivity  
Almost no external component needed  
Low current consumption  
Embedded common and normal noise elimination circuit  
RoHS compliant 14 SOP packages  
Moisture sensitivity level 3 (MSL3)  
1.2 Applications  
Home appliances (TV, Monitor keypads)  
Mobile applications (PMP, MP3, Car navigation)  
Membrane switch replacement  
Sealed control panels, keypads  
Touch screen replacement application Home application  
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2 Block Diagram  
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3 Pin Configuration  
[14-SOP]  
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4 Pin Description  
VDD, GND  
Supply voltage and ground pin.  
R.N.D  
Radio frequency Noise Detection pin. Normally, R.N.D pin does not connect to anywhere.  
But, in radio frequency noise environment, this pin must form a pattern line on PCB.  
CS1 ~ CS4  
Capacitive sensor input pins.  
LCAP  
Internal LDO output port.  
D1 ~ D4  
Parallel output ports of CS1~CS4 respectively / LED PWM drive output ports. The structure of these parallel  
output ports is open drain NMOS for active low output level operation.  
SCL, SDA  
SCL is I2C clock input pin and SDA is I2C data input-output pin. These ports have internal pull-up resistor.  
In case of not use, this pin must be not connected to any circuitry.  
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4.1 Pin Map (14 SOP package)  
Pin  
Number  
1
Name  
I/O  
Description  
Capacitive sensor input 2  
Protection  
CS2  
CS3  
CS4  
SCL  
Analog Input  
Analog Input  
Analog Input  
VDD/GND  
VDD/GND  
VDD/GND  
VDD/GND  
2
3
4
Capacitive sensor input 3  
Capacitive sensor input 4  
I2C clock input  
I2C data input-output  
Open drain NMOS structure  
Supply ground  
Digital Input  
Digital  
Input / Output  
Ground  
5
SDA  
VDD/GND  
6
7
GND  
VDD  
R.N.D  
Analog Input  
Radio frequency Noise Detection pin  
Parallel output of CS1  
VDD/GND  
8
9
D1  
D2  
D3  
D4  
Digital Output  
LED PWM drive output1  
Open drain NMOS structure  
Parallel output of CS2  
LED PWM drive output2  
Open drain NMOS structure  
Parallel output of CS3  
LED PWM drive output3  
Open drain NMOS structure  
Parallel output of CS4  
LED PWM drive output4  
Open drain NMOS structure  
Internal LDO Output  
VDD/GND  
VDD/GND  
VDD/GND  
VDD/GND  
Digital Output  
Digital Output  
Digital Output  
10  
11  
12  
13  
14  
LCAP  
VDD  
CS1  
Analog Output  
Power  
VDD/GND  
GND  
Power (2.5V~5.5V)  
Analog Input  
Capacitive sensor input 1  
VDD/GND  
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5 Absolute Maximum Rating  
Battery supply voltage  
Maximum voltage on any pin  
Maximum current on any PAD  
Power Dissipation  
6V  
VDD+0.3  
100mA  
800mW  
-50 ~ 150  
Storage Temperature  
Operating Temperature  
-20 ~ 75℃  
Junction Temperature  
150℃  
Note : Unless any other command is noted, all above are operated in normal temperature.  
6 ESD & Latch-up Characteristics  
6.1 ESD Characteristics  
Mode  
Polarity  
Max  
Reference  
8000V  
8000V  
8000V  
550V  
VDD  
VSS  
H.B.M  
Pos / Neg  
P to P  
VDD  
VSS  
M.M  
Pos / Neg  
550V  
400V  
P to P  
C.D.M  
-
800V  
Field Induced Charge  
6.2 Latch-up Characteristics  
Mode  
Polarity  
Max  
100mA  
-100mA  
8.25V  
Reference  
Positive  
Negative  
Positive  
I Test  
JESD78D : 2011  
V supply over 5.0V  
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7 Electrical Characteristics  
VDD=3.3V, Typical system frequency (Unless otherwise noted), TA = 25  
Characteristics  
Symbol  
Test Condition  
Min  
Typ  
Max  
Units  
Power supply requirement and current consumption  
Operating voltage  
VDD  
IDD  
2.5  
-
5.5  
-
V
Current consumption  
VDD= 3.3V, Standby state  
0.50  
2.1  
mA  
Reset and input level  
Internal reset voltage  
Input high level  
VDD_RST  
VIH  
TA = 25  
-
-
V
V
V
| IIH | ≤ +5μA  
| IIL | ≤ +5μA  
VDD*0.6  
0.3  
VDD+0.3  
VDD*0.3  
Input low level  
VIL  
Slow calibration speed  
Normal calibration speed  
Fast calibration speed  
-
-
-
100  
80  
60  
-
-
-
Self calibration time after  
system reset  
TCAL  
RP/U  
msec  
Internal Pull Up resister of  
SDA, SCL, INT  
-
30  
-
kΩ  
Touch sensing performance  
Minimum detective  
capacitance difference  
Sense input  
ΔCMIN  
CS  
0.1  
-
-
-
-
pF  
pF  
Ω
50  
capacitance range1  
Output impedance  
(open drain)  
ΔC > ΔCMIN  
ΔC < ΔCMIN  
-
-
12  
30M  
-
-
Zo  
System performance  
Max. output current  
(LED drive current)  
IOUT  
Per unit drive output port  
-
-
8.0  
LED PWM control2  
NPWM  
-
-
-
-
16  
256  
-
-
-
step  
step  
MHz  
sec  
Sensitivity control3  
Max. I2C SCL clock speed  
Touch expired time  
fSCL_MAX  
TEX  
Maximum internal I2C clock  
Normal calibration speed  
2
-
30  
1
The sensitivity can be decreased with higher parallel capacitance of CS pin including parasitic capacitance made by  
neighbor GND or other pattern. The series resistor(under 1k) of CS can be used in noisy condition to avoid mal-function  
from external surge and ESD.  
2
Refer to the chapter 10.2.12. LED luminance control register  
3
Refer to the chapter 10.2.8. Sensitivity register  
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8 ANMG04 Implementation  
8.1 Typical current consumption  
ANMG04 uses internal bias circuit, so internal clock frequency and current consumption is fixed and no  
external bias circuit is needed. Internal clock frequency and calibration speed can be changed by I2C register  
setting4. Faster calibration speed needs more current consumption than normal or slower calibration speed. Slow  
calibration speed isn’t recommended if it has not problem of current consumption.  
Internal bias circuit can make the circuit design simple and reduce external components.  
8.2 CS implementation  
ANMG04 has 256 step selections of sensitivity and internal surge protection resister. Sensitivity of each sensing  
channel (CS) can be independently controlled on others. External components of CS pin such as series resistor  
or parallel capacitor isn’t necessary. The parallel parasitic capacitance of CS pins caused by touch line, touch  
pad and neighbor GND or other pattern may affect sensitivity. The sensitivity will be decreased when bigger  
parallel parasitic capacitance of CS pin is added.  
Parallel capacitor (CS1~S4) of CS pin is useful in case of detail sensitivity mediation is required such as for  
complementation sensitivity difference between channels. Same as above parallel parasitic capacitance,  
sensitivity will be decreased when a big value of parallel capacitor (CS1~S4) is used. Under 50pF capacitor can be  
used as sensitivity meditation capacitor and a few pF is usually used. The RS, serial connection resistor of CS  
pins, may be used to avoid mal-function from external surge and ESD. (It might be optional.) From 200Ω to  
1kΩ is recommended for RS. Refer to below CS pins application figure.  
RS4  
CS4<<  
Touch PAD4  
CS4  
RS1  
Touch PAD1  
CS1<<  
CS1  
The ANMG04 has eight independent touch sensor input from CS1 to CS4. The internal touch decision process  
of each channel is separated from others. Therefore eight channel touch key board application can be designed  
by using only one ANMG04 without coupling problems.  
The size and shape of PAD might have influence on the sensitivity. The sensitivity will be optimal when the size  
of PAD is approximately an half of the first knuckle (it’s about 10 ㎜x 7 ). The connection line of CS to  
touch PAD is recommended to be routed as short as possible to prevent from abnormal touch detect caused by  
connection line. The unused CS pin should not be connected with the ground.  
4
Refer to 10.2.4. Clock control register.  
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8.3 LED drive implementation  
ANMG04 has a function to control the LED using D1~D4 ports. For using D1~D4 as LED driver ports, LEDs  
and resisters must be equipped as below figure, and write the ‘port_mode” register5 as ‘1’. D1 ~ D4 ports can  
drive LEDs by ‘PWM_ctrlx’ register6 control. ANMG04 can drive up to 8 LED as below method.  
VDD  
VDD  
LED4  
LED1  
RD4  
RD1  
D1 <<  
D4 <<  
8.4 Parallel output  
ANMG04 acts as active low parallel output mode. Parallel output ports (D1~D4) have an open drain NMOS  
structure. For this reason, the parallel output mode of ANMG04 needs ROUT as below figures. The maximum  
output drive current is 8mA, so over a few kΩ must be used as ROUT. Normally 10kΩ is used as ROUT  
.
VDD  
ROUT1  
ROUT2  
OUTPUT1  
OUTPUT2  
D1  
D2  
ROUT4  
OUTPUT4  
D4  
Active low parallel output mode circuit  
8.5 SCL, SDA implementation  
SCL is I2C clock input and SDA is I2C data input-output. These ports have internal pull-up resistor. SCL has  
Schmitt trigger input structure to prevent clock signal from being broken. Maximum supported I2C clock  
frequency is 2MHz. SDA has NMOS open drain structure and internal pull-up resister of which value is 30kΩ  
typical. So, according to communication speed a few kΩ resister must be used as pull-up resister for proper data  
pulse rising time. For more details refer to ‘Chapter 9. I2C Interface’.  
5
Refer to the chapter 10.2.12. Port mode control register  
6
Refer to the chapter 10.2.11. LED luminance control register  
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9 I2C Interface  
9.1 I2C Enable / Disable  
If the SDA or SCL signal goes to low, I2C control block is enabled automatically. And if the SDA and SCL  
signal maintain high during about 2 us, I2C control block is disabled automatically also.  
9.2 Start & stop condition  
Start Condition (S)  
Stop Condition (P)  
Repeated Start (Sr)  
9.3 Data validity  
The SDA should be stable when the SCL is high and the SDA can be changed when the SCL is low.  
9.4 Byte format  
The byte structure is composed with 8Bit data and an acknowledge signal.  
9.5 Acknowledge  
It is a check bit whether the receiver gets the data from the transmitter without error or not. The receiver will  
write ‘0’ when it received the data successfully and ‘1’ if not.  
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9.6 First byte  
9.6.1  
Slave address  
It is the first byte from the start condition. It is used to access the slave device. The initial chip address of  
ANMG04 is ‘48’ hexadecimal number.  
9.6.2  
R/W  
The direction of data is decided by the bit and it follows the address data.  
MSB  
LSB  
Address  
7 bit  
R/W  
1bit  
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9.7 Transferring data  
9.7.1  
Write operation  
The byte sequence is as follows:  
1. The first byte gives the device address plus the direction bit (R/W = 0).  
2. The second byte contains the internal address of the first register to be accessed.  
3. The next byte is written in the internal register. Following bytes are written in successive internal registers.  
4. The transfer lasts until stop conditions are encountered.  
5. The ANMG04 acknowledges every byte transfer.  
9.7.2  
Read operation  
The address of the first register to read is programmed in a write operation without data, and terminated by the  
stop condition. Then, another start is followed by the device address and R/W= 1. All following bytes are now  
data to be read at successive positions starting from the initial address.  
9.7.3  
Read/Write Operation  
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9.8 I2C write and read operations in normal mode  
The following figure represents the I2C normal mode write and read registers.  
Write register 0x00 to 0x01 with data AA and BB  
Device  
Address 0x48  
Register  
Address 0x00  
Start  
ACK  
ACK  
Data AA  
ACK  
Data BB  
ACK  
Stop  
Read register 0x00 and 0x01  
Device  
Address 0x48  
Register  
Address 0x00  
Start  
ACK  
ACK  
ACK  
Stop  
Device  
Address 0x49  
Start  
ACK  
Data Read AA  
Data Read BB  
Stop  
ACK  
From Slave to Master  
From Master to Slave  
9.9 I2C timing diagram  
100kbps  
400kbps  
PARAMETER  
SYMBOL  
UNIT  
MIN.  
4.0  
4.7  
4.0  
4.7  
1.0  
250  
-
MAX.  
MIN.  
MAX.  
Hold time (repeated)START condition.  
LOW period of the SCL clock  
HIGH period of the SCL clock  
Set-up time for a repeated START condition  
Data hold time  
tHD;STA  
-
0.6  
1.3  
0.6  
0.6  
-
-
us  
us  
us  
us  
us  
ns  
ns  
ns  
us  
tLOW  
tHIGH  
tSU;STA  
tHD;DAT  
tSU;DAT  
tr  
-
-
-
-
-
-
-
-
-
Data set-up time  
100  
20  
-
Rise time of both SDA and SCL signals  
Fall time of both SDA and SCL signals  
Set-up time for STOP condition  
1000  
300  
-
300  
300  
-
tf  
-
20  
tSU;STO  
4.0  
0.6  
Bus free time between a STOP and START  
condition  
Noise margin at the LOW level for each  
connected device  
Noise margin at the HIGH level for each  
connected device  
tBUF  
VnL  
VnH  
4.7  
-
-
-
1.3  
-
-
-
us  
V
V
0.1VDD  
0.2VDD  
0.1VDD  
0.2VDD  
Input Low level  
Input High level  
0
VDD*0.2  
VDD  
V
V
VDD*0.8  
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10 ANMG04 control register list  
Note: The unused bits (defined as reserved) in I2C registers must be kept to zero.  
10.1 I2C Register Map  
Addr Reset  
Bit name of each bytes  
Name  
.
Value  
Bit7  
Bit6  
Bit5  
Bit4  
Bit3  
Bit2  
Bit1  
Bit0  
(Hex) (Bin)  
ch_enable  
/soft_rst  
i2c_id  
01H 1111 1111  
-
-
-
-
ch4_en  
ch3_en  
ch2_en  
ch1_en  
06H 0100 1000  
2AH Read only  
i2c_id  
wr_bit  
o_ch1  
output  
-
-
-
-
-
o_ch4  
clk_sel  
response_ctrl  
o_ch3  
o_ch2  
rb_sel  
bf_mode software_rst  
clock_ctrl 34H 0000 0110  
global_ctrl1 36H 0100 1100  
state_count 37H 1111 1111  
init_cal_opt  
response_off_ctrl  
1
1
1
cal_pre_scaler  
sin_multi_mod  
e
global_ctrl2 38H 1011 1100 imp_sel  
cal_hold_time  
0
clk_off  
sensitivity1 39H 0001 1100  
sensitivity2 3AH 0001 1100  
sensitivity3 3BH 0001 1100  
sensitivity4 3CH 0001 1100  
sensitivity01  
sensitivity02  
sensitivity03  
sensitivity04  
cal_speed 41H 0110 0110  
cal_BS_spe  
42H 0110 0110  
ed  
rnd_bf_up  
rnd_bs_up  
rnd_bf_down  
rnd_bs_down  
sen_bf_up  
sen_bs_up  
sen_bf_down  
sen_bs_down  
PWM_ctrl1 43H 0000 0000  
PWM_ctrl2 44H 0000 0000  
pwm_d2  
pwm_d4  
pwm_d1  
pwm_d3  
0000 0000  
port_mode 4FH  
rd_ch_H1 50H  
rd_ch_L1 51H  
Percent_H 52H  
-
-
-
-
-
-
-
pmod_d4  
rd_ch_H1  
pmod_d3  
pmod_d2  
pmod_d1  
-
-
-
rd_ch_L1  
touch_percent[24:17]  
touch_percent[16:9]  
touch_percent[8:1]  
rd_ch_H2  
Percent_M 53H Read only  
Percent_L 54H  
rd_ch_H2 56H  
rd_ch_L2 57H  
-
-
-
-
-
-
rd_ch_L2  
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10.2 Details  
10.2.1 Channel enable / reset register  
Type: R/W  
Address  
Register Name  
Bit7  
Bit6  
Bit5  
Bit4  
Bit3  
Bit2  
Bit1  
Bit0  
ch_enable  
/soft_rst  
-
-
-
-
ch4_en  
ch3_en  
ch2_en  
ch1_en  
01h  
Description  
Enable, disable and reset of each channel control register.  
It is strongly recommended that the Bit7 ~ Bit4 of the ch_enable register is to be 0.  
Bit name  
Reset value  
Function  
Channel enable / disable and Channel reset (chx_en is control bit for CSx channel)  
chx_en  
1
0 : Channel disable and sensing channel reset  
1 : Channel enable  
10.2.2 I2C address of ANMG04  
Type: R/W  
Address  
06h  
Register Name  
i2c_id  
Bit7  
Bit6  
Bit5  
Bit4  
Bit3  
Bit2  
Bit1  
Bit0  
i2c_id  
wr_bit  
Description  
Chip address of ANMG04 control register.  
Bit name  
wr_bit  
Reset value  
0
Function  
Write/Read address selection - 0 : Write address, 1 : Read address  
Chip address of ANMG04.  
i2c_id  
0100100  
10.2.3 Output data  
Type: R  
Address  
2Ah  
Register Name  
output  
Bit7  
Bit6  
Bit5  
Bit4  
Bit3  
Bit2  
Bit1  
Bit0  
-
-
-
-
o_ch4  
o_ch3  
o_ch2  
o_ch1  
Description  
The output data register from channel 1 to channel 4.  
Bit name  
Reset value  
Function  
o_chx is output bit for CSx channel  
0 : No touch detected  
o_chx  
Read only  
1 : Touch detected  
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10.2.4 Clock control register  
Type: R/W  
Address  
Register Name  
clock_ctrl  
Bit7  
Bit6  
Bit5  
Bit4  
Bit3  
Bit2  
Bit1  
Bit0  
init_cal_opt  
-
clk_sel  
rb_sel  
34h  
Description  
This register controls the global options of ANMG04  
Bit name  
Reset value  
Function  
ANMG04 provides three internal calibration speeds with this register.  
00, 01 : Fast  
10 : Normal  
rb_sel  
10  
11 : Slow  
ANMG04 provides four internal calibration speeds with this register.  
00 : Fast  
01 : Normal  
clk_sel  
01  
10 : Slow  
11 : Slowest  
To control the initial BF time.  
init_cal_opt[2:0] * 5 + 5 (Seconds)  
init_cal_opt  
000  
10.2.5 Global option control register 1  
Type: R/W  
Address  
Register Name  
global_ctrl1  
Bit7  
Bit6  
Bit5  
Bit4  
Bit3  
Bit2  
Bit1  
Bit0  
software  
_rst  
response_off_ctrl  
response_ctrl  
bf_mode  
36h  
Description  
This register controls the global options of ANMG04  
Bit name  
Reset value  
Function  
Software reset control bit. Reset the data of all sensing channel.  
software_rst  
0
0 : No reset  
1 : Reset  
Operation mode selection  
bf_mode  
0
0 : Normal mode  
1 : BF mode  
Numbers of continuous touch detections for touch decision.  
response_ctrl[2:0] + 1 (Maximum time : 7)  
response_ctrl  
011  
010  
Numbers of continuous touch off detections for touch off decision.  
response_off_ ctrl[2:0] + 1 (Maximum time : 7)  
response_off_ctrl  
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ANMG04 (4-CH Auto Sensitivity Calibration Capacitive Touch Sensor)  
10.2.6 State count control register  
Type: R/W  
Address  
Register Name  
state_count  
Bit7  
Bit6  
Bit5  
Bit4  
Bit3  
Bit2  
Bit1  
Bit0  
1
1
1
cal_pre_scaler  
37h  
Description  
Register to set the pre-scaler for the calibration speed.  
Bit name  
Reset value  
Function  
The pre-scaler for the calibration speed.  
cal_pre_scaler[4:0] x 16ms (1-period)  
cal_pre_scaler  
1 1111  
10.2.7 Global option control register 2  
Type: R/W  
Address  
38h  
Register Name  
global_ctrl2  
Bit7  
Bit6  
Bit5  
Bit4  
Bit3  
Bit2  
Bit1  
Bit0  
sin_mult  
i_mode  
imp_sel  
cal_hold_time  
0
clk_off  
Description  
This register controls the global options of ANMG04.  
Bit name  
Reset value  
Function  
System clock off control bit.  
0 : Not clock off  
clk_off  
0
1 : Clock off  
Output expiration Time control.  
cal_hold_tim  
e
cal_hold_time[3:0] x 4 ( seconds)  
The output expiration time is infinite when the data of the “cal_hold_time”  
is “0000”.  
1111  
Single/Multi output operation mode selection bit.  
0 : Multi output mode  
sin_multi_mo  
de  
0
1
1 : Single output mode  
Impedance of the sensing wire of all channels control bit.  
0 : High impedance  
imp_sel  
1 : Low impedance except sensing period.  
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10.2.8 Sensitivity register  
Type: R/W  
Address  
39H  
Register Name  
sensitivity1  
sensitivity2  
sensitivity3  
sensitivity4  
Bit7  
Bit6  
Bit5  
Bit4  
Bit3  
Bit2  
Bit1  
Bit0  
sensitivity01  
sensitivity02  
sensitivity03  
sensitivity04  
3AH  
3BH  
3CH  
Description  
This register controls the global options of ANMG04.  
Bit name  
Reset value  
Function  
Sensitivities of each channel.  
sensitivity0x  
0001 1100  
Sensitivity of CSx channel: {(sensitivity0x[7:0] x 0.025)} (%).  
10.2.9 Calibration speed control register  
Type: R/W  
Address  
41H  
Register Name  
cal_speed  
Bit7  
Bit6  
Bit5  
Bit4  
Bit3  
Bit2  
Bit1  
Bit0  
rnd_bf_up  
rnd_bf_down  
sen_bf_up  
sen_bf_down  
Description  
Calibration speed can be controlled by this ‘cal_speed’ register at BF mode.  
Bit name  
Reset value  
Function  
Sense channel down calibration speed at BF mode control bits.  
00 : Fastest  
01 : Fast  
sen_bf_down  
10  
10 : Normal  
11 : Slow  
Sense channel up calibration speed at BF mode control bits.  
00 : Fastest  
01 : Fast  
10 : Normal  
11 : Slow  
sen_bf_up  
rnd_bf_down  
rnd_bf_up  
01  
10  
01  
RND channel down calibration speed at BF mode control bits.  
00 : Fastest  
01 : Fast  
10 : Normal  
11 : Slow  
RND channel up calibration speed at BF mode control bits.  
00 : Fastest  
01 : Fast  
10 : Normal  
11 : Slow  
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10.2.10 Calibration speed control register at BS mode  
Type: R/W  
Address  
42H  
Register Name  
cal_BS_speed  
Bit7  
Bit6  
Bit5  
Bit4  
Bit3  
Bit2  
Bit1  
Bit0  
rnd_bs_up  
rnd_bs_down  
sen_bs_up  
sen_bs_down  
Description  
Calibration speed can be controlled by this ‘cal_BS_speed’ register at BS mode.  
Bit name  
Reset value  
Function  
Sense channel down calibration speed at BS mode control bits.  
00 : Fastest  
01 : Fast  
sen_bs_down  
10  
10 : Normal  
11 : Slow  
Sense channel up calibration speed at BS mode control bits.  
00 : Fastest  
01 : Fast  
10 : Normal  
11 : Slow  
sen_bs_up  
rnd_bs_down  
rnd_bs_up  
01  
10  
01  
RND channel down calibration speed at BS mode control bits.  
00 : Fastest  
01 : Fast  
10 : Normal  
11 : Slow  
RND channel up calibration speed at BS mode control bits.  
00 : Fastest  
01 : Fast  
10 : Normal  
11 : Slow  
10.2.11 LED luminance control register  
Type: R/W  
Address  
43h  
Register Name  
PWM_ctrl1  
Bit7  
Bit6  
Bit5  
Bit4  
Bit3  
Bit2  
Bit1  
Bit0  
pwm_d2  
pwm_d4  
pwm_d1  
pwm_d3  
44h  
PWM_ctrl2  
Description  
LED luminance can be controlled by “PWM_ctrlx” register.  
Bit name  
Reset value  
Function  
The LED PWM control bits of Dx port.  
0000 : The minimum low duty  
pwm_dx  
0000  
1111 : The maximum low duty  
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10.2.12 Port mode control register  
Type: R/W  
Address  
Register Name  
port_mode  
Bit7  
Bit6  
Bit5  
Bit4  
Bit3  
Bit2  
Bit1  
Bit0  
pmod_d  
4
pmod_d  
3
pmod_d  
2
pmod_d  
1
-
-
-
-
4Fh  
Description  
This register controls the mode of output port.  
Bit name  
Reset value  
Function  
Select the output port operation mode of each channel.  
0 : Parallel output mode  
pmod_dx  
0
1 : LED drive mode  
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10.2.13 Sense, reference count read register  
Type: R  
Address  
50h  
Register Name  
rd_ch_H1  
Bit7  
Bit6  
Bit5  
Bit4  
Bit3  
Bit2  
Bit1  
Bit0  
rd_ch_H1  
rd_ch_L1  
-
-
-
-
-
-
rd_ch_L1  
51h  
touch_percent[25:18]  
touch_percent[17:10]  
touch_percent[9:2]  
rd_ch_H2  
Percent_H  
Percent_M  
Percent_L  
rd_ch_H2  
52h  
53h  
54h  
56h  
rd_ch_L2  
-
-
-
-
-
-
rd_ch_L2  
57h  
Description  
ANMG04 provides the special function to read sense count of each channels or reference count.  
Bit name  
Reset value  
Function  
Read channel indication register.  
00000001 : -  
00000010 : R.N.D channel  
00000100 : CS1 channel  
00001000 : CS2 channel  
00010000 : CS3 channel  
00100000 : CS4 channel  
01000000 : -  
rd_ch_H1  
Read only  
10000000 : -  
Read channel indication register.  
rd_ch_L1  
Read only  
01 : -  
10 : -  
The percent data of RND channel and sense channels.  
[25:18] bits of the touch percent data.  
touch_percent[24:17]  
touch_percent[16:9]  
touch_percent[8:1]  
Read only  
Read only  
Read only  
The percent data of RND channel and sense channels.  
[17:10] bits of the touch percent data.  
The percent data of RND channel and sense channels.  
[9:2] bits of the touch percent data.  
Read channel indication register.  
00000001 : -  
00000010 : R.N.D channel  
00000100 : CS1 channel  
00001000 : CS2 channel  
00010000 : CS3 channel  
00100000 : CS4 channel  
01000000 : -  
rd_ch_H2  
rd_ch_L2  
Read only  
Read only  
10000000 : -  
Read channel indication register.  
01 : -  
10 : -  
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11 Recommended Circuit Diagram  
11.1 ANMG04 (14 SOP)  
ANMG04 (14 SOP) Application Example Circuit  
ANMG04 is reset by internal reset circuit. VDD voltage rising time should be shorter than 100msec  
for proper operation.  
Normally, R.N.D pin dose not connection to anywhere. But, in radio frequency noise environment,  
R.N.D pin must form a pattern line on PCB.  
The VDD periodic voltage ripple over 50mV and the ripple frequency is lower than 10 kHz can cause  
wrong sensitivity calibration. To prevent above problem, power (VDD, GND) line of touch circuit  
should be separated from other circuit. Especially LED driver power line or digital switching circuit  
power line certainly should be treated to be separated from touch circuit.  
The CS patterns also should be routed as short as possible and the width of line might be about  
0.25mm.  
Parallel capacitor of CS pin could be useful in case detail sensitivity mediation is required such as for  
complementation sensitivity difference between channels.  
Serial connection resistor of CS pins may be used to avoid mal-function from external surge and ESD  
and the closer to IC(ANMG04), the stronger immunity against mal-function and ESD is.  
The CVDD capacitor that is between VDD and GND is an obligation.  
CVDD and CLCAP capacitors should be located as close as possible from ANMG04.  
The CS pattern routing should be formed by bottom metal (opposite metal of touch PAD).  
The empty space of PCB must be filled with GND pattern to strengthen GND pattern and to prevent  
external noise from interfere with sensing frequency.  
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11.2 Example Power Line Split Strategy PCB Layout  
A. Not split power Line (Bad power line design)  
The noise that is generated by AC load or relay can be loaded at 5V power line.  
A big inductance might be appeared in case of the connection line between main board and display  
board is too long, moreover the voltage ripple could be generated by LED (LCD) display driver at  
VDD (5V).  
B. Split power Line (One 5V regulator used) Recommended  
C. Split power Line (Separated 5V regulator used) Strongly recommended  
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12 MECHANICAL DRAWING  
12.1 Mechanical Drawing of ANMG04 (14 SOP)  
13  
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MARKING DESCRIPTION  
13.1 Marking Description of ANMG04 (14 SOP)  
Company Code : ADS  
AD Semiconductor  
Device Code : ANMG 04 SG  
Package Type  
Channel Number  
Touch Switch Group  
Year / Week Code : YY WW  
Manufacturing Week  
Manufacturing Year  
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NOTES:  
LIFE SUPPORT POLICY  
AD SEMICONDUCTOR’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE  
SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND  
GENERAL COUNSEL OF AD SEMICONDUCTOR CORPORATION  
The ADS logo is a registered trademark of ADSemiconductor  
2006 ADSemiconductor All Rights Reserved  
www.adsemicon.com  
www.adsemicon.co.kr  
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