BUF04 [ADI]
Closed-Loop High Speed Buffer; 闭环高速缓存
| 型号： | BUF04 |
| 厂家： | 
ADI |
| 描述： | Closed-Loop High Speed Buffer |
| 文件： | 总16页 (文件大小：440K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Closed-Loop
High Speed Buffer
a
BUF04*
FUNCTIONAL BLOCK DIAGRAMS
FEATURES
Bandwidth – 110 MHz
Slew Rate – 3000 V/s
Plastic DIP
8-Lead and Cerdip
(P, Z Suffix)
8-Lead Narrow-Body SO
(S Suffix)
Low Offset Voltage – <1 mV
Very Low Noise – < 4 nV/√Hz
Low Supply Current – 8.5 mA Mux
Wide Supply Range – ؎5 V to ؎15 V
Drives Capacitive Loads
Pin Compatible with BUF03
1
8
7
6
5
NULL
NC
IN
1
NULL
V+
BUF04
Top View
BUF04
2
3
4
OUT
NC
APPLICATIONS
V–
Instrumentation Buffer
RF Buffer
NC = NO CONNECT
Line Driver
High Speed Current Source
Op Amp Output Current Booster
High Performance Audio
High Speed AD/DA
GENERAL DESCRIPTION
High slew rate and very low noise and THD, coupled with wide
input and output dynamic range, make the BUF04 an excellent
choice for video and high performance audio circuits.
The BUF04 is a wideband, closed-loop buffer that combines
state of the art dynamic performance with excellent dc
performance. This combination enables designers to maximize
system performance without any speed versus dc accuracy
compromises.
The BUF04’s inherent ability to drive capacitive loads over a
wide voltage and temperature range makes it extremely useful
for a wide variety of applications in military, industrial, and
commercial equipment.
Built on a high speed Complementary Bipolar (CB) process for
better power performance ratio, the BUF04 consumes less than
8.5 mA operating from ±5 V or ±15 V supplies. With a 2000 V/µs
min slew rate, and 100 MHz gain bandwidth product, the
BUF04 is ideally suited for use in high speed applications where
low power dissipation is critical.
The BUF04 is specified over the extended industrial (–40°C to
+85°C) and military (–55°C to +125°C) temperature range.
BUF04s are available in plastic and ceramic DIP plus SO-8
surface mount packages.
Contact your local sales office for MIL-STD-883 data sheet and
availability.
Full ±10 V output swing over the extended temperature range
along with outstanding ac performance and high loop gain
accuracy makes the device useful in high speed data acquisition
systems.
*Patent pending.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
BUF04–SPECIFICATIONS
(@ V = ؎15.0 V, T = +25؇C unless otherwise noted)
ELECTRICAL CHARACTERISTICS
S
A
Parameter
Symbol
Conditions
Min
Typ
Max
Units
INPUT CHARACTERISTICS
Offset Voltage
VOS
IB
0.3
1.3
0.7
2.2
±13
30
1
4
5
10
mV
mV
µA
µA
V
–40°C ≤ TA ≤ +85°C
VCM = 0
–40°C ≤ TA ≤ +85°C
Input Bias Current
Input Voltage Range
Offset Voltage Drift
Offset Null Range
VCM
∆VOS/∆T
µV/°C
mV
±25
OUTPUT CHARACTERISTICS
Output Voltage Swing
VO
RL = 150 Ω,
±10.5 ±11.1
V
–40°C ≤ TA ≤ +85°C
RL = 2 kΩ,
–40°C ≤ TA ≤ +85°C
±10
±13
±13
±50
±11
V
V
V
mA
mA
±13.5
±13.15
±65
Output Current – Continuous
Peak Output Current
IOUT
IOUTP
Note 2
±80
TRANSFER CHARACTERISTICS
Gain
AVCL
NL
RL = 2 kΩ
0.995
0.995
0.9985 1.005
0.9980 1.005
0.005
V/V
V/V
%
–40°C ≤ TA ≤ +85°C
RL = 1 kΩ, VO = ±10 V
RL = 150 kΩ
Gain Linearity
0.008
%
POWER SUPPLY
Power Supply Rejection Ratio
PSRR
ISY
VS = ±4.5 V to ±18 V
–40°C ≤ TA ≤ +85°C
VO = 0 V, RL = ∞
76
76
93
93
6.9
6.9
dB
dB
mA
mA
Supply Current
8.5
8.5
–40°C ≤ TA ≤ +85°C
DYNAMIC PERFORMANCE
Slew Rate
Bandwidth
Bandwidth
Bandwidth
SR
RL = 2 kΩ, CL = 70 pF
2000
3000
110
110
110
60
V/µs
MHz
MHz
MHz
ns
BW
BW
BW
–3 dB, CL = 20 pF, RL = ∞
–3 dB, CL = 20 pF, RL = 1 kΩ
–3 dB, CL = 20 pF, RL = 150 Ω
Settling Time
VIN = ±10 V Step to 0.1%
Differential Phase
f = 3.58 MHz, RL = 150 Ω
f = 4.43 MHz, RL = 150 Ω
f = 3.58 MHz, RL = 150 Ω
f = 4.43 MHz, RL = 150 Ω
0.02
0.03
0.014
0.008
3
Degrees
Degrees
%
%
pF
Differential Gain
Input Capacitance
NOISE PERFORMANCE
Voltage Noise Density
Current Noise Density
en
in
f = 1 kHz
f = 1 kHz
4
2
nV/√Hz
pA/√Hz
NOTE
1Long term offset voltage is guaranteed by a 1000 hour life test performed on three independent lots at +125°C with an LTPD of 1.3.
Specifications subject to change without notice.
–2–
REV. 0
BUF04
ELECTRICAL CHARACTERISTICS (@ VS = ؎5.0 V, TA = +25؇C unless otherwise noted)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
INPUT CHARACTERISTICS
Offset Voltage
VOS
IB
0.8
1.0
0.15
1.6
2.0
4
5
mV
mV
µA
–40°C ≤ TA ≤ +85°C
VCM = 0 V
–40°C ≤ TA ≤ +85°C
Input Bias Current
10
µA
Input Voltage Range
Offset Voltage Drift
Offset Null Range
VCM
∆VOS/∆T
±3.0
30
±25
V
µV/°C
mV
OUTPUT CHARACTERISTICS
Output Voltage Swing
VO
RL = 150 Ω,
±3.0
V
–40°C ≤ TA ≤ +85°C
RL = 2 kΩ,
–40°C ≤ TA ≤ +85°C
±2.75 ±3.00
V
V
V
mA
mA
±3.0
±3.0
±40
±3.6
±3.35
Output Current - Continuous
Peak Output Current
IOUT
IOUTP
Note 2
±75
TRANSFER CHARACTERISTICS
Gain
AVCL
NL
RL = 2 kΩ,
–40°C ≤ TA ≤ +85°C
RL = 1 kΩ
0.995
0.995
0.9977 1.005
1.005
0.005
V/V
V/V
%
Gain Linearity
POWER SUPPLY
Power Supply Rejection Ratio
PSRR
ISY
VS = ±4.5 V to ±18 V
–40°C ≤ TA ≤ +85°C
VO = 0 V, RL = ∞
76
76
93
93
6.60
6.70
dB
dB
mA
mA
Supply Current
8
8
–40°C ≤ TA ≤ +85°C
DYNAMIC PERFORMANCE
Slew Rate
Bandwidth
Bandwidth
Bandwidth
SR
RL = 2 kΩ, CL = 70 pF
2000
100
100
V/µs
BW
BW
BW
–3 dB, CL = 20 pF, RL = ∞
–3 dB, CL = 20 pF, RL = 1 kΩ
–3 dB, CL = 20 pF, RL = 150 Ω
f = 3.58 MHz, RL = 150 Ω
f = 4.43 MHz, RL = 150 Ω
f = 3.58 MHz, RL = 150 Ω
f = 4.43 MHz, RL = 150 Ω
MHz
MHz
MHz
Degrees
Degrees
%
100
Differential Phase
0.13
0.15
0.04
0.06
Differential Gain
%
NOISE PERFORMANCE
Voltage Noise Density
Current Noise Density
en
in
f = 1 kHz
f = 1 kHz
4
2
nV/√Hz
pA/√Hz
NOTE
1Long term offset voltage is guaranteed by a 1000 hour life test performed on three independent lots at +125 °C, with an LTPD of 1.3.
Specifications subject to change without notice.
REV. 0
–3–
BUF04
WAFER TEST LIMITS
Parameter
(@ VS = ؎15.0 V, TA = +25؇C unless otherwise noted)
Symbol
Conditions
Limit
Units
Offset Voltage
VOS
VOS
IB
PSRR
VO
VS = ±15 V
VS = ±5 V
VCM = 0 V
V = ±4.5 V to ±18 V
RL = 150 Ω
1
2
5
76
±10.5
8.5
1 ± 0.005
mV max
mV max
µA max
dB
V min
mA max
V/V
Input Bias Current
Power Supply Rejection Ratio
Output Voltage Range
Supply Current
ISY
AVCL
VO = 0 V, RL = 2 kΩ
VO = ±10 V, RL = 2 kΩ
Gain
NOTE
Electrical tests and wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard
product dice. Consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing.
ABSOLUTE MAXIMUM RATINGS1
DICE CHARACTERISTICS
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±18 V
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±18 V
Maximum Power Dissipation . . . . . . . . . . . . . . . See Figure 16
Storage Temperature Range
Z Package . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +175°C
P, S Package . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Operating Temperature Range
BUF04Z . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to +125°C
BUF04S, P . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Junction Temperature Range
Z Package . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
P, S Package . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature Range (Soldering 60 sec) . . . . . . . . +300°C
2
BUF04 Die Size 0.075 x 0.064 inch, 5,280 Sq. Mils
Substrate (Die Backside) Is Connected to V+
Transistor Count 45.
Package Type
θJA
θJC
Units
8-Pin Cerdip (Z)
8-Pin Plastic DIP (P)
8-Pin SOIC (S)
148
103
158
16
43
43
°C/W
°C/W
°C/W
NOTES
1Absolute maximum ratings apply to both DICE and packaged parts, unless
otherwise noted.
2θJA is specified for the worst case conditions, i.e., θJA is specified for device in socket
for cerdip, P-DIP, and LCC packages; θJA is specified for device soldered in circuit
board for SOIC package.
ORDERING GUIDE
Temperature
Range
Package
Description
Package
Option
Model
BUF04AZ/883
BUF04GP
BUF04GS
–55°C to +125°C Cerdip
Q-8
N-8
SO-8
DICE
–40°C to +85°C
–40°C to +85°C
+25°C
Plastic DIP
SO
DICE
BUF04GBC
–4–
REV. 0
Typical Performance Characteristics–
BUF04
200
150
120
V = ±15V
S
V
= ±15V
S
315 CERDIPS
315 PLASTIC DIPS
= +25°C
160
T
= +25°C
T
A
A
120
80
90
60
40
30
0
–0.1
0
0.0
0.1
0.2
0.3
0.4
0.5
0.6
–0.15
–0.1
–0.5
0
0.5
0.1
0.15
0.2
OFFSET – mV
OFFSET – mV
Figure 1. Input Offset Voltage (VOS) Distribution @
Figure 4. Input Offset Voltage (VOS) Distribution @
±15 V, P-DIP
±15 V, Cerdip
125
125
V
= ±5V
V = ±5V
S
S
315 PLASTIC DIPS
= +25°C
315 CERDIPS
T = +25°C
A
100
100
T
A
75
50
75
50
25
0
25
0
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
OFFSET – mV
OFFSET – mV
Figure 2. Input Offset Voltage (VOS) Distribution @
Figure 5. Input Offset Voltage (VOS) Distribution @
±5 V, P-DIP
±5 V, Cerdip
2.0
0
V
= ±5V
S
1.0
–1.0
±5V
V
= ±15V
S
0
±15V
–2.0
–3.0
–4.0
–1.0
–2.0
–3.0
–4.0
–5.0
–5.0
–6.0
–6.0
–75
–50
–25
0
25
50
75
100
125
–75
–50
–25
0
25
50
75
100
125
TEMPERATURE – °C
TEMPERATURE – °C
Figure 3. Input Offset Voltage (VOS) vs. Temperature
Figure 6. Input Bias Current vs. Temperature
REV. 0
–5–
BUF04
8.0
50
45
40
35
30
25
20
15
10
5
T
= +25°C
A
7.5
7.0
V
= ±18V
S
V
= ±5V
S
V
= ±15V
S
6.5
6.0
V
= ±5V
S
V
= ±15V
S
0
5.5
–75
–50
–25
0
25
50
75
100
125
1k
10k
100k
1M
10M
100M
FREQUENCY – Hz
TEMPERATURE – °C
Figure 10. Output Impedance vs. Frequency
Figure 7. Supply Current vs. Temperature
5.0
15
V
= ±15V
V
= ±5V
R
R
= 2k Ω
= 1k Ω
4.5
4.0
S
14
13
S
L
Ω
= 2k , 1kΩ
R
L
L
3.5
3.0
12
11
Ω
= 150
R
L
Ω
R
= 150
L
R
= 150Ω
L
Ω
= 150
R
–3.0
–3.5
–4.0
–4.5
–5.0
–11
–12
–13
–14
–15
L
Ω
R
0
= 2k , 1kΩ
L
R
= 1k Ω
L
Ω
R
= 2k
25
L
0
–75
–50
–25
25
50
75
100
125
–75
–50
–25
50
75
100
125
TEMPERATURE – °C
TEMPERATURE – °C
Figure 8. Output Voltage Swing vs. Temperature @ ±15 V
Figure 11. Output Voltage Swing vs. Temperature @ ±5 V
16
14
5
4
12
POSITIVE
SWING
10
POSITIVE
SWING
3
8
ABS NEGATIVE
SWING
ABS NEGATIVE
SWING
2
6
V
T
= ±15V
= +25°C
S
4
2
0
V
T
= ±5V
= +25°C
S
A
1
0
A
10
100
1k
10k
10
100
1k
10k
100k
1M
LOAD RESISTANCE – Ω
LOAD RESISTANCE – Ω
Figure 9. Maximum VOUT Swing vs. Load @ ±5 V
Figure 12. Maximum VOUT Swing vs. Load @ ±15 V
–6–
REV. 0
BUF04
1.5
1.0
0.5
0
0.5
0
T
MAX = 150°C
FREE AIR
NO HEAT SINK
P DIP
= 103°C/W
J
Θ
JA
T
= +25°C
A
CERDIP
= 148°C/W
Θ
JA
–0.5
–1.0
SOIC
= 158°C/W
Θ
JA
–1.5
–2.0
0
25
50
75 85
100
125
–10
–8
–6
–4
–2
0
2
4
6
8
10
TEMPERATURE –
°C
COMMON MODE VOLTAGE – Volts
Figure 13. Bias Current vs. Input Voltage
Figure 16. Maximum Power Dissipation vs.
Ambient Temperature
100
100
90
80
70
60
50
40
30
20
10
0
T
V
= +25°C
= ±5, ±15V
A
S
– PSRR
10
+PSRR
0
1
10
100
1k
10k
100k
1M
1k
10k
100k
1M
10M
100M
FREQUENCY – Hz
FREQUENCY – Hz
Figure 14. Power Supply Rejection vs. Frequency
Figure 17. Input Noise Voltage vs. Frequency
6000
6000
V
= ±15V
S
V = ±15V
S
5000
5000
4000
3000
2000
1000
0
SWING = ±10V
= +25°C
T
A
+EDGE
–EDGE
POSITIVE
SLEW RATE
4000
3000
2000
1000
0
NEGATIVE
SLEW RATE
0
50
100
150
200
250
–75
–50
–25
25
50
75
100
125
0
CAPACITIVE LOAD – pF
TEMPERATURE – °C
Figure 15. Slew Rate vs. Temperature
Figure 18. Slew Rate vs. Capacitive Loads
REV. 0
–7–
BUF04
–45
–45
150
150
125
T
V
= +25°C
= ±5V
T
V
= +25°C
= ±15V
A
A
S
–67.5
–90
S
–67.5
–90
125
BANDWIDTH
100
75
100
75
Ω
R = 150
L
PHASE @
Ω
= 150
R
L
–112.5
–112.5
R
= 2kΩ
L
PHASE @
Ω
= 2k
R
–135
–135
–157.5
–180
50
25
50
25
L
BANDWIDTH
PHASE
100
–157.5
–180
250
0
0
0
50
100
150
200
0
50
150
200
250
CAPACITANCE – pF
CAPACITANCE – pF
Figure 19. Bandwidth and Phase vs.
Figure 22. Bandwidth & Phase vs.
Capacitive Loads @ ±5 V
Capacitive Loads @ ±15 V
140
200
150
R = 2kΩ
L
T
= +25°C
A
130
V
= ±15V
S
–55°C
120
+25°C
110
100
50
0
+125°C
100
90
80
±5
±10
±15
100
1k
10k
SUPPLY VOLTAGE –Volts
RESISTIVE LOAD – Ω
Figure 20. Bandwidth vs. Supply Voltage and
Temperature
Figure 23. Bandwidth vs. Loads
1.5
0.075
0.050
0.025
0
1.5
6
4
2
0
V
V
= ±15V
V
V
= ±15V
= 0.1V
S
S
= 0.1V
IN
RMS
IN
RMS
1.0
0.5
0
FREQUENCY = 10MHz
= 2kΩ
1.0
0.5
0
FREQUENCY = 10MHz
R
R
Ω
= 150
L
PHASE
L
GAIN
GAIN
–0.025
–0.050
–0.5
–1.0
–0.5
–1.0
–2
–4
PHASE
–0.075
–1.5
–1.5
–6
–10
–8
–6
–4
–2
2
4
6
8
10
–10
–8
–6
–4
–2
2
4
6
8
10
0
0
OUTPUT VOLTAGE – Volts
OUTPUT VOLTAGE – Volts
Figure 24. Gain and Phase Deviation, RL = 2 kΩ
Figure 21. Gain and Phase Deviation, RL = 150 Ω
–8–
REV. 0
BUF04
DLY
375.0ns
100
90
100
90
INPUT
INPUT
(50mV/DIV)
(2V/DIV)
OUTPUT
(50mV/DIV)
OUTPUT
(2V/DIV)
10
10
0%
0%
50mV
50mV
10ns
2V
2V
50ns
V
= ±15V, R = 2kΩ, C = 15pF
L L
S
V
= ±15V, R = 2kΩ, C = 15pF
L L
S
Figure 25. Small-Signal Transient Response
Figure 26. Large-Signal Transient Response
AUDIO PRECISION BUF04 THD+N (%) vs FREQ (Hz)
0.1
07 MAR 93 21:31:53
12
V
T
= ±15V
S
9
6
3
= +25°C
A
A
: V = 7.75V
IN
R
R
= 150W
= 600W
: V = 0.775V
IN
R
R
= 150W
= 600W
C
D
V
= ±15V
rms,
L
rms,
L
S
Ω
R
= 150
L
LPF=80kHz
B
: V = 7.75V
IN
: V = 0.775V
IN
rms,
L
rms,
L
A
C
= 100pF
L
0.010
C
= 50pF
C
L
C
= 0pF
0
L
B
C
D
–3
–6
Ω
150
10
0.001
D
BUF04
Ω
C
L
–9
T
–12
10k
0.0001
20
100
1k
10k
20k
100k
1M
10M
100M
1000M
FREQUENCY – Hz
Figure 27. THD + Noise vs. Amplitude
FUNCTIONAL DESCRIPTION
Figure 28. Bandwidth vs. Frequency
The BUF04 is a closed-loop voltage buffer based on a current
feedback architecture. Its high open-loop transimpedance, high
output current drive capability, and its low input offset voltage
makes it useful in a variety of applications, such as buffering the
inputs of sampling and flash A/D converters, audio and video
line drivers, active filters, and precision op amp hoosters.
Q11
Q13
Q5
Q7
Q3
C1
Q9
R
100Ω
FB
D1
D2
A transistor-level equivalent circuit for the BUF04 is illustrated
in Figure 29. The input stage consists of a pair of emitter
follower transistors, Q1 and Q2, whose outputs drive a second
set of transistors, Q3 and Q4. The emitters of Q3 and Q4 are
connected together through diodes, D1 and D2, to form a low
impedance input for the feedback signal (in current mode) from
the output stage. The outputs of Q3 and Q4 are then
“mirrored” to Q5 and Q6 which form the gain stage of the
BUF04. The signal is taken from the collectors of Q5 and Q6
which drive a “Darlington-connected” output stage made up of
transistors Q7-Q10. Three R-C networks (R1–C1, R2–C2, and
R3–C3) form feed-forward paths which bypass certain sections
of the BUF04 for improved high frequency performance and
capacitive load drive capability. Since the signal conveyed
internally in the BUF04 is a current, the frequency response
and slew rate of the BUF04 are insensitive to supply voltage
variations.
Ω
20
C3
R3
Q2
V
IN
V
OUT
Q1
Ω
R2
20
Q10
Q4
C2
Q8
Q14
Q6
Q12
Figure 29. Transistor-Level Equivalent Circuit
An interesting feature of the BUF04 architecture is the use of
“slew-enhancement” transistors, Q11–Q14. Under normal small
signal (VIN < 2 Vbes) conditions, these transistors are normally
“OFF.” In large signals, high speed transient applications where
the input signal is > 2 Vbes, these transistors turn on and literally
“brute-force” the output to follow the input. When the input
signal drops below 2 Vbes, the transistors return to their
normally “OFF” state.
REV. 0
–9–
BUF04
A two-terminal equivalent circuit of the BUF04 is shown in
Figure 30 where the transistor-level equivalent circuit is reduced
to its essential elements. The input stage develops a signal
current, IIN, that is replicated by an internal current conveyor so
as to flow through Rt, the transimpedance of the BUF04. The
voltage developed across Rt is buffered by a unity-gain output
voltage follower. With an open-loop Rt of 400 kΩ and an RIN of
30 Ω, the voltage gain of the BUF04, given by the ratio Rt/RIN is
approximately 13,000—accurate to approximately 13.5 bits.
The BUF04’s open-loop ac transimpedance response is
determined by the open-loop pole formed by Rt and Ct. Since
Ct is typically 8 pF, the open-loop pole occurs at approximately
50 kHz.
To minimize the effects of high-frequency coupling, circuits
must be built with short interconnect leads, and large ground
planes should he used whenever possible to provide a low
resistance, low-inductance circuit path. Sockets should be
avoided because the increased interlead capacitance can degrade
bandwidth and stability. If sockets are necessary, individual pin
sockets (oftentimes called “cage jacks,” AMP Part No.
5-330808-3 or 5-330808-6) should be used. They contribute far
less stray reactance than molded socket assemblies.
Offset Voltage Nulling
Although the offset voltage of the BUF04 is very low (1 mV,
maximum) for such a high speed buffer, the circuit shown in
Figure 32 can be used if additional offset voltage nulling is
required. A potentiometer ranging from 1 k to 10 k can be used
for VOS nulling; with a 10 kΩ potentiometer, the trim range is
±30 mV.
V
X1
IN
R
t
V
I
C
XI
OUT
IN
t
I
V+
IN
10µF
R
IN
TRIM RANGE
±30mV
0.1µF
R
FB
1
10k
8
R
= 30Ω
IN
7
3
R = 400 k
Ω
V
V
OUT
t
IN
BUF04
6
C = 8pF
t
RFB = 100Ω
0.1µF
4
Figure 30. Current-Feedback Functional Equivalent
Circuit of the BUF04
10µF
Grounding and Bypassing Considerations
V–
To take full advantage of the BUF04’s very wide bandwidth,
high slew rates, and dynamic range capabilities requires due
diligence with regard to supply bypassing. In high speed circuits,
the supply bypassing network must provide a very low impedance
return path for currents flowing to and from the load network.
As with any high speed application, multiple bypassing is always
recommended. A 10 µF tantalum electrolytic in parallel with a
0.1 µF ceramic capacitor is sufficient for most applications. For
those high speed applications where output load currents
approach 50 mA, small valued resistors (1.1 Ω to 4.7 Ω) in
series with the tantalum capacitors may improve circuit
transient response by damping out the capacitor’s self-
inductance. Figure 31 illustrates bypassing recommendations.
Figure 32. Optional Offset Voltage Nulling Scheme
APPLICATIONS
Output Short-Circuit Protection
To optimize the transient response and output voltage swing of
the BUF04, internal output short-circuit current limiting was
omitted. Although the BUF04 can provide continuous output
currents of 50 mA without protection, direct connection of the
BUF04’s output to ground or to the supplies will destroy the
device. An active current limit technique, illustrated in Figure
33, provides the necessary short-circuit protection while
retaining full dc output voltage swing to the load.
+15V
10µF
V+
10µF
R1
RSC1
≥10Ω
0.1µF
2N2905
KELVIN RETURN
FOR LOAD CURRENT
2N2905
SET ISC +(ISC–) <60mA,
CONTINUOUS
0.1µF
7
0.6V
RSC1 (RSC2) =
6
3
ISC + (ISC–)
V
7
V
IN
BUF04
4
OUT
6
3
V
V
OUT
R
IN
R
BUF04
S
L
0.1µF
0.1µF
Ω
6.2k
0.01µF
4
10µF
R2
2N2219
KELVIN RETURN
FOR LOAD CURRENT
2N2219
10µF
V–
RSC2
≥10Ω
NOTE
USE SHORT LEAD LENGTHS (<5mm)
Figure 31. Recommended Power-Supply Bypassing
–15V
Figure 33. Short-Circuit Current Limiting Using
Current Sources
–10–
REV. 0
BUF04
Output Current Transient Recovery
t
59.00ns
∆
Settling characteristics of high speed buffers also include the
buffer’s ability to recover, i.e., settle, from a transient output
current load condition. When driving the input of an A/D
converter, especially the successive-approximation converter
types, the buffer must maintain a constant output voltage under
dynamically changing load current conditions. In these types of
converters, the comparison point is usually diode-clamped, but
it may deviate several hundred millivolts resulting in high
frequency modulation of the A/D input current. Open-loop and
closed-loop buffers (also, op amps configured as followers) that
exhibit high closed-loop output impedances and/or low unity
gain crossover frequencies recover very slowly from output load
current transients. This slow recovery leads to linearity errors or
missing codes because of errors in the instantaneous input volt-
age. Therefore, the buffer (or op amp) chosen for this type of
application should exhibit low output impedance and high unity
gain bandwidth so that its output has had a chance to settle to
its nominal value before the converter makes its comparison.
25mA
I
SOURCE
100
90
(4mA/DIV)
35mA
10
V
OUT
0%
(5mV/DIV)
100mV
5mV
20ns
Figure 35. BUF04’s Output Load Current Recovery Time
Terminated Line Drivers
The BUF04’s high output current, large slew rate, and wide
bandwidth all combine to make it an ideal device for high speed
line driver applications. As shown in Figure 36, the BUF04 can
be configured for driving doubly terminated 50 Ω and 75 Ω
cables. To optimize the circuit’s pulse response, a capacitor, CT
(CX + CTRIM), is connected across the series back termination.
The BUF04 can drive a 50 Ω line to ±2.5 V and a 75 Ω line to
±3.75 V when operating on ±15 V supplies.
The circuit in Figure 34 illustrates a settling measurement
circuit for evaluating the recovery time of high speed buffers
from an output load current transient. The input to the buffer is
grounded for ease of measuring the recovery time, and two
resistors are used to sum steady-state and transient load currents
at the output. As a worst-case condition, R1, was chosen such
that the BUF04 would source (or sink) a steady-state current of
25 mA. R2 was then chosen to add a 10 mA transient current
upon the steady-state value. To set accurately the nodal voltages
internal to the BUF04, the supply voltages were offset by the
voltage applied to R1. Because of its high transimpedance, wide
bandwidth, and low output impedance, the BUF04 exhibits an
extremely fast recovery time of 60 ns to 0.01%, as shown in
Figure 34. Results were identical regardless whether the BUF04
was sourcing or sinking current.
C
T
C
X
6'
COAX
R
X
6
3
V
IN
BUF04
R
R
L
S
Z
COAX
R , R
S
50Ω
75Ω
R
C
C
T
O
L
X
X
50Ω RG-58
75Ω RG-59
50
75
91pF 3–15pF
62pF 3–15pF
Figure 36. Line Driver Configuration
Low-Pass Active Filter
In many signal-conditioning applications, filters are required to
band-limit noise or altogether eliminate other unwanted signals
prior to conversion. Often, high frequency filters are needed for
these applications; however, there are few op amps that exhibit
the high open-loop gain and wide unity-gain crossover
frequency required for these applications. As illustrated in
Figure 37, the BUF04 and a handful of passive components can
be configured as a high frequency, low-pass active filter. Since
the filter configuration is a unity-gain Sallen-Key topology, the
BUF04 is particularly well suited for this application. In this
circuit, an additional resistor, R3, was added to prevent
interaction between C2 and the BUF04’s input capacitance.
V+
10µF
0.1µF
TP2
TP1
7
R2
250Ω
6
3
V
BUF04
IN
R1
200Ω
SOURCE: 0➔ –2.5 V
SINK: 0➔ +2.5V
0.1µF
4
V
LOAD
10µF
SOURCE: –5V
SINK: +5V
V–
Figure 34. Transient Output Load Current Test Circuit
C1*
44pF (22pF x 2)
R1
R2
R3
499Ω
499Ω
47Ω
6
3
V
V
IN
OUT
BUF04
C2*
22pF
* SILVERED MICA OR
DIPPED CERAMIC
1
C1
;
Q =
4 · C2
W
=
R1 · R2 · C1 · C2
O
Figure 37. A 10 MHz Low-Pass Active Filter
REV. 0
–11–
BUF04
Paralleling BUF04s for Increased Load Drive Capability
In applications where continuous output currents greater than
50 mA are required or where heat management is an issue, a
number of BUF04s can be connected in parallel to reduce the
drive requirement of any one buffer. An example of one such
application is illustrated in Figure 39. In this circuit, the
BUF04s are required to drive a doubly terminated 50 Ω line to
±5 V. This type of a load for a single BUF04 would certainly
cause a power dissipation problem. Parallel operation results in
lower input and output impedances and increased bias currents;
on the other hand, input equivalent noise voltage is reduced and
input offset voltage remains unchanged.
Operation Within an Op Amp Feedback Loop
The BUF04 is well suited as a current booster or isolation
buffer within the closed loop of precision op amps such as the
OP177, the OP97, the OP27, or the OP77. Since the BUF04 is
a closed loop voltage buffer, no interstage coupling resistor
between the op amp and the buffer’s input is required for circuit
stability. The wide bandwidth and high slew rate of the BUF04
assure that the loop has the characteristics of the op amp; hence,
no additional rolloff is required.
R1
100
R2
2
3
6
6
R1
3
R3
OP177
BUF04
V
OUT
47Ω
100Ω
3
6
V
R
500Ω
BUF04
BUF04
IN
C
L
L
1000pF
±5V
GAIN
10
100
R2 (kΩ)
V
IN
V
OUT
1
10
100
±10V
R
R
50Ω
L
S
R2
47Ω
R4
100Ω
50Ω
3
6
1000
Figure 38. BUF04 as Booster Stage for a Precision Op Amp
Figure 39. Paralleling BUF04s for High Output Currents
Overdrive Recovery and Phase Reversal
In applications where the inputs could be driven to the supply
rails, the BUF04 recovers in 10 ns from positive or negative
overdrive. The BUF04 does not exhibit any output voltage
phase reversal when the input signal exceeds its input voltage
range.
–12–
REV. 0
BUF04
* BUF04 SPICE Macro-model
*
7/93, Rev. A
JCB / PMI
* POLE AT 200 MHz
*
*
R11
C7
G7
*
20
20
97
97
97
20
1E6
0.759E-15
12 22 1E-6
* Copyright 1993 by Analog Devices, Inc.
*
*
* Node assignments
*
*
*
*
*
* POLE AT 200 MHz
*
noninverting input
positive supply
R12
C8
G8
*
21
21
97
97
97
21
1E6
0.759E-15
20 22 1E-6
negative supply
output
*
* OUTPU T STAGE
*
.SUBCKT BUF04
1
99
50
6
*
FSY
R13
R14
R15
R16
L2
G11
G12
V5
99
22
22
27
27
27
27
50
23
27
21
24
97
70
72
71
97
50
99
50
99
50
6
99
27
27
24
23
21
70
71
70
97
72
POLY(2) V7 V8 1.85E-3 1 1
16.67E3
16.67E3
80
80
10E-9
99 21 12.5E-3
21 50 12.5E-3
3.3
3.3
DX
DX
27 21 12.5E-3
DX
DX
DC 0
DC 0
* INPUT STAGE
*
R1
R2
V1
D1
V2
D2
I1
99
10
99
9
11
10
99
4
50
99
8
10
5
8
50
9
200
200
4.4
DX
4.4
8
50
11
5
50
3
3
61
7
61
7
99
50
2
DX
1.8E-3
1.8E-3
5
4
30
V6
I2
D5
D6
G10
D7
D8
V7
Q1
Q2
Q3
Q4
R3
R4
CP1
CP2
RFB
*
QP
QN
QN
QP
30
50E3
50E3
14E-15
14E-15
100
4
61
7
V8
*
* MODELS USED
*
.MODEL QN NPN(BF= 1000 IS= 1E-15)
.MODEL QP PNP(BF= 1000 IS= 1E-15)
.MODEL DX D(IS= 1E-15)
6
* INPUT ERROR SOURCES
*
IB1
VOS
LS1
CS1
CS2
*
99
3
30
99
99
1
1
2
2
1
0.7E-6
0.7E-6
1E-9
2.0E-12
3.0E-12
.ENDS BUF04
EREF 97
*
0
22 0 1
* TRANSCONDUCTANCE STAGE
*
R5
C3
G1
G2
E3
E4
D3
D4
R6
C2
*
12
12
97
12
13
97
12
14
12
15
97
97
12
97
97
14
13
12
15
6
365E3
8E-12
99 8 SE-3
10 50 SE-3
POLY(1)
POLY(1)
DX
DX
200
20E-12
99
97
97 –2.5 1.1
50 –2.5 1.1
REV. 0
–13–
BUF04
BUF04 SPICE
99
C2
13
R6
15
6
V1
12
CP1
I1
R1
9
D1
CS1
D3
E3
D4
E4
IB1
14
G1
97
G2
R5
C3
12
8
R3
5
Q3
CS2
61
Q1
V
LS1
OS
1
30
+IN
Q2
3
R4
7
2
4
Q4
10
6
RFB
D2
11
V2
I2
CP2
R2
50
20
21
C8
C7
G8
R12
R11
G7
97
99
G11
FSY
R13
R14
R15
L2
V5
70
D5
23
21
27
22
D8
72
D7
71
V6
D6
24
6
G10
R16
V7
V8
G12
97
50
–14–
REV. 0
BUF04
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8-Lead Plastic DIP (N-8)
8
5
0.280 (7.11)
0.240 (6.10)
PIN 1
1
4
0.325 (8.25)
0.300 (7.62)
0.430 (10.92)
0.348 (8.84)
0.015
0.195 (4.95)
0.115 (2.93)
0.210
(5.33)
MAX
(0.381) TYP
0.130
(3.30)
MIN
0.160 (4.06)
0.115 (2.93)
0.015 (0.381)
0.008 (0.204)
SEATING
PLANE
0.100
(2.54)
0.070 (1.77)
0.045 (1.15)
0.022 (0.558)
0.014 (0.356)
BSC
8-Lead Cerdip (Q-8)
8-Lead Narrow-Body SO (R-8)
0.005 (0.13) MIN
0.055 (1.4) MAX
8
1
5
4
8
5
0.1574 (4.00)
0.1497 (3.80)
0.310 (7.87)
0.220 (5.59)
PIN 1
PIN 1
0.2440 (6.20)
0.2284 (5.80)
1
4
0.320 (8.13)
0.290 (7.37)
0.405 (10.29) MAX
0.1968 (5.00)
0.1890 (4.80)
0.0196 (0.50)
0.0099 (0.25)
0.102 (2.59)
0.094 (2.39)
x 45°
0.060 (1.52)
0.015 (0.38)
0.200
(5.08)
MAX
0.0098 (0.25)
0.0040 (0.10)
8
0
°
°
0.150
(3.81)
MIN
0.015 (0.38)
0.008 (0.20)
0.0500 (1.27)
0.0160 (0.41)
0.0192 (0.49)
0.0138 (0.35)
0.0500
(1.27)
BSC
0.0098 (0.25)
0.0075 (0.19)
0.200 (5.08)
0.125 (3.18)
15°
0°
0.070 (1.78)
0.100
(2.54)
BSC
0.023 (0.58)
0.014 (0.36)
SEATING
PLANE
0.030 (0.76)
REV. 0
–15–
–16–
相关型号：
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