DAC08BIHP [ADI]
IC PARALLEL, 8 BITS INPUT LOADING, 0.085 us SETTLING TIME, 8-BIT DAC, PDIP16, PLASTIC, DIP-16, Digital to Analog Converter;
| 型号： | DAC08BIHP |
| 厂家： | 
ADI |
| 描述： | IC PARALLEL, 8 BITS INPUT LOADING, 0.085 us SETTLING TIME, 8-BIT DAC, PDIP16, PLASTIC, DIP-16, Digital to Analog Converter 输入元件 光电二极管 转换器 |
| 文件： | 总20页 (文件大小：378K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
8-Bit, High Speed, Multiplying D/A Converter
(Universal Digital Logic Interface)
DAC08
scale trimming in most applications. Direct interface to all
popular logic families with full noise immunity is provided by
the high swing, adjustable threshold logic input.
FEATURES
Fast settling output current: 85 ns
Full-scale current prematched to 1 ꢀSB
Direct interface to TTꢀ, CMOS, ECꢀ, HTꢀ, PMOS
Nonlinearity to 0.1% maximum over temperature range
High output impedance and compliance: −10 V to +18 V
Complementary current outputs
Wide range multiplying capability: 1 MHz bandwidth
ꢀow FS current drift: 10 ppmꢁ/C
Wide power supply range: 4.5 V to 18 V
ꢀow power consumption: 33 mW @ 5 V
ꢀow cost
High voltage compliance complementary current outputs are
provided, increasing versatility and enabling differential
operation to effectively double the peak-to-peak output swing.
In many applications, the outputs can be directly converted to
voltage without the need for an external op amp. All DAC08
series models guarantee full 8-bit monotonicity, and nonlineari-
ties as tight as ±0.1% over the entire operating temperature
range are available. Device performance is essentially unchanged
over the ±±.5 V to ±18 V power supply range, with 33 mW
power consumption attainable at ±5 V supplies.
GENERAꢀ DESCRIPTION
The compact size and low power consumption make the DAC08
attractive for portable and military/aerospace applications;
devices processed to MIL-STD-883, Level B are available.
The DAC08 series of 8-bit monolithic digital-to-analog convert-
ers provide very high speed performance coupled with low cost
and outstanding applications flexibility.
DAC08 applications include 8-bit, 1 µs A/D converters, servo
motor and pen drivers, waveform generators, audio encoders
and attenuators, analog meter drivers, programmable power
supplies, LCD display drivers, high speed modems, and other
applications where low cost, high speed, and complete
input/output versatility are required.
Advanced circuit design achieves 85 ns settling times with very
low “glitch” energy and at low power consumption. Monotonic
multiplying performance is attained over a wide 20-to-1
reference current range. Matching to within 1 LSB between
reference and full-scale currents eliminates the need for full-
FUNCTIONAꢀ BꢀOCK DIAGRAM
(MSB)
B1
(LSB)
B8
V+
13
V
LC
B2
B3
B4
B5
B6
10
B7
11
1
5
6
7
8
9
12
DAC08
I
I
OUT
BIAS
NETWORK
CURRENT
SWITCHES
4
2
14
15
OUT
V
V
(+)
(–)
REF
REF
REFERENCE
AMPLIFIER
16
COMP
3
V–
Figure 1.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703
www.analog.com
© 2004 Analog Devices, Inc. All rights reserved.
DAC08
TABLE OF CONTENTS
Specifications..................................................................................... 3
Reference Amplifier Compensation for Multiplying
Applications ................................................................................ 13
Electrical Characteristics............................................................. 3
Typical Electrical Characteristics ............................................... ±
Absolute Maximum Ratings............................................................ 5
ESD Caution.................................................................................. 5
Pin Connections ............................................................................... 6
Test and Burn-In Circuits................................................................ 7
Typical Performance Characteristics ............................................. 8
Basic Connections .......................................................................... 11
Application Information................................................................ 13
Reference Amplifier Setup ........................................................ 13
Logic Inputs................................................................................. 13
Analog Output Currents ........................................................... 1±
Power Supplies............................................................................ 1±
Temperature Performance......................................................... 1±
Multiplying Operation............................................................... 1±
Settling Time............................................................................... 1±
ADI Current Output DACs........................................................... 16
Outline Dimensions....................................................................... 17
Ordering Guide .......................................................................... 18
REVISION HISTORY
11/04—Rev. B to Rev. C
Changed SO to SOIC .........................................................Universal
Removed DIE......................................................................Universal
Changes to Figure 30, Figure 31, Figure 32................................. 12
Change to Figure 33 ....................................................................... 15
Added Table ±.................................................................................. 16
Updated Outline Dimensions....................................................... 17
Changes to Ordering Guide .......................................................... 18
2/02—Rev. A to Rev. B
Edits to SPECIFICATIONS............................................................. 2
Edits to ABSOLUTE MAXIMUM RATING ................................ 3
Edits to ORDERING GUIDE.......................................................... 3
Edits to WAFER TEST LIMITS...................................................... 5
Edit to Figure 13 ............................................................................... 8
Edits to Figures 1± and 15 ............................................................... 9
Rev. C | Page 2 of 20
DAC08
SPECIFICATIONS
EꢀECTRICAꢀ CHARACTERISTICS
VS = ±15 V, IREF = 2.0 mA, –55°C ≤ TA ≤ +125°C for DAC08/DAC08A, 0°C ≤ TA ≤ +70°C for DAC08E and DAC08H, −±0°C to +85°C for
IOUT
DAC08C, unless otherwise noted. Output characteristics refer to both IOUT and
.
Table 1.
DAC08AꢁDAC08H
DAC08E
Min Typ
DAC08C
Min Typ
8
8
Symbol
Parameter
Resolution
Monotonicity
Nonlinearity
Settling Time
Conditions
Min Typ
Max
Max
Max
Unit
Bits
8
8
8
8
Bits
0.39 %FS
NL
tS
0.1
0.19
150
To 1ꢀ2 LSB, all bits
switched on or off,
TA = 25°C1
85
135
85
85
150
ns
Propagation Delay
Each Bit
All Bits Switched
1
tPLH
tPHL
TCIFS
TA = 25°C
35
35
10
60
60
50
35
35
10
60
60
80
50
35
35
10
60
60
80
ns
ns
ppmꢀ°C
1
Full-Scale Tempco
DAC08E
Output Voltage
Compliance
(True Compliance)
VOC
Full-scale current
Change <1ꢀ2 LSB, ROUT
20 MΩ typ
>
−10
+18
−10
+18
2.04
–10
+18
2.04
V
Full Range Current
IFR4
VREF = 10.000 V R14, R15 =
5.000 kΩ TA = 25°C
IFR4 − IFR2
1.984 1.992
2.000
1.94
1.99
1.94
1.99
mA
Full Range Symmetry
Zero-Scale Current
Output Current
Range
IFRS
IZS
IOR1
0.5
0.1
2.1
4
1
1
0.2
8
2
2
0.2
16
4
µA
µA
mA
R14, R15 = 5.000 kΩ
2.1
2.1
4.2
IOR2
VREF = +15.0 V,
V− = −10 V
VREF = +25.0 V,
V− = −12 V
IREF = 2 mA
4.2
4.2
mA
nA
Output Current
Noise
25
25
25
Logic Input Levels
Logic 0
Logic 1
VIL
VIL
VLC = 0 V
0.8
0.8
0.8
V
V
2
2
2
Logic Input Current
Logic 0
Logic 1
Logic Input Swing
Logic Threshold
Range
VLC = 0 V
IIL
IIH
VIS
VTHR
VIN = −10 V to +0.8 V
VIN = 2.0 V to 18 V
V− = −15 V
−2
0.002
−10
10
+18
+13.5
−2
0.002
−10
10
+18
+13.5
−2
0.002
−10
10
+18
+13.5
µA
µA
V
−10
−10
−10
−10
−10
−10
1
VS = 15 V
V
Reference Bias
Current
Reference Input
Slew Rate
I15
−1
−3
−1
8
−3
−1
8
−3
µA
dIꢀdt
REQ = 200 Ω
RL = 100 Ω
4
8
4
4
mAꢀµs
CC = 0 pF. See Figure 7.1
V+ = 4.5 V to 18 V
Power Supply
Sensitivity
PSSIFS+
PSSIFS–
0.0003
0.002
0.01
0.01
0.0003
0.002
0.01
0.01
0.0003
0.002
0.01 %∆IOꢀ%∆V+
0.01 %∆IOꢀ%∆V−
V− = −4.5 V to −18 V
IREF = 1.0 mA
Rev. C | Page 3 of 20
DAC08
DAC08AꢁDAC08H
DAC08E
Min Typ
DAC08C
Min Typ
Symbol
Power Supply Current I+
Parameter
Conditions
VS = 5 V, IREF = 1.0 mA
Min Typ
Max
Max
3.8
Max
3.8
−5.8
3.8
−7.8
3.8
−7.8
48
Unit
mA
mA
mA
mA
mA
mA
mW
2.3
3.8
2.3
2.3
I−
I+
I−
I+
I−
−4.3
2.4
−6.4
2.5
−6.5
33
−5.8
3.8
−7.8
3.8
−7.8
48
−4.3
2.4
−6.4
2.5
−6.5
33
−5.8
3.8
−7.8
3.8
−7.8
48
−4.3
2.4
−6.4
2.5
−6.5
33
VS = +5 V, −15 V,
IREF = 2.0 mA
VS = 15 V,
IREF = 2.0 mA
5 V, IREF = 1.0 mA +5 V,
−15 V,
Power Dissipation
PD
IREF = 2.0 mA 15 V, IREF
2.0 mA
=
108
135
136
174
103
135
136
174
108
135
136
174
mW
mW
1 Guaranteed by design.
TYPICAꢀ EꢀECTRICAꢀ CHARACTERISTICS
IOUT
VS = ±15 V, and IREF = 2.0 mA, unless otherwise noted. Output characteristics apply to both IOUT and
.
Table 2.
Parameter
Symbol
dIꢀdt
tPLH, tPHL
tS
Conditions
All Grades Typical
Unit
Reference Input Slew Rate
Propagation Delay
Settling Time
8
35
85
mAꢀµs
ns
ns
TA = 25°C, any bit
To 1ꢀ2 LSB, all bits switched on or
off, TA = 25°C
Rev. C | Page 4 of 20
DAC08
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
1
Rating
Package Type
θJA
θJC
16
39
36
35
Unit
°CꢀW
°CꢀW
°CꢀW
°CꢀW
Operating Temperature
DAC08AQ, DAC08Q
DAC08HQ, DAC08EQ, DAC08CQ,
DAC08HP, DAC08EP
16-Lead CERDIP (Q)
16-Lead PDIP (P)
20-Terminal LCC (RC)
16-Lead SOIC (S)
100
82
76
−55°C to +125°C
0°C to +70°C
111
DAC08CP, DAC08CS
−40°C to +85°C
−65°C to +150°C
−65°C to +150°C
−65°C to +125°C
300°C
36 V
V− to V− + 36 V
V− to V+
Junction Temperature (TJ)
Storage Temperature Q Package
Storage Temperature P Package
Lead Temperature (Soldering, 60 sec)
V+ Supply to V− Supply
Logic Inputs
1 θJA is specified for worst-case mounting conditions, that is, θJA is specified for
device in socket for CERDIP, PDIP, and LCC packages; θJA is specified for
device soldered to printed circuit board for SOIC package.
Stresses greater than those listed under Absolute Maximum
Ratings may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
VLC
Analog Current Outputs (at VS− = 15 V)
Reference Input (V14 to V15)
Reference Input Differential Voltage
(V14 to V15)
4.25 mA
V− to V+
18 V
5.0 mA
Reference Input Current (I14)
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. C | Page 5 of 20
DAC08
PIN CONNECTIONS
1
2
3
4
5
6
7
8
16
B8 (LSB)
1
2
3
4
5
6
7
8
16
15
14
13
V+
(+)
(–)
V
COMP
LC
V
V
15 B7
14 B6
I
V
V
(–)
REF
OUT
V–
REF
REF
3
2
1
20 19
(+)
REF
4
5
6
7
8
18
17
V
(+)
V–
REF
V+
DAC08
DAC08
TOP VIEW
(Not To Scale)
COMP
B5
13
I
I
V+
OUT
NC
OUT
DAC08
TOP VIEW
TOP VIEW
(Not To Scale)
16 NC
(Not To Scale)
V
12 B4
11 B3
10 B2
(MSB) B1
12 B8 (LSB)
11 B7
LC
(MSB) B1
B2
15
B8 (LSB)
I
B2
B3
B4
OUT
14 B7
V–
10 B6
10 11 12 13
9
9
B1 (MSB)
9
I
B5
OUT
NC = NO CONNECT
Figure 2. 16-Lead Dual In-Line Package
(Q and P Suffixes)
Figure 3. 16-Lead SOIC
(S Suffix)
Figure 4. DAC08RC/883 20-Lead LCC
(RC Suffix)
Rev. C | Page 6 of 20
DAC08
TEST AND BURN-IN CIRCUITS
+V
C2
REF
R1 = 9kΩ
+18V
R1
C1 = 0.001µF
C2, C3 = 0.01µF
OPTIONAL RESISTOR
FOR OFFSET INPUTS
R
REF
R
R
R
L
IN
14
4
2
C1
R
200Ω
≈
EQ
0V
TYPICAL VALUES:
=5kΩ
16 15 14 13 12 11 10
9
8
R
P
L
15
16
R
DAC08
IN
+V = 10V
IN
1
2
3
4
5
6
7
NO CAP
Figure 5. Pulsed Reference Operation
C3
–18V MIN
Figure 6. Burn-In Circuit
Rev. C | Page 7 of 20
DAC08
TYPICAL PERFORMANCE CHARACTERISTICS
ALL BITS SWITCHED ON
1V
1V
2.4V
0.4V
2.5V
0.5V
–1/2LSB
0V
+1/2LSB
OUTPUT
SETTLING
–0.5mA
I
OUT
–2.5mA
100mV
≈ 200Ω
= 100Ω
= 0
200ns
50ns
10mV
200ns/DIVISION
R
R
C
50ns/DIVISION
SETTLINGTIMEFIXTURE
=2mA,R =1kΩ
EQ
I
FS
L
L
1/2LSB=4µA
C
Figure 10. Full-Scale Settling Time
Figure 7. Fast Pulsed Reference Operation
5
T
= T TO T
MIN
LIMIT FOR
V– = –15V
A
MAX
ALL BITS HIGH
4
0mA
I
OUT
3
2
1
1.0mA
2.0mA
LIMIT FOR
V– = –5V
I
OUT
0
0
1
2
3
4
5
(0000|0000)
(1111|1111)
I
= 2mA
REF
I
, REFERENCE CURRENT (mA)
REF
Figure 8. True and Complementary Output Operation
Figure 11. Full-Scale Current vs. Reference Current
500
400
300
200
100
5mV
2V
2.4V
0.4V
0V
1LSB = 7.8µA
8µA
0
1LSB = 61nA
50ns
100mV
0
0.005 0.01 0.02 0.05 0.10 0.20 0.50 1.00 2.00 5.00 10.00
50ns/DIVISION
I
, OUTPUT FULL-SCALE CURRENT (mA)
FS
Figure 9. LSB Switching
Figure 12. LSB Propagation Delay vs. IFS
Rev. C | Page 8 of 20
DAC08
10
8
2.0
1.6
1.2
R14 = R15 = 1kΩ
500V
ALL BITS ON
= 0V
R
≤
L
6
4
2
V
R15
2
0
–2
–4
–6
–8
1
0.8
0.4
C
= 15pF, V = 2.0V p-p
IN
C
CENTERED AT +1.0V
LARGE SIGNAL
–10
–12
–14
C
= 15pF, V = 50mV p-p
IN
C
CENTERED AT +200mV
SMALL SIGNAL
0
0.1
0.5
2.0
5.0
10.0
–50
0
50
100
150
0.2
1.0
TEMPERATURE (°C)
FREQUENCY (MHz)
Figure 16. VTH − VLC vs. Temperature
Figure 13. Reference Input Frequency Response
4.0
4.0
3.6
3.2
T
= T
TO T
MAX
ALL BITS ON
ALL BITS ON
A
MIN
T
= T
TO T
MIN MAX
A
3.6
3.2
NOTE: POSITIVE COMMON-MODE
RANGE IS ALWAYS (V+) –1.5V
2.8
2.8
2.4
2.4
2.0
1.6
1.2
V– = –15V
V– = –5V
I
= 2mA
V– = –15V
V– = –5V
V+ = +15V
REF
2.0
1.6
1.2
0.8
I
= 2mA
REF
I
= 1mA
I
= 1mA
REF
REF
0.8
0.4
I
= 0.2mA
10
REF
I
= 0.2mA
10
0.4
0
REF
0
–14
–10
–6
–2
2
6
14
18
–14
–10
–6
18
–2
2
6
14
OUTPUT VOLTAGE (V)
V
, REFERENCE COMMON-MODE VOLTAGE (V)
15
Figure 17. Output Current vs. Output Voltage (Output Voltage Compliance)
Figure 14. Reference Amp Common-Mode Range
28
24
20
16
10
8
12
6
SHADED AREA INDICATES PERMISSIBLE
OUTPUT VOLTAGE RANGE FOR V– = –15V.
8
I
≤ 2.0mA.
REF
4
0
4
FOR OTHER V– OR I
SEE OUTPUT CURRENT VS. OUTPUT
VOLTAGE CURVE.
,
REF
–4
2
–8
–12
0
–12
–50
0
50
100
150
–8
–4
0
4
8
12
16
TEMPERATURE (°C)
LOGIC INPUT VOLTAGE (V)
Figure 18. Output Voltage Compliance vs. Temperature
Figure 15. Logic Input Current vs. Input Voltage
Rev. C | Page 9 of 20
DAC08
1.8
1.6
1.4
10
9
BITS MAY BE HIGH OR LOW
8
7
I– WITH I
= 2mA
= 1mA
1.2
1.0
REF
REF
B1
6
5
I
= 2.0mA
REF
I– WITH I
0.8
0.6
4
3
B2
B3
I– WITH I
= 0.2mA
REF
0.4
0.2
B4
B5
2
1
0
I+
V– = –5V
–4
ꢀꢀꢀꢀ
V– = –15V
0
–12
–8
0
4
8
12
16
0
–2
–4
–6
–8
–10 –12 –14 –16 –18 –20
LOGIC INPUT VOLTAGE (V)
V–, NEGATIVE POWER SUPPLY (V dc)
NOTE:
B1 THROUGH B8 HAVE IDENTICAL TRANSFER
CHARACTERISTICS. BITS ARE FULLY SWITCHED WITH LESS
THAN 1/2 LSB ERROR, AT LESS THAN ±100mV FROM ACTUAL
THRESHOLD. THESE SWITCHING POINTS ARE GUARANTEED
TO LIE BETWEEN 0.8V AND 2.0V OVER THE OPERATING
Figure 21. Power Supply Current vs. V−
TEMPERATURE RANGE (V = 0.0V).
LC
Figure 19. Bit Transfer Characteristics
10
9
10
9
ALL BITS HIGH OR LOW
ALL BITS HIGH OR LOW
8
7
8
7
6
5
4
3
2
V– = –15V
= 2.0mA
I–
I–
6
5
4
3
2
1
I
REF
I+
I+
V+ = +15V
1
0
0
0
2
4
6
8
10
12
14
16
18
20
–50
0
50
TEMPERATURE (°C)
100
150
V+, POSITIVE POWER SUPPLY (V dc)
Figure 20. Power Supply vs. V+
Figure 22. Power Supply Current vs. Temperature
Rev. C | Page 10 of 20
DAC08
BASIC CONNECTIONS
+V
REF
R
IN
REF
I
MSB
LSB
REF
I
B1 B2 B3 B4 B5 B6 B7 B8
V
I
REF
14
IN
V
(+)
(–)
R
I
I
REF
IN
O
O
5
6
7
8
9
10 11 12
+V
14
15
REF
4
2
R
REF
(R14)
15
V
REF
3
16
13
1
I
≥ PEAK NEGATIVE SWING OF I
IN
REF
R15
V–
C
V+
R
REF
FOR FIXED REFERENCE,
TTL OPERATION,
TYPICAL VALUES ARE:
R
≈ R15
+V
REF
REF
14
15
C
R15
(OPTIONAL)
COMP
0.1µF
V
R
= 10.000V
= 5.000kΩ
R15 = R
REF
= 0.01µF
REF
V
REF
IN
0.1µF
+V
255
REF
I
=
×
FR
HIGH INPUT
IMPEDANCE
R
REF
256
C
V
C
I
+ I = I FOR
O
O
FR
= 0V (GROUND)
LC
+V
REF
MUST BE ABOVE PEAK POSITIVE SWING OF V
IN
ALL LOGIC STATES
V
V+
V–
LC
Figure 23. Accommodating Bipolar References
Figure 24. Basic Positive Reference Operation
MSB
LSB
B1 B2 B3 B4 B5 B6 B7 B8
E
O
B1 B2 B3 B4 B5 B6 B7 B8
I
I
E
E
O
O
O
O
I
5.000kΩ
5.000kΩ
FULL RANGE
HALF SCALE +LSB
HALF SCALE
HALF SCALE –LSB
ZERO SCALE +LSB
ZERO SCALE
1
1
1
0
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
1
1
0
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
1
0
1
1
0
1.992 0.000 –9.960 –0.000
1.008 0.984 –5.040 –4.920
1.000 0.992 –5.000 –4.960
0.992 1.000 –4.960 –5.000
0.008 1.984 –0.040 –9.920
0.000 1.992 0.000 –9.960
O
4
2
I
= 2.000mA
REF
14
I
O
E
O
Figure 25. Basic Unipolar Negative Operation
10V
MSB
LSB
B1 B2 B3 B4 B5 B6 B7 B8
B1 B2 B3 B4 B5 B6 B7 B8
E
E
O
10kΩ
10kΩ
O
1
1
1
1
0
0
0
1
1
0
0
1
0
0
1
1
0
0
1
0
0
1
1
0
0
1
0
0
1
1
0
0
1
0
0
1
1
0
0
1
0
0
1
1
0
0
1
0
0
1
0
1
0
1
1
0
–9.920 +10.000
–9.840 +9.920
–0.080 +0.160
0.000 +0.080
+0.080 0.000
+9.920 –9.840
+10.000 –9.920
POS. FULL RANGE
POS. FULL RANGE –LSB
ZERO SCALE +LSB
ZERO SCALE
ZERO SCALE –LSB
NEG. FULL SCALE +LSB
NEG. FULL SCALE
I
O
O
4
I
= 2.000mA
REF
E
O
14
2
I
E
O
Figure 26. Basic Bipolar Output Operation
LOW T.C.
4.5kΩ
R
REF
I
I
O
O
14
V
REF
10V
4
2
14
15
I
(+) ≈ 2mA
REF
39kΩ
R15
–V
REF
15
≈1V
10kΩ
POT
NOTE
–V
APPROX
5kΩ
REF
I
≈
R
SETS I ; R15 IS FOR
FS
REF
FS
R
REF
BIAS CURRENT CANCELLATION.
Figure 28. Basic Negative Reference Operation
Figure 27. Recommended Full-Scale Adjustment Circuit
Rev. C | Page 11 of 20
DAC08
10kΩ
5.0kΩ
15V
MSB
LSB
B1 B2 B3 B4 B5 B6 B7 B8
+15V
2
5.000kΩ
5.0kΩ
10V
6
5
B1 B2 B3 B4 B5 B6 B7 B8
E
O
I
V
O
O
4
2
POS. FULL RANGE
O
ZERO SCALE
NEG. FULL SCALE +1LSB
NEG. FULL SCALE
1
1
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
1
0
0
1
0
0
0
1
0
0
0
1
0
1
0
+4.960
0.000
–4.960
–5.000
E
AD8671
REF01*
I
V
C
V+ –V
O
LC
C
4
*OR ADR01
+15V –15V
–15V
Figure 29. Offset Binary Operation
R
L
I
O
E
AD8671
0 TO –I
O
4
2
I
O
E
4
2
AD8671
O
I
O
×
R
L
FR
I
R
O
L
0 TO –I
FR
×
R
L
255
256
I
=
I
REF
FR
255
256
I
=
I
REF
FR
FOR COMPLEMENTARY OUTPUT (OPERATION AS A NEGATIVE LOGIC DAC).
CONNECT NONINVERTING INPUT OF OP AMP TO I (PIN 2): CONNECT I (PIN 4)
TO GROUND.
FOR COMPLEMENTARY OUTPUT (OPERATION AS A NEGATIVE LOGIC DAC).
CONNECT INVERTING INPUT OF OP AMP TO I (PIN 2): CONNECT I (PIN 4)
TO GROUND.
O
O
O
O
Figure 31. Negative Low Impedance Output Operation
Figure 30. Positive Low Impedance Output Operation
CMOS, HTL, NMOS
V+
V
= V 1.4V
LC
ECL
TH
15V CMOS
= 7.6V
V
15V
TH
TTL, DTL,
= 1.4V
V
TH
20kΩ
13k
Ω
9.1k
Ω
V
LC
2N3904
2N3904
2N3904
"A"
"A"
2N3904
V
LC
6.2kΩ
0.1
µ
F
3kΩ
3kΩ
TO PIN 1
TO PIN 1
1
39k
Ω
20kΩ
V
V
LC
LC
R3
400
6.2kΩ
µA
–5.2V
TEMPERATURE COMPENSATING V CIRCUITS
LC
Figure 32. Interfacing with Various Logic Families
Rev. C | Page 12 of 20
DAC08
APPLICATION INFORMATION
REFERENCE AMPꢀIFIER SETUP
REFERENCE AMPꢀIFIER COMPENSATION FOR
MUꢀTIPꢀYING APPꢀICATIONS
The DAC08 is a multiplying D/A converter in which the output
current is the product of a digital number and the input
reference current. The reference current may be fixed or may
vary from nearly zero to ±.0 mA. The full-scale output current
is a linear function of the reference current and is given by
AC reference applications require the reference amplifier to be
compensated using a capacitor from Pin 16 to V−. The value of
this capacitor depends on the impedance presented to Pin 1±;
for R1± values of 1.0 kΩ, 2.5 kΩ, and 5.0 kΩ, minimum values
of CC are 15 pF, 37 pF, and 75 pF. Larger values of R1± require
proportionately increased values of CC for proper phase margin,
so the ratio of CC (pF) to R1± (kΩ) = 15.
255
IFR
=
× IREF
256
where IREF = I1±
For fastest response to a pulse, low values of R1± enabling small
CC values should be used. If Pin 1± is driven by a high impedance
such as a transistor current source, none of the preceding values
suffice, and the amplifier must be heavily compensated, which
decreases overall bandwidth and slew rate. For R1± = 1 kΩ and
CC = 15 pF, the reference amplifier slews at ± mA/µs, enabling a
transition from IREF = 0 to IREF = 2 mA in 500 ns.
In positive reference applications, an external positive reference
voltage forces current through R1± into the VREF(+) terminal
(Pin 1±) of the reference amplifier. Alternatively, a negative
reference may be applied to VREF(–) at Pin 15; reference current
flows from ground through R1± into VREF(+) as in the positive
reference case. This negative reference connection has the
advantage of a very high impedance presented at Pin 15. The
voltage at Pin 1± is equal to and tracks the voltage at Pin 15 due
to the high gain of the internal reference amplifier. R15 (nomi-
nally equal to R1±) is used to cancel bias current errors; R15
may be eliminated with only a minor increase in error.
Operation with pulse inputs to the reference amplifier can be
accommodated by an alternate compensation scheme. This
technique provides lowest full-scale transition times. An internal
clamp allows quick recovery of the reference amplifier from a
cutoff (IREF = 0) condition. Full-scale transition (0 mA to 2 mA)
occurs in 120 ns when the equivalent impedance at Pin 1± is
200 Ω and CC = 0. This yields a reference slew rate of 16 mA/µs,
which is relatively independent of the RIN and VIN values.
Bipolar references may be accommodated by offsetting VREF or
Pin 15. The negative common-mode range of the reference
amplifier is given by VCM – = V− plus (IREF × 1 kΩ) plus 2.5 V.
The positive common-mode range is V+ less 1.5 V.
ꢀOGIC INPUTS
The DAC08 design incorporates a unique logic input circuit
that enables direct interface to all popular logic families and
provides maximum noise immunity. This feature is made
possible by the large input swing capability, 2 µA logic input
current, and completely adjustable logic threshold voltage. For
V− = −15 V, the logic inputs may swing between −10 V and
+18 V. This enables direct interface with 15 V CMOS logic, even
when the DAC08 is powered from a 5 V supply. Minimum
input logic swing and minimum logic threshold voltage are
given by
When a dc reference is used, a reference bypass capacitor is
recommended. A 5.0 V TTL logic supply is not recommended
as a reference. If a regulated power supply is used as a reference,
R1± should be split into two resistors with the junction bypas-
sed to ground with a 0.1 µF capacitor.
For most applications, the tight relationship between IREF and IFS
eliminates the need for trimming IREF. If required, full-scale
trimming can be accomplished by adjusting the value of R1±, or
by using a potentiometer for R1±. An improved method of full-
scale trimming that eliminates potentiometer T.C. effects is
shown in the recommended full-scale adjustment circuit
(Figure 27).
V− + (IREF × 1 kΩ) + 2.5 V
The logic threshold may be adjusted over a wide range by placing
an appropriate voltage at the logic threshold control pin (Pin 1,
VLC). Figure 16 shows the relationship between VLC and VTH
over the temperature range, with VTH nominally 1.± above VLC.
For TTL and DTL interface, simply ground Pin 1. When
interfacing ECL, an IREF = 1 mA is recommended. For interfacing
other logic families, see Figure 32. For general set-up of the
logic control circuit, note that Pin 1 sources 100 µA typical;
external circuitry should be designed to accommodate this
current.
Using lower values of reference current reduces negative power
supply current and increases reference amplifier negative
common-mode range. The recommended range for operation
with a dc reference current is 0.2 mA to ±.0 mA.
Rev. C | Page 13 of 20
DAC08
Fastest settling times are obtained when Pin 1 sees a low
impedance. If Pin 1 is connected to a 1 kΩ divider, for example,
it should be bypassed to ground by a 0.01 µF capacitor.
cryptographic applications and further reduces the size of the
power supply bypass capacitors.
TEMPERATURE PERFORMANCE
ANAꢀOG OUTPUT CURRENTS
The nonlinearity and monotonicity specifications of the DAC08
are guaranteed to apply over the entire rated operating tempera-
ture range. Full-scale output current drift is low, typically
±10 ppm/°C, with zero-scale output current and drift essentially
negligible compared to 1/2 LSB.
Both true and complemented output sink currents are provided
IO
where IO + = IFS. Current appears at the true (IO) output when
a 1 (logic high) is applied to each logic input. As the binary
count increases, the sink current at Pin ± increases proportionally,
in the fashion of a positive logic DAC. When a 0 is applied to
any input bit, that current is turned off at Pin ± and turned on at
The temperature coefficient of the reference resistor R1± should
match and track that of the output resistor for minimum overall
full-scale drift. Settling times of the DAC08 decrease approxi-
mately 10% at –55°C. At +125°C, an increase of about 15% is
typical.
IO
Pin 2. A decreasing logic count increases as in a negative or
inverted logic DAC. Both outputs may be used simultaneously.
If one of the outputs is not required, it must be connected to
ground or to a point capable of sourcing IFS; do not leave an
unused output pin open.
The reference amplifier must be compensated by using a
capacitor from Pin 16 to V−. For fixed reference operation, a
0.01 µF capacitor is recommended. For variable reference
applications, refer to the Reference Amplifier Compensation for
Multiplying Applications section.
Both outputs have an extremely wide voltage compliance
enabling fast direct current-to-voltage conversion through a
resistor tied to ground or other voltage source. Positive compli-
ance is 36 V above V− and is independent of the positive supply.
Negative compliance is given by
MUꢀTIPꢀYING OPERATION
The DAC08 provides excellent multiplying performance with
an extremely linear relationship between IFS and IREF over a
range of ± µA to ± mA. Monotonic operation is maintained over
a typical range of IREF from 100 µA to ±.0 mA.
V− + (IREF × 1 kΩ) + 2.5 V
The dual outputs enable double the usual peak-to-peak load
swing when driving loads in quasi-differential fashion. This
feature is especially useful in cable driving, CRT deflection and
in other balanced applications such as driving center-tapped
coils and transformers.
SETTꢀING TIME
The DAC08 is capable of extremely fast settling times, typically
85 ns at IREF = 2.0 mA. Judicious circuit design and careful
board layout must be used to obtain full performance potential
during testing and application. The logic switch design enables
propagation delays of only 35 ns for each of the 8 bits. Settling
time to within 1/2 LSB of the LSB is therefore 35 ns, with each
progressively larger bit taking successively longer. The MSB
settles in 85 ns, thus determining the overall settling time of
85 ns. Settling to 6-bit accuracy requires about 65 ns to 70 ns.
The output capacitance of the DAC08, including the package, is
approximately 15 pF; therefore the output RC time constant
dominates settling time if RL > 500 Ω.
POWER SUPPꢀIES
The DAC08 operates over a wide range of power supply
voltages from a total supply of 9 V to 36 V. When operating at
supplies of ±5 V or lower, IREF ≤ 1 mA is recommended. Low
reference current operation decreases power consumption and
increases negative compliance (Figure 11), reference amplifier
negative common-mode range (Figure 1±), negative logic input
range (Figure 15), and negative logic threshold range (Figure 16).
For example, operation at −±.5 V with IREF = 2 mA is not
recommended because negative output compliance would be
reduced to near zero. Operation from lower supplies is possible;
however, at least 8 V total must be applied to ensure turn-on of
the internal bias network.
Settling time and propagation delay are relatively insensitive to
logic input amplitude and rise and fall times, due to the high
gain of the logic switches. Settling time also remains essentially
constant for IREF values. The principal advantage of higher IREF
values lies in the ability to attain a given output level with lower
load resistors, thus reducing the output RC time constant.
Symmetrical supplies are not required, as the DAC08 is quite
insensitive to variations in supply voltage. Battery operation is
feasible because no ground connection is required: however, an
artificial ground may be used to ensure logic swings, etc., remain
between acceptable limits. Power consumption is calculated as
follows:
Measuring the settling time requires the ability to accurately
resolve ±± µA; therefore a 1 kΩ load is needed to provide
adequate drive for most oscilloscopes. The settling time fixture
shown in Figure 33 uses a cascade design to permit driving a
1 kΩ load with less than 5 pF of parasitic capacitance at the
measurement node. At IREF values of less than 1.0 mA, excessive
PD = (I +)(V +) + (I −)(V −)
A useful feature of the DAC08 design is that supply current is
constant and independent of input logic states. This is useful in
Rev. C | Page 14 of 20
DAC08
RC damping of the output is difficult to prevent while main-
taining adequate sensitivity. However, the major carry from
01111111 to 10000000 provides an accurate indicator of settling
time. This code change does not require the normal 6.2 time
constants to settle to within ±0.2% of the final value, and thus
minor sacrifice in settling time. Fastest operation can be
obtained by using short leads, minimizing output capacitance
and load resistor values, and by adequate bypassing at the
supply, reference, and VLC terminals. Supplies do not require
large electrolytic bypass capacitors because the supply current
drain is independent of input logic states; 0.1 µF capacitors at
the supply pins provide full transient protection.
settling time is observed at lower values of IREF
.
DAC08 switching transients or “glitches” are very low and can
be further reduced by small capacitive loads at the output at a
V
+5V
L
FORTURN-ON, V =2.7V
L
FORTURN-OFF, V =0.7V
L
1µF
1kΩ
50µF
1µF
MINIMUM
CAPACITANCE
Q2
1kΩ
V
1×
OUT
PROBE
V
CL
0.7V
+0.4V
0V
0V
Q1
V
8
0.1µF
IN
–0.4V
0.1µF
15kΩ
R
REF
100kΩ
2kΩ
5
6
9 10 11 12
7
+V
REF
14
15
4
I
OUT
DAC08
R15
2
13
3
16
–15V
0.01µF
0.1µF
0.1µF
+15V –15V
Figure 33. Settling Time Measurement
Rev. C | Page 15 of 20
DAC08
ADI CURRENT OUTPUT DACS
Table ± lists the latest DACS available from Analog Devices.
Table 4.
Model
Bits Outputs
Interface
SPI, 8-bit load
SPI
SPI
Parallel
SPI
Parallel
SPI
SPI
Parallel
SPI
Parallel
SPI
SPI
Parallel
SPI
SPI
SPI
Parallel
Parallel
SPI
SPI
Parallel
SPI
Package
MSOP-10
MSOP-10
SOT23-8
TSSOP-16
TSSOP-16
TSSOP-20
MSOP-10
SOT23-8
TSSOP-20
TSSOP-16
TSSOP-24
MSOP-10
SOT23-8
TSSOP-20
MSOP-10
TSSOP-16
TSSOP-24
TSSOP-24
LFCSP-40
SOT23-8
MSOP-8
Comments
AD5425
AD5426
AD5450
AD5424
AD5429
AD5428
AD5432
AD5451
AD5433
AD5439
AD5440
AD5443
AD5452
AD5445
AD5444
AD5449
AD5415
AD5447
AD5405
AD5453
AD5553
AD5556
AD5446
AD5555
AD5557
AD5543
AD5546
AD5545
AD5547
8
1
1
1
1
2
2
1
1
1
2
2
1
1
1
1
2
2
2
2
1
1
1
1
2
2
1
1
2
2
Fast 8-bit load; see also AD5426
See also AD5425 fast load
See also AD5425 fast load
8
8
8
8
8
10
10
10
10
10
12
12
12
12
12
12
12
12
14
14
14
14
14
14
16
16
16
16
See also AD5452 and AD5444
Higher accuracy version of AD5443; see also AD5444
Higher accuracy version of AD5443; see also AD5452
Uncommitted resistors
Uncommitted resistors
TSSOP-28
MSOP-10
TSSOP-16
TSSOP-38
MSOP-8
TSSOP-28
TSSOP-16
TSSOP-38
MSOP version of AD5453; compatible with AD5443, AD5432, AD5426
SPI
Parallel
SPI
Parallel
SPI
Parallel
Rev. C | Page 16 of 20
DAC08
OUTLINE DIMENSIONS
0.785 (19.94)
0.765 (19.43)
0.745 (18.92)
0.295 (7.49)
0.285 (7.24)
0.275 (6.99)
16
1
9
8
0.005
(0.13)
MIN
0.098 (2.49)
MAX
0.310 (7.87)
0.220 (5.59)
16
9
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.100 (2.54)
BSC
PIN 1
1
8
0.150 (3.81)
0.135 (3.43)
0.120 (3.05)
0.015 (0.38)
MIN
0.060 (1.52)
0.015 (0.38)
0.320 (8.13)
0.290 (7.37)
0.180 (4.57)
MAX
0.200 (5.08)
0.840 (21.34) MAX
MAX
0.150 (3.81)
MIN
0.150 (3.81)
0.130 (3.30)
0.110 (2.79)
0.015 (0.38)
0.008 (0.20)
0.015 (0.38)
0.010 (0.25)
0.008 (0.20)
SEATING
PLANE
0.060 (1.52)
0.050 (1.27)
0.045 (1.14)
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
0.200 (5.08)
0.125 (3.18)
15°
0°
SEATING
PLANE
0.100
(2.54)
BSC
0.070 (1.78)
0.030 (0.76)
0.023 (0.58)
0.014 (0.36)
COMPLIANT TO JEDEC STANDARDS MO-095AC
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETERS DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
Figure 34. 16-Lead PDIP (N-16)
Figure 35. 16-Lead CERDIP (Q-16)
Dimensions shown in inches and (mm)
Dimensions shown in inches and (mm)
10.00 (0.3937)
9.80 (0.3858)
0.200 (5.08)
0.075 (1.91)
REF
16
1
9
8
REF
0.100 (2.54)
0.064 (1.63)
6.20 (0.2441)
5.80 (0.2283)
4.00 (0.1575)
3.80 (0.1496)
0.100 (2.54) REF
0.095 (2.41)
0.015 (0.38)
MIN
0.075 (1.90)
3
19
18
20
4
8
1.75 (0.0689)
1.35 (0.0531)
0.028 (0.71)
0.022 (0.56)
1.27 (0.0500)
BSC
0.50 (0.0197)
0.25 (0.0098)
1
0.358 (9.09)
0.342 (8.69)
SQ
0.358
× 45°
0.011 (0.28)
0.007 (0.18)
R TYP
(9.09)
MAX
SQ
BOTTOM
VIEW
0.25 (0.0098)
0.10 (0.0039)
0.050 (1.27)
BSC
14
0.075 (1.91)
8°
0°
13
9
REF
0.51 (0.0201)
0.31 (0.0122)
SEATING
PLANE
1.27 (0.0500)
0.40 (0.0157)
COPLANARITY
0.10
0.25 (0.0098)
0.17 (0.0067)
45° TYP
0.088 (2.24)
0.054 (1.37)
0.055 (1.40)
0.045 (1.14)
0.150 (3.81)
BSC
COMPLIANT TO JEDEC STANDARDS MS-012AC
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETERS DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
Figure 36. 16-Lead SOIC (R-16A)
Dimensions shown in inches and (mm)
Figure 37. 20-Terminal Leadless Chip Carrier (E-20)
Dimensions shown in inches and (mm)
Rev. C | Page 17 of 20
DAC08
ORDERING GUIDE
Model1
Nꢀ
Temperature Range
−55°C to +125°C
−55°C to +125°C
0°C to 70°C
Package Description
CERDIP-16
CERDIP-16
PDIP-16
CERDIP-16
CERDIP-16
LCC-20
Package Option
Q-16
No. Parts Per Container
DAC08AQ
0.10%
25
DAC08AQꢀ883C2
0.10%
0.10%
0.10%
0.19%
0.19%
0.19%
0.19%
0.19%
0.19%
0.19%
0.19%
0.39%
0.39%
0.39%
0.39%
0.39%
0.39%
Q-16
25
DAC08HP
DAC08HQ
DAC08Q
DAC08RCꢀ883C2
N-16
Q-16
Q-16
25
25
25
0°C to 70°C
−55°C to +125°C
−55°C to +125°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
E-20
55
DAC08EP
DAC08EQ
DAC08ES
DAC08ES-REEL
DAC08ESZ3
DAC08ESZ-REEL3
DAC08CP
PDIP-16
CERDIP-16
SOIC-16
SOIC-16
SOIC-16
N-16
Q-16
25
25
47
2500
47
R-16A (Narrow Body)
R-16A (Narrow Body)
R-16A (Narrow Body)
R-16A (Narrow Body)
N-16
SOIC-16
PDIP-16
2500
25
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
DAC08CPZ3
PDIP-16
N-16
25
DAC08CS
SOIC-16
R-16A (Narrow Body)
R-16A (Narrow Body)
R-16A (Narrow Body)
R-16A (Narrow Body)
47
DAC08CS-REEL
DAC08CSZ3
DAC08CSZ-REEL3
SOIC-16
2500
47
SOIC-16
SOIC-16
2500
1 Devices processed in total compliance to MIL-STD-883. Consult the factory for the 883 data sheet.
2 For availability and burn-in information on the SOIC and PLCC packages, contact your local sales office.
3 Z = Pb-free part.
Rev. C | Page 18 of 20
DAC08
NOTES
Rev. C | Page 19 of 20
DAC08
NOTES
©
2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
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