DAC08HP [ADI]
8-Bit, High-Speed, Multiplying D/A Converter (Universal Digital Logic Interface); 8位，高速，乘法D / A转换器（通用数字逻辑接口）
| 型号： | DAC08HP |
| 厂家： | 
ADI |
| 描述： | 8-Bit, High-Speed, Multiplying D/A Converter (Universal Digital Logic Interface) |
| 文件： | 总12页 (文件大小：219K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
a 8-Bit, High-Speed, Multiplying D/A Converter
(Universal Digital Logic Interface)
DAC08
full-scale currents eliminates the need for full-scale trimming in
most applications. Direct interface to all popular logic families
with full noise immunity is provided by the high swing, adjust-
able threshold logic input.
FEATURES
Fast Settling Output Current: 85 ns
Full-Scale Current Prematched to ؎1 LSB
Direct Interface to TTL, CMOS, ECL, HTL, PMOS
Nonlinearity to 0.1% Maximum over
Temperature Range
High voltage compliance complementary current outputs are
provided, increasing versatility and enabling differential opera-
tion to effectively double the peak-to-peak output swing. In
many applications, the outputs can be directly converted to
voltage without the need for an external op amp.
High Output Impedance and Compliance:
–10 V to +18 V
Complementary Current Outputs
Wide Range Multiplying Capability: 1 MHz Bandwidth
Low FS Current Drift: ؎10 ppm/؇C
Wide Power Supply Range: ؎4.5 V to ؎18 V
Low Power Consumption: 33 mW @ ؎5 V
Low Cost
All DAC08 series models guarantee full 8-bit monotonicity,
and nonlinearities as tight as 0.1% over the entire operating
temperature range are available. Device performance is essen-
tially unchanged over the 4.5 V to 18 V power supply range,
with 33 mW power consumption attainable at 5 V supplies.
Available in Die Form
The compact size and low power consumption make the DAC08
attractive for portable and military/aerospace applications;
devices processed to MIL-STD-883, Level B are available.
GENERAL DESCRIPTION
The DAC08 series of 8-bit monolithic digital-to-analog convert-
ers provide very high-speed performance coupled with low cost
and outstanding applications flexibility.
DAC08 applications include 8-bit, 1 µs A/D converters, servo
motor and pen drivers, waveform generators, audio encoders
and attenuators, analog meter drivers, programmable power
supplies, CRT display drivers, high-speed modems and other
applications where low cost, high speed and complete input/
output versatility are required.
Advanced circuit design achieves 85 ns settling times with very
low “glitch” energy and at low power consumption. Monotonic
multiplying performance is attained over a wide 20-to-1 reference
current range. Matching to within 1 LSB between reference and
FUNCTIONAL BLOCK DIAGRAM
MSB
B1
LSB
B8
V+
13
V
B2
B3
B4
B5
B6
10
B7
11
LC
1
5
6
7
8
9
12
DAC08
I
OUT
BIAS
NETWORK
CURRENT
SWITCHES
4
2
14
15
I
OUT
V
(+)
(–)
REF
V
REF
REFERENCE
AMPLIFIER
16
COMP
3
V–
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© Analog Devices, Inc., 2002
DAC08–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
(@ VS = ؎15 V, IREF = 2.0 mA, –55؇C ꢀ TA ꢀ +125؇C for DAC08/08A, 0؇C ꢀ TA ꢀ +70؇C
for DAC08E and DAC08H, –40؇C to +85؇C for DAC08C, unless otherwise noted. Output characteristics refer to both IOUT and OUT .)
I
DAC08A/H
DAC08E
Typ
DAC08C
Typ
Parameter
Symbol Conditions
Min Typ
Max
Min
Max
Min
Max
Unit
Resolution
8
8
8
8
8
8
Bits
Bits
0.39 % FS
Monotonicity
Nonlinearity
Settling Time
NL
tS
0.1
135
0.19
150
To 1/2 LSB,
85
85
85
150
ns
All Bits Switched ON
or OFF, TA = 25°C1
Propagation Delay
Each Bit
tPLH
TA = 25°C1
35
35
10
60
60
50
35
35
10
60
60
80
50
35
35
10
60
60
80
ns
ns
ppm/°C
All Bits Switched
tPHL
TCIFS
Full-Scale Tempco1
DAC08E
Output Voltage
Compliance
(True Compliance)
VOC
Full-Scale Current
Change <1/2 LSB,
–10
+18
–10
+18
–10
+18
V
R
OUT > 20 MΩ typ
Full Range Current
IFR4
VREF = 10.000 V
1.984 1.992
2.000
1.94
1.99
2.04
1.94
1.99
2.04
mA
R14, R15 = 5.000 kΩ
T
A = 25°C
Full Range Symmetry
Zero-Scale Current
Output Current Range
IFRS
IZS
IOR1
IOR2
IFR4 – IFR2
0.5
0.1
2.1
4
1
1
0.2
8
2
2
0.2
16
4
µA
µA
mA
R14, R15 = 5.000 kΩ
VREF = +15.0 V,
V– = –10 V
2.1
4.2
2.1
4.2
V
REF = +25.0 V,
V– = –12 V
REF = 2 mA
4.2
mA
nA
Output Current Noise
Logic Input Levels
Logic “0”
Logic Input “1”
Logic Input Current
Logic “0”
Logic Input “1”
Logic Input Swing
Logic Threshold Range
Reference Bias Current
Reference Input
Slew Rate
I
25
25
25
VIL
VIL
VLC = 0 V
LC = 0 V
0.8
0.8
0.8
V
V
2
2
2
V
IIL
IIH
VIS
VTHR
I15
VIN = –10 V to +0.8 V
VIN = 2.0 V to 18 V
V– = –15 V
–2
0.002
–10
–10
10
+18
+13.5 –10
–3
–2
0.002
–10
10
+18
+13.5 –10
–3
–2
0.002
–10
10
+18
+13.5
–3
µA
µA
V
V
µA
mA/µs
–10
–10
VS
=
15 V1
–10
–1
–1
8
–1
8
dI/dt
REQ = 200 Ω
RL = 100 Ω
CC = 0 pF
4
8
4
4
See Fast Pulsed Ref. Info Following.1
0.0003 0.01
0.002 0.01
Power Supply Sensitivity PSSIFS+ V+ = 4.5 V to 18 V
PSSIFS– V– = –4.5 V to –18 V
IREF = 1.0 mA
0.0003 0.01
0.002
0.0003 0.01 %∆IO/%∆V+
0.002 0.01 %∆IO/%∆V–
0.01
Power Supply Current
I+
I–
I+
I–
I+
I–
VS = 5 V, IREF = 1.0 mA
2.3
–4.3
2.4
–6.4
2.5
–6.5
3.8
–5.8
3.8
–7.8
3.8
–7.8
2.3
–4.3
2.4
–6.4
2.5
–6.5
3.8
–5.8
3.8
–7.8
3.8
–7.8
2.3
–4.3
2.4
–6.4
2.5
–6.5
3.8
–5.8
3.8
–7.8
3.8
–7.8
mA
mA
mA
mA
mA
mA
V
S = +5 V, –15 V,
I
REF = 2.0 mA
VS = 15 V,
IREF = 2.0 mA
Power Dissipation
PD
5 V, IREF = 1.0 mA
+5 V, –15 V,
33
48
33
48
33
48
mW
I
REF = 2.0 mA
15 V, IREF = 2.0 mA
108
135
136
174
103
135
136
174
108
135
136
174
mW
mW
NOTES
1Guaranteed by design.
Specifications subject to change without notice.
–2–
REV. B
DAC08
(@ VS = ؎15 V, and IREF = 2.0 mA, unless otherwise noted. Output
TYPICAL ELECTRICAL CHARACTERISTICS
I
characteristics apply to both IOUT and OUT .)
All Grades
Parameter
Symbol
Conditions
Typical
Unit
Reference Input Slew Rate
Propagation Delay
Settling Time
dI/dt
tPLH, tPHL
tS
8
35
mA/µs
TA = 25°C, Any Bit
To 1/2 LSB, All Bits
Switched ON or OFF,
TA = 25°C
ns
85
ns
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS1
Operating Temperature
2
Package Type
Unit
JA
JC
16-Lead Cerdip (Q)
16-Lead Plastic DIP (P)
20-Terminal LCC (RC)
16-Lead SO (S)
100
82
16
39
36
35
°C/W
°C/W
°C/W
°C/W
DAC08AQ, Q . . . . . . . . . . . . . . . . . . . . . –55°C to +125°C
DAC08HQ, EQ, CQ, HP, EP . . . . . . . . . . . . 0°C to +70°C
DAC08CP, CS . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Junction Temperature (TJ) . . . . . . . . . . . . . –65°C to +150°C
Storage Temperature Q Package . . . . . . . . . –65°C to +150°C
Storage Temperature P Package . . . . . . . . . –65°C to +125°C
Lead Temperature (Soldering, 60 sec) . . . . . . . . . . . . . 300°C
V+ Supply to V– Supply . . . . . . . . . . . . . . . . . . . . . . . . . 36 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . V– to V– plus 36 V
VLC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V– to V+
Analog Current Outputs (at VS– = 15 V) . . . . . . . . . . 4.25 mA
Reference Input (V14 to V15) . . . . . . . . . . . . . . . . . . . V– to V+
Reference Input Differential Voltage
76
111
NOTES
1Absolute maximum ratings apply to both DICE and packaged parts, unless
otherwise noted.
2θJA is specified for worst-case mounting conditions, i.e., θJA is specified for device
in socket for cerdip, Plastic DIP, and LCC packages; θJA is specified for device
soldered to printed circuit board for SO package.
(V14 to V15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V
Reference Input Current (I14) . . . . . . . . . . . . . . . . . . . 5.0 mA
ORDERING GUIDE1
Temperature
Range
Package
Description
Package
Option
# Parts Per
Container
Model
NL
0.10%
DAC08AQ
–55°C to +125°C
–55°C to +125°C
0°C to 70°C
0°C to 70°C
–55°C to +125°C
–55°C to +125°C
–55°C to +125°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
–40°C to +85°C
0°C to 70°C
–40°C to +85°C
–40°C to +85°C
25°C
Cerdip-16
Cerdip-16
P-DIP-16
Cerdip-16
Cerdip-16
Cerdip-16
LCC-20
P-DIP-16
Cerdip-16
SO-16
Q-16
Q-16
N-16
Q-16
Q-16
Q-16
E-20
N-16
25
25
25
25
25
25
55
25
25
47
2500
25
25
47
2500
DAC08AQ2/883C
DAC08HP
0.10%
0.10%
0.10%
0.19%
0.19%
0.19%
0.19%
0.19%
0.19%
0.19%
0.39%
0.39%
0.39%
0.39%
0.10%
0.19%
0.39%
DAC08HQ
DAC08Q
DAC08Q2/883C
DAC08RC/883C
DAC08EP
DAC08EQ
DAC08ES
DAC08ES-REEL
DAC08CP
DAC08CQ
Q-16
R-16A (Narrow Body)
R-16A (Narrow Body)
N-16
SO-16
P-DIP-16
Cerdip-16
SO-16
SO-16
DICE
DICE
DICE
Q-16
DAC08CS
R-16A (Narrow Body)
R-16A (Narrow Body)
DAC08CS-REEL
DAC08NBC
DAC08GBC
DAC08GRBC
25°C
25°C
NOTES
1Devices processed in total compliance to MIL-STD-883. Consult factory for 883 data sheet.
2For availability and burn-in information on SO and PLCC packages, contact your local sales office.
The DAC08 contains 84 transistors. Die size 63 mil x 87 mil = 5,481 square mils.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the DAC08 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. B
–3–
DAC08
PIN CONNECTIONS
16-Lead SO
(S Suffix)
DAC08RC/883 20-Lead LCC
(RC Suffix)
16-Lead Dual-In-Line Package
(Q and P Suffix)
V+
(+)
(–)
1
2
3
4
5
6
7
8
16 B8 LSB
15 B7
V
1
2
3
4
5
6
7
8
16 COMPENSATION
LC
V
V
I
15
14
V
V
(–)
REF
OUT
REF
REF
14 B6
V–
(+)
REF
3
2
1
20 19
COMP
13 B5
I
13 V+
V
(+)
4
5
6
7
8
18
17
V–
OUT
REF
V+
I
12 B4
OUT
NC
V
MSB B1
B2
12 B8 LSB
11 B7
LC
16 NC
I
11 B3
OUT
MSB B1
B2
B8 LSB
15
V–
10 B2
B3
10 B6
14 B7
10 11 12 13
9
I
9
B1 MSB
B4
9
B5
OUT
NC = NO CONNECT
DICE CHARACTERISTICS
(125°C Tested Dice Available)
1. V
LC
2. I
OUT
3. V–
4. I
OUT
5. BIT 1 (MSB)
6. BIT 2
7. BIT 3
8. BIT 4
9. BIT 5
10. BIT 6
11. BIT 7
12. BIT 8 (LSB)
13. V+
14. V
(+)
REF
15. V
(–)
REF
16. COMP
DIE SIZE 0.087
؋
0.063 inch, 5,270 sq. mils (2.209
؋
1.60 mm, 3.54 sq. mm) –4–
REV. B
DAC08
(@ VS = ؎15 V, IREF = 2.0 mA; TA = 25؇C, unless otherwise noted. Output characteristics apply to both
I
IOUT and OUT .)
WAFER TEST LIMITS
DAC08N
Limit
DAC08G
Limit
DAC08GR
Limit
Parameter
Symbol
Conditions
Unit
Resolution
Monotonicity
Nonlinearity
Output Voltage
Compliance
Full-Scale Current
8
8
8
8
8
8
Bits min
Bits min
% FS max
V max
NL
VOC
0.1
+18
–10
2.04
1.94
8
0.19
+18
–10
2.04
1.94
8
0.39
+18
–10
2.04
1.94
16
Full-Scale Current
Change < 1/2 LSB
VREF = 10.000 V
V min
I
FS4 or
mA max
mA min
µA max
µA max
IFS2
IFSS
IZS
R14, R15 = 5.000 kΩ
Full-Scale Symmetry
Zero-Scale Current
Output Current Range
2
4
4
I
FS1 or
V– = –10 V,
V
REF = +15 V
2.1
4.2
2.1
4.2
2.1
4.2
mA min
mA min
V– = –12 V,
VREF = +25 V
IFS2
R
14, R15 = 5.000 kΩ
Logic Input “0”
Logic Input “1”
Logic Input Current
Logic “0”
Logic “1”
Logic Input Swing
VIL
VIH
0.8
2
0.8
2
0.8
2
V max
V min
V
LC = 0 V
IIL
IIH
VIS
VIN = –10 V to +0.8 V
VIN = +2.0 V to +18 V
V– = –15 V
10
10
+18
–10
–3
10
10
+18
–10
–3
10
10
+18
–10
–3
µA max
µA max
V max
V min
µA max
% FS/% V max
Reference Bias Current
Power Supply
Sensitivity
I15
PSSIFS+
PSSIFS–
V+ = +4.5 V to +18 V
V– = –4.5 V to –18 V
0.01
0.01
0.01
I
REF = 1.0 mA
Power Supply Current
Power Dissipation
I+
VS = 15 V
IREF ≤ 2.0 mA
VS = 15 V
IREF ≤ 2.0 mA
3.8
–7.8
174
3.8
–7.8
174
3.8
–7.8
174
mA max
µA max
mW max
PD
NOTE
Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed
for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing.
REV. B
–5–
DAC08
+V
REF
0mA
1.0mA
2.0mA
I
OPTIONAL RESISTOR
FOR OFFSET INPUTS
OUT
R
REF
R
R
L
IN
14
4
2
R
200⍀
EQ
0V
R
R
P
L
15
16
I
OUT
TYPICALVALUES:
= 5k⍀
R
IN
+V = 10V
IN
NO CAP
(0000|0000)
I
= 2mA
(1111|1111)
REF
Figure 1. Pulsed Reference Operation
Figure 4. True and Complementary Output Operation
C2
R1 = 9k⍀
+18V
C1 = 0.001F
C2, C3 = 0.01F
5mV
2V
C1
R1
2.4V
16 15 14 13 12 11 10
9
8
DAC08
0.4V
0V
1
2
3
4
5
6
7
8A
0
50ns
100mV
C3
50ns/DIVISION
–18V MIN
Figure 2. Burn-in Circuit
Figure 5. LSB Switching
ALL BITS SWITCHED ON
1V
1V
2.4V
0.4V
LOGIC INPUT
2.5V
0.5V
OUTPUT –1/2LSB
SETTLING 0V
+1/2LSB
–0.5mA
I
OUT
–2.5mA
200ns
100mV
50ns
10mV
50ns/DIVISION
SETTLINGTIME FIXTURE
R
R
C
200⍀
= 100⍀
200ns/DIVISION
EQ
I
= 2mA, R = 1k⍀
FS
L
L
1/2LSB = 4A
= 0
C
Figure 3. Fast Pulsed Reference Operation
Figure 6. Full-Scale Settling Time
–6–
REV. B
Typical Performance Characteristics–DAC08
5.0
4.0
3.0
2.0
1.0
0.0
500
400
300
200
100
0
10
R14 = R15 = 1k⍀
L
T
= T
TO T
MAX
LIMIT FOR
A
MIN
R
ꢁ 500⍀
8
6
V– = –15V
ALL BITS “HIGH”
ALL BITS “ON”
= 0V
V
R15
4
2
2
0
–2
–4
–6
–8
–10
–12
–14
1LSB = 7.8A
1
1. C = 15pF, V = 2.0V p–p
IN
C
LIMIT FOR
V– = –5V
CENTERED AT +1.0V
LARGE SIGNAL
2.
C
= 15pF, V = 50mV p–p
C
IN
1LSB = 61nA
CENTERED AT +200mV
SMALL SIGNAL
0.05
0.02
0.05
0.1
0.5
2.0
10
0.0
1.0
2.0
3.0
4.0
5.0
0.1
0.2
0.5
1.0
2.0
5.0
10
0.01
0.2
1.0
5.0
I
, REFERENCE CURRENT – mA
FREQUENCY – MHz
REF
I
, OUTPUT FULL SCALE CURRENT – mA
FS
TPC 1. Full-Scale Current vs.
Reference Current
TPC 2. LSB Propagation Delay vs. IFS
TPC 3. Reference Input Frequency
Response
4.0
3.6
3.2
2.8
2.4
2.0
1.6
1.2
0.8
0.4
0.0
10.0
8.0
6.0
4.0
2.0
0
2.0
1.6
1.2
0.8
0.4
0
T
= T
TO T
MIN MAX
ALL BITS ON
A
NOTE: POSITIVE COMMON-MODE
RANGE IS ALWAYS (V+) –1.5V
V– = –15V V– = –5V V+ = +15V
I
= 2mA
REF
I
= 1mA
REF
I
= 0.2mA
REF
–14 –10 –6
–2
2
6
10
14
18
–12.0 –8.0 –4.0
0
4.0 8.0 12.0 16.0
–50
0
50
100
150
V
, REFERENCE COMMON-MODEVOLTAGE –V
LOGIC INPUTVOLTAGE –V
TEMPERATURE – ؇C
15
TPC 5. Logic Input Current vs. Input
Voltage
TPC 6. VTH – VLC vs. Temperature
TPC 4. Reference Amp Common-
Mode Range
1.8
1.6
1.4
1.2
28
24
20
16
4.0
T
= T
TO T
MIN MAX
ALL BITS ON
A
3.6
3.2
2.8
2.4
2.0
1.6
1.2
0.8
0.4
0.0
12
B1
1.0
SHADED AREA INDICATES
V– = –15V V– = –5V
I
= 2mA
= 1mA
REF
I
= 2.0mA
PERMISSIBLE OUTPUTVOLTAGE
8
4
REF
RANGE FOR V– = –15V. I
2.0mA.
0.8
0.6
0.4
0.2
REF
B2
B3
FOR OTHER V– OR I
.
REF
I
0
REF
SEE OUTPUT CURRENT VS. OUTPUT
VOLTAGE CURVE.
4
V– = –5V
B4
B5
I
= 0.2mA
8
REF
V– = –15V
0
12
–12 –8
–4
LOGIC INPUTVOLTAGE –V
NOTE: B1THROUGH B8 HAVE IDENTICAL
0
4
8
12
16
–50
0
50
100
150
–14 –10 –6
–2
2
6
10
14
18
TEMPERATURE – ؇C
OUTPUTVOLTAGE –V
TRANSFER CHARACTERISTICS. BITS ARE FULLY
SWITCHEDWITH LESSTHAN 1/2 LSB ERROR, AT
LESSTHAN 100mV FROM ACTUALTHRESHOLD.
THESE SWITCHING POINTS ARE GUARANTEED
TO LIE BETWEEN 0.8V AND 2.0V OVERTHE
OPERATINGTEMPERATURE RANGE (V = 0.0V).
LC
TPC 7. Output Current vs. Output
Voltage (Output Voltage Compliance)
TPC 8. Output Voltage Compliance
vs. Temperature
TPC 9. Bit Transfer Characteristics
–7–
REV. B
DAC08
10
10
9
8
7
6
5
4
3
2
1
0
10
9
8
7
6
5
4
3
2
1
0
ALL BITS “HIGH” OR “LOW”
BITS MAY BE “HIGH” OR “LOW”
I–WITH I
ALL BITS “HIGH” OR “LOW”
V– = –15V
9
8
7
6
5
4
3
2
1
0
= 2mA
= 1mA
I–
REF
I–
I
= 2.0mA
REF
I–WITH I
I–WITH I
REF
= 0.2mA
REF
I+
V+ = +15V
I+
I+
0
2
4
6
8
10 12 14 16 18 20
–0 –2 –4 –6 –8 –10 –12 –14 –16 –18 –20
V–, NEGATIVE POWER SUPPLY –V dc
–50
0
50
100
150
TEMPERATURE – ؇C
V+, POSITIVE POWER SUPPLY –V dc
TPC 10. Power Supply Current vs. V+
TPC 11. Power Supply Current vs. V–
TPC 12. Power Supply Current vs.
Temperature
BASIC CONNECTIONS
+V
REF
R
REF
I
REF
14
MSB
LSB
I
IN
B1 B2 B3 B4 B5 B6 B7 B8
V
IN
I
REF
V
(+)
R
REF
I
I
IN
5
6
7
8
9
10 11 12
O
14
15
+V
REF
4
2
R
(R14)
R15
REF
15
V
(–)
REF
3
16
13
1
O
I
PEAK NEGATIVE SWING OF I
14
REF
IN
FOR FIXED REFERENCE,
TTL OPERATION,
TYPICALVALUES ARE:
V+
V–
R
REF
R
R15
+V
REF
REF
C
C
R15
(OPTIONAL)
COMP
0.1F
V
R
= 10.000V
= 5.000k⍀
REF
REF
V
15
IN
0.1F
255
R15 = R
+V
REF
REF
C = 0.01F
C
I
=
؋
FR
HIGH INPUT
IMPEDANCE
R
256
REF
V
= 0V (GROUND)
LC
I
+ I = I FOR
O
ALL LOGIC STATES
O
FR
+V
MUST BE ABOVE PEAK POSITIVE SWING OFV
REF
IN
V–
V+
V
LC
Figure 7. Accommodating Bipolar References
Figure 8. Basic Positive Reference Operation
MSB
LSB
B1 B2 B3 B4 B5 B6 B7 B8
E
O
B1 B2 B3 B4 B5 B6 B7 B8
I
mA
I
mA
E
E
O
O
O
O
FULL RANGE
HALF-SCALE +LSB
HALF-SCALE
HALF-SCALE –LSB
ZERO-SCALE +LSB
ZERO-SCALE
1
1
1
0
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
1
0
1
1
0
1.992 0.000 –9.960 –0.000
1.008 0.984 –5.040 –4.920
1.000 0.992 –5.000 –4.960
0.992 1.000 –4.960 –5.000
0.008 1.984 –0.040 –9.920
0.000 1.992 0.000 –9.860
I
5.000k⍀
5.000k⍀
O
4
2
I
= 2.000mA
REF
14
I
O
E
O
Figure 9. Basic Unipolar Negative Operation
–8–
REV. B
DAC08
10.000V
B1 B2 B3 B4 B5 B6 B7 B8
E
E
O
O
MSB
LSB
POS. FULL RANGE
POS. FULL RANGE –LSB
ZERO-SCALE +LSB
ZERO-SCALE
ZERO-SCALE –LSB
NEG. FULL-SCALE +LSB
NEG. FULL-SCALE
1
1
1
1
0
0
0
1
1
0
0
1
0
0
1
1
0
0
1
0
0
1
1
0
0
1
0
0
1
1
0
0
1
0
0
1
1
0
0
1
0
0
1
1
0
0
1
0
0
1
0
1
0
1
1
0
–9.920 +10.000
–9.840 +9.920
–0.080 +0.160
10.000k⍀
10.000k⍀
B1 B2 B3 B4 B5 B6 B7 B8
0.000
+0.080
I
E
E
O
O
O
4
2
I
(+) = 2.000mA
+0.080 0.000
+9.920 –9.840
+10.000 –9.920
REF
14
I
O
Figure 10. Basic Bipolar Output Operation
LOW T.C.
4.5k⍀
R
REF
I
I
O
14
15
V
REF
10V
4
2
14
15
I
(+) 2mA
1V
REF
O
39k⍀
R15
–V
REF
10k⍀
POT
NOTE
–V
R
REF
APPROX
I
R
SETS I ; R15 IS FOR
FS
REF
FS
5k⍀
REF
BIAS CURRENT CANCELLATION.
Figure 11. Recommended Full-Scale Adjustment Circuit
Figure 12. Basic Negative Reference Operation
10k⍀
5.0k⍀
15V
MSB
LSB
B1 B2 B3 B4 B5 B6 B7 B8
+15V
2
5.000k⍀
5.0k⍀
6
5
10V
B1 B2 B3 B4 B5 B6 B7 B8
E
O
I
I
O
O
V
O
4
2
POS. FULL RANGE
ZERO-SCALE
1
1
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1 +4.960
0 0.000
1 –4.960
0 –5.000
E
OP711
O
REF01*
NEG. FULL-SCALE +1 LSB 0
NEG. FULL-SCALE 0
V+ V–
C
V
C
LC
4
*OR ADR01
+15V –15V
–15V
Figure 13. Offset Binary Operation
R
L
I
I
O
E
OP711
O
L
4
I
I
O
4
2
E
O
OP711
0TO –I
؋
R O
FR
2
R
O
L
255
256
0TO +I
؋
R FR
L
I
=
I
REF
FR
255
256
I
=
I
REF
FR
FOR COMPLEMENTARY OUTPUT (OPERATION AS A NEGATIVE LOGIC DAC),
CONNECT INVERTING INPUT OF OP AMPTO I (PIN 2); CONNECT I (PIN 4)TO
FOR COMPLEMENTARY OUTPUT (OPERATION AS A NEGATIVE LOGIC DAC),
CONNECT NONINVERTING INPUT OF OP AMPTO I (PIN 2); CONNECT I (PIN 4)
O
O
O
O
GROUND.
TO GROUND.
Figure 14. Positive Low Impedance Output Operation
Figure 15. Negative Low Impedance Output Operation
CMOS, HTL, NMOS
V
=V
1.4V
LC
TH
ECL
15V CMOS
= 7.6V
V+
V
TH
15V
TTL, DTL
= 1.4V
V
TH
13k⍀
20k⍀
9.1k⍀
6.2k⍀
V
2N3904
3k⍀
2N3904
LC
“A”
“A”
2N3904
2N3904
V
LC
0.1F
3k⍀
TO PIN 1
TO PIN 1
1
39k⍀
20k⍀
V
V
LC
LC
R3
400A
6.2k⍀
–5.2V
TEMPERATURE COMPENSATINGV
CIRCUITS
LC
Figure 16. Interfacing with Various Logic Families
–9–
REV. B
DAC08
APPLICATION INFORMATION
REFERENCE AMPLIFIER SETUP
technique provides lowest full-scale transition times. An internal
clamp allows quick recovery of the reference amplifier from a
cutoff (IREF = 0) condition. Full-scale transition (0 mA to 2 mA)
occurs in 120 ns when the equivalent impedance at Pin 14 is
200 Ω and CC = 0. This yields a reference slew rate of 16 mA/µs,
which is relatively independent of RIN and VIN values.
The DAC08 is a multiplying D/A converter in which the output
current is the product of a digital number and the input refer-
ence current. The reference current may be fixed or may vary
from nearly zero to 4.0 mA. The full-scale output current is a
linear function of the reference current and is given by:
LOGIC INPUTS
255
256
The DAC08 design incorporates a unique logic input circuit
that enables direct interface to all popular logic families and
provides maximum noise immunity. This feature is made pos-
sible by the large input swing capability, 2 µA logic input
current and completely adjustable logic threshold voltage.
For V– = –15 V, the logic inputs may swing between –10 V
and +18 V. This enables direct interface with 15 V CMOS
logic, even when the DAC08 is powered from a 5 V supply.
Minimum input logic swing and minimum logic threshold
voltage are given by: V– plus (IREF × 1 kΩ) plus 2.5 V. The
logic threshold may be adjusted over a wide range by placing
an appropriate voltage at the logic threshold control pin (Pin 1,
VLC). The appropriate graph shows the relationship between
VLC and VTH over the temperature range, with VTH nominally
1.4 above VLC. For TTL and DTL interface, simply ground pin
1. When interfacing ECL, an IREF = 1 mA is recommended. For
interfacing other logic families, see preceding page. For general
set-up of the logic control circuit, it should be noted that Pin 1
will source 100 µA typical; external circuitry should be designed
to accommodate this current.
IFR
=
× I
REF , where IREF = I14
In positive reference applications, an external positive reference
voltage forces current through R14 into the VREF(+) terminal
(Pin 14) of the reference amplifier. Alternatively, a negative
reference may be applied to VREF(–) at Pin 15; reference current
flows from ground through R14 into VREF(+) as in the positive
reference case. This negative reference connection has the advan-
tage of a very high impedance presented at Pin 15. The voltage
at Pin 14 is equal to and tracks the voltage at Pin 15 due to the
high gain of the internal reference amplifier. R15 (nominally equal
to R14) is used to cancel bias current errors; R15 may be elimi-
nated with only a minor increase in error.
Bipolar references may be accommodated by offsetting VREF or
Pin 15. The negative common-mode range of the reference
amplifier is given by: VCM– = V– plus (IREF × 1 kΩ) plus 2.5 V.
The positive common-mode range is V+ less 1.5 V.
When a dc reference is used, a reference bypass capacitor is
recommended. A 5.0 V TTL logic supply is not recommended
as a reference. If a regulated power supply is used as a reference,
R14 should be split into two resistors with the junction bypassed to
ground with a 0.1 µF capacitor.
Fastest settling times are obtained when Pin 1 sees a low imped-
ance. If Pin 1 is connected to a 1 kΩ divider, for example, it
should be bypassed to ground by a 0.01 µF capacitor.
For most applications the tight relationship between IREF and IFS
will eliminate the need for trimming IREF. If required, full-scale
trimming may be accomplished by adjusting the value of R14, or
by using a potentiometer for R14. An improved method of
full-scale trimming which eliminates potentiometer T.C. effects
is shown in the recommended full-scale adjustment circuit.
ANALOG OUTPUT CURRENTS
Both true and complemented output sink currents are provided
where IO
+
IO = IFS. Current appears at the “true” (IO) output
when a “1” (logic high) is applied to each logic input. As the
binary count increases, the sink current at pin 4 increases pro-
portionally, in the fashion of a “positive logic” D/A converter.
When a “0” is applied to any input bit, that current is turned
off at Pin 4 and turned on at Pin 2. A decreasing logic count
increases IO as in a negative or inverted logic D/A converter.
Both outputs may be used simultaneously. If one of the outputs
is not required, it must be connected to ground or to a point
capable of sourcing IFS; do not leave an unused output pin open.
Using lower values of reference current reduces negative power
supply current and increases reference amplifier negative com-
mon-mode range. The recommended range for operation with
a dc reference current is 0.2 mA to 4.0 mA.
REFERENCE AMPLIFIER COMPENSATION FOR
MULTIPLYING APPLICATIONS
Both outputs have an extremely wide voltage compliance enabling
fast direct current-to-voltage conversion through a resistor tied
to ground or other voltage source. Positive compliance is 36 V
above V– and is independent of the positive supply. Negative
compliance is given by V– plus (IREF × 1 kΩ) plus 2.5 V.
AC reference applications will require the reference amplifier to
be compensated using a capacitor from Pin 16 to V–. The value
of this capacitor depends on the impedance presented to Pin 14:
for R14 values of 1.0, 2.5 and 5.0 kΩ, minimum values of CC
are 15, 37 and 75 pF. Larger values of R14 require proportion-
ately increased values of CC for proper phase margin, so the
ratio of CC (pF) to R14 (kΩ) = 15.
The dual outputs enable double the usual peak-to-peak load
swing when driving loads in quasi-differential fashion. This
feature is especially useful in cable driving, CRT deflection and
in other balanced applications such as driving center-tapped
coils and transformers.
For fastest response to a pulse, low values of R14 enabling
small CC values should be used. If Pin 14 is driven by a high
impedance such as a transistor current source, none of the
above values will suffice and the amplifier must be heavily
compensated which will decrease overall bandwidth and slew
rate. For R14 = 1 kΩ and CC = 15 pF, the reference amplifier
POWER SUPPLIES
The DAC08 operates over a wide range of power supply voltages
from a total supply of 9 V to 36 V. When operating at supplies
of 5 V or less, IREF ≤ 1 mA is recommended. Low reference
current operation decreases power consumption and increases
negative compliance, reference amplifier negative common-mode
slews at 4 mA/µs enabling a transition from IREF = 0 to IREF
2 mA in 500 ns.
=
Operation with pulse inputs to the reference amplifier may be
accommodated by an alternate compensation scheme. This
–10–
REV. B
DAC08
SETTLING TIME
range, negative logic input range and negative logic threshold
range; consult the various figures for guidance. For example,
operation at –4.5 V with IREF = 2 mA is not recommended
because negative output compliance would be reduced to near
zero. Operation from lower supplies is possible; however, at
least 8 V total must be applied to ensure turn-on of the internal
bias network.
The DAC08 is capable of extremely fast settling times, typically
85 ns at IREF = 2.0 mA. Judicious circuit design and careful
board layout must be employed to obtain full performance
potential during testing and application. The logic switch design
enables propagation delays of only 35 ns for each of the 8 bits.
Settling time to within 1/2 LSB of the LSB is therefore 35 ns,
with each progressively larger bit taking successively longer. The
MSB settles in 85 ns, thus determining the overall settling time
of 85 ns. Settling to 6-bit accuracy requires about 65 ns to 70 ns.
The output capacitance of the DAC08 including the package is
approximately 15 pF, therefore the output RC time constant
dominates settling time if RL > 500 Ω.
Symmetrical supplies are not required, as the DAC08 is quite
insensitive to variations in supply voltage. Battery operation is
feasible as no ground connection is required: however, an artificial
ground may be used to ensure logic swings, etc., remain
between acceptable limits.
Power consumption may be calculated as follows:
Settling time and propagation delay are relatively insensitive to
logic input amplitude and rise and fall times, due to the high
gain of the logic switches. Settling time also remains essentially
constant for IREF values. The principal advantage of higher IREF
values lies in the ability to attain a given output level with lower
load resistors, thus reducing the output RC time constant.
PD = (I+) (V+) + (I–) (V–)
A useful feature of the DAC08 design is that supply current is
constant and independent of input logic states; this is useful in
cryptographic applications and further serves to reduce the size
of the power supply bypass capacitors.
Measurement of settling time requires the ability to accurately
resolve 4 µA, therefore a 1 kΩ load is needed to provide
adequate drive for most oscilloscopes. The settling time fix-
ture shown in schematic labelled “Settling Time Measurement”
uses a cascade design to permit driving a 1 kΩ load with less
than 5 pF of parasitic capacitance at the measurement node. At
IREF values of less than 1.0 mA, excessive RC damping of the
output is difficult to prevent while maintaining adequate sensi-
tivity. However, the major carry from 01111111 to 10000000
provides an accurate indicator of settling time. This code change
does not require the normal 6.2 time constants to settle to
within 0.2% of the final value, and thus settling times may be
TEMPERATURE PERFORMANCE
The nonlinearity and monotonicity specifications of the DAC08
are guaranteed to apply over the entire rated operating temperature
range. Full-scale output current drift is low, typically 10 ppm/°C,
with zero-scale output current and drift essentially negligible
compared to 1/2 LSB.
The temperature coefficient of the reference resistor R14 should
match and track that of the output resistor for minimum overall
full-scale drift. Settling times of the DAC08 decrease approxi-
mately 10% at –55°C; at +125°C an increase of about 15%
is typical.
observed at lower values of IREF
.
The reference amplifier must be compensated by using a capacitor
from pin 16 to V–. For fixed reference operation, a 0.01 µF
capacitor is recommended. For variable reference applications,
see “Reference Amplifier Compensation for Multiplying Applica-
tions” section.
DAC08 switching transients or “glitches” are very low and may
be further reduced by small capacitive loads at the output at a
minor sacrifice in settling time.
Fastest operation can be obtained by using short leads, minimizing
output capacitance and load resistor values, and by adequate
bypassing at the supply, reference, and VLC terminals. Supplies
do not require large electrolytic bypass capacitors as the supply
current drain is independent of input logic states; 0.1 µF capacitors
at the supply pins provide full transient protection.
MULTIPLYING OPERATION
The DAC08 provides excellent multiplying performance with an
extremely linear relationship between IFS and IREF over a range
of 4 µA to 4 mA. Monotonic operation is maintained over a
typical range of IREF from 100 µA to 4.0 mA.
V
+5V
L
FORTURN-ON,V = 2.7V
L
FORTURN-OFF,V = 0.7V
L
1k⍀
1F
50F
1F
MINIMUM
CAPACITANCE
Q2
1k⍀
V
1X
OUT
V
0.7V
+0.4V
0V
0V
CL
Q1
PROBE
0.1F
V
IN
–0.4V
0.1F
15k⍀
R
100k⍀ 2k⍀
REF
5
6 7 8 9 10 11 12
14
15
+V
REF
4
I
OUT
DAC08
R15
2
13
3
16
–15V
0.01F
0.1F
0.1F
+15V –15V
Figure 17. Settling Time Measurement
–11–
REV. B
DAC08
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
16-Lead Plastic DIP (N-16)
16-Lead Cerdip (Q-16)
0.080 (2.03) MAX
0.005 (0.13) MIN
0.840 (21.34)
0.745 (18.92)
16
9
0.310 (7.87)
16
9
PIN 1
0.280 (7.11)
0.240 (6.10)
0.220 (5.59)
0.320 (8.13)
0.290 (7.37)
1
8
1
8
0.325 (8.25)
0.300 (7.62)
PIN 1
0.840 (21.34) MAX
0.060 (1.52)
0.015 (0.38)
0.060 (1.52)
0.015 (0.38)
0.200 (5.08)
0.195 (4.95)
0.115 (2.93)
MAX
0.210 (5.33)
MAX
0.160 (4.06)
0.115 (2.93)
0.150
(3.81)
MIN
SEATING
PLANE
0.200 (5.08)
0.125 (3.18)
0.130
(3.30)
MIN
0.015 (0.38)
0.008 (0.20)
0.100 0.070 (1.78)
(2.54)
BSC
0.023 (0.58)
15°
0°
0.015 (0.381)
0.008 (0.204)
SEATING
PLANE
0.100
(2.54)
BSC
0.030 (0.76)
0.014 (0.36)
0.070 (1.77)
0.045 (1.15)
0.022 (0.558)
0.014 (0.356)
16-Lead SO (R-16A)
20-Terminal Leadless Chip Carrier (E-20)
0.3937 (10.00)
0.3859 (9.80)
0.200 (5.08)
0.075
(1.91)
REF
BSC
0.358 (9.09)
0.342 (8.69)
SQ
0.100 (2.54)
0.064 (1.63)
0.100 (2.54) BSC
0.015 (0.38)
16
1
9
8
0.1574 (4.00)
0.1497 (3.80)
0.2440 (6.20)
0.2284 (5.80)
0.095 (2.41)
0.075 (1.90)
3
MIN
19
20
18
4
0.028 (0.71)
1
0.358
0.011 (0.28)
0.007 (0.18)
R TYP
TOP
VIEW
0.022 (0.56)
(9.09)
MAX
SQ
BOTTOM
VIEW
PIN 1
0.0688 (1.75)
0.0532 (1.35)
0.050 (1.27)
BSC
0.0196 (0.50)
0.0099 (0.25)
0.050 (1.27)
BSC
؋
45؇ 8
14
13
0.075 (1.91)
REF
9
45° TYP
0.150 (3.81)
BSC
8؇
0؇
0.088 (2.24)
0.054 (1.37)
0.055 (1.40)
0.045 (1.14)
0.0098 (0.25)
0.0040 (0.10)
0.0192 (0.49)
0.0138 (0.35)
SEATING
PLANE
0.0500 (1.27)
0.0160 (0.41)
0.0099 (0.25)
0.0075 (0.19)
Revision History
Location
Page
Data Sheet changed from REV. A to REV. B.
Edits to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Edits to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Edits to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Edits to WAFER TEST LIMITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Edit to Figure 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Edits to Figures 14 and 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Replacement of SO-16 with R-16A Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
–12–
REV. B
相关型号：
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PARALLEL, 8 BITS INPUT LOADING, 0.085 us SETTLING TIME, 8-BIT DAC, PDIP16, PLASTIC, DIP-16
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ADI
DAC08Q/883
IC PARALLEL, 8 BITS INPUT LOADING, 0.085 us SETTLING TIME, 8-BIT DAC, CDIP16, GLASS SEALED, CERDIP-16, Digital to Analog Converter
ADI
DAC08Q2/38510
IC PARALLEL, 8 BITS INPUT LOADING, 8-BIT DAC, CDIP16, 0.250 X 0.875 INCH, HERMETIC SEALED, CERAMIC, DIP-16, Digital to Analog Converter
ADI
DAC08Q5/38510
IC PARALLEL, 8 BITS INPUT LOADING, 8-BIT DAC, CDIP16, 0.250 X 0.875 INCH, HERMETIC SEALED, CERAMIC, DIP-16, Digital to Analog Converter
ADI
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