DAC10 [ADI]
10-Bit High Speed Multiplying D/A Converter Universal Digital Logic Interface; 10位高速乘法D / A转换器通用数字逻辑接口
| 型号： | DAC10 |
| 厂家： | 
ADI |
| 描述： | 10-Bit High Speed Multiplying D/A Converter Universal Digital Logic Interface |
| 文件： | 总10页 (文件大小：302K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
a 10-Bit High Speed Multiplying D/A Converter
(Universal Digital Logic Interface)
DAC10*
All DAC10 series models guarantee full 10-bit monotonicity,
and nonlinearities as tight as +0.05% over the entire operating
temperature range are available. Device performance is essen-
tially unchanged over the ±18 V power supply range, with
85 mW power consumption attainable at lower supplies.
FEATURES
Fast Settling: 85 ns
Low Full-Scale Drift: 10 ppm/؇C
Nonlinearity to 0.05% Max Over Temperature Range
Complementary Current Outputs: 0 mA to 4 mA
Wide Range Multiplying Capability: 1 MHz Bandwidth
Wide Power Supply Range: +5, –7.5 Min to ؎18 V Max
Direct Interface to TTL, CMOS, ECL, PMOS, NMOS
Availability in Die Form
A highly stable, unique trim method is used, which selectively
shorts Zener diodes, to provide 1/2 LSB full-scale accuracy
without the need for laser trimming.
Single-chip reliability, coupled with low cost and outstanding
flexibility, make the DAC10 device an ideal building block for
A/D converters, Data Acquisition systems, CRT displays, pro-
grammable test equipment and other applications where low
power consumption, input/output versatility and long-term
stability are required.
GENERAL DESCRIPTION
The DAC10 series of 10-bit monolithic multiplying digital-to-
analog converters provide high speed performance and full-scale
accuracy.
Advanced circuit design achieves 85 ns settling times with very
low “glitch” energy and low power consumption. Direct inter-
face to all popular logic families with full noise immunity is
provided by the high swing, adjustable threshold logic inputs.
SIMPLIFIED SCHEMATIC
MSB
LSB
V
B
B
B
B
B
B
B
B
B
B
V+
LC
1
1
2
3
4
5
6
7
8
9
10
15
5
6
7
8
9
10
11
12
13
14
BIAS NETWORK
4
2
I
I
OUT
OUT
CURRENT SWITCHES
16
17
V
V
(+)
(–)
REF
REFERENCE
AMPLIFIER
REF
18
3
COMP
V–
*Protected by Patent Nos. 4,055,770, 4,056,740 and 4,092,639.
REV. D
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 1998
DAC10–SPECIFICATIONS
(@ VS = ؎15 V; IREF = 2 mA; 0؇C ≤ TA ≤ +70؇C for DAC10F and G, unless otherwise noted.
Output characteristics apply to both IOUT and IOUT.)
ELECTRICAL CHARACTERISTICS
DAC10F
Typ
DAC10G
Typ
Parameter
Symbol
Conditions
Min
Max
Min
Max
Units
Bits
MONOTONICITY
NONLINEARITY
10
10
NL
0.3
0.3
0.5
1
0.6
0.7
1
LSB
DIFFERENTIAL
NONLINEARITY
DNL
tS
LSB
SETTLING TIME
All Bits Switched ON or OFF
Settle to 0.05% of FS (See Note)
85
18
135
85
18
150
ns
OUTPUT CAPACITANCE
PROPAGATION DELAY
CO
pF
tPLH
tPHL
All Bits Switched RL = 5 kΩ
RL = 0 kΩ
50
50
50
50
ns
ns
OUTPUT VOLTAGE
COMPLIANCE
Full-Scale Current Change
<1 LSB
–5.5
+10
–5.5
+10
V
V
VOC
GAIN TEMPCO
TCIFS
(See Note)
IFR–IFR
±10
0.1
±25
4
±10
0.1
±50
4
ppm/°C
µA
FULL-SCALE SYMMETRY IFSS
ZERO-SCALE CURRENT
FULL-SCALE CURRENT
IZS
IFR
0.01
0.5
0.01
0.5
µA
(See Note)
3.960 3.996 4.032
3.920 3.996 4.072
mA
REFERENCE INPUT
SLEW RATE
DI/dt
IB
6
6
mA/µs
µA
REFERENCE BIAS
CURRENT
–1
–3
–1
–3
POWER SUPPLY
SENSITIVITY
PPS/FS
PPS/FS
+
–
4.5 V ≤ V+ ≤ –18 V
–18 V ≤ V– ≤ –10 V
0.001 0.01
0.0012 0.01
0.001 0.01
0.0012 0.01
%∆IFS/%∆V
%∆IFS/%∆V
POWER SUPPLY CURRENT I+
VS = ±15 V; IREF = 2 mA
2.3
–9
1.8
–5.9
4
–15
4
2.3
–9
1.8
–5.9
4
–15
4
mA
mA
mA
mA
I–
I+
I–
VS = +5 V; –7.5 V; IREF = 1 mA
–9
–9
POWER DISSIPATION
LOGIC INPUT LEVELS
PD
PD
VS = ±15 V; IREF = 2 mA
VS = +5 V; –7.5 V; IREF = 1 mA
231
85
285
88
231
85
285
88
mW
mW
VIL
VIH
VLC = 0
VLC = 0
0.8
0.8
V
V
2
2
LOGIC INPUT CURRENTS IIL
IIH
VLC = 0; VIN = 0.8 V
VIN = 2.0 V
–10
–5
–10
–5
µA
µA
0.001 10
0.001 10
(@ VS = ؎15 V; IREF = 2 mA; TA = +25؇C, unless otherwise noted. Output characteristics
apply to both IOUT and IOUT.)
ELECTRICAL CHARACTERISTICS
DAC10F
Typ
DAC10G
Typ
Parameter
Symbol Conditions
Min
Max
Min
Max Units
MONOTONICITY
NONLINEARITY
10
10
Bits
NL
0.3
0.3
0.5
1
0.6
0.7
1
LSB
LSB
V
DIFFERENTIAL
NONLINEARITY
DNL
OUTPUT VOLTAGE
COMPLIANCE
VOC
IFS
Full-Scale Current Change, <1 LSB
–5
–6/+18 +10
–5
–6/+15 +10
FULL-SCALE CURRENT
VREF = 10.000 V,
R14 = R15 = 5.000 kΩ
3.978 3.996 4.014
3.956 3.996 4.036 mA
FULL-SCALE SYMMETRY IFSS
IFR–IFR
0.1
4
0.1
0.4
0.5
µA
µA
ZERO-SCALE CURRENT
NOTE: Guaranteed by design.
IZS
0.01
0.5
0.01
–2–
REV. D
DAC10
(@ VS = ؎15 V, IREF = 2 mA, TA = +25؇C, unless otherwise noted. Output characteristics refer to both
IOUT and IOUT).
WAFER TEST LIMITS
DAC10N
Limit
Parameter
Symbol
Conditions
Units
RESOLUTION
MONOTONICITY
NONLINEARITY
10
Bits min
Bits min
LSB max
10
NL
±0.5
OUTPUT VOLTAGE COMPLIANCE
VOC
True 1 LSB
+10
–5
V max
V min
OUTPUT CURRENT RANGE
ZERO-SCALE CURRENT
LOGIC INPUT “1”
I
FS ±3.996 mA
±18
0.5
2
µA max
µA max
V min
IZS
All Bits OFF
IIN = 100 nA
VIH
VIL
LOGIC INPUT “0”
VLC @ Ground
0.8
V max
IIN = –100 µA
POSITIVE SUPPLY CURRENT
NEGATIVE SUPPLY CURRENT
I+
I–
V+ = 15 V
4
mA max
mA max
V+ = –15 V
–15
NOTE: Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not
guaranteed for standard produce dice.
(@ VS = ؎15 V, IREF = 2 mA, unless otherwise noted. Output characteristics
refer to both IOUT and IOUT).
TYPICAL ELECTRICAL CHARACTERISTICS
DAC10F
Parameter
Symbol
Conditions
Typ
Units
SETTLING TIME
tS
To ±1/2 LSB When Output Is Switched from 0 to FS
85
ns
GAIN TEMPERATURE
COEFFICIENT (TC)
VREF Tempco Excluded
±10
18
ppm FS/°C
pF
OUTPUT CAPACITANCE
OUTPUT RESISTANCE
10
MΩ
DICE CHARACTERISTICS
DIE SIZE 0.091
؋
0.087 inch, 7,917 sq. mils (2.311
؋
2.210 mm, 5.107 sq. mm) REV. D
–3–
DAC10
ABSOLUTE MAXIMUM RATINGS1
ORDERING GUIDE
Operating Temperature
INL
(LSB) Range
Temperature Package
Package
DAC10FX, GX, GS, GP . . . . . . . . . . . . . . . . 0°C to +70°C
Junction Temperature (TJ) . . . . . . . . . . . . . –65°C to +150°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 60 sec) . . . . . . . . . . . +300°C
V+ Supply to V– Supply . . . . . . . . . . . . . . . . . . . . . . . . . 36 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . V– to V– plus 36 V
VLC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V– to V+
Analog Current Outputs . . . . . . . . . . . . . . . . +18 V to –18 V
Reference Inputs (V16 to V17) . . . . . . . . . . . . . . . . . V– to V+
Reference Input Differential Voltage (V16 to V17) . . . . ±18 V
Reference Input Current (I16) . . . . . . . . . . . . . . . . . . 2.5 mA
Model
Description Options
DAC10FX 0.5
0°C to +70°C Cerdip
0°C to +70°C Cerdip
0°C to +70°C SOIC
Q-18
Q-18
R-18
DAC10GX
DAC10GS
DAC10GP
1
1
1
0°C to +70°C Plastic DIP N-18
PIN CONNECTIONS
18-Lead Hermetic DIP
18-Lead Plastic DIP
18-Lead SOIC
2
Package Type
JC
Units
JA
18-Lead Hermetic DIP (X)
18-Lead SOIC (S)
18-Lead Plastic DIP (P)
48
89
74
15
28
33
°C/W
°C/W
°C/W
V
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
COMP
LC
I
V
V
(–)
O
REF
NOTES
V–
(+)
REF
1Absolute maximum ratings apply to both DICE and packaged parts, unless
otherwise noted.
I
V+
O
DAC10
TOP VIEW
(Not to Scale)
2θJA is specified for worst case mounting conditions, i.e., θJA is specified for device
in socket for Cerdip packages.
B10 (LSB)
(MSB) B1
B2
B3
B4
B5
B9
B8
B7
B6
–4–
REV. D
Typical Performance Characteristics–DAC10
8.0
7.2
6.4
5.6
4.8
4.0
3.2
+28
T
= T
TO T
A
MIN MAX
+24
+20
+16
+12
+8
ALL BITS ON
SHADED AREA INDICATES
PERMISSABLE OUTPUT
VOLTAGE RANGE
I
0mA
OUT
FOR V– = –15V
I
I
= 2mA
V– = –15V, V– = –10V
REF
REF
I
Յ 2.0mA
REF
1.0mA
+4
FOR OTHER V– OR I
REF
SEE OUTPUT CURRENT
vs. OUTPUT VOLTAGE
CURVE
I
= 2mA
REF
= 1mA
2.4
1.6
0
2.0mA
I
OUT
–4
I
= 0.2mA
REF
–8
0.8
0
(0000000000)
(11111111111)
–12
0
–14 –10 –6
–2
2
6
10 14
18
–50
+50 +100 +150
OUTPUT VOLTAGE – Volts
TEMPERATURE – ؇C
Figure 1. True and Complementary
Output Operations
Figure 2. Output Current vs. Output
Voltage (Output Voltage Compliance)
Figure 3. Output Voltage Compliance
vs. Temperature
10
10
10
BITS MAY BE HIGH OR LOW
I–
V– = –15V
= 2.0mA
9
9
8
7
6
5
4
3
2
1
0
9
I–
I – WITH I
= 2mA
= 1mA
REF
REF
I
REF
8
7
8
7
6
5
4
6
I – WITH I
ALL BITS "HIGH" OR "LOW"
ALL BITS MAY BE "HIGH" OR "LOW"
5
4
3
I – WITH I
= 0.2mA
REF
3
2
I+
V+ = +15V
2
1
0
I+
I – WITH I
–12
= 0.2mA
–16
REF
1
0
0
2
4
6
8
10 12 14 16 18 20
V+, POSITIVE POWER SUPPLY – V
0
–4
–8
–20
–50
0
+50 +100 +150
DC
V–, NEGATIVE POWER SUPPLY – V
DC
TEMPERATURE – ؇C
Figure 4. Power Supply Current
vs. V+
Figure 5. Power Supply Current
vs. V–
Figure 6. Power Supply Current vs.
Temperature
BASIC CONNECTIONS
+V
REF
+V
R
1023
1024
REF
REF
I
=
؋
؋
2 FR
R
I
REF
REF
MSB
LSB
I
+ I = I FOR ALL
FR
O
O
I
IN
LOGIC STATES
B
B
B
B
B
B
B
B
B
B
9
1
2
3
4
5
6
7
8
10
16
17
V
IN
R
REF
5
6
7
8
9
10 11 12 13 14
R
IN
DAC10
(R16)
16
17
4
2
+V
I
REF
O
I
REF
DAC10
I
O
I
PEAK NEGATIVE SWING OF I
REF
IN
R17
3
18
15
1
R
REF
16
17
FOR FIXED REFERENCE,
TTL OPERATION,
TYPICAL VALUES ARE:
C
+V
C
R
R17
REF
REF
R17
(OPTIONAL)
DAC10
COMP
V
= +10.000V
REF
V
IN
R
= 5.000k⍀
0.1F
0.01F
REF
R15 = R
HIGH INPUT
IMPEDANCE
REF
= 0.01F
= 0V (GROUND)
V
C
V
V+
V–
LC
C
+V
MUST BE ABOVE PEAK POSITIVE SWING OF V
IN
REF
LC
Figure 7. Basic Positive Reference Operation
Figure 8. Accommodating Bipolar References
CAUTION
WARNING!
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
ESD SENSITIVE DEVICE
REV. D
–5–
DAC10
LOW T.C.
4.5k⍀
V
REF
+10V
R
REF
16
17
16
17
39k⍀
4
2
I
I
O
O
I
(+) 2mA
1V
REF
DAC10
DAC10
R17
10k⍀
POT
–V
REF
APPROXIMATELY
–V
R
5k⍀
REF
REF
NOTE: R
SETS I ; R17 IS FOR BIAS
FS
I
؋
2 REF
FS
CURRENT CANCELLATION
Figure 9. Basic Negative Reference Operation
Figure 10. Recommended Full-Scale Adjustment Circuit
B
B
B
B
B
B
B B B B
6 7 8 9 10
MSB
I
mA
I
mA
E
E
O
LSB
1
2
3
4
5
O
O
O
B
B
B
B
B
B
B
B
B
B
1
1
1
1
1
1
1
1
1
1
FULL RANGE
3.996
2.004
2.000
1.996
0.004
0.000
0.000
1.992
1.996
2.000
3.992
3.996
–4.995
–2.505
–2.500
–2.495
–0.005
0.000
–0.000
–2.490
–2.495
–2.500
–4.990
–4.995
1
2
3
4
5
6
7
8
9
10
E
O
1
1
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
1
0
1
1
0
HALF-SCALE +LSB
HALF-SCALE
1.25k⍀
4
I
I
O
O
I
=
16
REF
HALF-SCALE –LSB
HALF-SCALE +LSB
ZERO SCALE +LSB
DAC10
1.25k⍀
2.000mA
2
E
O
Figure 11. Basic Unipolar Negative Operation
B
B
B
B
B
B
B B B B
E
E
O
1
2
3
4
5
6 7 8 9 10
O
+5V
MSB
LSB
–4.990
–4.980
–0.010
0.000
+5.000
+4.990
+0.020
+0.010
0.000
POSITIVE FULL RANGE
1
1
1
0
0
1
0
1
1
0
0
1
0
1
1
1
1
1
1 1
B
B
B
B
B
B
B
B
B
B
1
2
3
4
5
6
7
8
9 10
POSITIVE FULL RANGE –LSB
1
1
1
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
0
1
0
1
1
2.5k⍀
2.5k⍀
ZERO-SCALE +LSB
ZERO-SCALE
E
E
O
O
4
2
I
I
O
I
=
16
REF (+)
DAC10
ZERO-SCALE –LSB
+0.010
+4.990
+5.000
2.000mA
O
–4.980
–4.990
NEGATIVE FULL-SCALE +LSB
NEGATIVE FULL-SCALE
0
0
0
0
0
0
0
0
0 0
Figure 12. Basic Bipolar Output Operation
5k⍀
+15V
2
MSB
LSB
2.5k⍀
B
B
B
B
B
B
B
B
B
B
1
2
3
4
5
6
7
8
9
10
B
B
B
B
B
B
B B B B
6 7 8 9 10
E
V
1
2
3
4
5
O
IN
+15V
–15V
5.000
k⍀
POSITIVE FULL RANGE
ZERO-SCALE
+4.990
0.00
1
1
0
0
0
1
0
0
0
1
1
0
0
0
1
0
0
0
1
0
0
0
1
1
0
0
0
1
6
4
2
I
V
O
O
1
0
0
0
0
0
0
0
0
0
1
0
E
DAC10
O
5k⍀
I
–4.990
–5.000
REF01
NEGATIVE FULL-SCALE +LSB
NEGATIVE FULL-SCALE
O
C
V
LC
C
GND
4
V+
V–
Figure 13. Offset Binary Operation
–6–
REV. D
DAC10
LOW-TO-HIGH SETTLING V = 16.500V ؎0.001V
L
HIGH-TO-LOW SETTLING V = 0.500V ؎0.001V
L
V
+15V
0.500V ؎0.001V
L
51⍀
0.1F
10F
0.1F
10F
0.01F
4.7F
IN5711
4k⍀
14
5
D.U.T.
3
4
2N918
15 16 18
17
1
2
175mV
2N918
V
O
0.01F
2k⍀
1F
1k⍀
499k⍀
1/4W, 5% CARBON
+15V
1M⍀
1F
1/4W, 5%
CARBON
–15V
–15V
–15V
2.5k⍀
+15V
1/2 LSB SETTLING = 7.8mV
0.01F
4.7F
0.01F
2
REF-01
4
2.5k⍀
10k⍀
6
5
–15V
NOTES:
1. CASE OF 2N918s MUST BE GROUNDED.
2. RESISTORS ARE 1/4W MF, 1% UNLESS OTHERWISE SPECIFIED.
3. USE FET PROBE (7A11 SCOPE PLUGIN).
Figure 14. Settling Time Measurement
R
+15V
V
L
= V +1.4V
TTL
TH
LC
V
= +1.4V
+15V CMOS
= +7.6V
TH
V
TH
9.1k⍀
I
I
4
2
O
O
DAC10
E
V
DAC10
OP01
O
LC
V
LC
1
0 TO +I
؋
R FR
L
6.2k⍀
0.1F
1023
=
1024
I
؋
2 ؋
I FR
REF
FOR COMPLEMENTARY OUTPUT (OPERATION AS A NEGATIVE
LOGIC DAC), CONNECT INVERTING INPUT OF OP AMP TO
I
(PIN 2); CONNECT I (PIN 4) TO GROUND.
O
O
ECL
Figure 15. Positive Low Impedance Output Operation
13k⍀
2N3904
"A"
2N3904
3k⍀
E
OP15
O
TO PIN 1
I
I
4
2
O
O
39k⍀
V
LC
DAC10
R
0 TO –I
؋
R L
FR
L
6.2k⍀
1023
=
1024
I
؋
2 ؋
I FR
REF
FOR COMPLEMENTARY OUTPUT (OPERATION AS A NEGATIVE
LOGIC DAC), CONNECT NOINVERTING INPUT OF OP AMP TO
–5.2V
I
PIN 2); CONNECT I (PIN 4) TO GROUND.
O
O
Figure 16. Negative Low Impedance Output Operation
Figure 17. Interfacing with Various Logic Families
–7–
REV. D
DAC10
APPLICATIONS
Multiplying Operation
The DAC10 provides excellent multiplying performance with an
extremely linear relationship between IFS and IREF over a range
of 4 mA to 4 µA. Monotonic operation is maintained over a
typical range of IREF from 100 µA to 2 mA.
+V
REF
OPTIONAL RESISTOR
FOR OFFSET INPUTS
R
REF
R
R
R
L
IN
16
4
2
Reference Amplifier Compensation for Multiplying Applications
AC reference applications will require the reference amplifier to
be compensated using a capacitor from Pin 18 to V–. The value
of this capacitor depends on the impedance presented to Pin 16
for R16 values of 1.0 kΩ, 2.5 kΩ and 5.0 kΩ, minimum values
of CC are 15 pF, 37 pF and 75 pF. Larger values of R16 require
proportionately increased values of CC for proper phase margin.
R
= 800⍀
EQ
DAC10
0V
L
17
R
P
TYPICAL VALUES:
= 1k⍀
R
IN
NO CAP
+V = 2V
IN
1
1
1
R
1
REF
+
+
R
=
EQ
R
R
IN
P
For fastest response to a pulse, low values of R16 enabling small
CC values should be used. If Pin 16 is driven by a high imped-
ance such as a transistor current source, none of the above val-
ues will suffice and the amplifier must be heavily compensated,
which will decrease overall bandwidth and slew rate. For R16 =
1 kΩ and CC = 15 pF, the reference amplifier slews at 4 mA/µs
enabling a transition from IREF = 0 to IREF = 2 mA in 500 ns.
Figure 18. Pulsed Reference Operation
Reference Amplifier Setup
The DAC10 is a multiplying D/A converter in which the output
current is the product of a digital number and the input refer-
ence current. The reference current may be fixed or may vary
from nearly zero to 2 mA. The full-scale output current is a
linear function of the reference current and is given by:
Operation with pulse inputs to the reference amplifier may be
accommodated by an alternate compensation scheme. This
technique provides lowest full-scale transition times. An internal
clamp allows quick recovery of the reference amplifier from a
cutoff (IREF = 0) condition. Full-scale transition (0 mA to 2 mA)
occurs in 120 ns when the equivalent impedance at Pin 16 is
200 Ω and CC = 0. This yields a reference slew rate of 16 mA/
µs, which is relatively independent of RIN and VIN values.
1023
1024
IFR
=
× 2 × IREF
where IREF equals current flowing into Pin 16.
In positive reference applications, an external positive reference
voltage forces current through R16 into the VREF (+) terminal
(Pin 16) of the reference amplifier. Alternatively, a negative
reference may be applied to VREF (–) at Pin 17; reference current
flows from ground through R16 into V(+) as in the positive
reference case. This negative reference connection has the ad-
vantage of a very high impedance presented at Pin 17. R17
(nominally equal to R16) is used to cancel bias current errors;
R17 may be eliminated with only a minor increase in error.
LOGIC INPUTS
The DAC10 design incorporates a unique logic input circuit
that enables direct interface to all popular logic families and
provides maximum noise immunity. This feature is made pos-
sible by the large input swing capability, 2 µA logic input current
and completely adjustable logic threshold voltage. For V– = –15 V,
the logic inputs may swing between –5 and +18 V. This enables
direct interface with +15 V CMOS logic, even when the DAC10
is powered from a +5 V supply. Minimum input logic swing and
Bipolar references may be accommodated by offsetting VREF or
Pin 17. The negative common-mode range of the reference
amplifier is given by: VCM– = V– plus (IREF × 2 kΩ) plus 2 V.
The positive common-mode range is V+ less 1.8 V.
minimum logic threshold voltage are given by: V– plus (lREF
×
2 kΩ) plus 3 V. The logic threshold may be adjusted over a wide
range by placing an appropriate voltage at the logic threshold
control Pin (Pin 1, VLC). The appropriate graph shows the
relationship between VLC and VTH over the temperature range,
with VTH nominally 1.4 V above VLC. For TTL interface, simply
ground Pin 1. When interfacing ECL, an IREF = 1 mA is recom-
mended. For interfacing other logic families, see Figure 17. For
general setup of the logic control circuit, it should be noted that
Pin 1 will sink 1.1 mA typical; external circuitry should be de-
signed to accommodate this current.
When a dc reference is used, a reference bypass capacitor is
recommended. A 5 V TTL logic supply is not recommended as
a reference. If a regulated power supply is used as a reference,
R16 should be split into two resistors with the junction bypassed
to ground with a 0.1 µF capacitor.
For most applications, the tight relationship between IREF and
I
FS will eliminate the need for trimming IREF. If required, full-
scale trimming may be accomplished by adjusting the value of
R16, or by using a potentiometer for R16. An improved method
of full-scale trimming that eliminates potentiometer TC effect is
shown in the Recommended Full-Scale Adjustment circuit.
Fastest settling times are obtained when Pin 1 sees a low imped-
ance. If Pin 1 is connected to a 1 kΩ divider, for example, it
should be bypassed to ground by a 0.01 µF capacitor.
The reference amplifier must be compensated by using a capaci-
tor from Pin 18 to V–. For fixed reference operation, a 0.01 µF
capacitor is recommended. For variable reference applications,
see section entitled Reference Amplifier Compensation for Mul-
tiplying Applications.
–8–
REV. D
DAC10
ANALOG OUTPUT CURRENTS
Both true and complemented output sink currents are provided
The temperature coefficient of the reference resistor, R14,
should match and track that of the output resistor for minimum
overall full-scale drift. Settling times of the DAC10 decrease
approximately 10% at –55°C; an increase of about 15% is typi-
cal at +125°C.
where
. Current appears at the “true” output
IO + IO = IFS
when a “1” is applied to each logic input. As the binary count
increases, the sink current at Pin 4 increases proportionally, in
the fashion of a “positive logic” D/A converter. When a “0” is
applied to any input bit, that current is turned off at Pin 4 and
turned on at Pin 2. A decreasing logic count increases IO as in
a negative or inverted logic D/A converter. Both outputs may be
used simultaneously. If one of the outputs is not required, it
must still be connected to ground or to a point capable of sourc-
ing IFS. DO NOT LEAVE AN UNUSED OUTPUT PIN OPEN.
SETTLING TIME
The DAC10 is capable of extremely fast settling times; typically
85 ns at IREF = 2 mA. Judicious circuit design and careful board
layout must be employed to obtain full performance potential
during testing and application. The logic switch design enables
propagation delays of only 35 ns for each of the 10 bits. Settling
time to within 1/2 LSB of the LSB is therefore 35 ns, with each
progressively larger bit taking successively longer. The MSB
settles in 85 ns, thus determining the overall settling time of
130 ns. Settling to 8-bit accuracy requires about 60 ns to 78 ns.
The output capacitance of the DAC10, including the package, is
approximately 18 pF; therefore, the output RC time constant
dominates settling time if RL > 500 Ω.
Both outputs have an extremely wide voltage compliance en-
abling fast direct current-to-voltage conversion through a resis-
tor tied to ground or other voltage source. Positive compliance
is 36 V above V– and is independent of the positive supply.
Negative compliance is +10 V above V–.
The dual outputs enable double the usual peak-to-peak load
swing when driving loads in quasi-differential fashion. This
feature is especially useful in cable driving, CRT deflection and
in other balanced applications such as driving center-tapped
coils and transformers.
Settling time and propagation delay are relatively insensitive to
logic input amplitude and rise and fall times, due to the high
gain of the logic switches. Settling time also remains essentially
constant for IREF values down to 1 mA, with gradual increases
for lower IREF values. The principal advantage of higher IREF
values lies in the ability to attain a given output level with lower
load resistors, thus reducing the output RC time constant.
POWER SUPPLIES
The DAC10 operates over a wide range of power supply volt-
ages from a total supply of 9 V to 36 V. When operating with V–
supplies of –10 V or less, IREF ≤ 1 mA is recommended. Low
reference current operation decreases power consumption and
increases negative compliance, reference amplifier negative
common-mode range, negative logic input range and negative
logic threshold range; consult the various figures for guidance.
For example, operation at –9 V with IREF = 2 mA is not recom-
mended because negative output compliance would be reduced
to near zero. Operation from lower supplies is possible, however
at least 8 V total must be applied to ensure turn-on of the inter-
nal bias network.
Measurement of settling time requires the ability to accurately
resolve ±2 µA; therefore, a 4 kΩ load is needed to provide ad-
equate drive for most oscilloscopes. The settling time fixture of
schematic titled “Settling Time Measurement” uses a cascode
design to permit driving a 4 kΩ load with less than 5 pF of para-
sitic capacitance at the measurement node. At IREF values of less
than 1 mA, excessive RC damping of the output is difficult to
prevent while maintaining adequate sensitivity. However, the
major carry from 0111111111 to 1000000000 provides an accu-
rate indicator of settling time. This code change does not re-
quire the normal 6.2 time constants to settle to within ±0.2% of
the final value, and thus settling times may be observed at lower
Symmetrical supplies are not required, as the DAC10 is quite
insensitive to variations in supply voltage. Battery operation is
feasible as no ground connection is required; however, an artifi-
cial ground may be used to ensure that logic swings, etc., remain
within acceptable limits.
values of IREF
.
DAC10 switching transients or “glitches” are very low and may
be further reduced by small capacitive loads at the output with a
minor sacrifice in settling time.
TEMPERATURE PERFORMANCE
Fastest operation can be obtained by using short leads, minimiz-
ing output capacitance and load resistor values, and by adequate
bypassing at the supply, reference and VLC terminals. Supplies
do not require large electrolytic bypass capacitors as the supply
current drain is independent of input logic states; 0.1 µF capaci-
tors at the supply pins provide full transient protection.
The nonlinearity and monotonicity specifications of the DAC10
are guaranteed to apply over the entire rated operating tempera-
ture range. Full-scale output current drift is tight, typically
+10 ppm/°C, with zero-scale output current and drift essentially
negligible compared to 1/2 LSB.
–9–
REV. D
DAC10
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
18-Lead Cerdip
(Q-18)
0.005 (0.13) MIN
0.098 (2.49) MAX
18
10
0.310 (7.87)
0.220 (5.59)
1
9
0.320 (8.13)
0.290 (7.37)
PIN 1
0.960 (24.38) MAX
0.060 (1.52)
0.015 (0.38)
0.200 (5.08)
MAX
0.150
(3.81)
MIN
0.200 (5.08)
0.125 (3.18)
0.015 (0.38)
0.008 (0.20)
0.023 (0.58)
0.014 (0.36)
SEATING
PLANE
0.100
(2.54)
BSC
0.070 (1.78)
0.030 (0.76)
15°
0°
18-Lead Plastic DIP
(N-18)
0.925 (23.49)
0.845 (21.47)
18
1
10
9
0.280 (7.11)
0.240 (6.10)
0.325 (8.25)
0.300 (7.62)
0.195 (4.95)
0.115 (2.93)
PIN 1
0.060 (1.52)
0.015 (0.38)
0.210
(5.33)
MAX
0.130
(3.30)
MIN
0.160 (4.06)
0.115 (2.93)
0.015 (0.381)
0.008 (0.204)
SEATING
PLANE
0.100
(2.54)
BSC
0.070 (1.77)
0.045 (1.15)
0.022 (0.558)
0.014 (0.356)
18-Lead Wide Body SOL
(R-18)
0.4625 (11.75)
0.4469 (11.35)
18
10
0.2992 (7.60)
0.2914 (7.40)
0.4193 (10.65)
0.3937 (10.00)
1
9
PIN 1
0.1043 (2.65)
0.0926 (2.35)
0.0291 (0.74)
x 45°
0.0098 (0.25)
0.0500 (1.27)
0.0157 (0.40)
8°
0°
0.0500
(1.27)
BSC
0.0192 (0.49)
0.0118 (0.30)
0.0040 (0.10)
SEATING
PLANE
0.0125 (0.32)
0.0091 (0.23)
0.0138 (0.35)
–10–
REV. D
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