DAC16 [ADI]
16-Bit High Speed Current-Output DAC; 16位高速电流输出DAC
| 型号： | DAC16 |
| 厂家： | 
ADI |
| 描述： | 16-Bit High Speed Current-Output DAC |
| 文件： | 总12页 (文件大小：193K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
16-Bit High Speed
Current-Output DAC
a
DAC16
FUNCTIONAL BLOCK DIAGRAM
FEATURES
؎1 LSB Differential Linearity (max)
Guaranteed Monotonic Over Temperature Range
؎2 LSB Integral Linearity (max)
500 ns Settling Time
I
REF
DAC16
BUFFER
C
COMP
REF GND
5 mA Full-Scale Output
TTL/CMOS Compatible
Low Power: 190 mW (typ)
Available in Die Form
V
CC
AGND
V
DAC
I
OUT
EE
DGND
DB0 (LSB)
DB15 (MSB)
APPLICATIONS
Communications
ATE
Data Acquisition Systems
High Resolution Displays
0.1
GENERAL DESCRIPTION
The DAC16 is a 16-bit high speed current-output digital-to-
analog converter with a settling time of 500 ns. A unique com-
bination of low distortion, high signal-to-noise ratio, and high
speed make the DAC16 ideally suited to performing waveform
synthesis and modulation in communications, instrumentation,
and ATE systems. Input reference current is buffered, with full-
scale output current of 5 mA. The 16-bit parallel digital input
bus is TTL/CMOS compatible. Operating from +5 V and
–15 V supplies, the DAC16 consumes 190 mW (typ) and is
available in a 24-lead epoxy DIP, epoxy surface-mount small
outline (SOL), and in die form.
V
= +5V
LOGIC
TURNING OFF
V
= 0V
LOGIC
TURNING ON
0.01
I
T
= 4mA
FS
= 25؇C
A
0.001
0
100
200
300
400
500
600
700
800
SETTLING TIME – ns
Figure 1. DAC16 Settling Time Accuracy vs. Percent of
Full Scale
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 1999
DAC16–SPECIFICATIONS
(@ VCC = +5.0 V, VEE = –15.0 V, IREF = 0.5 mA, CCOMP = 47 F, TA = Full Operating Tem-
perature Range unless otherwise noted. See Note 1 for supply variations.)
ELECTRICAL CHARACTERISTICS
Parameter
Conditions
Min
Typ
Max
Units
Integral Linearity “G”
Integral Linearity “G”
Differential Linearity “G”
Differential Linearity “G”
Integral Linearity “F”
Integral Linearity “F”
Differential Linearity “F”
Differential Linearity “F”
Zero Scale Error
INL
INL
DNL
DNL
INL
TA = +25°C
TA = +25°C
TA = +25°C
TA = +25°C
–2
–4
–1
–1
–4
–6
–1
–1.5
±1.2
±1.6
±0.5
±0.7
±1.4
±2
+2
+4
+1
+1.5
+4
+6
+1.5
+2
1
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
INL
DNL
DNL
ZSE
±0.5
±0.6
LSB
Zero Scale Drift
Gain Error
Gain Drift
TCZSE
GE
TCGE
0.025
5
ppm/°C
% FS
ppm/°C
±0.225
REFERENCE2
Reference Input Current
IREF
Note 2
350
2.8
625
5.0
µA
OUTPUT CHARACTERISTICS
Output Current
Output Capacitance
Settling Time
IOUT
COUT
tS
Note 2
mA
pF
ns
10
500
0.003% of Full Scale
LOGIC CHARACTERISTICS
Logic Input High Voltage
Logic Input Low Voltage
Logic Input Current
Logic Input Current
Logic Input Current
VINH
VINL
IINH
IINH
IINL
CIN
TA = +25°C
TA = +25°C
VIN = 5.0 V, DB0–DB10
VIN = 5.0 V, DB11–DB15
VIN = 0 V, DB0–DB15
2.4
V
V
µA
µA
µA
pF
0.8
7.5
100
1
Input Capacitance
8
SUPPLY CHARACTERISTICS
Power Supply Sensitivity
Positive Supply Current
Positive Supply Current
Negative Supply Current
Power Dissipation
PSS
ICC
ICC
IEE
PDISS
VCC = 4.5 V to 5.5 V, VEE = –13 V to –17 V
All Bits HIGH
All Bits LOW
20
22
7.5
10
260
ppm/V
mA
mA
mA
mW
15
6
7.5
188
NOTES
1All supplies can be varied ±5% and operation is guaranteed. Device is tested with nominal supplies.
2Operation is guaranteed over this reference range, but linearity is neither tested not guaranteed (see Figures 7 and 8).
Specifications subject to change without notice.
(@ V = +5.0 V, V = –15.0 V, IREF = 0.5 mA, CCOMP = 47 F, TA = +25؇C unless otherwise noted.)
WAFER TEST LIMITS
CC
EE
DAC16G
Limit
Parameter
Symbol
Conditions
Units
Integral Nonlinearity
Differential Nonlinearity
Zero Scale Error
INL
DNL
ZSE
GE
VINH
VINL
IIN
ICC
IEE
PDISS
±3
±1
±1
±12
2.4
0.8
75
20
10
250
LSB max
LSB max
LSB max
% FS max
V min
V max
µA max
mA max
mA max
mW max
Gain Error
Logic Input High Voltage
Logic Input Low Voltage
Logic Input Current
Positive Supply Current
Negative Supply Current
Power Dissipation
NOTE
Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed
for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing.
–2–
REV. B
DAC16
CAUTION
ABSOLUTE MAXIMUM RATINGS
1. Stresses above those listed under “Absolute Maximum Rat-
ings” may cause permanent damage to the device. This is a
stress rating only and functional operation at or above this
specification is not implied. Exposure to the above maximum
rating conditions for extended periods may affect device
reliability.
(TA = +25°C unless otherwise noted)
VCC to VEE . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +25.0 V
VCC to DGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +7.0 V
V
EE to AGND . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V, –18.0 V
DGND to AGND . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +0.3 V
REF GND to AGND . . . . . . . . . . . . . . . . . . . –0.3 V, +1.0 V
IREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 mA
Analog Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . 8 mA
Digital Input Voltage to DGND . . . . . . . . . . . . . . . . . . . ≤VCC
Operating Temperature Range
FP, FS . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
GS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
Dice Junction Temperature . . . . . . . . . . . . . . . . . . . . . +150°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . 1000 mW
Lead Temperature (Soldering, 60 sec) . . . . . . . . . . . . +300°C
2. Digital inputs and outputs are protected; however, perma-
nent damage may occur on unprotected units from high en-
ergy electrostatic fields. Keep units in conductive foam or
packaging at all times until ready to use. Use proper anti-
static handling procedures.
3. Remove power before inserting or removing units from their
sockets.
PIN CONFIGURATION
24-Lead DIP (P, S)
1
Package Type
θJA
θJC
Units
1
2
24
23
22
21
20
19
18
17
16
15
14
13
I
C
I
REF
COMP
24-Lead Plastic DIP (P)
24-Lead Plastic SOL (S)
62
70
32
22
°C/W
°C/W
DGND
OUT
3
V
AGND
CC
4
DB15 (MSB)
DB14
DB13
DB12
DB11
DB10
DB9
REF GND
NOTE
1θJA is specified for worst case mounting conditions, i.e., θJA is specified for
V
5
EE
DAC16
TOP VIEW
(Not to Scale)
device in socket.
6
DB0 (LSB)
DB1
7
DICE CHARACTERISTICS
8
DB2
9
DB3
C
V
DGND
I
I
OUT
AGND
COMP
CC
REF
10
11
12
DB4
DB5
DB8
REF GND
DB6
DB7
DB15 (MSB)
DB14
V
EE
DB0 (LSB)
PIN DESCRIPTION
Description
DB13
DB12
DB11
Pin
(P, S) Name
DB1
DB2
1
2
3
IREF
DGND
VCC
Reference Current Input
Digital Ground
+5 V Digital Supply
DB10
DB3
4–19 DB15–DB0 16-Bit Digital Input Bus. DB15 is the MSB.
20
21
22
23
24
VEE
–15 V Analog Supply
DB9 DB8 DB7 DB6 DB5 DB4
REF GND Reference Current Return
AGND
IOUT
Analog Ground/Output Reference
Current Output
Current Ladder Compensation
Die Size 0.129 x 0.153 inch, 19,737 sq. mils
(3.277 x 3.886 mm, 12.73 sq. mm)
The DAC16 Contains 330 Transistors.
Substrate is VEE Polarity.
CCOMP
ORDERING GUIDE
Model
Grade DNL (max)
Temperature Ranges
Package Descriptions
Package Options
DAC16GS
DAC16FP
DAC16FS
DAC16GBC
±1
±2
±2
±1
0°C to +70°C
–40°C to +85°C
–40°C to +85°C
+25°C
24-Lead SOL
24-Lead PDIP
24-Lead SOL
Die
R-24
N-24
R-24
REV. B
–3–
DAC16
+5V
minimizing the deleterious effects of digital feedthrough
while allowing the user to tailor the digital interface to
the speed requirements and bus configuration of the
application.
10k⍀
1
2
24
23
22
21
20
19
18
17
16
15
14
13
NC
3
Equivalent Circuit Analysis
4
An equivalent circuit for static operation of the DAC16 is
illustrated in Figure 4. IREF is the current applied to the
DAC16 and is set externally to the device by VREF and
5
–15V
6
7
RREF. The output capacitance of the DAC16 is approxi-
8
mately 10 pF and is code independent. Its output resis-
tance RO is code dependent and is given by:
9
10
11
12
1
1
DB9
DB10
X
=
+
+
+
RO 8 kΩ 288 kΩ 144 kΩ 72 kΩ
where
Figure 2. Burn-In Diagram
DB9 = State of Data Bit 9 = 0 or 1;
OPERATION
Novel DAC Architecture
DB10 = State of Data Bit 10 = 0 or 1; and
X = Decimal representation of the 5 MSBs (DB11–DB15)
The DAC16 was designed with a compound DAC architecture
to achieve high accuracy, excellent linearity, and low transition
errors. As shown in Figure 3, the DAC’s five most-significant
bits utilize 31 identical segmented current sources to obtain
optimal high speed settling at major code transitions. The lower
nine bits utilize an inverted R-2R ladder network which is laser-
trimmed to ensure excellent differential nonlinearity. The middle
two bits (DB9 and DB10) arc binary-weighted and scaled from
the MSB segments. Note that the flow of output current is into
the DAC16—there is no signal inversion. As shown, the switches
for each current source are essentially diodes. It is for this rea-
son that the output voltage compliance of the DAC16 is limited
to a few millivolts. The DAC16 was designed to operate with an
operational amplifier configured as an I–V converter; therefore,
the DAC16’s output must be connected to the sum node of an
operational amplifier for proper operation. Exceeding the output
voltage compliance of the DAC16 will introduce linearity errors.
The reference current buffer assures full accuracy and fast set-
tling by controlling the MSB reference node. The 16-bit paral-
lel digital input is TTL/CMOS compatible and unbuffered,
= 0 to 31.
I
OUT
65,535 Digital Code
65,536
I
C
O
R
DAC
O
I
= 8 • I
REF
OUT
R
C
= SEE TEXT
= 10pF
O
O
Figure 4. Equivalent Circuit for the DAC16
Table I provides the relationship between the input digital
code and the output resistance of the DAC16.
Table I. DAC16 Output Resistance vs. Digital Code
Hex Digital Code
Scale
Output Resistance
FFFF
BFFF
7FFF
3FFF
0
Zero
1/4
1/2
3/4
8 kΩ
4.2 kΩ
2.9 kΩ
2.2 kΩ
1.8 kΩ
Full – 1 LSB
I
OUT
DB0 – DB8
AGND
8k⍀
4k⍀
8k⍀
4k⍀
4k⍀
DB11 – DB15
DB10
SW10
DB9
SW9
4k⍀
4k⍀
DB0 – DB15
SWITCH DETAIL
18k⍀
SW
SW
SW
SW8
SW7
SW6
SW0
SW
+5V
I
REF
FROM
SWITCH
DECODER
62.5A 31.25A
31 CURRENT SOURCES
9 CURRENT SOURCES
125A EACH
15.63A EACH
C
COMP
Figure 3. DAC16 Architecture
–4–
REV. B
Typical Performance Characteristics–DAC16
Digital Input Considerations
This input capacitance can be used in conjunction with an ex-
The threshold of the DAC16’s digital input circuitry is set at
1.4 V, independent of supply voltage. Hence, the digital inputs
can interface with any type of 5 V logic. Illustrated in Figure 5 is
the equivalent circuit of the digital inputs. Note that the indi-
vidual input capacitance is approximately 7 pF.
ternal R-C circuit for digital signal deskewing, if required. In
applications where some of the DAC16’s digital inputs are
not used, the recommended procedure to turn off one or more
inputs is to connect each input line to +5 V as shown in
Figure 6.
+5V
+0.7V
+5V
R2
75k⍀
DAC16
DB0
Q1
DBX
Q2
Q3
R1
20k⍀
TO DAC
SWITCH
DB1
R3
28k⍀
–0.7V
–15V
Figure 6. Handling Unused DAC16 Digital Inputs
Figure 5. Equivalent Circuit of a DAC16 Digital Input
4
3
2.0
1.5
1.0
0.5
0
1.0
V
V
T
= +5V
= –15V
= +25؇C
V
V
T
= +5V
= –15V
= +25؇C
CC
EE
CC
EE
V
V
I
= +5V
= –15V
= 0.5mA
CC
EE
A
A
0.8
0.6
0.4
0.2
0
2
REF
1
+INL
–INL
+DNL
–DNL
0
–1
–2
–3
–4
–0.5
–1.0
–1.5
–2.0
0.2
0.3
0.4
0.5
0.6
0.7
0.2
0.3
0.4
0.5
0.6
0.7
–40 –20
0
20
40
60
80
REFERENCE CURRENT – mA
TEMPERATURE – ؇C
REFERENCE CURRENT – mA
Figure 7. Integral Nonlinearity vs. IREF
Figure 8. Differential Nonlinearity
vs. IREF
Figure 9. Zero Scale Output vs.
Temperature
15
4
1.5
V
V
I
= +5V
= –15V
= 0.5mA
V
V
I
= +5V
= –15V
= 0.5mA
CC
EE
CC
EE
10
5
1.0
0.5
+INL
REF
REF
2
+DNL
–INL
0
0
0
–5
–10
–15
–0.5
–1.0
–1.5
V
V
I
= +5V
= –15V
= 0.5mA
CC
EE
–2
–4
–DNL
20
REF
–40 –20
0
20
40
60
80
–40 –20
0
20
40
60
80
–40 –20
0
40
60
80
TEMPERATURE – ؇C
TEMPERATURE – ؇C
TEMPERATURE – ؇C
Figure 10. Gain Error vs.
Temperature
Figure 11. Integral Nonlinearity
vs. Temperature
Figure 12. Differential Nonlinearity
vs. Temperature
–5–
REV. B
DAC16–Typical Performance Characteristics
20
15
10
5
20
15
10
5
50
40
30
20
10
0
V
V
V
= +5V
= –15V
= +5V
V
V
T
= –15V
= +5V
= +25؇C
CC
EE
EE
CC
I
, LOGIC BITS = HIGH
CC
IN
A
DB0 – DB4
IEE , LOGIC BITS = LOW
IEE , LOGIC BITS = HIGH
I
, LOGIC BITS = LOW
CC
DB5 – DB15
0
0
–40 –20
0
20
40
60
80
0
1
2
3
4
5
–40 –20
0
20
40
60
80
TEMPERATURE – ؇C
TEMPERATURE – ؇C
LOGIC INPUT VOLTAGE – V
ALL DATA BITS
Figure 13. Supply Current vs.
Temperature
Figure 14. VCC Supply Current vs.
Logic Input Voltage, All Data Bits
Figure 15. Digital Input Current vs.
Temperature
6
1.5
1.0
130
WORST CASE + INL
5
V
T
= +5V, V = –15V
EE
V
T
= +5V, V = –15V
EE
CC
CC
= +25؇C, I
= 0.5mA
= +25؇C, I
= 0.5mA
A
REF
A
REF
120
110
0
4
WORST CASE
+ GAIN ERROR
WORST CASE + DNL
TYPICAL + DNL
3
TYPICAL + INL
0.5
2
1
0
TYPICAL
GAIN ERROR
TYPICAL – INL
0
–0.5
–1.0
–1.5
–10
–20
–30
–1
WORST CASE – INL
TYPICAL – DNL
–2
WORST CASE
– GAIN ERROR
V
T
= +5V, V = –15V
EE
CC
= +25؇C, I
WORST CASE – DNL
–3
–4
= 0.5mA
A
REF
0
200
400
600 800 1000 1200
0
200
400
600
800 1000 1200
0
200
400
600
800
1000 1200
BURN-IN TIME – Hours
BURN-IN TIME – Hours
BURN-IN TIME – Hours
Figure 18. Gain Error vs. Time
Accelerated by Burn-In
Figure 16. Differential Nonlinearity
vs. Time Accelerated by Burn-In
Figure 17. Integral Nonlinearity vs
Time Accelerated by Burn-In
The DAC16 includes two ground connections in order to mini-
mize system accuracy degradation arising from grounding er-
rors. The two ground pins are designated DGND (Pin 2) and
AGND (Pin 22). The DGND pin is the return for the digital
circuit sections of the DAC and serves as their input threshold
reference point. Thus, DGND should be connected to the same
ground as the circuitry that drives the digital inputs.
APPLICATIONS
Power Supplies, Bypassing, and Grounding
All precision converter products require careful application of
good grounding practices to maintain full-rated performance. As
is always the case with analog circuits operating in digital envi-
ronments, digital noise is prevalent; therefore, special care must
be taken to ensure that the DAC16’s inherent precision is main-
tained. This means that particularly good engineering judgment
should be exercised when addressing the power supply, ground-
ing, and bypassing issues using the DAC16.
Pin 22, AGND, serves as the reference point for the 9-bit
lower-order DAC as well as the common for the reference am-
plifier, REFGND (Pin 21). This pin should also serve as the
reference point for all analog circuitry associated with the
DAC16. Therefore, to minimize any errors, it is recommended
that AGND connection on the DAC16 be connected to a high
quality analog ground. If the system contains any analog signal
path carrying a significant amount of current, then that path
should have its own return connection to Pin 22.
The DAC16 was designed to operate from +5 V and –15 V
supplies. The +5 V supply primarily powers the digital portion
of the DAC16 and can consume 20 mA, maximum. Although
very little +5 V supply current is used by the reference amplifier,
large amounts of digital noise present on the +5 V supply can
introduce analog errors. It is, therefore, very important that the
+5 V supply be well filtered and regulated. The –15 V supply
provides most of the current for the reference amplifier and all
of the current for the internal DAC. Although the maximum
current in this supply is 10 mA, it must provide a low imped-
ance path for the DAC switch currents. Therefore, it too must
be well filtered and regulated.
It is often advisable to maintain separate analog and digital
grounds throughout a complete system, tying them common to
one place only. If the common tie point is remote and an acci-
dental disconnection of that one common tie point were to oc-
cur due to card removal with power on, a large differential
voltage between the two commons could develop. To protect
devices that interface to both digital and analog parts of the
–6–
REV. B
DAC16
system, such as the DAC16, it is recommended that common
ground tie points be provided at each such device. If only one
system ground can be connected directly to the DAC16, it is
recommended that the analog common be used. If the system’s
AGND has suitable low impedance, then the digital signal cur-
rents flowing in it should not seriously affect the ground noise.
The amount of digital noise introduced by connecting the two
grounds together at the device will not adversely affect system
performance due to loss of digital noise immunity.
+5V
10F
FB
0.1F
V
CC
DAC16
V
AGND
EE
0.1F
10F
Generous bypassing of the DAC’s supplies goes a long way in
reducing supply-line induced errors. Even with well-filtered,
well-regulated supplies, local bypassing consisting of 10 µF tan-
talum electrolytic shunted by a 0.1 µF ceramic is recommended.
The decoupling capacitors should be connected between the
DAC’s supply pins (Pin 3 for +5 V, Pin 20 for –15 V) and
the analog ground (Pin 22). Figure 19 shows how the DGND,
AGND, and bypass connections should be made to the DAC16.
FB
–15V
Figure 20. Using a Ferrite Bead as a High Frequency Filter
Reference Amplifier Considerations
The reference input current buffer is a high performance ampli-
fier optimized for high accuracy and linearity. The design of the
reference amplifier ensures fast settling times by tightly control-
ling the node common to all the current sources internal to the
DAC with an external compensation capacitor (CCOMP). Since
the primary design goal of the DAC16 is to achieve 16-bit per-
formance, proper operation of the reference amplifier requires a
+5V
DB0 – DB15
V
10F
CC
DAC16
DGND
I
0.1F
OUT
V
EE
AGND
0.1F
10F
47 µF tantalum electrolytic capacitor shunted by a 0.1 µF
ceramic capacitor, as shown in Figure 21. Increasing the capaci-
tance at this node above the recommended values does not fur-
ther reduce the analog transition current noise spikes at the
output of the reference amplifier. Reducing the value of com-
pensation, however, is not recommended as DAC linearity will
degrade as a result. In most systems, the VEE supply offers suffi-
ciently low impedance to maintain a quiet return point for the
reference amplifier. If this is not the case, the AGND point can
also be used for the compensation capacitor return, as shown in
Figure 21.
TO OTHER
ANALOG
TO
POWER
–15V
CIRCUITS GROUND
Figure 19. Recommended Grounding and Bypassing
Scheme for the DAC16
Using the Right Capacitors
Probably the most important external components associated
with high speed design are the capacitors used to bypass the
power supplies and to provide compensation. Both selection
and placement of these capacitors can be critical and, to a large
extent, dependent upon the specifics of the system configura-
tion. The dominant consideration in selection of bypass and
compensation capacitors for the DAC16 is minimization of se-
ries resistance and inductance. Many capacitors begin to look
inductive at 20 MHz and above—the very frequencies where re-
jection of interference is needed. Ceramic and film-type capaci-
tors generally feature lower series inductance than tantalum or
electrolytic types. A few general rules are of universal use when
approaching the issue of compensation or bypassing.
DAC16
C
COMP
I
OUT
V
EE
0.1F
AGND
47F
–15V
Figure 21a. Recommended Compensation Scheme to VEE
DAC16
C
COMP
I
OUT
0.1F
AGND
Bypass capacitors should be installed on the printed circuit
board with the shortest possible leads consistent with reliable
construction. This helps to minimize series inductance in the
leads. Chip capacitors are optimal in this respect. Where illus-
trated in the applications section, large tantalum electrolytic
capacitors are shunted by low self-inductance ceramic capaci-
tors. This technique reduces the self-resonance of the electrolytic
while shifting the resonant frequency of the ceramics out-of-band.
47F
Figure 21b. Recommended Compensation Scheme to AGND
In applications where 16-bit multiplying performance is
required, the DAC16 might appear to be a viable solution.
However, the compensation capacitor network would have to
be removed in these applications. The DAC16’s reference am-
plifier was specifically designed for low frequency operation,
with a compensation capacitor network. In fact, this network
serves not only as a charge reservoir for the DAC’s internal
current sources but also as a wideband noise filter for the
Some series inductance between the DAC supply pins and the
power supply plane often helps to filter out high frequency
power supply noise. This inductance can be generated using a
small ferrite bead as shown in Figure 20.
REV. B
–7–
DAC16
reference amplifier. Completely removing the compensation
network would introduce large linearity errors, reference amplifier
instability, wideband reference amplifier noise, and poor settling
time.
thermally well-matched. Thin-film resistor networks work well
here. In this circuit, the parallel combination of R1 and R2
forms a 3 Hz low-pass filter with C1. The only noise source that
remains is the thermal noise of R2 which can be a significantly
lower noise generator than the voltage reference.
Because the DAC exhibits an internal current scaling factor of
eight times (8×), the reference amplifier requires only 500 µA
input current from the user-supplied precision reference for a
4 mA full-scale output current. In applications that do not re-
quire such high output currents, good accuracy can be achieved
with input reference currents in the range of 350 µA ≤ IREF
≤ 625 µA. The best signal-to-noise ratios, of course, will be
achieved with a 625 µA reference current which yields a maxi-
mum 5 mA output current. Figure 22 illustrates how to form
the reference input current with a REF02 and a 10 kΩ precision
resistor.
Input Coding
The unipolar digital input coding of the DAC16 employs nega-
tive logic to control the output current; that is, an all zero input
code (0000H) yields an output current 1 LSB below full scale.
Conversely, an all 1s input code (FFFFH) yields a zero analog
current output. An expression for the DAC16’s transfer equa-
tion can be expressed by:
65,535 – Digital Code
IOUT = 8 × IREF
×
65,536
Table II provides the relationship between the digital input
codes and the output current of the DAC16.
+15V
R
REF
10k⍀
Table II. Unipolar Code Table
I
REF
DAC16
0.1F
REF02
I
OUT
Digital Input
Word (Hex)
DAC16 Output
Current IOUT
REF GND
Comment
V
R
REF
REF
8 × (216 – 1)/216 × IREF
8 × (215 + 1)/216 × IREF
8 × (215/216) × IREF
8 × (215– 1)/216 × IREF
0
Full Scale
Midscale + 1 LSB
Midscale
Midscale – 1 LSB
Zero Scale
I
=
REF
0000
7FFE
7FFF
8000
FFFF
Figure 22. Generating the DAC16’s Reference Input Current
Reducing Voltage Reference Noise
In data converters of 16-bit and greater resolution, noise is of
critical importance. Surprisingly, the integrated voltage refer-
ence circuit used may contribute the dominant share of a
system’s noise floor, thereby degrading system dynamic range
and signal-to-noise ratio. To maximize system dynamic range
and SNR, all external noise contributions should be effectively
much less than 1/2 LSB. For example, in a 5 V DAC16 applica-
tion, one LSB is equivalent to 76 µV. This means that the total
wideband noise contribution due to a voltage reference and all
other sources should be less than 38 µV rms. These noise levels
are not easy targets to hit with standard off-the-shelf reference
devices. For example, commercially available references might
exhibit 5 µV rms noise from 0.1 Hz to 10 Hz: but, over a 100 kHz
bandwidth, its 300 µV rms of noise can easily swamp out a
16-bit system. Such noisy behavior can degrade a DAC’s effec-
tive resolution by increasing its differential nonlinearity which,
in turn, can lead to nonmonotonic behavior or analog errors.
Since the DAC16 exhibits a small output voltage compliance on
the order of a few millivolts, a high accuracy operational ampli-
fier must be used to convert the DAC’s output current to a volt-
age. Refer to the section on selecting operation amplifiers for the
DAC16. The circuit shown in Figure 24 illustrates a unipolar
output configuration. In symbolic form, the transfer equation
for this circuit can be expressed by:
65,535 – Digital Code
VO = R3 × 8 × IREF
65,536
In this example, the reference input current was set to 500 µA
which produces a full-scale output current of 4 mA – 1 LSB.
The DAC’s output current was scaled by R3, a 1.25 kΩ resistor,
to produce a 5 V full-scale output voltage. Bear in mind that to
ensure the highest possible accuracy, matched thin-film resistor
networks are almost a necessity, not an option. The resistors
used in the circuit must have close tolerance and tight thermal
tracking. Table III illustrates the relationship between the input
digital code and the circuit’s output voltage for the component
values shown.
The easiest way to reduce noise in the reference circuit is to
band-limit its noise before feeding it to the converter. In the
case of the DAC16, the reference is not a voltage, but a current.
Illustrated in Figure 23 is a simple way of hand-limiting
+15V
Table III. Unipolar Output Voltage vs. Digital Input Code
R1
R2
5k⍀
5k⍀
Digital Input Word
(Hex)
Decimal Number in
in DAC Decoder
Analog Output
Voltage (V)
I
DAC16
REF
0.1F
REF02
C1
22F
REF GND
AGND
0000
7FFE
7FFF
8000
FFFF
65,535
32,769
32,768
32,767
0
4.999924
2.500076
2.500000
2.499924
0
Figure 23. Filtering a Reference’s Wideband Noise
voltage reference noise by splitting RREF into two equal resistors
and bypassing the common node with a capacitor. To minimize
thermally induced errors, R1 and R2 must be electrically and
–8–
REV. B
DAC16
DIGITAL INPUT WORD
DB0 – DB7
DB8 – DB15
R3
2.5k⍀
(5k⍀،2)
CLK
74AC11377
8
74AC11377
EN
+15V
0.1F
+15V
8
10F
R1
5k⍀
R2
5k⍀
0.1F
I
I
OUT
REF02
REF
V
OP97A
OUT
22F
DAC16
REF GND
0V TO +10V FS
0.1F
C
AGND
COMP
10F
100nF
CERAMIC
0.1F
47F
DIGITAL +5V
PIN 3, DAC16
+5V
10F
–15V
–15V
0.1F
RESISTORS:
10F
CADDOCK T912–5K–010–02 (OR EQUIVALENT)
5k⍀, 0.01%, TC TRACK = 2 ppm/؇C
–15V
Figure 24. Unipolar Circuit Configuration
+5V
REF
DIGITAL INPUT WORD
DB8 – DB15
DB0 – DB7
R3
2.5k⍀
(5k⍀،2)
R4
2.5k⍀
(5k⍀،2)
CLK
74AC11377
74AC11377
EN
+15V
0.1F
+15
V
8
8
+5V
REF
10F
R1
5k⍀
R2
5k⍀
0.1F
I
I
OUT
REF02
REF
OP97A
V
OUT
؎5V FS
22F
DAC16
REF GND
0.1F
C
AGND
COMP
10F
100nF
CERAMIC
0.1F
47F
DIGITAL +5V
PIN 3, DAC16
+5V
10F
–15V
–15V
RESISTORS:
0.1F
10F
CADDOCK T912–5K–010–02 (OR EQUIVALENT)
5k⍀ , 0.01%, TC TRACK = 2 ppm/؇C
–15V
Figure 25. Bipolar Circuit Configuration
Bipolar Configuration
Table IV. Bipolar Output Operation vs. Digital Input Code
For applications that require a bipolar output voltage, the circuit
in Figure 24 can be modified slightly by adding a resistor from
the reference to the inverting sum node of the output amplifier
to level shift the output signal. The transfer equation for the cir-
cuit now becomes:
Digital Input
Word (Hex)
Decimal Number in
DAC Decoder
Analog Output
Voltage (V)
0000
7FFE
7FFF
8000
FFFF
65,535
32,769
32,768
32,767
0
4.999848
152E-6
0
–152E-6
–5.00000
65,535 – Digital Code
R4
R3
VO = R4 × 8 × IREF
–VREF ×
65,536
The circuit has the form shown in Figure 25, and Table IV pro-
vides the relationship between the digital input code and the
circuit’s output voltage for the component values shown.
REV. B
–9–
DAC16
DIGITAL INPUT WORD
DB8 – DB15
DB0 – DB7
R3
1.25k⍀
(2.49k⍀،2)
CLK
74AC11377
74AC11377
EN
+15V
0.1F
+15V
8
8
10F
R1
5k⍀
R2
5k⍀
0.1F
I
I
REF02
REF
OUT
V
OP27A
OUT
22F
DAC16
REF GND
0V TO +5V FS
0.1F
C
AGND
COMP
10F
C2
0.1F
C1
47F
100nF
CERAMIC
10F
–15V
DIGITAL +5V
PIN 3, DAC16
+5V
–15V
RESISTORS:
0.1F
CADDOCK T912–5K–010–02 (OR EQUIVALENT)
5k⍀, 0.01%, TC TRACK = 2 ppm/؇C
10F
–15V
Figure 26. DAC16 Noise Measurement Test Circuit
DAC16 Noise Performance
at different speeds, then the DAC output current will momen-
tarily take on some incorrect value. This effect is particularly
troublesome at the “carry points,” where the DAC output is to
change by only one LSB, but several of the larger current
sources must be switched to realize this change. Data skew can
allow the DAC output to move a substantial amount towards
full scale or zero (depending upon the direction of the skew)
when only a small transition is desired. The glitch-sensitive user
should be equally diligent about minimizing the data skew at the
DAC16’s inputs, particularly the five most significant bits. This
can be achieved by using the proper logic family and gate to
drive the DAC inputs, and keeping the interconnect lines be-
tween the latches and the DAC inputs as short and as well
matched as possible. Logic families that were empirically deter-
mined to operate well with the DAC16 are devices from the
74AC11xxx and 74ACT11xxx advanced CMOS logic families.
These devices have been purposely designed with improved lay-
out and tailored rise times for minimizing ground bounce and
digital feedthrough.
The novel architecture employed in the DAC16 yields very low
wideband noise. Figure 26 illustrates the circuit configuration
for evaluating the DAC16’s noise performance. An OP27 is
used as the DAC16’s output I–V converter which is configured
to produce a 5 V full-scale output voltage. The output of the
OP27 was then capacitively coupled to an OP37 stage config-
ured in a gain of 101. Note that the techniques for reducing
wideband noise of the voltage reference and the DAC’s internal
reference amplifier were used. As a result of these techniques,
the DAC16 exhibited a full-scale output noise spectral density
of 31 pA/√Hz at 1 kHz.
Digital Feedthrough and Data Skew
The DAC16 features a compound DAC architecture where the
5 most significant bits utilize 31 identical, segmented current
sources to obtain optimal high speed settling at major code tran-
sitions. Although every effort has been made to equalize the
speeds at which the DAC switches operate, there exists finite
skew in the MSB DAC switches.
Deglitching
As with any converter product, a high speed digital-to-analog
converter is forced to exist on the frontier between the noisy en-
vironment of high speed digital logic and the sensitive analog
domain. The problems of this interlace are particularly acute
when demands of high speed (greater than 10 MHz switching
times) and high precision are combined. No amount of design
effort can perfectly isolate the analog portions of a DAC from
the spectral components of a digital input signal with a 2 ns rise
time. Inevitably, once this digital signal is brought onto the chip,
some of its higher frequency components will find their way to
the sensitive analog nodes, producing a digital feedthrough
glitch. To minimize the exposure to this effect, the DAC16 was
designed to omit intentionally the on-board latches that are usu-
ally included in many slower DACs. This not only reduces the
overall level of digital activity on chip, it also avoids bringing a
latch clock pulse onto the IC, whose opposite edge inevitably
produces a substantial glitch, even when the DAC is not sup-
posed to be changing codes.
The output glitch of the DAC16 at the major carry (7FFEH to
7FFFH) is a not-insignificant 360 pA-sec, manifested as a
momentary output transition to the negative rail for approxi-
mately 200 ns. Due to the inherent low-pass or time-sampled
nature of many systems, this behavior in the DAC16 is not
noticeable and does not detract from overall performance. Some
applications however may prove so sensitive to glitch impulse
that reduction by an order of magnitude or more is required. In
order to realize low glitch impulses, some sort of sample-and-
hold amplifier-based deglitching scheme must be used.
There are high speed SHAs available with specifications suffi-
cient to deglitch the DAC16; however, most are hybrid in topol-
ogy at costs which can be prohibitive. A high performance, low
cost alternative shown in Figure 27 is a discrete SHA utilizing a
high speed monolithic op amp and high speed DMOS FET
switches.
This SHA circuit uses the inverting integrator structure. A
300 MHz gain-bandwidth product op amp, the AD841, is the
heart of this fast SHA. The time constant formed by the 200 Ω
resistor and the 100 pF capacitor determines the acquisition
time and also hand limits the output signal to eliminate slew-
induced distortion.
The DAC16 uses each digital input line to switch each current
segment in the DAC between the output diode-connected
transistor and the logic control transistor. If the input bits are
not changed simultaneously, or if the different DAC bits switch
–10–
REV. B
DAC16
200⍀
200⍀
INPUT
+15V
13
M1
12
M2
14
11
IN4735
16
9
100pF
360⍀
360⍀
+5V
MC10124
8
5
6
3
AD841
M3
Q1
Q2
OUTPUT
T/H
169⍀
–5V
249⍀
169⍀
–5V
249⍀
–15V
20k⍀
75⍀
510⍀
–15V
500pF
–5V
4
1
TO PIN 2
SD5000
M4
Q1, Q2 = MPS571
M1 – M4 = SD5000
0.39F
1.6k⍀
Figure 27. A High Performance Deglitching Circuit
A discrete drive circuit is used to achieve the best performance
from the SD5000 quad DMOS switch. This switch-driving cell
is composed of MPS571 RF NPN transistors and an MC10124
TTL-to-ECL translator. Using this technique provides both
high speed and highly symmetrical drive signals for the SD5000
switches. The switches arc arranged in a single-pole, double-
throw (SPDT) configuration. The 500 pF “flyback” capacitor is
switched to the op amp summing junction during the hold mode
to keep switching transients from feeding to the output. This ca-
pacitor is grounded during sample mode to minimize its effect
on acquisition time.
In high speed applications where resolution is more important
than absolute accuracy, operational amplifiers such as the
AD843 offer the requisite settling time. Although these amplifi-
ers are not specified for 16-bit performance, their settling times
are two to three times faster than the DAC16 and will introduce
negligible error to the overall circuit’s settling time. It is possible
to estimate the 16-bit settling time of an operational amplifier if
its 12-bit settling time is known. Assuming that the op amp can
be modeled by a single-pole response, then the ratio of the op
amp’s 16-bit settling time to its 12-bit settling can be expressed
as:
Careful circuit layout of the high speed SHA section is almost as
important as the design itself. Double-sided printed circuit
board, a compact layout, and short critical signal paths all ensure
best performance.
ts(16
ts(12
−
−
bit)
bit)
= 1. 33
Since many operational amplifier data sheets provide charts
illustrating 0.01% settling time versus output voltage step size,
all that is required to estimate an op amp’s 16-bit settling time is
to multiply the 12-bit settling time for the required full-scale
voltage by 1.33. The circuit’s overall settling time can then be
approximated by the root-sum-square method:
Op Amp Selection
When selecting the amplifier to be used for the DAC16’s I–V
converter, there are two main application areas; those requiring
high accuracy, and those seeking high speed. In high accuracy
applications, three parameters are of prime importance: (1)
input offset voltage. VOS; (2) input bias current, –IB; and (3) off-
set voltage drift, TCVOS. In these applications where 16-bit
performance must be maintained with an external reference
at +5 V, an op amp’s input offset voltage must be less than 15 µV
(≈0.1 LSB) with a bias current less than 6 nA. The op amp
must also exhibit high open-loop gain to keep the offset voltage
below this limit over the specified full-scale output range. Thus,
for a maximum output of 5 V, the op amp’s open loop gain
must be greater than 1300 V/mV.
tS = (tDAC )2 +(tOA
2
)
where
t
t
DAC = DAC16’s specified full-scale settling time
OA = Op amp full-scale settling time
As a design aid, Table VI illustrates a high speed operational
amplifier selector guide for devices compatible with the DAC16
for high speed applications. All these devices exhibit the requi-
site settling time, input offset voltage, and input bias current
consistent with maximum performance.
For low frequency, high accuracy applications, Table IV lists
selected compatible operational amplifiers available from Analog
Devices. These operational amplifiers satisfy all the above
requirements and in most all cases will not require offset voltage
nulling.
Table VI. High Speed Operational Amplifiers for the DAC16
Model tS to %
VOS
TCVOS
IB
AVOL
Table V. Precision Operational Amplifier the DAC16
OP467 200 ns –0.01 0.5 mV 3.5 µV/°C 0.5 µA
AD817 70 ns –0.01 2 mV 10 µV/°C 6.6 µA
AD829 90 ns –0.1 0.5 mV 0.3 µV/°C 7 µA
20 V/mV
6 V/mV
100 V/mV
45 V/mV
Model
VOS
TCVOS
IB
AVOL
OP177
OP77
OP27
OP97
10 µV
25 µV
25 µV
25 µV
0.3 µV/°C
0.6 µV/°C
0.3 µV/°C
2 µV/°C
2 nA
12000 V/mV
2000 V/mV
1500 V/mV
2000 V/mV
AD841 110 ns –0.01 1 mV
AD843 135 ns –0.01 1 mV
35 µV/°C 5 µA
12 µV/°C 0.001 µA 25 V/mV
2.8 nA
80 nA
0.15 nA
AD845 350 ns –0.01 0.25 mV 5 µV/°C 0.001 µA 500 V/mV
AD847 120 ns –0.01 1 mV 15 µV/°C 5 µA 5.5 V/mV
REV. B
–11–
DAC16
In using high speed op amps, the output capacitance of the
DAC16 appears across the inputs of the op amp where it and the
op amp’s input capacitance will set an additional pole in the op
amp’s loop gain response. The pole is formed with the feedback
resistance and the output resistance of the DAC. This additional
pole may adversely affect the transient response of the circuit
due to the added phase shift. Placing a small capacitor across the
feedback resistance, as shown in Figure 28, compensates for the
additional pole. The value of the capacitor can be determined by
setting RFBCFB = RO (CO + CIN) and should be adjusted for opti-
mum transient response.
The choice of amplifier depends entirely on the required system
accuracy, the required temperature range, and the operating
frequency.
C
FB
DAC16
R
FB
I
R
C
DAC
O
O
C
IN
V
OUT
Figure 28. Compensating for the Feedback Pole
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
24-Lead Epoxy DIP (P)
(N-24)
24-Lead Epoxy SOL (S)
(R-24)
1.275 (32.30)
1.125 (28.60)
0.6141 (15.60)
0.5985 (15.20)
24
13
12
0.280 (7.11)
0.240 (6.10)
24
13
12
1
0.325 (8.25)
0.300 (7.62)
0.2992 (7.60)
0.2914 (7.40)
PIN 1
0.060 (1.52)
0.015 (0.38)
0.4193 (10.65)
0.3937 (10.00)
0.210
(5.33)
MAX
0.195 (4.95)
0.115 (2.93)
1
0.150
(3.81)
MIN
0.200 (5.05)
0.125 (3.18)
0.015 (0.381)
0.008 (0.204)
PIN 1
0.1043 (2.65)
0.0926 (2.35)
0.0291 (0.74)
0.0098 (0.25)
0.100
(2.54)
BSC
0.022 (0.558)
0.014 (0.356)
0.070 (1.77) SEATING
؋
45؇ PLANE
0.045 (1.15)
8؇
0؇
0.0500
(1.27)
BSC
SEATING
PLANE
0.0192 (0.49)
0.0138 (0.35)
0.0118 (0.30)
0.0040 (0.10)
0.0500 (1.27)
0.0157 (0.40)
0.0125 (0.32)
0.0091 (0.23)
–12–
REV. B
相关型号：
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