DAC312ER [ADI]
12-Bit High Speed Multiplying D/A Converter; 12位高速乘法D / A转换器
| 型号： | DAC312ER |
| 厂家： | 
ADI |
| 描述： | 12-Bit High Speed Multiplying D/A Converter |
| 文件： | 总14页 (文件大小：271K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
12-Bit High Speed Multiplying
D/A Converter
a
DAC312
FEATURES
P IN CO NNECTIO NS
Differential Nonlinearity: ؎1/ 2 LSB
Nonlinearity: 0.05%
Fast Settling Tim e: 250 ns
20-P in H er m etic D IP (R-Suffix),
20-P in P lastic D IP (P -Suffix),
20-P in SO L (S-Suffix)
High Com pliance: –5 V to +10 V
Differential Outputs: 0 to 4 m A
Guaranteed Monotonicity: 12 Bits
Low Full-Scale Tem pco: 10 ppm / ؇C
Circuit Interface to TTL, CMOS, ECL, PMOS/ NMOS
Low Pow er Consum ption: 225 m W
Industry Standard AM6012 Pinout
Available In Die Form
GENERAL D ESCRIP TIO N
T he DAC312 series of 12-bit multiplying digital-to-analog con-
verters provide high speed with guaranteed performance to
0.012% differential nonlinearity over the full commercial oper-
ating temperature range.
High compliance and low drift characteristics (as low as
10 ppm/°C) are also features of the DAC312 along with an ex-
cellent power supply rejection ratio of ±.001% FS/%∆V. Oper-
ating over a power supply range of +5/–11 V to ±18 V the
device consumes 225 mW at the lower supply voltages with an
absolute maximum dissipation of 375 mW at the higher supply
levels.
T he DAC312 combines a 9-bit master D/A converter with a
3-bit (MSBs) segment generator to form an accurate 12-bit D/A
converter at low cost. T his technique guarantees a very uniform
step size (up to ±1/2 LSB from the ideal), monotonicity to
12-bits and integral nonlinearity to 0.05% at its differential cur-
rent outputs. In order to provide the same performance with a
12-bit R-2R ladder design, an integral nonlinearity over tem-
perature of 1/2 LSB (0.012%) would be required.
With their guaranteed specifications, single chip reliability and
low cost, the DAC312 device makes excellent building blocks
for A/D converters, data acquisition systems, video display driv-
ers, programmable test equipment and other applications where
low power consumption and complete input/output versatility
are required.
T he 250 ns settling time with low glitch energy and low power
consumption are achieved by careful attention to the circuit de-
sign and stringent process controls. Direct interface with all
popular logic families is achieved through the logic threshold
terminal.
FUNCTIO NAL BLO CK D IAGRAM
REV. C
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
© Analog Devices, Inc., 1996
One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.
Tel: 617/ 329-4700
Fax: 617/ 326-8703
DAC312–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
(@ V = ؎15 V, IREF = 1.0 mA, 0؇C ≤ T ≤ +70؇C for DAC312E and –40؇C ≤ T ≤ +85؇C
for DAC312F, DAC312H, unless otherwise noted. Output characteristics refer
to both IOUT and IOUT.)
S
A
A
D AC312E
Typ
D AC312F
Min Typ
D AC312H
Min Typ
P aram eter
Sym bol
Conditions
Min
Max
Max
Max
Units
Resolution
Monotonicity
12
12
12
12
12
12
Bits
Bits
Differential Nonlinearity
DNL
INL
Deviation from Ideal
Step Size2
Deviation from Ideal
Straight Line1
±0.0125
±0.5
±0.05
±0.0250
±1
±0.05
±0.0250 %FS
±1
LSB
%FS
Nonlinearity
±0.05
Full-Scale Current
Full-Scale T empco
IFS
VREF = 10 V
R14 = R15 = 10 kΩ2
3.967 3.999
±5
4.031
±20
±0.002
3.935 3.999
±10
4.063
±40
±0.004
3.935 3.999
±80
4.063
mA
ppm/°C
%FS/°C
T CIFS
±0.005
±0.001
±0.008
Output Voltage Compliance
VOC
DNL Specification Guaran-
teed over Compliance Range –5
| IFS| –| IFS
+10
±1
0.10
–5
+10
±2
0.10
–5
+10
±2
0.10
V
µA
µA
Full-Scale Symmetry
Zero-Scale Current
Settling T ime
IFSS
IZS
tS
|
±0.4
±0.4
±0.4
T o ±1/2 LSB, All Bits
Switched ON or OFF1
All Bits Switched 50% Point
Logic Swing to 50% Point
Output1
250
25
25
500
50
50
250
25
25
500
50
50
250
25
25
500
50
50
ns
ns
ns
Propagation Delay–All Bits
tPLH
tPHL
Output Resistance
Output Capacitance
Logic Input
RO
COUT
>10
20
>10
20
>10
20
MΩ
pF
Levels “0”
Levels “1”
VIL
VIH
IIN
VIS
I15
VLC = GND
VLC = GND
VIN = –5 to +18 V
0.8
0.8
0.8
V
V
µA
V
µA
2
2
2
Logic Input Current
Logic Input Swing
Reference Bias Current
Reference Input
Slew Rate
40
+18
–2
40
+18
–2
40
+18
–2
–5
0
–5
0
–5
0
–0.5
8
–0.5
8
–0.5
8
dl/dt
PSSIFS+
R14(eq) = 800 Ω, CC = 0 pF1
V+ = +13.5 V to +16.5 V,
V– = –15 V
V– = –13.5 V to –16.5 V,
V+ = +15 V
4
4
4
mA/µs
Power Supply Sensitivity
±0.0005 ±0.001
±0.0005 ±0.001
±0.0005 ±0.001 %FS/%∆V
±0.00025 ±0.001 %FS/%∆V
PSSIFS–
±0.00025 ±0.001
±0.00025 ±0.001
Power Supply Range
Power Supply Current
V+
V–
I+
I–
I+
I–
VOUT = 0 V
VOUT = 0 V
4.5
–18
18
–10.8
7
–18
7
–18
305
375
4.5
–18
18
–10.8
7
–18
7
–18
305
375
4.5
–18
18
–10.8
7
–18
7
–18
305
375
V
V
V+ = +5 V, V– = –15 V
V+ = +15 V, V– = –15 V
V+ = +5 V, V– = –15 V
V+ = +15 V, V– = –15 V
V+ = +5 V, V– = –15 V
V+ = +15 V, V– = –15 V
3.3
–13.9
3.9
–13.9
225
267
3.3
–13.9
3.9
–13.9
225
267
3.3
–13 9
3.9
–13.9
225
267
mA
mA
mA
mA
mW
mW
Power Dissipation
Pd
TYPICAL ELECTRICAL CHARACTERISTICS @ 25؇C; V = ؎15 V, and IREF = 1.0 mA, unless otherwise noted. Output
S
characteristics refer to both IOUT and IOUT.
D AC312N
Typical
D AC312G
Typical
P aram eter
Sym bol
Conditions
Units
Reference Input
Slew Rate
dl/dt
8
8
mA/µs
Propagation Delay
Settling T ime
tPLH, tPHL
tS
Any Bit
25
25
ns
T o ±1/2 LSB, All
Bits Switched ON
or OFF.
250
250
ns
Full-Scale
T CIFS
±10
±10
ppm/°C
–2–
REV. C
DAC312
ELECTRICAL CHARACTERISTICS @ V = ؎15 V, IREF = 1.0 mA, 0؇C ≤ T ≤ 70؇C for DAC312E and –40؇C ≤ T ≤ +85؇C for
S
A
A
DAC312F, DAC312H, unless otherwise noted. Output characteristics refer to both IOUT and IOUT. Continued
D AC312E
Typ
D AC312F
Min Typ
D AC312H
Min Typ
P aram eter
Sym bol
Conditions
Min
Max
Max
Max
Units
Logic Input
Levels “0”
VIL
VIH
IIN
VLC = GND
0.8
0.8
0.8
V
Logic Input
Levels “1”
VLC = GND
2
2
2
V
Logic Input
Current
VIN = –5 V to +18 V
40
40
40
µA
V
Logic Input
Swing
VIS
I15
–5
+18
–2
–5
+18
–2
–5
+18
–2
Reference Bias
Current
0
4
–0.5
8
0
4
–0.5
8
0
4
–0.5
8
µA
Reference Input dl/dt
Slew Rate
R14(eq) = 800 Ω
CC = 0 pF (Note 1)
mA/µs
V+ = +13.5 V to +16.5 V,
V– = –15 V
V– = –13.5 V to –16.5 V,
V+ = +15 V
±0.0005 ±0.001
±0.00025 ±0.001
±0.0005 ±0.001
±0.00025 ±0.001
±0.0005 ±0.001 %FS/%∆V
±0.00025 ±0.001 %FS/%∆V
Power Supply
Sensitivity
PSSIFS+
PSSIFS–
Power Supply
Range
V+
V–
4.5
–18
18
–10.8
4.5
–18
18
–10.8
4.5
–18
18
–10.8
VOUT = 0 V
V
I+
I–
I+
I–
3.3
–13.9
3.9
7
–18
7
3.3
–13.9
3.9
7
–18
7
3.3
–13.9
3.9
7
–18
7
Power Supply
Current
V+ = +5 V, V– = –15 V
V+ = +15 V, V– = –15 V
mA
mW
–13.9
–18
–13.9
–18
–13.9
–18
Power
Dissipation
V+ = +5 V, V– = –15 V
V+ = +15 V, V– = –15 V
225
267
305
375
225
267
305
375
225
267
305
375
Pd
NOT ES
1Guaranteed by design.
2T A = +25°C for DAC312H grade only.
Specifications subject to change without notice.
REV. C
–3–
DAC312
WAFER TEST LIMITS
@ V = ؎15 V, IREF = 1.0 mA, T = 25؇C, unless otherwise noted. Output characteristics refer to both IOUT and IOUT.
S
A
D AC312N
Lim it
D AC312G
Lim it
P aram eter
Sym bol
Conditions
Units
Resolution
12
12
Bits min
Bits min
%FS max
Monotonicity
Nonlinearity
12
12
±0.05
±0.05
Output Voltage
Compliance
Full-Scale Current
Change <1/2 LSB
+10
–5
+10
–5
V max
V min
Voc
Full-Scale
Current
VREF = 10.000 V
R14, R15 = 10.000 kΩ
4.031
3.967
4.063
3.935
mA max
mA min
Full-Scale Symmetry
Zero-Scale Current
IFSS
IZS
±1
±2
µA max
µA max
0.1
0.1
Differential
Nonlinearity
DNL
Deviation from
Ideal Step Size
±0.012
±1/2
±0.025
±1
%FS max
Bits (LSB) max
Logic Input Levels “0”
Logic Input Levels “1”
Logic Input Swing
VIL
VIH
VIS
VLC = GND
VLC = GND
0.8
2
0.8
2
V max
V min
+18
–5
+18
–5
V max
V min
Reference Bias
Current
I15
–2
–2
µA max
Power Supply
Sensitivity
PSSIFS+
PSSIFS–
V+ = +13.5 V to +16.5 V, V– = –15 V
V– = –13.5 V to –16.5 V, V+ = +15 V
±0.001
±0.001
±0.001
±0.001
%/%max
mA max
mW max
Power Supply
Current
I+
I–
VS = +15 V
IREF ≤ 1.0 mA
7
–18
7
–18
Power
Dissipation
VS = +15 V
IREF ≤ 1.0 mA
PD
375
375
NOT E
Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed
for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing.
D ICE CH ARACTERISTICS
1. B1 (MSB)
2. B2
3. B3
4. B4
5. B5
11. B11
12. B12 (LSB)
13. VLC/AGND
14. VREF(+)
15. VREF(–)
16. COMP
17. V–
6. B6
7. B7
8. B8
18. IO
9. B9
19. IO
10. B10
20. V+
DIE SIZE 0.141 × 0.096 inch, 13,536 sq. m ils (3.58 × 2.44 m m , 8.74 sq. m m )
REV. C
–4–
DAC312
ABSO LUTE MAXIMUM RATINGS1
Operating T emperature
O RD ERING GUID E 1
DAC312E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
DAC312F, DAC312H . . . . . . . . . . . . . . . . . . –40°C to +85°C
Junction T emperature . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Storage T emperature (T j) . . . . . . . . . . . . . . . . . –65°C to +125°C
Lead T emperature (Soldering, 60 sec) . . . . . . . . . . . . . . . . 300°C
Power Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±18 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –5 V to +18 V
Analog Current Outputs . . . . . . . . . . . . . . . . . . . . –8 V to +12 V
Reference Inputs V14, V15 . . . . . . . . . . . . . . . . . . . . . . . V– to V+
Reference Input Differential Voltage (V14, V15) . . . . . . . . . . ±18 V
Tem perature
Range
P ackage
D escription
P ackage
O ption
Model
D NL
DAC312ER2
DAC312FR
DAC312BR/883 ±1 LSB
DAC312HP
DAC312HS
±1/2 LSB 0°C to +70°C
±1 LSB –40°C to +85°C
Cerdip-20
Cerdip-20
Q-20
Q-20
Q-20
–55°C to +125°C Cerdip-20
–40°C to +85°C
–40°C to +85°C
±1 LSB
±1 LSB
Plastic DIP-20 N-20
SOL-20
R-20
NOT ES
1Burn-in is available on commercial and industrial temperature range parts in
cerdip, plastic DIP, and T O-can packages.
Reference Input Current (I14
)
. . . . . . . . . . . . . . . . . . . . . 1.25 mA
2For devices processed in total compliance to MIL-ST D-883, add/883 after part
number. Consult factory for 883 data sheet.
2
P ackage Type
Units
JA
JC
20-Pin Hermetic DIP (R)
20-Pin Plastic DIP (P)
20-Pin SOL (S)
76
69
88
11
27
25
°C/W
°C/W
°C/W
NOT ES
1Absolute maximum ratings apply to both DICE and packaged parts, unless
otherwise noted.
2θJA is specified for worst case mounting conditions, i.e., θJA is specified for device
in socket for cerdip and P-DIP packages; θJA is specified for device soldered to
printed circuit board for SOL package.
CAUTIO N
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the DAC312 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. T herefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. C
–5–
DAC312
TYP ICAL P ERFO RMANCE CH ARACTERISTICS
Output Current vs. Output Voltage
(Output Voltage Com pliance)
Reference Am plifier Com m on-Mode
Range
Output Com pliance vs. Tem perature
Power Supply Current vs. Power
Supply Voltage
Power Supply Current vs.
Tem perature
True and Com plem entary Output
Operation
Reference Am plifier Sm all-Signal
Frequency Response
Reference Am plifier Large-Signal
Frequency Response
Gain Accuracy vs. Reference Current
REV. C
–6–
DAC312
BASIC CO NNECTIO NS
Positive Low Im pedance Output Operation
Negative Low Im pedance Output Operation
Basic Negative Reference Operation
Accom m odating Bipolar References
Recom m ended Full-Scale Adjustm ent Circuit
Pulsed Reference Operation
Basic Positive Reference Operation
REV. C
–7–
DAC312
BASIC CO NNECTIO NS
Interfacing with Various Logic Fam ilies
Bipolar Offset (True Zero)
MSB
LSB IO
IO
Code Form at
O utput Scale
B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 (m A) (m A) VO UT
Offset Binary;
T rue Zero Output.
Positive Full-Scale
Positive Full-Scale –LSB
+LSB
Zero-Scale
–LSB
1
1
1
1
0
0
0
1
1
0
0
1
0
0
1
1
0
0
1
0
0
1
1
0
0
1
0
0
1
1
0
0
1
0
0
1
1
0
0
1
0
0
1
1
0
0
1
0
0
1
1
0
0
1
0
0
1
1
0
0
1
0
0
1
1
0
0
1
0
0
1
1
0
0
1
0
0
1
0
1
0
1
1
0
3.999 0.000 9.9951
3.998 0.001 9.9902
2.001 1.998 0.0049
2.000 1.999 0.000
1.999 2.000 –0.0049
0.001 3.998 –9.9951
0.000 3.999 –10.000
Negative Full-Scale +LSB
Negative Full-Scale
2s Complement;
Positive Full-Scale
Positive Full-Scale –LSB
+1 LSB
Zero-Scale
–1 LSB
0
0
0
0
1
1
1
1
1
0
0
1
0
0
1
1
0
0
1
0
0
1
1
0
0
1
0
0
1
1
0
0
1
0
0
1
1
0
0
1
0
0
1
1
0
0
1
0
0
1
1
0
0
1
0
0
1
1
0
0
1
0
0
1
1
0
0
1
0
0
1
1
0
0
1
0
0
1
0
1
0
1
1
0
3.999 0.000 9.9951
3.998 0.001 9.9902
2.001 1.998 0.0049
2.000 1.999 0.000
1.999 2.000 –0.0049
0.001 3.998 –9.9951
0.000 3.999 –10.000
T rue Zero Output
MSB Complemented
(Need Inverter at B1).
Negative Full-Scale +LSB
Negative Full-Scale
REV. C
–8–
DAC312
BASIC CO NNECTIO NS
Basic Unipolar Operation
MSB
LSB IO
IO
Code Form at
O utput Scale
B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 (m A) (m A) VO UT
Straight Binary;
Unipolar with T rue
Input Code, T rue
Zero Output.
Positive Full-Scale
Positive Full-Scale –LSB
LSB
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
3.999 0.000 9.9976
3.998 0.001 9.9951
0.001 3.998 0.0024
0.000 3.999 0.0000
Zero-Scale
Complementary Binary; Positive Full-Scale
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0.000 3.999 9.9976
0.001 3.998 9.9951
3.998 0.001 0.0024
3.999 0.000 0.0000
Unipolar with
Positive full-Scale –LSB
Complementary Input
LSB
Code, True Zero Output. Zero-Scale
Sym m etrical Offset Operation
MSB
LSB IO
IO
Code Form at
O utput Scale
Positive Full-Scale
B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 (m A) (m A) VO UT
Straight Offset Binary;
Symmetrical about Zero, Positive Full-Scale –LSB
No T rue Zero Output.
1
1
1
0
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
0
0
1
1
0
3.999 0.00
3.998 0.001
2.000 1.999
1.999 2.000
0.001 3.998
0.000 3.999
9.9976
9.9927
0.0024
–0.0024
–9.9927
–9.9976
(+) Zero-Scale
(–) Zero-Scale
Negative Full-Scale –LSB
Negative Full-Scale
1s Complement;
Symmetrical about Zero, Positive Full-Scale –LSB
No T rue Zero Output.
MSB Complemented
(Need Inverter at B1).
Positive Full-Scale
0
0
0
1
1
1
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
0
0
1
1
0
3.999 0.000
3.998 0.001
2.000 1.999
1.999 2.000
0.001 3.998
0.000 3.999
9.9976
9.9927
0.0024
–0.0024
–9.9927
–9.9976
(+) Zero-Scale
(–) Zero-Scale
Negative Full-Scale –LSB
Negative Full-Scale
REV. C
–9–
DAC312
AP P LICATIO NS INFO RMATIO N
REFERENCE AMP LIFIER SETUP
REFERENCE AMP LIFIER CO MP ENSATIO N FO R
MULTIP LYING AP P LICATIO NS
T he DAC312 is a multiplying D/A converter in which the out-
put current is the product of a digital number and the input ref-
erence current. T he reference current may be fixed or may vary
from nearly zero to +1.0 mA. T he full range output current is a
linear function of the reference current and is given by:
AC reference applications will require the reference amplifier to
be compensated using a capacitor from pin 16 to V–. T he value
of this capacitor depends on the impedance presented to pin 14
for R14 values of 1.0 Ω, 2.5 Ω and 5.0 kΩ, minimum values of
CC are 5 pF, 10 pF, and 25 pF. Larger values of R14 require
proportionately increased values of CC for proper phase margin.
4095
IFR
=
× 4 × (IREF) = 3.999 IREF,
For fastest response to a pulse, low values of R14 enabling small
CC values should be used. If pin 14 is driven by a high imped-
ance such as a transistor current source, none of the above val-
ues will suffice and the amplifier must be heavily compensated
which will decrease overall bandwidth and slew rate. For R14 =
1 kΩ and CC = 5 pF, the reference amplifier slews at 4 mA/µs
enabling a transition from IREF = 0 to IREF = 1 mA in 250 ns.
4096
where IREF = I14
In positive reference applications, an external positive reference
voltage forces current through R14 into the VREF(+) terminal
(pin 14) of the reference amplifier. Alternatively, a negative ref-
erence may be applied to VREF(–) at pin 15. Reference current
flows from ground through R14 into VREF(+) as in the positive
reference case. T his negative reference connection has the ad-
vantage of a very high impedance presented at pin 15. T he volt-
age at pin 14 is equal to and tracks the voltage at pin 15 due to
the high gain of the internal reference amplifier. R15 (nominally
equal to R14) is used to cancel bias current errors.
Operation with pulse inputs to the reference amplifier may be
accommodated by an alternate compensation scheme. T his
technique provides lowest full-scale transition times. An internal
clamp allows quick recovery of the reference amplifier from a
cutoff (IREF = 0) condition. Full-scale transition (0 mA to 1 mA)
occurs in 62.5 ns when the equivalent impedance at pin 14 is
800 Ω and CC = 0. T his yields a reference slew rate of 8 mA/µs
which is relatively independent of RIN and VIN values.
Bipolar references may be accommodated by offsetting VREF or
pin 15. T he negative common-mode range of the reference am-
plifier is given by: VCM– = V– plus (IREF × 3 kΩ) plus 1.23 V.
T he positive common-mode range is V+ less 1.8 V.
LO GIC INP UTS
T he DAC312 design incorporates a unique logic input circuit
which enables direct interface to all popular logic families and
provides maximum noise immunity. T his feature is made pos-
sible by the large input swing capability, 40 µA logic input cur-
rent, and completely adjustable logic threshold voltage. For V–
= –15 V, the logic inputs may swing between –5 V and +10 V.
T his enables direct interface with +15 V CMOS logic, even
when the DAC312 is powered from a +5 V supply. Minimum
input logic swing and minimum logic threshold voltage are given
by: V– plus (IREF × 3 kΩ) plus 1.8 V. T he logic threshold may
be adjusted over a wide range by placing an appropriate voltage
at the logic threshold control pin (pin 13, VLC). T he appropriate
graph shows the relationship between VLC and VT H over the
temperature range, with VT H nominally 1.4 above VLC. For
T T L interface, simply ground pin 13. When interfacing ECL,
an IREF ≤ 1 mA is recommended. For interfacing other logic
families, see block titled “Interfacing With Various Logic Fami-
lies”. For general setup of the logic control circuit, it should be
noted that pin 13 will sink 7 mA typical; external circuitry
should be designed to accommodate this current.
When a dc reference is used, a reference bypass capacitor is rec-
ommended. A 5.0 V T T L logic supply is not recommended as a
reference. If a regulated power supply is used as a reference,
R14 should be split into two resistors with the junction bypassed
to ground with a 0.1 µF capacitor.
For most applications the tight relationship between IREF and IFS
will eliminate the need for trimming IREF. If required, full scale
trimming may be accomplished by adjusting the value of R14,
or by using a potentiometer for R14. An improved method of
full-scale trimming which eliminates potentiometer T .C. effects
is shown in the Recommended Full-Scale Adjustment circuit.
T he reference amplifier must be compensated by using a capaci-
tor from pin 16 to V–. For fixed reference operation, a 0.01 µF
capacitor is recommended. For variable reference applications,
see section entitled “Reference Amplifier Compensation for
Multiplying Applications.”
MULTIP LYING O P ERATIO N
T he DAC312 provides excellent multiplying performance with
an extremely linear relationship between IFS and IREF over a
range of 1 mA to 1 µA. Monotonic operation is maintained over
a typical range of IREF from 100 µA to 1.0 mA. Although some
degradation of gain accuracy will be realized at reduced values
of IREF. (See Gain Accuracy vs. Reference Current).
REV. C
–10–
DAC312
ANALO G O UTP UT CURRENTS
full-scale drift. Settling times of the DAC312 decrease approxi-
mately 10% at –55°C; at +125°C an increase of about 15% is
typical.
Both true and complemented output sink currents are provided
where IO + IO = IFR. Current appears at the true output when a
“1” is applied to each logic input. As the binary count increases,
the sink current at pin 18 increases proportionally, in the fash-
ion of a “positive logic” D/A converter. When a “0” is applied to
any input bit, that current is turned off at pin 18 and turned on
at pin 19. A decreasing logic count increases IO as in a negative
or inverted logic D/A converter. Both outputs may be used si-
multaneously. If one of the outputs is not required it must still
be connected to ground or to a point capable of sourcing IFR; do
not leave an unused output pin open.
SETTLING TIME
T he DAC312 is capable of extremely fast settling times; typi-
cally 250 ns at IREF = 1.0 mA. Judicious circuit design and care-
ful board layout must be employed to obtain full performance
potential during testing and application. T he logic switch design
enables propagation delays of only 25 ns for each of the 12 bits.
Settling time to within 1/2 LSB of the LSB is therefore 25 ns,
with each progressively larger bit taking successively longer. T he
MSB settles in 250 ns, thus determining the overall settling time
of 250 ns. Settling to 10-bit accuracy requires about 90 ns to
130 ns. T he output capacitance of the DAC312 including the
package is approximately 20 pF; therefore, the output RC time
constant dominates settling time if RL > 500 Ω.
Both outputs have an extremely wide voltage compliance en-
abling fast direct current-to-voltage conversion through a resis-
tor tied to ground or other voltage source. Positive compliance
is 25 V above V– and is independent of the positive supply.
Negative compliance is +10 V above V–.
Settling time and propagation delay are relatively insensitive to
logic input amplitude and rise and fall times, due to the high
gain of the logic switches. Settling time also remains essentially
constant for IREF values down to 0.5 mA, with gradual increases
for lower IREF values lies in the ability to attain a given output
level with lower load resistors, thus reducing the output RC
time constant.
T he dual outputs enable double the usual peak-to-peak load
swing when driving loads in quasi-differential fashion. T his fea-
ture is especially useful in cable driving, CRT deflection and in
other balanced applications such as driving center-tapped coils
and transformers.
P O WER SUP P LIES
T he DAC312 operates over a wide range of power supply volt-
ages from a total supply of 20 V to 36 V. When operating with
V– supplies of –10 V or less, IREF ≤ 1 mA is recommended. Low
reference current operation decreases power consumption and
increases negative compliance, reference amplifier negative
common-mode range, negative logic input range, and negative
logic threshold range; consult the various figures for guidance.
For example, operation at –9 V with IREF = 1 mA is not recom-
mended because negative output compliance would be reduced
to near zero. Operation from lower supplies is possible, however
at least 8 V total must be applied to insure turn-on of the inter-
nal bias network.
Measurement of the settling time requires the ability to accu-
rately resolve ±1/2 LSB of current, which is ±500 nA for 4 mA
FSR. In order to assure the measurement is of the actual settling
time and not the RC time of the output network, the resistive
termination on the output of the DAC must be 500 Ω or less.
T his does, however, place certain limitations on the testing ap-
paratus. At IREF values of less than 0.5 mA, it is difficult to pre-
vent RC damping of the output and maintain adequate
sensitivity. Because the DAC312 has 8 equal current sources for
the 3 most significant bits, the major carry occurs at the code
change of 000111111111 to 111000000000. T he worst case set-
tling time occurs at the zero to full-scale transition and it re-
quires 9.2 time constants for the DAC output to settle to within
±1/2 LSB (0.0125%) of its final value.
Symmetrical supplies are not required, as the DAC312 is quite
insensitive to variations in supply voltage. Battery operation is
feasible as no ground connection is required; however, an artifi-
cial ground may be used to insure logic swings, etc. remain be-
tween acceptable limits.
T he DAC312 switching transients or “glitches” are on the order
of 500 mV-ns. T his is most evident when switching through the
major carry and may be further reduced by adding small capaci-
tive loads at the output with a minor sacrifice in transition speeds.
TEMP ERATURE P ERFO RMANCE
Fastest operation can be obtained by using short leads, minimiz-
ing output capacitance and load resistor values, and by adequate
bypassing at the supply, reference, and VLC terminals. Supplies
do not require large electrolytic bypass capacitors as the supply
current drain is independent of input logic states; 0.1 µF capaci-
tors at the supply pins provide full transient protection.
T he nonlinearity and monotonicity specifications of the
DAC312 are guaranteed to apply over the entire rated operating
temperature range. Full-scale output current drift is tight, typi-
cally ±10 ppm/°C, with zero-scale output current and drift es-
sentially negligible compared to 1/2 LSB.
T he temperature coefficient of the reference resistor R14 should
match and track that of the output resistor for minimum overall
REV. C
–11–
DAC312
One of the characteristics of an R-2R DAC in standard form is
that any transition which causes a zero LSB change (i.e., the
same output for two different codes) will exhibit the same out-
put each time that transition occurs. T he same holds true for
transitions causing a 2 LSB change. T hese two problem transi-
tions are allowable for the standard definition of monotonicity
and also allow the device to be specified very tightly for INL.
T he major problem arising from this error type is in A/D con-
verter implementations. Inputs producing the same output are
now represented by ambiguous output codes for an identical in-
put. Also, 2 LSB gaps can cause large errors at those input lev-
els (assuming 1/2 LSB quantizing levels). It can be seen from
the two figures that the DNL specified D/A converter will yield
much finer grained data than the INL specified part, thus im-
proving the ability of the A/D to resolve changes in the analog
input.
D IFFERENTIAL VS. INTEGRAL NO NLINEARITY
Integral nonlinearity, for the purposes of the discussion, refers
to the “straightness”of the line drawn through the individual re-
sponse points of a data converter. Differential nonlinearity, on
the other hand, refers to the deviation of the spacing of the adja-
cent points from a 1 LSB ideal spacing. Both may be expressed
as either a percentage of full-scale output or as fractional LSBs
or both. T he following figures define the manner in which these
parameters are specified. T he left figure shows a portion of the
transfer curve of a DAC with 1/2 LSB INL and the (implied)
DNL spec of 1 LSB. Below this is a graphic representation of
the way this would appear on a CRT , for example, if the D/A
converter output were to be applied to the Y input of a CRT as
shown in the application schematic titled “CRT Display Drive.”
On the right is a portion of the transfer curve of a DAC speci-
fied for 2 LSB INL with 1/2 LSB DNL specified and the
graphic display below it.
D IFFERENTIAL LINEARITY CO MP ARISO N
D/A Converter with ±1/2 LSB INL, ±1 LSB DNL
D/A Converter with ±2 LSB INL, ±1/2 LSB DNL
Video Deflection by DACs
Video Deflection by DACs
ENLARGED “POSITIONAL” OUTPUTS
ENLARGED “POSITIONAL” OUTPUTS
REV. C
–12–
DAC312
D ESCRIP TIO N O F O P ERATIO N
T he DAC312 is divided into two major sections, an 8 segment
generator and a 9-bit master/slave D/A converter. In operation
the device performs as follows (see Simplified Schematic).
T he three most significant bits (MSBs) are inputs to a 3-to-8
line decoder. T he selected resistor (R5 in the figure) is con-
nected to the master/slave 9-bit D/A converter. All lower order
resistors (R1 through R4) are summed into the IO line, while all
higher order resistors (R6 through R8) are summed into the IO
line. T he R5 current supplies 512 steps of current (0 mA to
0.499 mA for a 1 mA reference current) which are also summed
into the IO or IO lines depending on the bits selected. In the fig-
ure, the code selected is: 100 110000000. T herefore, 2 mA (4 ×
0.5 mA/segment) +0.375 mA (from master/slave D/A converter)
are summed into IO giving an IO of 2.375 mA. IO has a current
of 1.625 mA with this code. As the three MSB’s are increment-
ed, each successively higher code adds 0.5 mA to IO and sub-
tracts 0.5 mA from IO, with the selected resistor feeding its
current to the master/slave D/A converter; thus each increment
of the 3 MSBs allows the current in the 9-bit D/A converter to
be added to a pedestal consisting of the sum of all lower order
currents from the segment generator. T his configuration guar-
antees monotonicity.
Expanded Transfer Characteristic Segm ent (001 010 011)
Sim plified Schem atic
REV. C
–13–
12-Bit Fast A/D Converter
O utline D im ensions
D imension shown in inches and (mm).
20-Lead P lastic D IP (N-20)
20-Lead Cerdip (Q-20)
20-Lead Wide Body SO L (R-20)
–14–
相关型号：
DAC312HS-REEL
IC PARALLEL, WORD INPUT LOADING, 0.25 us SETTLING TIME, 12-BIT DAC, PDSO20, SOIC-20, Digital to Analog Converter
ADI
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